diff --git a/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py b/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py index 7812d20..eef8d96 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py @@ -42,7 +42,7 @@ '*': { "count":3, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py b/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py index 95ca6cd..8467fb9 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py @@ -41,7 +41,7 @@ '*': { "count":1, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py b/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py index fca749f..7dd0def 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py @@ -41,7 +41,7 @@ '*': { "count":3, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/TEST_APPS/testcases/nanostack_mac_tester/send_data.py b/TEST_APPS/testcases/nanostack_mac_tester/send_data.py index 0d3bd45..95e5fea 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/send_data.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/send_data.py @@ -41,7 +41,7 @@ '*': { "count":2, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py b/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py index 8fce107..f884818 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py @@ -41,7 +41,7 @@ '*': { "count":3, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py b/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py index 7553ca5..74427ca 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py @@ -41,7 +41,7 @@ '*': { "count":2, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c index 7d658ef..064fb28 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c @@ -115,9 +115,6 @@ xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000); gXcvrDeassertCS_d(); -#if !defined(TARGET_KW24D) - MCR20Drv_RST_B_Deassert(); -#endif RF_IRQ_Init(); RF_IRQ_Disable(); mPhyIrqDisableCnt = 1; @@ -640,7 +637,6 @@ void ) { -#if !defined(TARGET_KW24D) volatile uint32_t delay = 1000; //assert RST_B MCR20Drv_RST_B_Assert(); @@ -649,7 +645,6 @@ //deassert RST_B MCR20Drv_RST_B_Deassert(); -#endif } /*--------------------------------------------------------------------------- diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp b/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp index 2f70302..755d2fb 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp @@ -61,11 +61,8 @@ #define gCcaCCA_MODE1_c 1 #define gXcvrRunState_d gXcvrPwrAutodoze_c -#if !defined(TARGET_KW24D) #define gXcvrLowPowerState_d gXcvrPwrHibernate_c -#else #define gXcvrLowPowerState_d gXcvrPwrAutodoze_c -#endif namespace { @@ -504,9 +501,7 @@ /* Disable Tristate on MISO for SPI reads */ MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, 0x02); /* Set XCVR clock output settings */ -#if !defined(TARGET_KW24D) MCR20Drv_Set_CLK_OUT_Freq(gMCR20_ClkOutFreq_d); -#endif /* Set default XCVR power state */ rf_set_power_state(gXcvrRunState_d); @@ -1758,7 +1753,7 @@ irq_thread = NULL; } -#if MBED_CONF_MCR20A_PROVIDE_DEFAULT || TARGET_KW24D +#if MBED_CONF_MCR20A_PROVIDE_DEFAULT NanostackRfPhy &NanostackRfPhy::get_default_instance() { diff --git a/features/nanostack/mbed-mesh-api/mbed_lib.json b/features/nanostack/mbed-mesh-api/mbed_lib.json index 05b47a6..165d57a 100644 --- a/features/nanostack/mbed-mesh-api/mbed_lib.json +++ b/features/nanostack/mbed-mesh-api/mbed_lib.json @@ -193,10 +193,6 @@ } }, "target_overrides": { - "KW24D": { - "mbed-mesh-api.use-malloc-for-heap": true, - "mbed-mesh-api.heap-size": 14000 - }, "NCS36510": { "mbed-mesh-api.heap-size": 14000 }, diff --git a/features/nanostack/sal-stack-nanostack/mbed_lib.json b/features/nanostack/sal-stack-nanostack/mbed_lib.json index 6640b5e..1ea4926 100644 --- a/features/nanostack/sal-stack-nanostack/mbed_lib.json +++ b/features/nanostack/sal-stack-nanostack/mbed_lib.json @@ -9,9 +9,6 @@ }, "macros": ["NS_USE_EXTERNAL_MBED_TLS"], "target_overrides": { - "KW24D": { - "nanostack.configuration": "lowpan_router" - }, "NCS36510": { "nanostack.configuration": "lowpan_router" }, diff --git a/features/netsocket/mbed_lib.json b/features/netsocket/mbed_lib.json index 1d05e38..ca24434 100644 --- a/features/netsocket/mbed_lib.json +++ b/features/netsocket/mbed_lib.json @@ -76,9 +76,6 @@ } }, "target_overrides": { - "KW24D": { - "nsapi.default-mesh-type": "LOWPAN" - }, "NCS36510": { "nsapi.default-mesh-type": "LOWPAN" }, diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PeripheralNames.h deleted file mode 100644 index ddda19b..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PeripheralNames.h +++ /dev/null @@ -1,110 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - GPIO_X = 0, // dummy peripheral used instead of GPIO_A..GPIO_E -} GPIOName; - -typedef enum { - OSC32KCLK = 0, -} RTCName; - -typedef enum { - UART_0 = 0, - UART_1 = 1, - UART_2 = 2, -} UARTName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_1 - -/* SPI defines used to communicate with the MCR20 RF device */ -#define MCR20A_SPI_MOSI PTB16 -#define MCR20A_SPI_MISO PTB17 -#define MCR20A_SPI_SCLK PTB11 -#define MCR20A_SPI_CS PTB10 -#define MCR20A_SPI_RST PTB19 -#define MCR20A_SPI_IRQ PTB3 - -typedef enum { - I2C_0 = 0, - I2C_1 = 1, -} I2CName; - -#define TPM_SHIFT 8 -typedef enum { - PWM_0 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 - PWM_1 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 - PWM_2 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 - PWM_3 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 - PWM_4 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 - PWM_5 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 - PWM_6 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 - PWM_7 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 - PWM_8 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 - PWM_9 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 - PWM_10 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 - PWM_11 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 -} PWMName; - -#define ADC_INSTANCE_SHIFT 8 -#define ADC_B_CHANNEL_SHIFT 5 -typedef enum { - ADC0_SE4a = (0 << ADC_INSTANCE_SHIFT) | 4, - ADC0_SE5a = (0 << ADC_INSTANCE_SHIFT) | 5, - ADC0_SE6a = (0 << ADC_INSTANCE_SHIFT) | 6, - ADC0_SE7a = (0 << ADC_INSTANCE_SHIFT) | 7, - ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, - ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, - ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, - ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, - ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, - ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, - ADC0_SE10 = (0 << ADC_INSTANCE_SHIFT) | 10, - ADC0_SE11 = (0 << ADC_INSTANCE_SHIFT) | 11, - ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, - ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, - ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, - ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, - ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, - ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, - ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, -} ADCName; - -typedef enum { - DAC_0 = 0 -} DACName; - -#define DEVICE_SPI_COUNT 2 -typedef enum { - SPI_0 = 0, - SPI_1 = 1, -} SPIName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PeripheralPins.c deleted file mode 100644 index fedd056..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PeripheralPins.c +++ /dev/null @@ -1,144 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************RTC***************/ -const PinMap PinMap_RTC[] = { - {NC, OSC32KCLK, 0}, -}; - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PTD1, ADC0_SE5b, 0}, - {PTD4, ADC0_SE21, 0}, - {PTD5, ADC0_SE6b, 0}, - {PTD6, ADC0_SE7b, 0}, - {PTD7, ADC0_SE22, 0}, - {PTE0, ADC0_SE10, 0}, - {PTE1, ADC0_SE11, 0}, - {PTE16, ADC0_SE4a, 0}, - {PTE17, ADC0_SE5a, 0}, - {PTE18, ADC0_SE6a, 0}, - {PTE19, ADC0_SE7a, 0}, - {NC, NC, 0} -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {PTD3, I2C_0, 4}, - {PTE0, I2C_1, 6}, - {PTE18, I2C_0, 4}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PTD2, I2C_0, 4}, - {PTE1, I2C_1, 6}, - {PTE19, I2C_0, 4}, - {NC, NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {PTA2, UART_0, 2}, - {PTD7, UART_0, 3}, - {PTC4, UART_1, 3}, - {PTE0, UART_1, 3}, - {PTD3, UART_2, 3}, - {PTE16, UART_2, 3}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PTA1, UART_0, 2}, - {PTD6, UART_0, 3}, - {PTE1, UART_1, 3}, - {PTD2, UART_2, 3}, - {PTE17, UART_2, 3}, - - {NC, NC, 0} -}; - -const PinMap PinMap_UART_CTS[] = { - {PTD1, UART_2, 3}, - {PTD5, UART_0, 3}, - {PTE2, UART_1, 3}, - {PTE18, UART_2, 3}, - {PTA0, UART_0, 2}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RTS[] = { - {PTD4, UART_0, 3}, - {PTE3, UART_1, 3}, - {PTE19, UART_2, 3}, - {PTA3, UART_0, 2}, - {NC, NC, 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {PTB11, SPI_1, 2}, - {PTC5, SPI_0, 2}, - {PTD1, SPI_0, 2}, - {PTE2, SPI_1, 2}, - {PTE17, SPI_0, 2}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PTB16, SPI_1, 2}, - {PTC6, SPI_0, 2}, - {PTD2, SPI_0, 2}, - {PTE1, SPI_1, 2}, - {PTE3, SPI_1, 7}, - {PTE18, SPI_0, 2}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PTB17, SPI_1, 2}, - {PTC7, SPI_0, 2}, - {PTD3, SPI_0, 2}, - {PTE1, SPI_1, 7}, - {PTE3, SPI_1, 2}, - {PTE19, SPI_0, 2}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PTB10, SPI_1, 2}, - {PTC4, SPI_0, 2}, - {PTE4, SPI_1, 2}, - {PTE16, SPI_0, 2}, - {NC, NC, 0} -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {PTC4, PWM_3, 4}, - {PTD4, PWM_4, 4}, - {PTD5, PWM_5, 4}, - {PTD6, PWM_6, 4}, - {PTD7, PWM_7, 4}, - {PTA0, PWM_5, 3}, - {PTA1, PWM_6, 3}, - {PTA2, PWM_7, 3}, - {PTA3, PWM_0, 3}, - {PTA4, PWM_1, 3}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PinNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PinNames.h deleted file mode 100644 index 534e1d8..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PinNames.h +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define GPIO_PORT_SHIFT 12 - -typedef enum { - PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), - PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), - PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), - PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), - PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), - PTA18 = (0 << GPIO_PORT_SHIFT | 18), - PTA19 = (0 << GPIO_PORT_SHIFT | 19), - PTB3 = (1 << GPIO_PORT_SHIFT | 3), - PTB10 = (1 << GPIO_PORT_SHIFT | 10), - PTB11 = (1 << GPIO_PORT_SHIFT | 11), - PTB16 = (1 << GPIO_PORT_SHIFT | 16), - PTB17 = (1 << GPIO_PORT_SHIFT | 17), - PTB19 = (1 << GPIO_PORT_SHIFT | 19), - PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), - PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), - PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), - PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), - PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), - PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), - PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), - PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), - PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), - PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), - PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), - PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), - PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), - PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), - PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), - PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), - PTE2 = (4 << GPIO_PORT_SHIFT | 2 ), - PTE3 = (4 << GPIO_PORT_SHIFT | 3 ), - PTE4 = (4 << GPIO_PORT_SHIFT | 4 ), - PTE16 = (4 << GPIO_PORT_SHIFT | 16), - PTE17 = (4 << GPIO_PORT_SHIFT | 17), - PTE18 = (4 << GPIO_PORT_SHIFT | 18), - PTE19 = (4 << GPIO_PORT_SHIFT | 19), - - LED_RED = PTD4, - LED_GREEN = PTD5, - LED_BLUE = PTD6, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = PTD7, - - //Push buttons - SW1 = PTE4, - SW2 = PTE3, - SW3 = PTD1, - SW4 = PTA19, - // Standardized button names - BUTTON1 = SW1, - BUTTON2 = SW2, - BUTTON3 = SW3, - BUTTON4 = SW4, - - // USB Pins - USBTX = PTE0, - USBRX = PTE1, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Arduino Headers - D0 = PTD7, - D1 = PTD6, - D2 = PTD5, - D3 = PTD4, - D4 = NC, - D5 = NC, - D6 = PTE4, - D7 = PTD1, - D8 = PTA19, - D9 = PTA18, - D10 = PTC4, - D11 = PTC6, - D12 = PTC7, - D13 = PTC5, - D14 = PTD3, - D15 = PTD2, - - I2C_SCL = D15, - I2C_SDA = D14, - - A0 = NC, - A1 = NC, - A2 = NC, - A3 = NC, - A4 = NC, - A5 = NC -} PinName; - - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/device.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/device.h deleted file mode 100644 index 29a4e7a..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/device.h +++ /dev/null @@ -1,39 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 24 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/fsl_clock_config.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/fsl_clock_config.c deleted file mode 100644 index 20e9824..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/fsl_clock_config.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_common.h" -#include "fsl_smc.h" -#include "fsl_clock_config.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - * Code - ******************************************************************************/ -/* - * How to setup clock using clock driver functions: - * - * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock - * and flash clock are in allowed range during clock mode switch. - * - * 2. Call BOARD_ExtClk_Setup_HookUp to set the clock output for wireless modem. - * - * 3. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. - * - * 4. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and - * internal reference clock(MCGIRCLK). Follow the steps to setup: - * - * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. - * - * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured - * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig - * explicitly to setup MCGIRCLK. - * - * 3). Don't need to configure FLL explicitly, because if target mode is FLL - * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, - * if the target mode is not FLL mode, the FLL is disabled. - * - * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been - * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could - * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. - * - * 5. Call CLOCK_SetSimConfig to set the clock configuration in SIM. - */ - -uint8_t BOARD_ExtClk_Setup_HookUp(uint32_t clk_out_value) -{ - uint8_t result = 0; - - switch (clk_out_value) - { - case 4000000U: - /* Start XCVR clock in order to derive MCGOUTCLK */ - SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; /* Ungate PORTB and PORTC clock*/ - GPIOB->PDDR |= 0x00080000u; /* Set PORTB.19 as output - XCVR RESET pin */ - GPIOC->PDDR |= 0x00000001u; /* Set PORTC.0 as output - XCVR GPIO5 pin */ - PORTB->PCR[19] = (PORTB->PCR[19] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(0x01u); /* PORTB.19 as GPIO */ - PORTC->PCR[0] = (PORTC->PCR[0] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(0x01u); /* PORTC.0 as GPIO*/ - GPIOC->PCOR = 0x00000001u; /* Clear XCVR GPIO5 pin*/ - GPIOB->PCOR = 0x00080000u; /* Clear XCVR RESET pin*/ - GPIOB->PSOR = 0x00080000u; /* Set XCVR RESET pin*/ - result = 1U; /* The output was set successfully */ - break; - case 0U: - /* No initialization, modem remains in the reset state */ - result = 1U; /* The output was set successfully */ - break; - default: - result = 0U; /* Requested value cannot be set */ - break; - } - return result; -} - -void BOARD_BootClockVLPR(void) -{ - /* - * Core clock: 4MHz - */ - const sim_clock_config_t simConfig = { - .pllFllSel = 0U, /* PLLFLLSEL select FLL. */ - .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ - .clkdiv1 = 0x00030000U, /* SIM_CLKDIV1. */ - }; - - CLOCK_SetSimSafeDivs(); - - CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable); - - CLOCK_SetSimConfig(&simConfig); - - SystemCoreClock = 4000000U; - - SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); - SMC_SetPowerModeVlpr(SMC, false); - while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) - { - } -} - -void BOARD_BootClockRUN(void) -{ - /* - * Core clock: 48MHz - * Bus clock: 24MHz - */ - const mcg_pll_config_t pll0Config = { - .enableMode = 0U, - .prdiv = 0x1U, - .vdiv = 0x0U, - }; - const sim_clock_config_t simConfig = { - .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ - .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ - .clkdiv1 = 0x00010000U, /* SIM_CLKDIV1. */ - }; - - /* Perform initialization of the wireless modem clock output */ - if (BOARD_ExtClk_Setup_HookUp(BOARD_XTAL0_CLK_HZ) != 1U) - { - /* If the initialization was not successfully, do not continue with clock setup */ - return; - } - CLOCK_SetSimSafeDivs(); - BOARD_InitOsc0(); - - CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config); - - CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0); - CLOCK_SetSimConfig(&simConfig); - - SystemCoreClock = 48000000U; -} - -void BOARD_InitOsc0(void) -{ - const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, - .capLoad = 0, - .workMode = kOSC_ModeOscLowPower, - .oscerConfig = { - .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop, -#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) - .erclkDiv = 0U, -#endif - }}; - - CLOCK_InitOsc0(&oscConfig); - - /* Passing the XTAL0 frequency to clock driver. */ - CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/fsl_clock_config.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/fsl_clock_config.h deleted file mode 100644 index c5fcefa..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/fsl_clock_config.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 4000000U -#define BOARD_XTAL32K_CLK_HZ 32768U - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -void BOARD_BootClockVLPR(void); -void BOARD_BootClockRUN(void); -uint8_t BOARD_ExtClk_Setup_HookUp(uint32_t clk_out_value); -void BOARD_InitOsc0(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/mbed_overrides.c deleted file mode 100644 index 55e6972..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/mbed_overrides.c +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "fsl_rtc.h" -#include "fsl_clock_config.h" - -// called before main - implement here if board needs it otherwise, let -// the application override this if necessary -void mbed_sdk_init() -{ - rtc_config_t rtc_basic_config; - uint32_t u32cTPR_counter = 0; - - BOARD_BootClockRUN(); - - CLOCK_EnableClock(kCLOCK_Rtc0); - - /* Check if the Rtc oscillator is enabled */ - if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { - /*Init the RTC with default configuration*/ - RTC_GetDefaultConfig(&rtc_basic_config); - - /* Setup the 32K RTC OSC */ - RTC_Init(RTC, &rtc_basic_config); - - /* Enable the RTC 32KHz oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; - - /* Start the RTC time counter */ - RTC_StartTimer(RTC); - - /* Verify TPR register reaches 4096 counts */ - while (u32cTPR_counter < 4096) { - u32cTPR_counter = RTC->TPR; - } - /* 32kHz Oscillator is ready. */ - RTC_Deinit(RTC); - } - - CLOCK_DisableClock(kCLOCK_Rtc0); -} - -// Change the NMI pin to an input. This allows NMI pin to -// be used as a low power mode wakeup. The application will -// need to change the pin back to NMI_b or wakeup only occurs once! -void NMI_Handler(void) -{ - gpio_t gpio; - gpio_init_in(&gpio, PTA4); -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/MKW24D5.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/MKW24D5.h deleted file mode 100644 index cf029e1..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/MKW24D5.h +++ /dev/null @@ -1,8548 +0,0 @@ -/* -** ################################################################### -** Processor: MKW24D512VHA5 -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: MKW2xDRM Rev.2 July 2014 -** Version: rev. 2.0, 2014-11-26 -** Build: b160512 -** -** Abstract: -** CMSIS Peripheral Access Layer for MKW24D5 -** -** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-11-22) -** Initial version. -** - rev. 2.0 (2014-11-26) -** update of SystemInit() imlementation -** Module access macro module_BASES replaced by module_BASE_PTRS. -** Register accessor macros added to the memory map. -** MCG - bit LOLS in MCG_S register renamed to LOLS0. -** DAC0 registers removed. -** -** ################################################################### -*/ - -/*! - * @file MKW24D5.h - * @version 2.0 - * @date 2014-11-26 - * @brief CMSIS Peripheral Access Layer for MKW24D5 - * - * CMSIS Peripheral Access Layer for MKW24D5 - */ - -#ifndef _MKW24D5_H_ -#define _MKW24D5_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0200U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U - -/** - * @brief Macro to calculate address of an aliased word in the peripheral - * bitband area for a peripheral register and bit (bit band region 0x40000000 to - * 0x400FFFFF). - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Address of the aliased word in the peripheral bitband area. - */ -#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 32bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) -#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 16bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 8bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 81 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ - DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ - DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ - DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ - DMA4_IRQn = 4, /**< DMA channel 4 transfer complete */ - DMA5_IRQn = 5, /**< DMA channel 5 transfer complete */ - DMA6_IRQn = 6, /**< DMA channel 6 transfer complete */ - DMA7_IRQn = 7, /**< DMA channel 7 transfer complete */ - DMA8_IRQn = 8, /**< DMA channel 8 transfer complete */ - DMA9_IRQn = 9, /**< DMA channel 9 transfer complete */ - DMA10_IRQn = 10, /**< DMA channel 10 transfer complete */ - DMA11_IRQn = 11, /**< DMA channel 11 transfer complete */ - DMA12_IRQn = 12, /**< DMA channel 12 transfer complete */ - DMA13_IRQn = 13, /**< DMA channel 13 transfer complete */ - DMA14_IRQn = 14, /**< DMA channel 14 transfer complete */ - DMA15_IRQn = 15, /**< DMA channel 15 transfer complete */ - DMA_Error_IRQn = 16, /**< DMA channel 0 - 15 error */ - MCM_IRQn = 17, /**< MCM normal interrupt */ - FTFL_IRQn = 18, /**< FTFL command complete */ - FTFL_Collision_IRQn = 19, /**< FTFL read collision */ - PMC_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */ - LLWU_IRQn = 21, /**< Low leakage wakeup */ - WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */ - RNG_IRQn = 23, /**< Randon number generator */ - I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */ - I2C1_IRQn = 25, /**< Inter-integrated circuit 1 */ - SPI0_IRQn = 26, /**< Serial peripheral Interface 0 */ - SPI1_IRQn = 27, /**< Serial peripheral Interface 1 */ - I2S0_Tx_IRQn = 28, /**< Integrated interchip sound 0 transmit interrupt */ - I2S0_Rx_IRQn = 29, /**< Integrated interchip sound 0 receive interrupt */ - Reserved46_IRQn = 30, /**< Reserved interrupt */ - UART0_RX_TX_IRQn = 31, /**< UART0 receive/transmit interrupt */ - UART0_ERR_IRQn = 32, /**< UART0 error interrupt */ - UART1_RX_TX_IRQn = 33, /**< UART1 receive/transmit interrupt */ - UART1_ERR_IRQn = 34, /**< UART1 error interrupt */ - UART2_RX_TX_IRQn = 35, /**< UART2 receive/transmit interrupt */ - UART2_ERR_IRQn = 36, /**< UART2 error interrupt */ - Reserved53_IRQn = 37, /**< Reserved interrupt */ - Reserved54_IRQn = 38, /**< Reserved interrupt */ - ADC0_IRQn = 39, /**< Analog-to-digital converter 0 */ - CMP0_IRQn = 40, /**< Comparator 0 */ - CMP1_IRQn = 41, /**< Comparator 1 */ - FTM0_IRQn = 42, /**< FlexTimer module 0 fault, overflow and channels interrupt */ - FTM1_IRQn = 43, /**< FlexTimer module 1 fault, overflow and channels interrupt */ - FTM2_IRQn = 44, /**< FlexTimer module 2 fault, overflow and channels interrupt */ - CMT_IRQn = 45, /**< Carrier modulator transmitter */ - RTC_IRQn = 46, /**< Real time clock */ - RTC_Seconds_IRQn = 47, /**< Real time clock seconds */ - PIT0_IRQn = 48, /**< Periodic interrupt timer channel 0 */ - PIT1_IRQn = 49, /**< Periodic interrupt timer channel 1 */ - PIT2_IRQn = 50, /**< Periodic interrupt timer channel 2 */ - PIT3_IRQn = 51, /**< Periodic interrupt timer channel 3 */ - PDB0_IRQn = 52, /**< Programmable delay block */ - USB0_IRQn = 53, /**< USB OTG interrupt */ - USBDCD_IRQn = 54, /**< USB charger detect */ - Reserved71_IRQn = 55, /**< Reserved interrupt */ - Reserved72_IRQn = 56, /**< Reserved interrupt */ - MCG_IRQn = 57, /**< Multipurpose clock generator */ - LPTMR0_IRQn = 58, /**< Low power timer interrupt */ - PORTA_IRQn = 59, /**< Port A pin detect interrupt */ - PORTB_IRQn = 60, /**< Port B pin detect interrupt */ - PORTC_IRQn = 61, /**< Port C pin detect interrupt */ - PORTD_IRQn = 62, /**< Port D pin detect interrupt */ - PORTE_IRQn = 63, /**< Port E pin detect interrupt */ - SWI_IRQn = 64 /**< Software interrupt */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MKW24D5.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup edma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ - kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ - kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ - kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ - kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ - kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ - kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ - kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ - kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ - kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ - kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ - kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ - kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ - kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ - kDmaRequestMux0I2S0Rx = 14|0x100U, /**< I2S0 Receive. */ - kDmaRequestMux0I2S0Tx = 15|0x100U, /**< I2S0 Transmit. */ - kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */ - kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */ - kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */ - kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */ - kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */ - kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */ - kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */ - kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */ - kDmaRequestMux0FTM0Channel0 = 24|0x100U, /**< FTM0 C0V. */ - kDmaRequestMux0FTM0Channel1 = 25|0x100U, /**< FTM0 C1V. */ - kDmaRequestMux0FTM0Channel2 = 26|0x100U, /**< FTM0 C2V. */ - kDmaRequestMux0FTM0Channel3 = 27|0x100U, /**< FTM0 C3V. */ - kDmaRequestMux0FTM0Channel4 = 28|0x100U, /**< FTM0 C4V. */ - kDmaRequestMux0FTM0Channel5 = 29|0x100U, /**< FTM0 C5V. */ - kDmaRequestMux0FTM0Channel6 = 30|0x100U, /**< FTM0 C6V. */ - kDmaRequestMux0FTM0Channel7 = 31|0x100U, /**< FTM0 C7V. */ - kDmaRequestMux0FTM1Channel0 = 32|0x100U, /**< FTM1 C0V. */ - kDmaRequestMux0FTM1Channel1 = 33|0x100U, /**< FTM1 C1V. */ - kDmaRequestMux0FTM2Channel0 = 34|0x100U, /**< FTM2 C0V. */ - kDmaRequestMux0FTM2Channel1 = 35|0x100U, /**< FTM2 C1V. */ - kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ - kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ - kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ - kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ - kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ - kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ - kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ - kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ - kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ - kDmaRequestMux0Reserved45 = 45|0x100U, /**< Reserved45 */ - kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ - kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ - kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ - kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ - kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ - kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ - kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ - kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ - kDmaRequestMux0AlwaysOn54 = 54|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn55 = 55|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn56 = 56|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn57 = 57|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name SC1 - ADC Status and Control Registers 1 */ -#define ADC_SC1_ADCH_MASK (0x1FU) -#define ADC_SC1_ADCH_SHIFT (0U) -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) -#define ADC_SC1_DIFF_MASK (0x20U) -#define ADC_SC1_DIFF_SHIFT (5U) -#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) -#define ADC_SC1_AIEN_MASK (0x40U) -#define ADC_SC1_AIEN_SHIFT (6U) -#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) -#define ADC_SC1_COCO_MASK (0x80U) -#define ADC_SC1_COCO_SHIFT (7U) -#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) - -/* The count of ADC_SC1 */ -#define ADC_SC1_COUNT (2U) - -/*! @name CFG1 - ADC Configuration Register 1 */ -#define ADC_CFG1_ADICLK_MASK (0x3U) -#define ADC_CFG1_ADICLK_SHIFT (0U) -#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) -#define ADC_CFG1_MODE_MASK (0xCU) -#define ADC_CFG1_MODE_SHIFT (2U) -#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) -#define ADC_CFG1_ADLSMP_MASK (0x10U) -#define ADC_CFG1_ADLSMP_SHIFT (4U) -#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) -#define ADC_CFG1_ADIV_MASK (0x60U) -#define ADC_CFG1_ADIV_SHIFT (5U) -#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) -#define ADC_CFG1_ADLPC_MASK (0x80U) -#define ADC_CFG1_ADLPC_SHIFT (7U) -#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) - -/*! @name CFG2 - ADC Configuration Register 2 */ -#define ADC_CFG2_ADLSTS_MASK (0x3U) -#define ADC_CFG2_ADLSTS_SHIFT (0U) -#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) -#define ADC_CFG2_ADHSC_MASK (0x4U) -#define ADC_CFG2_ADHSC_SHIFT (2U) -#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) -#define ADC_CFG2_ADACKEN_MASK (0x8U) -#define ADC_CFG2_ADACKEN_SHIFT (3U) -#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) -#define ADC_CFG2_MUXSEL_MASK (0x10U) -#define ADC_CFG2_MUXSEL_SHIFT (4U) -#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) - -/*! @name R - ADC Data Result Register */ -#define ADC_R_D_MASK (0xFFFFU) -#define ADC_R_D_SHIFT (0U) -#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) - -/* The count of ADC_R */ -#define ADC_R_COUNT (2U) - -/*! @name CV1 - Compare Value Registers */ -#define ADC_CV1_CV_MASK (0xFFFFU) -#define ADC_CV1_CV_SHIFT (0U) -#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) - -/*! @name CV2 - Compare Value Registers */ -#define ADC_CV2_CV_MASK (0xFFFFU) -#define ADC_CV2_CV_SHIFT (0U) -#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) - -/*! @name SC2 - Status and Control Register 2 */ -#define ADC_SC2_REFSEL_MASK (0x3U) -#define ADC_SC2_REFSEL_SHIFT (0U) -#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) -#define ADC_SC2_DMAEN_MASK (0x4U) -#define ADC_SC2_DMAEN_SHIFT (2U) -#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) -#define ADC_SC2_ACREN_MASK (0x8U) -#define ADC_SC2_ACREN_SHIFT (3U) -#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) -#define ADC_SC2_ACFGT_MASK (0x10U) -#define ADC_SC2_ACFGT_SHIFT (4U) -#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) -#define ADC_SC2_ACFE_MASK (0x20U) -#define ADC_SC2_ACFE_SHIFT (5U) -#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) -#define ADC_SC2_ADTRG_MASK (0x40U) -#define ADC_SC2_ADTRG_SHIFT (6U) -#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) -#define ADC_SC2_ADACT_MASK (0x80U) -#define ADC_SC2_ADACT_SHIFT (7U) -#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) - -/*! @name SC3 - Status and Control Register 3 */ -#define ADC_SC3_AVGS_MASK (0x3U) -#define ADC_SC3_AVGS_SHIFT (0U) -#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) -#define ADC_SC3_AVGE_MASK (0x4U) -#define ADC_SC3_AVGE_SHIFT (2U) -#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) -#define ADC_SC3_ADCO_MASK (0x8U) -#define ADC_SC3_ADCO_SHIFT (3U) -#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) -#define ADC_SC3_CALF_MASK (0x40U) -#define ADC_SC3_CALF_SHIFT (6U) -#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) -#define ADC_SC3_CAL_MASK (0x80U) -#define ADC_SC3_CAL_SHIFT (7U) -#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) - -/*! @name OFS - ADC Offset Correction Register */ -#define ADC_OFS_OFS_MASK (0xFFFFU) -#define ADC_OFS_OFS_SHIFT (0U) -#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) - -/*! @name PG - ADC Plus-Side Gain Register */ -#define ADC_PG_PG_MASK (0xFFFFU) -#define ADC_PG_PG_SHIFT (0U) -#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) - -/*! @name MG - ADC Minus-Side Gain Register */ -#define ADC_MG_MG_MASK (0xFFFFU) -#define ADC_MG_MG_SHIFT (0U) -#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) - -/*! @name CLPD - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLPD_CLPD_MASK (0x3FU) -#define ADC_CLPD_CLPD_SHIFT (0U) -#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) - -/*! @name CLPS - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLPS_CLPS_MASK (0x3FU) -#define ADC_CLPS_CLPS_SHIFT (0U) -#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) - -/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLP4_CLP4_MASK (0x3FFU) -#define ADC_CLP4_CLP4_SHIFT (0U) -#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) - -/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLP3_CLP3_MASK (0x1FFU) -#define ADC_CLP3_CLP3_SHIFT (0U) -#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) - -/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLP2_CLP2_MASK (0xFFU) -#define ADC_CLP2_CLP2_SHIFT (0U) -#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) - -/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLP1_CLP1_MASK (0x7FU) -#define ADC_CLP1_CLP1_SHIFT (0U) -#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) - -/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLP0_CLP0_MASK (0x3FU) -#define ADC_CLP0_CLP0_SHIFT (0U) -#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) - -/*! @name CLMD - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLMD_CLMD_MASK (0x3FU) -#define ADC_CLMD_CLMD_SHIFT (0U) -#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) - -/*! @name CLMS - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLMS_CLMS_MASK (0x3FU) -#define ADC_CLMS_CLMS_SHIFT (0U) -#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) - -/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLM4_CLM4_MASK (0x3FFU) -#define ADC_CLM4_CLM4_SHIFT (0U) -#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) - -/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLM3_CLM3_MASK (0x1FFU) -#define ADC_CLM3_CLM3_SHIFT (0U) -#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) - -/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLM2_CLM2_MASK (0xFFU) -#define ADC_CLM2_CLM2_SHIFT (0U) -#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) - -/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLM1_CLM1_MASK (0x7FU) -#define ADC_CLM1_CLM1_SHIFT (0U) -#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) - -/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLM0_CLM0_MASK (0x3FU) -#define ADC_CLM0_CLM0_SHIFT (0U) -#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -/** Peripheral ADC0 base address */ -#define ADC0_BASE (0x4003B000u) -/** Peripheral ADC0 base pointer */ -#define ADC0 ((ADC_Type *)ADC0_BASE) -/** Array initializer of ADC peripheral base addresses */ -#define ADC_BASE_ADDRS { ADC0_BASE } -/** Array initializer of ADC peripheral base pointers */ -#define ADC_BASE_PTRS { ADC0 } -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CAU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer - * @{ - */ - -/** CAU - Register Layout Typedef */ -typedef struct { - __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[2048]; - __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */ - __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */ - __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */ - uint8_t RESERVED_1[20]; - __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */ - __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */ - __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */ - uint8_t RESERVED_2[20]; - __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */ - __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */ - __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */ - uint8_t RESERVED_3[20]; - __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */ - __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */ - __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */ - uint8_t RESERVED_4[84]; - __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */ - __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */ - __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */ - uint8_t RESERVED_5[20]; - __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */ - __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */ - __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */ - uint8_t RESERVED_6[276]; - __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */ - __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */ - __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */ - uint8_t RESERVED_7[20]; - __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */ - __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */ - __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */ -} CAU_Type; - -/* ---------------------------------------------------------------------------- - -- CAU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAU_Register_Masks CAU Register Masks - * @{ - */ - -/*! @name DIRECT - Direct access register 0..Direct access register 15 */ -#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK) -#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK) -#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK) -#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK) -#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK) -#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK) -#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK) -#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK) -#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK) -#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK) -#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK) -#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK) -#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK) -#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK) -#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK) -#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU) -#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U) -#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK) - -/* The count of CAU_DIRECT */ -#define CAU_DIRECT_COUNT (16U) - -/*! @name LDR_CASR - Status register - Load Register command */ -#define CAU_LDR_CASR_IC_MASK (0x1U) -#define CAU_LDR_CASR_IC_SHIFT (0U) -#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK) -#define CAU_LDR_CASR_DPE_MASK (0x2U) -#define CAU_LDR_CASR_DPE_SHIFT (1U) -#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK) -#define CAU_LDR_CASR_VER_MASK (0xF0000000U) -#define CAU_LDR_CASR_VER_SHIFT (28U) -#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK) - -/*! @name LDR_CAA - Accumulator register - Load Register command */ -#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU) -#define CAU_LDR_CAA_ACC_SHIFT (0U) -#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK) - -/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */ -#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU) -#define CAU_LDR_CA_CA0_SHIFT (0U) -#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK) -#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU) -#define CAU_LDR_CA_CA1_SHIFT (0U) -#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK) -#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU) -#define CAU_LDR_CA_CA2_SHIFT (0U) -#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK) -#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU) -#define CAU_LDR_CA_CA3_SHIFT (0U) -#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK) -#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU) -#define CAU_LDR_CA_CA4_SHIFT (0U) -#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK) -#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU) -#define CAU_LDR_CA_CA5_SHIFT (0U) -#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK) -#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU) -#define CAU_LDR_CA_CA6_SHIFT (0U) -#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK) -#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU) -#define CAU_LDR_CA_CA7_SHIFT (0U) -#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK) -#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU) -#define CAU_LDR_CA_CA8_SHIFT (0U) -#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK) - -/* The count of CAU_LDR_CA */ -#define CAU_LDR_CA_COUNT (9U) - -/*! @name STR_CASR - Status register - Store Register command */ -#define CAU_STR_CASR_IC_MASK (0x1U) -#define CAU_STR_CASR_IC_SHIFT (0U) -#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK) -#define CAU_STR_CASR_DPE_MASK (0x2U) -#define CAU_STR_CASR_DPE_SHIFT (1U) -#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK) -#define CAU_STR_CASR_VER_MASK (0xF0000000U) -#define CAU_STR_CASR_VER_SHIFT (28U) -#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK) - -/*! @name STR_CAA - Accumulator register - Store Register command */ -#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU) -#define CAU_STR_CAA_ACC_SHIFT (0U) -#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK) - -/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */ -#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU) -#define CAU_STR_CA_CA0_SHIFT (0U) -#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK) -#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU) -#define CAU_STR_CA_CA1_SHIFT (0U) -#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK) -#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU) -#define CAU_STR_CA_CA2_SHIFT (0U) -#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK) -#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU) -#define CAU_STR_CA_CA3_SHIFT (0U) -#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK) -#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU) -#define CAU_STR_CA_CA4_SHIFT (0U) -#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK) -#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU) -#define CAU_STR_CA_CA5_SHIFT (0U) -#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK) -#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU) -#define CAU_STR_CA_CA6_SHIFT (0U) -#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK) -#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU) -#define CAU_STR_CA_CA7_SHIFT (0U) -#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK) -#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU) -#define CAU_STR_CA_CA8_SHIFT (0U) -#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK) - -/* The count of CAU_STR_CA */ -#define CAU_STR_CA_COUNT (9U) - -/*! @name ADR_CASR - Status register - Add Register command */ -#define CAU_ADR_CASR_IC_MASK (0x1U) -#define CAU_ADR_CASR_IC_SHIFT (0U) -#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK) -#define CAU_ADR_CASR_DPE_MASK (0x2U) -#define CAU_ADR_CASR_DPE_SHIFT (1U) -#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK) -#define CAU_ADR_CASR_VER_MASK (0xF0000000U) -#define CAU_ADR_CASR_VER_SHIFT (28U) -#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK) - -/*! @name ADR_CAA - Accumulator register - Add to register command */ -#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU) -#define CAU_ADR_CAA_ACC_SHIFT (0U) -#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK) - -/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */ -#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU) -#define CAU_ADR_CA_CA0_SHIFT (0U) -#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK) -#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU) -#define CAU_ADR_CA_CA1_SHIFT (0U) -#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK) -#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU) -#define CAU_ADR_CA_CA2_SHIFT (0U) -#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK) -#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU) -#define CAU_ADR_CA_CA3_SHIFT (0U) -#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK) -#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU) -#define CAU_ADR_CA_CA4_SHIFT (0U) -#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK) -#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU) -#define CAU_ADR_CA_CA5_SHIFT (0U) -#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK) -#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU) -#define CAU_ADR_CA_CA6_SHIFT (0U) -#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK) -#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU) -#define CAU_ADR_CA_CA7_SHIFT (0U) -#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK) -#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU) -#define CAU_ADR_CA_CA8_SHIFT (0U) -#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK) - -/* The count of CAU_ADR_CA */ -#define CAU_ADR_CA_COUNT (9U) - -/*! @name RADR_CASR - Status register - Reverse and Add to Register command */ -#define CAU_RADR_CASR_IC_MASK (0x1U) -#define CAU_RADR_CASR_IC_SHIFT (0U) -#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK) -#define CAU_RADR_CASR_DPE_MASK (0x2U) -#define CAU_RADR_CASR_DPE_SHIFT (1U) -#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK) -#define CAU_RADR_CASR_VER_MASK (0xF0000000U) -#define CAU_RADR_CASR_VER_SHIFT (28U) -#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK) - -/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */ -#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU) -#define CAU_RADR_CAA_ACC_SHIFT (0U) -#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK) - -/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */ -#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU) -#define CAU_RADR_CA_CA0_SHIFT (0U) -#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK) -#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU) -#define CAU_RADR_CA_CA1_SHIFT (0U) -#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK) -#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU) -#define CAU_RADR_CA_CA2_SHIFT (0U) -#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK) -#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU) -#define CAU_RADR_CA_CA3_SHIFT (0U) -#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK) -#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU) -#define CAU_RADR_CA_CA4_SHIFT (0U) -#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK) -#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU) -#define CAU_RADR_CA_CA5_SHIFT (0U) -#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK) -#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU) -#define CAU_RADR_CA_CA6_SHIFT (0U) -#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK) -#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU) -#define CAU_RADR_CA_CA7_SHIFT (0U) -#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK) -#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU) -#define CAU_RADR_CA_CA8_SHIFT (0U) -#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK) - -/* The count of CAU_RADR_CA */ -#define CAU_RADR_CA_COUNT (9U) - -/*! @name XOR_CASR - Status register - Exclusive Or command */ -#define CAU_XOR_CASR_IC_MASK (0x1U) -#define CAU_XOR_CASR_IC_SHIFT (0U) -#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK) -#define CAU_XOR_CASR_DPE_MASK (0x2U) -#define CAU_XOR_CASR_DPE_SHIFT (1U) -#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK) -#define CAU_XOR_CASR_VER_MASK (0xF0000000U) -#define CAU_XOR_CASR_VER_SHIFT (28U) -#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK) - -/*! @name XOR_CAA - Accumulator register - Exclusive Or command */ -#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU) -#define CAU_XOR_CAA_ACC_SHIFT (0U) -#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK) - -/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */ -#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU) -#define CAU_XOR_CA_CA0_SHIFT (0U) -#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK) -#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU) -#define CAU_XOR_CA_CA1_SHIFT (0U) -#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK) -#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU) -#define CAU_XOR_CA_CA2_SHIFT (0U) -#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK) -#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU) -#define CAU_XOR_CA_CA3_SHIFT (0U) -#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK) -#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU) -#define CAU_XOR_CA_CA4_SHIFT (0U) -#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK) -#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU) -#define CAU_XOR_CA_CA5_SHIFT (0U) -#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK) -#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU) -#define CAU_XOR_CA_CA6_SHIFT (0U) -#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK) -#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU) -#define CAU_XOR_CA_CA7_SHIFT (0U) -#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK) -#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU) -#define CAU_XOR_CA_CA8_SHIFT (0U) -#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK) - -/* The count of CAU_XOR_CA */ -#define CAU_XOR_CA_COUNT (9U) - -/*! @name ROTL_CASR - Status register - Rotate Left command */ -#define CAU_ROTL_CASR_IC_MASK (0x1U) -#define CAU_ROTL_CASR_IC_SHIFT (0U) -#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK) -#define CAU_ROTL_CASR_DPE_MASK (0x2U) -#define CAU_ROTL_CASR_DPE_SHIFT (1U) -#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK) -#define CAU_ROTL_CASR_VER_MASK (0xF0000000U) -#define CAU_ROTL_CASR_VER_SHIFT (28U) -#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK) - -/*! @name ROTL_CAA - Accumulator register - Rotate Left command */ -#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU) -#define CAU_ROTL_CAA_ACC_SHIFT (0U) -#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK) - -/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */ -#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU) -#define CAU_ROTL_CA_CA0_SHIFT (0U) -#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK) -#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU) -#define CAU_ROTL_CA_CA1_SHIFT (0U) -#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK) -#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU) -#define CAU_ROTL_CA_CA2_SHIFT (0U) -#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK) -#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU) -#define CAU_ROTL_CA_CA3_SHIFT (0U) -#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK) -#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU) -#define CAU_ROTL_CA_CA4_SHIFT (0U) -#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK) -#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU) -#define CAU_ROTL_CA_CA5_SHIFT (0U) -#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK) -#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU) -#define CAU_ROTL_CA_CA6_SHIFT (0U) -#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK) -#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU) -#define CAU_ROTL_CA_CA7_SHIFT (0U) -#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK) -#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU) -#define CAU_ROTL_CA_CA8_SHIFT (0U) -#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK) - -/* The count of CAU_ROTL_CA */ -#define CAU_ROTL_CA_COUNT (9U) - -/*! @name AESC_CASR - Status register - AES Column Operation command */ -#define CAU_AESC_CASR_IC_MASK (0x1U) -#define CAU_AESC_CASR_IC_SHIFT (0U) -#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK) -#define CAU_AESC_CASR_DPE_MASK (0x2U) -#define CAU_AESC_CASR_DPE_SHIFT (1U) -#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK) -#define CAU_AESC_CASR_VER_MASK (0xF0000000U) -#define CAU_AESC_CASR_VER_SHIFT (28U) -#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK) - -/*! @name AESC_CAA - Accumulator register - AES Column Operation command */ -#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU) -#define CAU_AESC_CAA_ACC_SHIFT (0U) -#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK) - -/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */ -#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU) -#define CAU_AESC_CA_CA0_SHIFT (0U) -#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK) -#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU) -#define CAU_AESC_CA_CA1_SHIFT (0U) -#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK) -#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU) -#define CAU_AESC_CA_CA2_SHIFT (0U) -#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK) -#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU) -#define CAU_AESC_CA_CA3_SHIFT (0U) -#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK) -#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU) -#define CAU_AESC_CA_CA4_SHIFT (0U) -#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK) -#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU) -#define CAU_AESC_CA_CA5_SHIFT (0U) -#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK) -#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU) -#define CAU_AESC_CA_CA6_SHIFT (0U) -#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK) -#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU) -#define CAU_AESC_CA_CA7_SHIFT (0U) -#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK) -#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU) -#define CAU_AESC_CA_CA8_SHIFT (0U) -#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK) - -/* The count of CAU_AESC_CA */ -#define CAU_AESC_CA_COUNT (9U) - -/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */ -#define CAU_AESIC_CASR_IC_MASK (0x1U) -#define CAU_AESIC_CASR_IC_SHIFT (0U) -#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK) -#define CAU_AESIC_CASR_DPE_MASK (0x2U) -#define CAU_AESIC_CASR_DPE_SHIFT (1U) -#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK) -#define CAU_AESIC_CASR_VER_MASK (0xF0000000U) -#define CAU_AESIC_CASR_VER_SHIFT (28U) -#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK) - -/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */ -#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU) -#define CAU_AESIC_CAA_ACC_SHIFT (0U) -#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK) - -/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */ -#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU) -#define CAU_AESIC_CA_CA0_SHIFT (0U) -#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK) -#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU) -#define CAU_AESIC_CA_CA1_SHIFT (0U) -#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK) -#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU) -#define CAU_AESIC_CA_CA2_SHIFT (0U) -#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK) -#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU) -#define CAU_AESIC_CA_CA3_SHIFT (0U) -#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK) -#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU) -#define CAU_AESIC_CA_CA4_SHIFT (0U) -#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK) -#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU) -#define CAU_AESIC_CA_CA5_SHIFT (0U) -#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK) -#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU) -#define CAU_AESIC_CA_CA6_SHIFT (0U) -#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK) -#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU) -#define CAU_AESIC_CA_CA7_SHIFT (0U) -#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK) -#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU) -#define CAU_AESIC_CA_CA8_SHIFT (0U) -#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK) - -/* The count of CAU_AESIC_CA */ -#define CAU_AESIC_CA_COUNT (9U) - - -/*! - * @} - */ /* end of group CAU_Register_Masks */ - - -/* CAU - Peripheral instance base addresses */ -/** Peripheral CAU base address */ -#define CAU_BASE (0xE0081000u) -/** Peripheral CAU base pointer */ -#define CAU ((CAU_Type *)CAU_BASE) -/** Array initializer of CAU peripheral base addresses */ -#define CAU_BASE_ADDRS { CAU_BASE } -/** Array initializer of CAU peripheral base pointers */ -#define CAU_BASE_PTRS { CAU } - -/*! - * @} - */ /* end of group CAU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CMP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer - * @{ - */ - -/** CMP - Register Layout Typedef */ -typedef struct { - __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ - __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ - __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ - __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ - __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ - __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ -} CMP_Type; - -/* ---------------------------------------------------------------------------- - -- CMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Register_Masks CMP Register Masks - * @{ - */ - -/*! @name CR0 - CMP Control Register 0 */ -#define CMP_CR0_HYSTCTR_MASK (0x3U) -#define CMP_CR0_HYSTCTR_SHIFT (0U) -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) -#define CMP_CR0_FILTER_CNT_MASK (0x70U) -#define CMP_CR0_FILTER_CNT_SHIFT (4U) -#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) - -/*! @name CR1 - CMP Control Register 1 */ -#define CMP_CR1_EN_MASK (0x1U) -#define CMP_CR1_EN_SHIFT (0U) -#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) -#define CMP_CR1_OPE_MASK (0x2U) -#define CMP_CR1_OPE_SHIFT (1U) -#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) -#define CMP_CR1_COS_MASK (0x4U) -#define CMP_CR1_COS_SHIFT (2U) -#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) -#define CMP_CR1_INV_MASK (0x8U) -#define CMP_CR1_INV_SHIFT (3U) -#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) -#define CMP_CR1_PMODE_MASK (0x10U) -#define CMP_CR1_PMODE_SHIFT (4U) -#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) -#define CMP_CR1_WE_MASK (0x40U) -#define CMP_CR1_WE_SHIFT (6U) -#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) -#define CMP_CR1_SE_MASK (0x80U) -#define CMP_CR1_SE_SHIFT (7U) -#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) - -/*! @name FPR - CMP Filter Period Register */ -#define CMP_FPR_FILT_PER_MASK (0xFFU) -#define CMP_FPR_FILT_PER_SHIFT (0U) -#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) - -/*! @name SCR - CMP Status and Control Register */ -#define CMP_SCR_COUT_MASK (0x1U) -#define CMP_SCR_COUT_SHIFT (0U) -#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) -#define CMP_SCR_CFF_MASK (0x2U) -#define CMP_SCR_CFF_SHIFT (1U) -#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) -#define CMP_SCR_CFR_MASK (0x4U) -#define CMP_SCR_CFR_SHIFT (2U) -#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) -#define CMP_SCR_IEF_MASK (0x8U) -#define CMP_SCR_IEF_SHIFT (3U) -#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) -#define CMP_SCR_IER_MASK (0x10U) -#define CMP_SCR_IER_SHIFT (4U) -#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) -#define CMP_SCR_DMAEN_MASK (0x40U) -#define CMP_SCR_DMAEN_SHIFT (6U) -#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) - -/*! @name DACCR - DAC Control Register */ -#define CMP_DACCR_VOSEL_MASK (0x3FU) -#define CMP_DACCR_VOSEL_SHIFT (0U) -#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) -#define CMP_DACCR_VRSEL_MASK (0x40U) -#define CMP_DACCR_VRSEL_SHIFT (6U) -#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) -#define CMP_DACCR_DACEN_MASK (0x80U) -#define CMP_DACCR_DACEN_SHIFT (7U) -#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) - -/*! @name MUXCR - MUX Control Register */ -#define CMP_MUXCR_MSEL_MASK (0x7U) -#define CMP_MUXCR_MSEL_SHIFT (0U) -#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) -#define CMP_MUXCR_PSEL_MASK (0x38U) -#define CMP_MUXCR_PSEL_SHIFT (3U) -#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) -#define CMP_MUXCR_PSTM_MASK (0x80U) -#define CMP_MUXCR_PSTM_SHIFT (7U) -#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) - - -/*! - * @} - */ /* end of group CMP_Register_Masks */ - - -/* CMP - Peripheral instance base addresses */ -/** Peripheral CMP0 base address */ -#define CMP0_BASE (0x40073000u) -/** Peripheral CMP0 base pointer */ -#define CMP0 ((CMP_Type *)CMP0_BASE) -/** Peripheral CMP1 base address */ -#define CMP1_BASE (0x40073008u) -/** Peripheral CMP1 base pointer */ -#define CMP1 ((CMP_Type *)CMP1_BASE) -/** Array initializer of CMP peripheral base addresses */ -#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } -/** Array initializer of CMP peripheral base pointers */ -#define CMP_BASE_PTRS { CMP0, CMP1 } -/** Interrupt vectors for the CMP peripheral type */ -#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn } - -/*! - * @} - */ /* end of group CMP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CMT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer - * @{ - */ - -/** CMT - Register Layout Typedef */ -typedef struct { - __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ - __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ - __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ - __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ - __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ - __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ - __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ - __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ - __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ - __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ - __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ - __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */ -} CMT_Type; - -/* ---------------------------------------------------------------------------- - -- CMT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMT_Register_Masks CMT Register Masks - * @{ - */ - -/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ -#define CMT_CGH1_PH_MASK (0xFFU) -#define CMT_CGH1_PH_SHIFT (0U) -#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) - -/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ -#define CMT_CGL1_PL_MASK (0xFFU) -#define CMT_CGL1_PL_SHIFT (0U) -#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) - -/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ -#define CMT_CGH2_SH_MASK (0xFFU) -#define CMT_CGH2_SH_SHIFT (0U) -#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) - -/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ -#define CMT_CGL2_SL_MASK (0xFFU) -#define CMT_CGL2_SL_SHIFT (0U) -#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) - -/*! @name OC - CMT Output Control Register */ -#define CMT_OC_IROPEN_MASK (0x20U) -#define CMT_OC_IROPEN_SHIFT (5U) -#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) -#define CMT_OC_CMTPOL_MASK (0x40U) -#define CMT_OC_CMTPOL_SHIFT (6U) -#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) -#define CMT_OC_IROL_MASK (0x80U) -#define CMT_OC_IROL_SHIFT (7U) -#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) - -/*! @name MSC - CMT Modulator Status and Control Register */ -#define CMT_MSC_MCGEN_MASK (0x1U) -#define CMT_MSC_MCGEN_SHIFT (0U) -#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) -#define CMT_MSC_EOCIE_MASK (0x2U) -#define CMT_MSC_EOCIE_SHIFT (1U) -#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) -#define CMT_MSC_FSK_MASK (0x4U) -#define CMT_MSC_FSK_SHIFT (2U) -#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) -#define CMT_MSC_BASE_MASK (0x8U) -#define CMT_MSC_BASE_SHIFT (3U) -#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) -#define CMT_MSC_EXSPC_MASK (0x10U) -#define CMT_MSC_EXSPC_SHIFT (4U) -#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) -#define CMT_MSC_CMTDIV_MASK (0x60U) -#define CMT_MSC_CMTDIV_SHIFT (5U) -#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) -#define CMT_MSC_EOCF_MASK (0x80U) -#define CMT_MSC_EOCF_SHIFT (7U) -#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) - -/*! @name CMD1 - CMT Modulator Data Register Mark High */ -#define CMT_CMD1_MB_MASK (0xFFU) -#define CMT_CMD1_MB_SHIFT (0U) -#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) - -/*! @name CMD2 - CMT Modulator Data Register Mark Low */ -#define CMT_CMD2_MB_MASK (0xFFU) -#define CMT_CMD2_MB_SHIFT (0U) -#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) - -/*! @name CMD3 - CMT Modulator Data Register Space High */ -#define CMT_CMD3_SB_MASK (0xFFU) -#define CMT_CMD3_SB_SHIFT (0U) -#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) - -/*! @name CMD4 - CMT Modulator Data Register Space Low */ -#define CMT_CMD4_SB_MASK (0xFFU) -#define CMT_CMD4_SB_SHIFT (0U) -#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) - -/*! @name PPS - CMT Primary Prescaler Register */ -#define CMT_PPS_PPSDIV_MASK (0xFU) -#define CMT_PPS_PPSDIV_SHIFT (0U) -#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) - -/*! @name DMA - CMT Direct Memory Access Register */ -#define CMT_DMA_DMA_MASK (0x1U) -#define CMT_DMA_DMA_SHIFT (0U) -#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) - - -/*! - * @} - */ /* end of group CMT_Register_Masks */ - - -/* CMT - Peripheral instance base addresses */ -/** Peripheral CMT base address */ -#define CMT_BASE (0x40062000u) -/** Peripheral CMT base pointer */ -#define CMT ((CMT_Type *)CMT_BASE) -/** Array initializer of CMT peripheral base addresses */ -#define CMT_BASE_ADDRS { CMT_BASE } -/** Array initializer of CMT peripheral base pointers */ -#define CMT_BASE_PTRS { CMT } -/** Interrupt vectors for the CMT peripheral type */ -#define CMT_IRQS { CMT_IRQn } - -/*! - * @} - */ /* end of group CMT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - union { /* offset: 0x0 */ - struct { /* offset: 0x0 */ - __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ - __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ - } ACCESS16BIT; - __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ - struct { /* offset: 0x0 */ - __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ - __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ - __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ - __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ - } ACCESS8BIT; - }; - union { /* offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ - __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ - } GPOLY_ACCESS16BIT; - __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ - __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ - __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ - __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ - } GPOLY_ACCESS8BIT; - }; - union { /* offset: 0x8 */ - __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ - struct { /* offset: 0x8 */ - uint8_t RESERVED_0[3]; - __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ - } CTRL_ACCESS8BIT; - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name DATAL - CRC_DATAL register. */ -#define CRC_DATAL_DATAL_MASK (0xFFFFU) -#define CRC_DATAL_DATAL_SHIFT (0U) -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) - -/*! @name DATAH - CRC_DATAH register. */ -#define CRC_DATAH_DATAH_MASK (0xFFFFU) -#define CRC_DATAH_DATAH_SHIFT (0U) -#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) - -/*! @name DATA - CRC Data register */ -#define CRC_DATA_LL_MASK (0xFFU) -#define CRC_DATA_LL_SHIFT (0U) -#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) -#define CRC_DATA_LU_MASK (0xFF00U) -#define CRC_DATA_LU_SHIFT (8U) -#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) -#define CRC_DATA_HL_MASK (0xFF0000U) -#define CRC_DATA_HL_SHIFT (16U) -#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) -#define CRC_DATA_HU_MASK (0xFF000000U) -#define CRC_DATA_HU_SHIFT (24U) -#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) - -/*! @name DATALL - CRC_DATALL register. */ -#define CRC_DATALL_DATALL_MASK (0xFFU) -#define CRC_DATALL_DATALL_SHIFT (0U) -#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) - -/*! @name DATALU - CRC_DATALU register. */ -#define CRC_DATALU_DATALU_MASK (0xFFU) -#define CRC_DATALU_DATALU_SHIFT (0U) -#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) - -/*! @name DATAHL - CRC_DATAHL register. */ -#define CRC_DATAHL_DATAHL_MASK (0xFFU) -#define CRC_DATAHL_DATAHL_SHIFT (0U) -#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) - -/*! @name DATAHU - CRC_DATAHU register. */ -#define CRC_DATAHU_DATAHU_MASK (0xFFU) -#define CRC_DATAHU_DATAHU_SHIFT (0U) -#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) - -/*! @name GPOLYL - CRC_GPOLYL register. */ -#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) -#define CRC_GPOLYL_GPOLYL_SHIFT (0U) -#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) - -/*! @name GPOLYH - CRC_GPOLYH register. */ -#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) -#define CRC_GPOLYH_GPOLYH_SHIFT (0U) -#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) - -/*! @name GPOLY - CRC Polynomial register */ -#define CRC_GPOLY_LOW_MASK (0xFFFFU) -#define CRC_GPOLY_LOW_SHIFT (0U) -#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) -#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) -#define CRC_GPOLY_HIGH_SHIFT (16U) -#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) - -/*! @name GPOLYLL - CRC_GPOLYLL register. */ -#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) -#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) -#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) - -/*! @name GPOLYLU - CRC_GPOLYLU register. */ -#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) -#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) -#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) - -/*! @name GPOLYHL - CRC_GPOLYHL register. */ -#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) -#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) -#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) - -/*! @name GPOLYHU - CRC_GPOLYHU register. */ -#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) -#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) -#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) - -/*! @name CTRL - CRC Control register */ -#define CRC_CTRL_TCRC_MASK (0x1000000U) -#define CRC_CTRL_TCRC_SHIFT (24U) -#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) -#define CRC_CTRL_WAS_MASK (0x2000000U) -#define CRC_CTRL_WAS_SHIFT (25U) -#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) -#define CRC_CTRL_FXOR_MASK (0x4000000U) -#define CRC_CTRL_FXOR_SHIFT (26U) -#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) -#define CRC_CTRL_TOTR_MASK (0x30000000U) -#define CRC_CTRL_TOTR_SHIFT (28U) -#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) -#define CRC_CTRL_TOT_MASK (0xC0000000U) -#define CRC_CTRL_TOT_SHIFT (30U) -#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) - -/*! @name CTRLHU - CRC_CTRLHU register. */ -#define CRC_CTRLHU_TCRC_MASK (0x1U) -#define CRC_CTRLHU_TCRC_SHIFT (0U) -#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) -#define CRC_CTRLHU_WAS_MASK (0x2U) -#define CRC_CTRLHU_WAS_SHIFT (1U) -#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) -#define CRC_CTRLHU_FXOR_MASK (0x4U) -#define CRC_CTRLHU_FXOR_SHIFT (2U) -#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) -#define CRC_CTRLHU_TOTR_MASK (0x30U) -#define CRC_CTRLHU_TOTR_SHIFT (4U) -#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) -#define CRC_CTRLHU_TOT_MASK (0xC0U) -#define CRC_CTRLHU_TOT_SHIFT (6U) -#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -/** Peripheral CRC base address */ -#define CRC_BASE (0x40032000u) -/** Peripheral CRC base pointer */ -#define CRC0 ((CRC_Type *)CRC_BASE) -/** Array initializer of CRC peripheral base addresses */ -#define CRC_BASE_ADDRS { CRC_BASE } -/** Array initializer of CRC peripheral base pointers */ -#define CRC_BASE_PTRS { CRC0 } - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< Control Register, offset: 0x0 */ - __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ - uint8_t RESERVED_1[4]; - __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ - __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ - __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ - __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ - __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ - __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ - __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ - __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ - __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ - uint8_t RESERVED_2[4]; - __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ - uint8_t RESERVED_4[4]; - __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ - uint8_t RESERVED_5[200]; - __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ - __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ - __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ - __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ - __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ - __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ - __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ - __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ - __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ - __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ - __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ - __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ - __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ - __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ - __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ - __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ - uint8_t RESERVED_6[3824]; - struct { /* offset: 0x1000, array step: 0x20 */ - __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ - __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ - __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ - union { /* offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ - }; - __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ - __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ - __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ - union { /* offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ - }; - __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ - __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ - union { /* offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ - }; - } TCD[16]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CR - Control Register */ -#define DMA_CR_EDBG_MASK (0x2U) -#define DMA_CR_EDBG_SHIFT (1U) -#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) -#define DMA_CR_ERCA_MASK (0x4U) -#define DMA_CR_ERCA_SHIFT (2U) -#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) -#define DMA_CR_HOE_MASK (0x10U) -#define DMA_CR_HOE_SHIFT (4U) -#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) -#define DMA_CR_HALT_MASK (0x20U) -#define DMA_CR_HALT_SHIFT (5U) -#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) -#define DMA_CR_CLM_MASK (0x40U) -#define DMA_CR_CLM_SHIFT (6U) -#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) -#define DMA_CR_EMLM_MASK (0x80U) -#define DMA_CR_EMLM_SHIFT (7U) -#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) -#define DMA_CR_ECX_MASK (0x10000U) -#define DMA_CR_ECX_SHIFT (16U) -#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) -#define DMA_CR_CX_MASK (0x20000U) -#define DMA_CR_CX_SHIFT (17U) -#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) - -/*! @name ES - Error Status Register */ -#define DMA_ES_DBE_MASK (0x1U) -#define DMA_ES_DBE_SHIFT (0U) -#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) -#define DMA_ES_SBE_MASK (0x2U) -#define DMA_ES_SBE_SHIFT (1U) -#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) -#define DMA_ES_SGE_MASK (0x4U) -#define DMA_ES_SGE_SHIFT (2U) -#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) -#define DMA_ES_NCE_MASK (0x8U) -#define DMA_ES_NCE_SHIFT (3U) -#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) -#define DMA_ES_DOE_MASK (0x10U) -#define DMA_ES_DOE_SHIFT (4U) -#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) -#define DMA_ES_DAE_MASK (0x20U) -#define DMA_ES_DAE_SHIFT (5U) -#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) -#define DMA_ES_SOE_MASK (0x40U) -#define DMA_ES_SOE_SHIFT (6U) -#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) -#define DMA_ES_SAE_MASK (0x80U) -#define DMA_ES_SAE_SHIFT (7U) -#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) -#define DMA_ES_ERRCHN_MASK (0xF00U) -#define DMA_ES_ERRCHN_SHIFT (8U) -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) -#define DMA_ES_CPE_MASK (0x4000U) -#define DMA_ES_CPE_SHIFT (14U) -#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) -#define DMA_ES_ECX_MASK (0x10000U) -#define DMA_ES_ECX_SHIFT (16U) -#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) -#define DMA_ES_VLD_MASK (0x80000000U) -#define DMA_ES_VLD_SHIFT (31U) -#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) - -/*! @name ERQ - Enable Request Register */ -#define DMA_ERQ_ERQ0_MASK (0x1U) -#define DMA_ERQ_ERQ0_SHIFT (0U) -#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) -#define DMA_ERQ_ERQ1_MASK (0x2U) -#define DMA_ERQ_ERQ1_SHIFT (1U) -#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) -#define DMA_ERQ_ERQ2_MASK (0x4U) -#define DMA_ERQ_ERQ2_SHIFT (2U) -#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) -#define DMA_ERQ_ERQ3_MASK (0x8U) -#define DMA_ERQ_ERQ3_SHIFT (3U) -#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) -#define DMA_ERQ_ERQ4_MASK (0x10U) -#define DMA_ERQ_ERQ4_SHIFT (4U) -#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) -#define DMA_ERQ_ERQ5_MASK (0x20U) -#define DMA_ERQ_ERQ5_SHIFT (5U) -#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) -#define DMA_ERQ_ERQ6_MASK (0x40U) -#define DMA_ERQ_ERQ6_SHIFT (6U) -#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) -#define DMA_ERQ_ERQ7_MASK (0x80U) -#define DMA_ERQ_ERQ7_SHIFT (7U) -#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) -#define DMA_ERQ_ERQ8_MASK (0x100U) -#define DMA_ERQ_ERQ8_SHIFT (8U) -#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) -#define DMA_ERQ_ERQ9_MASK (0x200U) -#define DMA_ERQ_ERQ9_SHIFT (9U) -#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) -#define DMA_ERQ_ERQ10_MASK (0x400U) -#define DMA_ERQ_ERQ10_SHIFT (10U) -#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) -#define DMA_ERQ_ERQ11_MASK (0x800U) -#define DMA_ERQ_ERQ11_SHIFT (11U) -#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) -#define DMA_ERQ_ERQ12_MASK (0x1000U) -#define DMA_ERQ_ERQ12_SHIFT (12U) -#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) -#define DMA_ERQ_ERQ13_MASK (0x2000U) -#define DMA_ERQ_ERQ13_SHIFT (13U) -#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) -#define DMA_ERQ_ERQ14_MASK (0x4000U) -#define DMA_ERQ_ERQ14_SHIFT (14U) -#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) -#define DMA_ERQ_ERQ15_MASK (0x8000U) -#define DMA_ERQ_ERQ15_SHIFT (15U) -#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) - -/*! @name EEI - Enable Error Interrupt Register */ -#define DMA_EEI_EEI0_MASK (0x1U) -#define DMA_EEI_EEI0_SHIFT (0U) -#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) -#define DMA_EEI_EEI1_MASK (0x2U) -#define DMA_EEI_EEI1_SHIFT (1U) -#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) -#define DMA_EEI_EEI2_MASK (0x4U) -#define DMA_EEI_EEI2_SHIFT (2U) -#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) -#define DMA_EEI_EEI3_MASK (0x8U) -#define DMA_EEI_EEI3_SHIFT (3U) -#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) -#define DMA_EEI_EEI4_MASK (0x10U) -#define DMA_EEI_EEI4_SHIFT (4U) -#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) -#define DMA_EEI_EEI5_MASK (0x20U) -#define DMA_EEI_EEI5_SHIFT (5U) -#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) -#define DMA_EEI_EEI6_MASK (0x40U) -#define DMA_EEI_EEI6_SHIFT (6U) -#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) -#define DMA_EEI_EEI7_MASK (0x80U) -#define DMA_EEI_EEI7_SHIFT (7U) -#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) -#define DMA_EEI_EEI8_MASK (0x100U) -#define DMA_EEI_EEI8_SHIFT (8U) -#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) -#define DMA_EEI_EEI9_MASK (0x200U) -#define DMA_EEI_EEI9_SHIFT (9U) -#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) -#define DMA_EEI_EEI10_MASK (0x400U) -#define DMA_EEI_EEI10_SHIFT (10U) -#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) -#define DMA_EEI_EEI11_MASK (0x800U) -#define DMA_EEI_EEI11_SHIFT (11U) -#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) -#define DMA_EEI_EEI12_MASK (0x1000U) -#define DMA_EEI_EEI12_SHIFT (12U) -#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) -#define DMA_EEI_EEI13_MASK (0x2000U) -#define DMA_EEI_EEI13_SHIFT (13U) -#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) -#define DMA_EEI_EEI14_MASK (0x4000U) -#define DMA_EEI_EEI14_SHIFT (14U) -#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) -#define DMA_EEI_EEI15_MASK (0x8000U) -#define DMA_EEI_EEI15_SHIFT (15U) -#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) - -/*! @name CEEI - Clear Enable Error Interrupt Register */ -#define DMA_CEEI_CEEI_MASK (0xFU) -#define DMA_CEEI_CEEI_SHIFT (0U) -#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) -#define DMA_CEEI_CAEE_MASK (0x40U) -#define DMA_CEEI_CAEE_SHIFT (6U) -#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) -#define DMA_CEEI_NOP_MASK (0x80U) -#define DMA_CEEI_NOP_SHIFT (7U) -#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) - -/*! @name SEEI - Set Enable Error Interrupt Register */ -#define DMA_SEEI_SEEI_MASK (0xFU) -#define DMA_SEEI_SEEI_SHIFT (0U) -#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) -#define DMA_SEEI_SAEE_MASK (0x40U) -#define DMA_SEEI_SAEE_SHIFT (6U) -#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) -#define DMA_SEEI_NOP_MASK (0x80U) -#define DMA_SEEI_NOP_SHIFT (7U) -#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) - -/*! @name CERQ - Clear Enable Request Register */ -#define DMA_CERQ_CERQ_MASK (0xFU) -#define DMA_CERQ_CERQ_SHIFT (0U) -#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) -#define DMA_CERQ_CAER_MASK (0x40U) -#define DMA_CERQ_CAER_SHIFT (6U) -#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) -#define DMA_CERQ_NOP_MASK (0x80U) -#define DMA_CERQ_NOP_SHIFT (7U) -#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) - -/*! @name SERQ - Set Enable Request Register */ -#define DMA_SERQ_SERQ_MASK (0xFU) -#define DMA_SERQ_SERQ_SHIFT (0U) -#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) -#define DMA_SERQ_SAER_MASK (0x40U) -#define DMA_SERQ_SAER_SHIFT (6U) -#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) -#define DMA_SERQ_NOP_MASK (0x80U) -#define DMA_SERQ_NOP_SHIFT (7U) -#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) - -/*! @name CDNE - Clear DONE Status Bit Register */ -#define DMA_CDNE_CDNE_MASK (0xFU) -#define DMA_CDNE_CDNE_SHIFT (0U) -#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) -#define DMA_CDNE_CADN_MASK (0x40U) -#define DMA_CDNE_CADN_SHIFT (6U) -#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) -#define DMA_CDNE_NOP_MASK (0x80U) -#define DMA_CDNE_NOP_SHIFT (7U) -#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) - -/*! @name SSRT - Set START Bit Register */ -#define DMA_SSRT_SSRT_MASK (0xFU) -#define DMA_SSRT_SSRT_SHIFT (0U) -#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) -#define DMA_SSRT_SAST_MASK (0x40U) -#define DMA_SSRT_SAST_SHIFT (6U) -#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) -#define DMA_SSRT_NOP_MASK (0x80U) -#define DMA_SSRT_NOP_SHIFT (7U) -#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) - -/*! @name CERR - Clear Error Register */ -#define DMA_CERR_CERR_MASK (0xFU) -#define DMA_CERR_CERR_SHIFT (0U) -#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) -#define DMA_CERR_CAEI_MASK (0x40U) -#define DMA_CERR_CAEI_SHIFT (6U) -#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) -#define DMA_CERR_NOP_MASK (0x80U) -#define DMA_CERR_NOP_SHIFT (7U) -#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) - -/*! @name CINT - Clear Interrupt Request Register */ -#define DMA_CINT_CINT_MASK (0xFU) -#define DMA_CINT_CINT_SHIFT (0U) -#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) -#define DMA_CINT_CAIR_MASK (0x40U) -#define DMA_CINT_CAIR_SHIFT (6U) -#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) -#define DMA_CINT_NOP_MASK (0x80U) -#define DMA_CINT_NOP_SHIFT (7U) -#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) - -/*! @name INT - Interrupt Request Register */ -#define DMA_INT_INT0_MASK (0x1U) -#define DMA_INT_INT0_SHIFT (0U) -#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) -#define DMA_INT_INT1_MASK (0x2U) -#define DMA_INT_INT1_SHIFT (1U) -#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) -#define DMA_INT_INT2_MASK (0x4U) -#define DMA_INT_INT2_SHIFT (2U) -#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) -#define DMA_INT_INT3_MASK (0x8U) -#define DMA_INT_INT3_SHIFT (3U) -#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) -#define DMA_INT_INT4_MASK (0x10U) -#define DMA_INT_INT4_SHIFT (4U) -#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) -#define DMA_INT_INT5_MASK (0x20U) -#define DMA_INT_INT5_SHIFT (5U) -#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) -#define DMA_INT_INT6_MASK (0x40U) -#define DMA_INT_INT6_SHIFT (6U) -#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) -#define DMA_INT_INT7_MASK (0x80U) -#define DMA_INT_INT7_SHIFT (7U) -#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) -#define DMA_INT_INT8_MASK (0x100U) -#define DMA_INT_INT8_SHIFT (8U) -#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) -#define DMA_INT_INT9_MASK (0x200U) -#define DMA_INT_INT9_SHIFT (9U) -#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) -#define DMA_INT_INT10_MASK (0x400U) -#define DMA_INT_INT10_SHIFT (10U) -#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) -#define DMA_INT_INT11_MASK (0x800U) -#define DMA_INT_INT11_SHIFT (11U) -#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) -#define DMA_INT_INT12_MASK (0x1000U) -#define DMA_INT_INT12_SHIFT (12U) -#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) -#define DMA_INT_INT13_MASK (0x2000U) -#define DMA_INT_INT13_SHIFT (13U) -#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) -#define DMA_INT_INT14_MASK (0x4000U) -#define DMA_INT_INT14_SHIFT (14U) -#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) -#define DMA_INT_INT15_MASK (0x8000U) -#define DMA_INT_INT15_SHIFT (15U) -#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) - -/*! @name ERR - Error Register */ -#define DMA_ERR_ERR0_MASK (0x1U) -#define DMA_ERR_ERR0_SHIFT (0U) -#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) -#define DMA_ERR_ERR1_MASK (0x2U) -#define DMA_ERR_ERR1_SHIFT (1U) -#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) -#define DMA_ERR_ERR2_MASK (0x4U) -#define DMA_ERR_ERR2_SHIFT (2U) -#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) -#define DMA_ERR_ERR3_MASK (0x8U) -#define DMA_ERR_ERR3_SHIFT (3U) -#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) -#define DMA_ERR_ERR4_MASK (0x10U) -#define DMA_ERR_ERR4_SHIFT (4U) -#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) -#define DMA_ERR_ERR5_MASK (0x20U) -#define DMA_ERR_ERR5_SHIFT (5U) -#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) -#define DMA_ERR_ERR6_MASK (0x40U) -#define DMA_ERR_ERR6_SHIFT (6U) -#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) -#define DMA_ERR_ERR7_MASK (0x80U) -#define DMA_ERR_ERR7_SHIFT (7U) -#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) -#define DMA_ERR_ERR8_MASK (0x100U) -#define DMA_ERR_ERR8_SHIFT (8U) -#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) -#define DMA_ERR_ERR9_MASK (0x200U) -#define DMA_ERR_ERR9_SHIFT (9U) -#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) -#define DMA_ERR_ERR10_MASK (0x400U) -#define DMA_ERR_ERR10_SHIFT (10U) -#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) -#define DMA_ERR_ERR11_MASK (0x800U) -#define DMA_ERR_ERR11_SHIFT (11U) -#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) -#define DMA_ERR_ERR12_MASK (0x1000U) -#define DMA_ERR_ERR12_SHIFT (12U) -#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) -#define DMA_ERR_ERR13_MASK (0x2000U) -#define DMA_ERR_ERR13_SHIFT (13U) -#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) -#define DMA_ERR_ERR14_MASK (0x4000U) -#define DMA_ERR_ERR14_SHIFT (14U) -#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) -#define DMA_ERR_ERR15_MASK (0x8000U) -#define DMA_ERR_ERR15_SHIFT (15U) -#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) - -/*! @name HRS - Hardware Request Status Register */ -#define DMA_HRS_HRS0_MASK (0x1U) -#define DMA_HRS_HRS0_SHIFT (0U) -#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) -#define DMA_HRS_HRS1_MASK (0x2U) -#define DMA_HRS_HRS1_SHIFT (1U) -#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) -#define DMA_HRS_HRS2_MASK (0x4U) -#define DMA_HRS_HRS2_SHIFT (2U) -#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) -#define DMA_HRS_HRS3_MASK (0x8U) -#define DMA_HRS_HRS3_SHIFT (3U) -#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) -#define DMA_HRS_HRS4_MASK (0x10U) -#define DMA_HRS_HRS4_SHIFT (4U) -#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) -#define DMA_HRS_HRS5_MASK (0x20U) -#define DMA_HRS_HRS5_SHIFT (5U) -#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) -#define DMA_HRS_HRS6_MASK (0x40U) -#define DMA_HRS_HRS6_SHIFT (6U) -#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) -#define DMA_HRS_HRS7_MASK (0x80U) -#define DMA_HRS_HRS7_SHIFT (7U) -#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) -#define DMA_HRS_HRS8_MASK (0x100U) -#define DMA_HRS_HRS8_SHIFT (8U) -#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) -#define DMA_HRS_HRS9_MASK (0x200U) -#define DMA_HRS_HRS9_SHIFT (9U) -#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) -#define DMA_HRS_HRS10_MASK (0x400U) -#define DMA_HRS_HRS10_SHIFT (10U) -#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) -#define DMA_HRS_HRS11_MASK (0x800U) -#define DMA_HRS_HRS11_SHIFT (11U) -#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) -#define DMA_HRS_HRS12_MASK (0x1000U) -#define DMA_HRS_HRS12_SHIFT (12U) -#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) -#define DMA_HRS_HRS13_MASK (0x2000U) -#define DMA_HRS_HRS13_SHIFT (13U) -#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) -#define DMA_HRS_HRS14_MASK (0x4000U) -#define DMA_HRS_HRS14_SHIFT (14U) -#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) -#define DMA_HRS_HRS15_MASK (0x8000U) -#define DMA_HRS_HRS15_SHIFT (15U) -#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) - -/*! @name DCHPRI3 - Channel n Priority Register */ -#define DMA_DCHPRI3_CHPRI_MASK (0xFU) -#define DMA_DCHPRI3_CHPRI_SHIFT (0U) -#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) -#define DMA_DCHPRI3_DPA_MASK (0x40U) -#define DMA_DCHPRI3_DPA_SHIFT (6U) -#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) -#define DMA_DCHPRI3_ECP_MASK (0x80U) -#define DMA_DCHPRI3_ECP_SHIFT (7U) -#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) - -/*! @name DCHPRI2 - Channel n Priority Register */ -#define DMA_DCHPRI2_CHPRI_MASK (0xFU) -#define DMA_DCHPRI2_CHPRI_SHIFT (0U) -#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) -#define DMA_DCHPRI2_DPA_MASK (0x40U) -#define DMA_DCHPRI2_DPA_SHIFT (6U) -#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) -#define DMA_DCHPRI2_ECP_MASK (0x80U) -#define DMA_DCHPRI2_ECP_SHIFT (7U) -#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) - -/*! @name DCHPRI1 - Channel n Priority Register */ -#define DMA_DCHPRI1_CHPRI_MASK (0xFU) -#define DMA_DCHPRI1_CHPRI_SHIFT (0U) -#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) -#define DMA_DCHPRI1_DPA_MASK (0x40U) -#define DMA_DCHPRI1_DPA_SHIFT (6U) -#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) -#define DMA_DCHPRI1_ECP_MASK (0x80U) -#define DMA_DCHPRI1_ECP_SHIFT (7U) -#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) - -/*! @name DCHPRI0 - Channel n Priority Register */ -#define DMA_DCHPRI0_CHPRI_MASK (0xFU) -#define DMA_DCHPRI0_CHPRI_SHIFT (0U) -#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) -#define DMA_DCHPRI0_DPA_MASK (0x40U) -#define DMA_DCHPRI0_DPA_SHIFT (6U) -#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) -#define DMA_DCHPRI0_ECP_MASK (0x80U) -#define DMA_DCHPRI0_ECP_SHIFT (7U) -#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) - -/*! @name DCHPRI7 - Channel n Priority Register */ -#define DMA_DCHPRI7_CHPRI_MASK (0xFU) -#define DMA_DCHPRI7_CHPRI_SHIFT (0U) -#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) -#define DMA_DCHPRI7_DPA_MASK (0x40U) -#define DMA_DCHPRI7_DPA_SHIFT (6U) -#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) -#define DMA_DCHPRI7_ECP_MASK (0x80U) -#define DMA_DCHPRI7_ECP_SHIFT (7U) -#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) - -/*! @name DCHPRI6 - Channel n Priority Register */ -#define DMA_DCHPRI6_CHPRI_MASK (0xFU) -#define DMA_DCHPRI6_CHPRI_SHIFT (0U) -#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) -#define DMA_DCHPRI6_DPA_MASK (0x40U) -#define DMA_DCHPRI6_DPA_SHIFT (6U) -#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) -#define DMA_DCHPRI6_ECP_MASK (0x80U) -#define DMA_DCHPRI6_ECP_SHIFT (7U) -#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) - -/*! @name DCHPRI5 - Channel n Priority Register */ -#define DMA_DCHPRI5_CHPRI_MASK (0xFU) -#define DMA_DCHPRI5_CHPRI_SHIFT (0U) -#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) -#define DMA_DCHPRI5_DPA_MASK (0x40U) -#define DMA_DCHPRI5_DPA_SHIFT (6U) -#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) -#define DMA_DCHPRI5_ECP_MASK (0x80U) -#define DMA_DCHPRI5_ECP_SHIFT (7U) -#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) - -/*! @name DCHPRI4 - Channel n Priority Register */ -#define DMA_DCHPRI4_CHPRI_MASK (0xFU) -#define DMA_DCHPRI4_CHPRI_SHIFT (0U) -#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) -#define DMA_DCHPRI4_DPA_MASK (0x40U) -#define DMA_DCHPRI4_DPA_SHIFT (6U) -#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) -#define DMA_DCHPRI4_ECP_MASK (0x80U) -#define DMA_DCHPRI4_ECP_SHIFT (7U) -#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) - -/*! @name DCHPRI11 - Channel n Priority Register */ -#define DMA_DCHPRI11_CHPRI_MASK (0xFU) -#define DMA_DCHPRI11_CHPRI_SHIFT (0U) -#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) -#define DMA_DCHPRI11_DPA_MASK (0x40U) -#define DMA_DCHPRI11_DPA_SHIFT (6U) -#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) -#define DMA_DCHPRI11_ECP_MASK (0x80U) -#define DMA_DCHPRI11_ECP_SHIFT (7U) -#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) - -/*! @name DCHPRI10 - Channel n Priority Register */ -#define DMA_DCHPRI10_CHPRI_MASK (0xFU) -#define DMA_DCHPRI10_CHPRI_SHIFT (0U) -#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) -#define DMA_DCHPRI10_DPA_MASK (0x40U) -#define DMA_DCHPRI10_DPA_SHIFT (6U) -#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) -#define DMA_DCHPRI10_ECP_MASK (0x80U) -#define DMA_DCHPRI10_ECP_SHIFT (7U) -#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) - -/*! @name DCHPRI9 - Channel n Priority Register */ -#define DMA_DCHPRI9_CHPRI_MASK (0xFU) -#define DMA_DCHPRI9_CHPRI_SHIFT (0U) -#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) -#define DMA_DCHPRI9_DPA_MASK (0x40U) -#define DMA_DCHPRI9_DPA_SHIFT (6U) -#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) -#define DMA_DCHPRI9_ECP_MASK (0x80U) -#define DMA_DCHPRI9_ECP_SHIFT (7U) -#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) - -/*! @name DCHPRI8 - Channel n Priority Register */ -#define DMA_DCHPRI8_CHPRI_MASK (0xFU) -#define DMA_DCHPRI8_CHPRI_SHIFT (0U) -#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) -#define DMA_DCHPRI8_DPA_MASK (0x40U) -#define DMA_DCHPRI8_DPA_SHIFT (6U) -#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) -#define DMA_DCHPRI8_ECP_MASK (0x80U) -#define DMA_DCHPRI8_ECP_SHIFT (7U) -#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) - -/*! @name DCHPRI15 - Channel n Priority Register */ -#define DMA_DCHPRI15_CHPRI_MASK (0xFU) -#define DMA_DCHPRI15_CHPRI_SHIFT (0U) -#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) -#define DMA_DCHPRI15_DPA_MASK (0x40U) -#define DMA_DCHPRI15_DPA_SHIFT (6U) -#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) -#define DMA_DCHPRI15_ECP_MASK (0x80U) -#define DMA_DCHPRI15_ECP_SHIFT (7U) -#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) - -/*! @name DCHPRI14 - Channel n Priority Register */ -#define DMA_DCHPRI14_CHPRI_MASK (0xFU) -#define DMA_DCHPRI14_CHPRI_SHIFT (0U) -#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) -#define DMA_DCHPRI14_DPA_MASK (0x40U) -#define DMA_DCHPRI14_DPA_SHIFT (6U) -#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) -#define DMA_DCHPRI14_ECP_MASK (0x80U) -#define DMA_DCHPRI14_ECP_SHIFT (7U) -#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) - -/*! @name DCHPRI13 - Channel n Priority Register */ -#define DMA_DCHPRI13_CHPRI_MASK (0xFU) -#define DMA_DCHPRI13_CHPRI_SHIFT (0U) -#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) -#define DMA_DCHPRI13_DPA_MASK (0x40U) -#define DMA_DCHPRI13_DPA_SHIFT (6U) -#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) -#define DMA_DCHPRI13_ECP_MASK (0x80U) -#define DMA_DCHPRI13_ECP_SHIFT (7U) -#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) - -/*! @name DCHPRI12 - Channel n Priority Register */ -#define DMA_DCHPRI12_CHPRI_MASK (0xFU) -#define DMA_DCHPRI12_CHPRI_SHIFT (0U) -#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) -#define DMA_DCHPRI12_DPA_MASK (0x40U) -#define DMA_DCHPRI12_DPA_SHIFT (6U) -#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) -#define DMA_DCHPRI12_ECP_MASK (0x80U) -#define DMA_DCHPRI12_ECP_SHIFT (7U) -#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) - -/*! @name SADDR - TCD Source Address */ -#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) -#define DMA_SADDR_SADDR_SHIFT (0U) -#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) - -/* The count of DMA_SADDR */ -#define DMA_SADDR_COUNT (16U) - -/*! @name SOFF - TCD Signed Source Address Offset */ -#define DMA_SOFF_SOFF_MASK (0xFFFFU) -#define DMA_SOFF_SOFF_SHIFT (0U) -#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) - -/* The count of DMA_SOFF */ -#define DMA_SOFF_COUNT (16U) - -/*! @name ATTR - TCD Transfer Attributes */ -#define DMA_ATTR_DSIZE_MASK (0x7U) -#define DMA_ATTR_DSIZE_SHIFT (0U) -#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) -#define DMA_ATTR_DMOD_MASK (0xF8U) -#define DMA_ATTR_DMOD_SHIFT (3U) -#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) -#define DMA_ATTR_SSIZE_MASK (0x700U) -#define DMA_ATTR_SSIZE_SHIFT (8U) -#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) -#define DMA_ATTR_SMOD_MASK (0xF800U) -#define DMA_ATTR_SMOD_SHIFT (11U) -#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) - -/* The count of DMA_ATTR */ -#define DMA_ATTR_COUNT (16U) - -/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */ -#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) -#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) - -/* The count of DMA_NBYTES_MLNO */ -#define DMA_NBYTES_MLNO_COUNT (16U) - -/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ -#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) -#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) -#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) -#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) -#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) -#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) - -/* The count of DMA_NBYTES_MLOFFNO */ -#define DMA_NBYTES_MLOFFNO_COUNT (16U) - -/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ -#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) -#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) -#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) -#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) -#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) -#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) - -/* The count of DMA_NBYTES_MLOFFYES */ -#define DMA_NBYTES_MLOFFYES_COUNT (16U) - -/*! @name SLAST - TCD Last Source Address Adjustment */ -#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) -#define DMA_SLAST_SLAST_SHIFT (0U) -#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) - -/* The count of DMA_SLAST */ -#define DMA_SLAST_COUNT (16U) - -/*! @name DADDR - TCD Destination Address */ -#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) -#define DMA_DADDR_DADDR_SHIFT (0U) -#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) - -/* The count of DMA_DADDR */ -#define DMA_DADDR_COUNT (16U) - -/*! @name DOFF - TCD Signed Destination Address Offset */ -#define DMA_DOFF_DOFF_MASK (0xFFFFU) -#define DMA_DOFF_DOFF_SHIFT (0U) -#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) - -/* The count of DMA_DOFF */ -#define DMA_DOFF_COUNT (16U) - -/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ -#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) -#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) -#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) -#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) -#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) - -/* The count of DMA_CITER_ELINKNO */ -#define DMA_CITER_ELINKNO_COUNT (16U) - -/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ -#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) -#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) -#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) -#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U) -#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) -#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) -#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) -#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) - -/* The count of DMA_CITER_ELINKYES */ -#define DMA_CITER_ELINKYES_COUNT (16U) - -/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) -#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) -#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) - -/* The count of DMA_DLAST_SGA */ -#define DMA_DLAST_SGA_COUNT (16U) - -/*! @name CSR - TCD Control and Status */ -#define DMA_CSR_START_MASK (0x1U) -#define DMA_CSR_START_SHIFT (0U) -#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) -#define DMA_CSR_INTMAJOR_MASK (0x2U) -#define DMA_CSR_INTMAJOR_SHIFT (1U) -#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) -#define DMA_CSR_INTHALF_MASK (0x4U) -#define DMA_CSR_INTHALF_SHIFT (2U) -#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) -#define DMA_CSR_DREQ_MASK (0x8U) -#define DMA_CSR_DREQ_SHIFT (3U) -#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) -#define DMA_CSR_ESG_MASK (0x10U) -#define DMA_CSR_ESG_SHIFT (4U) -#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) -#define DMA_CSR_MAJORELINK_MASK (0x20U) -#define DMA_CSR_MAJORELINK_SHIFT (5U) -#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) -#define DMA_CSR_ACTIVE_MASK (0x40U) -#define DMA_CSR_ACTIVE_SHIFT (6U) -#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) -#define DMA_CSR_DONE_MASK (0x80U) -#define DMA_CSR_DONE_SHIFT (7U) -#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) -#define DMA_CSR_MAJORLINKCH_MASK (0xF00U) -#define DMA_CSR_MAJORLINKCH_SHIFT (8U) -#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) -#define DMA_CSR_BWC_MASK (0xC000U) -#define DMA_CSR_BWC_SHIFT (14U) -#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) - -/* The count of DMA_CSR */ -#define DMA_CSR_COUNT (16U) - -/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ -#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) -#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) -#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) -#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) -#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) - -/* The count of DMA_BITER_ELINKNO */ -#define DMA_BITER_ELINKNO_COUNT (16U) - -/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ -#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) -#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) -#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) -#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U) -#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) -#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) -#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) -#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) - -/* The count of DMA_BITER_ELINKYES */ -#define DMA_BITER_ELINKYES_COUNT (16U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA base address */ -#define DMA_BASE (0x40008000u) -/** Peripheral DMA base pointer */ -#define DMA0 ((DMA_Type *)DMA_BASE) -/** Array initializer of DMA peripheral base addresses */ -#define DMA_BASE_ADDRS { DMA_BASE } -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { DMA0 } -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } -#define DMA_ERROR_IRQS { DMA_Error_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer - * @{ - */ - -/** DMAMUX - Register Layout Typedef */ -typedef struct { - __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ -} DMAMUX_Type; - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/*! @name CHCFG - Channel Configuration register */ -#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) -#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) -#define DMAMUX_CHCFG_TRIG_MASK (0x40U) -#define DMAMUX_CHCFG_TRIG_SHIFT (6U) -#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) -#define DMAMUX_CHCFG_ENBL_MASK (0x80U) -#define DMAMUX_CHCFG_ENBL_SHIFT (7U) -#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) - -/* The count of DMAMUX_CHCFG */ -#define DMAMUX_CHCFG_COUNT (16U) - - -/*! - * @} - */ /* end of group DMAMUX_Register_Masks */ - - -/* DMAMUX - Peripheral instance base addresses */ -/** Peripheral DMAMUX base address */ -#define DMAMUX_BASE (0x40021000u) -/** Peripheral DMAMUX base pointer */ -#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) -/** Array initializer of DMAMUX peripheral base addresses */ -#define DMAMUX_BASE_ADDRS { DMAMUX_BASE } -/** Array initializer of DMAMUX peripheral base pointers */ -#define DMAMUX_BASE_PTRS { DMAMUX } - -/*! - * @} - */ /* end of group DMAMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EWM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer - * @{ - */ - -/** EWM - Register Layout Typedef */ -typedef struct { - __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ - __O uint8_t SERV; /**< Service Register, offset: 0x1 */ - __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ - __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ -} EWM_Type; - -/* ---------------------------------------------------------------------------- - -- EWM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Register_Masks EWM Register Masks - * @{ - */ - -/*! @name CTRL - Control Register */ -#define EWM_CTRL_EWMEN_MASK (0x1U) -#define EWM_CTRL_EWMEN_SHIFT (0U) -#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) -#define EWM_CTRL_ASSIN_MASK (0x2U) -#define EWM_CTRL_ASSIN_SHIFT (1U) -#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) -#define EWM_CTRL_INEN_MASK (0x4U) -#define EWM_CTRL_INEN_SHIFT (2U) -#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) -#define EWM_CTRL_INTEN_MASK (0x8U) -#define EWM_CTRL_INTEN_SHIFT (3U) -#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) - -/*! @name SERV - Service Register */ -#define EWM_SERV_SERVICE_MASK (0xFFU) -#define EWM_SERV_SERVICE_SHIFT (0U) -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) - -/*! @name CMPL - Compare Low Register */ -#define EWM_CMPL_COMPAREL_MASK (0xFFU) -#define EWM_CMPL_COMPAREL_SHIFT (0U) -#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) - -/*! @name CMPH - Compare High Register */ -#define EWM_CMPH_COMPAREH_MASK (0xFFU) -#define EWM_CMPH_COMPAREH_SHIFT (0U) -#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) - - -/*! - * @} - */ /* end of group EWM_Register_Masks */ - - -/* EWM - Peripheral instance base addresses */ -/** Peripheral EWM base address */ -#define EWM_BASE (0x40061000u) -/** Peripheral EWM base pointer */ -#define EWM ((EWM_Type *)EWM_BASE) -/** Array initializer of EWM peripheral base addresses */ -#define EWM_BASE_ADDRS { EWM_BASE } -/** Array initializer of EWM peripheral base pointers */ -#define EWM_BASE_PTRS { EWM } -/** Interrupt vectors for the EWM peripheral type */ -#define EWM_IRQS { WDOG_EWM_IRQn } - -/*! - * @} - */ /* end of group EWM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer - * @{ - */ - -/** FMC - Register Layout Typedef */ -typedef struct { - __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ - __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */ - __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */ - uint8_t RESERVED_0[244]; - __IO uint32_t TAGVD[4][2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x8, index2*0x4 */ - uint8_t RESERVED_1[224]; - struct { /* offset: 0x200, array step: index*0x10, index2*0x8 */ - __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x10, index2*0x8 */ - __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x10, index2*0x8 */ - } SET[4][2]; -} FMC_Type; - -/* ---------------------------------------------------------------------------- - -- FMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FMC_Register_Masks FMC Register Masks - * @{ - */ - -/*! @name PFAPR - Flash Access Protection Register */ -#define FMC_PFAPR_M0AP_MASK (0x3U) -#define FMC_PFAPR_M0AP_SHIFT (0U) -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK) -#define FMC_PFAPR_M1AP_MASK (0xCU) -#define FMC_PFAPR_M1AP_SHIFT (2U) -#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK) -#define FMC_PFAPR_M2AP_MASK (0x30U) -#define FMC_PFAPR_M2AP_SHIFT (4U) -#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK) -#define FMC_PFAPR_M3AP_MASK (0xC0U) -#define FMC_PFAPR_M3AP_SHIFT (6U) -#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK) -#define FMC_PFAPR_M4AP_MASK (0x300U) -#define FMC_PFAPR_M4AP_SHIFT (8U) -#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK) -#define FMC_PFAPR_M5AP_MASK (0xC00U) -#define FMC_PFAPR_M5AP_SHIFT (10U) -#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK) -#define FMC_PFAPR_M6AP_MASK (0x3000U) -#define FMC_PFAPR_M6AP_SHIFT (12U) -#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK) -#define FMC_PFAPR_M7AP_MASK (0xC000U) -#define FMC_PFAPR_M7AP_SHIFT (14U) -#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK) -#define FMC_PFAPR_M0PFD_MASK (0x10000U) -#define FMC_PFAPR_M0PFD_SHIFT (16U) -#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK) -#define FMC_PFAPR_M1PFD_MASK (0x20000U) -#define FMC_PFAPR_M1PFD_SHIFT (17U) -#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK) -#define FMC_PFAPR_M2PFD_MASK (0x40000U) -#define FMC_PFAPR_M2PFD_SHIFT (18U) -#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK) -#define FMC_PFAPR_M3PFD_MASK (0x80000U) -#define FMC_PFAPR_M3PFD_SHIFT (19U) -#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK) -#define FMC_PFAPR_M4PFD_MASK (0x100000U) -#define FMC_PFAPR_M4PFD_SHIFT (20U) -#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK) -#define FMC_PFAPR_M5PFD_MASK (0x200000U) -#define FMC_PFAPR_M5PFD_SHIFT (21U) -#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK) -#define FMC_PFAPR_M6PFD_MASK (0x400000U) -#define FMC_PFAPR_M6PFD_SHIFT (22U) -#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK) -#define FMC_PFAPR_M7PFD_MASK (0x800000U) -#define FMC_PFAPR_M7PFD_SHIFT (23U) -#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK) - -/*! @name PFB0CR - Flash Bank 0 Control Register */ -#define FMC_PFB0CR_B0SEBE_MASK (0x1U) -#define FMC_PFB0CR_B0SEBE_SHIFT (0U) -#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK) -#define FMC_PFB0CR_B0IPE_MASK (0x2U) -#define FMC_PFB0CR_B0IPE_SHIFT (1U) -#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK) -#define FMC_PFB0CR_B0DPE_MASK (0x4U) -#define FMC_PFB0CR_B0DPE_SHIFT (2U) -#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK) -#define FMC_PFB0CR_B0ICE_MASK (0x8U) -#define FMC_PFB0CR_B0ICE_SHIFT (3U) -#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK) -#define FMC_PFB0CR_B0DCE_MASK (0x10U) -#define FMC_PFB0CR_B0DCE_SHIFT (4U) -#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK) -#define FMC_PFB0CR_CRC_MASK (0xE0U) -#define FMC_PFB0CR_CRC_SHIFT (5U) -#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK) -#define FMC_PFB0CR_B0MW_MASK (0x60000U) -#define FMC_PFB0CR_B0MW_SHIFT (17U) -#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK) -#define FMC_PFB0CR_S_B_INV_MASK (0x80000U) -#define FMC_PFB0CR_S_B_INV_SHIFT (19U) -#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK) -#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U) -#define FMC_PFB0CR_CINV_WAY_SHIFT (20U) -#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK) -#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U) -#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U) -#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK) -#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U) -#define FMC_PFB0CR_B0RWSC_SHIFT (28U) -#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK) - -/*! @name PFB1CR - Flash Bank 1 Control Register */ -#define FMC_PFB1CR_B1SEBE_MASK (0x1U) -#define FMC_PFB1CR_B1SEBE_SHIFT (0U) -#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK) -#define FMC_PFB1CR_B1IPE_MASK (0x2U) -#define FMC_PFB1CR_B1IPE_SHIFT (1U) -#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK) -#define FMC_PFB1CR_B1DPE_MASK (0x4U) -#define FMC_PFB1CR_B1DPE_SHIFT (2U) -#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK) -#define FMC_PFB1CR_B1ICE_MASK (0x8U) -#define FMC_PFB1CR_B1ICE_SHIFT (3U) -#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK) -#define FMC_PFB1CR_B1DCE_MASK (0x10U) -#define FMC_PFB1CR_B1DCE_SHIFT (4U) -#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK) -#define FMC_PFB1CR_B1MW_MASK (0x60000U) -#define FMC_PFB1CR_B1MW_SHIFT (17U) -#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK) -#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U) -#define FMC_PFB1CR_B1RWSC_SHIFT (28U) -#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK) - -/*! @name TAGVD - Cache Tag Storage */ -#define FMC_TAGVD_valid_MASK (0x1U) -#define FMC_TAGVD_valid_SHIFT (0U) -#define FMC_TAGVD_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_valid_SHIFT)) & FMC_TAGVD_valid_MASK) -#define FMC_TAGVD_tag_MASK (0x7FFF0U) -#define FMC_TAGVD_tag_SHIFT (4U) -#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_tag_SHIFT)) & FMC_TAGVD_tag_MASK) - -/* The count of FMC_TAGVD */ -#define FMC_TAGVD_COUNT (4U) - -/* The count of FMC_TAGVD */ -#define FMC_TAGVD_COUNT2 (2U) - -/*! @name DATA_U - Cache Data Storage (upper word) */ -#define FMC_DATA_U_data_MASK (0xFFFFFFFFU) -#define FMC_DATA_U_data_SHIFT (0U) -#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK) - -/* The count of FMC_DATA_U */ -#define FMC_DATA_U_COUNT (4U) - -/* The count of FMC_DATA_U */ -#define FMC_DATA_U_COUNT2 (2U) - -/*! @name DATA_L - Cache Data Storage (lower word) */ -#define FMC_DATA_L_data_MASK (0xFFFFFFFFU) -#define FMC_DATA_L_data_SHIFT (0U) -#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK) - -/* The count of FMC_DATA_L */ -#define FMC_DATA_L_COUNT (4U) - -/* The count of FMC_DATA_L */ -#define FMC_DATA_L_COUNT2 (2U) - - -/*! - * @} - */ /* end of group FMC_Register_Masks */ - - -/* FMC - Peripheral instance base addresses */ -/** Peripheral FMC base address */ -#define FMC_BASE (0x4001F000u) -/** Peripheral FMC base pointer */ -#define FMC ((FMC_Type *)FMC_BASE) -/** Array initializer of FMC peripheral base addresses */ -#define FMC_BASE_ADDRS { FMC_BASE } -/** Array initializer of FMC peripheral base pointers */ -#define FMC_BASE_PTRS { FMC } - -/*! - * @} - */ /* end of group FMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FTFL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer - * @{ - */ - -/** FTFL - Register Layout Typedef */ -typedef struct { - __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ - __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ - __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ - __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ - __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ - __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ - __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ - __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ - __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ - __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ - __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ - __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ - __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ - __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ - __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ - __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ - __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ - __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ - __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ - __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ - uint8_t RESERVED_0[2]; - __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ - __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ -} FTFL_Type; - -/* ---------------------------------------------------------------------------- - -- FTFL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFL_Register_Masks FTFL Register Masks - * @{ - */ - -/*! @name FSTAT - Flash Status Register */ -#define FTFL_FSTAT_MGSTAT0_MASK (0x1U) -#define FTFL_FSTAT_MGSTAT0_SHIFT (0U) -#define FTFL_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_MGSTAT0_SHIFT)) & FTFL_FSTAT_MGSTAT0_MASK) -#define FTFL_FSTAT_FPVIOL_MASK (0x10U) -#define FTFL_FSTAT_FPVIOL_SHIFT (4U) -#define FTFL_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_FPVIOL_SHIFT)) & FTFL_FSTAT_FPVIOL_MASK) -#define FTFL_FSTAT_ACCERR_MASK (0x20U) -#define FTFL_FSTAT_ACCERR_SHIFT (5U) -#define FTFL_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_ACCERR_SHIFT)) & FTFL_FSTAT_ACCERR_MASK) -#define FTFL_FSTAT_RDCOLERR_MASK (0x40U) -#define FTFL_FSTAT_RDCOLERR_SHIFT (6U) -#define FTFL_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_RDCOLERR_SHIFT)) & FTFL_FSTAT_RDCOLERR_MASK) -#define FTFL_FSTAT_CCIF_MASK (0x80U) -#define FTFL_FSTAT_CCIF_SHIFT (7U) -#define FTFL_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_CCIF_SHIFT)) & FTFL_FSTAT_CCIF_MASK) - -/*! @name FCNFG - Flash Configuration Register */ -#define FTFL_FCNFG_EEERDY_MASK (0x1U) -#define FTFL_FCNFG_EEERDY_SHIFT (0U) -#define FTFL_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_EEERDY_SHIFT)) & FTFL_FCNFG_EEERDY_MASK) -#define FTFL_FCNFG_RAMRDY_MASK (0x2U) -#define FTFL_FCNFG_RAMRDY_SHIFT (1U) -#define FTFL_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RAMRDY_SHIFT)) & FTFL_FCNFG_RAMRDY_MASK) -#define FTFL_FCNFG_PFLSH_MASK (0x4U) -#define FTFL_FCNFG_PFLSH_SHIFT (2U) -#define FTFL_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_PFLSH_SHIFT)) & FTFL_FCNFG_PFLSH_MASK) -#define FTFL_FCNFG_SWAP_MASK (0x8U) -#define FTFL_FCNFG_SWAP_SHIFT (3U) -#define FTFL_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_SWAP_SHIFT)) & FTFL_FCNFG_SWAP_MASK) -#define FTFL_FCNFG_ERSSUSP_MASK (0x10U) -#define FTFL_FCNFG_ERSSUSP_SHIFT (4U) -#define FTFL_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSSUSP_SHIFT)) & FTFL_FCNFG_ERSSUSP_MASK) -#define FTFL_FCNFG_ERSAREQ_MASK (0x20U) -#define FTFL_FCNFG_ERSAREQ_SHIFT (5U) -#define FTFL_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSAREQ_SHIFT)) & FTFL_FCNFG_ERSAREQ_MASK) -#define FTFL_FCNFG_RDCOLLIE_MASK (0x40U) -#define FTFL_FCNFG_RDCOLLIE_SHIFT (6U) -#define FTFL_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RDCOLLIE_SHIFT)) & FTFL_FCNFG_RDCOLLIE_MASK) -#define FTFL_FCNFG_CCIE_MASK (0x80U) -#define FTFL_FCNFG_CCIE_SHIFT (7U) -#define FTFL_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_CCIE_SHIFT)) & FTFL_FCNFG_CCIE_MASK) - -/*! @name FSEC - Flash Security Register */ -#define FTFL_FSEC_SEC_MASK (0x3U) -#define FTFL_FSEC_SEC_SHIFT (0U) -#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_SEC_SHIFT)) & FTFL_FSEC_SEC_MASK) -#define FTFL_FSEC_FSLACC_MASK (0xCU) -#define FTFL_FSEC_FSLACC_SHIFT (2U) -#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_FSLACC_SHIFT)) & FTFL_FSEC_FSLACC_MASK) -#define FTFL_FSEC_MEEN_MASK (0x30U) -#define FTFL_FSEC_MEEN_SHIFT (4U) -#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_MEEN_SHIFT)) & FTFL_FSEC_MEEN_MASK) -#define FTFL_FSEC_KEYEN_MASK (0xC0U) -#define FTFL_FSEC_KEYEN_SHIFT (6U) -#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_KEYEN_SHIFT)) & FTFL_FSEC_KEYEN_MASK) - -/*! @name FOPT - Flash Option Register */ -#define FTFL_FOPT_OPT_MASK (0xFFU) -#define FTFL_FOPT_OPT_SHIFT (0U) -#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FOPT_OPT_SHIFT)) & FTFL_FOPT_OPT_MASK) - -/*! @name FCCOB3 - Flash Common Command Object Registers */ -#define FTFL_FCCOB3_CCOBn_MASK (0xFFU) -#define FTFL_FCCOB3_CCOBn_SHIFT (0U) -#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB3_CCOBn_SHIFT)) & FTFL_FCCOB3_CCOBn_MASK) - -/*! @name FCCOB2 - Flash Common Command Object Registers */ -#define FTFL_FCCOB2_CCOBn_MASK (0xFFU) -#define FTFL_FCCOB2_CCOBn_SHIFT (0U) -#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB2_CCOBn_SHIFT)) & FTFL_FCCOB2_CCOBn_MASK) - -/*! @name FCCOB1 - Flash Common Command Object Registers */ -#define FTFL_FCCOB1_CCOBn_MASK (0xFFU) -#define FTFL_FCCOB1_CCOBn_SHIFT (0U) -#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB1_CCOBn_SHIFT)) & FTFL_FCCOB1_CCOBn_MASK) - -/*! @name FCCOB0 - Flash Common Command Object Registers */ -#define FTFL_FCCOB0_CCOBn_MASK (0xFFU) -#define FTFL_FCCOB0_CCOBn_SHIFT (0U) -#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB0_CCOBn_SHIFT)) & FTFL_FCCOB0_CCOBn_MASK) - -/*! @name FCCOB7 - Flash Common Command Object Registers */ -#define FTFL_FCCOB7_CCOBn_MASK (0xFFU) -#define FTFL_FCCOB7_CCOBn_SHIFT (0U) -#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB7_CCOBn_SHIFT)) & FTFL_FCCOB7_CCOBn_MASK) - -/*! @name FCCOB6 - Flash Common Command Object Registers */ -#define FTFL_FCCOB6_CCOBn_MASK (0xFFU) -#define FTFL_FCCOB6_CCOBn_SHIFT (0U) -#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB6_CCOBn_SHIFT)) & FTFL_FCCOB6_CCOBn_MASK) - -/*! @name FCCOB5 - Flash Common Command Object Registers */ -#define FTFL_FCCOB5_CCOBn_MASK (0xFFU) -#define FTFL_FCCOB5_CCOBn_SHIFT (0U) -#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB5_CCOBn_SHIFT)) & FTFL_FCCOB5_CCOBn_MASK) - -/*! @name FCCOB4 - Flash Common Command Object Registers */ -#define FTFL_FCCOB4_CCOBn_MASK (0xFFU) -#define FTFL_FCCOB4_CCOBn_SHIFT (0U) -#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB4_CCOBn_SHIFT)) & FTFL_FCCOB4_CCOBn_MASK) - -/*! @name FCCOBB - Flash Common Command Object Registers */ -#define FTFL_FCCOBB_CCOBn_MASK (0xFFU) -#define FTFL_FCCOBB_CCOBn_SHIFT (0U) -#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBB_CCOBn_SHIFT)) & FTFL_FCCOBB_CCOBn_MASK) - -/*! @name FCCOBA - Flash Common Command Object Registers */ -#define FTFL_FCCOBA_CCOBn_MASK (0xFFU) -#define FTFL_FCCOBA_CCOBn_SHIFT (0U) -#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBA_CCOBn_SHIFT)) & FTFL_FCCOBA_CCOBn_MASK) - -/*! @name FCCOB9 - Flash Common Command Object Registers */ -#define FTFL_FCCOB9_CCOBn_MASK (0xFFU) -#define FTFL_FCCOB9_CCOBn_SHIFT (0U) -#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB9_CCOBn_SHIFT)) & FTFL_FCCOB9_CCOBn_MASK) - -/*! @name FCCOB8 - Flash Common Command Object Registers */ -#define FTFL_FCCOB8_CCOBn_MASK (0xFFU) -#define FTFL_FCCOB8_CCOBn_SHIFT (0U) -#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB8_CCOBn_SHIFT)) & FTFL_FCCOB8_CCOBn_MASK) - -/*! @name FPROT3 - Program Flash Protection Registers */ -#define FTFL_FPROT3_PROT_MASK (0xFFU) -#define FTFL_FPROT3_PROT_SHIFT (0U) -#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT3_PROT_SHIFT)) & FTFL_FPROT3_PROT_MASK) - -/*! @name FPROT2 - Program Flash Protection Registers */ -#define FTFL_FPROT2_PROT_MASK (0xFFU) -#define FTFL_FPROT2_PROT_SHIFT (0U) -#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT2_PROT_SHIFT)) & FTFL_FPROT2_PROT_MASK) - -/*! @name FPROT1 - Program Flash Protection Registers */ -#define FTFL_FPROT1_PROT_MASK (0xFFU) -#define FTFL_FPROT1_PROT_SHIFT (0U) -#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT1_PROT_SHIFT)) & FTFL_FPROT1_PROT_MASK) - -/*! @name FPROT0 - Program Flash Protection Registers */ -#define FTFL_FPROT0_PROT_MASK (0xFFU) -#define FTFL_FPROT0_PROT_SHIFT (0U) -#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT0_PROT_SHIFT)) & FTFL_FPROT0_PROT_MASK) - -/*! @name FEPROT - EEPROM Protection Register */ -#define FTFL_FEPROT_EPROT_MASK (0xFFU) -#define FTFL_FEPROT_EPROT_SHIFT (0U) -#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FEPROT_EPROT_SHIFT)) & FTFL_FEPROT_EPROT_MASK) - -/*! @name FDPROT - Data Flash Protection Register */ -#define FTFL_FDPROT_DPROT_MASK (0xFFU) -#define FTFL_FDPROT_DPROT_SHIFT (0U) -#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FDPROT_DPROT_SHIFT)) & FTFL_FDPROT_DPROT_MASK) - - -/*! - * @} - */ /* end of group FTFL_Register_Masks */ - - -/* FTFL - Peripheral instance base addresses */ -/** Peripheral FTFL base address */ -#define FTFL_BASE (0x40020000u) -/** Peripheral FTFL base pointer */ -#define FTFL ((FTFL_Type *)FTFL_BASE) -/** Array initializer of FTFL peripheral base addresses */ -#define FTFL_BASE_ADDRS { FTFL_BASE } -/** Array initializer of FTFL peripheral base pointers */ -#define FTFL_BASE_PTRS { FTFL } -/** Interrupt vectors for the FTFL peripheral type */ -#define FTFL_COMMAND_COMPLETE_IRQS { FTFL_IRQn } -#define FTFL_READ_COLLISION_IRQS { FTFL_Collision_IRQn } - -/*! - * @} - */ /* end of group FTFL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FTM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer - * @{ - */ - -/** FTM - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ - __IO uint32_t CNT; /**< Counter, offset: 0x4 */ - __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ - struct { /* offset: 0xC, array step: 0x8 */ - __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ - __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ - } CONTROLS[8]; - __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ - __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ - __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ - __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ - __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ - __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ - __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ - __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ - __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ - __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ - __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ - __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ - __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ - __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ - __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ - __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ - __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ - __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ - __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ - __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ -} FTM_Type; - -/* ---------------------------------------------------------------------------- - -- FTM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTM_Register_Masks FTM Register Masks - * @{ - */ - -/*! @name SC - Status And Control */ -#define FTM_SC_PS_MASK (0x7U) -#define FTM_SC_PS_SHIFT (0U) -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) -#define FTM_SC_CLKS_MASK (0x18U) -#define FTM_SC_CLKS_SHIFT (3U) -#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) -#define FTM_SC_CPWMS_MASK (0x20U) -#define FTM_SC_CPWMS_SHIFT (5U) -#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) -#define FTM_SC_TOIE_MASK (0x40U) -#define FTM_SC_TOIE_SHIFT (6U) -#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) -#define FTM_SC_TOF_MASK (0x80U) -#define FTM_SC_TOF_SHIFT (7U) -#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) - -/*! @name CNT - Counter */ -#define FTM_CNT_COUNT_MASK (0xFFFFU) -#define FTM_CNT_COUNT_SHIFT (0U) -#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) - -/*! @name MOD - Modulo */ -#define FTM_MOD_MOD_MASK (0xFFFFU) -#define FTM_MOD_MOD_SHIFT (0U) -#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) - -/*! @name CnSC - Channel (n) Status And Control */ -#define FTM_CnSC_DMA_MASK (0x1U) -#define FTM_CnSC_DMA_SHIFT (0U) -#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) -#define FTM_CnSC_ELSA_MASK (0x4U) -#define FTM_CnSC_ELSA_SHIFT (2U) -#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) -#define FTM_CnSC_ELSB_MASK (0x8U) -#define FTM_CnSC_ELSB_SHIFT (3U) -#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) -#define FTM_CnSC_MSA_MASK (0x10U) -#define FTM_CnSC_MSA_SHIFT (4U) -#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) -#define FTM_CnSC_MSB_MASK (0x20U) -#define FTM_CnSC_MSB_SHIFT (5U) -#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) -#define FTM_CnSC_CHIE_MASK (0x40U) -#define FTM_CnSC_CHIE_SHIFT (6U) -#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) -#define FTM_CnSC_CHF_MASK (0x80U) -#define FTM_CnSC_CHF_SHIFT (7U) -#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) - -/* The count of FTM_CnSC */ -#define FTM_CnSC_COUNT (8U) - -/*! @name CnV - Channel (n) Value */ -#define FTM_CnV_VAL_MASK (0xFFFFU) -#define FTM_CnV_VAL_SHIFT (0U) -#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) - -/* The count of FTM_CnV */ -#define FTM_CnV_COUNT (8U) - -/*! @name CNTIN - Counter Initial Value */ -#define FTM_CNTIN_INIT_MASK (0xFFFFU) -#define FTM_CNTIN_INIT_SHIFT (0U) -#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) - -/*! @name STATUS - Capture And Compare Status */ -#define FTM_STATUS_CH0F_MASK (0x1U) -#define FTM_STATUS_CH0F_SHIFT (0U) -#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) -#define FTM_STATUS_CH1F_MASK (0x2U) -#define FTM_STATUS_CH1F_SHIFT (1U) -#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) -#define FTM_STATUS_CH2F_MASK (0x4U) -#define FTM_STATUS_CH2F_SHIFT (2U) -#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) -#define FTM_STATUS_CH3F_MASK (0x8U) -#define FTM_STATUS_CH3F_SHIFT (3U) -#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) -#define FTM_STATUS_CH4F_MASK (0x10U) -#define FTM_STATUS_CH4F_SHIFT (4U) -#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) -#define FTM_STATUS_CH5F_MASK (0x20U) -#define FTM_STATUS_CH5F_SHIFT (5U) -#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) -#define FTM_STATUS_CH6F_MASK (0x40U) -#define FTM_STATUS_CH6F_SHIFT (6U) -#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) -#define FTM_STATUS_CH7F_MASK (0x80U) -#define FTM_STATUS_CH7F_SHIFT (7U) -#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) - -/*! @name MODE - Features Mode Selection */ -#define FTM_MODE_FTMEN_MASK (0x1U) -#define FTM_MODE_FTMEN_SHIFT (0U) -#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) -#define FTM_MODE_INIT_MASK (0x2U) -#define FTM_MODE_INIT_SHIFT (1U) -#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) -#define FTM_MODE_WPDIS_MASK (0x4U) -#define FTM_MODE_WPDIS_SHIFT (2U) -#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) -#define FTM_MODE_PWMSYNC_MASK (0x8U) -#define FTM_MODE_PWMSYNC_SHIFT (3U) -#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) -#define FTM_MODE_CAPTEST_MASK (0x10U) -#define FTM_MODE_CAPTEST_SHIFT (4U) -#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) -#define FTM_MODE_FAULTM_MASK (0x60U) -#define FTM_MODE_FAULTM_SHIFT (5U) -#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) -#define FTM_MODE_FAULTIE_MASK (0x80U) -#define FTM_MODE_FAULTIE_SHIFT (7U) -#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) - -/*! @name SYNC - Synchronization */ -#define FTM_SYNC_CNTMIN_MASK (0x1U) -#define FTM_SYNC_CNTMIN_SHIFT (0U) -#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) -#define FTM_SYNC_CNTMAX_MASK (0x2U) -#define FTM_SYNC_CNTMAX_SHIFT (1U) -#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) -#define FTM_SYNC_REINIT_MASK (0x4U) -#define FTM_SYNC_REINIT_SHIFT (2U) -#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) -#define FTM_SYNC_SYNCHOM_MASK (0x8U) -#define FTM_SYNC_SYNCHOM_SHIFT (3U) -#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) -#define FTM_SYNC_TRIG0_MASK (0x10U) -#define FTM_SYNC_TRIG0_SHIFT (4U) -#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) -#define FTM_SYNC_TRIG1_MASK (0x20U) -#define FTM_SYNC_TRIG1_SHIFT (5U) -#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) -#define FTM_SYNC_TRIG2_MASK (0x40U) -#define FTM_SYNC_TRIG2_SHIFT (6U) -#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) -#define FTM_SYNC_SWSYNC_MASK (0x80U) -#define FTM_SYNC_SWSYNC_SHIFT (7U) -#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) - -/*! @name OUTINIT - Initial State For Channels Output */ -#define FTM_OUTINIT_CH0OI_MASK (0x1U) -#define FTM_OUTINIT_CH0OI_SHIFT (0U) -#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) -#define FTM_OUTINIT_CH1OI_MASK (0x2U) -#define FTM_OUTINIT_CH1OI_SHIFT (1U) -#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) -#define FTM_OUTINIT_CH2OI_MASK (0x4U) -#define FTM_OUTINIT_CH2OI_SHIFT (2U) -#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) -#define FTM_OUTINIT_CH3OI_MASK (0x8U) -#define FTM_OUTINIT_CH3OI_SHIFT (3U) -#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) -#define FTM_OUTINIT_CH4OI_MASK (0x10U) -#define FTM_OUTINIT_CH4OI_SHIFT (4U) -#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) -#define FTM_OUTINIT_CH5OI_MASK (0x20U) -#define FTM_OUTINIT_CH5OI_SHIFT (5U) -#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) -#define FTM_OUTINIT_CH6OI_MASK (0x40U) -#define FTM_OUTINIT_CH6OI_SHIFT (6U) -#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) -#define FTM_OUTINIT_CH7OI_MASK (0x80U) -#define FTM_OUTINIT_CH7OI_SHIFT (7U) -#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) - -/*! @name OUTMASK - Output Mask */ -#define FTM_OUTMASK_CH0OM_MASK (0x1U) -#define FTM_OUTMASK_CH0OM_SHIFT (0U) -#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) -#define FTM_OUTMASK_CH1OM_MASK (0x2U) -#define FTM_OUTMASK_CH1OM_SHIFT (1U) -#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) -#define FTM_OUTMASK_CH2OM_MASK (0x4U) -#define FTM_OUTMASK_CH2OM_SHIFT (2U) -#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) -#define FTM_OUTMASK_CH3OM_MASK (0x8U) -#define FTM_OUTMASK_CH3OM_SHIFT (3U) -#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) -#define FTM_OUTMASK_CH4OM_MASK (0x10U) -#define FTM_OUTMASK_CH4OM_SHIFT (4U) -#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) -#define FTM_OUTMASK_CH5OM_MASK (0x20U) -#define FTM_OUTMASK_CH5OM_SHIFT (5U) -#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) -#define FTM_OUTMASK_CH6OM_MASK (0x40U) -#define FTM_OUTMASK_CH6OM_SHIFT (6U) -#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) -#define FTM_OUTMASK_CH7OM_MASK (0x80U) -#define FTM_OUTMASK_CH7OM_SHIFT (7U) -#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) - -/*! @name COMBINE - Function For Linked Channels */ -#define FTM_COMBINE_COMBINE0_MASK (0x1U) -#define FTM_COMBINE_COMBINE0_SHIFT (0U) -#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) -#define FTM_COMBINE_COMP0_MASK (0x2U) -#define FTM_COMBINE_COMP0_SHIFT (1U) -#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) -#define FTM_COMBINE_DECAPEN0_MASK (0x4U) -#define FTM_COMBINE_DECAPEN0_SHIFT (2U) -#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) -#define FTM_COMBINE_DECAP0_MASK (0x8U) -#define FTM_COMBINE_DECAP0_SHIFT (3U) -#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) -#define FTM_COMBINE_DTEN0_MASK (0x10U) -#define FTM_COMBINE_DTEN0_SHIFT (4U) -#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) -#define FTM_COMBINE_SYNCEN0_MASK (0x20U) -#define FTM_COMBINE_SYNCEN0_SHIFT (5U) -#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) -#define FTM_COMBINE_FAULTEN0_MASK (0x40U) -#define FTM_COMBINE_FAULTEN0_SHIFT (6U) -#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) -#define FTM_COMBINE_COMBINE1_MASK (0x100U) -#define FTM_COMBINE_COMBINE1_SHIFT (8U) -#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) -#define FTM_COMBINE_COMP1_MASK (0x200U) -#define FTM_COMBINE_COMP1_SHIFT (9U) -#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) -#define FTM_COMBINE_DECAPEN1_MASK (0x400U) -#define FTM_COMBINE_DECAPEN1_SHIFT (10U) -#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) -#define FTM_COMBINE_DECAP1_MASK (0x800U) -#define FTM_COMBINE_DECAP1_SHIFT (11U) -#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) -#define FTM_COMBINE_DTEN1_MASK (0x1000U) -#define FTM_COMBINE_DTEN1_SHIFT (12U) -#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) -#define FTM_COMBINE_SYNCEN1_MASK (0x2000U) -#define FTM_COMBINE_SYNCEN1_SHIFT (13U) -#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) -#define FTM_COMBINE_FAULTEN1_MASK (0x4000U) -#define FTM_COMBINE_FAULTEN1_SHIFT (14U) -#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) -#define FTM_COMBINE_COMBINE2_MASK (0x10000U) -#define FTM_COMBINE_COMBINE2_SHIFT (16U) -#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) -#define FTM_COMBINE_COMP2_MASK (0x20000U) -#define FTM_COMBINE_COMP2_SHIFT (17U) -#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) -#define FTM_COMBINE_DECAPEN2_MASK (0x40000U) -#define FTM_COMBINE_DECAPEN2_SHIFT (18U) -#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) -#define FTM_COMBINE_DECAP2_MASK (0x80000U) -#define FTM_COMBINE_DECAP2_SHIFT (19U) -#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) -#define FTM_COMBINE_DTEN2_MASK (0x100000U) -#define FTM_COMBINE_DTEN2_SHIFT (20U) -#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) -#define FTM_COMBINE_SYNCEN2_MASK (0x200000U) -#define FTM_COMBINE_SYNCEN2_SHIFT (21U) -#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) -#define FTM_COMBINE_FAULTEN2_MASK (0x400000U) -#define FTM_COMBINE_FAULTEN2_SHIFT (22U) -#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) -#define FTM_COMBINE_COMBINE3_MASK (0x1000000U) -#define FTM_COMBINE_COMBINE3_SHIFT (24U) -#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) -#define FTM_COMBINE_COMP3_MASK (0x2000000U) -#define FTM_COMBINE_COMP3_SHIFT (25U) -#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) -#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) -#define FTM_COMBINE_DECAPEN3_SHIFT (26U) -#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) -#define FTM_COMBINE_DECAP3_MASK (0x8000000U) -#define FTM_COMBINE_DECAP3_SHIFT (27U) -#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) -#define FTM_COMBINE_DTEN3_MASK (0x10000000U) -#define FTM_COMBINE_DTEN3_SHIFT (28U) -#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) -#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) -#define FTM_COMBINE_SYNCEN3_SHIFT (29U) -#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) -#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) -#define FTM_COMBINE_FAULTEN3_SHIFT (30U) -#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) - -/*! @name DEADTIME - Deadtime Insertion Control */ -#define FTM_DEADTIME_DTVAL_MASK (0x3FU) -#define FTM_DEADTIME_DTVAL_SHIFT (0U) -#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) -#define FTM_DEADTIME_DTPS_MASK (0xC0U) -#define FTM_DEADTIME_DTPS_SHIFT (6U) -#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) - -/*! @name EXTTRIG - FTM External Trigger */ -#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) -#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) -#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) -#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) -#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) -#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) -#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) -#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) -#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) -#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) -#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) -#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) -#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) -#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) -#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) -#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) -#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) -#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) -#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) -#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) -#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) -#define FTM_EXTTRIG_TRIGF_MASK (0x80U) -#define FTM_EXTTRIG_TRIGF_SHIFT (7U) -#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) - -/*! @name POL - Channels Polarity */ -#define FTM_POL_POL0_MASK (0x1U) -#define FTM_POL_POL0_SHIFT (0U) -#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) -#define FTM_POL_POL1_MASK (0x2U) -#define FTM_POL_POL1_SHIFT (1U) -#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) -#define FTM_POL_POL2_MASK (0x4U) -#define FTM_POL_POL2_SHIFT (2U) -#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) -#define FTM_POL_POL3_MASK (0x8U) -#define FTM_POL_POL3_SHIFT (3U) -#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) -#define FTM_POL_POL4_MASK (0x10U) -#define FTM_POL_POL4_SHIFT (4U) -#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) -#define FTM_POL_POL5_MASK (0x20U) -#define FTM_POL_POL5_SHIFT (5U) -#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) -#define FTM_POL_POL6_MASK (0x40U) -#define FTM_POL_POL6_SHIFT (6U) -#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) -#define FTM_POL_POL7_MASK (0x80U) -#define FTM_POL_POL7_SHIFT (7U) -#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) - -/*! @name FMS - Fault Mode Status */ -#define FTM_FMS_FAULTF0_MASK (0x1U) -#define FTM_FMS_FAULTF0_SHIFT (0U) -#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) -#define FTM_FMS_FAULTF1_MASK (0x2U) -#define FTM_FMS_FAULTF1_SHIFT (1U) -#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) -#define FTM_FMS_FAULTF2_MASK (0x4U) -#define FTM_FMS_FAULTF2_SHIFT (2U) -#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) -#define FTM_FMS_FAULTF3_MASK (0x8U) -#define FTM_FMS_FAULTF3_SHIFT (3U) -#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) -#define FTM_FMS_FAULTIN_MASK (0x20U) -#define FTM_FMS_FAULTIN_SHIFT (5U) -#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) -#define FTM_FMS_WPEN_MASK (0x40U) -#define FTM_FMS_WPEN_SHIFT (6U) -#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) -#define FTM_FMS_FAULTF_MASK (0x80U) -#define FTM_FMS_FAULTF_SHIFT (7U) -#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) - -/*! @name FILTER - Input Capture Filter Control */ -#define FTM_FILTER_CH0FVAL_MASK (0xFU) -#define FTM_FILTER_CH0FVAL_SHIFT (0U) -#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) -#define FTM_FILTER_CH1FVAL_MASK (0xF0U) -#define FTM_FILTER_CH1FVAL_SHIFT (4U) -#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) -#define FTM_FILTER_CH2FVAL_MASK (0xF00U) -#define FTM_FILTER_CH2FVAL_SHIFT (8U) -#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) -#define FTM_FILTER_CH3FVAL_MASK (0xF000U) -#define FTM_FILTER_CH3FVAL_SHIFT (12U) -#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) - -/*! @name FLTCTRL - Fault Control */ -#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) -#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) -#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) -#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) -#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) -#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) -#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) -#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) -#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) -#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) -#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) -#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) -#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) -#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) -#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) -#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) -#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) -#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) -#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) -#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) -#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) -#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) -#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) -#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) -#define FTM_FLTCTRL_FFVAL_MASK (0xF00U) -#define FTM_FLTCTRL_FFVAL_SHIFT (8U) -#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) - -/*! @name QDCTRL - Quadrature Decoder Control And Status */ -#define FTM_QDCTRL_QUADEN_MASK (0x1U) -#define FTM_QDCTRL_QUADEN_SHIFT (0U) -#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) -#define FTM_QDCTRL_TOFDIR_MASK (0x2U) -#define FTM_QDCTRL_TOFDIR_SHIFT (1U) -#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) -#define FTM_QDCTRL_QUADIR_MASK (0x4U) -#define FTM_QDCTRL_QUADIR_SHIFT (2U) -#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) -#define FTM_QDCTRL_QUADMODE_MASK (0x8U) -#define FTM_QDCTRL_QUADMODE_SHIFT (3U) -#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) -#define FTM_QDCTRL_PHBPOL_MASK (0x10U) -#define FTM_QDCTRL_PHBPOL_SHIFT (4U) -#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) -#define FTM_QDCTRL_PHAPOL_MASK (0x20U) -#define FTM_QDCTRL_PHAPOL_SHIFT (5U) -#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) -#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) -#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) -#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) -#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) -#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) -#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) - -/*! @name CONF - Configuration */ -#define FTM_CONF_NUMTOF_MASK (0x1FU) -#define FTM_CONF_NUMTOF_SHIFT (0U) -#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) -#define FTM_CONF_BDMMODE_MASK (0xC0U) -#define FTM_CONF_BDMMODE_SHIFT (6U) -#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) -#define FTM_CONF_GTBEEN_MASK (0x200U) -#define FTM_CONF_GTBEEN_SHIFT (9U) -#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) -#define FTM_CONF_GTBEOUT_MASK (0x400U) -#define FTM_CONF_GTBEOUT_SHIFT (10U) -#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) - -/*! @name FLTPOL - FTM Fault Input Polarity */ -#define FTM_FLTPOL_FLT0POL_MASK (0x1U) -#define FTM_FLTPOL_FLT0POL_SHIFT (0U) -#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) -#define FTM_FLTPOL_FLT1POL_MASK (0x2U) -#define FTM_FLTPOL_FLT1POL_SHIFT (1U) -#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) -#define FTM_FLTPOL_FLT2POL_MASK (0x4U) -#define FTM_FLTPOL_FLT2POL_SHIFT (2U) -#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) -#define FTM_FLTPOL_FLT3POL_MASK (0x8U) -#define FTM_FLTPOL_FLT3POL_SHIFT (3U) -#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) - -/*! @name SYNCONF - Synchronization Configuration */ -#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) -#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) -#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) -#define FTM_SYNCONF_CNTINC_MASK (0x4U) -#define FTM_SYNCONF_CNTINC_SHIFT (2U) -#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) -#define FTM_SYNCONF_INVC_MASK (0x10U) -#define FTM_SYNCONF_INVC_SHIFT (4U) -#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) -#define FTM_SYNCONF_SWOC_MASK (0x20U) -#define FTM_SYNCONF_SWOC_SHIFT (5U) -#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) -#define FTM_SYNCONF_SYNCMODE_MASK (0x80U) -#define FTM_SYNCONF_SYNCMODE_SHIFT (7U) -#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) -#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) -#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) -#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) -#define FTM_SYNCONF_SWWRBUF_MASK (0x200U) -#define FTM_SYNCONF_SWWRBUF_SHIFT (9U) -#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) -#define FTM_SYNCONF_SWOM_MASK (0x400U) -#define FTM_SYNCONF_SWOM_SHIFT (10U) -#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) -#define FTM_SYNCONF_SWINVC_MASK (0x800U) -#define FTM_SYNCONF_SWINVC_SHIFT (11U) -#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) -#define FTM_SYNCONF_SWSOC_MASK (0x1000U) -#define FTM_SYNCONF_SWSOC_SHIFT (12U) -#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) -#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) -#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) -#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) -#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) -#define FTM_SYNCONF_HWWRBUF_SHIFT (17U) -#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) -#define FTM_SYNCONF_HWOM_MASK (0x40000U) -#define FTM_SYNCONF_HWOM_SHIFT (18U) -#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) -#define FTM_SYNCONF_HWINVC_MASK (0x80000U) -#define FTM_SYNCONF_HWINVC_SHIFT (19U) -#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) -#define FTM_SYNCONF_HWSOC_MASK (0x100000U) -#define FTM_SYNCONF_HWSOC_SHIFT (20U) -#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) - -/*! @name INVCTRL - FTM Inverting Control */ -#define FTM_INVCTRL_INV0EN_MASK (0x1U) -#define FTM_INVCTRL_INV0EN_SHIFT (0U) -#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) -#define FTM_INVCTRL_INV1EN_MASK (0x2U) -#define FTM_INVCTRL_INV1EN_SHIFT (1U) -#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) -#define FTM_INVCTRL_INV2EN_MASK (0x4U) -#define FTM_INVCTRL_INV2EN_SHIFT (2U) -#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) -#define FTM_INVCTRL_INV3EN_MASK (0x8U) -#define FTM_INVCTRL_INV3EN_SHIFT (3U) -#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) - -/*! @name SWOCTRL - FTM Software Output Control */ -#define FTM_SWOCTRL_CH0OC_MASK (0x1U) -#define FTM_SWOCTRL_CH0OC_SHIFT (0U) -#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) -#define FTM_SWOCTRL_CH1OC_MASK (0x2U) -#define FTM_SWOCTRL_CH1OC_SHIFT (1U) -#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) -#define FTM_SWOCTRL_CH2OC_MASK (0x4U) -#define FTM_SWOCTRL_CH2OC_SHIFT (2U) -#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) -#define FTM_SWOCTRL_CH3OC_MASK (0x8U) -#define FTM_SWOCTRL_CH3OC_SHIFT (3U) -#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) -#define FTM_SWOCTRL_CH4OC_MASK (0x10U) -#define FTM_SWOCTRL_CH4OC_SHIFT (4U) -#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) -#define FTM_SWOCTRL_CH5OC_MASK (0x20U) -#define FTM_SWOCTRL_CH5OC_SHIFT (5U) -#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) -#define FTM_SWOCTRL_CH6OC_MASK (0x40U) -#define FTM_SWOCTRL_CH6OC_SHIFT (6U) -#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) -#define FTM_SWOCTRL_CH7OC_MASK (0x80U) -#define FTM_SWOCTRL_CH7OC_SHIFT (7U) -#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) -#define FTM_SWOCTRL_CH0OCV_MASK (0x100U) -#define FTM_SWOCTRL_CH0OCV_SHIFT (8U) -#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) -#define FTM_SWOCTRL_CH1OCV_MASK (0x200U) -#define FTM_SWOCTRL_CH1OCV_SHIFT (9U) -#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) -#define FTM_SWOCTRL_CH2OCV_MASK (0x400U) -#define FTM_SWOCTRL_CH2OCV_SHIFT (10U) -#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) -#define FTM_SWOCTRL_CH3OCV_MASK (0x800U) -#define FTM_SWOCTRL_CH3OCV_SHIFT (11U) -#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) -#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) -#define FTM_SWOCTRL_CH4OCV_SHIFT (12U) -#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) -#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) -#define FTM_SWOCTRL_CH5OCV_SHIFT (13U) -#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) -#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) -#define FTM_SWOCTRL_CH6OCV_SHIFT (14U) -#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) -#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) -#define FTM_SWOCTRL_CH7OCV_SHIFT (15U) -#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) - -/*! @name PWMLOAD - FTM PWM Load */ -#define FTM_PWMLOAD_CH0SEL_MASK (0x1U) -#define FTM_PWMLOAD_CH0SEL_SHIFT (0U) -#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) -#define FTM_PWMLOAD_CH1SEL_MASK (0x2U) -#define FTM_PWMLOAD_CH1SEL_SHIFT (1U) -#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) -#define FTM_PWMLOAD_CH2SEL_MASK (0x4U) -#define FTM_PWMLOAD_CH2SEL_SHIFT (2U) -#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) -#define FTM_PWMLOAD_CH3SEL_MASK (0x8U) -#define FTM_PWMLOAD_CH3SEL_SHIFT (3U) -#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) -#define FTM_PWMLOAD_CH4SEL_MASK (0x10U) -#define FTM_PWMLOAD_CH4SEL_SHIFT (4U) -#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) -#define FTM_PWMLOAD_CH5SEL_MASK (0x20U) -#define FTM_PWMLOAD_CH5SEL_SHIFT (5U) -#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) -#define FTM_PWMLOAD_CH6SEL_MASK (0x40U) -#define FTM_PWMLOAD_CH6SEL_SHIFT (6U) -#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) -#define FTM_PWMLOAD_CH7SEL_MASK (0x80U) -#define FTM_PWMLOAD_CH7SEL_SHIFT (7U) -#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) -#define FTM_PWMLOAD_LDOK_MASK (0x200U) -#define FTM_PWMLOAD_LDOK_SHIFT (9U) -#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) - - -/*! - * @} - */ /* end of group FTM_Register_Masks */ - - -/* FTM - Peripheral instance base addresses */ -/** Peripheral FTM0 base address */ -#define FTM0_BASE (0x40038000u) -/** Peripheral FTM0 base pointer */ -#define FTM0 ((FTM_Type *)FTM0_BASE) -/** Peripheral FTM1 base address */ -#define FTM1_BASE (0x40039000u) -/** Peripheral FTM1 base pointer */ -#define FTM1 ((FTM_Type *)FTM1_BASE) -/** Peripheral FTM2 base address */ -#define FTM2_BASE (0x4003A000u) -/** Peripheral FTM2 base pointer */ -#define FTM2 ((FTM_Type *)FTM2_BASE) -/** Array initializer of FTM peripheral base addresses */ -#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE } -/** Array initializer of FTM peripheral base pointers */ -#define FTM_BASE_PTRS { FTM0, FTM1, FTM2 } -/** Interrupt vectors for the FTM peripheral type */ -#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn } - -/*! - * @} - */ /* end of group FTM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ - __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ - __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ - __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ - __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ - __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name PDOR - Port Data Output Register */ -#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) -#define GPIO_PDOR_PDO_SHIFT (0U) -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) - -/*! @name PSOR - Port Set Output Register */ -#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) -#define GPIO_PSOR_PTSO_SHIFT (0U) -#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) - -/*! @name PCOR - Port Clear Output Register */ -#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) -#define GPIO_PCOR_PTCO_SHIFT (0U) -#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) - -/*! @name PTOR - Port Toggle Output Register */ -#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) -#define GPIO_PTOR_PTTO_SHIFT (0U) -#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) - -/*! @name PDIR - Port Data Input Register */ -#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) -#define GPIO_PDIR_PDI_SHIFT (0U) -#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) - -/*! @name PDDR - Port Data Direction Register */ -#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) -#define GPIO_PDDR_PDD_SHIFT (0U) -#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -/** Peripheral GPIOA base address */ -#define GPIOA_BASE (0x400FF000u) -/** Peripheral GPIOA base pointer */ -#define GPIOA ((GPIO_Type *)GPIOA_BASE) -/** Peripheral GPIOB base address */ -#define GPIOB_BASE (0x400FF040u) -/** Peripheral GPIOB base pointer */ -#define GPIOB ((GPIO_Type *)GPIOB_BASE) -/** Peripheral GPIOC base address */ -#define GPIOC_BASE (0x400FF080u) -/** Peripheral GPIOC base pointer */ -#define GPIOC ((GPIO_Type *)GPIOC_BASE) -/** Peripheral GPIOD base address */ -#define GPIOD_BASE (0x400FF0C0u) -/** Peripheral GPIOD base pointer */ -#define GPIOD ((GPIO_Type *)GPIOD_BASE) -/** Peripheral GPIOE base address */ -#define GPIOE_BASE (0x400FF100u) -/** Peripheral GPIOE base pointer */ -#define GPIOE ((GPIO_Type *)GPIOE_BASE) -/** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } -/** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ - __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ - __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ - __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ - __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ - __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ - __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ - __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ - __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ - __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ - __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ - __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name A1 - I2C Address Register 1 */ -#define I2C_A1_AD_MASK (0xFEU) -#define I2C_A1_AD_SHIFT (1U) -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) - -/*! @name F - I2C Frequency Divider register */ -#define I2C_F_ICR_MASK (0x3FU) -#define I2C_F_ICR_SHIFT (0U) -#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) -#define I2C_F_MULT_MASK (0xC0U) -#define I2C_F_MULT_SHIFT (6U) -#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) - -/*! @name C1 - I2C Control Register 1 */ -#define I2C_C1_DMAEN_MASK (0x1U) -#define I2C_C1_DMAEN_SHIFT (0U) -#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) -#define I2C_C1_WUEN_MASK (0x2U) -#define I2C_C1_WUEN_SHIFT (1U) -#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) -#define I2C_C1_RSTA_MASK (0x4U) -#define I2C_C1_RSTA_SHIFT (2U) -#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) -#define I2C_C1_TXAK_MASK (0x8U) -#define I2C_C1_TXAK_SHIFT (3U) -#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) -#define I2C_C1_TX_MASK (0x10U) -#define I2C_C1_TX_SHIFT (4U) -#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) -#define I2C_C1_MST_MASK (0x20U) -#define I2C_C1_MST_SHIFT (5U) -#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) -#define I2C_C1_IICIE_MASK (0x40U) -#define I2C_C1_IICIE_SHIFT (6U) -#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) -#define I2C_C1_IICEN_MASK (0x80U) -#define I2C_C1_IICEN_SHIFT (7U) -#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) - -/*! @name S - I2C Status register */ -#define I2C_S_RXAK_MASK (0x1U) -#define I2C_S_RXAK_SHIFT (0U) -#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) -#define I2C_S_IICIF_MASK (0x2U) -#define I2C_S_IICIF_SHIFT (1U) -#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) -#define I2C_S_SRW_MASK (0x4U) -#define I2C_S_SRW_SHIFT (2U) -#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) -#define I2C_S_RAM_MASK (0x8U) -#define I2C_S_RAM_SHIFT (3U) -#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) -#define I2C_S_ARBL_MASK (0x10U) -#define I2C_S_ARBL_SHIFT (4U) -#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) -#define I2C_S_BUSY_MASK (0x20U) -#define I2C_S_BUSY_SHIFT (5U) -#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) -#define I2C_S_IAAS_MASK (0x40U) -#define I2C_S_IAAS_SHIFT (6U) -#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) -#define I2C_S_TCF_MASK (0x80U) -#define I2C_S_TCF_SHIFT (7U) -#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) - -/*! @name D - I2C Data I/O register */ -#define I2C_D_DATA_MASK (0xFFU) -#define I2C_D_DATA_SHIFT (0U) -#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) - -/*! @name C2 - I2C Control Register 2 */ -#define I2C_C2_AD_MASK (0x7U) -#define I2C_C2_AD_SHIFT (0U) -#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) -#define I2C_C2_RMEN_MASK (0x8U) -#define I2C_C2_RMEN_SHIFT (3U) -#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) -#define I2C_C2_SBRC_MASK (0x10U) -#define I2C_C2_SBRC_SHIFT (4U) -#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) -#define I2C_C2_HDRS_MASK (0x20U) -#define I2C_C2_HDRS_SHIFT (5U) -#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) -#define I2C_C2_ADEXT_MASK (0x40U) -#define I2C_C2_ADEXT_SHIFT (6U) -#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) -#define I2C_C2_GCAEN_MASK (0x80U) -#define I2C_C2_GCAEN_SHIFT (7U) -#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) - -/*! @name FLT - I2C Programmable Input Glitch Filter register */ -#define I2C_FLT_FLT_MASK (0x1FU) -#define I2C_FLT_FLT_SHIFT (0U) -#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) - -/*! @name RA - I2C Range Address register */ -#define I2C_RA_RAD_MASK (0xFEU) -#define I2C_RA_RAD_SHIFT (1U) -#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) - -/*! @name SMB - I2C SMBus Control and Status register */ -#define I2C_SMB_SHTF2IE_MASK (0x1U) -#define I2C_SMB_SHTF2IE_SHIFT (0U) -#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) -#define I2C_SMB_SHTF2_MASK (0x2U) -#define I2C_SMB_SHTF2_SHIFT (1U) -#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) -#define I2C_SMB_SHTF1_MASK (0x4U) -#define I2C_SMB_SHTF1_SHIFT (2U) -#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) -#define I2C_SMB_SLTF_MASK (0x8U) -#define I2C_SMB_SLTF_SHIFT (3U) -#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) -#define I2C_SMB_TCKSEL_MASK (0x10U) -#define I2C_SMB_TCKSEL_SHIFT (4U) -#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) -#define I2C_SMB_SIICAEN_MASK (0x20U) -#define I2C_SMB_SIICAEN_SHIFT (5U) -#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) -#define I2C_SMB_ALERTEN_MASK (0x40U) -#define I2C_SMB_ALERTEN_SHIFT (6U) -#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) -#define I2C_SMB_FACK_MASK (0x80U) -#define I2C_SMB_FACK_SHIFT (7U) -#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) - -/*! @name A2 - I2C Address Register 2 */ -#define I2C_A2_SAD_MASK (0xFEU) -#define I2C_A2_SAD_SHIFT (1U) -#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) - -/*! @name SLTH - I2C SCL Low Timeout Register High */ -#define I2C_SLTH_SSLT_MASK (0xFFU) -#define I2C_SLTH_SSLT_SHIFT (0U) -#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) - -/*! @name SLTL - I2C SCL Low Timeout Register Low */ -#define I2C_SLTL_SSLT_MASK (0xFFU) -#define I2C_SLTL_SSLT_SHIFT (0U) -#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -/** Peripheral I2C0 base address */ -#define I2C0_BASE (0x40066000u) -/** Peripheral I2C0 base pointer */ -#define I2C0 ((I2C_Type *)I2C0_BASE) -/** Peripheral I2C1 base address */ -#define I2C1_BASE (0x40067000u) -/** Peripheral I2C1 base pointer */ -#define I2C1 ((I2C_Type *)I2C1_BASE) -/** Array initializer of I2C peripheral base addresses */ -#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } -/** Array initializer of I2C peripheral base pointers */ -#define I2C_BASE_PTRS { I2C0, I2C1 } -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ - __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ - __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ - __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ - __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ - __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ - uint8_t RESERVED_0[8]; - __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[28]; - __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[28]; - __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ - uint8_t RESERVED_3[28]; - __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ - __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ - __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ - __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ - __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ - __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ - uint8_t RESERVED_4[8]; - __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ - uint8_t RESERVED_5[28]; - __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_6[28]; - __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ - uint8_t RESERVED_7[28]; - __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ - __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name TCSR - SAI Transmit Control Register */ -#define I2S_TCSR_FRDE_MASK (0x1U) -#define I2S_TCSR_FRDE_SHIFT (0U) -#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) -#define I2S_TCSR_FWDE_MASK (0x2U) -#define I2S_TCSR_FWDE_SHIFT (1U) -#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) -#define I2S_TCSR_FRIE_MASK (0x100U) -#define I2S_TCSR_FRIE_SHIFT (8U) -#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) -#define I2S_TCSR_FWIE_MASK (0x200U) -#define I2S_TCSR_FWIE_SHIFT (9U) -#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) -#define I2S_TCSR_FEIE_MASK (0x400U) -#define I2S_TCSR_FEIE_SHIFT (10U) -#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) -#define I2S_TCSR_SEIE_MASK (0x800U) -#define I2S_TCSR_SEIE_SHIFT (11U) -#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) -#define I2S_TCSR_WSIE_MASK (0x1000U) -#define I2S_TCSR_WSIE_SHIFT (12U) -#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) -#define I2S_TCSR_FRF_MASK (0x10000U) -#define I2S_TCSR_FRF_SHIFT (16U) -#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) -#define I2S_TCSR_FWF_MASK (0x20000U) -#define I2S_TCSR_FWF_SHIFT (17U) -#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) -#define I2S_TCSR_FEF_MASK (0x40000U) -#define I2S_TCSR_FEF_SHIFT (18U) -#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) -#define I2S_TCSR_SEF_MASK (0x80000U) -#define I2S_TCSR_SEF_SHIFT (19U) -#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) -#define I2S_TCSR_WSF_MASK (0x100000U) -#define I2S_TCSR_WSF_SHIFT (20U) -#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) -#define I2S_TCSR_SR_MASK (0x1000000U) -#define I2S_TCSR_SR_SHIFT (24U) -#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) -#define I2S_TCSR_FR_MASK (0x2000000U) -#define I2S_TCSR_FR_SHIFT (25U) -#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) -#define I2S_TCSR_BCE_MASK (0x10000000U) -#define I2S_TCSR_BCE_SHIFT (28U) -#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) -#define I2S_TCSR_DBGE_MASK (0x20000000U) -#define I2S_TCSR_DBGE_SHIFT (29U) -#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) -#define I2S_TCSR_STOPE_MASK (0x40000000U) -#define I2S_TCSR_STOPE_SHIFT (30U) -#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) -#define I2S_TCSR_TE_MASK (0x80000000U) -#define I2S_TCSR_TE_SHIFT (31U) -#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) - -/*! @name TCR1 - SAI Transmit Configuration 1 Register */ -#define I2S_TCR1_TFW_MASK (0x7U) -#define I2S_TCR1_TFW_SHIFT (0U) -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) - -/*! @name TCR2 - SAI Transmit Configuration 2 Register */ -#define I2S_TCR2_DIV_MASK (0xFFU) -#define I2S_TCR2_DIV_SHIFT (0U) -#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) -#define I2S_TCR2_BCD_MASK (0x1000000U) -#define I2S_TCR2_BCD_SHIFT (24U) -#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) -#define I2S_TCR2_BCP_MASK (0x2000000U) -#define I2S_TCR2_BCP_SHIFT (25U) -#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) -#define I2S_TCR2_MSEL_MASK (0xC000000U) -#define I2S_TCR2_MSEL_SHIFT (26U) -#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) -#define I2S_TCR2_BCI_MASK (0x10000000U) -#define I2S_TCR2_BCI_SHIFT (28U) -#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) -#define I2S_TCR2_BCS_MASK (0x20000000U) -#define I2S_TCR2_BCS_SHIFT (29U) -#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) -#define I2S_TCR2_SYNC_MASK (0xC0000000U) -#define I2S_TCR2_SYNC_SHIFT (30U) -#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) - -/*! @name TCR3 - SAI Transmit Configuration 3 Register */ -#define I2S_TCR3_WDFL_MASK (0xFU) -#define I2S_TCR3_WDFL_SHIFT (0U) -#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) -#define I2S_TCR3_TCE_MASK (0x10000U) -#define I2S_TCR3_TCE_SHIFT (16U) -#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) - -/*! @name TCR4 - SAI Transmit Configuration 4 Register */ -#define I2S_TCR4_FSD_MASK (0x1U) -#define I2S_TCR4_FSD_SHIFT (0U) -#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) -#define I2S_TCR4_FSP_MASK (0x2U) -#define I2S_TCR4_FSP_SHIFT (1U) -#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) -#define I2S_TCR4_FSE_MASK (0x8U) -#define I2S_TCR4_FSE_SHIFT (3U) -#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) -#define I2S_TCR4_MF_MASK (0x10U) -#define I2S_TCR4_MF_SHIFT (4U) -#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) -#define I2S_TCR4_SYWD_MASK (0x1F00U) -#define I2S_TCR4_SYWD_SHIFT (8U) -#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) -#define I2S_TCR4_FRSZ_MASK (0xF0000U) -#define I2S_TCR4_FRSZ_SHIFT (16U) -#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) - -/*! @name TCR5 - SAI Transmit Configuration 5 Register */ -#define I2S_TCR5_FBT_MASK (0x1F00U) -#define I2S_TCR5_FBT_SHIFT (8U) -#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) -#define I2S_TCR5_W0W_MASK (0x1F0000U) -#define I2S_TCR5_W0W_SHIFT (16U) -#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) -#define I2S_TCR5_WNW_MASK (0x1F000000U) -#define I2S_TCR5_WNW_SHIFT (24U) -#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) - -/*! @name TDR - SAI Transmit Data Register */ -#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) -#define I2S_TDR_TDR_SHIFT (0U) -#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) - -/* The count of I2S_TDR */ -#define I2S_TDR_COUNT (1U) - -/*! @name TFR - SAI Transmit FIFO Register */ -#define I2S_TFR_RFP_MASK (0xFU) -#define I2S_TFR_RFP_SHIFT (0U) -#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) -#define I2S_TFR_WFP_MASK (0xF0000U) -#define I2S_TFR_WFP_SHIFT (16U) -#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) - -/* The count of I2S_TFR */ -#define I2S_TFR_COUNT (1U) - -/*! @name TMR - SAI Transmit Mask Register */ -#define I2S_TMR_TWM_MASK (0xFFFFU) -#define I2S_TMR_TWM_SHIFT (0U) -#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) - -/*! @name RCSR - SAI Receive Control Register */ -#define I2S_RCSR_FRDE_MASK (0x1U) -#define I2S_RCSR_FRDE_SHIFT (0U) -#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) -#define I2S_RCSR_FWDE_MASK (0x2U) -#define I2S_RCSR_FWDE_SHIFT (1U) -#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) -#define I2S_RCSR_FRIE_MASK (0x100U) -#define I2S_RCSR_FRIE_SHIFT (8U) -#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) -#define I2S_RCSR_FWIE_MASK (0x200U) -#define I2S_RCSR_FWIE_SHIFT (9U) -#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) -#define I2S_RCSR_FEIE_MASK (0x400U) -#define I2S_RCSR_FEIE_SHIFT (10U) -#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) -#define I2S_RCSR_SEIE_MASK (0x800U) -#define I2S_RCSR_SEIE_SHIFT (11U) -#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) -#define I2S_RCSR_WSIE_MASK (0x1000U) -#define I2S_RCSR_WSIE_SHIFT (12U) -#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) -#define I2S_RCSR_FRF_MASK (0x10000U) -#define I2S_RCSR_FRF_SHIFT (16U) -#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) -#define I2S_RCSR_FWF_MASK (0x20000U) -#define I2S_RCSR_FWF_SHIFT (17U) -#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) -#define I2S_RCSR_FEF_MASK (0x40000U) -#define I2S_RCSR_FEF_SHIFT (18U) -#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) -#define I2S_RCSR_SEF_MASK (0x80000U) -#define I2S_RCSR_SEF_SHIFT (19U) -#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) -#define I2S_RCSR_WSF_MASK (0x100000U) -#define I2S_RCSR_WSF_SHIFT (20U) -#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) -#define I2S_RCSR_SR_MASK (0x1000000U) -#define I2S_RCSR_SR_SHIFT (24U) -#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) -#define I2S_RCSR_FR_MASK (0x2000000U) -#define I2S_RCSR_FR_SHIFT (25U) -#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) -#define I2S_RCSR_BCE_MASK (0x10000000U) -#define I2S_RCSR_BCE_SHIFT (28U) -#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) -#define I2S_RCSR_DBGE_MASK (0x20000000U) -#define I2S_RCSR_DBGE_SHIFT (29U) -#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) -#define I2S_RCSR_STOPE_MASK (0x40000000U) -#define I2S_RCSR_STOPE_SHIFT (30U) -#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) -#define I2S_RCSR_RE_MASK (0x80000000U) -#define I2S_RCSR_RE_SHIFT (31U) -#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) - -/*! @name RCR1 - SAI Receive Configuration 1 Register */ -#define I2S_RCR1_RFW_MASK (0x7U) -#define I2S_RCR1_RFW_SHIFT (0U) -#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) - -/*! @name RCR2 - SAI Receive Configuration 2 Register */ -#define I2S_RCR2_DIV_MASK (0xFFU) -#define I2S_RCR2_DIV_SHIFT (0U) -#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) -#define I2S_RCR2_BCD_MASK (0x1000000U) -#define I2S_RCR2_BCD_SHIFT (24U) -#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) -#define I2S_RCR2_BCP_MASK (0x2000000U) -#define I2S_RCR2_BCP_SHIFT (25U) -#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) -#define I2S_RCR2_MSEL_MASK (0xC000000U) -#define I2S_RCR2_MSEL_SHIFT (26U) -#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) -#define I2S_RCR2_BCI_MASK (0x10000000U) -#define I2S_RCR2_BCI_SHIFT (28U) -#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) -#define I2S_RCR2_BCS_MASK (0x20000000U) -#define I2S_RCR2_BCS_SHIFT (29U) -#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) -#define I2S_RCR2_SYNC_MASK (0xC0000000U) -#define I2S_RCR2_SYNC_SHIFT (30U) -#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) - -/*! @name RCR3 - SAI Receive Configuration 3 Register */ -#define I2S_RCR3_WDFL_MASK (0xFU) -#define I2S_RCR3_WDFL_SHIFT (0U) -#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) -#define I2S_RCR3_RCE_MASK (0x10000U) -#define I2S_RCR3_RCE_SHIFT (16U) -#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) - -/*! @name RCR4 - SAI Receive Configuration 4 Register */ -#define I2S_RCR4_FSD_MASK (0x1U) -#define I2S_RCR4_FSD_SHIFT (0U) -#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) -#define I2S_RCR4_FSP_MASK (0x2U) -#define I2S_RCR4_FSP_SHIFT (1U) -#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) -#define I2S_RCR4_FSE_MASK (0x8U) -#define I2S_RCR4_FSE_SHIFT (3U) -#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) -#define I2S_RCR4_MF_MASK (0x10U) -#define I2S_RCR4_MF_SHIFT (4U) -#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) -#define I2S_RCR4_SYWD_MASK (0x1F00U) -#define I2S_RCR4_SYWD_SHIFT (8U) -#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) -#define I2S_RCR4_FRSZ_MASK (0xF0000U) -#define I2S_RCR4_FRSZ_SHIFT (16U) -#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) - -/*! @name RCR5 - SAI Receive Configuration 5 Register */ -#define I2S_RCR5_FBT_MASK (0x1F00U) -#define I2S_RCR5_FBT_SHIFT (8U) -#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) -#define I2S_RCR5_W0W_MASK (0x1F0000U) -#define I2S_RCR5_W0W_SHIFT (16U) -#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) -#define I2S_RCR5_WNW_MASK (0x1F000000U) -#define I2S_RCR5_WNW_SHIFT (24U) -#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) - -/*! @name RDR - SAI Receive Data Register */ -#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) -#define I2S_RDR_RDR_SHIFT (0U) -#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) - -/* The count of I2S_RDR */ -#define I2S_RDR_COUNT (1U) - -/*! @name RFR - SAI Receive FIFO Register */ -#define I2S_RFR_RFP_MASK (0xFU) -#define I2S_RFR_RFP_SHIFT (0U) -#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) -#define I2S_RFR_WFP_MASK (0xF0000U) -#define I2S_RFR_WFP_SHIFT (16U) -#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) - -/* The count of I2S_RFR */ -#define I2S_RFR_COUNT (1U) - -/*! @name RMR - SAI Receive Mask Register */ -#define I2S_RMR_RWM_MASK (0xFFFFU) -#define I2S_RMR_RWM_SHIFT (0U) -#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) - -/*! @name MCR - SAI MCLK Control Register */ -#define I2S_MCR_MICS_MASK (0x3000000U) -#define I2S_MCR_MICS_SHIFT (24U) -#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK) -#define I2S_MCR_MOE_MASK (0x40000000U) -#define I2S_MCR_MOE_SHIFT (30U) -#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) -#define I2S_MCR_DUF_MASK (0x80000000U) -#define I2S_MCR_DUF_SHIFT (31U) -#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK) - -/*! @name MDR - SAI MCLK Divide Register */ -#define I2S_MDR_DIVIDE_MASK (0xFFFU) -#define I2S_MDR_DIVIDE_SHIFT (0U) -#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK) -#define I2S_MDR_FRACT_MASK (0xFF000U) -#define I2S_MDR_FRACT_SHIFT (12U) -#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK) - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -/** Peripheral I2S0 base address */ -#define I2S0_BASE (0x4002F000u) -/** Peripheral I2S0 base pointer */ -#define I2S0 ((I2S_Type *)I2S0_BASE) -/** Array initializer of I2S peripheral base addresses */ -#define I2S_BASE_ADDRS { I2S0_BASE } -/** Array initializer of I2S peripheral base pointers */ -#define I2S_BASE_PTRS { I2S0 } -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_RX_IRQS { I2S0_Rx_IRQn } -#define I2S_TX_IRQS { I2S0_Tx_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LLWU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer - * @{ - */ - -/** LLWU - Register Layout Typedef */ -typedef struct { - __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ - __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ - __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ - __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ - __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ - __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ - __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ - __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ - __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ - __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ - __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */ -} LLWU_Type; - -/* ---------------------------------------------------------------------------- - -- LLWU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Register_Masks LLWU Register Masks - * @{ - */ - -/*! @name PE1 - LLWU Pin Enable 1 register */ -#define LLWU_PE1_WUPE0_MASK (0x3U) -#define LLWU_PE1_WUPE0_SHIFT (0U) -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) -#define LLWU_PE1_WUPE1_MASK (0xCU) -#define LLWU_PE1_WUPE1_SHIFT (2U) -#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) -#define LLWU_PE1_WUPE2_MASK (0x30U) -#define LLWU_PE1_WUPE2_SHIFT (4U) -#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) -#define LLWU_PE1_WUPE3_MASK (0xC0U) -#define LLWU_PE1_WUPE3_SHIFT (6U) -#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) - -/*! @name PE2 - LLWU Pin Enable 2 register */ -#define LLWU_PE2_WUPE4_MASK (0x3U) -#define LLWU_PE2_WUPE4_SHIFT (0U) -#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) -#define LLWU_PE2_WUPE5_MASK (0xCU) -#define LLWU_PE2_WUPE5_SHIFT (2U) -#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) -#define LLWU_PE2_WUPE6_MASK (0x30U) -#define LLWU_PE2_WUPE6_SHIFT (4U) -#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) -#define LLWU_PE2_WUPE7_MASK (0xC0U) -#define LLWU_PE2_WUPE7_SHIFT (6U) -#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) - -/*! @name PE3 - LLWU Pin Enable 3 register */ -#define LLWU_PE3_WUPE8_MASK (0x3U) -#define LLWU_PE3_WUPE8_SHIFT (0U) -#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) -#define LLWU_PE3_WUPE9_MASK (0xCU) -#define LLWU_PE3_WUPE9_SHIFT (2U) -#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) -#define LLWU_PE3_WUPE10_MASK (0x30U) -#define LLWU_PE3_WUPE10_SHIFT (4U) -#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) -#define LLWU_PE3_WUPE11_MASK (0xC0U) -#define LLWU_PE3_WUPE11_SHIFT (6U) -#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) - -/*! @name PE4 - LLWU Pin Enable 4 register */ -#define LLWU_PE4_WUPE12_MASK (0x3U) -#define LLWU_PE4_WUPE12_SHIFT (0U) -#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) -#define LLWU_PE4_WUPE13_MASK (0xCU) -#define LLWU_PE4_WUPE13_SHIFT (2U) -#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) -#define LLWU_PE4_WUPE14_MASK (0x30U) -#define LLWU_PE4_WUPE14_SHIFT (4U) -#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) -#define LLWU_PE4_WUPE15_MASK (0xC0U) -#define LLWU_PE4_WUPE15_SHIFT (6U) -#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) - -/*! @name ME - LLWU Module Enable register */ -#define LLWU_ME_WUME0_MASK (0x1U) -#define LLWU_ME_WUME0_SHIFT (0U) -#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) -#define LLWU_ME_WUME1_MASK (0x2U) -#define LLWU_ME_WUME1_SHIFT (1U) -#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) -#define LLWU_ME_WUME2_MASK (0x4U) -#define LLWU_ME_WUME2_SHIFT (2U) -#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) -#define LLWU_ME_WUME3_MASK (0x8U) -#define LLWU_ME_WUME3_SHIFT (3U) -#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) -#define LLWU_ME_WUME4_MASK (0x10U) -#define LLWU_ME_WUME4_SHIFT (4U) -#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) -#define LLWU_ME_WUME5_MASK (0x20U) -#define LLWU_ME_WUME5_SHIFT (5U) -#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) -#define LLWU_ME_WUME6_MASK (0x40U) -#define LLWU_ME_WUME6_SHIFT (6U) -#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) -#define LLWU_ME_WUME7_MASK (0x80U) -#define LLWU_ME_WUME7_SHIFT (7U) -#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) - -/*! @name F1 - LLWU Flag 1 register */ -#define LLWU_F1_WUF0_MASK (0x1U) -#define LLWU_F1_WUF0_SHIFT (0U) -#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) -#define LLWU_F1_WUF1_MASK (0x2U) -#define LLWU_F1_WUF1_SHIFT (1U) -#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) -#define LLWU_F1_WUF2_MASK (0x4U) -#define LLWU_F1_WUF2_SHIFT (2U) -#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) -#define LLWU_F1_WUF3_MASK (0x8U) -#define LLWU_F1_WUF3_SHIFT (3U) -#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) -#define LLWU_F1_WUF4_MASK (0x10U) -#define LLWU_F1_WUF4_SHIFT (4U) -#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) -#define LLWU_F1_WUF5_MASK (0x20U) -#define LLWU_F1_WUF5_SHIFT (5U) -#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) -#define LLWU_F1_WUF6_MASK (0x40U) -#define LLWU_F1_WUF6_SHIFT (6U) -#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) -#define LLWU_F1_WUF7_MASK (0x80U) -#define LLWU_F1_WUF7_SHIFT (7U) -#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) - -/*! @name F2 - LLWU Flag 2 register */ -#define LLWU_F2_WUF8_MASK (0x1U) -#define LLWU_F2_WUF8_SHIFT (0U) -#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) -#define LLWU_F2_WUF9_MASK (0x2U) -#define LLWU_F2_WUF9_SHIFT (1U) -#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) -#define LLWU_F2_WUF10_MASK (0x4U) -#define LLWU_F2_WUF10_SHIFT (2U) -#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) -#define LLWU_F2_WUF11_MASK (0x8U) -#define LLWU_F2_WUF11_SHIFT (3U) -#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) -#define LLWU_F2_WUF12_MASK (0x10U) -#define LLWU_F2_WUF12_SHIFT (4U) -#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) -#define LLWU_F2_WUF13_MASK (0x20U) -#define LLWU_F2_WUF13_SHIFT (5U) -#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) -#define LLWU_F2_WUF14_MASK (0x40U) -#define LLWU_F2_WUF14_SHIFT (6U) -#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) -#define LLWU_F2_WUF15_MASK (0x80U) -#define LLWU_F2_WUF15_SHIFT (7U) -#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) - -/*! @name F3 - LLWU Flag 3 register */ -#define LLWU_F3_MWUF0_MASK (0x1U) -#define LLWU_F3_MWUF0_SHIFT (0U) -#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) -#define LLWU_F3_MWUF1_MASK (0x2U) -#define LLWU_F3_MWUF1_SHIFT (1U) -#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) -#define LLWU_F3_MWUF2_MASK (0x4U) -#define LLWU_F3_MWUF2_SHIFT (2U) -#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) -#define LLWU_F3_MWUF3_MASK (0x8U) -#define LLWU_F3_MWUF3_SHIFT (3U) -#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) -#define LLWU_F3_MWUF4_MASK (0x10U) -#define LLWU_F3_MWUF4_SHIFT (4U) -#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) -#define LLWU_F3_MWUF5_MASK (0x20U) -#define LLWU_F3_MWUF5_SHIFT (5U) -#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) -#define LLWU_F3_MWUF6_MASK (0x40U) -#define LLWU_F3_MWUF6_SHIFT (6U) -#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) -#define LLWU_F3_MWUF7_MASK (0x80U) -#define LLWU_F3_MWUF7_SHIFT (7U) -#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) - -/*! @name FILT1 - LLWU Pin Filter 1 register */ -#define LLWU_FILT1_FILTSEL_MASK (0xFU) -#define LLWU_FILT1_FILTSEL_SHIFT (0U) -#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) -#define LLWU_FILT1_FILTE_MASK (0x60U) -#define LLWU_FILT1_FILTE_SHIFT (5U) -#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) -#define LLWU_FILT1_FILTF_MASK (0x80U) -#define LLWU_FILT1_FILTF_SHIFT (7U) -#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) - -/*! @name FILT2 - LLWU Pin Filter 2 register */ -#define LLWU_FILT2_FILTSEL_MASK (0xFU) -#define LLWU_FILT2_FILTSEL_SHIFT (0U) -#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) -#define LLWU_FILT2_FILTE_MASK (0x60U) -#define LLWU_FILT2_FILTE_SHIFT (5U) -#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) -#define LLWU_FILT2_FILTF_MASK (0x80U) -#define LLWU_FILT2_FILTF_SHIFT (7U) -#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) - -/*! @name RST - LLWU Reset Enable register */ -#define LLWU_RST_RSTFILT_MASK (0x1U) -#define LLWU_RST_RSTFILT_SHIFT (0U) -#define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK) -#define LLWU_RST_LLRSTE_MASK (0x2U) -#define LLWU_RST_LLRSTE_SHIFT (1U) -#define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK) - - -/*! - * @} - */ /* end of group LLWU_Register_Masks */ - - -/* LLWU - Peripheral instance base addresses */ -/** Peripheral LLWU base address */ -#define LLWU_BASE (0x4007C000u) -/** Peripheral LLWU base pointer */ -#define LLWU ((LLWU_Type *)LLWU_BASE) -/** Array initializer of LLWU peripheral base addresses */ -#define LLWU_BASE_ADDRS { LLWU_BASE } -/** Array initializer of LLWU peripheral base pointers */ -#define LLWU_BASE_PTRS { LLWU } -/** Interrupt vectors for the LLWU peripheral type */ -#define LLWU_IRQS { LLWU_IRQn } - -/*! - * @} - */ /* end of group LLWU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPTMR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer - * @{ - */ - -/** LPTMR - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ - __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ - __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ - __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ -} LPTMR_Type; - -/* ---------------------------------------------------------------------------- - -- LPTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Register_Masks LPTMR Register Masks - * @{ - */ - -/*! @name CSR - Low Power Timer Control Status Register */ -#define LPTMR_CSR_TEN_MASK (0x1U) -#define LPTMR_CSR_TEN_SHIFT (0U) -#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) -#define LPTMR_CSR_TMS_MASK (0x2U) -#define LPTMR_CSR_TMS_SHIFT (1U) -#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) -#define LPTMR_CSR_TFC_MASK (0x4U) -#define LPTMR_CSR_TFC_SHIFT (2U) -#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) -#define LPTMR_CSR_TPP_MASK (0x8U) -#define LPTMR_CSR_TPP_SHIFT (3U) -#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) -#define LPTMR_CSR_TPS_MASK (0x30U) -#define LPTMR_CSR_TPS_SHIFT (4U) -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) -#define LPTMR_CSR_TIE_MASK (0x40U) -#define LPTMR_CSR_TIE_SHIFT (6U) -#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) -#define LPTMR_CSR_TCF_MASK (0x80U) -#define LPTMR_CSR_TCF_SHIFT (7U) -#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) - -/*! @name PSR - Low Power Timer Prescale Register */ -#define LPTMR_PSR_PCS_MASK (0x3U) -#define LPTMR_PSR_PCS_SHIFT (0U) -#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) -#define LPTMR_PSR_PBYP_MASK (0x4U) -#define LPTMR_PSR_PBYP_SHIFT (2U) -#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) -#define LPTMR_PSR_PRESCALE_MASK (0x78U) -#define LPTMR_PSR_PRESCALE_SHIFT (3U) -#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) - -/*! @name CMR - Low Power Timer Compare Register */ -#define LPTMR_CMR_COMPARE_MASK (0xFFFFU) -#define LPTMR_CMR_COMPARE_SHIFT (0U) -#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) - -/*! @name CNR - Low Power Timer Counter Register */ -#define LPTMR_CNR_COUNTER_MASK (0xFFFFU) -#define LPTMR_CNR_COUNTER_SHIFT (0U) -#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) - - -/*! - * @} - */ /* end of group LPTMR_Register_Masks */ - - -/* LPTMR - Peripheral instance base addresses */ -/** Peripheral LPTMR0 base address */ -#define LPTMR0_BASE (0x40040000u) -/** Peripheral LPTMR0 base pointer */ -#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) -/** Array initializer of LPTMR peripheral base addresses */ -#define LPTMR_BASE_ADDRS { LPTMR0_BASE } -/** Array initializer of LPTMR peripheral base pointers */ -#define LPTMR_BASE_PTRS { LPTMR0 } -/** Interrupt vectors for the LPTMR peripheral type */ -#define LPTMR_IRQS { LPTMR0_IRQn } - -/*! - * @} - */ /* end of group LPTMR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MCG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer - * @{ - */ - -/** MCG - Register Layout Typedef */ -typedef struct { - __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ - __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ - __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ - __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ - __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ - __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ - __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ - uint8_t RESERVED_0[1]; - __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ - uint8_t RESERVED_1[1]; - __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ - __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ - __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ - __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ - __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */ - __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */ -} MCG_Type; - -/* ---------------------------------------------------------------------------- - -- MCG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCG_Register_Masks MCG Register Masks - * @{ - */ - -/*! @name C1 - MCG Control 1 Register */ -#define MCG_C1_IREFSTEN_MASK (0x1U) -#define MCG_C1_IREFSTEN_SHIFT (0U) -#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) -#define MCG_C1_IRCLKEN_MASK (0x2U) -#define MCG_C1_IRCLKEN_SHIFT (1U) -#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) -#define MCG_C1_IREFS_MASK (0x4U) -#define MCG_C1_IREFS_SHIFT (2U) -#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) -#define MCG_C1_FRDIV_MASK (0x38U) -#define MCG_C1_FRDIV_SHIFT (3U) -#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) -#define MCG_C1_CLKS_MASK (0xC0U) -#define MCG_C1_CLKS_SHIFT (6U) -#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) - -/*! @name C2 - MCG Control 2 Register */ -#define MCG_C2_IRCS_MASK (0x1U) -#define MCG_C2_IRCS_SHIFT (0U) -#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) -#define MCG_C2_LP_MASK (0x2U) -#define MCG_C2_LP_SHIFT (1U) -#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) -#define MCG_C2_EREFS0_MASK (0x4U) -#define MCG_C2_EREFS0_SHIFT (2U) -#define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK) -#define MCG_C2_HGO0_MASK (0x8U) -#define MCG_C2_HGO0_SHIFT (3U) -#define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK) -#define MCG_C2_RANGE0_MASK (0x30U) -#define MCG_C2_RANGE0_SHIFT (4U) -#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK) -#define MCG_C2_LOCRE0_MASK (0x80U) -#define MCG_C2_LOCRE0_SHIFT (7U) -#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) - -/*! @name C3 - MCG Control 3 Register */ -#define MCG_C3_SCTRIM_MASK (0xFFU) -#define MCG_C3_SCTRIM_SHIFT (0U) -#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) - -/*! @name C4 - MCG Control 4 Register */ -#define MCG_C4_SCFTRIM_MASK (0x1U) -#define MCG_C4_SCFTRIM_SHIFT (0U) -#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) -#define MCG_C4_FCTRIM_MASK (0x1EU) -#define MCG_C4_FCTRIM_SHIFT (1U) -#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) -#define MCG_C4_DRST_DRS_MASK (0x60U) -#define MCG_C4_DRST_DRS_SHIFT (5U) -#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) -#define MCG_C4_DMX32_MASK (0x80U) -#define MCG_C4_DMX32_SHIFT (7U) -#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) - -/*! @name C5 - MCG Control 5 Register */ -#define MCG_C5_PRDIV0_MASK (0x1FU) -#define MCG_C5_PRDIV0_SHIFT (0U) -#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK) -#define MCG_C5_PLLSTEN0_MASK (0x20U) -#define MCG_C5_PLLSTEN0_SHIFT (5U) -#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK) -#define MCG_C5_PLLCLKEN0_MASK (0x40U) -#define MCG_C5_PLLCLKEN0_SHIFT (6U) -#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK) - -/*! @name C6 - MCG Control 6 Register */ -#define MCG_C6_VDIV0_MASK (0x1FU) -#define MCG_C6_VDIV0_SHIFT (0U) -#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK) -#define MCG_C6_CME0_MASK (0x20U) -#define MCG_C6_CME0_SHIFT (5U) -#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) -#define MCG_C6_PLLS_MASK (0x40U) -#define MCG_C6_PLLS_SHIFT (6U) -#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) -#define MCG_C6_LOLIE0_MASK (0x80U) -#define MCG_C6_LOLIE0_SHIFT (7U) -#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) - -/*! @name S - MCG Status Register */ -#define MCG_S_IRCST_MASK (0x1U) -#define MCG_S_IRCST_SHIFT (0U) -#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) -#define MCG_S_OSCINIT0_MASK (0x2U) -#define MCG_S_OSCINIT0_SHIFT (1U) -#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) -#define MCG_S_CLKST_MASK (0xCU) -#define MCG_S_CLKST_SHIFT (2U) -#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) -#define MCG_S_IREFST_MASK (0x10U) -#define MCG_S_IREFST_SHIFT (4U) -#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) -#define MCG_S_PLLST_MASK (0x20U) -#define MCG_S_PLLST_SHIFT (5U) -#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) -#define MCG_S_LOCK0_MASK (0x40U) -#define MCG_S_LOCK0_SHIFT (6U) -#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) -#define MCG_S_LOLS0_MASK (0x80U) -#define MCG_S_LOLS0_SHIFT (7U) -#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) - -/*! @name SC - MCG Status and Control Register */ -#define MCG_SC_LOCS0_MASK (0x1U) -#define MCG_SC_LOCS0_SHIFT (0U) -#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) -#define MCG_SC_FCRDIV_MASK (0xEU) -#define MCG_SC_FCRDIV_SHIFT (1U) -#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) -#define MCG_SC_FLTPRSRV_MASK (0x10U) -#define MCG_SC_FLTPRSRV_SHIFT (4U) -#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) -#define MCG_SC_ATMF_MASK (0x20U) -#define MCG_SC_ATMF_SHIFT (5U) -#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) -#define MCG_SC_ATMS_MASK (0x40U) -#define MCG_SC_ATMS_SHIFT (6U) -#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) -#define MCG_SC_ATME_MASK (0x80U) -#define MCG_SC_ATME_SHIFT (7U) -#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) - -/*! @name ATCVH - MCG Auto Trim Compare Value High Register */ -#define MCG_ATCVH_ATCVH_MASK (0xFFU) -#define MCG_ATCVH_ATCVH_SHIFT (0U) -#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) - -/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ -#define MCG_ATCVL_ATCVL_MASK (0xFFU) -#define MCG_ATCVL_ATCVL_SHIFT (0U) -#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) - -/*! @name C7 - MCG Control 7 Register */ -#define MCG_C7_OSCSEL_MASK (0x1U) -#define MCG_C7_OSCSEL_SHIFT (0U) -#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) - -/*! @name C8 - MCG Control 8 Register */ -#define MCG_C8_LOCS1_MASK (0x1U) -#define MCG_C8_LOCS1_SHIFT (0U) -#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) -#define MCG_C8_CME1_MASK (0x20U) -#define MCG_C8_CME1_SHIFT (5U) -#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) -#define MCG_C8_LOLRE_MASK (0x40U) -#define MCG_C8_LOLRE_SHIFT (6U) -#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) -#define MCG_C8_LOCRE1_MASK (0x80U) -#define MCG_C8_LOCRE1_SHIFT (7U) -#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) - - -/*! - * @} - */ /* end of group MCG_Register_Masks */ - - -/* MCG - Peripheral instance base addresses */ -/** Peripheral MCG base address */ -#define MCG_BASE (0x40064000u) -/** Peripheral MCG base pointer */ -#define MCG ((MCG_Type *)MCG_BASE) -/** Array initializer of MCG peripheral base addresses */ -#define MCG_BASE_ADDRS { MCG_BASE } -/** Array initializer of MCG peripheral base pointers */ -#define MCG_BASE_PTRS { MCG } -/** Interrupt vectors for the MCG peripheral type */ -#define MCG_IRQS { MCG_IRQn } -/* MCG C2[EREFS] backward compatibility */ -#define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK) -#define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT) -#define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH) -#define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x)) - -/* MCG C2[HGO] backward compatibility */ -#define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK) -#define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT) -#define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH) -#define MCG_C2_HGO(x) (MCG_C2_HGO0(x)) - -/* MCG C2[RANGE] backward compatibility */ -#define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK) -#define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT) -#define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH) -#define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x)) - - -/*! - * @} - */ /* end of group MCG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MCM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer - * @{ - */ - -/** MCM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[8]; - __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ - __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ - __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */ -} MCM_Type; - -/* ---------------------------------------------------------------------------- - -- MCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Register_Masks MCM Register Masks - * @{ - */ - -/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ -#define MCM_PLASC_ASC_MASK (0xFFU) -#define MCM_PLASC_ASC_SHIFT (0U) -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) - -/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ -#define MCM_PLAMC_AMC_MASK (0xFFU) -#define MCM_PLAMC_AMC_SHIFT (0U) -#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) - -/*! @name PLACR - Crossbar Switch (AXBS) Control Register */ -#define MCM_PLACR_ARB_MASK (0x200U) -#define MCM_PLACR_ARB_SHIFT (9U) -#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) - - -/*! - * @} - */ /* end of group MCM_Register_Masks */ - - -/* MCM - Peripheral instance base addresses */ -/** Peripheral MCM base address */ -#define MCM_BASE (0xE0080000u) -/** Peripheral MCM base pointer */ -#define MCM ((MCM_Type *)MCM_BASE) -/** Array initializer of MCM peripheral base addresses */ -#define MCM_BASE_ADDRS { MCM_BASE } -/** Array initializer of MCM peripheral base pointers */ -#define MCM_BASE_PTRS { MCM } -/** Interrupt vectors for the MCM peripheral type */ -#define MCM_IRQS { MCM_IRQn } - -/*! - * @} - */ /* end of group MCM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- NV Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer - * @{ - */ - -/** NV - Register Layout Typedef */ -typedef struct { - __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ - __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ - __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ - __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ - __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ - __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ - __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ - __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ - __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ - __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ - __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ - __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ - __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ - __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ - __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */ - __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */ -} NV_Type; - -/* ---------------------------------------------------------------------------- - -- NV Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup NV_Register_Masks NV Register Masks - * @{ - */ - -/*! @name BACKKEY3 - Backdoor Comparison Key 3. */ -#define NV_BACKKEY3_KEY_MASK (0xFFU) -#define NV_BACKKEY3_KEY_SHIFT (0U) -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) - -/*! @name BACKKEY2 - Backdoor Comparison Key 2. */ -#define NV_BACKKEY2_KEY_MASK (0xFFU) -#define NV_BACKKEY2_KEY_SHIFT (0U) -#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) - -/*! @name BACKKEY1 - Backdoor Comparison Key 1. */ -#define NV_BACKKEY1_KEY_MASK (0xFFU) -#define NV_BACKKEY1_KEY_SHIFT (0U) -#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) - -/*! @name BACKKEY0 - Backdoor Comparison Key 0. */ -#define NV_BACKKEY0_KEY_MASK (0xFFU) -#define NV_BACKKEY0_KEY_SHIFT (0U) -#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) - -/*! @name BACKKEY7 - Backdoor Comparison Key 7. */ -#define NV_BACKKEY7_KEY_MASK (0xFFU) -#define NV_BACKKEY7_KEY_SHIFT (0U) -#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) - -/*! @name BACKKEY6 - Backdoor Comparison Key 6. */ -#define NV_BACKKEY6_KEY_MASK (0xFFU) -#define NV_BACKKEY6_KEY_SHIFT (0U) -#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) - -/*! @name BACKKEY5 - Backdoor Comparison Key 5. */ -#define NV_BACKKEY5_KEY_MASK (0xFFU) -#define NV_BACKKEY5_KEY_SHIFT (0U) -#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) - -/*! @name BACKKEY4 - Backdoor Comparison Key 4. */ -#define NV_BACKKEY4_KEY_MASK (0xFFU) -#define NV_BACKKEY4_KEY_SHIFT (0U) -#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) - -/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ -#define NV_FPROT3_PROT_MASK (0xFFU) -#define NV_FPROT3_PROT_SHIFT (0U) -#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) - -/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ -#define NV_FPROT2_PROT_MASK (0xFFU) -#define NV_FPROT2_PROT_SHIFT (0U) -#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) - -/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ -#define NV_FPROT1_PROT_MASK (0xFFU) -#define NV_FPROT1_PROT_SHIFT (0U) -#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) - -/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ -#define NV_FPROT0_PROT_MASK (0xFFU) -#define NV_FPROT0_PROT_SHIFT (0U) -#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) - -/*! @name FSEC - Non-volatile Flash Security Register */ -#define NV_FSEC_SEC_MASK (0x3U) -#define NV_FSEC_SEC_SHIFT (0U) -#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) -#define NV_FSEC_FSLACC_MASK (0xCU) -#define NV_FSEC_FSLACC_SHIFT (2U) -#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) -#define NV_FSEC_MEEN_MASK (0x30U) -#define NV_FSEC_MEEN_SHIFT (4U) -#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) -#define NV_FSEC_KEYEN_MASK (0xC0U) -#define NV_FSEC_KEYEN_SHIFT (6U) -#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) - -/*! @name FOPT - Non-volatile Flash Option Register */ -#define NV_FOPT_LPBOOT_MASK (0x1U) -#define NV_FOPT_LPBOOT_SHIFT (0U) -#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) -#define NV_FOPT_EZPORT_DIS_MASK (0x2U) -#define NV_FOPT_EZPORT_DIS_SHIFT (1U) -#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK) -#define NV_FOPT_NMI_DIS_MASK (0x4U) -#define NV_FOPT_NMI_DIS_SHIFT (2U) -#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) - -/*! @name FEPROT - Non-volatile EERAM Protection Register */ -#define NV_FEPROT_EPROT_MASK (0xFFU) -#define NV_FEPROT_EPROT_SHIFT (0U) -#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK) - -/*! @name FDPROT - Non-volatile D-Flash Protection Register */ -#define NV_FDPROT_DPROT_MASK (0xFFU) -#define NV_FDPROT_DPROT_SHIFT (0U) -#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK) - - -/*! - * @} - */ /* end of group NV_Register_Masks */ - - -/* NV - Peripheral instance base addresses */ -/** Peripheral FTFL_FlashConfig base address */ -#define FTFL_FlashConfig_BASE (0x400u) -/** Peripheral FTFL_FlashConfig base pointer */ -#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE) -/** Array initializer of NV peripheral base addresses */ -#define NV_BASE_ADDRS { FTFL_FlashConfig_BASE } -/** Array initializer of NV peripheral base pointers */ -#define NV_BASE_PTRS { FTFL_FlashConfig } - -/*! - * @} - */ /* end of group NV_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OSC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer - * @{ - */ - -/** OSC - Register Layout Typedef */ -typedef struct { - __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ -} OSC_Type; - -/* ---------------------------------------------------------------------------- - -- OSC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Masks OSC Register Masks - * @{ - */ - -/*! @name CR - OSC Control Register */ -#define OSC_CR_SC16P_MASK (0x1U) -#define OSC_CR_SC16P_SHIFT (0U) -#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) -#define OSC_CR_SC8P_MASK (0x2U) -#define OSC_CR_SC8P_SHIFT (1U) -#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) -#define OSC_CR_SC4P_MASK (0x4U) -#define OSC_CR_SC4P_SHIFT (2U) -#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) -#define OSC_CR_SC2P_MASK (0x8U) -#define OSC_CR_SC2P_SHIFT (3U) -#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) -#define OSC_CR_EREFSTEN_MASK (0x20U) -#define OSC_CR_EREFSTEN_SHIFT (5U) -#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) -#define OSC_CR_ERCLKEN_MASK (0x80U) -#define OSC_CR_ERCLKEN_SHIFT (7U) -#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) - - -/*! - * @} - */ /* end of group OSC_Register_Masks */ - - -/* OSC - Peripheral instance base addresses */ -/** Peripheral OSC base address */ -#define OSC_BASE (0x40065000u) -/** Peripheral OSC base pointer */ -#define OSC ((OSC_Type *)OSC_BASE) -/** Array initializer of OSC peripheral base addresses */ -#define OSC_BASE_ADDRS { OSC_BASE } -/** Array initializer of OSC peripheral base pointers */ -#define OSC_BASE_PTRS { OSC } - -/*! - * @} - */ /* end of group OSC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PDB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer - * @{ - */ - -/** PDB - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */ - __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */ - __I uint32_t CNT; /**< Counter Register, offset: 0x8 */ - __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */ - struct { /* offset: 0x10, array step: 0x28 */ - __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */ - __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */ - __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */ - uint8_t RESERVED_0[24]; - } CH[2]; - uint8_t RESERVED_0[240]; - struct { /* offset: 0x150, array step: 0x8 */ - __IO uint32_t INTC; /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */ - __IO uint32_t INT; /**< DAC Interval n Register, array offset: 0x154, array step: 0x8 */ - } DAC[1]; - uint8_t RESERVED_1[56]; - __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ - __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ -} PDB_Type; - -/* ---------------------------------------------------------------------------- - -- PDB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Register_Masks PDB Register Masks - * @{ - */ - -/*! @name SC - Status and Control Register */ -#define PDB_SC_LDOK_MASK (0x1U) -#define PDB_SC_LDOK_SHIFT (0U) -#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) -#define PDB_SC_CONT_MASK (0x2U) -#define PDB_SC_CONT_SHIFT (1U) -#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) -#define PDB_SC_MULT_MASK (0xCU) -#define PDB_SC_MULT_SHIFT (2U) -#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) -#define PDB_SC_PDBIE_MASK (0x20U) -#define PDB_SC_PDBIE_SHIFT (5U) -#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) -#define PDB_SC_PDBIF_MASK (0x40U) -#define PDB_SC_PDBIF_SHIFT (6U) -#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) -#define PDB_SC_PDBEN_MASK (0x80U) -#define PDB_SC_PDBEN_SHIFT (7U) -#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) -#define PDB_SC_TRGSEL_MASK (0xF00U) -#define PDB_SC_TRGSEL_SHIFT (8U) -#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) -#define PDB_SC_PRESCALER_MASK (0x7000U) -#define PDB_SC_PRESCALER_SHIFT (12U) -#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) -#define PDB_SC_DMAEN_MASK (0x8000U) -#define PDB_SC_DMAEN_SHIFT (15U) -#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) -#define PDB_SC_SWTRIG_MASK (0x10000U) -#define PDB_SC_SWTRIG_SHIFT (16U) -#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) -#define PDB_SC_PDBEIE_MASK (0x20000U) -#define PDB_SC_PDBEIE_SHIFT (17U) -#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) -#define PDB_SC_LDMOD_MASK (0xC0000U) -#define PDB_SC_LDMOD_SHIFT (18U) -#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) - -/*! @name MOD - Modulus Register */ -#define PDB_MOD_MOD_MASK (0xFFFFU) -#define PDB_MOD_MOD_SHIFT (0U) -#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) - -/*! @name CNT - Counter Register */ -#define PDB_CNT_CNT_MASK (0xFFFFU) -#define PDB_CNT_CNT_SHIFT (0U) -#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) - -/*! @name IDLY - Interrupt Delay Register */ -#define PDB_IDLY_IDLY_MASK (0xFFFFU) -#define PDB_IDLY_IDLY_SHIFT (0U) -#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) - -/*! @name C1 - Channel n Control Register 1 */ -#define PDB_C1_EN_MASK (0xFFU) -#define PDB_C1_EN_SHIFT (0U) -#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) -#define PDB_C1_TOS_MASK (0xFF00U) -#define PDB_C1_TOS_SHIFT (8U) -#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) -#define PDB_C1_BB_MASK (0xFF0000U) -#define PDB_C1_BB_SHIFT (16U) -#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) - -/* The count of PDB_C1 */ -#define PDB_C1_COUNT (2U) - -/*! @name S - Channel n Status Register */ -#define PDB_S_ERR_MASK (0xFFU) -#define PDB_S_ERR_SHIFT (0U) -#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) -#define PDB_S_CF_MASK (0xFF0000U) -#define PDB_S_CF_SHIFT (16U) -#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) - -/* The count of PDB_S */ -#define PDB_S_COUNT (2U) - -/*! @name DLY - Channel n Delay 0 Register..Channel n Delay 1 Register */ -#define PDB_DLY_DLY_MASK (0xFFFFU) -#define PDB_DLY_DLY_SHIFT (0U) -#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) - -/* The count of PDB_DLY */ -#define PDB_DLY_COUNT (2U) - -/* The count of PDB_DLY */ -#define PDB_DLY_COUNT2 (2U) - -/*! @name INTC - DAC Interval Trigger n Control Register */ -#define PDB_INTC_TOE_MASK (0x1U) -#define PDB_INTC_TOE_SHIFT (0U) -#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK) -#define PDB_INTC_EXT_MASK (0x2U) -#define PDB_INTC_EXT_SHIFT (1U) -#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK) - -/* The count of PDB_INTC */ -#define PDB_INTC_COUNT (1U) - -/*! @name INT - DAC Interval n Register */ -#define PDB_INT_INT_MASK (0xFFFFU) -#define PDB_INT_INT_SHIFT (0U) -#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK) - -/* The count of PDB_INT */ -#define PDB_INT_COUNT (1U) - -/*! @name POEN - Pulse-Out n Enable Register */ -#define PDB_POEN_POEN_MASK (0xFFU) -#define PDB_POEN_POEN_SHIFT (0U) -#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) - -/*! @name PODLY - Pulse-Out n Delay Register */ -#define PDB_PODLY_DLY2_MASK (0xFFFFU) -#define PDB_PODLY_DLY2_SHIFT (0U) -#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) -#define PDB_PODLY_DLY1_MASK (0xFFFF0000U) -#define PDB_PODLY_DLY1_SHIFT (16U) -#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) - -/* The count of PDB_PODLY */ -#define PDB_PODLY_COUNT (2U) - - -/*! - * @} - */ /* end of group PDB_Register_Masks */ - - -/* PDB - Peripheral instance base addresses */ -/** Peripheral PDB0 base address */ -#define PDB0_BASE (0x40036000u) -/** Peripheral PDB0 base pointer */ -#define PDB0 ((PDB_Type *)PDB0_BASE) -/** Array initializer of PDB peripheral base addresses */ -#define PDB_BASE_ADDRS { PDB0_BASE } -/** Array initializer of PDB peripheral base pointers */ -#define PDB_BASE_PTRS { PDB0 } -/** Interrupt vectors for the PDB peripheral type */ -#define PDB_IRQS { PDB0_IRQn } - -/*! - * @} - */ /* end of group PDB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PIT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer - * @{ - */ - -/** PIT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ - uint8_t RESERVED_0[252]; - struct { /* offset: 0x100, array step: 0x10 */ - __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ - __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ - __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ - __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ - } CHANNEL[4]; -} PIT_Type; - -/* ---------------------------------------------------------------------------- - -- PIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Register_Masks PIT Register Masks - * @{ - */ - -/*! @name MCR - PIT Module Control Register */ -#define PIT_MCR_FRZ_MASK (0x1U) -#define PIT_MCR_FRZ_SHIFT (0U) -#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) -#define PIT_MCR_MDIS_MASK (0x2U) -#define PIT_MCR_MDIS_SHIFT (1U) -#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) - -/*! @name LDVAL - Timer Load Value Register */ -#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) -#define PIT_LDVAL_TSV_SHIFT (0U) -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) - -/* The count of PIT_LDVAL */ -#define PIT_LDVAL_COUNT (4U) - -/*! @name CVAL - Current Timer Value Register */ -#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) -#define PIT_CVAL_TVL_SHIFT (0U) -#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) - -/* The count of PIT_CVAL */ -#define PIT_CVAL_COUNT (4U) - -/*! @name TCTRL - Timer Control Register */ -#define PIT_TCTRL_TEN_MASK (0x1U) -#define PIT_TCTRL_TEN_SHIFT (0U) -#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) -#define PIT_TCTRL_TIE_MASK (0x2U) -#define PIT_TCTRL_TIE_SHIFT (1U) -#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) -#define PIT_TCTRL_CHN_MASK (0x4U) -#define PIT_TCTRL_CHN_SHIFT (2U) -#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) - -/* The count of PIT_TCTRL */ -#define PIT_TCTRL_COUNT (4U) - -/*! @name TFLG - Timer Flag Register */ -#define PIT_TFLG_TIF_MASK (0x1U) -#define PIT_TFLG_TIF_SHIFT (0U) -#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) - -/* The count of PIT_TFLG */ -#define PIT_TFLG_COUNT (4U) - - -/*! - * @} - */ /* end of group PIT_Register_Masks */ - - -/* PIT - Peripheral instance base addresses */ -/** Peripheral PIT base address */ -#define PIT_BASE (0x40037000u) -/** Peripheral PIT base pointer */ -#define PIT ((PIT_Type *)PIT_BASE) -/** Array initializer of PIT peripheral base addresses */ -#define PIT_BASE_ADDRS { PIT_BASE } -/** Array initializer of PIT peripheral base pointers */ -#define PIT_BASE_PTRS { PIT } -/** Interrupt vectors for the PIT peripheral type */ -#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } - -/*! - * @} - */ /* end of group PIT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ - __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ - __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ -#define PMC_LVDSC1_LVDV_MASK (0x3U) -#define PMC_LVDSC1_LVDV_SHIFT (0U) -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) -#define PMC_LVDSC1_LVDRE_MASK (0x10U) -#define PMC_LVDSC1_LVDRE_SHIFT (4U) -#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) -#define PMC_LVDSC1_LVDIE_MASK (0x20U) -#define PMC_LVDSC1_LVDIE_SHIFT (5U) -#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) -#define PMC_LVDSC1_LVDACK_MASK (0x40U) -#define PMC_LVDSC1_LVDACK_SHIFT (6U) -#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) -#define PMC_LVDSC1_LVDF_MASK (0x80U) -#define PMC_LVDSC1_LVDF_SHIFT (7U) -#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) - -/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ -#define PMC_LVDSC2_LVWV_MASK (0x3U) -#define PMC_LVDSC2_LVWV_SHIFT (0U) -#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) -#define PMC_LVDSC2_LVWIE_MASK (0x20U) -#define PMC_LVDSC2_LVWIE_SHIFT (5U) -#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) -#define PMC_LVDSC2_LVWACK_MASK (0x40U) -#define PMC_LVDSC2_LVWACK_SHIFT (6U) -#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) -#define PMC_LVDSC2_LVWF_MASK (0x80U) -#define PMC_LVDSC2_LVWF_SHIFT (7U) -#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) - -/*! @name REGSC - Regulator Status And Control register */ -#define PMC_REGSC_BGBE_MASK (0x1U) -#define PMC_REGSC_BGBE_SHIFT (0U) -#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) -#define PMC_REGSC_REGONS_MASK (0x4U) -#define PMC_REGSC_REGONS_SHIFT (2U) -#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) -#define PMC_REGSC_ACKISO_MASK (0x8U) -#define PMC_REGSC_ACKISO_SHIFT (3U) -#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) -#define PMC_REGSC_BGEN_MASK (0x10U) -#define PMC_REGSC_BGEN_SHIFT (4U) -#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) - - -/*! - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -/** Peripheral PMC base address */ -#define PMC_BASE (0x4007D000u) -/** Peripheral PMC base pointer */ -#define PMC ((PMC_Type *)PMC_BASE) -/** Array initializer of PMC peripheral base addresses */ -#define PMC_BASE_ADDRS { PMC_BASE } -/** Array initializer of PMC peripheral base pointers */ -#define PMC_BASE_PTRS { PMC } -/** Interrupt vectors for the PMC peripheral type */ -#define PMC_IRQS { PMC_IRQn } - -/*! - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PORT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer - * @{ - */ - -/** PORT - Register Layout Typedef */ -typedef struct { - __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ - __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ - __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ - uint8_t RESERVED_0[24]; - __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ - uint8_t RESERVED_1[28]; - __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ - __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ - __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ -} PORT_Type; - -/* ---------------------------------------------------------------------------- - -- PORT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Register_Masks PORT Register Masks - * @{ - */ - -/*! @name PCR - Pin Control Register n */ -#define PORT_PCR_PS_MASK (0x1U) -#define PORT_PCR_PS_SHIFT (0U) -#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) -#define PORT_PCR_PE_MASK (0x2U) -#define PORT_PCR_PE_SHIFT (1U) -#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) -#define PORT_PCR_SRE_MASK (0x4U) -#define PORT_PCR_SRE_SHIFT (2U) -#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) -#define PORT_PCR_PFE_MASK (0x10U) -#define PORT_PCR_PFE_SHIFT (4U) -#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) -#define PORT_PCR_ODE_MASK (0x20U) -#define PORT_PCR_ODE_SHIFT (5U) -#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) -#define PORT_PCR_DSE_MASK (0x40U) -#define PORT_PCR_DSE_SHIFT (6U) -#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) -#define PORT_PCR_MUX_MASK (0x700U) -#define PORT_PCR_MUX_SHIFT (8U) -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) -#define PORT_PCR_LK_MASK (0x8000U) -#define PORT_PCR_LK_SHIFT (15U) -#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) -#define PORT_PCR_IRQC_MASK (0xF0000U) -#define PORT_PCR_IRQC_SHIFT (16U) -#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) -#define PORT_PCR_ISF_MASK (0x1000000U) -#define PORT_PCR_ISF_SHIFT (24U) -#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) - -/* The count of PORT_PCR */ -#define PORT_PCR_COUNT (32U) - -/*! @name GPCLR - Global Pin Control Low Register */ -#define PORT_GPCLR_GPWD_MASK (0xFFFFU) -#define PORT_GPCLR_GPWD_SHIFT (0U) -#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) -#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) -#define PORT_GPCLR_GPWE_SHIFT (16U) -#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) - -/*! @name GPCHR - Global Pin Control High Register */ -#define PORT_GPCHR_GPWD_MASK (0xFFFFU) -#define PORT_GPCHR_GPWD_SHIFT (0U) -#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) -#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) -#define PORT_GPCHR_GPWE_SHIFT (16U) -#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) - -/*! @name ISFR - Interrupt Status Flag Register */ -#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) -#define PORT_ISFR_ISF_SHIFT (0U) -#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) - -/*! @name DFER - Digital Filter Enable Register */ -#define PORT_DFER_DFE_MASK (0xFFFFFFFFU) -#define PORT_DFER_DFE_SHIFT (0U) -#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) - -/*! @name DFCR - Digital Filter Clock Register */ -#define PORT_DFCR_CS_MASK (0x1U) -#define PORT_DFCR_CS_SHIFT (0U) -#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) - -/*! @name DFWR - Digital Filter Width Register */ -#define PORT_DFWR_FILT_MASK (0x1FU) -#define PORT_DFWR_FILT_SHIFT (0U) -#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) - - -/*! - * @} - */ /* end of group PORT_Register_Masks */ - - -/* PORT - Peripheral instance base addresses */ -/** Peripheral PORTA base address */ -#define PORTA_BASE (0x40049000u) -/** Peripheral PORTA base pointer */ -#define PORTA ((PORT_Type *)PORTA_BASE) -/** Peripheral PORTB base address */ -#define PORTB_BASE (0x4004A000u) -/** Peripheral PORTB base pointer */ -#define PORTB ((PORT_Type *)PORTB_BASE) -/** Peripheral PORTC base address */ -#define PORTC_BASE (0x4004B000u) -/** Peripheral PORTC base pointer */ -#define PORTC ((PORT_Type *)PORTC_BASE) -/** Peripheral PORTD base address */ -#define PORTD_BASE (0x4004C000u) -/** Peripheral PORTD base pointer */ -#define PORTD ((PORT_Type *)PORTD_BASE) -/** Peripheral PORTE base address */ -#define PORTE_BASE (0x4004D000u) -/** Peripheral PORTE base pointer */ -#define PORTE ((PORT_Type *)PORTE_BASE) -/** Array initializer of PORT peripheral base addresses */ -#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } -/** Array initializer of PORT peripheral base pointers */ -#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } -/** Interrupt vectors for the PORT peripheral type */ -#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } - -/*! - * @} - */ /* end of group PORT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RCM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer - * @{ - */ - -/** RCM - Register Layout Typedef */ -typedef struct { - __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ - __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ - uint8_t RESERVED_0[2]; - __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ - __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ - uint8_t RESERVED_1[1]; - __I uint8_t MR; /**< Mode Register, offset: 0x7 */ -} RCM_Type; - -/* ---------------------------------------------------------------------------- - -- RCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RCM_Register_Masks RCM Register Masks - * @{ - */ - -/*! @name SRS0 - System Reset Status Register 0 */ -#define RCM_SRS0_WAKEUP_MASK (0x1U) -#define RCM_SRS0_WAKEUP_SHIFT (0U) -#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) -#define RCM_SRS0_LVD_MASK (0x2U) -#define RCM_SRS0_LVD_SHIFT (1U) -#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) -#define RCM_SRS0_LOC_MASK (0x4U) -#define RCM_SRS0_LOC_SHIFT (2U) -#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) -#define RCM_SRS0_LOL_MASK (0x8U) -#define RCM_SRS0_LOL_SHIFT (3U) -#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) -#define RCM_SRS0_WDOG_MASK (0x20U) -#define RCM_SRS0_WDOG_SHIFT (5U) -#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) -#define RCM_SRS0_PIN_MASK (0x40U) -#define RCM_SRS0_PIN_SHIFT (6U) -#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) -#define RCM_SRS0_POR_MASK (0x80U) -#define RCM_SRS0_POR_SHIFT (7U) -#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) - -/*! @name SRS1 - System Reset Status Register 1 */ -#define RCM_SRS1_JTAG_MASK (0x1U) -#define RCM_SRS1_JTAG_SHIFT (0U) -#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK) -#define RCM_SRS1_LOCKUP_MASK (0x2U) -#define RCM_SRS1_LOCKUP_SHIFT (1U) -#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) -#define RCM_SRS1_SW_MASK (0x4U) -#define RCM_SRS1_SW_SHIFT (2U) -#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) -#define RCM_SRS1_MDM_AP_MASK (0x8U) -#define RCM_SRS1_MDM_AP_SHIFT (3U) -#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) -#define RCM_SRS1_EZPT_MASK (0x10U) -#define RCM_SRS1_EZPT_SHIFT (4U) -#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK) -#define RCM_SRS1_SACKERR_MASK (0x20U) -#define RCM_SRS1_SACKERR_SHIFT (5U) -#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) - -/*! @name RPFC - Reset Pin Filter Control register */ -#define RCM_RPFC_RSTFLTSRW_MASK (0x3U) -#define RCM_RPFC_RSTFLTSRW_SHIFT (0U) -#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) -#define RCM_RPFC_RSTFLTSS_MASK (0x4U) -#define RCM_RPFC_RSTFLTSS_SHIFT (2U) -#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) - -/*! @name RPFW - Reset Pin Filter Width register */ -#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) -#define RCM_RPFW_RSTFLTSEL_SHIFT (0U) -#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) - -/*! @name MR - Mode Register */ -#define RCM_MR_EZP_MS_MASK (0x2U) -#define RCM_MR_EZP_MS_SHIFT (1U) -#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK) - - -/*! - * @} - */ /* end of group RCM_Register_Masks */ - - -/* RCM - Peripheral instance base addresses */ -/** Peripheral RCM base address */ -#define RCM_BASE (0x4007F000u) -/** Peripheral RCM base pointer */ -#define RCM ((RCM_Type *)RCM_BASE) -/** Array initializer of RCM peripheral base addresses */ -#define RCM_BASE_ADDRS { RCM_BASE } -/** Array initializer of RCM peripheral base pointers */ -#define RCM_BASE_PTRS { RCM } - -/*! - * @} - */ /* end of group RCM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RFSYS Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer - * @{ - */ - -/** RFSYS - Register Layout Typedef */ -typedef struct { - __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ -} RFSYS_Type; - -/* ---------------------------------------------------------------------------- - -- RFSYS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFSYS_Register_Masks RFSYS Register Masks - * @{ - */ - -/*! @name REG - Register file register */ -#define RFSYS_REG_LL_MASK (0xFFU) -#define RFSYS_REG_LL_SHIFT (0U) -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) -#define RFSYS_REG_LH_MASK (0xFF00U) -#define RFSYS_REG_LH_SHIFT (8U) -#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) -#define RFSYS_REG_HL_MASK (0xFF0000U) -#define RFSYS_REG_HL_SHIFT (16U) -#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) -#define RFSYS_REG_HH_MASK (0xFF000000U) -#define RFSYS_REG_HH_SHIFT (24U) -#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) - -/* The count of RFSYS_REG */ -#define RFSYS_REG_COUNT (8U) - - -/*! - * @} - */ /* end of group RFSYS_Register_Masks */ - - -/* RFSYS - Peripheral instance base addresses */ -/** Peripheral RFSYS base address */ -#define RFSYS_BASE (0x40041000u) -/** Peripheral RFSYS base pointer */ -#define RFSYS ((RFSYS_Type *)RFSYS_BASE) -/** Array initializer of RFSYS peripheral base addresses */ -#define RFSYS_BASE_ADDRS { RFSYS_BASE } -/** Array initializer of RFSYS peripheral base pointers */ -#define RFSYS_BASE_PTRS { RFSYS } - -/*! - * @} - */ /* end of group RFSYS_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RFVBAT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer - * @{ - */ - -/** RFVBAT - Register Layout Typedef */ -typedef struct { - __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ -} RFVBAT_Type; - -/* ---------------------------------------------------------------------------- - -- RFVBAT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks - * @{ - */ - -/*! @name REG - VBAT register file register */ -#define RFVBAT_REG_LL_MASK (0xFFU) -#define RFVBAT_REG_LL_SHIFT (0U) -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK) -#define RFVBAT_REG_LH_MASK (0xFF00U) -#define RFVBAT_REG_LH_SHIFT (8U) -#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK) -#define RFVBAT_REG_HL_MASK (0xFF0000U) -#define RFVBAT_REG_HL_SHIFT (16U) -#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK) -#define RFVBAT_REG_HH_MASK (0xFF000000U) -#define RFVBAT_REG_HH_SHIFT (24U) -#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK) - -/* The count of RFVBAT_REG */ -#define RFVBAT_REG_COUNT (8U) - - -/*! - * @} - */ /* end of group RFVBAT_Register_Masks */ - - -/* RFVBAT - Peripheral instance base addresses */ -/** Peripheral RFVBAT base address */ -#define RFVBAT_BASE (0x4003E000u) -/** Peripheral RFVBAT base pointer */ -#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) -/** Array initializer of RFVBAT peripheral base addresses */ -#define RFVBAT_BASE_ADDRS { RFVBAT_BASE } -/** Array initializer of RFVBAT peripheral base pointers */ -#define RFVBAT_BASE_PTRS { RFVBAT } - -/*! - * @} - */ /* end of group RFVBAT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer - * @{ - */ - -/** RNG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */ - __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */ - __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */ - __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */ -} RNG_Type; - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/*! @name CR - RNGA Control Register */ -#define RNG_CR_GO_MASK (0x1U) -#define RNG_CR_GO_SHIFT (0U) -#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK) -#define RNG_CR_HA_MASK (0x2U) -#define RNG_CR_HA_SHIFT (1U) -#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK) -#define RNG_CR_INTM_MASK (0x4U) -#define RNG_CR_INTM_SHIFT (2U) -#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK) -#define RNG_CR_CLRI_MASK (0x8U) -#define RNG_CR_CLRI_SHIFT (3U) -#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK) -#define RNG_CR_SLP_MASK (0x10U) -#define RNG_CR_SLP_SHIFT (4U) -#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK) - -/*! @name SR - RNGA Status Register */ -#define RNG_SR_SECV_MASK (0x1U) -#define RNG_SR_SECV_SHIFT (0U) -#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK) -#define RNG_SR_LRS_MASK (0x2U) -#define RNG_SR_LRS_SHIFT (1U) -#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK) -#define RNG_SR_ORU_MASK (0x4U) -#define RNG_SR_ORU_SHIFT (2U) -#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK) -#define RNG_SR_ERRI_MASK (0x8U) -#define RNG_SR_ERRI_SHIFT (3U) -#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK) -#define RNG_SR_SLP_MASK (0x10U) -#define RNG_SR_SLP_SHIFT (4U) -#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) -#define RNG_SR_OREG_LVL_MASK (0xFF00U) -#define RNG_SR_OREG_LVL_SHIFT (8U) -#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK) -#define RNG_SR_OREG_SIZE_MASK (0xFF0000U) -#define RNG_SR_OREG_SIZE_SHIFT (16U) -#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK) - -/*! @name ER - RNGA Entropy Register */ -#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU) -#define RNG_ER_EXT_ENT_SHIFT (0U) -#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK) - -/*! @name OR - RNGA Output Register */ -#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU) -#define RNG_OR_RANDOUT_SHIFT (0U) -#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK) - - -/*! - * @} - */ /* end of group RNG_Register_Masks */ - - -/* RNG - Peripheral instance base addresses */ -/** Peripheral RNG base address */ -#define RNG_BASE (0x40029000u) -/** Peripheral RNG base pointer */ -#define RNG ((RNG_Type *)RNG_BASE) -/** Array initializer of RNG peripheral base addresses */ -#define RNG_BASE_ADDRS { RNG_BASE } -/** Array initializer of RNG peripheral base pointers */ -#define RNG_BASE_PTRS { RNG } -/** Interrupt vectors for the RNG peripheral type */ -#define RNG_IRQS { RNG_IRQn } - -/*! - * @} - */ /* end of group RNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ - __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ - __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ - __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ - __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ - __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ - __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ - __I uint32_t TTSR; /**< RTC Tamper Time Seconds Register, offset: 0x20 */ - __IO uint32_t MER; /**< RTC Monotonic Enable Register, offset: 0x24 */ - __IO uint32_t MCLR; /**< RTC Monotonic Counter Low Register, offset: 0x28 */ - __IO uint32_t MCHR; /**< RTC Monotonic Counter High Register, offset: 0x2C */ - uint8_t RESERVED_0[2000]; - __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ - __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name TSR - RTC Time Seconds Register */ -#define RTC_TSR_TSR_MASK (0xFFFFFFFFU) -#define RTC_TSR_TSR_SHIFT (0U) -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) - -/*! @name TPR - RTC Time Prescaler Register */ -#define RTC_TPR_TPR_MASK (0xFFFFU) -#define RTC_TPR_TPR_SHIFT (0U) -#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) - -/*! @name TAR - RTC Time Alarm Register */ -#define RTC_TAR_TAR_MASK (0xFFFFFFFFU) -#define RTC_TAR_TAR_SHIFT (0U) -#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) - -/*! @name TCR - RTC Time Compensation Register */ -#define RTC_TCR_TCR_MASK (0xFFU) -#define RTC_TCR_TCR_SHIFT (0U) -#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) -#define RTC_TCR_CIR_MASK (0xFF00U) -#define RTC_TCR_CIR_SHIFT (8U) -#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) -#define RTC_TCR_TCV_MASK (0xFF0000U) -#define RTC_TCR_TCV_SHIFT (16U) -#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) -#define RTC_TCR_CIC_MASK (0xFF000000U) -#define RTC_TCR_CIC_SHIFT (24U) -#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) - -/*! @name CR - RTC Control Register */ -#define RTC_CR_SWR_MASK (0x1U) -#define RTC_CR_SWR_SHIFT (0U) -#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) -#define RTC_CR_WPE_MASK (0x2U) -#define RTC_CR_WPE_SHIFT (1U) -#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) -#define RTC_CR_SUP_MASK (0x4U) -#define RTC_CR_SUP_SHIFT (2U) -#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) -#define RTC_CR_UM_MASK (0x8U) -#define RTC_CR_UM_SHIFT (3U) -#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) -#define RTC_CR_WPS_MASK (0x10U) -#define RTC_CR_WPS_SHIFT (4U) -#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) -#define RTC_CR_OSCE_MASK (0x100U) -#define RTC_CR_OSCE_SHIFT (8U) -#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) -#define RTC_CR_CLKO_MASK (0x200U) -#define RTC_CR_CLKO_SHIFT (9U) -#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) -#define RTC_CR_SC16P_MASK (0x400U) -#define RTC_CR_SC16P_SHIFT (10U) -#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) -#define RTC_CR_SC8P_MASK (0x800U) -#define RTC_CR_SC8P_SHIFT (11U) -#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) -#define RTC_CR_SC4P_MASK (0x1000U) -#define RTC_CR_SC4P_SHIFT (12U) -#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) -#define RTC_CR_SC2P_MASK (0x2000U) -#define RTC_CR_SC2P_SHIFT (13U) -#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) - -/*! @name SR - RTC Status Register */ -#define RTC_SR_TIF_MASK (0x1U) -#define RTC_SR_TIF_SHIFT (0U) -#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) -#define RTC_SR_TOF_MASK (0x2U) -#define RTC_SR_TOF_SHIFT (1U) -#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) -#define RTC_SR_TAF_MASK (0x4U) -#define RTC_SR_TAF_SHIFT (2U) -#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) -#define RTC_SR_MOF_MASK (0x8U) -#define RTC_SR_MOF_SHIFT (3U) -#define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK) -#define RTC_SR_TCE_MASK (0x10U) -#define RTC_SR_TCE_SHIFT (4U) -#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) - -/*! @name LR - RTC Lock Register */ -#define RTC_LR_TCL_MASK (0x8U) -#define RTC_LR_TCL_SHIFT (3U) -#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) -#define RTC_LR_CRL_MASK (0x10U) -#define RTC_LR_CRL_SHIFT (4U) -#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) -#define RTC_LR_SRL_MASK (0x20U) -#define RTC_LR_SRL_SHIFT (5U) -#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) -#define RTC_LR_LRL_MASK (0x40U) -#define RTC_LR_LRL_SHIFT (6U) -#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) -#define RTC_LR_TTSL_MASK (0x100U) -#define RTC_LR_TTSL_SHIFT (8U) -#define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK) -#define RTC_LR_MEL_MASK (0x200U) -#define RTC_LR_MEL_SHIFT (9U) -#define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK) -#define RTC_LR_MCLL_MASK (0x400U) -#define RTC_LR_MCLL_SHIFT (10U) -#define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK) -#define RTC_LR_MCHL_MASK (0x800U) -#define RTC_LR_MCHL_SHIFT (11U) -#define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK) - -/*! @name IER - RTC Interrupt Enable Register */ -#define RTC_IER_TIIE_MASK (0x1U) -#define RTC_IER_TIIE_SHIFT (0U) -#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) -#define RTC_IER_TOIE_MASK (0x2U) -#define RTC_IER_TOIE_SHIFT (1U) -#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) -#define RTC_IER_TAIE_MASK (0x4U) -#define RTC_IER_TAIE_SHIFT (2U) -#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) -#define RTC_IER_MOIE_MASK (0x8U) -#define RTC_IER_MOIE_SHIFT (3U) -#define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK) -#define RTC_IER_TSIE_MASK (0x10U) -#define RTC_IER_TSIE_SHIFT (4U) -#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) -#define RTC_IER_WPON_MASK (0x80U) -#define RTC_IER_WPON_SHIFT (7U) -#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) - -/*! @name TTSR - RTC Tamper Time Seconds Register */ -#define RTC_TTSR_TTS_MASK (0xFFFFFFFFU) -#define RTC_TTSR_TTS_SHIFT (0U) -#define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK) - -/*! @name MER - RTC Monotonic Enable Register */ -#define RTC_MER_MCE_MASK (0x10U) -#define RTC_MER_MCE_SHIFT (4U) -#define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK) - -/*! @name MCLR - RTC Monotonic Counter Low Register */ -#define RTC_MCLR_MCL_MASK (0xFFFFFFFFU) -#define RTC_MCLR_MCL_SHIFT (0U) -#define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK) - -/*! @name MCHR - RTC Monotonic Counter High Register */ -#define RTC_MCHR_MCH_MASK (0xFFFFFFFFU) -#define RTC_MCHR_MCH_SHIFT (0U) -#define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK) - -/*! @name WAR - RTC Write Access Register */ -#define RTC_WAR_TSRW_MASK (0x1U) -#define RTC_WAR_TSRW_SHIFT (0U) -#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) -#define RTC_WAR_TPRW_MASK (0x2U) -#define RTC_WAR_TPRW_SHIFT (1U) -#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) -#define RTC_WAR_TARW_MASK (0x4U) -#define RTC_WAR_TARW_SHIFT (2U) -#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) -#define RTC_WAR_TCRW_MASK (0x8U) -#define RTC_WAR_TCRW_SHIFT (3U) -#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) -#define RTC_WAR_CRW_MASK (0x10U) -#define RTC_WAR_CRW_SHIFT (4U) -#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) -#define RTC_WAR_SRW_MASK (0x20U) -#define RTC_WAR_SRW_SHIFT (5U) -#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) -#define RTC_WAR_LRW_MASK (0x40U) -#define RTC_WAR_LRW_SHIFT (6U) -#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) -#define RTC_WAR_IERW_MASK (0x80U) -#define RTC_WAR_IERW_SHIFT (7U) -#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) -#define RTC_WAR_TTSW_MASK (0x100U) -#define RTC_WAR_TTSW_SHIFT (8U) -#define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK) -#define RTC_WAR_MERW_MASK (0x200U) -#define RTC_WAR_MERW_SHIFT (9U) -#define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK) -#define RTC_WAR_MCLW_MASK (0x400U) -#define RTC_WAR_MCLW_SHIFT (10U) -#define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK) -#define RTC_WAR_MCHW_MASK (0x800U) -#define RTC_WAR_MCHW_SHIFT (11U) -#define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK) - -/*! @name RAR - RTC Read Access Register */ -#define RTC_RAR_TSRR_MASK (0x1U) -#define RTC_RAR_TSRR_SHIFT (0U) -#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) -#define RTC_RAR_TPRR_MASK (0x2U) -#define RTC_RAR_TPRR_SHIFT (1U) -#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) -#define RTC_RAR_TARR_MASK (0x4U) -#define RTC_RAR_TARR_SHIFT (2U) -#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) -#define RTC_RAR_TCRR_MASK (0x8U) -#define RTC_RAR_TCRR_SHIFT (3U) -#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) -#define RTC_RAR_CRR_MASK (0x10U) -#define RTC_RAR_CRR_SHIFT (4U) -#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) -#define RTC_RAR_SRR_MASK (0x20U) -#define RTC_RAR_SRR_SHIFT (5U) -#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) -#define RTC_RAR_LRR_MASK (0x40U) -#define RTC_RAR_LRR_SHIFT (6U) -#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) -#define RTC_RAR_IERR_MASK (0x80U) -#define RTC_RAR_IERR_SHIFT (7U) -#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) -#define RTC_RAR_TTSR_MASK (0x100U) -#define RTC_RAR_TTSR_SHIFT (8U) -#define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK) -#define RTC_RAR_MERR_MASK (0x200U) -#define RTC_RAR_MERR_SHIFT (9U) -#define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK) -#define RTC_RAR_MCLR_MASK (0x400U) -#define RTC_RAR_MCLR_SHIFT (10U) -#define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK) -#define RTC_RAR_MCHR_MASK (0x800U) -#define RTC_RAR_MCHR_SHIFT (11U) -#define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK) - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -/** Peripheral RTC base address */ -#define RTC_BASE (0x4003D000u) -/** Peripheral RTC base pointer */ -#define RTC ((RTC_Type *)RTC_BASE) -/** Array initializer of RTC peripheral base addresses */ -#define RTC_BASE_ADDRS { RTC_BASE } -/** Array initializer of RTC peripheral base pointers */ -#define RTC_BASE_PTRS { RTC } -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } -#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer - * @{ - */ - -/** SIM - Register Layout Typedef */ -typedef struct { - __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ - __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ - uint8_t RESERVED_0[4092]; - __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ - __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ - uint8_t RESERVED_2[4]; - __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ - uint8_t RESERVED_3[8]; - __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ - uint8_t RESERVED_4[12]; - __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ - __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ - __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ - __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ - __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ - __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ - __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ - __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ - __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ - __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ - __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ - __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ -} SIM_Type; - -/* ---------------------------------------------------------------------------- - -- SIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Register_Masks SIM Register Masks - * @{ - */ - -/*! @name SOPT1 - System Options Register 1 */ -#define SIM_SOPT1_RAMSIZE_MASK (0xF000U) -#define SIM_SOPT1_RAMSIZE_SHIFT (12U) -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK) -#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) -#define SIM_SOPT1_OSC32KSEL_SHIFT (18U) -#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) -#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) -#define SIM_SOPT1_USBVSTBY_SHIFT (29U) -#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) -#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) -#define SIM_SOPT1_USBSSTBY_SHIFT (30U) -#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) -#define SIM_SOPT1_USBREGEN_MASK (0x80000000U) -#define SIM_SOPT1_USBREGEN_SHIFT (31U) -#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) - -/*! @name SOPT1CFG - SOPT1 Configuration Register */ -#define SIM_SOPT1CFG_URWE_MASK (0x1000000U) -#define SIM_SOPT1CFG_URWE_SHIFT (24U) -#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) -#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) -#define SIM_SOPT1CFG_UVSWE_SHIFT (25U) -#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) -#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) -#define SIM_SOPT1CFG_USSWE_SHIFT (26U) -#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) - -/*! @name SOPT2 - System Options Register 2 */ -#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) -#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) -#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) -#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) -#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) -#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) -#define SIM_SOPT2_PTD7PAD_MASK (0x800U) -#define SIM_SOPT2_PTD7PAD_SHIFT (11U) -#define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK) -#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U) -#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U) -#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK) -#define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U) -#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) -#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) -#define SIM_SOPT2_USBSRC_MASK (0x40000U) -#define SIM_SOPT2_USBSRC_SHIFT (18U) -#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) - -/*! @name SOPT4 - System Options Register 4 */ -#define SIM_SOPT4_FTM0FLT0_MASK (0x1U) -#define SIM_SOPT4_FTM0FLT0_SHIFT (0U) -#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK) -#define SIM_SOPT4_FTM0FLT1_MASK (0x2U) -#define SIM_SOPT4_FTM0FLT1_SHIFT (1U) -#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK) -#define SIM_SOPT4_FTM1FLT0_MASK (0x10U) -#define SIM_SOPT4_FTM1FLT0_SHIFT (4U) -#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK) -#define SIM_SOPT4_FTM2FLT0_MASK (0x100U) -#define SIM_SOPT4_FTM2FLT0_SHIFT (8U) -#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK) -#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U) -#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U) -#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK) -#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U) -#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U) -#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK) -#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U) -#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U) -#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK) -#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U) -#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U) -#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK) -#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U) -#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U) -#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK) -#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U) -#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U) -#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK) -#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U) -#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U) -#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK) - -/*! @name SOPT5 - System Options Register 5 */ -#define SIM_SOPT5_UART0TXSRC_MASK (0x3U) -#define SIM_SOPT5_UART0TXSRC_SHIFT (0U) -#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK) -#define SIM_SOPT5_UART0RXSRC_MASK (0xCU) -#define SIM_SOPT5_UART0RXSRC_SHIFT (2U) -#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK) -#define SIM_SOPT5_UART1TXSRC_MASK (0x30U) -#define SIM_SOPT5_UART1TXSRC_SHIFT (4U) -#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK) -#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U) -#define SIM_SOPT5_UART1RXSRC_SHIFT (6U) -#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK) - -/*! @name SOPT7 - System Options Register 7 */ -#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) -#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) -#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) -#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) -#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) -#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) -#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) -#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) -#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) - -/*! @name SDID - System Device Identification Register */ -#define SIM_SDID_PINID_MASK (0xFU) -#define SIM_SDID_PINID_SHIFT (0U) -#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) -#define SIM_SDID_FAMID_MASK (0x70U) -#define SIM_SDID_FAMID_SHIFT (4U) -#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) -#define SIM_SDID_DIEID_MASK (0xF80U) -#define SIM_SDID_DIEID_SHIFT (7U) -#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) -#define SIM_SDID_REVID_MASK (0xF000U) -#define SIM_SDID_REVID_SHIFT (12U) -#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) - -/*! @name SCGC4 - System Clock Gating Control Register 4 */ -#define SIM_SCGC4_EWM_MASK (0x2U) -#define SIM_SCGC4_EWM_SHIFT (1U) -#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) -#define SIM_SCGC4_CMT_MASK (0x4U) -#define SIM_SCGC4_CMT_SHIFT (2U) -#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK) -#define SIM_SCGC4_I2C0_MASK (0x40U) -#define SIM_SCGC4_I2C0_SHIFT (6U) -#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) -#define SIM_SCGC4_I2C1_MASK (0x80U) -#define SIM_SCGC4_I2C1_SHIFT (7U) -#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) -#define SIM_SCGC4_UART0_MASK (0x400U) -#define SIM_SCGC4_UART0_SHIFT (10U) -#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) -#define SIM_SCGC4_UART1_MASK (0x800U) -#define SIM_SCGC4_UART1_SHIFT (11U) -#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) -#define SIM_SCGC4_UART2_MASK (0x1000U) -#define SIM_SCGC4_UART2_SHIFT (12U) -#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) -#define SIM_SCGC4_UART3_MASK (0x2000U) -#define SIM_SCGC4_UART3_SHIFT (13U) -#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK) -#define SIM_SCGC4_USBOTG_MASK (0x40000U) -#define SIM_SCGC4_USBOTG_SHIFT (18U) -#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) -#define SIM_SCGC4_CMP_MASK (0x80000U) -#define SIM_SCGC4_CMP_SHIFT (19U) -#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) -#define SIM_SCGC4_VREF_MASK (0x100000U) -#define SIM_SCGC4_VREF_SHIFT (20U) -#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) - -/*! @name SCGC5 - System Clock Gating Control Register 5 */ -#define SIM_SCGC5_LPTMR_MASK (0x1U) -#define SIM_SCGC5_LPTMR_SHIFT (0U) -#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) -#define SIM_SCGC5_PORTA_MASK (0x200U) -#define SIM_SCGC5_PORTA_SHIFT (9U) -#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) -#define SIM_SCGC5_PORTB_MASK (0x400U) -#define SIM_SCGC5_PORTB_SHIFT (10U) -#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) -#define SIM_SCGC5_PORTC_MASK (0x800U) -#define SIM_SCGC5_PORTC_SHIFT (11U) -#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) -#define SIM_SCGC5_PORTD_MASK (0x1000U) -#define SIM_SCGC5_PORTD_SHIFT (12U) -#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) -#define SIM_SCGC5_PORTE_MASK (0x2000U) -#define SIM_SCGC5_PORTE_SHIFT (13U) -#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) - -/*! @name SCGC6 - System Clock Gating Control Register 6 */ -#define SIM_SCGC6_FTFL_MASK (0x1U) -#define SIM_SCGC6_FTFL_SHIFT (0U) -#define SIM_SCGC6_FTFL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTFL_SHIFT)) & SIM_SCGC6_FTFL_MASK) -#define SIM_SCGC6_DMAMUX_MASK (0x2U) -#define SIM_SCGC6_DMAMUX_SHIFT (1U) -#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) -#define SIM_SCGC6_RNGA_MASK (0x200U) -#define SIM_SCGC6_RNGA_SHIFT (9U) -#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK) -#define SIM_SCGC6_SPI0_MASK (0x1000U) -#define SIM_SCGC6_SPI0_SHIFT (12U) -#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) -#define SIM_SCGC6_SPI1_MASK (0x2000U) -#define SIM_SCGC6_SPI1_SHIFT (13U) -#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK) -#define SIM_SCGC6_I2S_MASK (0x8000U) -#define SIM_SCGC6_I2S_SHIFT (15U) -#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK) -#define SIM_SCGC6_CRC_MASK (0x40000U) -#define SIM_SCGC6_CRC_SHIFT (18U) -#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) -#define SIM_SCGC6_USBDCD_MASK (0x200000U) -#define SIM_SCGC6_USBDCD_SHIFT (21U) -#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK) -#define SIM_SCGC6_PDB_MASK (0x400000U) -#define SIM_SCGC6_PDB_SHIFT (22U) -#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK) -#define SIM_SCGC6_PIT_MASK (0x800000U) -#define SIM_SCGC6_PIT_SHIFT (23U) -#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) -#define SIM_SCGC6_FTM0_MASK (0x1000000U) -#define SIM_SCGC6_FTM0_SHIFT (24U) -#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK) -#define SIM_SCGC6_FTM1_MASK (0x2000000U) -#define SIM_SCGC6_FTM1_SHIFT (25U) -#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK) -#define SIM_SCGC6_FTM2_MASK (0x4000000U) -#define SIM_SCGC6_FTM2_SHIFT (26U) -#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK) -#define SIM_SCGC6_ADC0_MASK (0x8000000U) -#define SIM_SCGC6_ADC0_SHIFT (27U) -#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) -#define SIM_SCGC6_RTC_MASK (0x20000000U) -#define SIM_SCGC6_RTC_SHIFT (29U) -#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) - -/*! @name SCGC7 - System Clock Gating Control Register 7 */ -#define SIM_SCGC7_DMA_MASK (0x2U) -#define SIM_SCGC7_DMA_SHIFT (1U) -#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) - -/*! @name CLKDIV1 - System Clock Divider Register 1 */ -#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U) -#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) -#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) -#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U) -#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U) -#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK) -#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) -#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) -#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) - -/*! @name CLKDIV2 - System Clock Divider Register 2 */ -#define SIM_CLKDIV2_USBFRAC_MASK (0x1U) -#define SIM_CLKDIV2_USBFRAC_SHIFT (0U) -#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK) -#define SIM_CLKDIV2_USBDIV_MASK (0xEU) -#define SIM_CLKDIV2_USBDIV_SHIFT (1U) -#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK) - -/*! @name FCFG1 - Flash Configuration Register 1 */ -#define SIM_FCFG1_FLASHDIS_MASK (0x1U) -#define SIM_FCFG1_FLASHDIS_SHIFT (0U) -#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) -#define SIM_FCFG1_FLASHDOZE_MASK (0x2U) -#define SIM_FCFG1_FLASHDOZE_SHIFT (1U) -#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) -#define SIM_FCFG1_DEPART_MASK (0xF00U) -#define SIM_FCFG1_DEPART_SHIFT (8U) -#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK) -#define SIM_FCFG1_EESIZE_MASK (0xF0000U) -#define SIM_FCFG1_EESIZE_SHIFT (16U) -#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK) -#define SIM_FCFG1_PFSIZE_MASK (0xF000000U) -#define SIM_FCFG1_PFSIZE_SHIFT (24U) -#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) -#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U) -#define SIM_FCFG1_NVMSIZE_SHIFT (28U) -#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK) - -/*! @name FCFG2 - Flash Configuration Register 2 */ -#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) -#define SIM_FCFG2_MAXADDR1_SHIFT (16U) -#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) -#define SIM_FCFG2_PFLSH_MASK (0x800000U) -#define SIM_FCFG2_PFLSH_SHIFT (23U) -#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK) -#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) -#define SIM_FCFG2_MAXADDR0_SHIFT (24U) -#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) -#define SIM_FCFG2_SWAPPFLSH_MASK (0x80000000U) -#define SIM_FCFG2_SWAPPFLSH_SHIFT (31U) -#define SIM_FCFG2_SWAPPFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK) - -/*! @name UIDH - Unique Identification Register High */ -#define SIM_UIDH_UID_MASK (0xFFFFFFFFU) -#define SIM_UIDH_UID_SHIFT (0U) -#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) - -/*! @name UIDMH - Unique Identification Register Mid-High */ -#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU) -#define SIM_UIDMH_UID_SHIFT (0U) -#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) - -/*! @name UIDML - Unique Identification Register Mid Low */ -#define SIM_UIDML_UID_MASK (0xFFFFFFFFU) -#define SIM_UIDML_UID_SHIFT (0U) -#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) - -/*! @name UIDL - Unique Identification Register Low */ -#define SIM_UIDL_UID_MASK (0xFFFFFFFFU) -#define SIM_UIDL_UID_SHIFT (0U) -#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) - - -/*! - * @} - */ /* end of group SIM_Register_Masks */ - - -/* SIM - Peripheral instance base addresses */ -/** Peripheral SIM base address */ -#define SIM_BASE (0x40047000u) -/** Peripheral SIM base pointer */ -#define SIM ((SIM_Type *)SIM_BASE) -/** Array initializer of SIM peripheral base addresses */ -#define SIM_BASE_ADDRS { SIM_BASE } -/** Array initializer of SIM peripheral base pointers */ -#define SIM_BASE_PTRS { SIM } - -/*! - * @} - */ /* end of group SIM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer - * @{ - */ - -/** SMC - Register Layout Typedef */ -typedef struct { - __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ - __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ - __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */ - __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ -} SMC_Type; - -/* ---------------------------------------------------------------------------- - -- SMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Register_Masks SMC Register Masks - * @{ - */ - -/*! @name PMPROT - Power Mode Protection register */ -#define SMC_PMPROT_AVLLS_MASK (0x2U) -#define SMC_PMPROT_AVLLS_SHIFT (1U) -#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) -#define SMC_PMPROT_ALLS_MASK (0x8U) -#define SMC_PMPROT_ALLS_SHIFT (3U) -#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) -#define SMC_PMPROT_AVLP_MASK (0x20U) -#define SMC_PMPROT_AVLP_SHIFT (5U) -#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) - -/*! @name PMCTRL - Power Mode Control register */ -#define SMC_PMCTRL_STOPM_MASK (0x7U) -#define SMC_PMCTRL_STOPM_SHIFT (0U) -#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) -#define SMC_PMCTRL_STOPA_MASK (0x8U) -#define SMC_PMCTRL_STOPA_SHIFT (3U) -#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) -#define SMC_PMCTRL_RUNM_MASK (0x60U) -#define SMC_PMCTRL_RUNM_SHIFT (5U) -#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) -#define SMC_PMCTRL_LPWUI_MASK (0x80U) -#define SMC_PMCTRL_LPWUI_SHIFT (7U) -#define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK) - -/*! @name VLLSCTRL - VLLS Control register */ -#define SMC_VLLSCTRL_VLLSM_MASK (0x7U) -#define SMC_VLLSCTRL_VLLSM_SHIFT (0U) -#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK) -#define SMC_VLLSCTRL_RAM2PO_MASK (0x10U) -#define SMC_VLLSCTRL_RAM2PO_SHIFT (4U) -#define SMC_VLLSCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_RAM2PO_SHIFT)) & SMC_VLLSCTRL_RAM2PO_MASK) -#define SMC_VLLSCTRL_PORPO_MASK (0x20U) -#define SMC_VLLSCTRL_PORPO_SHIFT (5U) -#define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK) - -/*! @name PMSTAT - Power Mode Status register */ -#define SMC_PMSTAT_PMSTAT_MASK (0x7FU) -#define SMC_PMSTAT_PMSTAT_SHIFT (0U) -#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) - - -/*! - * @} - */ /* end of group SMC_Register_Masks */ - - -/* SMC - Peripheral instance base addresses */ -/** Peripheral SMC base address */ -#define SMC_BASE (0x4007E000u) -/** Peripheral SMC base pointer */ -#define SMC ((SMC_Type *)SMC_BASE) -/** Array initializer of SMC peripheral base addresses */ -#define SMC_BASE_ADDRS { SMC_BASE } -/** Array initializer of SMC peripheral base pointers */ -#define SMC_BASE_PTRS { SMC } - -/*! - * @} - */ /* end of group SMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ - union { /* offset: 0xC */ - __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ - __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ - }; - uint8_t RESERVED_1[24]; - __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */ - __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ - union { /* offset: 0x34 */ - __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ - __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ - }; - __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ - __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */ - __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */ - __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */ - __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */ - uint8_t RESERVED_2[48]; - __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */ - __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */ - __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */ - __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name MCR - Module Configuration Register */ -#define SPI_MCR_HALT_MASK (0x1U) -#define SPI_MCR_HALT_SHIFT (0U) -#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) -#define SPI_MCR_SMPL_PT_MASK (0x300U) -#define SPI_MCR_SMPL_PT_SHIFT (8U) -#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) -#define SPI_MCR_CLR_RXF_MASK (0x400U) -#define SPI_MCR_CLR_RXF_SHIFT (10U) -#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) -#define SPI_MCR_CLR_TXF_MASK (0x800U) -#define SPI_MCR_CLR_TXF_SHIFT (11U) -#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) -#define SPI_MCR_DIS_RXF_MASK (0x1000U) -#define SPI_MCR_DIS_RXF_SHIFT (12U) -#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) -#define SPI_MCR_DIS_TXF_MASK (0x2000U) -#define SPI_MCR_DIS_TXF_SHIFT (13U) -#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) -#define SPI_MCR_MDIS_MASK (0x4000U) -#define SPI_MCR_MDIS_SHIFT (14U) -#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) -#define SPI_MCR_DOZE_MASK (0x8000U) -#define SPI_MCR_DOZE_SHIFT (15U) -#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) -#define SPI_MCR_PCSIS_MASK (0x1F0000U) -#define SPI_MCR_PCSIS_SHIFT (16U) -#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) -#define SPI_MCR_ROOE_MASK (0x1000000U) -#define SPI_MCR_ROOE_SHIFT (24U) -#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) -#define SPI_MCR_MTFE_MASK (0x4000000U) -#define SPI_MCR_MTFE_SHIFT (26U) -#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) -#define SPI_MCR_FRZ_MASK (0x8000000U) -#define SPI_MCR_FRZ_SHIFT (27U) -#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) -#define SPI_MCR_DCONF_MASK (0x30000000U) -#define SPI_MCR_DCONF_SHIFT (28U) -#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) -#define SPI_MCR_CONT_SCKE_MASK (0x40000000U) -#define SPI_MCR_CONT_SCKE_SHIFT (30U) -#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) -#define SPI_MCR_MSTR_MASK (0x80000000U) -#define SPI_MCR_MSTR_SHIFT (31U) -#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) - -/*! @name TCR - Transfer Count Register */ -#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) -#define SPI_TCR_SPI_TCNT_SHIFT (16U) -#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) - -/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ -#define SPI_CTAR_BR_MASK (0xFU) -#define SPI_CTAR_BR_SHIFT (0U) -#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) -#define SPI_CTAR_DT_MASK (0xF0U) -#define SPI_CTAR_DT_SHIFT (4U) -#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) -#define SPI_CTAR_ASC_MASK (0xF00U) -#define SPI_CTAR_ASC_SHIFT (8U) -#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) -#define SPI_CTAR_CSSCK_MASK (0xF000U) -#define SPI_CTAR_CSSCK_SHIFT (12U) -#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) -#define SPI_CTAR_PBR_MASK (0x30000U) -#define SPI_CTAR_PBR_SHIFT (16U) -#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) -#define SPI_CTAR_PDT_MASK (0xC0000U) -#define SPI_CTAR_PDT_SHIFT (18U) -#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) -#define SPI_CTAR_PASC_MASK (0x300000U) -#define SPI_CTAR_PASC_SHIFT (20U) -#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) -#define SPI_CTAR_PCSSCK_MASK (0xC00000U) -#define SPI_CTAR_PCSSCK_SHIFT (22U) -#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) -#define SPI_CTAR_LSBFE_MASK (0x1000000U) -#define SPI_CTAR_LSBFE_SHIFT (24U) -#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) -#define SPI_CTAR_CPHA_MASK (0x2000000U) -#define SPI_CTAR_CPHA_SHIFT (25U) -#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) -#define SPI_CTAR_CPOL_MASK (0x4000000U) -#define SPI_CTAR_CPOL_SHIFT (26U) -#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) -#define SPI_CTAR_FMSZ_MASK (0x78000000U) -#define SPI_CTAR_FMSZ_SHIFT (27U) -#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) -#define SPI_CTAR_DBR_MASK (0x80000000U) -#define SPI_CTAR_DBR_SHIFT (31U) -#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) - -/* The count of SPI_CTAR */ -#define SPI_CTAR_COUNT (2U) - -/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */ -#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) -#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) -#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) -#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) -#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) -#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) -#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U) -#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) -#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) - -/* The count of SPI_CTAR_SLAVE */ -#define SPI_CTAR_SLAVE_COUNT (1U) - -/*! @name SR - DSPI Status Register */ -#define SPI_SR_POPNXTPTR_MASK (0xFU) -#define SPI_SR_POPNXTPTR_SHIFT (0U) -#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) -#define SPI_SR_RXCTR_MASK (0xF0U) -#define SPI_SR_RXCTR_SHIFT (4U) -#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) -#define SPI_SR_TXNXTPTR_MASK (0xF00U) -#define SPI_SR_TXNXTPTR_SHIFT (8U) -#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) -#define SPI_SR_TXCTR_MASK (0xF000U) -#define SPI_SR_TXCTR_SHIFT (12U) -#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) -#define SPI_SR_RFDF_MASK (0x20000U) -#define SPI_SR_RFDF_SHIFT (17U) -#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) -#define SPI_SR_RFOF_MASK (0x80000U) -#define SPI_SR_RFOF_SHIFT (19U) -#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) -#define SPI_SR_TFFF_MASK (0x2000000U) -#define SPI_SR_TFFF_SHIFT (25U) -#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) -#define SPI_SR_TFUF_MASK (0x8000000U) -#define SPI_SR_TFUF_SHIFT (27U) -#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) -#define SPI_SR_EOQF_MASK (0x10000000U) -#define SPI_SR_EOQF_SHIFT (28U) -#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) -#define SPI_SR_TXRXS_MASK (0x40000000U) -#define SPI_SR_TXRXS_SHIFT (30U) -#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) -#define SPI_SR_TCF_MASK (0x80000000U) -#define SPI_SR_TCF_SHIFT (31U) -#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) - -/*! @name RSER - DMA/Interrupt Request Select and Enable Register */ -#define SPI_RSER_RFDF_DIRS_MASK (0x10000U) -#define SPI_RSER_RFDF_DIRS_SHIFT (16U) -#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) -#define SPI_RSER_RFDF_RE_MASK (0x20000U) -#define SPI_RSER_RFDF_RE_SHIFT (17U) -#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) -#define SPI_RSER_RFOF_RE_MASK (0x80000U) -#define SPI_RSER_RFOF_RE_SHIFT (19U) -#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) -#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) -#define SPI_RSER_TFFF_DIRS_SHIFT (24U) -#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) -#define SPI_RSER_TFFF_RE_MASK (0x2000000U) -#define SPI_RSER_TFFF_RE_SHIFT (25U) -#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) -#define SPI_RSER_TFUF_RE_MASK (0x8000000U) -#define SPI_RSER_TFUF_RE_SHIFT (27U) -#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) -#define SPI_RSER_EOQF_RE_MASK (0x10000000U) -#define SPI_RSER_EOQF_RE_SHIFT (28U) -#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) -#define SPI_RSER_TCF_RE_MASK (0x80000000U) -#define SPI_RSER_TCF_RE_SHIFT (31U) -#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) - -/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ -#define SPI_PUSHR_TXDATA_MASK (0xFFFFU) -#define SPI_PUSHR_TXDATA_SHIFT (0U) -#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) -#define SPI_PUSHR_PCS_MASK (0x3F0000U) -#define SPI_PUSHR_PCS_SHIFT (16U) -#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) -#define SPI_PUSHR_CTCNT_MASK (0x4000000U) -#define SPI_PUSHR_CTCNT_SHIFT (26U) -#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) -#define SPI_PUSHR_EOQ_MASK (0x8000000U) -#define SPI_PUSHR_EOQ_SHIFT (27U) -#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) -#define SPI_PUSHR_CTAS_MASK (0x70000000U) -#define SPI_PUSHR_CTAS_SHIFT (28U) -#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) -#define SPI_PUSHR_CONT_MASK (0x80000000U) -#define SPI_PUSHR_CONT_SHIFT (31U) -#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) - -/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ -#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU) -#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) -#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) - -/*! @name POPR - POP RX FIFO Register */ -#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) -#define SPI_POPR_RXDATA_SHIFT (0U) -#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) - -/*! @name TXFR0 - DSPI Transmit FIFO Registers */ -#define SPI_TXFR0_TXDATA_MASK (0xFFFFU) -#define SPI_TXFR0_TXDATA_SHIFT (0U) -#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) -#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) -#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) -#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) - -/*! @name TXFR1 - DSPI Transmit FIFO Registers */ -#define SPI_TXFR1_TXDATA_MASK (0xFFFFU) -#define SPI_TXFR1_TXDATA_SHIFT (0U) -#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) -#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) -#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) -#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) - -/*! @name TXFR2 - DSPI Transmit FIFO Registers */ -#define SPI_TXFR2_TXDATA_MASK (0xFFFFU) -#define SPI_TXFR2_TXDATA_SHIFT (0U) -#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) -#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) -#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) -#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) - -/*! @name TXFR3 - DSPI Transmit FIFO Registers */ -#define SPI_TXFR3_TXDATA_MASK (0xFFFFU) -#define SPI_TXFR3_TXDATA_SHIFT (0U) -#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) -#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) -#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) -#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) - -/*! @name RXFR0 - DSPI Receive FIFO Registers */ -#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) -#define SPI_RXFR0_RXDATA_SHIFT (0U) -#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) - -/*! @name RXFR1 - DSPI Receive FIFO Registers */ -#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) -#define SPI_RXFR1_RXDATA_SHIFT (0U) -#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) - -/*! @name RXFR2 - DSPI Receive FIFO Registers */ -#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) -#define SPI_RXFR2_RXDATA_SHIFT (0U) -#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) - -/*! @name RXFR3 - DSPI Receive FIFO Registers */ -#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) -#define SPI_RXFR3_RXDATA_SHIFT (0U) -#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -/** Peripheral SPI0 base address */ -#define SPI0_BASE (0x4002C000u) -/** Peripheral SPI0 base pointer */ -#define SPI0 ((SPI_Type *)SPI0_BASE) -/** Peripheral SPI1 base address */ -#define SPI1_BASE (0x4002D000u) -/** Peripheral SPI1 base pointer */ -#define SPI1 ((SPI_Type *)SPI1_BASE) -/** Array initializer of SPI peripheral base addresses */ -#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } -/** Array initializer of SPI peripheral base pointers */ -#define SPI_BASE_PTRS { SPI0, SPI1 } -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer - * @{ - */ - -/** UART - Register Layout Typedef */ -typedef struct { - __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ - __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ - __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ - __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ - __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ - __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ - __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ - __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ - __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ - __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ - __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ - __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ - __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ - __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ - __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ - uint8_t RESERVED_0[1]; - __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ - __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ - __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ - __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ - __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ - __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ - __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ - uint8_t RESERVED_1[1]; - __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ - __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ - __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ - union { /* offset: 0x1B */ - __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ - __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ - }; - __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ - __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ - __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ - __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ -} UART_Type; - -/* ---------------------------------------------------------------------------- - -- UART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UART_Register_Masks UART Register Masks - * @{ - */ - -/*! @name BDH - UART Baud Rate Registers: High */ -#define UART_BDH_SBR_MASK (0x1FU) -#define UART_BDH_SBR_SHIFT (0U) -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) -#define UART_BDH_RXEDGIE_MASK (0x40U) -#define UART_BDH_RXEDGIE_SHIFT (6U) -#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) -#define UART_BDH_LBKDIE_MASK (0x80U) -#define UART_BDH_LBKDIE_SHIFT (7U) -#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) - -/*! @name BDL - UART Baud Rate Registers: Low */ -#define UART_BDL_SBR_MASK (0xFFU) -#define UART_BDL_SBR_SHIFT (0U) -#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) - -/*! @name C1 - UART Control Register 1 */ -#define UART_C1_PT_MASK (0x1U) -#define UART_C1_PT_SHIFT (0U) -#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) -#define UART_C1_PE_MASK (0x2U) -#define UART_C1_PE_SHIFT (1U) -#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) -#define UART_C1_ILT_MASK (0x4U) -#define UART_C1_ILT_SHIFT (2U) -#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) -#define UART_C1_WAKE_MASK (0x8U) -#define UART_C1_WAKE_SHIFT (3U) -#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) -#define UART_C1_M_MASK (0x10U) -#define UART_C1_M_SHIFT (4U) -#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) -#define UART_C1_RSRC_MASK (0x20U) -#define UART_C1_RSRC_SHIFT (5U) -#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) -#define UART_C1_UARTSWAI_MASK (0x40U) -#define UART_C1_UARTSWAI_SHIFT (6U) -#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) -#define UART_C1_LOOPS_MASK (0x80U) -#define UART_C1_LOOPS_SHIFT (7U) -#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) - -/*! @name C2 - UART Control Register 2 */ -#define UART_C2_SBK_MASK (0x1U) -#define UART_C2_SBK_SHIFT (0U) -#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) -#define UART_C2_RWU_MASK (0x2U) -#define UART_C2_RWU_SHIFT (1U) -#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) -#define UART_C2_RE_MASK (0x4U) -#define UART_C2_RE_SHIFT (2U) -#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) -#define UART_C2_TE_MASK (0x8U) -#define UART_C2_TE_SHIFT (3U) -#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) -#define UART_C2_ILIE_MASK (0x10U) -#define UART_C2_ILIE_SHIFT (4U) -#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) -#define UART_C2_RIE_MASK (0x20U) -#define UART_C2_RIE_SHIFT (5U) -#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) -#define UART_C2_TCIE_MASK (0x40U) -#define UART_C2_TCIE_SHIFT (6U) -#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) -#define UART_C2_TIE_MASK (0x80U) -#define UART_C2_TIE_SHIFT (7U) -#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) - -/*! @name S1 - UART Status Register 1 */ -#define UART_S1_PF_MASK (0x1U) -#define UART_S1_PF_SHIFT (0U) -#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) -#define UART_S1_FE_MASK (0x2U) -#define UART_S1_FE_SHIFT (1U) -#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) -#define UART_S1_NF_MASK (0x4U) -#define UART_S1_NF_SHIFT (2U) -#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) -#define UART_S1_OR_MASK (0x8U) -#define UART_S1_OR_SHIFT (3U) -#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) -#define UART_S1_IDLE_MASK (0x10U) -#define UART_S1_IDLE_SHIFT (4U) -#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) -#define UART_S1_RDRF_MASK (0x20U) -#define UART_S1_RDRF_SHIFT (5U) -#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) -#define UART_S1_TC_MASK (0x40U) -#define UART_S1_TC_SHIFT (6U) -#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) -#define UART_S1_TDRE_MASK (0x80U) -#define UART_S1_TDRE_SHIFT (7U) -#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) - -/*! @name S2 - UART Status Register 2 */ -#define UART_S2_RAF_MASK (0x1U) -#define UART_S2_RAF_SHIFT (0U) -#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) -#define UART_S2_LBKDE_MASK (0x2U) -#define UART_S2_LBKDE_SHIFT (1U) -#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) -#define UART_S2_BRK13_MASK (0x4U) -#define UART_S2_BRK13_SHIFT (2U) -#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) -#define UART_S2_RWUID_MASK (0x8U) -#define UART_S2_RWUID_SHIFT (3U) -#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) -#define UART_S2_RXINV_MASK (0x10U) -#define UART_S2_RXINV_SHIFT (4U) -#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) -#define UART_S2_MSBF_MASK (0x20U) -#define UART_S2_MSBF_SHIFT (5U) -#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) -#define UART_S2_RXEDGIF_MASK (0x40U) -#define UART_S2_RXEDGIF_SHIFT (6U) -#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) -#define UART_S2_LBKDIF_MASK (0x80U) -#define UART_S2_LBKDIF_SHIFT (7U) -#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) - -/*! @name C3 - UART Control Register 3 */ -#define UART_C3_PEIE_MASK (0x1U) -#define UART_C3_PEIE_SHIFT (0U) -#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) -#define UART_C3_FEIE_MASK (0x2U) -#define UART_C3_FEIE_SHIFT (1U) -#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) -#define UART_C3_NEIE_MASK (0x4U) -#define UART_C3_NEIE_SHIFT (2U) -#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) -#define UART_C3_ORIE_MASK (0x8U) -#define UART_C3_ORIE_SHIFT (3U) -#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) -#define UART_C3_TXINV_MASK (0x10U) -#define UART_C3_TXINV_SHIFT (4U) -#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) -#define UART_C3_TXDIR_MASK (0x20U) -#define UART_C3_TXDIR_SHIFT (5U) -#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) -#define UART_C3_T8_MASK (0x40U) -#define UART_C3_T8_SHIFT (6U) -#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) -#define UART_C3_R8_MASK (0x80U) -#define UART_C3_R8_SHIFT (7U) -#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) - -/*! @name D - UART Data Register */ -#define UART_D_RT_MASK (0xFFU) -#define UART_D_RT_SHIFT (0U) -#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) - -/*! @name MA1 - UART Match Address Registers 1 */ -#define UART_MA1_MA_MASK (0xFFU) -#define UART_MA1_MA_SHIFT (0U) -#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) - -/*! @name MA2 - UART Match Address Registers 2 */ -#define UART_MA2_MA_MASK (0xFFU) -#define UART_MA2_MA_SHIFT (0U) -#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) - -/*! @name C4 - UART Control Register 4 */ -#define UART_C4_BRFA_MASK (0x1FU) -#define UART_C4_BRFA_SHIFT (0U) -#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) -#define UART_C4_M10_MASK (0x20U) -#define UART_C4_M10_SHIFT (5U) -#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) -#define UART_C4_MAEN2_MASK (0x40U) -#define UART_C4_MAEN2_SHIFT (6U) -#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) -#define UART_C4_MAEN1_MASK (0x80U) -#define UART_C4_MAEN1_SHIFT (7U) -#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) - -/*! @name C5 - UART Control Register 5 */ -#define UART_C5_RDMAS_MASK (0x20U) -#define UART_C5_RDMAS_SHIFT (5U) -#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) -#define UART_C5_TDMAS_MASK (0x80U) -#define UART_C5_TDMAS_SHIFT (7U) -#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) - -/*! @name ED - UART Extended Data Register */ -#define UART_ED_PARITYE_MASK (0x40U) -#define UART_ED_PARITYE_SHIFT (6U) -#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK) -#define UART_ED_NOISY_MASK (0x80U) -#define UART_ED_NOISY_SHIFT (7U) -#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK) - -/*! @name MODEM - UART Modem Register */ -#define UART_MODEM_TXCTSE_MASK (0x1U) -#define UART_MODEM_TXCTSE_SHIFT (0U) -#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK) -#define UART_MODEM_TXRTSE_MASK (0x2U) -#define UART_MODEM_TXRTSE_SHIFT (1U) -#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK) -#define UART_MODEM_TXRTSPOL_MASK (0x4U) -#define UART_MODEM_TXRTSPOL_SHIFT (2U) -#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK) -#define UART_MODEM_RXRTSE_MASK (0x8U) -#define UART_MODEM_RXRTSE_SHIFT (3U) -#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK) - -/*! @name IR - UART Infrared Register */ -#define UART_IR_TNP_MASK (0x3U) -#define UART_IR_TNP_SHIFT (0U) -#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK) -#define UART_IR_IREN_MASK (0x4U) -#define UART_IR_IREN_SHIFT (2U) -#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK) - -/*! @name PFIFO - UART FIFO Parameters */ -#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U) -#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U) -#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK) -#define UART_PFIFO_RXFE_MASK (0x8U) -#define UART_PFIFO_RXFE_SHIFT (3U) -#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK) -#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U) -#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U) -#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK) -#define UART_PFIFO_TXFE_MASK (0x80U) -#define UART_PFIFO_TXFE_SHIFT (7U) -#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK) - -/*! @name CFIFO - UART FIFO Control Register */ -#define UART_CFIFO_RXUFE_MASK (0x1U) -#define UART_CFIFO_RXUFE_SHIFT (0U) -#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK) -#define UART_CFIFO_TXOFE_MASK (0x2U) -#define UART_CFIFO_TXOFE_SHIFT (1U) -#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK) -#define UART_CFIFO_RXOFE_MASK (0x4U) -#define UART_CFIFO_RXOFE_SHIFT (2U) -#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK) -#define UART_CFIFO_RXFLUSH_MASK (0x40U) -#define UART_CFIFO_RXFLUSH_SHIFT (6U) -#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK) -#define UART_CFIFO_TXFLUSH_MASK (0x80U) -#define UART_CFIFO_TXFLUSH_SHIFT (7U) -#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK) - -/*! @name SFIFO - UART FIFO Status Register */ -#define UART_SFIFO_RXUF_MASK (0x1U) -#define UART_SFIFO_RXUF_SHIFT (0U) -#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK) -#define UART_SFIFO_TXOF_MASK (0x2U) -#define UART_SFIFO_TXOF_SHIFT (1U) -#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK) -#define UART_SFIFO_RXOF_MASK (0x4U) -#define UART_SFIFO_RXOF_SHIFT (2U) -#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK) -#define UART_SFIFO_RXEMPT_MASK (0x40U) -#define UART_SFIFO_RXEMPT_SHIFT (6U) -#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK) -#define UART_SFIFO_TXEMPT_MASK (0x80U) -#define UART_SFIFO_TXEMPT_SHIFT (7U) -#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK) - -/*! @name TWFIFO - UART FIFO Transmit Watermark */ -#define UART_TWFIFO_TXWATER_MASK (0xFFU) -#define UART_TWFIFO_TXWATER_SHIFT (0U) -#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK) - -/*! @name TCFIFO - UART FIFO Transmit Count */ -#define UART_TCFIFO_TXCOUNT_MASK (0xFFU) -#define UART_TCFIFO_TXCOUNT_SHIFT (0U) -#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK) - -/*! @name RWFIFO - UART FIFO Receive Watermark */ -#define UART_RWFIFO_RXWATER_MASK (0xFFU) -#define UART_RWFIFO_RXWATER_SHIFT (0U) -#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK) - -/*! @name RCFIFO - UART FIFO Receive Count */ -#define UART_RCFIFO_RXCOUNT_MASK (0xFFU) -#define UART_RCFIFO_RXCOUNT_SHIFT (0U) -#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK) - -/*! @name C7816 - UART 7816 Control Register */ -#define UART_C7816_ISO_7816E_MASK (0x1U) -#define UART_C7816_ISO_7816E_SHIFT (0U) -#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) -#define UART_C7816_TTYPE_MASK (0x2U) -#define UART_C7816_TTYPE_SHIFT (1U) -#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) -#define UART_C7816_INIT_MASK (0x4U) -#define UART_C7816_INIT_SHIFT (2U) -#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) -#define UART_C7816_ANACK_MASK (0x8U) -#define UART_C7816_ANACK_SHIFT (3U) -#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) -#define UART_C7816_ONACK_MASK (0x10U) -#define UART_C7816_ONACK_SHIFT (4U) -#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) - -/*! @name IE7816 - UART 7816 Interrupt Enable Register */ -#define UART_IE7816_RXTE_MASK (0x1U) -#define UART_IE7816_RXTE_SHIFT (0U) -#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) -#define UART_IE7816_TXTE_MASK (0x2U) -#define UART_IE7816_TXTE_SHIFT (1U) -#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) -#define UART_IE7816_GTVE_MASK (0x4U) -#define UART_IE7816_GTVE_SHIFT (2U) -#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) -#define UART_IE7816_INITDE_MASK (0x10U) -#define UART_IE7816_INITDE_SHIFT (4U) -#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) -#define UART_IE7816_BWTE_MASK (0x20U) -#define UART_IE7816_BWTE_SHIFT (5U) -#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) -#define UART_IE7816_CWTE_MASK (0x40U) -#define UART_IE7816_CWTE_SHIFT (6U) -#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) -#define UART_IE7816_WTE_MASK (0x80U) -#define UART_IE7816_WTE_SHIFT (7U) -#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) - -/*! @name IS7816 - UART 7816 Interrupt Status Register */ -#define UART_IS7816_RXT_MASK (0x1U) -#define UART_IS7816_RXT_SHIFT (0U) -#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) -#define UART_IS7816_TXT_MASK (0x2U) -#define UART_IS7816_TXT_SHIFT (1U) -#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) -#define UART_IS7816_GTV_MASK (0x4U) -#define UART_IS7816_GTV_SHIFT (2U) -#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) -#define UART_IS7816_INITD_MASK (0x10U) -#define UART_IS7816_INITD_SHIFT (4U) -#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) -#define UART_IS7816_BWT_MASK (0x20U) -#define UART_IS7816_BWT_SHIFT (5U) -#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) -#define UART_IS7816_CWT_MASK (0x40U) -#define UART_IS7816_CWT_SHIFT (6U) -#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) -#define UART_IS7816_WT_MASK (0x80U) -#define UART_IS7816_WT_SHIFT (7U) -#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) - -/*! @name WP7816T0 - UART 7816 Wait Parameter Register */ -#define UART_WP7816T0_WI_MASK (0xFFU) -#define UART_WP7816T0_WI_SHIFT (0U) -#define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK) - -/*! @name WP7816T1 - UART 7816 Wait Parameter Register */ -#define UART_WP7816T1_BWI_MASK (0xFU) -#define UART_WP7816T1_BWI_SHIFT (0U) -#define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK) -#define UART_WP7816T1_CWI_MASK (0xF0U) -#define UART_WP7816T1_CWI_SHIFT (4U) -#define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK) - -/*! @name WN7816 - UART 7816 Wait N Register */ -#define UART_WN7816_GTN_MASK (0xFFU) -#define UART_WN7816_GTN_SHIFT (0U) -#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) - -/*! @name WF7816 - UART 7816 Wait FD Register */ -#define UART_WF7816_GTFD_MASK (0xFFU) -#define UART_WF7816_GTFD_SHIFT (0U) -#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) - -/*! @name ET7816 - UART 7816 Error Threshold Register */ -#define UART_ET7816_RXTHRESHOLD_MASK (0xFU) -#define UART_ET7816_RXTHRESHOLD_SHIFT (0U) -#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) -#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) -#define UART_ET7816_TXTHRESHOLD_SHIFT (4U) -#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) - -/*! @name TL7816 - UART 7816 Transmit Length Register */ -#define UART_TL7816_TLEN_MASK (0xFFU) -#define UART_TL7816_TLEN_SHIFT (0U) -#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) - - -/*! - * @} - */ /* end of group UART_Register_Masks */ - - -/* UART - Peripheral instance base addresses */ -/** Peripheral UART0 base address */ -#define UART0_BASE (0x4006A000u) -/** Peripheral UART0 base pointer */ -#define UART0 ((UART_Type *)UART0_BASE) -/** Peripheral UART1 base address */ -#define UART1_BASE (0x4006B000u) -/** Peripheral UART1 base pointer */ -#define UART1 ((UART_Type *)UART1_BASE) -/** Peripheral UART2 base address */ -#define UART2_BASE (0x4006C000u) -/** Peripheral UART2 base pointer */ -#define UART2 ((UART_Type *)UART2_BASE) -/** Array initializer of UART peripheral base addresses */ -#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE } -/** Array initializer of UART peripheral base pointers */ -#define UART_BASE_PTRS { UART0, UART1, UART2 } -/** Interrupt vectors for the UART peripheral type */ -#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn } -#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn } - -/*! - * @} - */ /* end of group UART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ - uint8_t RESERVED_0[3]; - __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ - uint8_t RESERVED_1[3]; - __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ - uint8_t RESERVED_2[3]; - __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ - uint8_t RESERVED_3[3]; - __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ - uint8_t RESERVED_4[3]; - __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */ - uint8_t RESERVED_5[3]; - __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ - uint8_t RESERVED_6[3]; - __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ - uint8_t RESERVED_7[99]; - __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ - uint8_t RESERVED_8[3]; - __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ - uint8_t RESERVED_9[3]; - __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ - uint8_t RESERVED_10[3]; - __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ - uint8_t RESERVED_11[3]; - __I uint8_t STAT; /**< Status register, offset: 0x90 */ - uint8_t RESERVED_12[3]; - __IO uint8_t CTL; /**< Control register, offset: 0x94 */ - uint8_t RESERVED_13[3]; - __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ - uint8_t RESERVED_14[3]; - __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */ - uint8_t RESERVED_15[3]; - __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ - uint8_t RESERVED_16[3]; - __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ - uint8_t RESERVED_17[3]; - __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ - uint8_t RESERVED_18[3]; - __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */ - uint8_t RESERVED_19[3]; - __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ - uint8_t RESERVED_20[3]; - __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ - uint8_t RESERVED_21[11]; - struct { /* offset: 0xC0, array step: 0x4 */ - __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_0[3]; - } ENDPOINT[16]; - __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ - uint8_t RESERVED_22[3]; - __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ - uint8_t RESERVED_23[3]; - __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ - uint8_t RESERVED_24[3]; - __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */ - uint8_t RESERVED_25[7]; - __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name PERID - Peripheral ID register */ -#define USB_PERID_ID_MASK (0x3FU) -#define USB_PERID_ID_SHIFT (0U) -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) - -/*! @name IDCOMP - Peripheral ID Complement register */ -#define USB_IDCOMP_NID_MASK (0x3FU) -#define USB_IDCOMP_NID_SHIFT (0U) -#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) - -/*! @name REV - Peripheral Revision register */ -#define USB_REV_REV_MASK (0xFFU) -#define USB_REV_REV_SHIFT (0U) -#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) - -/*! @name ADDINFO - Peripheral Additional Info register */ -#define USB_ADDINFO_IEHOST_MASK (0x1U) -#define USB_ADDINFO_IEHOST_SHIFT (0U) -#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) -#define USB_ADDINFO_IRQNUM_MASK (0xF8U) -#define USB_ADDINFO_IRQNUM_SHIFT (3U) -#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK) - -/*! @name OTGISTAT - OTG Interrupt Status register */ -#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U) -#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U) -#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK) -#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U) -#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U) -#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK) -#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U) -#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U) -#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK) -#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) -#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) -#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) -#define USB_OTGISTAT_ONEMSEC_MASK (0x40U) -#define USB_OTGISTAT_ONEMSEC_SHIFT (6U) -#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) -#define USB_OTGISTAT_IDCHG_MASK (0x80U) -#define USB_OTGISTAT_IDCHG_SHIFT (7U) -#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK) - -/*! @name OTGICR - OTG Interrupt Control Register */ -#define USB_OTGICR_AVBUSEN_MASK (0x1U) -#define USB_OTGICR_AVBUSEN_SHIFT (0U) -#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK) -#define USB_OTGICR_BSESSEN_MASK (0x4U) -#define USB_OTGICR_BSESSEN_SHIFT (2U) -#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK) -#define USB_OTGICR_SESSVLDEN_MASK (0x8U) -#define USB_OTGICR_SESSVLDEN_SHIFT (3U) -#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK) -#define USB_OTGICR_LINESTATEEN_MASK (0x20U) -#define USB_OTGICR_LINESTATEEN_SHIFT (5U) -#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) -#define USB_OTGICR_ONEMSECEN_MASK (0x40U) -#define USB_OTGICR_ONEMSECEN_SHIFT (6U) -#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) -#define USB_OTGICR_IDEN_MASK (0x80U) -#define USB_OTGICR_IDEN_SHIFT (7U) -#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK) - -/*! @name OTGSTAT - OTG Status register */ -#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U) -#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U) -#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK) -#define USB_OTGSTAT_BSESSEND_MASK (0x4U) -#define USB_OTGSTAT_BSESSEND_SHIFT (2U) -#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK) -#define USB_OTGSTAT_SESS_VLD_MASK (0x8U) -#define USB_OTGSTAT_SESS_VLD_SHIFT (3U) -#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK) -#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) -#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) -#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) -#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) -#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) -#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) -#define USB_OTGSTAT_ID_MASK (0x80U) -#define USB_OTGSTAT_ID_SHIFT (7U) -#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK) - -/*! @name OTGCTL - OTG Control register */ -#define USB_OTGCTL_OTGEN_MASK (0x4U) -#define USB_OTGCTL_OTGEN_SHIFT (2U) -#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) -#define USB_OTGCTL_DMLOW_MASK (0x10U) -#define USB_OTGCTL_DMLOW_SHIFT (4U) -#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) -#define USB_OTGCTL_DPLOW_MASK (0x20U) -#define USB_OTGCTL_DPLOW_SHIFT (5U) -#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) -#define USB_OTGCTL_DPHIGH_MASK (0x80U) -#define USB_OTGCTL_DPHIGH_SHIFT (7U) -#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) - -/*! @name ISTAT - Interrupt Status register */ -#define USB_ISTAT_USBRST_MASK (0x1U) -#define USB_ISTAT_USBRST_SHIFT (0U) -#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) -#define USB_ISTAT_ERROR_MASK (0x2U) -#define USB_ISTAT_ERROR_SHIFT (1U) -#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) -#define USB_ISTAT_SOFTOK_MASK (0x4U) -#define USB_ISTAT_SOFTOK_SHIFT (2U) -#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) -#define USB_ISTAT_TOKDNE_MASK (0x8U) -#define USB_ISTAT_TOKDNE_SHIFT (3U) -#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) -#define USB_ISTAT_SLEEP_MASK (0x10U) -#define USB_ISTAT_SLEEP_SHIFT (4U) -#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) -#define USB_ISTAT_RESUME_MASK (0x20U) -#define USB_ISTAT_RESUME_SHIFT (5U) -#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) -#define USB_ISTAT_ATTACH_MASK (0x40U) -#define USB_ISTAT_ATTACH_SHIFT (6U) -#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) -#define USB_ISTAT_STALL_MASK (0x80U) -#define USB_ISTAT_STALL_SHIFT (7U) -#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) - -/*! @name INTEN - Interrupt Enable register */ -#define USB_INTEN_USBRSTEN_MASK (0x1U) -#define USB_INTEN_USBRSTEN_SHIFT (0U) -#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) -#define USB_INTEN_ERROREN_MASK (0x2U) -#define USB_INTEN_ERROREN_SHIFT (1U) -#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) -#define USB_INTEN_SOFTOKEN_MASK (0x4U) -#define USB_INTEN_SOFTOKEN_SHIFT (2U) -#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) -#define USB_INTEN_TOKDNEEN_MASK (0x8U) -#define USB_INTEN_TOKDNEEN_SHIFT (3U) -#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) -#define USB_INTEN_SLEEPEN_MASK (0x10U) -#define USB_INTEN_SLEEPEN_SHIFT (4U) -#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) -#define USB_INTEN_RESUMEEN_MASK (0x20U) -#define USB_INTEN_RESUMEEN_SHIFT (5U) -#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) -#define USB_INTEN_ATTACHEN_MASK (0x40U) -#define USB_INTEN_ATTACHEN_SHIFT (6U) -#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) -#define USB_INTEN_STALLEN_MASK (0x80U) -#define USB_INTEN_STALLEN_SHIFT (7U) -#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) - -/*! @name ERRSTAT - Error Interrupt Status register */ -#define USB_ERRSTAT_PIDERR_MASK (0x1U) -#define USB_ERRSTAT_PIDERR_SHIFT (0U) -#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) -#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) -#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) -#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) -#define USB_ERRSTAT_CRC16_MASK (0x4U) -#define USB_ERRSTAT_CRC16_SHIFT (2U) -#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) -#define USB_ERRSTAT_DFN8_MASK (0x8U) -#define USB_ERRSTAT_DFN8_SHIFT (3U) -#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) -#define USB_ERRSTAT_BTOERR_MASK (0x10U) -#define USB_ERRSTAT_BTOERR_SHIFT (4U) -#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) -#define USB_ERRSTAT_DMAERR_MASK (0x20U) -#define USB_ERRSTAT_DMAERR_SHIFT (5U) -#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) -#define USB_ERRSTAT_BTSERR_MASK (0x80U) -#define USB_ERRSTAT_BTSERR_SHIFT (7U) -#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) - -/*! @name ERREN - Error Interrupt Enable register */ -#define USB_ERREN_PIDERREN_MASK (0x1U) -#define USB_ERREN_PIDERREN_SHIFT (0U) -#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) -#define USB_ERREN_CRC5EOFEN_MASK (0x2U) -#define USB_ERREN_CRC5EOFEN_SHIFT (1U) -#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) -#define USB_ERREN_CRC16EN_MASK (0x4U) -#define USB_ERREN_CRC16EN_SHIFT (2U) -#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) -#define USB_ERREN_DFN8EN_MASK (0x8U) -#define USB_ERREN_DFN8EN_SHIFT (3U) -#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) -#define USB_ERREN_BTOERREN_MASK (0x10U) -#define USB_ERREN_BTOERREN_SHIFT (4U) -#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) -#define USB_ERREN_DMAERREN_MASK (0x20U) -#define USB_ERREN_DMAERREN_SHIFT (5U) -#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) -#define USB_ERREN_BTSERREN_MASK (0x80U) -#define USB_ERREN_BTSERREN_SHIFT (7U) -#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) - -/*! @name STAT - Status register */ -#define USB_STAT_ODD_MASK (0x4U) -#define USB_STAT_ODD_SHIFT (2U) -#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) -#define USB_STAT_TX_MASK (0x8U) -#define USB_STAT_TX_SHIFT (3U) -#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) -#define USB_STAT_ENDP_MASK (0xF0U) -#define USB_STAT_ENDP_SHIFT (4U) -#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) - -/*! @name CTL - Control register */ -#define USB_CTL_USBENSOFEN_MASK (0x1U) -#define USB_CTL_USBENSOFEN_SHIFT (0U) -#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) -#define USB_CTL_ODDRST_MASK (0x2U) -#define USB_CTL_ODDRST_SHIFT (1U) -#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) -#define USB_CTL_RESUME_MASK (0x4U) -#define USB_CTL_RESUME_SHIFT (2U) -#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) -#define USB_CTL_HOSTMODEEN_MASK (0x8U) -#define USB_CTL_HOSTMODEEN_SHIFT (3U) -#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) -#define USB_CTL_RESET_MASK (0x10U) -#define USB_CTL_RESET_SHIFT (4U) -#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) -#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) -#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) -#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) -#define USB_CTL_SE0_MASK (0x40U) -#define USB_CTL_SE0_SHIFT (6U) -#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) -#define USB_CTL_JSTATE_MASK (0x80U) -#define USB_CTL_JSTATE_SHIFT (7U) -#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) - -/*! @name ADDR - Address register */ -#define USB_ADDR_ADDR_MASK (0x7FU) -#define USB_ADDR_ADDR_SHIFT (0U) -#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) -#define USB_ADDR_LSEN_MASK (0x80U) -#define USB_ADDR_LSEN_SHIFT (7U) -#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) - -/*! @name BDTPAGE1 - BDT Page Register 1 */ -#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) -#define USB_BDTPAGE1_BDTBA_SHIFT (1U) -#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) - -/*! @name FRMNUML - Frame Number Register Low */ -#define USB_FRMNUML_FRM_MASK (0xFFU) -#define USB_FRMNUML_FRM_SHIFT (0U) -#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) - -/*! @name FRMNUMH - Frame Number Register High */ -#define USB_FRMNUMH_FRM_MASK (0x7U) -#define USB_FRMNUMH_FRM_SHIFT (0U) -#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) - -/*! @name TOKEN - Token register */ -#define USB_TOKEN_TOKENENDPT_MASK (0xFU) -#define USB_TOKEN_TOKENENDPT_SHIFT (0U) -#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) -#define USB_TOKEN_TOKENPID_MASK (0xF0U) -#define USB_TOKEN_TOKENPID_SHIFT (4U) -#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) - -/*! @name SOFTHLD - SOF Threshold Register */ -#define USB_SOFTHLD_CNT_MASK (0xFFU) -#define USB_SOFTHLD_CNT_SHIFT (0U) -#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) - -/*! @name BDTPAGE2 - BDT Page Register 2 */ -#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) -#define USB_BDTPAGE2_BDTBA_SHIFT (0U) -#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) - -/*! @name BDTPAGE3 - BDT Page Register 3 */ -#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) -#define USB_BDTPAGE3_BDTBA_SHIFT (0U) -#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) - -/*! @name ENDPT - Endpoint Control register */ -#define USB_ENDPT_EPHSHK_MASK (0x1U) -#define USB_ENDPT_EPHSHK_SHIFT (0U) -#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) -#define USB_ENDPT_EPSTALL_MASK (0x2U) -#define USB_ENDPT_EPSTALL_SHIFT (1U) -#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) -#define USB_ENDPT_EPTXEN_MASK (0x4U) -#define USB_ENDPT_EPTXEN_SHIFT (2U) -#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) -#define USB_ENDPT_EPRXEN_MASK (0x8U) -#define USB_ENDPT_EPRXEN_SHIFT (3U) -#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) -#define USB_ENDPT_EPCTLDIS_MASK (0x10U) -#define USB_ENDPT_EPCTLDIS_SHIFT (4U) -#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) -#define USB_ENDPT_RETRYDIS_MASK (0x40U) -#define USB_ENDPT_RETRYDIS_SHIFT (6U) -#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) -#define USB_ENDPT_HOSTWOHUB_MASK (0x80U) -#define USB_ENDPT_HOSTWOHUB_SHIFT (7U) -#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) - -/* The count of USB_ENDPT */ -#define USB_ENDPT_COUNT (16U) - -/*! @name USBCTRL - USB Control register */ -#define USB_USBCTRL_PDE_MASK (0x40U) -#define USB_USBCTRL_PDE_SHIFT (6U) -#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) -#define USB_USBCTRL_SUSP_MASK (0x80U) -#define USB_USBCTRL_SUSP_SHIFT (7U) -#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) - -/*! @name OBSERVE - USB OTG Observe register */ -#define USB_OBSERVE_DMPD_MASK (0x10U) -#define USB_OBSERVE_DMPD_SHIFT (4U) -#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) -#define USB_OBSERVE_DPPD_MASK (0x40U) -#define USB_OBSERVE_DPPD_SHIFT (6U) -#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) -#define USB_OBSERVE_DPPU_MASK (0x80U) -#define USB_OBSERVE_DPPU_SHIFT (7U) -#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) - -/*! @name CONTROL - USB OTG Control register */ -#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) -#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) -#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) - -/*! @name USBTRC0 - USB Transceiver Control Register 0 */ -#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) -#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) -#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) -#define USB_USBTRC0_SYNC_DET_MASK (0x2U) -#define USB_USBTRC0_SYNC_DET_SHIFT (1U) -#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) -#define USB_USBTRC0_USBRESMEN_MASK (0x20U) -#define USB_USBTRC0_USBRESMEN_SHIFT (5U) -#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) -#define USB_USBTRC0_USBRESET_MASK (0x80U) -#define USB_USBTRC0_USBRESET_SHIFT (7U) -#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) - -/*! @name USBFRMADJUST - Frame Adjust Register */ -#define USB_USBFRMADJUST_ADJ_MASK (0xFFU) -#define USB_USBFRMADJUST_ADJ_SHIFT (0U) -#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -/** Peripheral USB0 base address */ -#define USB0_BASE (0x40072000u) -/** Peripheral USB0 base pointer */ -#define USB0 ((USB_Type *)USB0_BASE) -/** Array initializer of USB peripheral base addresses */ -#define USB_BASE_ADDRS { USB0_BASE } -/** Array initializer of USB peripheral base pointers */ -#define USB_BASE_PTRS { USB0 } -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBDCD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer - * @{ - */ - -/** USBDCD - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */ - __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */ - __I uint32_t STATUS; /**< Status register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */ - __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */ - __IO uint32_t TIMER2; /**< TIMER2 register, offset: 0x18 */ -} USBDCD_Type; - -/* ---------------------------------------------------------------------------- - -- USBDCD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBDCD_Register_Masks USBDCD Register Masks - * @{ - */ - -/*! @name CONTROL - Control register */ -#define USBDCD_CONTROL_IACK_MASK (0x1U) -#define USBDCD_CONTROL_IACK_SHIFT (0U) -#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK) -#define USBDCD_CONTROL_IF_MASK (0x100U) -#define USBDCD_CONTROL_IF_SHIFT (8U) -#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK) -#define USBDCD_CONTROL_IE_MASK (0x10000U) -#define USBDCD_CONTROL_IE_SHIFT (16U) -#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK) -#define USBDCD_CONTROL_START_MASK (0x1000000U) -#define USBDCD_CONTROL_START_SHIFT (24U) -#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK) -#define USBDCD_CONTROL_SR_MASK (0x2000000U) -#define USBDCD_CONTROL_SR_SHIFT (25U) -#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK) - -/*! @name CLOCK - Clock register */ -#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) -#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) -#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK) -#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) -#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) -#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK) - -/*! @name STATUS - Status register */ -#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U) -#define USBDCD_STATUS_SEQ_RES_SHIFT (16U) -#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK) -#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U) -#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U) -#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK) -#define USBDCD_STATUS_ERR_MASK (0x100000U) -#define USBDCD_STATUS_ERR_SHIFT (20U) -#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK) -#define USBDCD_STATUS_TO_MASK (0x200000U) -#define USBDCD_STATUS_TO_SHIFT (21U) -#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK) -#define USBDCD_STATUS_ACTIVE_MASK (0x400000U) -#define USBDCD_STATUS_ACTIVE_SHIFT (22U) -#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK) - -/*! @name TIMER0 - TIMER0 register */ -#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU) -#define USBDCD_TIMER0_TUNITCON_SHIFT (0U) -#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK) -#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) -#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U) -#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK) - -/*! @name TIMER1 - TIMER1 register */ -#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) -#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) -#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK) -#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) -#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U) -#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK) - -/*! @name TIMER2 - TIMER2 register */ -#define USBDCD_TIMER2_CHECK_DM_MASK (0xFU) -#define USBDCD_TIMER2_CHECK_DM_SHIFT (0U) -#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_CHECK_DM_SHIFT)) & USBDCD_TIMER2_CHECK_DM_MASK) -#define USBDCD_TIMER2_TVDPSRC_CON_MASK (0x3FF0000U) -#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT (16U) -#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_TVDPSRC_CON_MASK) - - -/*! - * @} - */ /* end of group USBDCD_Register_Masks */ - - -/* USBDCD - Peripheral instance base addresses */ -/** Peripheral USBDCD base address */ -#define USBDCD_BASE (0x40035000u) -/** Peripheral USBDCD base pointer */ -#define USBDCD ((USBDCD_Type *)USBDCD_BASE) -/** Array initializer of USBDCD peripheral base addresses */ -#define USBDCD_BASE_ADDRS { USBDCD_BASE } -/** Array initializer of USBDCD peripheral base pointers */ -#define USBDCD_BASE_PTRS { USBDCD } -/** Interrupt vectors for the USBDCD peripheral type */ -#define USBDCD_IRQS { USBDCD_IRQn } - -/*! - * @} - */ /* end of group USBDCD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WDOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer - * @{ - */ - -/** WDOG - Register Layout Typedef */ -typedef struct { - __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ - __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ - __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ - __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ - __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ - __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ - __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */ - __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */ - __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ - __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ - __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */ - __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */ -} WDOG_Type; - -/* ---------------------------------------------------------------------------- - -- WDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Register_Masks WDOG Register Masks - * @{ - */ - -/*! @name STCTRLH - Watchdog Status and Control Register High */ -#define WDOG_STCTRLH_WDOGEN_MASK (0x1U) -#define WDOG_STCTRLH_WDOGEN_SHIFT (0U) -#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) -#define WDOG_STCTRLH_CLKSRC_MASK (0x2U) -#define WDOG_STCTRLH_CLKSRC_SHIFT (1U) -#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) -#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) -#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) -#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) -#define WDOG_STCTRLH_WINEN_MASK (0x8U) -#define WDOG_STCTRLH_WINEN_SHIFT (3U) -#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) -#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) -#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) -#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) -#define WDOG_STCTRLH_DBGEN_MASK (0x20U) -#define WDOG_STCTRLH_DBGEN_SHIFT (5U) -#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) -#define WDOG_STCTRLH_STOPEN_MASK (0x40U) -#define WDOG_STCTRLH_STOPEN_SHIFT (6U) -#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) -#define WDOG_STCTRLH_WAITEN_MASK (0x80U) -#define WDOG_STCTRLH_WAITEN_SHIFT (7U) -#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK) -#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) -#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) -#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) -#define WDOG_STCTRLH_TESTSEL_MASK (0x800U) -#define WDOG_STCTRLH_TESTSEL_SHIFT (11U) -#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) -#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) -#define WDOG_STCTRLH_BYTESEL_SHIFT (12U) -#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) -#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) -#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) -#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) - -/*! @name STCTRLL - Watchdog Status and Control Register Low */ -#define WDOG_STCTRLL_INTFLG_MASK (0x8000U) -#define WDOG_STCTRLL_INTFLG_SHIFT (15U) -#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) - -/*! @name TOVALH - Watchdog Time-out Value Register High */ -#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) -#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) -#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) - -/*! @name TOVALL - Watchdog Time-out Value Register Low */ -#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) -#define WDOG_TOVALL_TOVALLOW_SHIFT (0U) -#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) - -/*! @name WINH - Watchdog Window Register High */ -#define WDOG_WINH_WINHIGH_MASK (0xFFFFU) -#define WDOG_WINH_WINHIGH_SHIFT (0U) -#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) - -/*! @name WINL - Watchdog Window Register Low */ -#define WDOG_WINL_WINLOW_MASK (0xFFFFU) -#define WDOG_WINL_WINLOW_SHIFT (0U) -#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) - -/*! @name REFRESH - Watchdog Refresh register */ -#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) -#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) -#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) - -/*! @name UNLOCK - Watchdog Unlock register */ -#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) -#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) -#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) - -/*! @name TMROUTH - Watchdog Timer Output Register High */ -#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) -#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) -#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) - -/*! @name TMROUTL - Watchdog Timer Output Register Low */ -#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) -#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) -#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) - -/*! @name RSTCNT - Watchdog Reset Count register */ -#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) -#define WDOG_RSTCNT_RSTCNT_SHIFT (0U) -#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) - -/*! @name PRESC - Watchdog Prescaler register */ -#define WDOG_PRESC_PRESCVAL_MASK (0x700U) -#define WDOG_PRESC_PRESCVAL_SHIFT (8U) -#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) - - -/*! - * @} - */ /* end of group WDOG_Register_Masks */ - - -/* WDOG - Peripheral instance base addresses */ -/** Peripheral WDOG base address */ -#define WDOG_BASE (0x40052000u) -/** Peripheral WDOG base pointer */ -#define WDOG ((WDOG_Type *)WDOG_BASE) -/** Array initializer of WDOG peripheral base addresses */ -#define WDOG_BASE_ADDRS { WDOG_BASE } -/** Array initializer of WDOG peripheral base pointers */ -#define WDOG_BASE_PTRS { WDOG } -/** Interrupt vectors for the WDOG peripheral type */ -#define WDOG_IRQS { WDOG_EWM_IRQn } - -/*! - * @} - */ /* end of group WDOG_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -#define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK -#define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT -#define DAC0_IRQn This_symbol_has_been_deprecated -#define DAC_DATL_REG(base,index) This_symbol_has_been_deprecated -#define DAC_DATH_REG(base,index) This_symbol_has_been_deprecated -#define DAC_SR_REG(base) This_symbol_has_been_deprecated -#define DAC_C0_REG(base) This_symbol_has_been_deprecated -#define DAC_C1_REG(base) This_symbol_has_been_deprecated -#define DAC_C2_REG(base) This_symbol_has_been_deprecated -#define DAC_DATL_DATA0_MASK This_symbol_has_been_deprecated -#define DAC_DATL_DATA0_SHIFT This_symbol_has_been_deprecated -#define DAC_DATL_DATA0(x) This_symbol_has_been_deprecated -#define DAC_DATH_DATA1_MASK This_symbol_has_been_deprecated -#define DAC_DATH_DATA1_SHIFT This_symbol_has_been_deprecated -#define DAC_DATH_DATA1(x) This_symbol_has_been_deprecated -#define DAC_SR_DACBFRPBF_MASK This_symbol_has_been_deprecated -#define DAC_SR_DACBFRPBF_SHIFT This_symbol_has_been_deprecated -#define DAC_SR_DACBFRPTF_MASK This_symbol_has_been_deprecated -#define DAC_SR_DACBFRPTF_SHIFT This_symbol_has_been_deprecated -#define DAC_SR_DACBFWMF_MASK This_symbol_has_been_deprecated -#define DAC_SR_DACBFWMF_SHIFT This_symbol_has_been_deprecated -#define DAC_C0_DACBBIEN_MASK This_symbol_has_been_deprecated -#define DAC_C0_DACBBIEN_SHIFT This_symbol_has_been_deprecated -#define DAC_C0_DACBTIEN_MASK This_symbol_has_been_deprecated -#define DAC_C0_DACBTIEN_SHIFT This_symbol_has_been_deprecated -#define DAC_C0_DACBWIEN_MASK This_symbol_has_been_deprecated -#define DAC_C0_DACBWIEN_SHIFT This_symbol_has_been_deprecated -#define DAC_C0_LPEN_MASK This_symbol_has_been_deprecated -#define DAC_C0_LPEN_SHIFT This_symbol_has_been_deprecated -#define DAC_C0_DACSWTRG_MASK This_symbol_has_been_deprecated -#define DAC_C0_DACSWTRG_SHIFT This_symbol_has_been_deprecated -#define DAC_C0_DACTRGSEL_MASK This_symbol_has_been_deprecated -#define DAC_C0_DACTRGSEL_SHIFT This_symbol_has_been_deprecated -#define DAC_C0_DACRFS_MASK This_symbol_has_been_deprecated -#define DAC_C0_DACRFS_SHIFT This_symbol_has_been_deprecated -#define DAC_C0_DACEN_MASK This_symbol_has_been_deprecated -#define DAC_C0_DACEN_SHIFT This_symbol_has_been_deprecated -#define DAC_C1_DACBFEN_MASK This_symbol_has_been_deprecated -#define DAC_C1_DACBFEN_SHIFT This_symbol_has_been_deprecated -#define DAC_C1_DACBFMD_MASK This_symbol_has_been_deprecated -#define DAC_C1_DACBFMD_SHIFT This_symbol_has_been_deprecated -#define DAC_C1_DACBFMD(x) This_symbol_has_been_deprecated -#define DAC_C1_DACBFWM_MASK This_symbol_has_been_deprecated -#define DAC_C1_DACBFWM_SHIFT This_symbol_has_been_deprecated -#define DAC_C1_DACBFWM(x) This_symbol_has_been_deprecated -#define DAC_C1_DMAEN_MASK This_symbol_has_been_deprecated -#define DAC_C1_DMAEN_SHIFT This_symbol_has_been_deprecated -#define DAC_C2_DACBFUP_MASK This_symbol_has_been_deprecated -#define DAC_C2_DACBFUP_SHIFT This_symbol_has_been_deprecated -#define DAC_C2_DACBFUP(x) This_symbol_has_been_deprecated -#define DAC_C2_DACBFRP_MASK This_symbol_has_been_deprecated -#define DAC_C2_DACBFRP_SHIFT This_symbol_has_been_deprecated -#define DAC_C2_DACBFRP(x) This_symbol_has_been_deprecated -#define DAC0_BASE This_symbol_has_been_deprecated -#define DAC0 This_symbol_has_been_deprecated -#define DAC_BASE_ADDRS This_symbol_has_been_deprecated -#define DAC_IRQS This_symbol_has_been_deprecated -#define DAC0_DAT0L This_symbol_has_been_deprecated -#define DAC0_DAT0H This_symbol_has_been_deprecated -#define DAC0_DAT1L This_symbol_has_been_deprecated -#define DAC0_DAT1H This_symbol_has_been_deprecated -#define DAC0_DAT2L This_symbol_has_been_deprecated -#define DAC0_DAT2H This_symbol_has_been_deprecated -#define DAC0_DAT3L This_symbol_has_been_deprecated -#define DAC0_DAT3H This_symbol_has_been_deprecated -#define DAC0_DAT4L This_symbol_has_been_deprecated -#define DAC0_DAT4H This_symbol_has_been_deprecated -#define DAC0_DAT5L This_symbol_has_been_deprecated -#define DAC0_DAT5H This_symbol_has_been_deprecated -#define DAC0_DAT6L This_symbol_has_been_deprecated -#define DAC0_DAT6H This_symbol_has_been_deprecated -#define DAC0_DAT7L This_symbol_has_been_deprecated -#define DAC0_DAT7H This_symbol_has_been_deprecated -#define DAC0_DAT8L This_symbol_has_been_deprecated -#define DAC0_DAT8H This_symbol_has_been_deprecated -#define DAC0_DAT9L This_symbol_has_been_deprecated -#define DAC0_DAT9H This_symbol_has_been_deprecated -#define DAC0_DAT10L This_symbol_has_been_deprecated -#define DAC0_DAT10H This_symbol_has_been_deprecated -#define DAC0_DAT11L This_symbol_has_been_deprecated -#define DAC0_DAT11H This_symbol_has_been_deprecated -#define DAC0_DAT12L This_symbol_has_been_deprecated -#define DAC0_DAT12H This_symbol_has_been_deprecated -#define DAC0_DAT13L This_symbol_has_been_deprecated -#define DAC0_DAT13H This_symbol_has_been_deprecated -#define DAC0_DAT14L This_symbol_has_been_deprecated -#define DAC0_DAT14H This_symbol_has_been_deprecated -#define DAC0_DAT15L This_symbol_has_been_deprecated -#define DAC0_DAT15H This_symbol_has_been_deprecated -#define DAC0_SR This_symbol_has_been_deprecated -#define DAC0_C0 This_symbol_has_been_deprecated -#define DAC0_C1 This_symbol_has_been_deprecated -#define DAC0_C2 This_symbol_has_been_deprecated -#define DAC0_DATL(index) This_symbol_has_been_deprecated -#define DAC0_DATH(index) This_symbol_has_been_deprecated -#define DMA_EARS_REG(base) This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated -#define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated -#define DMA_EARS This_symbol_has_been_deprecated -#define DSPI0 SPI0 -#define DSPI1 SPI1 -#define DMAMUX0 DMAMUX -#define WP7816_T_TYPE0 WP7816T0 -#define WP7816_T_TYPE1 WP7816T1 -#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base) -#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base) -#define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK -#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT -#define UART_WP7816_T_TYPE0_WI(X) UART_WP7816T0_WI(X) -#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK -#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT -#define UART_WP7816_T_TYPE1_BWI(X) UART_WP7816T1_BWI(X) -#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK -#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT -#define UART_WP7816_T_TYPE1_CWI(X) UART_WP7816T1_CWI(X) -#define SIM_SCGC6_DAC0_MASK This_symbol_has_been_deprecated -#define SIM_SCGC6_DAC0_SHIFT This_symbol_has_been_deprecated -#define Watchdog_IRQn WDOG_EWM_IRQn -#define Watchdog_IRQHandler WDOG_EWM_IRQHandler -#define LPTimer_IRQn LPTMR0_IRQn -#define LPTimer_IRQHandler LPTMR0_IRQHandler -#define LLW_IRQn LLWU_IRQn -#define LLW_IRQHandler LLWU_IRQHandler - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _MKW24D5_H_ */ - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/MKW24D5_features.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/MKW24D5_features.h deleted file mode 100644 index 844c580..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/MKW24D5_features.h +++ /dev/null @@ -1,1523 +0,0 @@ -/* -** ################################################################### -** Version: rev. 2.5, 2015-06-08 -** Build: b160512 -** -** Abstract: -** Chip specific module features. -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-11-22) -** Initial version. -** - rev. 1.1 (2014-01-30) -** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. -** - rev. 2.0 (2014-11-26) -** update of SystemInit() imlementation -** Module access macro module_BASES replaced by module_BASE_PTRS. -** Register accessor macros added to the memory map. -** MCG - bit LOLS in MCG_S register renamed to LOLS0. -** DAC0 registers removed. -** - rev. 2.1 (2015-01-21) -** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances -** - rev. 2.2 (2015-05-19) -** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. -** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. -** Added features for PORT and PDB. -** - rev. 2.3 (2015-05-25) -** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS -** - rev. 2.4 (2015-05-27) -** Several USB features added. -** - rev. 2.5 (2015-06-08) -** FTM features BUS_CLOCK and FAST_CLOCK removed. -** -** ################################################################### -*/ - -#ifndef _MKW24D5_FEATURES_H_ -#define _MKW24D5_FEATURES_H_ - -/* SOC module features */ - -/* @brief ACMP availability on the SoC. */ -#define FSL_FEATURE_SOC_ACMP_COUNT (0) -/* @brief ADC16 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC16_COUNT (1) -/* @brief ADC12 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC12_COUNT (0) -/* @brief AFE availability on the SoC. */ -#define FSL_FEATURE_SOC_AFE_COUNT (0) -/* @brief AIPS availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPS_COUNT (0) -/* @brief AOI availability on the SoC. */ -#define FSL_FEATURE_SOC_AOI_COUNT (0) -/* @brief AXBS availability on the SoC. */ -#define FSL_FEATURE_SOC_AXBS_COUNT (0) -/* @brief ASMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASMC_COUNT (0) -/* @brief CADC availability on the SoC. */ -#define FSL_FEATURE_SOC_CADC_COUNT (0) -/* @brief FLEXCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) -/* @brief MMCAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMCAU_COUNT (1) -/* @brief CMP availability on the SoC. */ -#define FSL_FEATURE_SOC_CMP_COUNT (2) -/* @brief CMT availability on the SoC. */ -#define FSL_FEATURE_SOC_CMT_COUNT (1) -/* @brief CNC availability on the SoC. */ -#define FSL_FEATURE_SOC_CNC_COUNT (0) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief DAC availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC_COUNT (0) -/* @brief DAC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC32_COUNT (0) -/* @brief DCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_DCDC_COUNT (0) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (0) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (0) -/* @brief EDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief DMAMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief DRY availability on the SoC. */ -#define FSL_FEATURE_SOC_DRY_COUNT (0) -/* @brief DSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_DSPI_COUNT (2) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) -/* @brief ENC availability on the SoC. */ -#define FSL_FEATURE_SOC_ENC_COUNT (0) -/* @brief ENET availability on the SoC. */ -#define FSL_FEATURE_SOC_ENET_COUNT (0) -/* @brief EWM availability on the SoC. */ -#define FSL_FEATURE_SOC_EWM_COUNT (1) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (0) -/* @brief FGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FGPIO_COUNT (0) -/* @brief FLEXIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (1) -/* @brief FSKDT availability on the SoC. */ -#define FSL_FEATURE_SOC_FSKDT_COUNT (0) -/* @brief FTFA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFA_COUNT (0) -/* @brief FTFE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFE_COUNT (0) -/* @brief FTFL availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFL_COUNT (1) -/* @brief FTM availability on the SoC. */ -#define FSL_FEATURE_SOC_FTM_COUNT (3) -/* @brief FTMRA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRA_COUNT (0) -/* @brief FTMRE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRE_COUNT (0) -/* @brief FTMRH availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRH_COUNT (0) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (5) -/* @brief HSADC availability on the SoC. */ -#define FSL_FEATURE_SOC_HSADC_COUNT (0) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (2) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (1) -/* @brief ICS availability on the SoC. */ -#define FSL_FEATURE_SOC_ICS_COUNT (0) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (0) -/* @brief IRQ availability on the SoC. */ -#define FSL_FEATURE_SOC_IRQ_COUNT (0) -/* @brief KBI availability on the SoC. */ -#define FSL_FEATURE_SOC_KBI_COUNT (0) -/* @brief SLCD availability on the SoC. */ -#define FSL_FEATURE_SOC_SLCD_COUNT (0) -/* @brief LCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDC_COUNT (0) -/* @brief LDO availability on the SoC. */ -#define FSL_FEATURE_SOC_LDO_COUNT (0) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (1) -/* @brief LMEM availability on the SoC. */ -#define FSL_FEATURE_SOC_LMEM_COUNT (0) -/* @brief LPI2C availability on the SoC. */ -#define FSL_FEATURE_SOC_LPI2C_COUNT (0) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (0) -/* @brief LPSCI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSCI_COUNT (0) -/* @brief LPSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSPI_COUNT (0) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (1) -/* @brief LPTPM availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTPM_COUNT (0) -/* @brief LPUART availability on the SoC. */ -#define FSL_FEATURE_SOC_LPUART_COUNT (0) -/* @brief LTC availability on the SoC. */ -#define FSL_FEATURE_SOC_LTC_COUNT (0) -/* @brief MC availability on the SoC. */ -#define FSL_FEATURE_SOC_MC_COUNT (0) -/* @brief MCG availability on the SoC. */ -#define FSL_FEATURE_SOC_MCG_COUNT (1) -/* @brief MCGLITE availability on the SoC. */ -#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (1) -/* @brief MMAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMAU_COUNT (0) -/* @brief MMDVSQ availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) -/* @brief MPU availability on the SoC. */ -#define FSL_FEATURE_SOC_MPU_COUNT (0) -/* @brief MSCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCAN_COUNT (0) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (0) -/* @brief MTB availability on the SoC. */ -#define FSL_FEATURE_SOC_MTB_COUNT (0) -/* @brief MTBDWT availability on the SoC. */ -#define FSL_FEATURE_SOC_MTBDWT_COUNT (0) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (0) -/* @brief NFC availability on the SoC. */ -#define FSL_FEATURE_SOC_NFC_COUNT (0) -/* @brief OPAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_OPAMP_COUNT (0) -/* @brief OSC availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC_COUNT (1) -/* @brief OSC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC32_COUNT (0) -/* @brief OTFAD availability on the SoC. */ -#define FSL_FEATURE_SOC_OTFAD_COUNT (0) -/* @brief PDB availability on the SoC. */ -#define FSL_FEATURE_SOC_PDB_COUNT (1) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (0) -/* @brief PGA availability on the SoC. */ -#define FSL_FEATURE_SOC_PGA_COUNT (0) -/* @brief PIT availability on the SoC. */ -#define FSL_FEATURE_SOC_PIT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (5) -/* @brief PWM availability on the SoC. */ -#define FSL_FEATURE_SOC_PWM_COUNT (0) -/* @brief PWT availability on the SoC. */ -#define FSL_FEATURE_SOC_PWT_COUNT (0) -/* @brief QuadSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) -/* @brief RCM availability on the SoC. */ -#define FSL_FEATURE_SOC_RCM_COUNT (1) -/* @brief RFSYS availability on the SoC. */ -#define FSL_FEATURE_SOC_RFSYS_COUNT (1) -/* @brief RFVBAT availability on the SoC. */ -#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) -/* @brief RNG availability on the SoC. */ -#define FSL_FEATURE_SOC_RNG_COUNT (1) -/* @brief RNGB availability on the SoC. */ -#define FSL_FEATURE_SOC_RNGB_COUNT (0) -/* @brief ROM availability on the SoC. */ -#define FSL_FEATURE_SOC_ROM_COUNT (0) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (0) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (0) -/* @brief SCI availability on the SoC. */ -#define FSL_FEATURE_SOC_SCI_COUNT (0) -/* @brief SDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_SDHC_COUNT (0) -/* @brief SDRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDRAM_COUNT (0) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (0) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (1) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (0) -/* @brief TMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TMR_COUNT (0) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (0) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) -/* @brief TRIAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (0) -/* @brief TSI availability on the SoC. */ -#define FSL_FEATURE_SOC_TSI_COUNT (0) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (0) -/* @brief UART availability on the SoC. */ -#define FSL_FEATURE_SOC_UART_COUNT (3) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief USBDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBDCD_COUNT (1) -/* @brief USBHSDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (0) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (0) -/* @brief WDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_WDOG_COUNT (1) -/* @brief XBAR availability on the SoC. */ -#define FSL_FEATURE_SOC_XBAR_COUNT (0) -/* @brief XBARA availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARA_COUNT (0) -/* @brief XBARB availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARB_COUNT (0) -/* @brief XCVR availability on the SoC. */ -#define FSL_FEATURE_SOC_XCVR_COUNT (0) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (0) -/* @brief ZLL availability on the SoC. */ -#define FSL_FEATURE_SOC_ZLL_COUNT (0) - -/* ADC16 module features */ - -/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ -#define FSL_FEATURE_ADC16_HAS_PGA (0) -/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ -#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) -/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ -#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) -/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ -#define FSL_FEATURE_ADC16_HAS_DMA (1) -/* @brief Has differential mode (bitfield SC1x[DIFF]). */ -#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) -/* @brief Has FIFO (bit SC4[AFDEP]). */ -#define FSL_FEATURE_ADC16_HAS_FIFO (0) -/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ -#define FSL_FEATURE_ADC16_FIFO_SIZE (0) -/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ -#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) -/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ -#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) -/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ -#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) -/* @brief Has HW averaging (bit SC3[AVGE]). */ -#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) -/* @brief Has offset correction (register OFS). */ -#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) -/* @brief Maximum ADC resolution. */ -#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) -/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ -#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) - -/* CMP module features */ - -/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ -#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) -/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ -#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) -/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ -#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) -/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ -#define FSL_FEATURE_CMP_HAS_DMA (1) -/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ -#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) -/* @brief Has DAC Test function in CMP (register DACTEST). */ -#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) - -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - -/* EDMA module features */ - -/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16) -/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) -/* @brief Has DMA_Error interrupt vector. */ -#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) -/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) - -/* DMAMUX module features */ - -/* @brief Number of DMA channels (related to number of register CHCFGn). */ -#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16) -/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ -#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) - -/* EWM module features */ - -/* @brief Has clock select (register CLKCTRL). */ -#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) -/* @brief Has clock prescaler (register CLKPRESCALER). */ -#define FSL_FEATURE_EWM_HAS_PRESCALER (0) - -/* FLASH module features */ - -/* @brief Is of type FTFA. */ -#define FSL_FEATURE_FLASH_IS_FTFA (0) -/* @brief Is of type FTFE. */ -#define FSL_FEATURE_FLASH_IS_FTFE (0) -/* @brief Is of type FTFL. */ -#define FSL_FEATURE_FLASH_IS_FTFL (1) -/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ -#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) -/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ -#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) -/* @brief Has EEPROM region protection (register FEPROT). */ -#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) -/* @brief Has data flash region protection (register FDPROT). */ -#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) -/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ -#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) -/* @brief Has flash cache control in FMC module. */ -#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) -/* @brief Has flash cache control in MCM module. */ -#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) -/* @brief Has flash cache control in MSCM module. */ -#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) -/* @brief P-Flash start address. */ -#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) -/* @brief P-Flash block count. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) -/* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) -/* @brief P-Flash sector size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) -/* @brief P-Flash write unit size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) -/* @brief P-Flash data path width. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) -/* @brief P-Flash block swap feature. */ -#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) -/* @brief P-Flash protection region count. */ -#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) -/* @brief Has FlexNVM memory. */ -#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) -/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ -#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) -/* @brief FlexNVM block count. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) -/* @brief FlexNVM block size. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) -/* @brief FlexNVM sector size. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) -/* @brief FlexNVM write unit size. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) -/* @brief FlexNVM data path width. */ -#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) -/* @brief Has FlexRAM memory. */ -#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) -/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ -#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) -/* @brief FlexRAM size. */ -#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) -/* @brief Has 0x00 Read 1s Block command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) -/* @brief Has 0x01 Read 1s Section command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) -/* @brief Has 0x02 Program Check command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) -/* @brief Has 0x03 Read Resource command. */ -#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) -/* @brief Has 0x06 Program Longword command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) -/* @brief Has 0x07 Program Phrase command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) -/* @brief Has 0x08 Erase Flash Block command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) -/* @brief Has 0x09 Erase Flash Sector command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) -/* @brief Has 0x0B Program Section command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) -/* @brief Has 0x40 Read 1s All Blocks command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) -/* @brief Has 0x41 Read Once command. */ -#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) -/* @brief Has 0x43 Program Once command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) -/* @brief Has 0x44 Erase All Blocks command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) -/* @brief Has 0x45 Verify Backdoor Access Key command. */ -#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) -/* @brief Has 0x46 Swap Control command. */ -#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) -/* @brief Has 0x49 Erase All Blocks Unsecure command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) -/* @brief Has 0x4A Read 1s All Execute-only Segments command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) -/* @brief Has 0x4B Erase All Execute-only Segments command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) -/* @brief Has 0x80 Program Partition command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) -/* @brief Has 0x81 Set FlexRAM Function command. */ -#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) -/* @brief P-Flash Erase/Read 1st all block command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) -/* @brief P-Flash Erase sector command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) -/* @brief P-Flash Rrogram/Verify section command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) -/* @brief P-Flash Read resource command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) -/* @brief P-Flash Program check command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) -/* @brief P-Flash Program check command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (8) -/* @brief FlexNVM Erase/Read 1st all block command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Erase sector command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Rrogram/Verify section command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Read resource command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Program check command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) -/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) -/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) -/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) -/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) -/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) -/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) -/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) -/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) -/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) -/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) -/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) -/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) -/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) -/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) -/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) -/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) - -/* FTM module features */ - -/* @brief Number of channels. */ -#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ - ((x) == FTM0 ? (8) : \ - ((x) == FTM1 ? (2) : \ - ((x) == FTM2 ? (2) : (-1)))) -/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ -#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) -/* @brief Enable pwm output for the module. */ -#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) -/* @brief Has half-cycle reload for the module. */ -#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) -/* @brief Has reload interrupt. */ -#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) -/* @brief Has reload initialization trigger. */ -#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) - -/* GPIO module features */ - -/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ -#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) -/* @brief Has port input disable register (PIDR). */ -#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) - -/* I2C module features */ - -/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ -#define FSL_FEATURE_I2C_HAS_SMBUS (1) -/* @brief Maximum supported baud rate in kilobit per second. */ -#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) -/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ -#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) -/* @brief Has DMA support (register bit C1[DMAEN]). */ -#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) -/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ -#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (0) -/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ -#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) -/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ -#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (0) -/* @brief Maximum width of the glitch filter in number of bus clocks. */ -#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) -/* @brief Has control of the drive capability of the I2C pins. */ -#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) -/* @brief Has double buffering support (register S2). */ -#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) -/* @brief Has double buffer enable. */ -#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) - -/* SAI module features */ - -/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ -#define FSL_FEATURE_SAI_FIFO_COUNT (8) -/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ -#define FSL_FEATURE_SAI_CHANNEL_COUNT (1) -/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ -#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (16) -/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) -/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) -/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) -/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ -#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) -/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ -#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) -/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ -#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) -/* @brief Ihe interrupt source number */ -#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) -/* @brief Has register of MCR. */ -#define FSL_FEATURE_SAI_HAS_MCR (1) -/* @brief Has register of MDR */ -#define FSL_FEATURE_SAI_HAS_MDR (1) - -/* LLWU module features */ - -/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) -/* @brief Has pins 8-15 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) -/* @brief Maximum number of internal modules connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) -/* @brief Number of digital filters. */ -#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) -/* @brief Has MF register. */ -#define FSL_FEATURE_LLWU_HAS_MF (0) -/* @brief Has PF register. */ -#define FSL_FEATURE_LLWU_HAS_PF (0) -/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ -#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) -/* @brief Has external pin 0 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) -/* @brief Has external pin 1 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) -/* @brief Has external pin 2 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) -/* @brief Has external pin 3 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) -/* @brief Has external pin 4 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) -/* @brief Has external pin 5 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) -/* @brief Has external pin 6 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) -/* @brief Has external pin 7 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) -/* @brief Has external pin 8 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) -/* @brief Has external pin 9 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) -/* @brief Has external pin 10 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) -/* @brief Has external pin 11 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) -/* @brief Has external pin 12 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) -/* @brief Has external pin 13 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) -/* @brief Has external pin 14 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) -/* @brief Has external pin 15 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) -/* @brief Has external pin 16 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) -/* @brief Has external pin 17 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) -/* @brief Has external pin 18 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) -/* @brief Has external pin 19 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) -/* @brief Has external pin 20 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) -/* @brief Has external pin 21 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) -/* @brief Has external pin 22 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) -/* @brief Has external pin 23 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) -/* @brief Has external pin 24 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) -/* @brief Has external pin 25 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) -/* @brief Has external pin 26 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) -/* @brief Has external pin 27 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) -/* @brief Has external pin 28 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) -/* @brief Has external pin 29 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) -/* @brief Has external pin 30 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) -/* @brief Has external pin 31 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) -/* @brief Has internal module 0 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) -/* @brief Has internal module 1 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) -/* @brief Has internal module 2 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) -/* @brief Has internal module 3 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) -/* @brief Has internal module 4 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) -/* @brief Has internal module 5 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) -/* @brief Has internal module 6 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) -/* @brief Has internal module 7 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) -/* @brief Has Version ID Register (LLWU_VERID). */ -#define FSL_FEATURE_LLWU_HAS_VERID (0) -/* @brief Has Parameter Register (LLWU_PARAM). */ -#define FSL_FEATURE_LLWU_HAS_PARAM (0) -/* @brief Width of registers of the LLWU. */ -#define FSL_FEATURE_LLWU_REG_BITWIDTH (8) -/* @brief Has DMA Enable register (LLWU_DE). */ -#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) - -/* LPTMR module features */ - -/* @brief Has shared interrupt handler with another LPTMR module. */ -#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) - -/* MCG module features */ - -/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ -#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) -/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ -#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) -/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ -#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) -/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ -#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) -/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ -#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) -/* @brief The PLL clock is divided by 2 before VCO divider. */ -#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) -/* @brief FRDIV supports 1280. */ -#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) -/* @brief FRDIV supports 1536. */ -#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) -/* @brief MCGFFCLK divider. */ -#define FSL_FEATURE_MCG_FFCLK_DIV (1) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ -#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) -/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ -#define FSL_FEATURE_MCG_HAS_RTC_32K (1) -/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ -#define FSL_FEATURE_MCG_HAS_PLL1 (0) -/* @brief Has 48MHz internal oscillator. */ -#define FSL_FEATURE_MCG_HAS_IRC_48M (0) -/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ -#define FSL_FEATURE_MCG_HAS_OSC1 (0) -/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ -#define FSL_FEATURE_MCG_HAS_FCFTRIM (0) -/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ -#define FSL_FEATURE_MCG_HAS_LOLRE (1) -/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ -#define FSL_FEATURE_MCG_USE_OSCSEL (1) -/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ -#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) -/* @brief TBD */ -#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) -/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ -#define FSL_FEATURE_MCG_HAS_PLL (1) -/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ -#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) -/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ -#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) -/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ -#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) -/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ -#define FSL_FEATURE_MCG_HAS_FLL (1) -/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ -#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) -/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ -#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) -/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ -#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) -/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ -#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) -/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ -#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) -/* @brief Has external clock monitor (register bit C6[CME]). */ -#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) -/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ -#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) -/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ -#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -/* @brief Has PEI mode or PBI mode. */ -#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) -/* @brief Reset clock mode is BLPI. */ -#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (64) - -/* OSC module features */ - -/* @brief Has OSC1 external oscillator. */ -#define FSL_FEATURE_OSC_HAS_OSC1 (0) -/* @brief Has OSC0 external oscillator. */ -#define FSL_FEATURE_OSC_HAS_OSC0 (0) -/* @brief Has OSC external oscillator (without index). */ -#define FSL_FEATURE_OSC_HAS_OSC (1) -/* @brief Number of OSC external oscillators. */ -#define FSL_FEATURE_OSC_OSC_COUNT (1) -/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ -#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) - -/* PDB module features */ - -/* @brief Define the count of supporting ADC pre-trigger for each channel. */ -#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) -/* @brief Has DAC support. */ -#define FSL_FEATURE_PDB_HAS_DAC (1) -/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ -#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) - -/* PIT module features */ - -/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ -#define FSL_FEATURE_PIT_TIMER_COUNT (4) -/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ -#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) -/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ -#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) -/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ -#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) - -/* PMC module features */ - -/* @brief Has Bandgap Enable In VLPx Operation support. */ -#define FSL_FEATURE_PMC_HAS_BGEN (1) -/* @brief Has Bandgap Buffer Enable. */ -#define FSL_FEATURE_PMC_HAS_BGBE (1) -/* @brief Has Bandgap Buffer Drive Select. */ -#define FSL_FEATURE_PMC_HAS_BGBDS (0) -/* @brief Has Low-Voltage Detect Voltage Select support. */ -#define FSL_FEATURE_PMC_HAS_LVDV (1) -/* @brief Has Low-Voltage Warning Voltage Select support. */ -#define FSL_FEATURE_PMC_HAS_LVWV (1) -/* @brief Has LPO. */ -#define FSL_FEATURE_PMC_HAS_LPO (0) -/* @brief Has VLPx option PMC_REGSC[VLPO]. */ -#define FSL_FEATURE_PMC_HAS_VLPO (0) -/* @brief Has acknowledge isolation support. */ -#define FSL_FEATURE_PMC_HAS_ACKISO (1) -/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ -#define FSL_FEATURE_PMC_HAS_REGFPM (0) -/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ -#define FSL_FEATURE_PMC_HAS_REGONS (1) -/* @brief Has PMC_HVDSC1. */ -#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) -/* @brief Has PMC_PARAM. */ -#define FSL_FEATURE_PMC_HAS_PARAM (0) -/* @brief Has PMC_VERID. */ -#define FSL_FEATURE_PMC_HAS_VERID (0) - -/* PORT module features */ - -/* @brief Has control lock (register bit PCR[LK]). */ -#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) -/* @brief Has open drain control (register bit PCR[ODE]). */ -#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) -/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ -#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) -/* @brief Has DMA request (register bit field PCR[IRQC] values). */ -#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) -/* @brief Has pull resistor selection available. */ -#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) -/* @brief Has pull resistor enable (register bit PCR[PE]). */ -#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) -/* @brief Has slew rate control (register bit PCR[SRE]). */ -#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) -/* @brief Has passive filter (register bit field PCR[PFE]). */ -#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) -/* @brief Has drive strength control (register bit PCR[DSE]). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) -/* @brief Has separate drive strength register (HDRVE). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) -/* @brief Has glitch filter (register IOFLT). */ -#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -/* @brief Defines width of PCR[MUX] field. */ -#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) -/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) -/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) - -/* RCM module features */ - -/* @brief Has Loss-of-Lock Reset support. */ -#define FSL_FEATURE_RCM_HAS_LOL (1) -/* @brief Has Loss-of-Clock Reset support. */ -#define FSL_FEATURE_RCM_HAS_LOC (1) -/* @brief Has JTAG generated Reset support. */ -#define FSL_FEATURE_RCM_HAS_JTAG (1) -/* @brief Has EzPort generated Reset support. */ -#define FSL_FEATURE_RCM_HAS_EZPORT (1) -/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ -#define FSL_FEATURE_RCM_HAS_EZPMS (1) -/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ -#define FSL_FEATURE_RCM_HAS_BOOTROM (0) -/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ -#define FSL_FEATURE_RCM_HAS_SSRS (0) -/* @brief Has Version ID Register (RCM_VERID). */ -#define FSL_FEATURE_RCM_HAS_VERID (0) -/* @brief Has Parameter Register (RCM_PARAM). */ -#define FSL_FEATURE_RCM_HAS_PARAM (0) -/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ -#define FSL_FEATURE_RCM_HAS_SRIE (0) -/* @brief Width of registers of the RCM. */ -#define FSL_FEATURE_RCM_REG_WIDTH (8) -/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ -#define FSL_FEATURE_RCM_HAS_CORE1 (0) -/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ -#define FSL_FEATURE_RCM_HAS_MDM_AP (1) -/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ -#define FSL_FEATURE_RCM_HAS_WAKEUP (1) - -/* RTC module features */ - -/* @brief Has wakeup pin. */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) -/* @brief Has wakeup pin selection (bit field CR[WPS]). */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) -/* @brief Has low power features (registers MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_MONOTONIC (1) -/* @brief Has read/write access control (registers WAR and RAR). */ -#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) -/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_SECURITY (1) -/* @brief Has RTC_CLKIN available. */ -#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) -/* @brief Has prescaler adjust for LPO. */ -#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) -/* @brief Has Clock Pin Enable field. */ -#define FSL_FEATURE_RTC_HAS_CPE (0) -/* @brief Has Timer Seconds Interrupt Configuration field. */ -#define FSL_FEATURE_RTC_HAS_TSIC (0) -/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ -#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) - -/* SIM module features */ - -/* @brief Has USB FS divider. */ -#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ -#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) -/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) -/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) -/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) -/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) -/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) -/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) -/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) -/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) -/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) -/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) -/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) -/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ -#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) -/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ -#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) -/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ -#define FSL_FEATURE_SIM_OPT_UART_COUNT (4) -/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) -/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) -/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) -/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) -/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) -/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) -/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) -/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) -/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) -/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) -/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) -/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) -/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) -/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) -/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) -/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) -/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) -/* @brief Has FTM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM (1) -/* @brief Number of FTM modules. */ -#define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) -/* @brief Number of FTM triggers with selectable source. */ -#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) -/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) -/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) -/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) -/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) -/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) -/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) -/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) -/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) -/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) -/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) -/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) -/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) -/* @brief Has TPM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM (0) -/* @brief The highest TPM module index. */ -#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) -/* @brief Has TPM module with index 0. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) -/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) -/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) -/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) -/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) -/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) -/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) -/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) -/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) -/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) -/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) -/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) -/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) -/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) -/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) -/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) -/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) -/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) -/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) -/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) -/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) -/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) -/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) -/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) -/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) -/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) -/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) -/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) -/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) -/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) -/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) -/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) -/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) -/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) -/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) -/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) -/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) -/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) -/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) -/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) -/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) -/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) -/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) -/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) -/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (0) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0) -/* @brief Has device die ID (register bit field SDID[DIEID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) -/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) -/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) -/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) -/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) -/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) -/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) -/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) -/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) -/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) -/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) -/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) -/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) -/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) -/* @brief Has miscellanious control register (register MCR). */ -#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) -/* @brief Has COP watchdog (registers COPC and SRVCOP). */ -#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) -/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ -#define FSL_FEATURE_SIM_HAS_COP_STOP (0) -/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ -#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) - -/* SMC module features */ - -/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ -#define FSL_FEATURE_SMC_HAS_PSTOPO (0) -/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ -#define FSL_FEATURE_SMC_HAS_LPOPO (0) -/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ -#define FSL_FEATURE_SMC_HAS_PORPO (1) -/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ -#define FSL_FEATURE_SMC_HAS_LPWUI (1) -/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ -#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) -/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) -/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) -/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ -#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) -/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ -#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) -/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ -#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ -#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has stop submode. */ -#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) -/* @brief Has stop submode 0(VLLS0). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) -/* @brief Has stop submode 2(VLLS2). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) -/* @brief Has SMC_PARAM. */ -#define FSL_FEATURE_SMC_HAS_PARAM (0) -/* @brief Has SMC_VERID. */ -#define FSL_FEATURE_SMC_HAS_VERID (0) - -/* DSPI module features */ - -/* @brief Receive/transmit FIFO size in number of items. */ -#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) -/* @brief Maximum transfer data width in bits. */ -#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) -/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ -#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (5) -/* @brief Number of chip select pins. */ -#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4) -/* @brief Has chip select strobe capability on the PCS5 pin. */ -#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) -/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ -#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) -/* @brief Has 16-bit data transfer support. */ -#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) - -/* SysTick module features */ - -/* @brief Systick has external reference clock. */ -#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) -/* @brief Systick external reference clock is core clock divided by this value. */ -#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) - -/* UART module features */ - -/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ -#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) -/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ -#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) -/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ -#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_UART_HAS_FIFO (1) -/* @brief Hardware flow control (RTS, CTS) is supported. */ -#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) -/* @brief Infrared (modulation) is supported. */ -#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) -/* @brief 2 bits long stop bit is available. */ -#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) -/* @brief If 10-bit mode is supported. */ -#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) -/* @brief Baud rate fine adjustment is available. */ -#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) -/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ -#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) -/* @brief Peripheral type. */ -#define FSL_FEATURE_UART_IS_SCI (0) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == UART0 ? (8) : \ - ((x) == UART1 ? (1) : \ - ((x) == UART2 ? (1) : (-1)))) -/* @brief Maximal data width without parity bit. */ -#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) -/* @brief Maximal data width with parity bit. */ -#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) -/* @brief Supports two match addresses to filter incoming frames. */ -#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) -/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ -#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) -/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ -#define FSL_FEATURE_UART_HAS_DMA_SELECT (1) -/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ -#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) -/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ -#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) -/* @brief Has improved smart card (ISO7816 protocol) support. */ -#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) -/* @brief Has local operation network (CEA709.1-B protocol) support. */ -#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) -/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ -#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ -#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) -/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ -#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) - -/* USB module features */ - -/* @brief HOST mode enabled */ -#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) -/* @brief OTG mode enabled */ -#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_KHCI_USB_RAM (0) -/* @brief Has KEEP_ALIVE_CTRL register */ -#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) -/* @brief Has the Dynamic SOF threshold compare support */ -#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) -/* @brief Has the VBUS detect support */ -#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) -/* @brief Has the IRC48M module clock support */ -#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0) -/* @brief Number of endpoints supported */ -#define FSL_FEATURE_USB_ENDPT_COUNT (16) - -/* WDOG module features */ - -/* @brief Watchdog is available. */ -#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) -/* @brief Has Wait mode support. */ -#define FSL_FEATURE_WDOG_HAS_WAITEN (1) - -#endif /* _MKW24D5_FEATURES_H_ */ - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct deleted file mode 100644 index d979b3d..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processor: MKW24D512VHA5 -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: MKW2xDRM Rev.2 July 2014 -** Version: rev. 2.0, 2014-11-26 -** Build: b160512 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** ################################################################### -*/ -#define __ram_vector_table__ 1 - -#if (defined(__ram_vector_table__)) - #define __ram_vector_table_size__ 0x00000400 -#else - #define __ram_vector_table_size__ 0x00000000 -#endif - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x80000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define m_interrupts_start MBED_APP_START -#define m_interrupts_size 0x00000400 - -#define m_flash_config_start MBED_APP_START + 0x400 -#define m_flash_config_size 0x00000010 - -#define m_text_start MBED_APP_START + 0x410 -#define m_text_size MBED_APP_SIZE - 0x410 - -#define m_interrupts_ram_start 0x1FFF8000 -#define m_interrupts_ram_size __ram_vector_table_size__ - -#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) -#define m_data_size (0x00008000 - m_interrupts_ram_size) - -#define m_data_2_start 0x20000000 -#define m_data_2_size 0x00008000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size MBED_BOOT_STACK_SIZE -#endif - -LR_IROM1 m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } - ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address - * (FlashConfig) - } - ER_IROM1 m_text_start m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__ram_vector_table__)) - VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { - } -#else - VECTOR_RAM m_interrupts_start EMPTY 0 { - } -#endif - RW_m_data m_data_start m_data_size { ; RW data - .ANY (+RW +ZI) - } - RW_m_data_2 m_data_2_start m_data_2_size { ; RW data - .ANY (+RW +ZI) - } - RW_IRAM1 ImageLimit(RW_m_data_2) { - } - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (m_data_2_start + m_data_2_size - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up - } - ARM_LIB_STACK m_data_2_start+m_data_2_size EMPTY -Stack_Size { ; Stack region growing down - } -} - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/startup_MKW24D5.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/startup_MKW24D5.S deleted file mode 100644 index d176a97..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/startup_MKW24D5.S +++ /dev/null @@ -1,878 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MKW24D5.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * MKW24D5 -; * @version: 2.0 -; * @date: 2014-11-26 -; * @build: b160512 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ;Top of Stack - DCD Reset_Handler ;Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD MemManage_Handler ;MPU Fault Handler - DCD BusFault_Handler ;Bus Fault Handler - DCD UsageFault_Handler ;Usage Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD DMA4_IRQHandler ;DMA channel 4 transfer complete - DCD DMA5_IRQHandler ;DMA channel 5 transfer complete - DCD DMA6_IRQHandler ;DMA channel 6 transfer complete - DCD DMA7_IRQHandler ;DMA channel 7 transfer complete - DCD DMA8_IRQHandler ;DMA channel 8 transfer complete - DCD DMA9_IRQHandler ;DMA channel 9 transfer complete - DCD DMA10_IRQHandler ;DMA channel 10 transfer complete - DCD DMA11_IRQHandler ;DMA channel 11 transfer complete - DCD DMA12_IRQHandler ;DMA channel 12 transfer complete - DCD DMA13_IRQHandler ;DMA channel 13 transfer complete - DCD DMA14_IRQHandler ;DMA channel 14 transfer complete - DCD DMA15_IRQHandler ;DMA channel 15 transfer complete - DCD DMA_Error_IRQHandler ;DMA channel 0 - 15 error - DCD MCM_IRQHandler ;MCM normal interrupt - DCD FTFL_IRQHandler ;FTFL command complete - DCD FTFL_Collision_IRQHandler ;FTFL read collision - DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low leakage wakeup - DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM - DCD RNG_IRQHandler ;Randon number generator - DCD I2C0_IRQHandler ;Inter-integrated circuit 0 - DCD I2C1_IRQHandler ;Inter-integrated circuit 1 - DCD SPI0_IRQHandler ;Serial peripheral Interface 0 - DCD SPI1_IRQHandler ;Serial peripheral Interface 1 - DCD I2S0_Tx_IRQHandler ;Integrated interchip sound 0 transmit interrupt - DCD I2S0_Rx_IRQHandler ;Integrated interchip sound 0 receive interrupt - DCD Reserved46_IRQHandler ;Reserved interrupt - DCD UART0_RX_TX_IRQHandler ;UART0 receive/transmit interrupt - DCD UART0_ERR_IRQHandler ;UART0 error interrupt - DCD UART1_RX_TX_IRQHandler ;UART1 receive/transmit interrupt - DCD UART1_ERR_IRQHandler ;UART1 error interrupt - DCD UART2_RX_TX_IRQHandler ;UART2 receive/transmit interrupt - DCD UART2_ERR_IRQHandler ;UART2 error interrupt - DCD Reserved53_IRQHandler ;Reserved interrupt - DCD Reserved54_IRQHandler ;Reserved interrupt - DCD ADC0_IRQHandler ;Analog-to-digital converter 0 - DCD CMP0_IRQHandler ;Comparator 0 - DCD CMP1_IRQHandler ;Comparator 1 - DCD FTM0_IRQHandler ;FlexTimer module 0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ;FlexTimer module 1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ;FlexTimer module 2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ;Carrier modulator transmitter - DCD RTC_IRQHandler ;Real time clock - DCD RTC_Seconds_IRQHandler ;Real time clock seconds - DCD PIT0_IRQHandler ;Periodic interrupt timer channel 0 - DCD PIT1_IRQHandler ;Periodic interrupt timer channel 1 - DCD PIT2_IRQHandler ;Periodic interrupt timer channel 2 - DCD PIT3_IRQHandler ;Periodic interrupt timer channel 3 - DCD PDB0_IRQHandler ;Programmable delay block - DCD USB0_IRQHandler ;USB OTG interrupt - DCD USBDCD_IRQHandler ;USB charger detect - DCD Reserved71_IRQHandler ;Reserved interrupt - DCD Reserved72_IRQHandler ;Reserved interrupt - DCD MCG_IRQHandler ;Multipurpose clock generator - DCD LPTMR0_IRQHandler ;Low power timer interrupt - DCD PORTA_IRQHandler ;Port A pin detect interrupt - DCD PORTB_IRQHandler ;Port B pin detect interrupt - DCD PORTC_IRQHandler ;Port C pin detect interrupt - DCD PORTD_IRQHandler ;Port D pin detect interrupt - DCD PORTE_IRQHandler ;Port E pin detect interrupt - DCD SWI_IRQHandler ;Software interrupt - DCD DefaultISR ;81 - DCD DefaultISR ;82 - DCD DefaultISR ;83 - DCD DefaultISR ;84 - DCD DefaultISR ;85 - DCD DefaultISR ;86 - DCD DefaultISR ;87 - DCD DefaultISR ;88 - DCD DefaultISR ;89 - DCD DefaultISR ;90 - DCD DefaultISR ;91 - DCD DefaultISR ;92 - DCD DefaultISR ;93 - DCD DefaultISR ;94 - DCD DefaultISR ;95 - DCD DefaultISR ;96 - DCD DefaultISR ;97 - DCD DefaultISR ;98 - DCD DefaultISR ;99 - DCD DefaultISR ;100 - DCD DefaultISR ;101 - DCD DefaultISR ;102 - DCD DefaultISR ;103 - DCD DefaultISR ;104 - DCD DefaultISR ;105 - DCD DefaultISR ;106 - DCD DefaultISR ;107 - DCD DefaultISR ;108 - DCD DefaultISR ;109 - DCD DefaultISR ;110 - DCD DefaultISR ;111 - DCD DefaultISR ;112 - DCD DefaultISR ;113 - DCD DefaultISR ;114 - DCD DefaultISR ;115 - DCD DefaultISR ;116 - DCD DefaultISR ;117 - DCD DefaultISR ;118 - DCD DefaultISR ;119 - DCD DefaultISR ;120 - DCD DefaultISR ;121 - DCD DefaultISR ;122 - DCD DefaultISR ;123 - DCD DefaultISR ;124 - DCD DefaultISR ;125 - DCD DefaultISR ;126 - DCD DefaultISR ;127 - DCD DefaultISR ;128 - DCD DefaultISR ;129 - DCD DefaultISR ;130 - DCD DefaultISR ;131 - DCD DefaultISR ;132 - DCD DefaultISR ;133 - DCD DefaultISR ;134 - DCD DefaultISR ;135 - DCD DefaultISR ;136 - DCD DefaultISR ;137 - DCD DefaultISR ;138 - DCD DefaultISR ;139 - DCD DefaultISR ;140 - DCD DefaultISR ;141 - DCD DefaultISR ;142 - DCD DefaultISR ;143 - DCD DefaultISR ;144 - DCD DefaultISR ;145 - DCD DefaultISR ;146 - DCD DefaultISR ;147 - DCD DefaultISR ;148 - DCD DefaultISR ;149 - DCD DefaultISR ;150 - DCD DefaultISR ;151 - DCD DefaultISR ;152 - DCD DefaultISR ;153 - DCD DefaultISR ;154 - DCD DefaultISR ;155 - DCD DefaultISR ;156 - DCD DefaultISR ;157 - DCD DefaultISR ;158 - DCD DefaultISR ;159 - DCD DefaultISR ;160 - DCD DefaultISR ;161 - DCD DefaultISR ;162 - DCD DefaultISR ;163 - DCD DefaultISR ;164 - DCD DefaultISR ;165 - DCD DefaultISR ;166 - DCD DefaultISR ;167 - DCD DefaultISR ;168 - DCD DefaultISR ;169 - DCD DefaultISR ;170 - DCD DefaultISR ;171 - DCD DefaultISR ;172 - DCD DefaultISR ;173 - DCD DefaultISR ;174 - DCD DefaultISR ;175 - DCD DefaultISR ;176 - DCD DefaultISR ;177 - DCD DefaultISR ;178 - DCD DefaultISR ;179 - DCD DefaultISR ;180 - DCD DefaultISR ;181 - DCD DefaultISR ;182 - DCD DefaultISR ;183 - DCD DefaultISR ;184 - DCD DefaultISR ;185 - DCD DefaultISR ;186 - DCD DefaultISR ;187 - DCD DefaultISR ;188 - DCD DefaultISR ;189 - DCD DefaultISR ;190 - DCD DefaultISR ;191 - DCD DefaultISR ;192 - DCD DefaultISR ;193 - DCD DefaultISR ;194 - DCD DefaultISR ;195 - DCD DefaultISR ;196 - DCD DefaultISR ;197 - DCD DefaultISR ;198 - DCD DefaultISR ;199 - DCD DefaultISR ;200 - DCD DefaultISR ;201 - DCD DefaultISR ;202 - DCD DefaultISR ;203 - DCD DefaultISR ;204 - DCD DefaultISR ;205 - DCD DefaultISR ;206 - DCD DefaultISR ;207 - DCD DefaultISR ;208 - DCD DefaultISR ;209 - DCD DefaultISR ;210 - DCD DefaultISR ;211 - DCD DefaultISR ;212 - DCD DefaultISR ;213 - DCD DefaultISR ;214 - DCD DefaultISR ;215 - DCD DefaultISR ;216 - DCD DefaultISR ;217 - DCD DefaultISR ;218 - DCD DefaultISR ;219 - DCD DefaultISR ;220 - DCD DefaultISR ;221 - DCD DefaultISR ;222 - DCD DefaultISR ;223 - DCD DefaultISR ;224 - DCD DefaultISR ;225 - DCD DefaultISR ;226 - DCD DefaultISR ;227 - DCD DefaultISR ;228 - DCD DefaultISR ;229 - DCD DefaultISR ;230 - DCD DefaultISR ;231 - DCD DefaultISR ;232 - DCD DefaultISR ;233 - DCD DefaultISR ;234 - DCD DefaultISR ;235 - DCD DefaultISR ;236 - DCD DefaultISR ;237 - DCD DefaultISR ;238 - DCD DefaultISR ;239 - DCD DefaultISR ;240 - DCD DefaultISR ;241 - DCD DefaultISR ;242 - DCD DefaultISR ;243 - DCD DefaultISR ;244 - DCD DefaultISR ;245 - DCD DefaultISR ;246 - DCD DefaultISR ;247 - DCD DefaultISR ;248 - DCD DefaultISR ;249 - DCD DefaultISR ;250 - DCD DefaultISR ;251 - DCD DefaultISR ;252 - DCD DefaultISR ;253 - DCD DefaultISR ;254 - DCD 0xFFFFFFFF ; Reserved for user TRIM value -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict access to the FTFL module. -; Backdoor Comparison Key -; Backdoor Comparison Key 0. <0x0-0xFF:2> -; Backdoor Comparison Key 1. <0x0-0xFF:2> -; Backdoor Comparison Key 2. <0x0-0xFF:2> -; Backdoor Comparison Key 3. <0x0-0xFF:2> -; Backdoor Comparison Key 4. <0x0-0xFF:2> -; Backdoor Comparison Key 5. <0x0-0xFF:2> -; Backdoor Comparison Key 6. <0x0-0xFF:2> -; Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program Flash Region Protect Register 0 -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Data flash protection byte (FDPROT) -; Each bit protects a 1/8 region of the data flash memory. -; (Program flash only devices: Reserved) -; FDPROT.0 -; FDPROT.1 -; FDPROT.2 -; FDPROT.3 -; FDPROT.4 -; FDPROT.5 -; FDPROT.6 -; FDPROT.7 -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT:EOR:0xFF -; -; EEPROM protection byte (FEPROT) -; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. -; (Program flash only devices: Reserved) -; FEPROT.0 -; FEPROT.1 -; FEPROT.2 -; FEPROT.3 -; FEPROT.4 -; FEPROT.5 -; FEPROT.6 -; FEPROT.7 -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT:EOR:0xFF -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT -; <0=> Low-power boot -; <1=> Normal boot -; EZPORT_DIS -; <0=> EzPort operation is disabled -; <1=> EzPort operation is enabled -; NMI_DIS -; <0=> NMI interrupts are always blocked -; <1=> NMI_b pin/interrupts reset default to enabled -FOPT EQU 0xFF -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor Key Security Enable -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA FlashConfig, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , FEPROT , FDPROT - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - IF :LNOT::DEF:RAM_TARGET - REQUIRE FlashConfig - ENDIF - - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__Vectors - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -DMA1_IRQHandler\ - PROC - EXPORT DMA1_IRQHandler [WEAK] - LDR R0, =DMA1_DriverIRQHandler - BX R0 - ENDP - -DMA2_IRQHandler\ - PROC - EXPORT DMA2_IRQHandler [WEAK] - LDR R0, =DMA2_DriverIRQHandler - BX R0 - ENDP - -DMA3_IRQHandler\ - PROC - EXPORT DMA3_IRQHandler [WEAK] - LDR R0, =DMA3_DriverIRQHandler - BX R0 - ENDP - -DMA4_IRQHandler\ - PROC - EXPORT DMA4_IRQHandler [WEAK] - LDR R0, =DMA4_DriverIRQHandler - BX R0 - ENDP - -DMA5_IRQHandler\ - PROC - EXPORT DMA5_IRQHandler [WEAK] - LDR R0, =DMA5_DriverIRQHandler - BX R0 - ENDP - -DMA6_IRQHandler\ - PROC - EXPORT DMA6_IRQHandler [WEAK] - LDR R0, =DMA6_DriverIRQHandler - BX R0 - ENDP - -DMA7_IRQHandler\ - PROC - EXPORT DMA7_IRQHandler [WEAK] - LDR R0, =DMA7_DriverIRQHandler - BX R0 - ENDP - -DMA8_IRQHandler\ - PROC - EXPORT DMA8_IRQHandler [WEAK] - LDR R0, =DMA8_DriverIRQHandler - BX R0 - ENDP - -DMA9_IRQHandler\ - PROC - EXPORT DMA9_IRQHandler [WEAK] - LDR R0, =DMA9_DriverIRQHandler - BX R0 - ENDP - -DMA10_IRQHandler\ - PROC - EXPORT DMA10_IRQHandler [WEAK] - LDR R0, =DMA10_DriverIRQHandler - BX R0 - ENDP - -DMA11_IRQHandler\ - PROC - EXPORT DMA11_IRQHandler [WEAK] - LDR R0, =DMA11_DriverIRQHandler - BX R0 - ENDP - -DMA12_IRQHandler\ - PROC - EXPORT DMA12_IRQHandler [WEAK] - LDR R0, =DMA12_DriverIRQHandler - BX R0 - ENDP - -DMA13_IRQHandler\ - PROC - EXPORT DMA13_IRQHandler [WEAK] - LDR R0, =DMA13_DriverIRQHandler - BX R0 - ENDP - -DMA14_IRQHandler\ - PROC - EXPORT DMA14_IRQHandler [WEAK] - LDR R0, =DMA14_DriverIRQHandler - BX R0 - ENDP - -DMA15_IRQHandler\ - PROC - EXPORT DMA15_IRQHandler [WEAK] - LDR R0, =DMA15_DriverIRQHandler - BX R0 - ENDP - -DMA_Error_IRQHandler\ - PROC - EXPORT DMA_Error_IRQHandler [WEAK] - LDR R0, =DMA_Error_DriverIRQHandler - BX R0 - ENDP - -I2C0_IRQHandler\ - PROC - EXPORT I2C0_IRQHandler [WEAK] - LDR R0, =I2C0_DriverIRQHandler - BX R0 - ENDP - -I2C1_IRQHandler\ - PROC - EXPORT I2C1_IRQHandler [WEAK] - LDR R0, =I2C1_DriverIRQHandler - BX R0 - ENDP - -SPI0_IRQHandler\ - PROC - EXPORT SPI0_IRQHandler [WEAK] - LDR R0, =SPI0_DriverIRQHandler - BX R0 - ENDP - -SPI1_IRQHandler\ - PROC - EXPORT SPI1_IRQHandler [WEAK] - LDR R0, =SPI1_DriverIRQHandler - BX R0 - ENDP - -I2S0_Tx_IRQHandler\ - PROC - EXPORT I2S0_Tx_IRQHandler [WEAK] - LDR R0, =I2S0_Tx_DriverIRQHandler - BX R0 - ENDP - -I2S0_Rx_IRQHandler\ - PROC - EXPORT I2S0_Rx_IRQHandler [WEAK] - LDR R0, =I2S0_Rx_DriverIRQHandler - BX R0 - ENDP - -UART0_RX_TX_IRQHandler\ - PROC - EXPORT UART0_RX_TX_IRQHandler [WEAK] - LDR R0, =UART0_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART0_ERR_IRQHandler\ - PROC - EXPORT UART0_ERR_IRQHandler [WEAK] - LDR R0, =UART0_ERR_DriverIRQHandler - BX R0 - ENDP - -UART1_RX_TX_IRQHandler\ - PROC - EXPORT UART1_RX_TX_IRQHandler [WEAK] - LDR R0, =UART1_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART1_ERR_IRQHandler\ - PROC - EXPORT UART1_ERR_IRQHandler [WEAK] - LDR R0, =UART1_ERR_DriverIRQHandler - BX R0 - ENDP - -UART2_RX_TX_IRQHandler\ - PROC - EXPORT UART2_RX_TX_IRQHandler [WEAK] - LDR R0, =UART2_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART2_ERR_IRQHandler\ - PROC - EXPORT UART2_ERR_IRQHandler [WEAK] - LDR R0, =UART2_ERR_DriverIRQHandler - BX R0 - ENDP - -Default_Handler\ - PROC - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT DMA1_DriverIRQHandler [WEAK] - EXPORT DMA2_DriverIRQHandler [WEAK] - EXPORT DMA3_DriverIRQHandler [WEAK] - EXPORT DMA4_DriverIRQHandler [WEAK] - EXPORT DMA5_DriverIRQHandler [WEAK] - EXPORT DMA6_DriverIRQHandler [WEAK] - EXPORT DMA7_DriverIRQHandler [WEAK] - EXPORT DMA8_DriverIRQHandler [WEAK] - EXPORT DMA9_DriverIRQHandler [WEAK] - EXPORT DMA10_DriverIRQHandler [WEAK] - EXPORT DMA11_DriverIRQHandler [WEAK] - EXPORT DMA12_DriverIRQHandler [WEAK] - EXPORT DMA13_DriverIRQHandler [WEAK] - EXPORT DMA14_DriverIRQHandler [WEAK] - EXPORT DMA15_DriverIRQHandler [WEAK] - EXPORT DMA_Error_DriverIRQHandler [WEAK] - EXPORT MCM_IRQHandler [WEAK] - EXPORT FTFL_IRQHandler [WEAK] - EXPORT FTFL_Collision_IRQHandler [WEAK] - EXPORT PMC_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT WDOG_EWM_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT I2C0_DriverIRQHandler [WEAK] - EXPORT I2C1_DriverIRQHandler [WEAK] - EXPORT SPI0_DriverIRQHandler [WEAK] - EXPORT SPI1_DriverIRQHandler [WEAK] - EXPORT I2S0_Tx_DriverIRQHandler [WEAK] - EXPORT I2S0_Rx_DriverIRQHandler [WEAK] - EXPORT Reserved46_IRQHandler [WEAK] - EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART0_ERR_DriverIRQHandler [WEAK] - EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART1_ERR_DriverIRQHandler [WEAK] - EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART2_ERR_DriverIRQHandler [WEAK] - EXPORT Reserved53_IRQHandler [WEAK] - EXPORT Reserved54_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT CMP1_IRQHandler [WEAK] - EXPORT FTM0_IRQHandler [WEAK] - EXPORT FTM1_IRQHandler [WEAK] - EXPORT FTM2_IRQHandler [WEAK] - EXPORT CMT_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT0_IRQHandler [WEAK] - EXPORT PIT1_IRQHandler [WEAK] - EXPORT PIT2_IRQHandler [WEAK] - EXPORT PIT3_IRQHandler [WEAK] - EXPORT PDB0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USBDCD_IRQHandler [WEAK] - EXPORT Reserved71_IRQHandler [WEAK] - EXPORT Reserved72_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTB_IRQHandler [WEAK] - EXPORT PORTC_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] - EXPORT PORTE_IRQHandler [WEAK] - EXPORT SWI_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -DMA4_DriverIRQHandler -DMA5_DriverIRQHandler -DMA6_DriverIRQHandler -DMA7_DriverIRQHandler -DMA8_DriverIRQHandler -DMA9_DriverIRQHandler -DMA10_DriverIRQHandler -DMA11_DriverIRQHandler -DMA12_DriverIRQHandler -DMA13_DriverIRQHandler -DMA14_DriverIRQHandler -DMA15_DriverIRQHandler -DMA_Error_DriverIRQHandler -MCM_IRQHandler -FTFL_IRQHandler -FTFL_Collision_IRQHandler -PMC_IRQHandler -LLWU_IRQHandler -WDOG_EWM_IRQHandler -RNG_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -SPI1_DriverIRQHandler -I2S0_Tx_DriverIRQHandler -I2S0_Rx_DriverIRQHandler -Reserved46_IRQHandler -UART0_RX_TX_DriverIRQHandler -UART0_ERR_DriverIRQHandler -UART1_RX_TX_DriverIRQHandler -UART1_ERR_DriverIRQHandler -UART2_RX_TX_DriverIRQHandler -UART2_ERR_DriverIRQHandler -Reserved53_IRQHandler -Reserved54_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -Reserved71_IRQHandler -Reserved72_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -DefaultISR - B DefaultISR - ENDP - ALIGN - - - END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld deleted file mode 100644 index a5d44b1..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld +++ /dev/null @@ -1,274 +0,0 @@ -/* -** ################################################################### -** Processor: MKW24D512VHA5 -** Compiler: GNU C Compiler -** Reference manual: MKW2xDRM Rev.2 July 2014 -** Version: rev. 2.0, 2014-11-26 -** Build: b160512 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -__ram_vector_table__ = 1; - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -/* With the RTOS in use, this does not affect the main stack size. The size of - * the stack where main runs is determined via the RTOS. */ -__stack_size__ = MBED_BOOT_STACK_SIZE; - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x80000 -#endif - -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; -M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x400 - m_flash_config (RX) : ORIGIN = MBED_APP_START + 0x400, LENGTH = 0x10 - m_text (RX) : ORIGIN = MBED_APP_START + 0x410, LENGTH = MBED_APP_SIZE - 0x410 - m_data (RW) : ORIGIN = 0x1FFF8000, LENGTH = 0x00008000 - m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - __VECTOR_TABLE = .; - . = ALIGN(8); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(8); - } > m_interrupts - - .flash_config : - { - . = ALIGN(8); - KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ - . = ALIGN(8); - } > m_flash_config - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(8); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .interrupts_ram : - { - . = ALIGN(8); - __VECTOR_RAM__ = .; - __interrupts_ram_start__ = .; /* Create a global symbol at data start */ - *(.m_interrupts_ram) /* This is a user defined section */ - . += M_VECTOR_RAM_SIZE; - . = ALIGN(8); - __interrupts_ram_end__ = .; /* Define a global symbol at data end */ - } > m_data - - __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); - __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; - - .data : AT(__DATA_ROM) - { - . = ALIGN(8); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(8); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800; - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(8); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - . = ALIGN(512); - USB_RAM_START = .; - . += USB_RAM_GAP; - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . = ORIGIN(m_data_2) + LENGTH(m_data_2) - STACK_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data_2 - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data_2 - - m_usb_bdt USB_RAM_START (NOLOAD) : - { - *(m_usb_bdt) - USB_RAM_BDT_END = .; - } - - m_usb_global USB_RAM_BDT_END (NOLOAD) : - { - *(m_usb_global) - } - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") -} - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/startup_MKW24D5.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/startup_MKW24D5.S deleted file mode 100644 index 5feb3e9..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/startup_MKW24D5.S +++ /dev/null @@ -1,797 +0,0 @@ -/* ---------------------------------------------------------------------------------------*/ -/* @file: startup_MKW24D5.s */ -/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ -/* MKW24D5 */ -/* @version: 2.0 */ -/* @date: 2014-11-26 */ -/* @build: b160512 */ -/* ---------------------------------------------------------------------------------------*/ -/* */ -/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without modification, */ -/* are permitted provided that the following conditions are met: */ -/* */ -/* o Redistributions of source code must retain the above copyright notice, this list */ -/* of conditions and the following disclaimer. */ -/* */ -/* o Redistributions in binary form must reproduce the above copyright notice, this */ -/* list of conditions and the following disclaimer in the documentation and/or */ -/* other materials provided with the distribution. */ -/* */ -/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ -/* contributors may be used to endorse or promote products derived from this */ -/* software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ -/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ -/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ -/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ -/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ -/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ -/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ -/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ -/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - .syntax unified - .arch armv7-m - - .section .isr_vector, "a" - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/ - .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/ - .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/ - .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/ - .long DMA4_IRQHandler /* DMA channel 4 transfer complete*/ - .long DMA5_IRQHandler /* DMA channel 5 transfer complete*/ - .long DMA6_IRQHandler /* DMA channel 6 transfer complete*/ - .long DMA7_IRQHandler /* DMA channel 7 transfer complete*/ - .long DMA8_IRQHandler /* DMA channel 8 transfer complete*/ - .long DMA9_IRQHandler /* DMA channel 9 transfer complete*/ - .long DMA10_IRQHandler /* DMA channel 10 transfer complete*/ - .long DMA11_IRQHandler /* DMA channel 11 transfer complete*/ - .long DMA12_IRQHandler /* DMA channel 12 transfer complete*/ - .long DMA13_IRQHandler /* DMA channel 13 transfer complete*/ - .long DMA14_IRQHandler /* DMA channel 14 transfer complete*/ - .long DMA15_IRQHandler /* DMA channel 15 transfer complete*/ - .long DMA_Error_IRQHandler /* DMA channel 0 - 15 error*/ - .long MCM_IRQHandler /* MCM normal interrupt*/ - .long FTFL_IRQHandler /* FTFL command complete*/ - .long FTFL_Collision_IRQHandler /* FTFL read collision*/ - .long PMC_IRQHandler /* PMC controller low-voltage detect, low-voltage warning*/ - .long LLWU_IRQHandler /* Low leakage wakeup*/ - .long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM*/ - .long RNG_IRQHandler /* Randon number generator*/ - .long I2C0_IRQHandler /* Inter-integrated circuit 0*/ - .long I2C1_IRQHandler /* Inter-integrated circuit 1*/ - .long SPI0_IRQHandler /* Serial peripheral Interface 0*/ - .long SPI1_IRQHandler /* Serial peripheral Interface 1*/ - .long I2S0_Tx_IRQHandler /* Integrated interchip sound 0 transmit interrupt*/ - .long I2S0_Rx_IRQHandler /* Integrated interchip sound 0 receive interrupt*/ - .long Reserved46_IRQHandler /* Reserved interrupt*/ - .long UART0_RX_TX_IRQHandler /* UART0 receive/transmit interrupt*/ - .long UART0_ERR_IRQHandler /* UART0 error interrupt*/ - .long UART1_RX_TX_IRQHandler /* UART1 receive/transmit interrupt*/ - .long UART1_ERR_IRQHandler /* UART1 error interrupt*/ - .long UART2_RX_TX_IRQHandler /* UART2 receive/transmit interrupt*/ - .long UART2_ERR_IRQHandler /* UART2 error interrupt*/ - .long Reserved53_IRQHandler /* Reserved interrupt*/ - .long Reserved54_IRQHandler /* Reserved interrupt*/ - .long ADC0_IRQHandler /* Analog-to-digital converter 0*/ - .long CMP0_IRQHandler /* Comparator 0*/ - .long CMP1_IRQHandler /* Comparator 1*/ - .long FTM0_IRQHandler /* FlexTimer module 0 fault, overflow and channels interrupt*/ - .long FTM1_IRQHandler /* FlexTimer module 1 fault, overflow and channels interrupt*/ - .long FTM2_IRQHandler /* FlexTimer module 2 fault, overflow and channels interrupt*/ - .long CMT_IRQHandler /* Carrier modulator transmitter*/ - .long RTC_IRQHandler /* Real time clock*/ - .long RTC_Seconds_IRQHandler /* Real time clock seconds*/ - .long PIT0_IRQHandler /* Periodic interrupt timer channel 0*/ - .long PIT1_IRQHandler /* Periodic interrupt timer channel 1*/ - .long PIT2_IRQHandler /* Periodic interrupt timer channel 2*/ - .long PIT3_IRQHandler /* Periodic interrupt timer channel 3*/ - .long PDB0_IRQHandler /* Programmable delay block*/ - .long USB0_IRQHandler /* USB OTG interrupt*/ - .long USBDCD_IRQHandler /* USB charger detect*/ - .long Reserved71_IRQHandler /* Reserved interrupt*/ - .long Reserved72_IRQHandler /* Reserved interrupt*/ - .long MCG_IRQHandler /* Multipurpose clock generator*/ - .long LPTMR0_IRQHandler /* Low power timer interrupt*/ - .long PORTA_IRQHandler /* Port A pin detect interrupt*/ - .long PORTB_IRQHandler /* Port B pin detect interrupt*/ - .long PORTC_IRQHandler /* Port C pin detect interrupt*/ - .long PORTD_IRQHandler /* Port D pin detect interrupt*/ - .long PORTE_IRQHandler /* Port E pin detect interrupt*/ - .long SWI_IRQHandler /* Software interrupt*/ - .long DefaultISR /* 81*/ - .long DefaultISR /* 82*/ - .long DefaultISR /* 83*/ - .long DefaultISR /* 84*/ - .long DefaultISR /* 85*/ - .long DefaultISR /* 86*/ - .long DefaultISR /* 87*/ - .long DefaultISR /* 88*/ - .long DefaultISR /* 89*/ - .long DefaultISR /* 90*/ - .long DefaultISR /* 91*/ - .long DefaultISR /* 92*/ - .long DefaultISR /* 93*/ - .long DefaultISR /* 94*/ - .long DefaultISR /* 95*/ - .long DefaultISR /* 96*/ - .long DefaultISR /* 97*/ - .long DefaultISR /* 98*/ - .long DefaultISR /* 99*/ - .long DefaultISR /* 100*/ - .long DefaultISR /* 101*/ - .long DefaultISR /* 102*/ - .long DefaultISR /* 103*/ - .long DefaultISR /* 104*/ - .long DefaultISR /* 105*/ - .long DefaultISR /* 106*/ - .long DefaultISR /* 107*/ - .long DefaultISR /* 108*/ - .long DefaultISR /* 109*/ - .long DefaultISR /* 110*/ - .long DefaultISR /* 111*/ - .long DefaultISR /* 112*/ - .long DefaultISR /* 113*/ - .long DefaultISR /* 114*/ - .long DefaultISR /* 115*/ - .long DefaultISR /* 116*/ - .long DefaultISR /* 117*/ - .long DefaultISR /* 118*/ - .long DefaultISR /* 119*/ - .long DefaultISR /* 120*/ - .long DefaultISR /* 121*/ - .long DefaultISR /* 122*/ - .long DefaultISR /* 123*/ - .long DefaultISR /* 124*/ - .long DefaultISR /* 125*/ - .long DefaultISR /* 126*/ - .long DefaultISR /* 127*/ - .long DefaultISR /* 128*/ - .long DefaultISR /* 129*/ - .long DefaultISR /* 130*/ - .long DefaultISR /* 131*/ - .long DefaultISR /* 132*/ - .long DefaultISR /* 133*/ - .long DefaultISR /* 134*/ - .long DefaultISR /* 135*/ - .long DefaultISR /* 136*/ - .long DefaultISR /* 137*/ - .long DefaultISR /* 138*/ - .long DefaultISR /* 139*/ - .long DefaultISR /* 140*/ - .long DefaultISR /* 141*/ - .long DefaultISR /* 142*/ - .long DefaultISR /* 143*/ - .long DefaultISR /* 144*/ - .long DefaultISR /* 145*/ - .long DefaultISR /* 146*/ - .long DefaultISR /* 147*/ - .long DefaultISR /* 148*/ - .long DefaultISR /* 149*/ - .long DefaultISR /* 150*/ - .long DefaultISR /* 151*/ - .long DefaultISR /* 152*/ - .long DefaultISR /* 153*/ - .long DefaultISR /* 154*/ - .long DefaultISR /* 155*/ - .long DefaultISR /* 156*/ - .long DefaultISR /* 157*/ - .long DefaultISR /* 158*/ - .long DefaultISR /* 159*/ - .long DefaultISR /* 160*/ - .long DefaultISR /* 161*/ - .long DefaultISR /* 162*/ - .long DefaultISR /* 163*/ - .long DefaultISR /* 164*/ - .long DefaultISR /* 165*/ - .long DefaultISR /* 166*/ - .long DefaultISR /* 167*/ - .long DefaultISR /* 168*/ - .long DefaultISR /* 169*/ - .long DefaultISR /* 170*/ - .long DefaultISR /* 171*/ - .long DefaultISR /* 172*/ - .long DefaultISR /* 173*/ - .long DefaultISR /* 174*/ - .long DefaultISR /* 175*/ - .long DefaultISR /* 176*/ - .long DefaultISR /* 177*/ - .long DefaultISR /* 178*/ - .long DefaultISR /* 179*/ - .long DefaultISR /* 180*/ - .long DefaultISR /* 181*/ - .long DefaultISR /* 182*/ - .long DefaultISR /* 183*/ - .long DefaultISR /* 184*/ - .long DefaultISR /* 185*/ - .long DefaultISR /* 186*/ - .long DefaultISR /* 187*/ - .long DefaultISR /* 188*/ - .long DefaultISR /* 189*/ - .long DefaultISR /* 190*/ - .long DefaultISR /* 191*/ - .long DefaultISR /* 192*/ - .long DefaultISR /* 193*/ - .long DefaultISR /* 194*/ - .long DefaultISR /* 195*/ - .long DefaultISR /* 196*/ - .long DefaultISR /* 197*/ - .long DefaultISR /* 198*/ - .long DefaultISR /* 199*/ - .long DefaultISR /* 200*/ - .long DefaultISR /* 201*/ - .long DefaultISR /* 202*/ - .long DefaultISR /* 203*/ - .long DefaultISR /* 204*/ - .long DefaultISR /* 205*/ - .long DefaultISR /* 206*/ - .long DefaultISR /* 207*/ - .long DefaultISR /* 208*/ - .long DefaultISR /* 209*/ - .long DefaultISR /* 210*/ - .long DefaultISR /* 211*/ - .long DefaultISR /* 212*/ - .long DefaultISR /* 213*/ - .long DefaultISR /* 214*/ - .long DefaultISR /* 215*/ - .long DefaultISR /* 216*/ - .long DefaultISR /* 217*/ - .long DefaultISR /* 218*/ - .long DefaultISR /* 219*/ - .long DefaultISR /* 220*/ - .long DefaultISR /* 221*/ - .long DefaultISR /* 222*/ - .long DefaultISR /* 223*/ - .long DefaultISR /* 224*/ - .long DefaultISR /* 225*/ - .long DefaultISR /* 226*/ - .long DefaultISR /* 227*/ - .long DefaultISR /* 228*/ - .long DefaultISR /* 229*/ - .long DefaultISR /* 230*/ - .long DefaultISR /* 231*/ - .long DefaultISR /* 232*/ - .long DefaultISR /* 233*/ - .long DefaultISR /* 234*/ - .long DefaultISR /* 235*/ - .long DefaultISR /* 236*/ - .long DefaultISR /* 237*/ - .long DefaultISR /* 238*/ - .long DefaultISR /* 239*/ - .long DefaultISR /* 240*/ - .long DefaultISR /* 241*/ - .long DefaultISR /* 242*/ - .long DefaultISR /* 243*/ - .long DefaultISR /* 244*/ - .long DefaultISR /* 245*/ - .long DefaultISR /* 246*/ - .long DefaultISR /* 247*/ - .long DefaultISR /* 248*/ - .long DefaultISR /* 249*/ - .long DefaultISR /* 250*/ - .long DefaultISR /* 251*/ - .long DefaultISR /* 252*/ - .long DefaultISR /* 253*/ - .long DefaultISR /* 254*/ - .long 0xFFFFFFFF /* Reserved for user TRIM value*/ - - .size __isr_vector, . - __isr_vector - -/* Flash Configuration */ - .section .FlashConfig, "a" - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFE - - .text - .thumb - -/* Reset Handler */ - - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__isr_vector - str r1, [r0] -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - - cpsie i /* Unmask interrupts */ -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak DMA2_IRQHandler - .type DMA2_IRQHandler, %function -DMA2_IRQHandler: - ldr r0,=DMA2_DriverIRQHandler - bx r0 - .size DMA2_IRQHandler, . - DMA2_IRQHandler - - .align 1 - .thumb_func - .weak DMA3_IRQHandler - .type DMA3_IRQHandler, %function -DMA3_IRQHandler: - ldr r0,=DMA3_DriverIRQHandler - bx r0 - .size DMA3_IRQHandler, . - DMA3_IRQHandler - - .align 1 - .thumb_func - .weak DMA4_IRQHandler - .type DMA4_IRQHandler, %function -DMA4_IRQHandler: - ldr r0,=DMA4_DriverIRQHandler - bx r0 - .size DMA4_IRQHandler, . - DMA4_IRQHandler - - .align 1 - .thumb_func - .weak DMA5_IRQHandler - .type DMA5_IRQHandler, %function -DMA5_IRQHandler: - ldr r0,=DMA5_DriverIRQHandler - bx r0 - .size DMA5_IRQHandler, . - DMA5_IRQHandler - - .align 1 - .thumb_func - .weak DMA6_IRQHandler - .type DMA6_IRQHandler, %function -DMA6_IRQHandler: - ldr r0,=DMA6_DriverIRQHandler - bx r0 - .size DMA6_IRQHandler, . - DMA6_IRQHandler - - .align 1 - .thumb_func - .weak DMA7_IRQHandler - .type DMA7_IRQHandler, %function -DMA7_IRQHandler: - ldr r0,=DMA7_DriverIRQHandler - bx r0 - .size DMA7_IRQHandler, . - DMA7_IRQHandler - - .align 1 - .thumb_func - .weak DMA8_IRQHandler - .type DMA8_IRQHandler, %function -DMA8_IRQHandler: - ldr r0,=DMA8_DriverIRQHandler - bx r0 - .size DMA8_IRQHandler, . - DMA8_IRQHandler - - .align 1 - .thumb_func - .weak DMA9_IRQHandler - .type DMA9_IRQHandler, %function -DMA9_IRQHandler: - ldr r0,=DMA9_DriverIRQHandler - bx r0 - .size DMA9_IRQHandler, . - DMA9_IRQHandler - - .align 1 - .thumb_func - .weak DMA10_IRQHandler - .type DMA10_IRQHandler, %function -DMA10_IRQHandler: - ldr r0,=DMA10_DriverIRQHandler - bx r0 - .size DMA10_IRQHandler, . - DMA10_IRQHandler - - .align 1 - .thumb_func - .weak DMA11_IRQHandler - .type DMA11_IRQHandler, %function -DMA11_IRQHandler: - ldr r0,=DMA11_DriverIRQHandler - bx r0 - .size DMA11_IRQHandler, . - DMA11_IRQHandler - - .align 1 - .thumb_func - .weak DMA12_IRQHandler - .type DMA12_IRQHandler, %function -DMA12_IRQHandler: - ldr r0,=DMA12_DriverIRQHandler - bx r0 - .size DMA12_IRQHandler, . - DMA12_IRQHandler - - .align 1 - .thumb_func - .weak DMA13_IRQHandler - .type DMA13_IRQHandler, %function -DMA13_IRQHandler: - ldr r0,=DMA13_DriverIRQHandler - bx r0 - .size DMA13_IRQHandler, . - DMA13_IRQHandler - - .align 1 - .thumb_func - .weak DMA14_IRQHandler - .type DMA14_IRQHandler, %function -DMA14_IRQHandler: - ldr r0,=DMA14_DriverIRQHandler - bx r0 - .size DMA14_IRQHandler, . - DMA14_IRQHandler - - .align 1 - .thumb_func - .weak DMA15_IRQHandler - .type DMA15_IRQHandler, %function -DMA15_IRQHandler: - ldr r0,=DMA15_DriverIRQHandler - bx r0 - .size DMA15_IRQHandler, . - DMA15_IRQHandler - - .align 1 - .thumb_func - .weak DMA_Error_IRQHandler - .type DMA_Error_IRQHandler, %function -DMA_Error_IRQHandler: - ldr r0,=DMA_Error_DriverIRQHandler - bx r0 - .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler - - .align 1 - .thumb_func - .weak I2C0_IRQHandler - .type I2C0_IRQHandler, %function -I2C0_IRQHandler: - ldr r0,=I2C0_DriverIRQHandler - bx r0 - .size I2C0_IRQHandler, . - I2C0_IRQHandler - - .align 1 - .thumb_func - .weak I2C1_IRQHandler - .type I2C1_IRQHandler, %function -I2C1_IRQHandler: - ldr r0,=I2C1_DriverIRQHandler - bx r0 - .size I2C1_IRQHandler, . - I2C1_IRQHandler - - .align 1 - .thumb_func - .weak SPI0_IRQHandler - .type SPI0_IRQHandler, %function -SPI0_IRQHandler: - ldr r0,=SPI0_DriverIRQHandler - bx r0 - .size SPI0_IRQHandler, . - SPI0_IRQHandler - - .align 1 - .thumb_func - .weak SPI1_IRQHandler - .type SPI1_IRQHandler, %function -SPI1_IRQHandler: - ldr r0,=SPI1_DriverIRQHandler - bx r0 - .size SPI1_IRQHandler, . - SPI1_IRQHandler - - .align 1 - .thumb_func - .weak I2S0_Tx_IRQHandler - .type I2S0_Tx_IRQHandler, %function -I2S0_Tx_IRQHandler: - ldr r0,=I2S0_Tx_DriverIRQHandler - bx r0 - .size I2S0_Tx_IRQHandler, . - I2S0_Tx_IRQHandler - - .align 1 - .thumb_func - .weak I2S0_Rx_IRQHandler - .type I2S0_Rx_IRQHandler, %function -I2S0_Rx_IRQHandler: - ldr r0,=I2S0_Rx_DriverIRQHandler - bx r0 - .size I2S0_Rx_IRQHandler, . - I2S0_Rx_IRQHandler - - .align 1 - .thumb_func - .weak UART0_RX_TX_IRQHandler - .type UART0_RX_TX_IRQHandler, %function -UART0_RX_TX_IRQHandler: - ldr r0,=UART0_RX_TX_DriverIRQHandler - bx r0 - .size UART0_RX_TX_IRQHandler, . - UART0_RX_TX_IRQHandler - - .align 1 - .thumb_func - .weak UART0_ERR_IRQHandler - .type UART0_ERR_IRQHandler, %function -UART0_ERR_IRQHandler: - ldr r0,=UART0_ERR_DriverIRQHandler - bx r0 - .size UART0_ERR_IRQHandler, . - UART0_ERR_IRQHandler - - .align 1 - .thumb_func - .weak UART1_RX_TX_IRQHandler - .type UART1_RX_TX_IRQHandler, %function -UART1_RX_TX_IRQHandler: - ldr r0,=UART1_RX_TX_DriverIRQHandler - bx r0 - .size UART1_RX_TX_IRQHandler, . - UART1_RX_TX_IRQHandler - - .align 1 - .thumb_func - .weak UART1_ERR_IRQHandler - .type UART1_ERR_IRQHandler, %function -UART1_ERR_IRQHandler: - ldr r0,=UART1_ERR_DriverIRQHandler - bx r0 - .size UART1_ERR_IRQHandler, . - UART1_ERR_IRQHandler - - .align 1 - .thumb_func - .weak UART2_RX_TX_IRQHandler - .type UART2_RX_TX_IRQHandler, %function -UART2_RX_TX_IRQHandler: - ldr r0,=UART2_RX_TX_DriverIRQHandler - bx r0 - .size UART2_RX_TX_IRQHandler, . - UART2_RX_TX_IRQHandler - - .align 1 - .thumb_func - .weak UART2_ERR_IRQHandler - .type UART2_ERR_IRQHandler, %function -UART2_ERR_IRQHandler: - ldr r0,=UART2_ERR_DriverIRQHandler - bx r0 - .size UART2_ERR_IRQHandler, . - UART2_ERR_IRQHandler - - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler DMA0_DriverIRQHandler - def_irq_handler DMA1_DriverIRQHandler - def_irq_handler DMA2_DriverIRQHandler - def_irq_handler DMA3_DriverIRQHandler - def_irq_handler DMA4_DriverIRQHandler - def_irq_handler DMA5_DriverIRQHandler - def_irq_handler DMA6_DriverIRQHandler - def_irq_handler DMA7_DriverIRQHandler - def_irq_handler DMA8_DriverIRQHandler - def_irq_handler DMA9_DriverIRQHandler - def_irq_handler DMA10_DriverIRQHandler - def_irq_handler DMA11_DriverIRQHandler - def_irq_handler DMA12_DriverIRQHandler - def_irq_handler DMA13_DriverIRQHandler - def_irq_handler DMA14_DriverIRQHandler - def_irq_handler DMA15_DriverIRQHandler - def_irq_handler DMA_Error_DriverIRQHandler - def_irq_handler MCM_IRQHandler - def_irq_handler FTFL_IRQHandler - def_irq_handler FTFL_Collision_IRQHandler - def_irq_handler PMC_IRQHandler - def_irq_handler LLWU_IRQHandler - def_irq_handler WDOG_EWM_IRQHandler - def_irq_handler RNG_IRQHandler - def_irq_handler I2C0_DriverIRQHandler - def_irq_handler I2C1_DriverIRQHandler - def_irq_handler SPI0_DriverIRQHandler - def_irq_handler SPI1_DriverIRQHandler - def_irq_handler I2S0_Tx_DriverIRQHandler - def_irq_handler I2S0_Rx_DriverIRQHandler - def_irq_handler Reserved46_IRQHandler - def_irq_handler UART0_RX_TX_DriverIRQHandler - def_irq_handler UART0_ERR_DriverIRQHandler - def_irq_handler UART1_RX_TX_DriverIRQHandler - def_irq_handler UART1_ERR_DriverIRQHandler - def_irq_handler UART2_RX_TX_DriverIRQHandler - def_irq_handler UART2_ERR_DriverIRQHandler - def_irq_handler Reserved53_IRQHandler - def_irq_handler Reserved54_IRQHandler - def_irq_handler ADC0_IRQHandler - def_irq_handler CMP0_IRQHandler - def_irq_handler CMP1_IRQHandler - def_irq_handler FTM0_IRQHandler - def_irq_handler FTM1_IRQHandler - def_irq_handler FTM2_IRQHandler - def_irq_handler CMT_IRQHandler - def_irq_handler RTC_IRQHandler - def_irq_handler RTC_Seconds_IRQHandler - def_irq_handler PIT0_IRQHandler - def_irq_handler PIT1_IRQHandler - def_irq_handler PIT2_IRQHandler - def_irq_handler PIT3_IRQHandler - def_irq_handler PDB0_IRQHandler - def_irq_handler USB0_IRQHandler - def_irq_handler USBDCD_IRQHandler - def_irq_handler Reserved71_IRQHandler - def_irq_handler Reserved72_IRQHandler - def_irq_handler MCG_IRQHandler - def_irq_handler LPTMR0_IRQHandler - def_irq_handler PORTA_IRQHandler - def_irq_handler PORTB_IRQHandler - def_irq_handler PORTC_IRQHandler - def_irq_handler PORTD_IRQHandler - def_irq_handler PORTE_IRQHandler - def_irq_handler SWI_IRQHandler - - .end diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/MKW24D512xxx5.icf b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/MKW24D512xxx5.icf deleted file mode 100644 index 2ce502a..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/MKW24D512xxx5.icf +++ /dev/null @@ -1,125 +0,0 @@ -/* -** ################################################################### -** Processor: MKW24D512VHA5 -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: MKW2xDRM Rev.2 July 2014 -** Version: rev. 2.0, 2014-11-26 -** Build: b160512 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** ################################################################### -*/ -define symbol __ram_vector_table__ = 1; - -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -define symbol __stack_size__=MBED_BOOT_STACK_SIZE; -define symbol __heap_size__=0x4000; - -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = 0; -} - -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = 0x80000; -} - -define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; -define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; - -define symbol m_interrupts_start = MBED_APP_START; -define symbol m_interrupts_end = MBED_APP_START + 0x3FF; - -define symbol m_flash_config_start = MBED_APP_START + 0x400; -define symbol m_flash_config_end = MBED_APP_START + 0x40F; - -define symbol m_text_start = MBED_APP_START + 0x410; -define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1; - -define symbol m_interrupts_ram_start = 0x1FFF8000; -define symbol m_interrupts_ram_end = 0x1FFF8000 + __ram_vector_table_offset__; - -define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; -define symbol m_data_end = 0x1FFFFFFF; - -define symbol m_data_2_start = 0x20000000; -define symbol m_data_2_end = 0x20007FFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; - -define memory mem with size = 4G; -define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end] - | mem:[from m_data_2_start to m_data_2_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end]; -define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in m_flash_config_region { section FlashConfig }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in m_interrupts_ram_region { section m_interrupts_ram }; - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.S deleted file mode 100644 index 1363c29..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.S +++ /dev/null @@ -1,718 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKW24D5.s -; @purpose: CMSIS Cortex-M4 Core Device Startup File -; MKW24D5 -; @version: 2.0 -; @date: 2014-11-26 -; @build: b160512 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD MemManage_Handler ;MPU Fault Handler - DCD BusFault_Handler ;Bus Fault Handler - DCD UsageFault_Handler ;Usage Fault Handler -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD DMA4_IRQHandler ;DMA channel 4 transfer complete - DCD DMA5_IRQHandler ;DMA channel 5 transfer complete - DCD DMA6_IRQHandler ;DMA channel 6 transfer complete - DCD DMA7_IRQHandler ;DMA channel 7 transfer complete - DCD DMA8_IRQHandler ;DMA channel 8 transfer complete - DCD DMA9_IRQHandler ;DMA channel 9 transfer complete - DCD DMA10_IRQHandler ;DMA channel 10 transfer complete - DCD DMA11_IRQHandler ;DMA channel 11 transfer complete - DCD DMA12_IRQHandler ;DMA channel 12 transfer complete - DCD DMA13_IRQHandler ;DMA channel 13 transfer complete - DCD DMA14_IRQHandler ;DMA channel 14 transfer complete - DCD DMA15_IRQHandler ;DMA channel 15 transfer complete - DCD DMA_Error_IRQHandler ;DMA channel 0 - 15 error - DCD MCM_IRQHandler ;MCM normal interrupt - DCD FTFL_IRQHandler ;FTFL command complete - DCD FTFL_Collision_IRQHandler ;FTFL read collision - DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low leakage wakeup - DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM - DCD RNG_IRQHandler ;Randon number generator - DCD I2C0_IRQHandler ;Inter-integrated circuit 0 - DCD I2C1_IRQHandler ;Inter-integrated circuit 1 - DCD SPI0_IRQHandler ;Serial peripheral Interface 0 - DCD SPI1_IRQHandler ;Serial peripheral Interface 1 - DCD I2S0_Tx_IRQHandler ;Integrated interchip sound 0 transmit interrupt - DCD I2S0_Rx_IRQHandler ;Integrated interchip sound 0 receive interrupt - DCD Reserved46_IRQHandler ;Reserved interrupt - DCD UART0_RX_TX_IRQHandler ;UART0 receive/transmit interrupt - DCD UART0_ERR_IRQHandler ;UART0 error interrupt - DCD UART1_RX_TX_IRQHandler ;UART1 receive/transmit interrupt - DCD UART1_ERR_IRQHandler ;UART1 error interrupt - DCD UART2_RX_TX_IRQHandler ;UART2 receive/transmit interrupt - DCD UART2_ERR_IRQHandler ;UART2 error interrupt - DCD Reserved53_IRQHandler ;Reserved interrupt - DCD Reserved54_IRQHandler ;Reserved interrupt - DCD ADC0_IRQHandler ;Analog-to-digital converter 0 - DCD CMP0_IRQHandler ;Comparator 0 - DCD CMP1_IRQHandler ;Comparator 1 - DCD FTM0_IRQHandler ;FlexTimer module 0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ;FlexTimer module 1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ;FlexTimer module 2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ;Carrier modulator transmitter - DCD RTC_IRQHandler ;Real time clock - DCD RTC_Seconds_IRQHandler ;Real time clock seconds - DCD PIT0_IRQHandler ;Periodic interrupt timer channel 0 - DCD PIT1_IRQHandler ;Periodic interrupt timer channel 1 - DCD PIT2_IRQHandler ;Periodic interrupt timer channel 2 - DCD PIT3_IRQHandler ;Periodic interrupt timer channel 3 - DCD PDB0_IRQHandler ;Programmable delay block - DCD USB0_IRQHandler ;USB OTG interrupt - DCD USBDCD_IRQHandler ;USB charger detect - DCD Reserved71_IRQHandler ;Reserved interrupt - DCD Reserved72_IRQHandler ;Reserved interrupt - DCD MCG_IRQHandler ;Multipurpose clock generator - DCD LPTMR0_IRQHandler ;Low power timer interrupt - DCD PORTA_IRQHandler ;Port A pin detect interrupt - DCD PORTB_IRQHandler ;Port B pin detect interrupt - DCD PORTC_IRQHandler ;Port C pin detect interrupt - DCD PORTD_IRQHandler ;Port D pin detect interrupt - DCD PORTE_IRQHandler ;Port E pin detect interrupt - DCD SWI_IRQHandler ;Software interrupt - DCD DefaultISR ;81 - DCD DefaultISR ;82 - DCD DefaultISR ;83 - DCD DefaultISR ;84 - DCD DefaultISR ;85 - DCD DefaultISR ;86 - DCD DefaultISR ;87 - DCD DefaultISR ;88 - DCD DefaultISR ;89 - DCD DefaultISR ;90 - DCD DefaultISR ;91 - DCD DefaultISR ;92 - DCD DefaultISR ;93 - DCD DefaultISR ;94 - DCD DefaultISR ;95 - DCD DefaultISR ;96 - DCD DefaultISR ;97 - DCD DefaultISR ;98 - DCD DefaultISR ;99 - DCD DefaultISR ;100 - DCD DefaultISR ;101 - DCD DefaultISR ;102 - DCD DefaultISR ;103 - DCD DefaultISR ;104 - DCD DefaultISR ;105 - DCD DefaultISR ;106 - DCD DefaultISR ;107 - DCD DefaultISR ;108 - DCD DefaultISR ;109 - DCD DefaultISR ;110 - DCD DefaultISR ;111 - DCD DefaultISR ;112 - DCD DefaultISR ;113 - DCD DefaultISR ;114 - DCD DefaultISR ;115 - DCD DefaultISR ;116 - DCD DefaultISR ;117 - DCD DefaultISR ;118 - DCD DefaultISR ;119 - DCD DefaultISR ;120 - DCD DefaultISR ;121 - DCD DefaultISR ;122 - DCD DefaultISR ;123 - DCD DefaultISR ;124 - DCD DefaultISR ;125 - DCD DefaultISR ;126 - DCD DefaultISR ;127 - DCD DefaultISR ;128 - DCD DefaultISR ;129 - DCD DefaultISR ;130 - DCD DefaultISR ;131 - DCD DefaultISR ;132 - DCD DefaultISR ;133 - DCD DefaultISR ;134 - DCD DefaultISR ;135 - DCD DefaultISR ;136 - DCD DefaultISR ;137 - DCD DefaultISR ;138 - DCD DefaultISR ;139 - DCD DefaultISR ;140 - DCD DefaultISR ;141 - DCD DefaultISR ;142 - DCD DefaultISR ;143 - DCD DefaultISR ;144 - DCD DefaultISR ;145 - DCD DefaultISR ;146 - DCD DefaultISR ;147 - DCD DefaultISR ;148 - DCD DefaultISR ;149 - DCD DefaultISR ;150 - DCD DefaultISR ;151 - DCD DefaultISR ;152 - DCD DefaultISR ;153 - DCD DefaultISR ;154 - DCD DefaultISR ;155 - DCD DefaultISR ;156 - DCD DefaultISR ;157 - DCD DefaultISR ;158 - DCD DefaultISR ;159 - DCD DefaultISR ;160 - DCD DefaultISR ;161 - DCD DefaultISR ;162 - DCD DefaultISR ;163 - DCD DefaultISR ;164 - DCD DefaultISR ;165 - DCD DefaultISR ;166 - DCD DefaultISR ;167 - DCD DefaultISR ;168 - DCD DefaultISR ;169 - DCD DefaultISR ;170 - DCD DefaultISR ;171 - DCD DefaultISR ;172 - DCD DefaultISR ;173 - DCD DefaultISR ;174 - DCD DefaultISR ;175 - DCD DefaultISR ;176 - DCD DefaultISR ;177 - DCD DefaultISR ;178 - DCD DefaultISR ;179 - DCD DefaultISR ;180 - DCD DefaultISR ;181 - DCD DefaultISR ;182 - DCD DefaultISR ;183 - DCD DefaultISR ;184 - DCD DefaultISR ;185 - DCD DefaultISR ;186 - DCD DefaultISR ;187 - DCD DefaultISR ;188 - DCD DefaultISR ;189 - DCD DefaultISR ;190 - DCD DefaultISR ;191 - DCD DefaultISR ;192 - DCD DefaultISR ;193 - DCD DefaultISR ;194 - DCD DefaultISR ;195 - DCD DefaultISR ;196 - DCD DefaultISR ;197 - DCD DefaultISR ;198 - DCD DefaultISR ;199 - DCD DefaultISR ;200 - DCD DefaultISR ;201 - DCD DefaultISR ;202 - DCD DefaultISR ;203 - DCD DefaultISR ;204 - DCD DefaultISR ;205 - DCD DefaultISR ;206 - DCD DefaultISR ;207 - DCD DefaultISR ;208 - DCD DefaultISR ;209 - DCD DefaultISR ;210 - DCD DefaultISR ;211 - DCD DefaultISR ;212 - DCD DefaultISR ;213 - DCD DefaultISR ;214 - DCD DefaultISR ;215 - DCD DefaultISR ;216 - DCD DefaultISR ;217 - DCD DefaultISR ;218 - DCD DefaultISR ;219 - DCD DefaultISR ;220 - DCD DefaultISR ;221 - DCD DefaultISR ;222 - DCD DefaultISR ;223 - DCD DefaultISR ;224 - DCD DefaultISR ;225 - DCD DefaultISR ;226 - DCD DefaultISR ;227 - DCD DefaultISR ;228 - DCD DefaultISR ;229 - DCD DefaultISR ;230 - DCD DefaultISR ;231 - DCD DefaultISR ;232 - DCD DefaultISR ;233 - DCD DefaultISR ;234 - DCD DefaultISR ;235 - DCD DefaultISR ;236 - DCD DefaultISR ;237 - DCD DefaultISR ;238 - DCD DefaultISR ;239 - DCD DefaultISR ;240 - DCD DefaultISR ;241 - DCD DefaultISR ;242 - DCD DefaultISR ;243 - DCD DefaultISR ;244 - DCD DefaultISR ;245 - DCD DefaultISR ;246 - DCD DefaultISR ;247 - DCD DefaultISR ;248 - DCD DefaultISR ;249 - DCD DefaultISR ;250 - DCD DefaultISR ;251 - DCD DefaultISR ;252 - DCD DefaultISR ;253 - DCD DefaultISR ;254 - DCD 0xFFFFFFFF ; Reserved for user TRIM value -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA2_IRQHandler - LDR R0, =DMA2_DriverIRQHandler - BX R0 - - PUBWEAK DMA3_IRQHandler - PUBWEAK DMA3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA3_IRQHandler - LDR R0, =DMA3_DriverIRQHandler - BX R0 - - PUBWEAK DMA4_IRQHandler - PUBWEAK DMA4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA4_IRQHandler - LDR R0, =DMA4_DriverIRQHandler - BX R0 - - PUBWEAK DMA5_IRQHandler - PUBWEAK DMA5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA5_IRQHandler - LDR R0, =DMA5_DriverIRQHandler - BX R0 - - PUBWEAK DMA6_IRQHandler - PUBWEAK DMA6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA6_IRQHandler - LDR R0, =DMA6_DriverIRQHandler - BX R0 - - PUBWEAK DMA7_IRQHandler - PUBWEAK DMA7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA7_IRQHandler - LDR R0, =DMA7_DriverIRQHandler - BX R0 - - PUBWEAK DMA8_IRQHandler - PUBWEAK DMA8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA8_IRQHandler - LDR R0, =DMA8_DriverIRQHandler - BX R0 - - PUBWEAK DMA9_IRQHandler - PUBWEAK DMA9_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA9_IRQHandler - LDR R0, =DMA9_DriverIRQHandler - BX R0 - - PUBWEAK DMA10_IRQHandler - PUBWEAK DMA10_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA10_IRQHandler - LDR R0, =DMA10_DriverIRQHandler - BX R0 - - PUBWEAK DMA11_IRQHandler - PUBWEAK DMA11_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA11_IRQHandler - LDR R0, =DMA11_DriverIRQHandler - BX R0 - - PUBWEAK DMA12_IRQHandler - PUBWEAK DMA12_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA12_IRQHandler - LDR R0, =DMA12_DriverIRQHandler - BX R0 - - PUBWEAK DMA13_IRQHandler - PUBWEAK DMA13_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA13_IRQHandler - LDR R0, =DMA13_DriverIRQHandler - BX R0 - - PUBWEAK DMA14_IRQHandler - PUBWEAK DMA14_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA14_IRQHandler - LDR R0, =DMA14_DriverIRQHandler - BX R0 - - PUBWEAK DMA15_IRQHandler - PUBWEAK DMA15_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA15_IRQHandler - LDR R0, =DMA15_DriverIRQHandler - BX R0 - - PUBWEAK DMA_Error_IRQHandler - PUBWEAK DMA_Error_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA_Error_IRQHandler - LDR R0, =DMA_Error_DriverIRQHandler - BX R0 - - PUBWEAK MCM_IRQHandler - PUBWEAK FTFL_IRQHandler - PUBWEAK FTFL_Collision_IRQHandler - PUBWEAK PMC_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK WDOG_EWM_IRQHandler - PUBWEAK RNG_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C0_IRQHandler - LDR R0, =I2C0_DriverIRQHandler - BX R0 - - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C1_IRQHandler - LDR R0, =I2C1_DriverIRQHandler - BX R0 - - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI0_IRQHandler - LDR R0, =SPI0_DriverIRQHandler - BX R0 - - PUBWEAK SPI1_IRQHandler - PUBWEAK SPI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI1_IRQHandler - LDR R0, =SPI1_DriverIRQHandler - BX R0 - - PUBWEAK I2S0_Tx_IRQHandler - PUBWEAK I2S0_Tx_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2S0_Tx_IRQHandler - LDR R0, =I2S0_Tx_DriverIRQHandler - BX R0 - - PUBWEAK I2S0_Rx_IRQHandler - PUBWEAK I2S0_Rx_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2S0_Rx_IRQHandler - LDR R0, =I2S0_Rx_DriverIRQHandler - BX R0 - - PUBWEAK Reserved46_IRQHandler - PUBWEAK UART0_RX_TX_IRQHandler - PUBWEAK UART0_RX_TX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART0_RX_TX_IRQHandler - LDR R0, =UART0_RX_TX_DriverIRQHandler - BX R0 - - PUBWEAK UART0_ERR_IRQHandler - PUBWEAK UART0_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART0_ERR_IRQHandler - LDR R0, =UART0_ERR_DriverIRQHandler - BX R0 - - PUBWEAK UART1_RX_TX_IRQHandler - PUBWEAK UART1_RX_TX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART1_RX_TX_IRQHandler - LDR R0, =UART1_RX_TX_DriverIRQHandler - BX R0 - - PUBWEAK UART1_ERR_IRQHandler - PUBWEAK UART1_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART1_ERR_IRQHandler - LDR R0, =UART1_ERR_DriverIRQHandler - BX R0 - - PUBWEAK UART2_RX_TX_IRQHandler - PUBWEAK UART2_RX_TX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART2_RX_TX_IRQHandler - LDR R0, =UART2_RX_TX_DriverIRQHandler - BX R0 - - PUBWEAK UART2_ERR_IRQHandler - PUBWEAK UART2_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART2_ERR_IRQHandler - LDR R0, =UART2_ERR_DriverIRQHandler - BX R0 - - PUBWEAK Reserved53_IRQHandler - PUBWEAK Reserved54_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK CMP1_IRQHandler - PUBWEAK FTM0_IRQHandler - PUBWEAK FTM1_IRQHandler - PUBWEAK FTM2_IRQHandler - PUBWEAK CMT_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT0_IRQHandler - PUBWEAK PIT1_IRQHandler - PUBWEAK PIT2_IRQHandler - PUBWEAK PIT3_IRQHandler - PUBWEAK PDB0_IRQHandler - PUBWEAK USB0_IRQHandler - PUBWEAK USBDCD_IRQHandler - PUBWEAK Reserved71_IRQHandler - PUBWEAK Reserved72_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTB_IRQHandler - PUBWEAK PORTC_IRQHandler - PUBWEAK PORTD_IRQHandler - PUBWEAK PORTE_IRQHandler - PUBWEAK SWI_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(1) -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -DMA4_DriverIRQHandler -DMA5_DriverIRQHandler -DMA6_DriverIRQHandler -DMA7_DriverIRQHandler -DMA8_DriverIRQHandler -DMA9_DriverIRQHandler -DMA10_DriverIRQHandler -DMA11_DriverIRQHandler -DMA12_DriverIRQHandler -DMA13_DriverIRQHandler -DMA14_DriverIRQHandler -DMA15_DriverIRQHandler -DMA_Error_DriverIRQHandler -MCM_IRQHandler -FTFL_IRQHandler -FTFL_Collision_IRQHandler -PMC_IRQHandler -LLWU_IRQHandler -WDOG_EWM_IRQHandler -RNG_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -SPI1_DriverIRQHandler -I2S0_Tx_DriverIRQHandler -I2S0_Rx_DriverIRQHandler -Reserved46_IRQHandler -UART0_RX_TX_DriverIRQHandler -UART0_ERR_DriverIRQHandler -UART1_RX_TX_DriverIRQHandler -UART1_ERR_DriverIRQHandler -UART2_RX_TX_DriverIRQHandler -UART2_ERR_DriverIRQHandler -Reserved53_IRQHandler -Reserved54_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -Reserved71_IRQHandler -Reserved72_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -DefaultISR - B DefaultISR - - END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/cmsis.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/cmsis.h deleted file mode 100644 index 7423a12..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "fsl_device_registers.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/cmsis_nvic.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/cmsis_nvic.h deleted file mode 100644 index 348e984..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/cmsis_nvic.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -extern uint32_t Image$$VECTOR_RAM$$Base[]; -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#else -extern uint32_t __VECTOR_RAM[]; -#endif - -/* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 65) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/fsl_device_registers.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/fsl_device_registers.h deleted file mode 100644 index 43347a2..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/fsl_device_registers.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_MKW24D512VHA5)) - -#define KW24D5_SERIES - -/* CMSIS-style register definitions */ -#include "MKW24D5.h" -/* CPU specific feature definitions */ -#include "MKW24D5_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/system_MKW24D5.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/system_MKW24D5.c deleted file mode 100644 index b7f1b7d..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/system_MKW24D5.c +++ /dev/null @@ -1,232 +0,0 @@ -/* -** ################################################################### -** Processor: MKW24D512VHA5 -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: MKW2xDRM Rev.2 July 2014 -** Version: rev. 2.0, 2014-11-26 -** Build: b160512 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-11-22) -** Initial version. -** - rev. 2.0 (2014-11-26) -** update of SystemInit() imlementation -** Module access macro module_BASES replaced by module_BASE_PTRS. -** Register accessor macros added to the memory map. -** MCG - bit LOLS in MCG_S register renamed to LOLS0. -** DAC0 registers removed. -** -** ################################################################### -*/ - -/*! - * @file MKW24D5 - * @version 2.0 - * @date 2014-11-26 - * @brief Device specific configuration file for MKW24D5 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - - -/* ---------------------------------------------------------------------------- - -- ExtClk_Setup_HookUp() - ---------------------------------------------------------------------------- */ - -#pragma weak ExtClk_Setup_HookUp -uint8_t ExtClk_Setup_HookUp(uint32_t clk_out_value) { - uint8_t result = 0; - switch (clk_out_value) { - case 4000000U: - /* Start XCVR clock in order to derive MCGOUTCLK */ - SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; /* Ungate PORTB and PORTC clock*/ - GPIOB->PDDR |= 0x00080000u; /* Set PORTB.19 as output - XCVR RESET pin */ - GPIOC->PDDR |= 0x00000001u; /* Set PORTC.0 as output - XCVR GPIO5 pin */ - PORTB->PCR[19] = (PORTB->PCR[19] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(0x01u); /* PORTB.19 as GPIO */ - PORTC->PCR[0] = (PORTC->PCR[0] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(0x01u); /* PORTC.0 as GPIO*/ - GPIOC->PCOR = 0x00000001u; /* Clear XCVR GPIO5 pin*/ - GPIOB->PCOR = 0x00080000u; /* Clear XCVR RESET pin*/ - GPIOB->PSOR = 0x00080000u; /* Set XCVR RESET pin*/ - result = 1U; /* The output was set successfully */ - break; - case 0U: - /* No initialization, modem remains in the reset state */ - result = 1U; /* The output was set successfully */ - break; - default: - result = 0U; /* Requested value cannot be set */ - break; - } - return result; -} - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { - /* Watchdog disable */ -#if (DISABLE_WDOG) - /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ - WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ - /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ - WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ - /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ - WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | - WDOG_STCTRLH_WAITEN_MASK | - WDOG_STCTRLH_STOPEN_MASK | - WDOG_STCTRLH_ALLOWUPDATE_MASK | - WDOG_STCTRLH_CLKSRC_MASK | - 0x0100U; -#endif /* (DISABLE_WDOG) */ - -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - - uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ - uint16_t Divider; - - if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { - /* Output of FLL or PLL is selected */ - if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { - /* FLL is selected */ - if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { - /* External reference clock is selected */ - if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) { - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - } - if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { - switch (MCG->C1 & MCG_C1_FRDIV_MASK) { - case 0x38U: - Divider = 1536U; - break; - case 0x30U: - Divider = 1280U; - break; - default: - Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - break; - } - } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ - Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - } - MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ - } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ - } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - /* Select correct multiplier to calculate the MCG output clock */ - switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case 0x00U: - MCGOUTClock *= 640U; - break; - case 0x20U: - MCGOUTClock *= 1280U; - break; - case 0x40U: - MCGOUTClock *= 1920U; - break; - case 0x60U: - MCGOUTClock *= 2560U; - break; - case 0x80U: - MCGOUTClock *= 732U; - break; - case 0xA0U: - MCGOUTClock *= 1464U; - break; - case 0xC0U: - MCGOUTClock *= 2197U; - break; - case 0xE0U: - MCGOUTClock *= 2929U; - break; - default: - break; - } - } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ - /* PLL is selected */ - Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); - MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ - Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); - MCGOUTClock *= Divider; /* Calculate the MCG output clock */ - } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { - /* Internal reference clock is selected */ - if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ - } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ - Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); - MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ - } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { - /* External reference clock is selected */ - if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) { - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - } - } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ - /* Reserved value */ - return; - } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ - SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/system_MKW24D5.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/system_MKW24D5.h deleted file mode 100644 index b3f96dc..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/system_MKW24D5.h +++ /dev/null @@ -1,147 +0,0 @@ -/* -** ################################################################### -** Processor: MKW24D512VHA5 -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: MKW2xDRM Rev.2 July 2014 -** Version: rev. 2.0, 2014-11-26 -** Build: b160512 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-11-22) -** Initial version. -** - rev. 2.0 (2014-11-26) -** update of SystemInit() imlementation -** Module access macro module_BASES replaced by module_BASE_PTRS. -** Register accessor macros added to the memory map. -** MCG - bit LOLS in MCG_S register renamed to LOLS0. -** DAC0 registers removed. -** -** ################################################################### -*/ - -/*! - * @file MKW24D5 - * @version 2.0 - * @date 2014-11-26 - * @brief Device specific configuration file for MKW24D5 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_MKW24D5_H_ -#define _SYSTEM_MKW24D5_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#ifndef DISABLE_WDOG - #define DISABLE_WDOG 1 -#endif - -/* Define clock source values */ - -#define CPU_XTAL32k_CLK_HZ 32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz */ -#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */ -#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */ - -/* RTC oscillator setting */ -/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */ -#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */ - -/* Low power mode enable */ -/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ -#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ - -#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ -#define CPU_XTAL_CLK_HZ 4000000U /* Value of the clock provided by the wireless modem by default */ - - - -/** - * @brief Configure the external clock source - * - * The wireless modem present in the system can supply clock which can be used - * as a clock source for the whole system. This function is defined as weak. - * - */ -extern uint8_t ExtClk_Setup_HookUp(uint32_t clk_out_value); -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_MKW24D5_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_adc16.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_adc16.c deleted file mode 100644 index 4fee1a8..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_adc16.c +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_adc16.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ADC16 module. - * - * @param base ADC16 peripheral base address - */ -static uint32_t ADC16_GetInstance(ADC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ADC16 bases for each instance. */ -static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS; - -/*! @brief Pointers to ADC16 clocks for each instance. */ -static const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t ADC16_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++) - { - if (s_adc16Bases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_ADC16_COUNT); - - return instance; -} - -void ADC16_Init(ADC_Type *base, const adc16_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - - /* Enable the clock. */ - CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]); - - /* ADCx_CFG1. */ - tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution); - if (kADC16_LongSampleDisabled != config->longSampleMode) - { - tmp32 |= ADC_CFG1_ADLSMP_MASK; - } - tmp32 |= ADC_CFG1_ADIV(config->clockDivider); - if (config->enableLowPower) - { - tmp32 |= ADC_CFG1_ADLPC_MASK; - } - base->CFG1 = tmp32; - - /* ADCx_CFG2. */ - tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK); - if (kADC16_LongSampleDisabled != config->longSampleMode) - { - tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode); - } - if (config->enableHighSpeed) - { - tmp32 |= ADC_CFG2_ADHSC_MASK; - } - if (config->enableAsynchronousClock) - { - tmp32 |= ADC_CFG2_ADACKEN_MASK; - } - base->CFG2 = tmp32; - - /* ADCx_SC2. */ - tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK); - tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource); - base->SC2 = tmp32; - - /* ADCx_SC3. */ - if (config->enableContinuousConversion) - { - base->SC3 |= ADC_SC3_ADCO_MASK; - } - else - { - base->SC3 &= ~ADC_SC3_ADCO_MASK; - } -} - -void ADC16_Deinit(ADC_Type *base) -{ - /* Disable the clock. */ - CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]); -} - -void ADC16_GetDefaultConfig(adc16_config_t *config) -{ - assert(NULL != config); - - config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; - config->clockSource = kADC16_ClockSourceAsynchronousClock; - config->enableAsynchronousClock = true; - config->clockDivider = kADC16_ClockDivider8; - config->resolution = kADC16_ResolutionSE12Bit; - config->longSampleMode = kADC16_LongSampleDisabled; - config->enableHighSpeed = false; - config->enableLowPower = false; - config->enableContinuousConversion = false; -} - -#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION -status_t ADC16_DoAutoCalibration(ADC_Type *base) -{ - bool bHWTrigger = false; - volatile uint32_t tmp32; /* 'volatile' here is for the dummy read of ADCx_R[0] register. */ - status_t status = kStatus_Success; - - /* The calibration would be failed when in hardwar mode. - * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ - if (0U != (ADC_SC2_ADTRG_MASK & base->SC2)) - { - bHWTrigger = true; - base->SC2 &= ~ADC_SC2_ADTRG_MASK; - } - - /* Clear the CALF and launch the calibration. */ - base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK; - while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U))) - { - /* Check the CALF when the calibration is active. */ - if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) - { - status = kStatus_Fail; - break; - } - } - tmp32 = base->R[0]; /* Dummy read to clear COCO caused by calibration. */ - - /* Restore the hardware trigger setting if it was enabled before. */ - if (bHWTrigger) - { - base->SC2 |= ADC_SC2_ADTRG_MASK; - } - /* Check the CALF at the end of calibration. */ - if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) - { - status = kStatus_Fail; - } - if (kStatus_Success != status) /* Check if the calibration process is succeed. */ - { - return status; - } - - /* Calculate the calibration values. */ - tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS; - tmp32 = 0x8000U | (tmp32 >> 1U); - base->PG = tmp32; - -#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE - tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS; - tmp32 = 0x8000U | (tmp32 >> 1U); - base->MG = tmp32; -#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ - - return kStatus_Success; -} -#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ - -#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT -void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode) -{ - if (kADC16_ChannelMuxA == mode) - { - base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; - } - else /* kADC16_ChannelMuxB. */ - { - base->CFG2 |= ADC_CFG2_MUXSEL_MASK; - } -} -#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ - -void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config) -{ - uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK); - - if (!config) /* Pass "NULL" to disable the feature. */ - { - base->SC2 = tmp32; - return; - } - /* Enable the feature. */ - tmp32 |= ADC_SC2_ACFE_MASK; - - /* Select the hardware compare working mode. */ - switch (config->hardwareCompareMode) - { - case kADC16_HardwareCompareMode0: - break; - case kADC16_HardwareCompareMode1: - tmp32 |= ADC_SC2_ACFGT_MASK; - break; - case kADC16_HardwareCompareMode2: - tmp32 |= ADC_SC2_ACREN_MASK; - break; - case kADC16_HardwareCompareMode3: - tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK; - break; - default: - break; - } - base->SC2 = tmp32; - - /* Load the compare values. */ - base->CV1 = ADC_CV1_CV(config->value1); - base->CV2 = ADC_CV2_CV(config->value2); -} - -#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE -void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode) -{ - uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK); - - if (kADC16_HardwareAverageDisabled != mode) - { - tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode); - } - base->SC3 = tmp32; -} -#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ - -#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA -void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config) -{ - uint32_t tmp32; - - if (!config) /* Passing "NULL" is to disable the feature. */ - { - base->PGA = 0U; - return; - } - - /* Enable the PGA and set the gain value. */ - tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain); - - /* Configure the misc features for PGA. */ - if (config->enableRunInNormalMode) - { - tmp32 |= ADC_PGA_PGALPb_MASK; - } -#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING - if (config->disablePgaChopping) - { - tmp32 |= ADC_PGA_PGACHPb_MASK; - } -#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ -#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT - if (config->enableRunInOffsetMeasurement) - { - tmp32 |= ADC_PGA_PGAOFSM_MASK; - } -#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ - base->PGA = tmp32; -} -#endif /* FSL_FEATURE_ADC16_HAS_PGA */ - -uint32_t ADC16_GetStatusFlags(ADC_Type *base) -{ - uint32_t ret = 0; - - if (0U != (base->SC2 & ADC_SC2_ADACT_MASK)) - { - ret |= kADC16_ActiveFlag; - } -#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION - if (0U != (base->SC3 & ADC_SC3_CALF_MASK)) - { - ret |= kADC16_CalibrationFailedFlag; - } -#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ - return ret; -} - -void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ -#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION - if (0U != (mask & kADC16_CalibrationFailedFlag)) - { - base->SC3 |= ADC_SC3_CALF_MASK; - } -#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ -} - -void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config) -{ - assert(channelGroup < ADC_SC1_COUNT); - assert(NULL != config); - - uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */ - -#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE - /* Enable the differential conversion. */ - if (config->enableDifferentialConversion) - { - sc1 |= ADC_SC1_DIFF_MASK; - } -#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ - /* Enable the interrupt when the conversion is done. */ - if (config->enableInterruptOnConversionCompleted) - { - sc1 |= ADC_SC1_AIEN_MASK; - } - base->SC1[channelGroup] = sc1; -} - -uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) -{ - assert(channelGroup < ADC_SC1_COUNT); - - uint32_t ret = 0U; - - if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK)) - { - ret |= kADC16_ChannelConversionDoneFlag; - } - return ret; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_adc16.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_adc16.h deleted file mode 100644 index 7f5169a..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_adc16.h +++ /dev/null @@ -1,526 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_ADC16_H_ -#define _FSL_ADC16_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup adc16 - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief ADC16 driver version 2.0.0. */ -#define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief Channel status flags. - */ -enum _adc16_channel_status_flags -{ - kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */ -}; - -/*! - * @brief Converter status flags. - */ -enum _adc16_status_flags -{ - kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */ -#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION - kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */ -#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ -}; - -#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT -/*! - * @brief Channel multiplexer mode for each channel. - * - * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b - * are the different channels but share the same channel number. - */ -typedef enum _adc_channel_mux_mode -{ - kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */ - kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */ -} adc16_channel_mux_mode_t; -#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ - -/*! - * @brief Clock divider for the converter. - */ -typedef enum _adc16_clock_divider -{ - kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */ - kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */ - kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */ - kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */ -} adc16_clock_divider_t; - -/*! - *@brief Converter's resolution. - */ -typedef enum _adc16_resolution -{ - /* This group of enumeration is for internal use which is related to register setting. */ - kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */ - kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */ - kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */ - - /* This group of enumeration is for public user. */ - kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */ - kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */ - kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */ -#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE - kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */ - kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */ - kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */ -#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ - -#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U) - /* 16-bit is supported by default. */ - kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */ - kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */ -#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE - kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */ -#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ -#endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */ -} adc16_resolution_t; - -/*! - * @brief Clock source. - */ -typedef enum _adc16_clock_source -{ - kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */ - kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */ - kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */ - kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */ - - /* Chip defined clock source */ - kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */ -} adc16_clock_source_t; - -/*! - * @brief Long sample mode. - */ -typedef enum _adc16_long_sample_mode -{ - kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */ - kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */ - kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */ - kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */ - kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */ -} adc16_long_sample_mode_t; - -/*! - * @brief Reference voltage source. - */ -typedef enum _adc16_reference_voltage_source -{ - kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */ - kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */ -} adc16_reference_voltage_source_t; - -#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE -/*! - * @brief Hardware average mode. - */ -typedef enum _adc16_hardware_average_mode -{ - kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ - kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ - kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ - kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ - kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/ -} adc16_hardware_average_mode_t; -#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ - -/*! - * @brief Hardware compare mode. - */ -typedef enum _adc16_hardware_compare_mode -{ - kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */ - kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */ - kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2; - else, value1 > x > value2. */ - kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2; - else x >= value1 || x <= value2. */ -} adc16_hardware_compare_mode_t; - -#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA -/*! - * @brief PGA's Gain mode. - */ -typedef enum _adc16_pga_gain -{ - kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */ - kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */ - kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */ - kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */ - kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */ - kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */ - kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */ -} adc16_pga_gain_t; -#endif /* FSL_FEATURE_ADC16_HAS_PGA */ - -/*! - * @brief ADC16 converter configuration . - */ -typedef struct _adc16_config -{ - adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ - adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */ - bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */ - adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */ - adc16_resolution_t resolution; /*!< Select the sample resolution mode. */ - adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */ - bool enableHighSpeed; /*!< Enable the high-speed mode. */ - bool enableLowPower; /*!< Enable low power. */ - bool enableContinuousConversion; /*!< Enable continuous conversion mode. */ -} adc16_config_t; - -/*! - * @brief ADC16 Hardware compare configuration. - */ -typedef struct _adc16_hardware_compare_config -{ - adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. - See "adc16_hardware_compare_mode_t". */ - int16_t value1; /*!< Setting value1 for hardware compare mode. */ - int16_t value2; /*!< Setting value2 for hardware compare mode. */ -} adc16_hardware_compare_config_t; - -/*! - * @brief ADC16 channel conversion configuration. - */ -typedef struct _adc16_channel_config -{ - uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. - See channel connection information for each chip in Reference - Manual document. */ - bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */ -#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE - bool enableDifferentialConversion; /*!< Using Differential sample mode. */ -#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ -} adc16_channel_config_t; - -#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA -/*! - * @brief ADC16 programmable gain amplifier configuration. - */ -typedef struct _adc16_pga_config -{ - adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */ - bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */ -#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING - bool disablePgaChopping; /*!< Disable the PGA chopping function. - The PGA employs chopping to remove/reduce offset and 1/f noise and offers - an offset measurement configuration that aids the offset calibration. */ -#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ -#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT - bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode. - When this feature is enabled, the PGA disconnects itself from the external - inputs and auto-configures into offset measurement mode. With this field - set, run the ADC in the recommended settings and enable the maximum hardware - averaging to get the PGA offset number. The output is the - (PGA offset * (64+1)) for the given PGA setting. */ -#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ -} adc16_pga_config_t; -#endif /* FSL_FEATURE_ADC16_HAS_PGA */ - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the ADC16 module. - * - * @param base ADC16 peripheral base address. - * @param config Pointer to configuration structure. See "adc16_config_t". - */ -void ADC16_Init(ADC_Type *base, const adc16_config_t *config); - -/*! - * @brief De-initializes the ADC16 module. - * - * @param base ADC16 peripheral base address. - */ -void ADC16_Deinit(ADC_Type *base); - -/*! - * @brief Gets an available pre-defined settings for converter's configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * @code - * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; - * config->clockSource = kADC16_ClockSourceAsynchronousClock; - * config->enableAsynchronousClock = true; - * config->clockDivider = kADC16_ClockDivider8; - * config->resolution = kADC16_ResolutionSE12Bit; - * config->longSampleMode = kADC16_LongSampleDisabled; - * config->enableHighSpeed = false; - * config->enableLowPower = false; - * config->enableContinuousConversion = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void ADC16_GetDefaultConfig(adc16_config_t *config); - -#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION -/*! - * @brief Automates the hardware calibration. - * - * This auto calibration helps to adjust the plus/minus side gain automatically on the converter's working situation. - * Execute the calibration before using the converter. Note that the hardware trigger should be used - * during calibration. - * - * @param base ADC16 peripheral base address. - * - * @return Execution status. - * @retval kStatus_Success Calibration is done successfully. - * @retval kStatus_Fail Calibration is failed. - */ -status_t ADC16_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ - -#if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION -/*! - * @brief Sets the offset value for the conversion result. - * - * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result - * is subtracted by it. Note, the hardware calibration fills the offset value automatically. - * - * @param base ADC16 peripheral base address. - * @param value Setting offset value. - */ -static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value) -{ - base->OFS = (uint32_t)(value); -} -#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */ - -/* @} */ - -/*! - * @name Advanced Feature - * @{ - */ - -#if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA -/*! - * @brief Enables generating the DMA trigger when conversion is completed. - * - * @param base ADC16 peripheral base address. - * @param enable Switcher of DMA feature. "true" means to enable, "false" means not. - */ -static inline void ADC16_EnableDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SC2 |= ADC_SC2_DMAEN_MASK; - } - else - { - base->SC2 &= ~ADC_SC2_DMAEN_MASK; - } -} -#endif /* FSL_FEATURE_ADC16_HAS_DMA */ - -/*! - * @brief Enables the hardware trigger mode. - * - * @param base ADC16 peripheral base address. - * @param enable Switcher of hardware trigger feature. "true" means to enable, "false" means not. - */ -static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SC2 |= ADC_SC2_ADTRG_MASK; - } - else - { - base->SC2 &= ~ADC_SC2_ADTRG_MASK; - } -} - -#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT -/*! - * @brief Sets the channel mux mode. - * - * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an - * indicated channel. - * - * @param base ADC16 peripheral base address. - * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t". - */ -void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode); -#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ - -/*! - * @brief Configures the hardware compare mode. - * - * The hardware compare mode provides a way to process the conversion result automatically by hardware. Only the result - * in - * compare range is available. To compare the range, see "adc16_hardware_compare_mode_t", or the reference - * manual document for more detailed information. - * - * @param base ADC16 peripheral base address. - * @param config Pointer to "adc16_hardware_compare_config_t" structure. Passing "NULL" is to disable the feature. - */ -void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config); - -#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE -/*! - * @brief Sets the hardware average mode. - * - * Hardware average mode provides a way to process the conversion result automatically by hardware. The multiple - * conversion results are accumulated and averaged internally. This aids reading results. - * - * @param base ADC16 peripheral base address. - * @param mode Setting hardware average mode. See "adc16_hardware_average_mode_t". - */ -void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode); -#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ - -#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA -/*! - * @brief Configures the PGA for converter's front end. - * - * @param base ADC16 peripheral base address. - * @param config Pointer to "adc16_pga_config_t" structure. Passing "NULL" is to disable the feature. - */ -void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config); -#endif /* FSL_FEATURE_ADC16_HAS_PGA */ - -/*! - * @brief Gets the status flags of the converter. - * - * @param base ADC16 peripheral base address. - * - * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags". - */ -uint32_t ADC16_GetStatusFlags(ADC_Type *base); - -/*! - * @brief Clears the status flags of the converter. - * - * @param base ADC16 peripheral base address. - * @param mask Mask value for the cleared flags. See "_adc16_status_flags". - */ -void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Conversion Channel - * @{ - */ - -/*! - * @brief Configures the conversion channel. - * - * This operation triggers the conversion if in software trigger mode. When in hardware trigger mode, this API - * configures the channel while the external trigger source helps to trigger the conversion. - * - * Note that the "Channel Group" has a detailed description. - * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one - * group of status and control register, one for each conversion. The channel group parameter indicates which group of - * registers are used channel group 0 is for Group A registers and channel group 1 is for Group B registers. The - * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of - * the channel groups is actively controlling ADC conversions. Channel group 0 is used for both software and hardware - * trigger modes of operation. Channel groups 1 and greater indicate potentially multiple channel group registers for - * use only in hardware trigger mode. See the chip configuration information in the MCU reference manual about the - * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used - * for software trigger operation and therefore writes to these channel groups do not initiate a new conversion. - * Updating channel group 0 while a different channel group is actively controlling a conversion is allowed and - * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a - * conversion aborts the current conversion. - * - * @param base ADC16 peripheral base address. - * @param channelGroup Channel group index. - * @param config Pointer to "adc16_channel_config_t" structure for conversion channel. - */ -void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config); - -/*! - * @brief Gets the conversion value. - * - * @param base ADC16 peripheral base address. - * @param channelGroup Channel group index. - * - * @return Conversion value. - */ -static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) -{ - assert(channelGroup < ADC_R_COUNT); - - return base->R[channelGroup]; -} - -/*! - * @brief Gets the status flags of channel. - * - * @param base ADC16 peripheral base address. - * @param channelGroup Channel group index. - * - * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags". - */ -uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_ADC16_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_clock.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_clock.c deleted file mode 100644 index da51adc..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_clock.c +++ /dev/null @@ -1,2295 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 - 2019, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_clock.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.clock" -#endif - -/* Macro definition remap workaround. */ -#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) -#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK -#endif -#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) -#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK -#endif -#if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK))) -#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK -#endif -#if (defined(MCG_C6_CME_MASK) && !(defined(MCG_C6_CME0_MASK))) -#define MCG_C6_CME0_MASK MCG_C6_CME_MASK -#endif - -/* PLL fixed multiplier when there is not PRDIV and VDIV. */ -#define PLL_FIXED_MULT (375U) -/* Max frequency of the reference clock used for internal clock trim. */ -#define TRIM_REF_CLK_MIN (8000000U) -/* Min frequency of the reference clock used for internal clock trim. */ -#define TRIM_REF_CLK_MAX (16000000U) -/* Max trim value of fast internal reference clock. */ -#define TRIM_FIRC_MAX (5000000U) -/* Min trim value of fast internal reference clock. */ -#define TRIM_FIRC_MIN (3000000U) -/* Max trim value of fast internal reference clock. */ -#define TRIM_SIRC_MAX (39063U) -/* Min trim value of fast internal reference clock. */ -#define TRIM_SIRC_MIN (31250U) - -#define MCG_S_IRCST_VAL ((MCG->S & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT) -#define MCG_S_CLKST_VAL (((uint32_t)MCG->S & (uint32_t)MCG_S_CLKST_MASK) >> (uint32_t)MCG_S_CLKST_SHIFT) -#define MCG_S_IREFST_VAL (((uint32_t)MCG->S & (uint32_t)MCG_S_IREFST_MASK) >> (uint32_t)MCG_S_IREFST_SHIFT) -#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT) -#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT) -#define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT) -#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT) -#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT) -#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT) -#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT) -#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT) -#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT) -#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT) -#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) -#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) -#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT) -#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT) -#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT) -#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT) - -#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK) - -#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) -#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) -#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) -#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT) -#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT) - -/* MCG_S_CLKST definition. */ -enum _mcg_clkout_stat -{ - kMCG_ClkOutStatFll, /* FLL. */ - kMCG_ClkOutStatInt, /* Internal clock. */ - kMCG_ClkOutStatExt, /* External clock. */ - kMCG_ClkOutStatPll /* PLL. */ -}; - -/* MCG_S_PLLST definition. */ -enum _mcg_pllst -{ - kMCG_PllstFll, /* FLL is used. */ - kMCG_PllstPll /* PLL is used. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Slow internal reference clock frequency. */ -static uint32_t s_slowIrcFreq = 32768U; -/* Fast internal reference clock frequency. */ -static uint32_t s_fastIrcFreq = 4000000U; - -/* External XTAL0 (OSC0) clock frequency. */ -volatile uint32_t g_xtal0Freq; -/* External XTAL32K clock frequency. */ -volatile uint32_t g_xtal32Freq; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the MCG external reference clock frequency. - * - * Get the current MCG external reference clock frequency in Hz. It is - * the frequency select by MCG_C7[OSCSEL]. This is an internal function. - * - * @return MCG external reference clock frequency in Hz. - */ -static uint32_t CLOCK_GetMcgExtClkFreq(void); - -/*! - * @brief Get the MCG FLL external reference clock frequency. - * - * Get the current MCG FLL external reference clock frequency in Hz. It is - * the frequency after by MCG_C1[FRDIV]. This is an internal function. - * - * @return MCG FLL external reference clock frequency in Hz. - */ -static uint32_t CLOCK_GetFllExtRefClkFreq(void); - -/*! - * @brief Get the MCG FLL reference clock frequency. - * - * Get the current MCG FLL reference clock frequency in Hz. It is - * the frequency select by MCG_C1[IREFS]. This is an internal function. - * - * @return MCG FLL reference clock frequency in Hz. - */ -static uint32_t CLOCK_GetFllRefClkFreq(void); - -/*! - * @brief Get the frequency of clock selected by MCG_C2[IRCS]. - * - * This clock's two output: - * 1. MCGOUTCLK when MCG_S[CLKST]=0. - * 2. MCGIRCLK when MCG_C1[IRCLKEN]=1. - * - * @return The frequency in Hz. - */ -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void); - -/*! - * @brief Get the MCG PLL/PLL0 reference clock frequency. - * - * Get the current MCG PLL/PLL0 reference clock frequency in Hz. - * This is an internal function. - * - * @return MCG PLL/PLL0 reference clock frequency in Hz. - */ -static uint32_t CLOCK_GetPll0RefFreq(void); - -/*! - * @brief Calculate the RANGE value base on crystal frequency. - * - * To setup external crystal oscillator, must set the register bits RANGE - * base on the crystal frequency. This function returns the RANGE base on the - * input frequency. This is an internal function. - * - * @param freq Crystal frequency in Hz. - * @return The RANGE value. - */ -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq); - -#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN -/*! - * @brief Delay function to wait FLL stable. - * - * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least - * 1ms. Every time changes FLL setting, should wait this time for FLL stable. - */ -static void CLOCK_FllStableDelay(void); -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN -static void CLOCK_FllStableDelay(void) -{ - /* - Should wait at least 1ms. Because in these modes, the core clock is 100MHz - at most, so this function could obtain the 1ms delay. - */ - volatile uint32_t i = 30000U; - while (0U != (i--)) - { - __NOP(); - } -} -#else /* With MCG_USER_CONFIG_FLL_STABLE_DELAY_EN defined. */ -/* Once user defines the MCG_USER_CONFIG_FLL_STABLE_DELAY_EN to use their own delay function, he has to - * create his own CLOCK_FllStableDelay() function in application code. Since the clock functions in this - * file would call the CLOCK_FllStableDelay() regardless how it is defined. - */ -extern void CLOCK_FllStableDelay(void); -#endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */ - -static uint32_t CLOCK_GetMcgExtClkFreq(void) -{ - uint32_t freq; - - switch (MCG_C7_OSCSEL_VAL) - { - case 0U: - /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ - assert(0U != g_xtal0Freq); - freq = g_xtal0Freq; - break; - case 1U: - /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ - assert(0U != g_xtal32Freq); - freq = g_xtal32Freq; - break; - default: - freq = 0U; - break; - } - - return freq; -} - -static uint32_t CLOCK_GetFllExtRefClkFreq(void) -{ - /* FllExtRef = McgExtRef / FllExtRefDiv */ - uint8_t frdiv; - uint8_t range; - uint8_t oscsel; - - uint32_t freq = CLOCK_GetMcgExtClkFreq(); - - if (0U == freq) - { - return freq; - } - - frdiv = MCG_C1_FRDIV_VAL; - freq >>= frdiv; - - range = MCG_C2_RANGE_VAL; - oscsel = MCG_C7_OSCSEL_VAL; - - /* - When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536. - 1. MCG_C7[OSCSEL] selects IRC48M. - 2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0. - */ - if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel))) - { - switch (frdiv) - { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - freq >>= 5u; - break; - case 6: - /* 64*20=1280 */ - freq /= 20u; - break; - case 7: - /* 128*12=1536 */ - freq /= 12u; - break; - default: - freq = 0u; - break; - } - } - - return freq; -} - -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void) -{ - if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) - { - /* Slow internal reference clock selected*/ - return s_slowIrcFreq; - } - else - { - /* Fast internal reference clock selected*/ - return s_fastIrcFreq >> MCG_SC_FCRDIV_VAL; - } -} - -static uint32_t CLOCK_GetFllRefClkFreq(void) -{ - /* If use external reference clock. */ - if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { - return CLOCK_GetFllExtRefClkFreq(); - } - /* If use internal reference clock. */ - else - { - return s_slowIrcFreq; - } -} - -static uint32_t CLOCK_GetPll0RefFreq(void) -{ - /* MCG external reference clock. */ - return CLOCK_GetMcgExtClkFreq(); -} - -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq) -{ - uint8_t range; - - if (freq <= 39063U) - { - range = 0U; - } - else if (freq <= 8000000U) - { - range = 1U; - } - else - { - range = 2U; - } - - return range; -} - -/*! - * brief Get the OSC0 external reference clock frequency (OSC0ERCLK). - * - * return Clock frequency in Hz. - */ -uint32_t CLOCK_GetOsc0ErClkFreq(void) -{ - if (OSC0->CR & OSC_CR_ERCLKEN_MASK) - { - /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ - assert(g_xtal0Freq); - return g_xtal0Freq; - } - else - { - return 0U; - } -} - -/*! - * brief Get the external reference 32K clock frequency (ERCLK32K). - * - * return Clock frequency in Hz. - */ -uint32_t CLOCK_GetEr32kClkFreq(void) -{ - uint32_t freq; - - switch (SIM_SOPT1_OSC32KSEL_VAL) - { - case 0U: /* OSC 32k clock */ - freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U; - break; - case 2U: /* RTC 32k clock */ - /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ - assert(g_xtal32Freq); - freq = g_xtal32Freq; - break; - case 3U: /* LPO clock */ - freq = LPO_CLK_FREQ; - break; - default: - freq = 0U; - break; - } - return freq; -} - -/*! - * brief Get the output clock frequency selected by SIM[PLLFLLSEL]. - * - * return Clock frequency in Hz. - */ -uint32_t CLOCK_GetPllFllSelClkFreq(void) -{ - uint32_t freq; - - switch (SIM_SOPT2_PLLFLLSEL_VAL) - { - case 0U: /* FLL. */ - freq = CLOCK_GetFllFreq(); - break; - case 1U: /* PLL. */ - freq = CLOCK_GetPll0Freq(); - break; - default: - freq = 0U; - break; - } - - return freq; -} - -/*! - * brief Get the platform clock frequency. - * - * return Clock frequency in Hz. - */ -uint32_t CLOCK_GetPlatClkFreq(void) -{ - return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); -} - -/*! - * brief Get the flash clock frequency. - * - * return Clock frequency in Hz. - */ -uint32_t CLOCK_GetFlashClkFreq(void) -{ - return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); -} - -/*! - * brief Get the bus clock frequency. - * - * return Clock frequency in Hz. - */ -uint32_t CLOCK_GetBusClkFreq(void) -{ - return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); -} - -/*! - * brief Get the core clock or system clock frequency. - * - * return Clock frequency in Hz. - */ -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); -} - -/*! - * brief Gets the clock frequency for a specific clock name. - * - * This function checks the current clock configurations and then calculates - * the clock frequency for a specific clock name defined in clock_name_t. - * The MCG must be properly configured before using this function. - * - * param clockName Clock names defined in clock_name_t - * return Clock frequency value in Hertz - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - - switch (clockName) - { - case kCLOCK_CoreSysClk: - case kCLOCK_PlatClk: - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); - break; - case kCLOCK_FlashClk: - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); - break; - case kCLOCK_PllFllSelClk: - freq = CLOCK_GetPllFllSelClkFreq(); - break; - case kCLOCK_Er32kClk: - freq = CLOCK_GetEr32kClkFreq(); - break; - case kCLOCK_McgFixedFreqClk: - freq = CLOCK_GetFixedFreqClkFreq(); - break; - case kCLOCK_McgInternalRefClk: - freq = CLOCK_GetInternalRefClkFreq(); - break; - case kCLOCK_McgFllClk: - freq = CLOCK_GetFllFreq(); - break; - case kCLOCK_McgPll0Clk: - freq = CLOCK_GetPll0Freq(); - break; - case kCLOCK_LpoClk: - freq = LPO_CLK_FREQ; - break; - case kCLOCK_Osc0ErClk: - freq = CLOCK_GetOsc0ErClkFreq(); - break; - default: - freq = 0U; - break; - } - - return freq; -} - -/*! - * brief Set the clock configure in SIM module. - * - * This function sets system layer clock settings in SIM module. - * - * param config Pointer to the configure structure. - */ -void CLOCK_SetSimConfig(sim_clock_config_t const *config) -{ - SIM->CLKDIV1 = config->clkdiv1; - CLOCK_SetPllFllSelClock(config->pllFllSel); - CLOCK_SetEr32kClock(config->er32kSrc); -} - -/*! brief Enable USB FS clock. - * - * param src USB FS clock source. - * param freq The frequency specified by src. - * retval true The clock is set successfully. - * retval false The clock source is invalid to get proper USB FS clock. - */ -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbfs0); - - if (kCLOCK_UsbSrcExt == src) - { - SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; - } - else - { - switch (freq) - { - case 120000000U: - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1); - break; - case 96000000U: - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0); - break; - case 72000000U: - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1); - break; - case 48000000U: - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0); - break; - default: - ret = false; - break; - } - - SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src); - } - - CLOCK_EnableClock(kCLOCK_Usbfs0); - - return ret; -} - -/*! - * brief Gets the MCG output clock (MCGOUTCLK) frequency. - * - * This function gets the MCG output clock frequency in Hz based on the current MCG - * register value. - * - * return The frequency of MCGOUTCLK. - */ -uint32_t CLOCK_GetOutClkFreq(void) -{ - uint32_t mcgoutclk; - uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL; - - switch (clkst) - { - case (uint32_t)kMCG_ClkOutStatPll: - mcgoutclk = CLOCK_GetPll0Freq(); - break; - case (uint32_t)kMCG_ClkOutStatFll: - mcgoutclk = CLOCK_GetFllFreq(); - break; - case (uint32_t)kMCG_ClkOutStatInt: - mcgoutclk = CLOCK_GetInternalRefClkSelectFreq(); - break; - case (uint32_t)kMCG_ClkOutStatExt: - mcgoutclk = CLOCK_GetMcgExtClkFreq(); - break; - default: - mcgoutclk = 0U; - break; - } - return mcgoutclk; -} - -/*! - * brief Gets the MCG FLL clock (MCGFLLCLK) frequency. - * - * This function gets the MCG FLL clock frequency in Hz based on the current MCG - * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and - * disabled in low power state in other modes. - * - * return The frequency of MCGFLLCLK. - */ -uint32_t CLOCK_GetFllFreq(void) -{ - static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}}; - - uint8_t drs, dmx32; - uint32_t freq; - - /* If FLL is not enabled currently, then return 0U. */ - if (0U != (MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) - { - return 0U; - } - - /* Get FLL reference clock frequency. */ - freq = CLOCK_GetFllRefClkFreq(); - if (0U == freq) - { - return freq; - } - - drs = MCG_C4_DRST_DRS_VAL; - dmx32 = MCG_C4_DMX32_VAL; - - return freq * fllFactorTable[drs][dmx32]; -} - -/*! - * brief Gets the MCG internal reference clock (MCGIRCLK) frequency. - * - * This function gets the MCG internal reference clock frequency in Hz based - * on the current MCG register value. - * - * return The frequency of MCGIRCLK. - */ -uint32_t CLOCK_GetInternalRefClkFreq(void) -{ - /* If MCGIRCLK is gated. */ - if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) - { - return 0U; - } - - return CLOCK_GetInternalRefClkSelectFreq(); -} - -/*! - * brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency. - * - * This function gets the MCG fixed frequency clock frequency in Hz based - * on the current MCG register value. - * - * return The frequency of MCGFFCLK. - */ -uint32_t CLOCK_GetFixedFreqClkFreq(void) -{ - uint32_t freq = CLOCK_GetFllRefClkFreq(); - - /* MCGFFCLK must be no more than MCGOUTCLK/8. */ - if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) - { - return freq; - } - else - { - return 0U; - } -} - -/*! - * brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency. - * - * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG - * register value. - * - * return The frequency of MCGPLL0CLK. - */ -uint32_t CLOCK_GetPll0Freq(void) -{ - uint32_t mcgpll0clk; - - /* If PLL0 is not enabled, return 0. */ - if (!(MCG->S & MCG_S_LOCK0_MASK)) - { - return 0U; - } - - mcgpll0clk = CLOCK_GetPll0RefFreq(); - - /* - * Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. - * Please call CLOCK_SetXtal1Freq base on board setting before using OSC1 clock. - */ - assert(mcgpll0clk); - - mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL); - mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); - - return mcgpll0clk; -} - -/*! - * brief Selects the MCG external reference clock. - * - * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL], - * and waits for the clock source to be stable. Because the external reference - * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes. - * - * param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. - * retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source, - * the configuration should not be changed. Otherwise, a glitch occurs. - * retval kStatus_Success External reference clock set successfully. - */ -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) -{ - bool needDelay; - uint32_t i; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */ - if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) - { - return kStatus_MCG_SourceUsed; - } -#endif /* MCG_CONFIG_CHECK_PARAM */ - - if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) - { - /* If change OSCSEL, need to delay, ERR009878. */ - needDelay = true; - } - else - { - needDelay = false; - } - - MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel); - if (needDelay) - { - /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */ - i = 1500U; - while (0U != (i--)) - { - __NOP(); - } - } - - return kStatus_Success; -} - -/*! - * brief Configures the Internal Reference clock (MCGIRCLK). - * - * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC - * source. If the fast IRC is used, this function sets the fast IRC divider. - * This function also sets whether the \c MCGIRCLK is enabled in stop mode. - * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result, - * using the function in these modes it is not allowed. - * - * param enableMode MCGIRCLK enable mode, OR'ed value of ref _mcg_irclk_enable_mode. - * param ircs MCGIRCLK clock source, choose fast or slow. - * param fcrdiv Fast IRC divider setting (\c FCRDIV). - * retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source, - * the configuration should not be changed. Otherwise, a glitch occurs. - * retval kStatus_Success MCGIRCLK configuration finished successfully. - */ -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) -{ - uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL; - mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)MCG_S_IRCST_VAL; - uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - /* If MCGIRCLK is used as system clock source. */ - if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) - { - /* If need to change MCGIRCLK source or driver, return error. */ - if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) - { - return kStatus_MCG_SourceUsed; - } - } -#endif - - /* If need to update the FCRDIV. */ - if (fcrdiv != curFcrdiv) - { - /* If fast IRC is in use currently, change to slow IRC. */ - if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) && - (kMCG_IrcFast == curIrcs)) - { - MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); - while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) - { - } - } - /* Update FCRDIV. */ - MCG->SC = - (uint8_t)(MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv); - } - - /* Set internal reference clock selection. */ - MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode); - - /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */ - if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) - { - while (MCG_S_IRCST_VAL != (uint8_t)ircs) - { - } - } - - return kStatus_Success; -} - -/*! - * brief Calculates the PLL divider setting for a desired output frequency. - * - * This function calculates the correct reference clock divider (\c PRDIV) and - * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the - * closest frequency match with the corresponding \c PRDIV/VDIV - * returned from parameters. If a desired frequency is not valid, this function - * returns 0. - * - * param refFreq PLL reference clock frequency. - * param desireFreq Desired PLL output frequency. - * param prdiv PRDIV value to generate desired PLL frequency. - * param vdiv VDIV value to generate desired PLL frequency. - * return Closest frequency match that the PLL was able generate. - */ -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv) -{ - uint8_t ret_prdiv; /* PRDIV to return. */ - uint8_t ret_vdiv; /* VDIV to return. */ - uint8_t prdiv_min; /* Min PRDIV value to make reference clock in allowed range. */ - uint8_t prdiv_max; /* Max PRDIV value to make reference clock in allowed range. */ - uint8_t prdiv_cur; /* PRDIV value for iteration. */ - uint8_t vdiv_cur; /* VDIV value for iteration. */ - uint32_t ret_freq = 0U; /* PLL output frequency to return. */ - uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */ - uint32_t ref_div; /* Reference frequency after PRDIV. */ - - /* - Steps: - 1. Get allowed prdiv with such rules: - 1). refFreq / prdiv >= FSL_FEATURE_MCG_PLL_REF_MIN. - 2). refFreq / prdiv <= FSL_FEATURE_MCG_PLL_REF_MAX. - 2. For each allowed prdiv, there are two candidate vdiv values: - 1). (desireFreq / (refFreq / prdiv)). - 2). (desireFreq / (refFreq / prdiv)) + 1. - If could get the precise desired frequency, return current prdiv and - vdiv directly. Otherwise choose the one which is closer to desired - frequency. - */ - - /* Reference frequency is out of range. */ - if ((refFreq < FSL_FEATURE_MCG_PLL_REF_MIN) || - (refFreq > (FSL_FEATURE_MCG_PLL_REF_MAX * (FSL_FEATURE_MCG_PLL_PRDIV_MAX + FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) - { - return 0U; - } - - /* refFreq/PRDIV must in a range. First get the allowed PRDIV range. */ - prdiv_max = refFreq / FSL_FEATURE_MCG_PLL_REF_MIN; - prdiv_min = (refFreq + FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / FSL_FEATURE_MCG_PLL_REF_MAX; - - /* PRDIV traversal. */ - for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) - { - /* Reference frequency after PRDIV. */ - ref_div = refFreq / prdiv_cur; - - vdiv_cur = desireFreq / ref_div; - - if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) || (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) - { - /* No VDIV is available with this PRDIV. */ - continue; - } - - ret_freq = vdiv_cur * ref_div; - - if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE) - { - if (ret_freq == desireFreq) /* If desire frequency is got. */ - { - *prdiv = prdiv_cur - FSL_FEATURE_MCG_PLL_PRDIV_BASE; - *vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE; - return ret_freq; - } - /* New PRDIV/VDIV is closer. */ - if (diff > desireFreq - ret_freq) - { - diff = desireFreq - ret_freq; - ret_prdiv = prdiv_cur; - ret_vdiv = vdiv_cur; - } - } - vdiv_cur++; - if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) - { - ret_freq += ref_div; - /* New PRDIV/VDIV is closer. */ - if (diff > ret_freq - desireFreq) - { - diff = ret_freq - desireFreq; - ret_prdiv = prdiv_cur; - ret_vdiv = vdiv_cur; - } - } - } - - if (0xFFFFFFFFU != diff) - { - /* PRDIV/VDIV found. */ - *prdiv = ret_prdiv - FSL_FEATURE_MCG_PLL_PRDIV_BASE; - *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE; - ret_freq = (refFreq / ret_prdiv) * ret_vdiv; - return ret_freq; - } - else - { - /* No proper PRDIV/VDIV found. */ - return 0U; - } -} - -/*! - * brief Enables the PLL0 in FLL mode. - * - * This function sets us the PLL0 in FLL mode and reconfigures - * the PLL0. Ensure that the PLL reference - * clock is enabled before calling this function and that the PLL0 is not used as a clock source. - * The function CLOCK_CalcPllDiv gets the correct PLL - * divider values. - * - * param config Pointer to the configuration structure. - */ -void CLOCK_EnablePll0(mcg_pll_config_t const *config) -{ - assert(config); - - uint8_t mcg_c5 = 0U; - - mcg_c5 |= MCG_C5_PRDIV0(config->prdiv); - MCG->C5 = mcg_c5; /* Disable the PLL first. */ - - MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); - - /* Set enable mode. */ - MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); - - /* Wait for PLL lock. */ - while (!(MCG->S & MCG_S_LOCK0_MASK)) - { - } -} - -/*! - * brief Sets the OSC0 clock monitor mode. - * - * This function sets the OSC0 clock monitor mode. See ref mcg_monitor_mode_t for details. - * - * param mode Monitor mode to set. - */ -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) -{ - /* Clear the previous flag, MCG_SC[LOCS0]. */ - MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK; - - if (kMCG_MonitorNone == mode) - { - MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK; - } - else - { - if (kMCG_MonitorInt == mode) - { - MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; - } - else - { - MCG->C2 |= MCG_C2_LOCRE0_MASK; - } - MCG->C6 |= MCG_C6_CME0_MASK; - } -} - -/*! - * brief Sets the RTC OSC clock monitor mode. - * - * This function sets the RTC OSC clock monitor mode. See ref mcg_monitor_mode_t for details. - * - * param mode Monitor mode to set. - */ -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) -{ - uint8_t mcg_c8 = MCG->C8; - - mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK); - - if (kMCG_MonitorNone != mode) - { - if (kMCG_MonitorReset == mode) - { - mcg_c8 |= MCG_C8_LOCRE1_MASK; - } - mcg_c8 |= MCG_C8_CME1_MASK; - } - MCG->C8 = mcg_c8; -} - -/*! - * brief Sets the PLL0 clock monitor mode. - * - * This function sets the PLL0 clock monitor mode. See ref mcg_monitor_mode_t for details. - * - * param mode Monitor mode to set. - */ -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) -{ - uint8_t mcg_c8; - - /* Clear previous flag. */ - MCG->S = MCG_S_LOLS0_MASK; - - if (kMCG_MonitorNone == mode) - { - MCG->C6 &= ~MCG_C6_LOLIE0_MASK; - } - else - { - mcg_c8 = MCG->C8; - - mcg_c8 &= ~MCG_C8_LOCS1_MASK; - - if (kMCG_MonitorInt == mode) - { - mcg_c8 &= ~MCG_C8_LOLRE_MASK; - } - else - { - mcg_c8 |= MCG_C8_LOLRE_MASK; - } - MCG->C8 = mcg_c8; - MCG->C6 |= MCG_C6_LOLIE0_MASK; - } -} - -/*! - * brief Gets the MCG status flags. - * - * This function gets the MCG clock status flags. All status flags are - * returned as a logical OR of the enumeration ref _mcg_status_flags_t. To - * check a specific flag, compare the return value with the flag. - * - * Example: - * code - * To check the clock lost lock status of OSC0 and PLL0. - * uint32_t mcgFlags; - * - * mcgFlags = CLOCK_GetStatusFlags(); - * - * if (mcgFlags & kMCG_Osc0LostFlag) - * { - * OSC0 clock lock lost. Do something. - * } - * if (mcgFlags & kMCG_Pll0LostFlag) - * { - * PLL0 clock lock lost. Do something. - * } - * endcode - * - * return Logical OR value of the ref _mcg_status_flags_t. - */ -uint32_t CLOCK_GetStatusFlags(void) -{ - uint32_t ret = 0U; - uint8_t mcg_s = MCG->S; - - if (MCG->SC & MCG_SC_LOCS0_MASK) - { - ret |= (uint32_t)kMCG_Osc0LostFlag; - } - if (mcg_s & MCG_S_OSCINIT0_MASK) - { - ret |= (uint32_t)kMCG_Osc0InitFlag; - } - if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) - { - ret |= (uint32_t)kMCG_RtcOscLostFlag; - } - if (mcg_s & MCG_S_LOLS0_MASK) - { - ret |= (uint32_t)kMCG_Pll0LostFlag; - } - if (mcg_s & MCG_S_LOCK0_MASK) - { - ret |= (uint32_t)kMCG_Pll0LockFlag; - } - return ret; -} - -/*! - * brief Clears the MCG status flags. - * - * This function clears the MCG clock lock lost status. The parameter is a logical - * OR value of the flags to clear. See ref _mcg_status_flags_t. - * - * Example: - * code - * To clear the clock lost lock status flags of OSC0 and PLL0. - * - * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag); - * endcode - * - * param mask The status flags to clear. This is a logical OR of members of the - * enumeration ref _mcg_status_flags_t. - */ -void CLOCK_ClearStatusFlags(uint32_t mask) -{ - uint8_t reg; - - if (mask & kMCG_Osc0LostFlag) - { - MCG->SC &= ~MCG_SC_ATMF_MASK; - } - if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) - { - reg = MCG->C8; - MCG->C8 = reg; - } - if (mask & kMCG_Pll0LostFlag) - { - MCG->S = MCG_S_LOLS0_MASK; - } -} - -/*! - * brief Initializes the OSC0. - * - * This function initializes the OSC0 according to the board configuration. - * - * param config Pointer to the OSC0 configuration structure. - */ -void CLOCK_InitOsc0(osc_config_t const *config) -{ - uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); - - OSC_SetCapLoad(OSC0, config->capLoad); - - MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); - OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); - - if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK)) - { - /* Wait for stable. */ - while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) - { - } - } -} - -/*! - * brief Deinitializes the OSC0. - * - * This function deinitializes the OSC0. - */ -void CLOCK_DeinitOsc0(void) -{ - OSC0->CR = 0U; - MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; -} - -/*! - * brief Auto trims the internal reference clock. - * - * This function trims the internal reference clock by using the external clock. If - * successful, it returns the kStatus_Success and the frequency after - * trimming is received in the parameter p actualFreq. If an error occurs, - * the error code is returned. - * - * param extFreq External clock frequency, which should be a bus clock. - * param desireFreq Frequency to trim to. - * param actualFreq Actual frequency after trimming. - * param atms Trim fast or slow internal reference clock. - * retval kStatus_Success ATM success. - * retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM. - * retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency. - * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source. - * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming. - */ -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) -{ - uint32_t multi; /* extFreq / desireFreq */ - uint32_t actv; /* Auto trim value. */ - uint8_t mcg_sc; - - static const uint32_t trimRange[2][2] = { - /* Min Max */ - {TRIM_SIRC_MIN, TRIM_SIRC_MAX}, /* Slow IRC. */ - {TRIM_FIRC_MIN, TRIM_FIRC_MAX} /* Fast IRC. */ - }; - - if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) - { - return kStatus_MCG_AtmBusClockInvalid; - } - - /* Check desired frequency range. */ - if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) - { - return kStatus_MCG_AtmDesiredFreqInvalid; - } - - /* - Make sure internal reference clock is not used to generate bus clock. - Here only need to check (MCG_S_IREFST == 1). - */ - if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) - { - return kStatus_MCG_AtmIrcUsed; - } - - multi = extFreq / desireFreq; - actv = multi * 21U; - - if (kMCG_AtmSel4m == atms) - { - actv *= 128U; - } - - /* Now begin to start trim. */ - MCG->ATCVL = (uint8_t)actv; - MCG->ATCVH = (uint8_t)(actv >> 8U); - - mcg_sc = MCG->SC; - mcg_sc &= ~(uint8_t)(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK); - mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms)); - MCG->SC = (mcg_sc | MCG_SC_ATME_MASK); - - /* Wait for finished. */ - while (0U != (MCG->SC & MCG_SC_ATME_MASK)) - { - } - - /* Error occurs? */ - if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) - { - /* Clear the failed flag. */ - MCG->SC = mcg_sc; - return kStatus_MCG_AtmHardwareFail; - } - - *actualFreq = extFreq / multi; - - if (kMCG_AtmSel4m == atms) - { - s_fastIrcFreq = *actualFreq; - } - else - { - s_slowIrcFreq = *actualFreq; - } - - return kStatus_Success; -} - -/*! - * brief Gets the current MCG mode. - * - * This function checks the MCG registers and determines the current MCG mode. - * - * return Current MCG mode or error code; See ref mcg_mode_t. - */ -mcg_mode_t CLOCK_GetMode(void) -{ - mcg_mode_t mode = kMCG_ModeError; - uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL; - uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL; - uint32_t lp = (uint32_t)MCG_C2_LP_VAL; - uint32_t pllst = MCG_S_PLLST_VAL; - - /*------------------------------------------------------------------ - Mode and Registers - ____________________________________________________________________ - - Mode | CLKST | IREFST | PLLST | LP - ____________________________________________________________________ - - FEI | 00(FLL) | 1(INT) | 0(FLL) | X - ____________________________________________________________________ - - FEE | 00(FLL) | 0(EXT) | 0(FLL) | X - ____________________________________________________________________ - - FBE | 10(EXT) | 0(EXT) | 0(FLL) | 0(NORMAL) - ____________________________________________________________________ - - FBI | 01(INT) | 1(INT) | 0(FLL) | 0(NORMAL) - ____________________________________________________________________ - - BLPI | 01(INT) | 1(INT) | 0(FLL) | 1(LOW POWER) - ____________________________________________________________________ - - BLPE | 10(EXT) | 0(EXT) | X | 1(LOW POWER) - ____________________________________________________________________ - - PEE | 11(PLL) | 0(EXT) | 1(PLL) | X - ____________________________________________________________________ - - PBE | 10(EXT) | 0(EXT) | 1(PLL) | O(NORMAL) - ____________________________________________________________________ - - PBI | 01(INT) | 1(INT) | 1(PLL) | 0(NORMAL) - ____________________________________________________________________ - - PEI | 11(PLL) | 1(INT) | 1(PLL) | X - ____________________________________________________________________ - - ----------------------------------------------------------------------*/ - - if (clkst == (uint32_t)kMCG_ClkOutStatFll) - { - if ((uint32_t)kMCG_FllSrcExternal == irefst) - { - mode = kMCG_ModeFEE; - } - else - { - mode = kMCG_ModeFEI; - } - } - else if (clkst == (uint32_t)kMCG_ClkOutStatInt) - { - if (0U != lp) - { - mode = kMCG_ModeBLPI; - } - else - { - { - mode = kMCG_ModeFBI; - } - } - } - else if (clkst == (uint32_t)kMCG_ClkOutStatExt) - { - if (0U != lp) - { - mode = kMCG_ModeBLPE; - } - else - { - if (kMCG_PllstPll == pllst) - { - mode = kMCG_ModePBE; - } - else - { - mode = kMCG_ModeFBE; - } - } - } - if (clkst == (uint32_t)kMCG_ClkOutStatPll) - { - { - mode = kMCG_ModePEE; - } - } - else - { - /*do nothing*/ - } - - return mode; -} - -/*! - * brief Sets the MCG to FEI mode. - * - * This function sets the MCG to FEI mode. If setting to FEI mode fails - * from the current mode, this function returns an error. - * - * param dmx32 DMX32 in FEI mode. - * param drs The DCO range selection. - * param fllStableDelay Delay function to ensure that the FLL is stable. Passing - * NULL does not cause a delay. - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed - * to a frequency above 32768 Hz. - */ -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - uint8_t mcg_c4; - bool change_drs = false; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - mcg_mode_t mode = CLOCK_GetMode(); - if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) - { - return kStatus_MCG_ModeUnreachable; - } -#endif - mcg_c4 = MCG->C4; - - /* - Errata: ERR007993 - Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before - reference clock source changes, then reset to previous value after - reference clock changes. - */ - if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { - change_drs = true; - /* Change the LSB of DRST_DRS. */ - MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); - } - - /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | - (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ - | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ - - /* Wait and check status. */ - while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) - { - } - - /* Errata: ERR007993 */ - if (change_drs) - { - MCG->C4 = mcg_c4; - } - - /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */ - MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); - - /* Check MCG_S[CLKST] */ - while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) - { - } - - /* Wait for FLL stable time. */ - if (NULL != fllStableDelay) - { - fllStableDelay(); - } - - return kStatus_Success; -} - -/*! - * brief Sets the MCG to FEE mode. - * - * This function sets the MCG to FEE mode. If setting to FEE mode fails - * from the current mode, this function returns an error. - * - * param frdiv FLL reference clock divider setting, FRDIV. - * param dmx32 DMX32 in FEE mode. - * param drs The DCO range selection. - * param fllStableDelay Delay function to make sure FLL is stable. Passing - * NULL does not cause a delay. - * - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - uint8_t mcg_c4; - bool change_drs = false; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - mcg_mode_t mode = CLOCK_GetMode(); - if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) - { - return kStatus_MCG_ModeUnreachable; - } -#endif - mcg_c4 = MCG->C4; - - /* - Errata: ERR007993 - Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before - reference clock source changes, then reset to previous value after - reference clock changes. - */ - if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) - { - change_drs = true; - /* Change the LSB of DRST_DRS. */ - MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); - } - - /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ - | MCG_C1_FRDIV(frdiv) /* FRDIV */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ - - /* If use external crystal as clock source, wait for it stable. */ - if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) - { - if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) - { - while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) - { - } - } - } - - /* Wait and check status. */ - while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) - { - } - - /* Errata: ERR007993 */ - if (change_drs) - { - MCG->C4 = mcg_c4; - } - - /* Set DRS and DMX32. */ - mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); - MCG->C4 = mcg_c4; - - /* Wait for DRST_DRS update. */ - while (MCG->C4 != mcg_c4) - { - } - - /* Check MCG_S[CLKST] */ - while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) - { - } - - /* Wait for FLL stable time. */ - if (NULL != fllStableDelay) - { - fllStableDelay(); - } - - return kStatus_Success; -} - -/*! - * brief Sets the MCG to FBI mode. - * - * This function sets the MCG to FBI mode. If setting to FBI mode fails - * from the current mode, this function returns an error. - * - * param dmx32 DMX32 in FBI mode. - * param drs The DCO range selection. - * param fllStableDelay Delay function to make sure FLL is stable. If the FLL - * is not used in FBI mode, this parameter can be NULL. Passing - * NULL does not cause a delay. - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed - * to frequency above 32768 Hz. - */ -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - uint8_t mcg_c4; - bool change_drs = false; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - mcg_mode_t mode = CLOCK_GetMode(); - - if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || - (kMCG_ModeBLPI == mode))) - - { - return kStatus_MCG_ModeUnreachable; - } -#endif - - mcg_c4 = MCG->C4; - - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */ - - /* - Errata: ERR007993 - Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before - reference clock source changes, then reset to previous value after - reference clock changes. - */ - if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { - change_drs = true; - /* Change the LSB of DRST_DRS. */ - MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); - } - - /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ - | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ - - /* Wait and check status. */ - while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) - { - } - - /* Errata: ERR007993 */ - if (change_drs) - { - MCG->C4 = mcg_c4; - } - - while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) - { - } - - MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); - - /* Wait for FLL stable time. */ - if (NULL != fllStableDelay) - { - fllStableDelay(); - } - - return kStatus_Success; -} - -/*! - * brief Sets the MCG to FBE mode. - * - * This function sets the MCG to FBE mode. If setting to FBE mode fails - * from the current mode, this function returns an error. - * - * param frdiv FLL reference clock divider setting, FRDIV. - * param dmx32 DMX32 in FBE mode. - * param drs The DCO range selection. - * param fllStableDelay Delay function to make sure FLL is stable. If the FLL - * is not used in FBE mode, this parameter can be NULL. Passing NULL - * does not cause a delay. - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - uint8_t mcg_c4; - bool change_drs = false; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - mcg_mode_t mode = CLOCK_GetMode(); - if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || - (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) - { - return kStatus_MCG_ModeUnreachable; - } -#endif - - /* Change to FLL mode. */ - MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK; - while (MCG->S & MCG_S_PLLST_MASK) - { - } - - /* Set LP bit to enable the FLL */ - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; - - mcg_c4 = MCG->C4; - - /* - Errata: ERR007993 - Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before - reference clock source changes, then reset to previous value after - reference clock changes. - */ - if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) - { - change_drs = true; - /* Change the LSB of DRST_DRS. */ - MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); - } - - /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ - | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ - - /* If use external crystal as clock source, wait for it stable. */ - if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) - { - if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) - { - while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) - { - } - } - } - - /* Wait for Reference clock Status bit to clear */ - while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) - { - } - - /* Errata: ERR007993 */ - if (change_drs) - { - MCG->C4 = mcg_c4; - } - - /* Set DRST_DRS and DMX32. */ - mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); - - /* Wait for clock status bits to show clock source is ext ref clk */ - while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) - { - } - - /* Wait for fll stable time. */ - if (NULL != fllStableDelay) - { - fllStableDelay(); - } - - return kStatus_Success; -} - -/*! - * brief Sets the MCG to BLPI mode. - * - * This function sets the MCG to BLPI mode. If setting to BLPI mode fails - * from the current mode, this function returns an error. - * - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetBlpiMode(void) -{ -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) - { - return kStatus_MCG_ModeUnreachable; - } -#endif /* MCG_CONFIG_CHECK_PARAM */ - - /* Set LP. */ - MCG->C2 |= MCG_C2_LP_MASK; - - return kStatus_Success; -} - -/*! - * brief Sets the MCG to BLPE mode. - * - * This function sets the MCG to BLPE mode. If setting to BLPE mode fails - * from the current mode, this function returns an error. - * - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetBlpeMode(void) -{ -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) - { - return kStatus_MCG_ModeUnreachable; - } -#endif - - /* Set LP bit to enter BLPE mode. */ - MCG->C2 |= MCG_C2_LP_MASK; - - return kStatus_Success; -} - -/*! - * brief Sets the MCG to PBE mode. - * - * This function sets the MCG to PBE mode. If setting to PBE mode fails - * from the current mode, this function returns an error. - * - * param pllcs The PLL selection, PLLCS. - * param config Pointer to the PLL configuration. - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - * - * note - * 1. The parameter \c pllcs selects the PLL. For platforms with - * only one PLL, the parameter pllcs is kept for interface compatibility. - * 2. The parameter \c config is the PLL configuration structure. On some - * platforms, it is possible to choose the external PLL directly, which renders the - * configuration structure not necessary. In this case, pass in NULL. - * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); - */ -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) -{ - assert(config); - - /* - This function is designed to change MCG to PBE mode from PEE/BLPE/FBE, - but with this workflow, the source mode could be all modes except PEI/PBI. - */ - MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ - - /* Change to use external clock first. */ - MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); - - /* Wait for CLKST clock status bits to show clock source is ext ref clk */ - while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != - (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) - { - } - - /* Disable PLL first, then configure PLL. */ - MCG->C6 &= ~MCG_C6_PLLS_MASK; - while (MCG->S & MCG_S_PLLST_MASK) - { - } - - /* Configure the PLL. */ - { - CLOCK_EnablePll0(config); - } - - /* Change to PLL mode. */ - MCG->C6 |= MCG_C6_PLLS_MASK; - - /* Wait for PLL mode changed. */ - while (!(MCG->S & MCG_S_PLLST_MASK)) - { - } - - return kStatus_Success; -} - -/*! - * brief Sets the MCG to PEE mode. - * - * This function sets the MCG to PEE mode. - * - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - * - * note This function only changes the CLKS to use the PLL/FLL output. If the - * PRDIV/VDIV are different than in the PBE mode, set them up - * in PBE mode and wait. When the clock is stable, switch to PEE mode. - */ -status_t CLOCK_SetPeeMode(void) -{ -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - mcg_mode_t mode = CLOCK_GetMode(); - if (kMCG_ModePBE != mode) - { - return kStatus_MCG_ModeUnreachable; - } -#endif - - /* Change to use PLL/FLL output clock first. */ - MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); - - /* Wait for clock status bits to update */ - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) - { - } - - return kStatus_Success; -} - -/*! - * brief Switches the MCG to FBE mode from the external mode. - * - * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly. - * The external clock is used as the system clock source and PLL is disabled. However, - * the FLL settings are not configured. This is a lite function with a small code size, which is useful - * during the mode switch. For example, to switch from PEE mode to FEI mode: - * - * code - * CLOCK_ExternalModeToFbeModeQuick(); - * CLOCK_SetFeiMode(...); - * endcode - * - * retval kStatus_Success Switched successfully. - * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function. - */ -status_t CLOCK_ExternalModeToFbeModeQuick(void) -{ -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if (MCG->S & MCG_S_IREFST_MASK) - { - return kStatus_MCG_ModeInvalid; - } -#endif /* MCG_CONFIG_CHECK_PARAM */ - - /* Disable low power */ - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; - - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) - { - } - - /* Disable PLL. */ - MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK; - while (MCG->S & MCG_S_PLLST_MASK) - { - } - - return kStatus_Success; -} - -/*! - * brief Switches the MCG to FBI mode from internal modes. - * - * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly. - * The MCGIRCLK is used as the system clock source and PLL is disabled. However, - * FLL settings are not configured. This is a lite function with a small code size, which is useful - * during the mode switch. For example, to switch from PEI mode to FEE mode: - * - * code - * CLOCK_InternalModeToFbiModeQuick(); - * CLOCK_SetFeeMode(...); - * endcode - * - * retval kStatus_Success Switched successfully. - * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function. - */ -status_t CLOCK_InternalModeToFbiModeQuick(void) -{ -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if (!(MCG->S & MCG_S_IREFST_MASK)) - { - return kStatus_MCG_ModeInvalid; - } -#endif - - /* Disable low power */ - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; - - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) - { - } - - return kStatus_Success; -} - -/*! - * brief Sets the MCG to FEI mode during system boot up. - * - * This function sets the MCG to FEI mode from the reset mode. It can also be used to - * set up MCG during system boot up. - * - * param dmx32 DMX32 in FEI mode. - * param drs The DCO range selection. - * param fllStableDelay Delay function to ensure that the FLL is stable. - * - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed - * to frequency above 32768 Hz. - */ -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay); -} - -/*! - * brief Sets the MCG to FEE mode during system bootup. - * - * This function sets MCG to FEE mode from the reset mode. It can also be used to - * set up the MCG during system boot up. - * - * param oscsel OSC clock select, OSCSEL. - * param frdiv FLL reference clock divider setting, FRDIV. - * param dmx32 DMX32 in FEE mode. - * param drs The DCO range selection. - * param fllStableDelay Delay function to ensure that the FLL is stable. - * - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToFeeMode( - mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - (void)CLOCK_SetExternalRefClkConfig(oscsel); - - return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay); -} - -/*! - * brief Sets the MCG to BLPI mode during system boot up. - * - * This function sets the MCG to BLPI mode from the reset mode. It can also be used to - * set up the MCG during system boot up. - * - * param fcrdiv Fast IRC divider, FCRDIV. - * param ircs The internal reference clock to select, IRCS. - * param ircEnableMode The MCGIRCLK enable mode, OR'ed value of ref _mcg_irclk_enable_mode. - * - * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. - * retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) -{ - /* If reset mode is FEI mode, set MCGIRCLK and always success. */ - (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv); - - /* If reset mode is not BLPI, first enter FBI mode. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) - { - } - - /* Enter BLPI mode. */ - MCG->C2 |= MCG_C2_LP_MASK; - - return kStatus_Success; -} - -/*! - * brief Sets the MCG to BLPE mode during system boot up. - * - * This function sets the MCG to BLPE mode from the reset mode. It can also be used to - * set up the MCG during system boot up. - * - * param oscsel OSC clock select, MCG_C7[OSCSEL]. - * - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) -{ - (void)CLOCK_SetExternalRefClkConfig(oscsel); - - /* Set to FBE mode. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ - - /* If use external crystal as clock source, wait for it stable. */ - if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) - { - if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) - { - while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) - { - } - } - } - - /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */ - while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != - (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) - { - } - - /* In FBE now, start to enter BLPE. */ - MCG->C2 |= MCG_C2_LP_MASK; - - return kStatus_Success; -} - -/*! - * brief Sets the MCG to PEE mode during system boot up. - * - * This function sets the MCG to PEE mode from reset mode. It can also be used to - * set up the MCG during system boot up. - * - * param oscsel OSC clock select, MCG_C7[OSCSEL]. - * param pllcs The PLL selection, PLLCS. - * param config Pointer to the PLL configuration. - * - * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) -{ - assert(config); - - CLOCK_SetExternalRefClkConfig(oscsel); - - CLOCK_SetPbeMode(pllcs, config); - - /* Change to use PLL output clock. */ - MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) - { - } - - return kStatus_Success; -} - -/* - The transaction matrix. It defines the path for mode switch, the row is for - current mode and the column is target mode. - For example, switch from FEI to PEE: - 1. Current mode FEI, next mode is mcgModeMatrix[FEI][PEE] = FBE, so swith to FBE. - 2. Current mode FBE, next mode is mcgModeMatrix[FBE][PEE] = PBE, so swith to PBE. - 3. Current mode PBE, next mode is mcgModeMatrix[PBE][PEE] = PEE, so swith to PEE. - Thus the MCG mode has changed from FEI to PEE. - */ -static const mcg_mode_t mcgModeMatrix[8][8] = { - {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, - kMCG_ModeFBE}, /* FEI */ - {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, - kMCG_ModeFBE}, /* FBI */ - {kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, - kMCG_ModeFBI}, /* BLPI */ - {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, - kMCG_ModeFBE}, /* FEE */ - {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, - kMCG_ModePBE}, /* FBE */ - {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, - kMCG_ModePBE}, /* BLPE */ - {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, - kMCG_ModePEE}, /* PBE */ - {kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, - kMCG_ModePBE} /* PEE */ - /* FEI FBI BLPI FEE FBE BLPE PBE PEE */ -}; - -/*! - * brief Sets the MCG to a target mode. - * - * This function sets MCG to a target mode defined by the configuration - * structure. If switching to the target mode fails, this function - * chooses the correct path. - * - * param config Pointer to the target MCG mode configuration structure. - * return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status. - * - * note If the external clock is used in the target mode, ensure that it is - * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this - * function. - */ -status_t CLOCK_SetMcgConfig(const mcg_config_t *config) -{ - mcg_mode_t next_mode; - status_t status = kStatus_Success; - - mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0; - - /* If need to change external clock, MCG_C7[OSCSEL]. */ - if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) - { - /* If external clock is in use, change to FEI first. */ - if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { - (void)CLOCK_ExternalModeToFbeModeQuick(); - (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL); - } - - (void)CLOCK_SetExternalRefClkConfig(config->oscsel); - } - - /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */ - if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) - { - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */ - - { - (void)CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay); - } - } - - /* Configure MCGIRCLK. */ - (void)CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv); - - next_mode = CLOCK_GetMode(); - - do - { - next_mode = mcgModeMatrix[next_mode][config->mcgMode]; - - switch (next_mode) - { - case kMCG_ModeFEI: - status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay); - break; - case kMCG_ModeFEE: - status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay); - break; - case kMCG_ModeFBI: - status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL); - break; - case kMCG_ModeFBE: - status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL); - break; - case kMCG_ModeBLPI: - status = CLOCK_SetBlpiMode(); - break; - case kMCG_ModeBLPE: - status = CLOCK_SetBlpeMode(); - break; - case kMCG_ModePBE: - /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */ - if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) - { - { - status = CLOCK_SetPbeMode(pllcs, &config->pll0Config); - } - } - else - { - MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) - { - } - } - break; - case kMCG_ModePEE: - status = CLOCK_SetPeeMode(); - break; - default: - break; - } - if (kStatus_Success != status) - { - return status; - } - } while (next_mode != config->mcgMode); - - if (config->pll0Config.enableMode & kMCG_PllEnableIndependent) - { - CLOCK_EnablePll0(&config->pll0Config); - } - else - { - MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; - } - return kStatus_Success; -} - -/*! - * brief Use DWT to delay at least for some time. - * Please note that, this API will calculate the microsecond period with the maximum devices - * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise - * delay count was needed, please implement a new timer count to achieve this function. - * - * param delay_us Delay time in unit of microsecond. - */ -__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us) -{ - assert(0U != delay_us); - uint64_t count = 0U; - uint32_t period = SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 1000000; - - /* Make sure the DWT trace fucntion is enabled. */ - if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) - { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } - - /* CYCCNT not supported on this device. */ - assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); - - /* If CYCCENT has already been enabled, read directly, otherwise, need enable it. */ - if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) - { - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; - } - - /* Calculate the count ticks. */ - count = DWT->CYCCNT; - count += (uint64_t)period * delay_us; - - if (count > 0xFFFFFFFFUL) - { - count -= 0xFFFFFFFFUL; - /* wait for cyccnt overflow. */ - while (count < DWT->CYCCNT) - { - } - } - - /* Wait for cyccnt reach count value. */ - while (count > DWT->CYCCNT) - { - } -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_clock.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_clock.h deleted file mode 100644 index f1c9387..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_clock.h +++ /dev/null @@ -1,1454 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 - 2019, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_common.h" - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Configurations - ******************************************************************************/ - -/*! @brief Configures whether to check a parameter in a function. - * - * Some MCG settings must be changed with conditions, for example: - * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when - * MCGIRCLK is used as a system clock source. - * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used - * as a system clock source. For example, in FBE/BLPE/PBE modes. - * 3. The users should only switch between the supported clock modes. - * - * MCG functions check the parameter and MCG status before setting, if not allowed - * to change, the functions return error. The parameter checking increases code size, - * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to - * disable parameter checking. - */ -#ifndef MCG_CONFIG_CHECK_PARAM -#define MCG_CONFIG_CHECK_PARAM 0U -#endif - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could control the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.3.0. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/* Definition for delay API in clock driver, users can redefine it to the real application. */ -#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY -#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL) -#endif - -/*! @brief External XTAL0 (OSC0) clock frequency. - * - * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the - * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, - * if XTAL0 is 8 MHz: - * @code - * Set up the OSC0 - * CLOCK_InitOsc0(...); - * Set the XTAL0 value to the clock driver. - * CLOCK_SetXtal0Freq(80000000); - * @endcode - * - * This is important for the multicore platforms where only one core needs to set up the - * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq - * to get a valid clock frequency. - */ -extern volatile uint32_t g_xtal0Freq; - -/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. - * - * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the - * function CLOCK_SetXtal32Freq to set the value in the clock driver. - * - * This is important for the multicore platforms where only one core needs to set up - * the clock. All other cores need to call the CLOCK_SetXtal32Freq - * to get a valid clock frequency. - */ -extern volatile uint32_t g_xtal32Freq; - -#if (defined(OSC) && !(defined(OSC0))) -#define OSC0 OSC -#endif - -/*! @brief Clock ip name array for DMAMUX. */ -#define DMAMUX_CLOCKS \ - { \ - kCLOCK_Dmamux0 \ - } - -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc0 \ - } - -/*! @brief Clock ip name array for SAI. */ -#define SAI_CLOCKS \ - { \ - kCLOCK_Sai0 \ - } - -/*! @brief Clock ip name array for PORT. */ -#define PORT_CLOCKS \ - { \ - kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \ - } - -/*! @brief Clock ip name array for EWM. */ -#define EWM_CLOCKS \ - { \ - kCLOCK_Ewm0 \ - } - -/*! @brief Clock ip name array for PIT. */ -#define PIT_CLOCKS \ - { \ - kCLOCK_Pit0 \ - } - -/*! @brief Clock ip name array for DSPI. */ -#define DSPI_CLOCKS \ - { \ - kCLOCK_Spi0, kCLOCK_Spi1 \ - } - -/*! @brief Clock ip name array for LPTMR. */ -#define LPTMR_CLOCKS \ - { \ - kCLOCK_Lptmr0 \ - } - -/*! @brief Clock ip name array for FTM. */ -#define FTM_CLOCKS \ - { \ - kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2 \ - } - -/*! @brief Clock ip name array for EDMA. */ -#define EDMA_CLOCKS \ - { \ - kCLOCK_Dma0 \ - } - -/*! @brief Clock ip name array for ADC16. */ -#define ADC16_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } - -/*! @brief Clock ip name array for CMT. */ -#define CMT_CLOCKS \ - { \ - kCLOCK_Cmt0 \ - } - -/*! @brief Clock ip name array for UART. */ -#define UART_CLOCKS \ - { \ - kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2 \ - } - -/*! @brief Clock ip name array for RNGA. */ -#define RNGA_CLOCKS \ - { \ - kCLOCK_Rnga0 \ - } - -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc0 \ - } - -/*! @brief Clock ip name array for I2C. */ -#define I2C_CLOCKS \ - { \ - kCLOCK_I2c0, kCLOCK_I2c1 \ - } - -/*! @brief Clock ip name array for PDB. */ -#define PDB_CLOCKS \ - { \ - kCLOCK_Pdb0 \ - } - -/*! @brief Clock ip name array for CMP. */ -#define CMP_CLOCKS \ - { \ - kCLOCK_Cmp0, kCLOCK_Cmp1 \ - } - -/*! @brief Clock ip name array for FTF. */ -#define FTF_CLOCKS \ - { \ - kCLOCK_Ftf0 \ - } - -/*! - * @brief LPO clock frequency. - */ -#define LPO_CLK_FREQ 1000U - -/*! @brief Peripherals clock source definition. */ -#define SYS_CLK kCLOCK_CoreSysClk -#define BUS_CLK kCLOCK_BusClk -#define FAST_CLK kCLOCK_FastPeriphClk - -#define I2C0_CLK_SRC BUS_CLK -#define I2C1_CLK_SRC BUS_CLK -#define DSPI0_CLK_SRC BUS_CLK -#define DSPI1_CLK_SRC BUS_CLK -#define UART0_CLK_SRC SYS_CLK -#define UART1_CLK_SRC SYS_CLK -#define UART2_CLK_SRC BUS_CLK - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - - /* ----------------------------- System layer clock -------------------------------*/ - kCLOCK_CoreSysClk, /*!< Core/system clock */ - kCLOCK_PlatClk, /*!< Platform clock */ - kCLOCK_BusClk, /*!< Bus clock */ - kCLOCK_FlashClk, /*!< Flash clock */ - kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */ - - /* ---------------------------------- OSC clock -----------------------------------*/ - kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */ - kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */ - - /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/ - kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */ - kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */ - kCLOCK_McgFllClk, /*!< MCGFLLCLK */ - kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */ - kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */ - kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */ - kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */ - - /* --------------------------------- Other clock ----------------------------------*/ - kCLOCK_LpoClk, /*!< LPO clock */ - -} clock_name_t; - -/*! @brief USB clock source definition. */ -typedef enum _clock_usb_src -{ - kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */ - kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */ -} clock_usb_src_t; -/*------------------------------------------------------------------------------ - - clock_gate_t definition: - - 31 16 0 - ----------------------------------------------------------------- - | SIM_SCGC register offset | control bit offset in SCGC | - ----------------------------------------------------------------- - - For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the - SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as - - kCLOCK_GateSdhc0 = (0x1030 << 16) | 17; - -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 16U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, - - kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U), - kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U), - kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U), - kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U), - kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U), - kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U), - kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U), - kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U), - kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U), - kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U), - kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U), - - kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U), - kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U), - kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U), - kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U), - kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U), - kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U), - - kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U), - kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U), - kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U), - kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U), - kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U), - kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U), - kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U), - kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U), - kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U), - kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U), - kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U), - kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U), - kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U), - kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U), - kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U), - kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U), - - kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U), -} clock_ip_name_t; - -/*!@brief SIM configuration structure for clock setting. */ -typedef struct _sim_clock_config -{ - uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */ - uint8_t er32kSrc; /*!< ERCLK32K source selection. */ - uint32_t clkdiv1; /*!< SIM_CLKDIV1. */ -} sim_clock_config_t; - -/*! @brief OSC work mode. */ -typedef enum _osc_mode -{ - kOSC_ModeExt = 0U, /*!< Use an external clock. */ -#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) - kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */ -#else - kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */ -#endif - kOSC_ModeOscHighGain = 0U -#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) - | MCG_C2_EREFS_MASK -#else - | MCG_C2_EREFS0_MASK -#endif -#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) - | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */ -#else - | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */ -#endif -} osc_mode_t; - -/*! @brief Oscillator capacitor load setting.*/ -enum _osc_cap_load -{ - kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ - kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ - kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ - kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ -}; - -/*! @brief OSCERCLK enable mode. */ -enum _oscer_enable_mode -{ - kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */ - kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */ -}; - -/*! @brief OSC configuration for OSCERCLK. */ -typedef struct _oscer_config -{ - uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */ - -} oscer_config_t; - -/*! - * @brief OSC Initialization Configuration Structure - * - * Defines the configuration data structure to initialize the OSC. - * When porting to a new board, set the following members - * according to the board setting: - * 1. freq: The external frequency. - * 2. workMode: The OSC module mode. - */ -typedef struct _osc_config -{ - uint32_t freq; /*!< External clock frequency. */ - uint8_t capLoad; /*!< Capacitor load setting. */ - osc_mode_t workMode; /*!< OSC work mode setting. */ - oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */ -} osc_config_t; - -/*! @brief MCG FLL reference clock source select. */ -typedef enum _mcg_fll_src -{ - kMCG_FllSrcExternal, /*!< External reference clock is selected */ - kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */ -} mcg_fll_src_t; - -/*! @brief MCG internal reference clock select */ -typedef enum _mcg_irc_mode -{ - kMCG_IrcSlow, /*!< Slow internal reference clock selected */ - kMCG_IrcFast /*!< Fast internal reference clock selected */ -} mcg_irc_mode_t; - -/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */ -typedef enum _mcg_dmx32 -{ - kMCG_Dmx32Default, /*!< DCO has a default range of 25% */ - kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ -} mcg_dmx32_t; - -/*! @brief MCG DCO range select */ -typedef enum _mcg_drs -{ - kMCG_DrsLow, /*!< Low frequency range */ - kMCG_DrsMid, /*!< Mid frequency range */ - kMCG_DrsMidHigh, /*!< Mid-High frequency range */ - kMCG_DrsHigh /*!< High frequency range */ -} mcg_drs_t; - -/*! @brief MCG PLL reference clock select */ -typedef enum _mcg_pll_ref_src -{ - kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */ - kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */ -} mcg_pll_ref_src_t; - -/*! @brief MCGOUT clock source. */ -typedef enum _mcg_clkout_src -{ - kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */ - kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */ - kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */ -} mcg_clkout_src_t; - -/*! @brief MCG Automatic Trim Machine Select */ -typedef enum _mcg_atm_select -{ - kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */ - kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */ -} mcg_atm_select_t; - -/*! @brief MCG OSC Clock Select */ -typedef enum _mcg_oscsel -{ - kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */ - kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */ -} mcg_oscsel_t; - -/*! @brief MCG PLLCS select */ -typedef enum _mcg_pll_clk_select -{ - kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */ - kMCG_PllClkSelPll1 /* PLL1 output clock is selected */ -} mcg_pll_clk_select_t; - -/*! @brief MCG clock monitor mode. */ -typedef enum _mcg_monitor_mode -{ - kMCG_MonitorNone, /*!< Clock monitor is disabled. */ - kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */ - kMCG_MonitorReset /*!< System reset when clock lost. */ -} mcg_monitor_mode_t; - -/*! @brief MCG status. */ -enum _mcg_status -{ - kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */ - kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific - function. */ - kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */ - kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */ - kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */ - kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */ - kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because - it is in use. */ -}; - -/*! @brief MCG status flags. */ -enum _mcg_status_flags_t -{ - kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */ - kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */ - kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */ - kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */ - kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */ -}; - -/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */ -enum _mcg_irclk_enable_mode -{ - kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */ - kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */ -}; - -/*! @brief MCG PLL clock enable mode definition. */ -enum _mcg_pll_enable_mode -{ - kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the - MCG clock mode. Generally, the PLL - is disabled in FLL modes - (FEI/FBI/FEE/FBE). Setting the PLL clock - enable independent, enables the - PLL in the FLL modes. */ - kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */ -}; - -/*! @brief MCG mode definitions */ -typedef enum _mcg_mode -{ - kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */ - kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */ - kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */ - kMCG_ModeFEE, /*!< FEE - FLL Engaged External */ - kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */ - kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */ - kMCG_ModePBE, /*!< PBE - PLL Bypassed External */ - kMCG_ModePEE, /*!< PEE - PLL Engaged External */ - kMCG_ModeError /*!< Unknown mode */ -} mcg_mode_t; - -/*! @brief MCG PLL configuration. */ -typedef struct _mcg_pll_config -{ - uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */ - uint8_t prdiv; /*!< Reference divider PRDIV. */ - uint8_t vdiv; /*!< VCO divider VDIV. */ -} mcg_pll_config_t; - -/*! @brief MCG mode change configuration structure - * - * When porting to a new board, set the following members - * according to the board setting: - * 1. frdiv: If the FLL uses the external reference clock, set this - * value to ensure that the external reference clock divided by frdiv is - * in the 31.25 kHz to 39.0625 kHz range. - * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after - * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to - * FSL_FEATURE_MCG_PLL_REF_MAX range. - */ -typedef struct _mcg_config -{ - mcg_mode_t mcgMode; /*!< MCG mode. */ - - /* ----------------------- MCGIRCCLK settings ------------------------ */ - uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */ - mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */ - uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */ - - /* ------------------------ MCG FLL settings ------------------------- */ - uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */ - mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */ - mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */ - mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */ - - /* ------------------------ MCG PLL settings ------------------------- */ - mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */ - -} mcg_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief Enable the clock for specific IP. - * - * @param name Which clock to enable, see \ref clock_ip_name_t. - */ -static inline void CLOCK_EnableClock(clock_ip_name_t name) -{ - uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); - (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); -} - -/*! - * @brief Disable the clock for specific IP. - * - * @param name Which clock to disable, see \ref clock_ip_name_t. - */ -static inline void CLOCK_DisableClock(clock_ip_name_t name) -{ - uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); - (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); -} - -/*! - * @brief Set ERCLK32K source. - * - * @param src The value to set ERCLK32K clock source. - */ -static inline void CLOCK_SetEr32kClock(uint32_t src) -{ - SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); -} - -/*! - * @brief Set debug trace clock source. - * - * @param src The value to set debug trace clock source. - */ -static inline void CLOCK_SetTraceClock(uint32_t src) -{ - SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src)); -} - -/*! - * @brief Set PLLFLLSEL clock source. - * - * @param src The value to set PLLFLLSEL clock source. - */ -static inline void CLOCK_SetPllFllSelClock(uint32_t src) -{ - SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src)); -} - -/*! - * @brief Set CLKOUT source. - * - * @param src The value to set CLKOUT source. - */ -static inline void CLOCK_SetClkOutClock(uint32_t src) -{ - SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); -} - -/*! - * @brief Set RTC_CLKOUT source. - * - * @param src The value to set RTC_CLKOUT source. - */ -static inline void CLOCK_SetRtcClkOutClock(uint32_t src) -{ - SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src)); -} - -/*! @brief Enable USB FS clock. - * - * @param src USB FS clock source. - * @param freq The frequency specified by src. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB FS clock. - */ -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); - -/*! @brief Disable USB FS clock. - * - * Disable USB FS clock. - */ -static inline void CLOCK_DisableUsbfs0Clock(void) -{ - CLOCK_DisableClock(kCLOCK_Usbfs0); -} - -/*! - * @brief System clock divider - * - * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV4]. - * - * @param outdiv1 Clock 1 output divider value. - * - * @param outdiv2 Clock 2 output divider value. - * - * @param outdiv4 Clock 4 output divider value. - */ -static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv4) -{ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV4(outdiv4); -} - -/*! - * @brief Gets the clock frequency for a specific clock name. - * - * This function checks the current clock configurations and then calculates - * the clock frequency for a specific clock name defined in clock_name_t. - * The MCG must be properly configured before using this function. - * - * @param clockName Clock names defined in clock_name_t - * @return Clock frequency value in Hertz - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); - -/*! - * @brief Get the core clock or system clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); - -/*! - * @brief Get the platform clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetPlatClkFreq(void); - -/*! - * @brief Get the bus clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetBusClkFreq(void); - -/*! - * @brief Get the flash clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetFlashClkFreq(void); - -/*! - * @brief Get the output clock frequency selected by SIM[PLLFLLSEL]. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetPllFllSelClkFreq(void); - -/*! - * @brief Get the external reference 32K clock frequency (ERCLK32K). - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetEr32kClkFreq(void); - -/*! - * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK). - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetOsc0ErClkFreq(void); - -/*! - * @brief Set the clock configure in SIM module. - * - * This function sets system layer clock settings in SIM module. - * - * @param config Pointer to the configure structure. - */ -void CLOCK_SetSimConfig(sim_clock_config_t const *config); - -/*! - * @brief Set the system clock dividers in SIM to safe value. - * - * The system level clocks (core clock, bus clock, flexbus clock and flash clock) - * must be in allowed ranges. During MCG clock mode switch, the MCG output clock - * changes then the system level clocks may be out of range. This function could - * be used before MCG mode change, to make sure system level clocks are in allowed - * range. - * - * @param config Pointer to the configure structure. - */ -static inline void CLOCK_SetSimSafeDivs(void) -{ - SIM->CLKDIV1 = 0x00010000U; -} - -/*! @name MCG frequency functions. */ -/*@{*/ - -/*! - * @brief Gets the MCG output clock (MCGOUTCLK) frequency. - * - * This function gets the MCG output clock frequency in Hz based on the current MCG - * register value. - * - * @return The frequency of MCGOUTCLK. - */ -uint32_t CLOCK_GetOutClkFreq(void); - -/*! - * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency. - * - * This function gets the MCG FLL clock frequency in Hz based on the current MCG - * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and - * disabled in low power state in other modes. - * - * @return The frequency of MCGFLLCLK. - */ -uint32_t CLOCK_GetFllFreq(void); - -/*! - * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency. - * - * This function gets the MCG internal reference clock frequency in Hz based - * on the current MCG register value. - * - * @return The frequency of MCGIRCLK. - */ -uint32_t CLOCK_GetInternalRefClkFreq(void); - -/*! - * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency. - * - * This function gets the MCG fixed frequency clock frequency in Hz based - * on the current MCG register value. - * - * @return The frequency of MCGFFCLK. - */ -uint32_t CLOCK_GetFixedFreqClkFreq(void); - -/*! - * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency. - * - * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG - * register value. - * - * @return The frequency of MCGPLL0CLK. - */ -uint32_t CLOCK_GetPll0Freq(void); - -/*@}*/ - -/*! @name MCG clock configuration. */ -/*@{*/ - -/*! - * @brief Enables or disables the MCG low power. - * - * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words, - * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and - * PBI modes, enabling low power sets the MCG to BLPI mode. - * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings. - * - * @param enable True to enable MCG low power, false to disable MCG low power. - */ -static inline void CLOCK_SetLowPowerEnable(bool enable) -{ - if (enable) - { - MCG->C2 |= MCG_C2_LP_MASK; - } - else - { - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; - } -} - -/*! - * @brief Configures the Internal Reference clock (MCGIRCLK). - * - * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC - * source. If the fast IRC is used, this function sets the fast IRC divider. - * This function also sets whether the \c MCGIRCLK is enabled in stop mode. - * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result, - * using the function in these modes it is not allowed. - * - * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. - * @param ircs MCGIRCLK clock source, choose fast or slow. - * @param fcrdiv Fast IRC divider setting (\c FCRDIV). - * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source, - * the configuration should not be changed. Otherwise, a glitch occurs. - * @retval kStatus_Success MCGIRCLK configuration finished successfully. - */ -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv); - -/*! - * @brief Selects the MCG external reference clock. - * - * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL], - * and waits for the clock source to be stable. Because the external reference - * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes. - * - * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. - * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source, - * the configuration should not be changed. Otherwise, a glitch occurs. - * @retval kStatus_Success External reference clock set successfully. - */ -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); - -/*! - * @brief Set the FLL external reference clock divider value. - * - * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV]. - * - * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV]. - */ -static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv) -{ - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); -} - -/*! - * @brief Enables the PLL0 in FLL mode. - * - * This function sets us the PLL0 in FLL mode and reconfigures - * the PLL0. Ensure that the PLL reference - * clock is enabled before calling this function and that the PLL0 is not used as a clock source. - * The function CLOCK_CalcPllDiv gets the correct PLL - * divider values. - * - * @param config Pointer to the configuration structure. - */ -void CLOCK_EnablePll0(mcg_pll_config_t const *config); - -/*! - * @brief Disables the PLL0 in FLL mode. - * - * This function disables the PLL0 in FLL mode. It should be used together with the - * @ref CLOCK_EnablePll0. - */ -static inline void CLOCK_DisablePll0(void) -{ - MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); -} - -/*! - * @brief Calculates the PLL divider setting for a desired output frequency. - * - * This function calculates the correct reference clock divider (\c PRDIV) and - * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the - * closest frequency match with the corresponding \c PRDIV/VDIV - * returned from parameters. If a desired frequency is not valid, this function - * returns 0. - * - * @param refFreq PLL reference clock frequency. - * @param desireFreq Desired PLL output frequency. - * @param prdiv PRDIV value to generate desired PLL frequency. - * @param vdiv VDIV value to generate desired PLL frequency. - * @return Closest frequency match that the PLL was able generate. - */ -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv); - -/*! - * brief Sets the OSC0 clock monitor mode. - * - * This function sets the OSC0 clock monitor mode. See ref mcg_monitor_mode_t for details. - * - * param mode Monitor mode to set. - */ -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode); - -/*@}*/ - -/*! @name MCG clock lock monitor functions. */ -/*@{*/ - -/*! - * @brief Sets the OSC0 clock monitor mode. - * - * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details. - * - * @param mode Monitor mode to set. - */ -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode); - -/*! - * @brief Sets the RTC OSC clock monitor mode. - * - * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details. - * - * @param mode Monitor mode to set. - */ -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode); - -/*! - * @brief Sets the PLL0 clock monitor mode. - * - * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details. - * - * @param mode Monitor mode to set. - */ -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode); - -/*! - * @brief Gets the MCG status flags. - * - * This function gets the MCG clock status flags. All status flags are - * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To - * check a specific flag, compare the return value with the flag. - * - * Example: - * @code - * To check the clock lost lock status of OSC0 and PLL0. - * uint32_t mcgFlags; - * - * mcgFlags = CLOCK_GetStatusFlags(); - * - * if (mcgFlags & kMCG_Osc0LostFlag) - * { - * OSC0 clock lock lost. Do something. - * } - * if (mcgFlags & kMCG_Pll0LostFlag) - * { - * PLL0 clock lock lost. Do something. - * } - * @endcode - * - * @return Logical OR value of the @ref _mcg_status_flags_t. - */ -uint32_t CLOCK_GetStatusFlags(void); - -/*! - * @brief Clears the MCG status flags. - * - * This function clears the MCG clock lock lost status. The parameter is a logical - * OR value of the flags to clear. See @ref _mcg_status_flags_t. - * - * Example: - * @code - * To clear the clock lost lock status flags of OSC0 and PLL0. - * - * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag); - * @endcode - * - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration @ref _mcg_status_flags_t. - */ -void CLOCK_ClearStatusFlags(uint32_t mask); - -/*@}*/ - -/*! - * @name OSC configuration - * @{ - */ - -/*! - * @brief Configures the OSC external reference clock (OSCERCLK). - * - * This function configures the OSC external reference clock (OSCERCLK). - * This is an example to enable the OSCERCLK in normal and stop modes and also set - * the output divider to 1: - * - @code - oscer_config_t config = - { - .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop, - .erclkDiv = 1U, - }; - - OSC_SetExtRefClkConfig(OSC, &config); - @endcode - * - * @param base OSC peripheral address. - * @param config Pointer to the configuration structure. - */ -static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config) -{ - uint8_t reg = base->CR; - - reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); - reg |= config->enableMode; - - base->CR = reg; -} - -/*! - * @brief Sets the capacitor load configuration for the oscillator. - * - * This function sets the specified capacitors configuration for the oscillator. - * This should be done in the early system level initialization function call - * based on the system configuration. - * - * @param base OSC peripheral address. - * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load. - * - * Example: - @code - To enable only 2 pF and 8 pF capacitor load, please use like this. - OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P); - @endcode - */ -static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) -{ - uint8_t reg = base->CR; - - reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK); - reg |= capLoad; - - base->CR = reg; -} - -/*! - * @brief Initializes the OSC0. - * - * This function initializes the OSC0 according to the board configuration. - * - * @param config Pointer to the OSC0 configuration structure. - */ -void CLOCK_InitOsc0(osc_config_t const *config); - -/*! - * @brief Deinitializes the OSC0. - * - * This function deinitializes the OSC0. - */ -void CLOCK_DeinitOsc0(void); - -/* @} */ - -/*! - * @name External clock frequency - * @{ - */ - -/*! - * @brief Sets the XTAL0 frequency based on board settings. - * - * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. - */ -static inline void CLOCK_SetXtal0Freq(uint32_t freq) -{ - g_xtal0Freq = freq; -} - -/*! - * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings. - * - * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. - */ -static inline void CLOCK_SetXtal32Freq(uint32_t freq) -{ - g_xtal32Freq = freq; -} -/* @} */ - -/*! - * @name MCG auto-trim machine. - * @{ - */ - -/*! - * @brief Auto trims the internal reference clock. - * - * This function trims the internal reference clock by using the external clock. If - * successful, it returns the kStatus_Success and the frequency after - * trimming is received in the parameter @p actualFreq. If an error occurs, - * the error code is returned. - * - * @param extFreq External clock frequency, which should be a bus clock. - * @param desireFreq Frequency to trim to. - * @param actualFreq Actual frequency after trimming. - * @param atms Trim fast or slow internal reference clock. - * @retval kStatus_Success ATM success. - * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM. - * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency. - * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source. - * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming. - */ -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms); -/* @} */ - -/*! @name MCG mode functions. */ -/*@{*/ - -/*! - * @brief Gets the current MCG mode. - * - * This function checks the MCG registers and determines the current MCG mode. - * - * @return Current MCG mode or error code; See @ref mcg_mode_t. - */ -mcg_mode_t CLOCK_GetMode(void); - -/*! - * @brief Sets the MCG to FEI mode. - * - * This function sets the MCG to FEI mode. If setting to FEI mode fails - * from the current mode, this function returns an error. - * - * @param dmx32 DMX32 in FEI mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing - * NULL does not cause a delay. - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed - * to a frequency above 32768 Hz. - */ -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to FEE mode. - * - * This function sets the MCG to FEE mode. If setting to FEE mode fails - * from the current mode, this function returns an error. - * - * @param frdiv FLL reference clock divider setting, FRDIV. - * @param dmx32 DMX32 in FEE mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to make sure FLL is stable. Passing - * NULL does not cause a delay. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to FBI mode. - * - * This function sets the MCG to FBI mode. If setting to FBI mode fails - * from the current mode, this function returns an error. - * - * @param dmx32 DMX32 in FBI mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL - * is not used in FBI mode, this parameter can be NULL. Passing - * NULL does not cause a delay. - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed - * to frequency above 32768 Hz. - */ -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to FBE mode. - * - * This function sets the MCG to FBE mode. If setting to FBE mode fails - * from the current mode, this function returns an error. - * - * @param frdiv FLL reference clock divider setting, FRDIV. - * @param dmx32 DMX32 in FBE mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL - * is not used in FBE mode, this parameter can be NULL. Passing NULL - * does not cause a delay. - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to BLPI mode. - * - * This function sets the MCG to BLPI mode. If setting to BLPI mode fails - * from the current mode, this function returns an error. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetBlpiMode(void); - -/*! - * @brief Sets the MCG to BLPE mode. - * - * This function sets the MCG to BLPE mode. If setting to BLPE mode fails - * from the current mode, this function returns an error. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetBlpeMode(void); - -/*! - * @brief Sets the MCG to PBE mode. - * - * This function sets the MCG to PBE mode. If setting to PBE mode fails - * from the current mode, this function returns an error. - * - * @param pllcs The PLL selection, PLLCS. - * @param config Pointer to the PLL configuration. - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - * - * @note - * 1. The parameter \c pllcs selects the PLL. For platforms with - * only one PLL, the parameter pllcs is kept for interface compatibility. - * 2. The parameter \c config is the PLL configuration structure. On some - * platforms, it is possible to choose the external PLL directly, which renders the - * configuration structure not necessary. In this case, pass in NULL. - * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); - */ -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); - -/*! - * @brief Sets the MCG to PEE mode. - * - * This function sets the MCG to PEE mode. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - * - * @note This function only changes the CLKS to use the PLL/FLL output. If the - * PRDIV/VDIV are different than in the PBE mode, set them up - * in PBE mode and wait. When the clock is stable, switch to PEE mode. - */ -status_t CLOCK_SetPeeMode(void); - -/*! - * @brief Switches the MCG to FBE mode from the external mode. - * - * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly. - * The external clock is used as the system clock source and PLL is disabled. However, - * the FLL settings are not configured. This is a lite function with a small code size, which is useful - * during the mode switch. For example, to switch from PEE mode to FEI mode: - * - * @code - * CLOCK_ExternalModeToFbeModeQuick(); - * CLOCK_SetFeiMode(...); - * @endcode - * - * @retval kStatus_Success Switched successfully. - * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function. - */ -status_t CLOCK_ExternalModeToFbeModeQuick(void); - -/*! - * @brief Switches the MCG to FBI mode from internal modes. - * - * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly. - * The MCGIRCLK is used as the system clock source and PLL is disabled. However, - * FLL settings are not configured. This is a lite function with a small code size, which is useful - * during the mode switch. For example, to switch from PEI mode to FEE mode: - * - * @code - * CLOCK_InternalModeToFbiModeQuick(); - * CLOCK_SetFeeMode(...); - * @endcode - * - * @retval kStatus_Success Switched successfully. - * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function. - */ -status_t CLOCK_InternalModeToFbiModeQuick(void); - -/*! - * @brief Sets the MCG to FEI mode during system boot up. - * - * This function sets the MCG to FEI mode from the reset mode. It can also be used to - * set up MCG during system boot up. - * - * @param dmx32 DMX32 in FEI mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to ensure that the FLL is stable. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed - * to frequency above 32768 Hz. - */ -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to FEE mode during system bootup. - * - * This function sets MCG to FEE mode from the reset mode. It can also be used to - * set up the MCG during system boot up. - * - * @param oscsel OSC clock select, OSCSEL. - * @param frdiv FLL reference clock divider setting, FRDIV. - * @param dmx32 DMX32 in FEE mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to ensure that the FLL is stable. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToFeeMode( - mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to BLPI mode during system boot up. - * - * This function sets the MCG to BLPI mode from the reset mode. It can also be used to - * set up the MCG during system boot up. - * - * @param fcrdiv Fast IRC divider, FCRDIV. - * @param ircs The internal reference clock to select, IRCS. - * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. - * - * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode); - -/*! - * @brief Sets the MCG to BLPE mode during system boot up. - * - * This function sets the MCG to BLPE mode from the reset mode. It can also be used to - * set up the MCG during system boot up. - * - * @param oscsel OSC clock select, MCG_C7[OSCSEL]. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel); - -/*! - * @brief Sets the MCG to PEE mode during system boot up. - * - * This function sets the MCG to PEE mode from reset mode. It can also be used to - * set up the MCG during system boot up. - * - * @param oscsel OSC clock select, MCG_C7[OSCSEL]. - * @param pllcs The PLL selection, PLLCS. - * @param config Pointer to the PLL configuration. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); - -/*! - * @brief Sets the MCG to a target mode. - * - * This function sets MCG to a target mode defined by the configuration - * structure. If switching to the target mode fails, this function - * chooses the correct path. - * - * @param config Pointer to the target MCG mode configuration structure. - * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status. - * - * @note If the external clock is used in the target mode, ensure that it is - * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this - * function. - */ -status_t CLOCK_SetMcgConfig(mcg_config_t const *config); - -/*! - * @brief Use DWT to delay at least for some time. - * Please note that, this API will calculate the microsecond period with the maximum - * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise - * delay count was needed, please implement a new timer count to achieve this function. - * - * @param delay_us Delay time in unit of microsecond. - */ -void SDK_DelayAtLeastUs(uint32_t delay_us); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_CLOCK_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmp.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmp.c deleted file mode 100644 index 557a0c5..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmp.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_cmp.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for CMP module. - * - * @param base CMP peripheral base address - */ -static uint32_t CMP_GetInstance(CMP_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to CMP bases for each instance. */ -static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; -/*! @brief Pointers to CMP clocks for each instance. */ -static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; - -/******************************************************************************* - * Codes - ******************************************************************************/ -static uint32_t CMP_GetInstance(CMP_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_CMP_COUNT; instance++) - { - if (s_cmpBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_CMP_COUNT); - - return instance; -} - -void CMP_Init(CMP_Type *base, const cmp_config_t *config) -{ - assert(NULL != config); - - uint8_t tmp8; - - /* Enable the clock. */ - CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); - - /* Configure. */ - CMP_Enable(base, false); /* Disable the CMP module during configuring. */ - /* CMPx_CR1. */ - tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK); - if (config->enableHighSpeed) - { - tmp8 |= CMP_CR1_PMODE_MASK; - } - if (config->enableInvertOutput) - { - tmp8 |= CMP_CR1_INV_MASK; - } - if (config->useUnfilteredOutput) - { - tmp8 |= CMP_CR1_COS_MASK; - } - if (config->enablePinOut) - { - tmp8 |= CMP_CR1_OPE_MASK; - } -#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE - if (config->enableTriggerMode) - { - tmp8 |= CMP_CR1_TRIGM_MASK; - } - else - { - tmp8 &= ~CMP_CR1_TRIGM_MASK; - } -#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ - base->CR1 = tmp8; - - /* CMPx_CR0. */ - tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK; - tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); - base->CR0 = tmp8; - - CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ -} - -void CMP_Deinit(CMP_Type *base) -{ - /* Disable the CMP module. */ - CMP_Enable(base, false); - - /* Disable the clock. */ - CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); -} - -void CMP_GetDefaultConfig(cmp_config_t *config) -{ - assert(NULL != config); - - config->enableCmp = true; /* Enable the CMP module after initialization. */ - config->hysteresisMode = kCMP_HysteresisLevel0; - config->enableHighSpeed = false; - config->enableInvertOutput = false; - config->useUnfilteredOutput = false; - config->enablePinOut = false; -#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE - config->enableTriggerMode = false; -#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ -} - -void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) -{ - uint8_t tmp8 = base->MUXCR; - - tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); - tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); - base->MUXCR = tmp8; -} - -#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA -void CMP_EnableDMA(CMP_Type *base, bool enable) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (enable) - { - tmp8 |= CMP_SCR_DMAEN_MASK; - } - else - { - tmp8 &= ~CMP_SCR_DMAEN_MASK; - } - base->SCR = tmp8; -} -#endif /* FSL_FEATURE_CMP_HAS_DMA */ - -void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) -{ - assert(NULL != config); - - uint8_t tmp8; - -#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT - /* Choose the clock source for sampling. */ - if (config->enableSample) - { - base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ - } - else - { - base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ - } -#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ - /* Set the filter count. */ - tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK; - tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); - base->CR0 = tmp8; - /* Set the filter period. It is used as the divider to bus clock. */ - base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); -} - -void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) -{ - uint8_t tmp8 = 0U; - - if (NULL == config) - { - /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ - base->DACCR = 0U; - return; - } - /* CMPx_DACCR. */ - tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ - if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) - { - tmp8 |= CMP_DACCR_VRSEL_MASK; - } - tmp8 |= CMP_DACCR_VOSEL(config->DACValue); - - base->DACCR = tmp8; -} - -void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (0U != (kCMP_OutputRisingInterruptEnable & mask)) - { - tmp8 |= CMP_SCR_IER_MASK; - } - if (0U != (kCMP_OutputFallingInterruptEnable & mask)) - { - tmp8 |= CMP_SCR_IEF_MASK; - } - base->SCR = tmp8; -} - -void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (0U != (kCMP_OutputRisingInterruptEnable & mask)) - { - tmp8 &= ~CMP_SCR_IER_MASK; - } - if (0U != (kCMP_OutputFallingInterruptEnable & mask)) - { - tmp8 &= ~CMP_SCR_IEF_MASK; - } - base->SCR = tmp8; -} - -uint32_t CMP_GetStatusFlags(CMP_Type *base) -{ - uint32_t ret32 = 0U; - - if (0U != (CMP_SCR_CFR_MASK & base->SCR)) - { - ret32 |= kCMP_OutputRisingEventFlag; - } - if (0U != (CMP_SCR_CFF_MASK & base->SCR)) - { - ret32 |= kCMP_OutputFallingEventFlag; - } - if (0U != (CMP_SCR_COUT_MASK & base->SCR)) - { - ret32 |= kCMP_OutputAssertEventFlag; - } - return ret32; -} - -void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (0U != (kCMP_OutputRisingEventFlag & mask)) - { - tmp8 |= CMP_SCR_CFR_MASK; - } - if (0U != (kCMP_OutputFallingEventFlag & mask)) - { - tmp8 |= CMP_SCR_CFF_MASK; - } - base->SCR = tmp8; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmp.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmp.h deleted file mode 100644 index 4c85bba..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmp.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CMP_H_ -#define _FSL_CMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmp - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CMP driver version 2.0.0. */ -#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! -* @brief Interrupt enable/disable mask. -*/ -enum _cmp_interrupt_enable -{ - kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */ - kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */ -}; - -/*! - * @brief Status flags' mask. - */ -enum _cmp_status_flags -{ - kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on compare output has occurred. */ - kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on compare output has occurred. */ - kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */ -}; - -/*! - * @brief CMP Hysteresis mode. - */ -typedef enum _cmp_hysteresis_mode -{ - kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */ - kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */ - kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */ - kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */ -} cmp_hysteresis_mode_t; - -/*! - * @brief CMP Voltage Reference source. - */ -typedef enum _cmp_reference_voltage_source -{ - kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as resistor ladder network supply reference Vin. */ - kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as resistor ladder network supply reference Vin. */ -} cmp_reference_voltage_source_t; - -/*! - * @brief Configuration for the comparator. - */ -typedef struct _cmp_config -{ - bool enableCmp; /*!< Enable the CMP module. */ - cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */ - bool enableHighSpeed; /*!< Enable High-speed comparison mode. */ - bool enableInvertOutput; /*!< Enable inverted comparator output. */ - bool useUnfilteredOutput; /*!< Set compare output(COUT) to equal COUTA(true) or COUT(false). */ - bool enablePinOut; /*!< The comparator output is available on the associated pin. */ -#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE - bool enableTriggerMode; /*!< Enable the trigger mode. */ -#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ -} cmp_config_t; - -/*! - * @brief Configuration for the filter. - */ -typedef struct _cmp_filter_config -{ -#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT - bool enableSample; /*!< Using external SAMPLE as sampling clock input, or using divided bus clock. */ -#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ - uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled.*/ - uint8_t filterPeriod; /*!< Filter Sample Period. The divider to bus clock. Available range is 0-255. */ -} cmp_filter_config_t; - -/*! - * @brief Configuration for the internal DAC. - */ -typedef struct _cmp_dac_config -{ - cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */ - uint8_t DACValue; /*!< Value for DAC Output Voltage. Available range is 0-63.*/ -} cmp_dac_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the CMP. - * - * This function initializes the CMP module. The operations included are: - * - Enabling the clock for CMP module. - * - Configuring the comparator. - * - Enabling the CMP module. - * Note: For some devices, multiple CMP instance share the same clock gate. In this case, to enable the clock for - * any instance enables all the CMPs. Check the chip reference manual for the clock assignment of the CMP. - * - * @param base CMP peripheral base address. - * @param config Pointer to configuration structure. - */ -void CMP_Init(CMP_Type *base, const cmp_config_t *config); - -/*! - * @brief De-initializes the CMP module. - * - * This function de-initializes the CMP module. The operations included are: - * - Disabling the CMP module. - * - Disabling the clock for CMP module. - * - * This function disables the clock for the CMP. - * Note: For some devices, multiple CMP instance shares the same clock gate. In this case, before disabling the - * clock for the CMP, ensure that all the CMP instances are not used. - * - * @param base CMP peripheral base address. - */ -void CMP_Deinit(CMP_Type *base); - -/*! - * @brief Enables/disables the CMP module. - * - * @param base CMP peripheral base address. - * @param enable Enable the module or not. - */ -static inline void CMP_Enable(CMP_Type *base, bool enable) -{ - if (enable) - { - base->CR1 |= CMP_CR1_EN_MASK; - } - else - { - base->CR1 &= ~CMP_CR1_EN_MASK; - } -} - -/*! -* @brief Initializes the CMP user configuration structure. -* -* This function initializes the user configuration structure to these default values: -* @code -* config->enableCmp = true; -* config->hysteresisMode = kCMP_HysteresisLevel0; -* config->enableHighSpeed = false; -* config->enableInvertOutput = false; -* config->useUnfilteredOutput = false; -* config->enablePinOut = false; -* config->enableTriggerMode = false; -* @endcode -* @param config Pointer to the configuration structure. -*/ -void CMP_GetDefaultConfig(cmp_config_t *config); - -/*! - * @brief Sets the input channels for the comparator. - * - * This function sets the input channels for the comparator. - * Note that two input channels cannot be set as same in the application. When the user selects the same input - * from the analog mux to the positive and negative port, the comparator is disabled automatically. - * - * @param base CMP peripheral base address. - * @param positiveChannel Positive side input channel number. Available range is 0-7. - * @param negativeChannel Negative side input channel number. Available range is 0-7. - */ -void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel); - -/* @} */ - -/*! - * @name Advanced Features - * @{ - */ - -#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA -/*! - * @brief Enables/disables the DMA request for rising/falling events. - * - * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of - * the DMA - * request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP - * if the - * DMA is disabled. - * - * @param base CMP peripheral base address. - * @param enable Enable the feature or not. - */ -void CMP_EnableDMA(CMP_Type *base, bool enable); -#endif /* FSL_FEATURE_CMP_HAS_DMA */ - -#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE -/*! - * @brief Enables/disables the window mode. - * - * @param base CMP peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable) -{ - if (enable) - { - base->CR1 |= CMP_CR1_WE_MASK; - } - else - { - base->CR1 &= ~CMP_CR1_WE_MASK; - } -} -#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */ - -#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE -/*! - * @brief Enables/disables the pass through mode. - * - * @param base CMP peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable) -{ - if (enable) - { - base->MUXCR |= CMP_MUXCR_PSTM_MASK; - } - else - { - base->MUXCR &= ~CMP_MUXCR_PSTM_MASK; - } -} -#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */ - -/*! - * @brief Configures the filter. - * - * @param base CMP peripheral base address. - * @param config Pointer to configuration structure. - */ -void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config); - -/*! - * @brief Configures the internal DAC. - * - * @param base CMP peripheral base address. - * @param config Pointer to configuration structure. "NULL" is for disabling the feature. - */ -void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config); - -/*! - * @brief Enables the interrupts. - * - * @param base CMP peripheral base address. - * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". - */ -void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask); - -/*! - * @brief Disables the interrupts. - * - * @param base CMP peripheral base address. - * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". - */ -void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Results - * @{ - */ - -/*! - * @brief Gets the status flags. - * - * @param base CMP peripheral base address. - * - * @return Mask value for the asserted flags. See "_cmp_status_flags". - */ -uint32_t CMP_GetStatusFlags(CMP_Type *base); - -/*! - * @brief Clears the status flags. - * - * @param base CMP peripheral base address. - * @param mask Mask value for the flags. See "_cmp_status_flags". - */ -void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask); - -/* @} */ -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_CMP_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmt.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmt.c deleted file mode 100644 index 43b2d3c..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmt.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_cmt.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* The standard intermediate frequency (IF). */ -#define CMT_INTERMEDIATEFREQUENCY_8MHZ (8000000U) -/* CMT data modulate mask. */ -#define CMT_MODULATE_COUNT_WIDTH (8U) -/* CMT diver 1. */ -#define CMT_CMTDIV_ONE (1) -/* CMT diver 2. */ -#define CMT_CMTDIV_TWO (2) -/* CMT diver 4. */ -#define CMT_CMTDIV_FOUR (4) -/* CMT diver 8. */ -#define CMT_CMTDIV_EIGHT (8) -/* CMT mode bit mask. */ -#define CMT_MODE_BIT_MASK (CMT_MSC_MCGEN_MASK | CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for CMT module. - * - * @param base CMT peripheral base address. - */ -static uint32_t CMT_GetInstance(CMT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to cmt clocks for each instance. */ -static const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS; - -/*! @brief Pointers to cmt bases for each instance. */ -static CMT_Type *const s_cmtBases[] = CMT_BASE_PTRS; - -/*! @brief Pointers to cmt IRQ number for each instance. */ -static const IRQn_Type s_cmtIrqs[] = CMT_IRQS; - -/******************************************************************************* - * Codes - ******************************************************************************/ - -static uint32_t CMT_GetInstance(CMT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_CMT_COUNT; instance++) - { - if (s_cmtBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_CMT_COUNT); - - return instance; -} - -void CMT_GetDefaultConfig(cmt_config_t *config) -{ - assert(config); - - /* Default infrared output is enabled and set with high active, the divider is set to 1. */ - config->isInterruptEnabled = false; - config->isIroEnabled = true; - config->iroPolarity = kCMT_IROActiveHigh; - config->divider = kCMT_SecondClkDiv1; -} - -void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz) -{ - assert(config); - assert(busClock_Hz >= CMT_INTERMEDIATEFREQUENCY_8MHZ); - - uint8_t divider; - - /* Ungate clock. */ - CLOCK_EnableClock(s_cmtClock[CMT_GetInstance(base)]); - - /* Sets clock divider. The divider set in pps should be set - to make sycClock_Hz/divder = 8MHz */ - base->PPS = CMT_PPS_PPSDIV(busClock_Hz / CMT_INTERMEDIATEFREQUENCY_8MHZ - 1); - divider = base->MSC; - divider &= ~CMT_MSC_CMTDIV_MASK; - divider |= CMT_MSC_CMTDIV(config->divider); - base->MSC = divider; - - /* Set the IRO signal. */ - base->OC = CMT_OC_CMTPOL(config->iroPolarity) | CMT_OC_IROPEN(config->isIroEnabled); - - /* Set interrupt. */ - if (config->isInterruptEnabled) - { - CMT_EnableInterrupts(base, kCMT_EndOfCycleInterruptEnable); - EnableIRQ(s_cmtIrqs[CMT_GetInstance(base)]); - } -} - -void CMT_Deinit(CMT_Type *base) -{ - /*Disable the CMT modulator. */ - base->MSC = 0; - - /* Disable the interrupt. */ - CMT_DisableInterrupts(base, kCMT_EndOfCycleInterruptEnable); - DisableIRQ(s_cmtIrqs[CMT_GetInstance(base)]); - - /* Gate the clock. */ - CLOCK_DisableClock(s_cmtClock[CMT_GetInstance(base)]); -} - -void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig) -{ - uint8_t mscReg; - - /* Set the mode. */ - if (mode != kCMT_DirectIROCtl) - { - assert(modulateConfig); - - /* Set carrier generator. */ - CMT_SetCarrirGenerateCountOne(base, modulateConfig->highCount1, modulateConfig->lowCount1); - if (mode == kCMT_FSKMode) - { - CMT_SetCarrirGenerateCountTwo(base, modulateConfig->highCount2, modulateConfig->lowCount2); - } - - /* Set carrier modulator. */ - CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount); - } - - /* Set the CMT mode. */ - mscReg = base->MSC; - mscReg &= ~CMT_MODE_BIT_MASK; - mscReg |= mode; - - base->MSC = mscReg; -} - -cmt_mode_t CMT_GetMode(CMT_Type *base) -{ - uint8_t mode = base->MSC; - - if (!(mode & CMT_MSC_MCGEN_MASK)) - { /* Carrier modulator disabled and the IRO signal is in direct software control. */ - return kCMT_DirectIROCtl; - } - else - { - /* Carrier modulator is enabled. */ - if (mode & CMT_MSC_BASE_MASK) - { - /* Base band mode. */ - return kCMT_BasebandMode; - } - else if (mode & CMT_MSC_FSK_MASK) - { - /* FSK mode. */ - return kCMT_FSKMode; - } - else - { - /* Time mode. */ - return kCMT_TimeMode; - } - } -} - -uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz) -{ - uint32_t frequency; - uint32_t divider; - - /* Get intermediate frequency. */ - frequency = busClock_Hz / ((base->PPS & CMT_PPS_PPSDIV_MASK) + 1); - - /* Get the second divider. */ - divider = ((base->MSC & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT); - /* Get CMT frequency. */ - switch ((cmt_second_clkdiv_t)divider) - { - case kCMT_SecondClkDiv1: - frequency = frequency / CMT_CMTDIV_ONE; - break; - case kCMT_SecondClkDiv2: - frequency = frequency / CMT_CMTDIV_TWO; - break; - case kCMT_SecondClkDiv4: - frequency = frequency / CMT_CMTDIV_FOUR; - break; - case kCMT_SecondClkDiv8: - frequency = frequency / CMT_CMTDIV_EIGHT; - break; - default: - frequency = frequency / CMT_CMTDIV_ONE; - break; - } - - return frequency; -} - -void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount) -{ - /* Set modulate mark. */ - base->CMD1 = (markCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD1_MB_MASK; - base->CMD2 = (markCount & CMT_CMD2_MB_MASK); - /* Set modulate space. */ - base->CMD3 = (spaceCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD3_SB_MASK; - base->CMD4 = spaceCount & CMT_CMD4_SB_MASK; -} - -void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state) -{ - uint8_t ocReg = base->OC; - - ocReg &= ~CMT_OC_IROL_MASK; - ocReg |= CMT_OC_IROL(state); - - /* Set the infrared output signal control. */ - base->OC = ocReg; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmt.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmt.h deleted file mode 100644 index 0d57583..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_cmt.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_CMT_H_ -#define _FSL_CMT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmt - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CMT driver version 2.0.1. */ -#define FSL_CMT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief The modes of CMT. - */ -typedef enum _cmt_mode -{ - kCMT_DirectIROCtl = 0x00U, /*!< Carrier modulator is disabled and the IRO signal is directly in software control */ - kCMT_TimeMode = 0x01U, /*!< Carrier modulator is enabled in time mode. */ - kCMT_FSKMode = 0x05U, /*!< Carrier modulator is enabled in FSK mode. */ - kCMT_BasebandMode = 0x09U /*!< Carrier modulator is enabled in baseband mode. */ -} cmt_mode_t; - -/*! - * @brief The CMT clock divide primary prescaler. - * The primary clock divider is used to divider the bus clock to - * get the intermediate frequency to approximately equal to 8 MHZ. - * When the bus clock is 8 MHZ, set primary prescaler to "kCMT_PrimaryClkDiv1". - */ -typedef enum _cmt_primary_clkdiv -{ - kCMT_PrimaryClkDiv1 = 0U, /*!< The intermediate frequency is the bus clock divided by 1. */ - kCMT_PrimaryClkDiv2 = 1U, /*!< The intermediate frequency is the bus clock divided by 2. */ - kCMT_PrimaryClkDiv3 = 2U, /*!< The intermediate frequency is the bus clock divided by 3. */ - kCMT_PrimaryClkDiv4 = 3U, /*!< The intermediate frequency is the bus clock divided by 4. */ - kCMT_PrimaryClkDiv5 = 4U, /*!< The intermediate frequency is the bus clock divided by 5. */ - kCMT_PrimaryClkDiv6 = 5U, /*!< The intermediate frequency is the bus clock divided by 6. */ - kCMT_PrimaryClkDiv7 = 6U, /*!< The intermediate frequency is the bus clock divided by 7. */ - kCMT_PrimaryClkDiv8 = 7U, /*!< The intermediate frequency is the bus clock divided by 8. */ - kCMT_PrimaryClkDiv9 = 8U, /*!< The intermediate frequency is the bus clock divided by 9. */ - kCMT_PrimaryClkDiv10 = 9U, /*!< The intermediate frequency is the bus clock divided by 10. */ - kCMT_PrimaryClkDiv11 = 10U, /*!< The intermediate frequency is the bus clock divided by 11. */ - kCMT_PrimaryClkDiv12 = 11U, /*!< The intermediate frequency is the bus clock divided by 12. */ - kCMT_PrimaryClkDiv13 = 12U, /*!< The intermediate frequency is the bus clock divided by 13. */ - kCMT_PrimaryClkDiv14 = 13U, /*!< The intermediate frequency is the bus clock divided by 14. */ - kCMT_PrimaryClkDiv15 = 14U, /*!< The intermediate frequency is the bus clock divided by 15. */ - kCMT_PrimaryClkDiv16 = 15U /*!< The intermediate frequency is the bus clock divided by 16. */ -} cmt_primary_clkdiv_t; - -/*! - * @brief The CMT clock divide secondary prescaler. - * The second prescaler can be used to divide the 8 MHZ CMT clock - * by 1, 2, 4, or 8 according to the specification. - */ -typedef enum _cmt_second_clkdiv -{ - kCMT_SecondClkDiv1 = 0U, /*!< The CMT clock is the intermediate frequency frequency divided by 1. */ - kCMT_SecondClkDiv2 = 1U, /*!< The CMT clock is the intermediate frequency frequency divided by 2. */ - kCMT_SecondClkDiv4 = 2U, /*!< The CMT clock is the intermediate frequency frequency divided by 4. */ - kCMT_SecondClkDiv8 = 3U /*!< The CMT clock is the intermediate frequency frequency divided by 8. */ -} cmt_second_clkdiv_t; - -/*! - * @brief The CMT infrared output polarity. - */ -typedef enum _cmt_infrared_output_polarity -{ - kCMT_IROActiveLow = 0U, /*!< The CMT infrared output signal polarity is active-low. */ - kCMT_IROActiveHigh = 1U /*!< The CMT infrared output signal polarity is active-high. */ -} cmt_infrared_output_polarity_t; - -/*! - * @brief The CMT infrared output signal state control. - */ -typedef enum _cmt_infrared_output_state -{ - kCMT_IROCtlLow = 0U, /*!< The CMT Infrared output signal state is controlled to low. */ - kCMT_IROCtlHigh = 1U /*!< The CMT Infrared output signal state is controlled to high. */ -} cmt_infrared_output_state_t; - -/*! - * @brief CMT interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the CMT interrupt configurations. - */ -enum _cmt_interrupt_enable -{ - kCMT_EndOfCycleInterruptEnable = CMT_MSC_EOCIE_MASK, /*!< CMT end of cycle interrupt. */ -}; - -/*! - * @brief CMT carrier generator and modulator configuration structure - * - */ -typedef struct _cmt_modulate_config -{ - uint8_t highCount1; /*!< The high time for carrier generator first register. */ - uint8_t lowCount1; /*!< The low time for carrier generator first register. */ - uint8_t highCount2; /*!< The high time for carrier generator second register for FSK mode. */ - uint8_t lowCount2; /*!< The low time for carrier generator second register for FSK mode. */ - uint16_t markCount; /*!< The mark time for the modulator gate. */ - uint16_t spaceCount; /*!< The space time for the modulator gate. */ -} cmt_modulate_config_t; - -/*! @brief CMT basic configuration structure. */ -typedef struct _cmt_config -{ - bool isInterruptEnabled; /*!< Timer interrupt 0-disable, 1-enable. */ - bool isIroEnabled; /*!< The IRO output 0-disabled, 1-enabled. */ - cmt_infrared_output_polarity_t iroPolarity; /*!< The IRO polarity. */ - cmt_second_clkdiv_t divider; /*!< The CMT clock divide prescaler. */ -} cmt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Gets the CMT default configuration structure. The purpose - * of this API is to get the default configuration structure for the CMT_Init(). - * Use the initialized structure unchanged in CMT_Init(), or modify - * some fields of the structure before calling the CMT_Init(). - * - * @param config The CMT configuration structure pointer. - */ -void CMT_GetDefaultConfig(cmt_config_t *config); - -/*! - * @brief Initializes the CMT module. - * - * This function ungates the module clock and sets the CMT internal clock, - * interrupt, and infrared output signal for the CMT module. - * - * @param base CMT peripheral base address. - * @param config The CMT basic configuration structure. - * @param busClock_Hz The CMT module input clock - bus clock frequency. - */ -void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz); - -/*! - * @brief Disables the CMT module and gate control. - * - * This function disables CMT modulator, interrupts, and gates the - * CMT clock control. CMT_Init must be called to use the CMT again. - * - * @param base CMT peripheral base address. - */ -void CMT_Deinit(CMT_Type *base); - -/*! @}*/ - -/*! - * @name Basic Control Operations - * @{ - */ - -/*! - * @brief Selects the mode for CMT. - * - * @param base CMT peripheral base address. - * @param mode The CMT feature mode enumeration. See "cmt_mode_t". - * @param modulateConfig The carrier generation and modulator configuration. - */ -void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig); - -/*! - * @brief Gets the mode of the CMT module. - * - * @param base CMT peripheral base address. - * @return The CMT mode. - * kCMT_DirectIROCtl Carrier modulator is disabled, the IRO signal is directly in software control. - * kCMT_TimeMode Carrier modulator is enabled in time mode. - * kCMT_FSKMode Carrier modulator is enabled in FSK mode. - * kCMT_BasebandMode Carrier modulator is enabled in baseband mode. - */ -cmt_mode_t CMT_GetMode(CMT_Type *base); - -/*! - * @brief Gets the actual CMT clock frequency. - * - * @param base CMT peripheral base address. - * @param busClock_Hz CMT module input clock - bus clock frequency. - * @return The CMT clock frequency. - */ -uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz); - -/*! - * @brief Sets the primary data set for the CMT carrier generator counter. - * - * This function sets the high time and low time of the primary data set for the - * CMT carrier generator counter to control the period and the duty cycle of the - * output carrier signal. - * If the CMT clock period is Tcmt, The period of the carrier generator signal equals - * (highCount + lowCount) * Tcmt. The duty cycle equals highCount / (highCount + lowCount). - * - * @param base CMT peripheral base address. - * @param highCount The number of CMT clocks for carrier generator signal high time, - * integer in the range of 1 ~ 0xFF. - * @param lowCount The number of CMT clocks for carrier generator signal low time, - * integer in the range of 1 ~ 0xFF. - */ -static inline void CMT_SetCarrirGenerateCountOne(CMT_Type *base, uint32_t highCount, uint32_t lowCount) -{ - assert(highCount <= CMT_CGH1_PH_MASK); - assert(highCount); - assert(lowCount <= CMT_CGL1_PL_MASK); - assert(lowCount); - - base->CGH1 = highCount; - base->CGL1 = lowCount; -} - -/*! - * @brief Sets the secondary data set for the CMT carrier generator counter. - * - * This function is used for FSK mode setting the high time and low time of the secondary - * data set CMT carrier generator counter to control the period and the duty cycle - * of the output carrier signal. - * If the CMT clock period is Tcmt, The period of the carrier generator signal equals - * (highCount + lowCount) * Tcmt. The duty cycle equals highCount / (highCount + lowCount). - * - * @param base CMT peripheral base address. - * @param highCount The number of CMT clocks for carrier generator signal high time, - * integer in the range of 1 ~ 0xFF. - * @param lowCount The number of CMT clocks for carrier generator signal low time, - * integer in the range of 1 ~ 0xFF. - */ -static inline void CMT_SetCarrirGenerateCountTwo(CMT_Type *base, uint32_t highCount, uint32_t lowCount) -{ - assert(highCount <= CMT_CGH2_SH_MASK); - assert(highCount); - assert(lowCount <= CMT_CGL2_SL_MASK); - assert(lowCount); - - base->CGH2 = highCount; - base->CGL2 = lowCount; -} - -/*! - * @brief Sets the modulation mark and space time period for the CMT modulator. - * - * This function sets the mark time period of the CMT modulator counter - * to control the mark time of the output modulated signal from the carrier generator output signal. - * If the CMT clock frequency is Fcmt and the carrier out signal frequency is fcg: - * - In Time and Baseband mode: The mark period of the generated signal equals (markCount + 1) / (Fcmt/8). - * The space period of the generated signal equals spaceCount / (Fcmt/8). - * - In FSK mode: The mark period of the generated signal equals (markCount + 1)/fcg. - * The space period of the generated signal equals spaceCount / fcg. - * - * @param base Base address for current CMT instance. - * @param markCount The number of clock period for CMT modulator signal mark period, - * in the range of 0 ~ 0xFFFF. - * @param spaceCount The number of clock period for CMT modulator signal space period, - * in the range of the 0 ~ 0xFFFF. - */ -void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount); - -/*! - * @brief Enables or disables the extended space operation. - * - * This function is used to make the space period longer - * for time, baseband, and FSK modes. - * - * @param base CMT peripheral base address. - * @param enable True enable the extended space, false disable the extended space. - */ -static inline void CMT_EnableExtendedSpace(CMT_Type *base, bool enable) -{ - if (enable) - { - base->MSC |= CMT_MSC_EXSPC_MASK; - } - else - { - base->MSC &= ~CMT_MSC_EXSPC_MASK; - } -} - -/*! - * @brief Sets IRO - infrared output signal state. - * - * Changes the states of the IRO signal when the kCMT_DirectIROMode mode is set - * and the IRO signal is enabled. - * - * @param base CMT peripheral base address. - * @param state The control of the IRO signal. See "cmt_infrared_output_state_t" - */ -void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state); - -/*! - * @brief Enables the CMT interrupt. - * - * This function enables the CMT interrupts according to the provided maskIf enabled. - * The CMT only has the end of the cycle interrupt - an interrupt occurs at the end - * of the modulator cycle. This interrupt provides a means for the user - * to reload the new mark/space values into the CMT modulator data registers - * and verify the modulator mark and space. - * For example, to enable the end of cycle, do the following: - * @code - * CMT_EnableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable); - * @endcode - * @param base CMT peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable. - */ -static inline void CMT_EnableInterrupts(CMT_Type *base, uint32_t mask) -{ - base->MSC |= mask; -} - -/*! - * @brief Disables the CMT interrupt. - * - * This function disables the CMT interrupts according to the provided maskIf enabled. - * The CMT only has the end of the cycle interrupt. - * For example, to disable the end of cycle, do the following: - * @code - * CMT_DisableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable); - * @endcode - * - * @param base CMT peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable. - */ -static inline void CMT_DisableInterrupts(CMT_Type *base, uint32_t mask) -{ - base->MSC &= ~mask; -} - -/*! - * @brief Gets the end of the cycle status flag. - * - * The flag is set: - * - When the modulator is not currently active and carrier and modulator - * are set to start the initial CMT transmission. - * - At the end of each modulation cycle when the counter is reloaded and - * the carrier and modulator are enabled. - * @param base CMT peripheral base address. - * @return Current status of the end of cycle status flag - * @arg non-zero: End-of-cycle has occurred. - * @arg zero: End-of-cycle has not yet occurred since the flag last cleared. - */ -static inline uint32_t CMT_GetStatusFlags(CMT_Type *base) -{ - return base->MSC & CMT_MSC_EOCF_MASK; -} - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CMT_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_common.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_common.h deleted file mode 100644 index ab04cd9..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_common.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include -#include -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Construct the version number for drivers. */ -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/*! @name Min/max macros */ -/* @{ */ -#if !defined(MIN) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enable specific interrupt. - * - * Enable the interrupt not routed from intmux. - * - * @param interrupt The IRQ number. - */ -static inline void EnableIRQ(IRQn_Type interrupt) -{ -#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) - if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) -#endif - { - NVIC_EnableIRQ(interrupt); - } -} - -/*! - * @brief Disable specific interrupt. - * - * Disable the interrupt not routed from intmux. - * - * @param interrupt The IRQ number. - */ -static inline void DisableIRQ(IRQn_Type interrupt) -{ -#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) - if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) -#endif - { - NVIC_DisableIRQ(interrupt); - } -} - -/*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ -static inline uint32_t DisableGlobalIRQ(void) -{ - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -} - -/*! - * @brief Enaable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ -static inline void EnableGlobalIRQ(uint32_t primask) -{ - __set_PRIMASK(primask); -} - -/*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - */ -void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_COMMON_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_crc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_crc.c deleted file mode 100644 index de86e32..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_crc.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @internal @brief Has data register with name CRC. */ -#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG -#define DATA CRC -#define DATALL CRCLL -#endif - -#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT -/* @brief Default user configuration structure for CRC-16-CCITT */ -#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U -/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */ -#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU -/*< Default initial checksum */ -#define CRC_DRIVER_DEFAULT_REFLECT_IN false -/*< Default is no transpose */ -#define CRC_DRIVER_DEFAULT_REFLECT_OUT false -/*< Default is transpose bytes */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false -/*< Default is without complement of CRC data register read data */ -#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16 -/*< Default is 16-bit CRC protocol */ -#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum -/*< Default is resutl type is final checksum */ -#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ - -/*! @brief CRC type of transpose of read write data */ -typedef enum _crc_transpose_type -{ - kCrcTransposeNone = 0U, /*! No transpose */ - kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */ - kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */ - kCrcTransposeBytes = 3U, /*! Transpose bytes */ -} crc_transpose_type_t; - -/*! -* @brief CRC module configuration. -* -* This structure holds the configuration for the CRC module. -*/ -typedef struct _crc_module_config -{ - uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n - Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ - uint32_t seed; /*!< Starting checksum value */ - crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */ - crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */ - bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ - crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ -} crc_module_config_t; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Returns transpose type for CRC protocol reflect in parameter. - * - * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter. - * - * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter. - */ -static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectIn(bool enable) -{ - return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes); -} - -/*! - * @brief Returns transpose type for CRC protocol reflect out parameter. - * - * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter. - * - * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter. - */ -static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectOut(bool enable) -{ - return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone); -} - -/*! - * @brief Starts checksum computation. - * - * Configures the CRC module for the specified CRC protocol. @n - * Starts the checksum computation by writing the seed value - * - * @param base CRC peripheral address. - * @param config Pointer to protocol configuration structure. - */ -static void crc_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config) -{ - uint32_t crcControl; - - /* pre-compute value for CRC control registger based on user configuraton without WAS field */ - crcControl = 0 | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) | - CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits); - - /* make sure the control register is clear - WAS is deasserted, and protocol is set */ - base->CTRL = crcControl; - - /* write polynomial register */ - base->GPOLY = config->polynomial; - - /* write pre-computed control register value along with WAS to start checksum computation */ - base->CTRL = crcControl | CRC_CTRL_WAS(true); - - /* write seed (initial checksum) */ - base->DATA = config->seed; - - /* deassert WAS by writing pre-computed CRC control register value */ - base->CTRL = crcControl; -} - -/*! - * @brief Starts final checksum computation. - * - * Configures the CRC module for the specified CRC protocol. @n - * Starts final checksum computation by writing the seed value. - * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum - * (output reflection and xor functions are applied). - * - * @param base CRC peripheral address. - * @param protocolConfig Pointer to protocol configuration structure. - */ -static void crc_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) -{ - crc_module_config_t moduleConfig; - /* convert protocol to CRC peripheral module configuration, prepare for final checksum */ - moduleConfig.polynomial = protocolConfig->polynomial; - moduleConfig.seed = protocolConfig->seed; - moduleConfig.readTranspose = crc_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut); - moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); - moduleConfig.complementChecksum = protocolConfig->complementChecksum; - moduleConfig.crcBits = protocolConfig->crcBits; - - crc_ConfigureAndStart(base, &moduleConfig); -} - -/*! - * @brief Starts intermediate checksum computation. - * - * Configures the CRC module for the specified CRC protocol. @n - * Starts intermediate checksum computation by writing the seed value. - * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value). - * - * @param base CRC peripheral address. - * @param protocolConfig Pointer to protocol configuration structure. - */ -static void crc_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) -{ - crc_module_config_t moduleConfig; - /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */ - moduleConfig.polynomial = protocolConfig->polynomial; - moduleConfig.seed = protocolConfig->seed; - moduleConfig.readTranspose = - kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */ - moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); - moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */ - moduleConfig.crcBits = protocolConfig->crcBits; - - crc_ConfigureAndStart(base, &moduleConfig); -} - -void CRC_Init(CRC_Type *base, const crc_config_t *config) -{ - /* ungate clock */ - CLOCK_EnableClock(kCLOCK_Crc0); - /* configure CRC module and write the seed */ - if (config->crcResult == kCrcFinalChecksum) - { - crc_SetProtocolConfig(base, config); - } - else - { - crc_SetRawProtocolConfig(base, config); - } -} - -void CRC_GetDefaultConfig(crc_config_t *config) -{ - static const crc_config_t crc16ccit = { - CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, - CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, - CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS, - CRC_DRIVER_DEFAULT_CRC_RESULT, - }; - - *config = crc16ccit; -} - -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) -{ - const uint32_t *data32; - - /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((dataSize) && ((uint32_t)data & 3U)) - { - base->ACCESS8BIT.DATALL = *data; - data++; - dataSize--; - } - - /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)data; - while (dataSize >= sizeof(uint32_t)) - { - base->DATA = *data32; - data32++; - dataSize -= sizeof(uint32_t); - } - - data = (const uint8_t *)data32; - - /* 8-bit reads and writes till end of data buffer */ - while (dataSize) - { - base->ACCESS8BIT.DATALL = *data; - data++; - dataSize--; - } -} - -uint32_t CRC_Get32bitResult(CRC_Type *base) -{ - return base->DATA; -} - -uint16_t CRC_Get16bitResult(CRC_Type *base) -{ - uint32_t retval; - uint32_t totr; /* type of transpose read bitfield */ - - retval = base->DATA; - totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; - - /* check transpose type to get 16-bit out of 32-bit register */ - if (totr >= 2U) - { - /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */ - retval &= 0xFFFF0000U; - retval = retval >> 16U; - } - else - { - /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */ - retval &= 0x0000FFFFU; - } - return (uint16_t)retval; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_crc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_crc.h deleted file mode 100644 index 9d76731..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_crc.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup crc - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.0.1. - * - * Current version: 2.0.1 - * - * Change log: - * - Version 2.0.1 - * - move DATA and DATALL macro definition from header file to source file - */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -#ifndef CRC_DRIVER_CUSTOM_DEFAULTS -/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ -#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1 -#endif - -/*! @brief CRC bit width */ -typedef enum _crc_bits -{ - kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */ - kCrcBits32 = 1U /*!< Generate 32-bit CRC code */ -} crc_bits_t; - -/*! @brief CRC result type */ -typedef enum _crc_result -{ - kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum. - Reflect out and final xor protocol features are applied. */ - kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value). - Reflect out and final xor protocol feature are not applied. - Intermediate checksum can be used as a seed for CRC_Init() - to continue adding data to this checksum. */ -} crc_result_t; - -/*! -* @brief CRC protocol configuration. -* -* This structure holds the configuration for the CRC protocol. -* -*/ -typedef struct _crc_config -{ - uint32_t polynomial; /*!< CRC Polynomial, MSBit first. - Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ - uint32_t seed; /*!< Starting checksum value */ - bool reflectIn; /*!< Reflect bits on input. */ - bool reflectOut; /*!< Reflect bits on output. */ - bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ - crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ - crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or - CRC_Get32bitResult() */ -} crc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enables and configures the CRC peripheral module. - * - * This functions enables the clock gate in the Kinetis SIM module for the CRC peripheral. - * It also configures the CRC module and starts checksum computation by writing the seed. - * - * @param base CRC peripheral address. - * @param config CRC module configuration structure - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config); - -/*! - * @brief Disables the CRC peripheral module. - * - * This functions disables the clock gate in the Kinetis SIM module for the CRC peripheral. - * - * @param base CRC peripheral address. - */ -static inline void CRC_Deinit(CRC_Type *base) -{ - /* gate clock */ - CLOCK_DisableClock(kCLOCK_Crc0); -} - -/*! - * @brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * @code - * config->polynomial = 0x1021; - * config->seed = 0xFFFF; - * config->reflectIn = false; - * config->reflectOut = false; - * config->complementChecksum = false; - * config->crcBits = kCrcBits16; - * config->crcResult = kCrcFinalChecksum; - * @endcode - * - * @param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config); - -/*! - * @brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * The configured type of transpose is applied. - * - * @param base CRC peripheral address. - * @param data Input data stream, MSByte in data[0]. - * @param dataSize Size in bytes of the input data buffer. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); - -/*! - * @brief Reads 32-bit checksum from the CRC module. - * - * Reads CRC data register (intermediate or final checksum). - * The configured type of transpose and complement are applied. - * - * @param base CRC peripheral address. - * @return intermediate or final 32-bit checksum, after configured transpose and complement operations. - */ -uint32_t CRC_Get32bitResult(CRC_Type *base); - -/*! - * @brief Reads 16-bit checksum from the CRC module. - * - * Reads CRC data register (intermediate or final checksum). - * The configured type of transpose and complement are applied. - * - * @param base CRC peripheral address. - * @return intermediate or final 16-bit checksum, after configured transpose and complement operations. - */ -uint16_t CRC_Get16bitResult(CRC_Type *base); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_CRC_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dmamux.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dmamux.c deleted file mode 100644 index a288b9f..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dmamux.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dmamux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMAMUX. - * - * @param base DMAMUX peripheral base address. - */ -static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMAMUX instance number to base pointer. */ -static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS; - -/*! @brief Array to map DMAMUX instance number to clock name. */ -static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_DMAMUX_COUNT; instance++) - { - if (s_dmamuxBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_DMAMUX_COUNT); - - return instance; -} - -void DMAMUX_Init(DMAMUX_Type *base) -{ - CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); -} - -void DMAMUX_Deinit(DMAMUX_Type *base) -{ - CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dmamux.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dmamux.h deleted file mode 100644 index 5dce562..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dmamux.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_DMAMUX_H_ -#define _FSL_DMAMUX_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dmamux - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMAMUX driver version 2.0.1. */ -#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMAMUX Initialize and De-initialize - * @{ - */ - -/*! - * @brief Initializes DMAMUX peripheral. - * - * This function ungate the DMAMUX clock. - * - * @param base DMAMUX peripheral base address. - * - */ -void DMAMUX_Init(DMAMUX_Type *base); - -/*! - * @brief Deinitializes DMAMUX peripheral. - * - * This function gate the DMAMUX clock. - * - * @param base DMAMUX peripheral base address. - */ -void DMAMUX_Deinit(DMAMUX_Type *base); - -/* @} */ -/*! - * @name DMAMUX Channel Operation - * @{ - */ - -/*! - * @brief Enable DMAMUX channel. - * - * This function enable DMAMUX channel to work. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; -} - -/*! - * @brief Disable DMAMUX channel. - * - * This function disable DMAMUX channel. - * - * @note User must disable DMAMUX channel before configuring it. - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; -} - -/*! - * @brief Configure DMAMUX channel source. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - * @param source Channel source which is used to trigger DMA transfer. - */ -static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); -} - -#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U -/*! - * @brief Enable DMAMUX period trigger. - * - * This function enable DMAMUX period trigger feature. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; -} - -/*! - * @brief Disable DMAMUX period trigger. - * - * This function disable DMAMUX period trigger. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; -} -#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /* _FSL_DMAMUX_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi.c deleted file mode 100644 index a15314c..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi.c +++ /dev/null @@ -1,2248 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dspi.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.dspi" -#endif - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*dspi_master_isr_t)(SPI_Type *base, dspi_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*dspi_slave_isr_t)(SPI_Type *base, dspi_slave_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Configures the DSPI peripheral chip select polarity. - * - * This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and - * configures the Pcs signal to operate with the desired characteristic. - * - * @param base DSPI peripheral address. - * @param pcs The particular peripheral chip select (parameter value is of type dspi_which_pcs_t) for which we wish to - * apply the active high or active low characteristic. - * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of - * type dspi_pcs_polarity_config_t. - */ -static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh); - -/*! - * @brief Master fill up the TX FIFO with data. - * This is not a public API. - */ -static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle); - -/*! - * @brief Master finish up a transfer. - * It would call back if there is callback function and set the state to idle. - * This is not a public API. - */ -static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle); - -/*! - * @brief Slave fill up the TX FIFO with data. - * This is not a public API. - */ -static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle); - -/*! - * @brief Slave finish up a transfer. - * It would call back if there is callback function and set the state to idle. - * This is not a public API. - */ -static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle); - -/*! - * @brief DSPI common interrupt handler. - * - * @param base DSPI peripheral address. - * @param handle pointer to g_dspiHandle which stores the transfer state. - */ -static void DSPI_CommonIRQHandler(SPI_Type *base, void *param); - -/*! - * @brief Master prepare the transfer. - * Basically it set up dspi_master_handle . - * This is not a public API. - */ -static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ -static const uint32_t s_baudratePrescaler[] = {2, 3, 5, 7}; -static const uint32_t s_baudrateScaler[] = {2, 4, 6, 8, 16, 32, 64, 128, - 256, 512, 1024, 2048, 4096, 8192, 16384, 32768}; - -static const uint32_t s_delayPrescaler[] = {1, 3, 5, 7}; -static const uint32_t s_delayScaler[] = {2, 4, 8, 16, 32, 64, 128, 256, - 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536}; - -/*! @brief Pointers to dspi bases for each instance. */ -static SPI_Type *const s_dspiBases[] = SPI_BASE_PTRS; - -/*! @brief Pointers to dspi IRQ number for each instance. */ -static IRQn_Type const s_dspiIRQ[] = SPI_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to dspi clocks for each instance. */ -static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to dspi handles for each instance. */ -static void *g_dspiHandle[ARRAY_SIZE(s_dspiBases)]; - -/*! @brief Pointer to master IRQ handler for each instance. */ -static dspi_master_isr_t s_dspiMasterIsr; - -/*! @brief Pointer to slave IRQ handler for each instance. */ -static dspi_slave_isr_t s_dspiSlaveIsr; - -/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t g_dspiDummyData[ARRAY_SIZE(s_dspiBases)] = {0}; -/********************************************************************************************************************** - * Code - *********************************************************************************************************************/ -/*! - * brief Get instance number for DSPI module. - * - * param base DSPI peripheral base address. - */ -uint32_t DSPI_GetInstance(SPI_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dspiBases); instance++) - { - if (s_dspiBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dspiBases)); - - return instance; -} - -/*! - * brief Dummy data for each instance. - * - * The purpose of this API is to avoid MISRA rule8.5 : Multiple declarations of - * externally-linked object or function g_dspiDummyData. - * - * param base DSPI peripheral base address. - */ -uint8_t DSPI_GetDummyDataInstance(SPI_Type *base) -{ - uint8_t instance = g_dspiDummyData[DSPI_GetInstance(base)]; - - return instance; -} - -/*! - * brief Set up the dummy data. - * - * param base DSPI peripheral address. - * param dummyData Data to be transferred when tx buffer is NULL. - */ -void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData) -{ - uint32_t instance = DSPI_GetInstance(base); - g_dspiDummyData[instance] = dummyData; -} - -/*! - * brief Initializes the DSPI master. - * - * This function initializes the DSPI master configuration. This is an example use case. - * code - * dspi_master_config_t masterConfig; - * masterConfig.whichCtar = kDSPI_Ctar0; - * masterConfig.ctarConfig.baudRate = 500000000U; - * masterConfig.ctarConfig.bitsPerFrame = 8; - * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - * masterConfig.ctarConfig.direction = kDSPI_MsbFirst; - * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; - * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; - * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; - * masterConfig.whichPcs = kDSPI_Pcs0; - * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow; - * masterConfig.enableContinuousSCK = false; - * masterConfig.enableRxFifoOverWrite = false; - * masterConfig.enableModifiedTimingFormat = false; - * masterConfig.samplePoint = kDSPI_SckToSin0Clock; - * DSPI_MasterInit(base, &masterConfig, srcClock_Hz); - * endcode - * - * param base DSPI peripheral address. - * param masterConfig Pointer to the structure dspi_master_config_t. - * param srcClock_Hz Module source input clock in Hertz. - */ -void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - assert(NULL != masterConfig); - - uint32_t temp; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable DSPI clock */ - CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - DSPI_Enable(base, true); - DSPI_StopTransfer(base); - - DSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); - DSPI_SetMasterSlaveMode(base, kDSPI_Master); - - temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK | - SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK)); - - base->MCR = temp | SPI_MCR_CONT_SCKE(masterConfig->enableContinuousSCK) | - SPI_MCR_MTFE(masterConfig->enableModifiedTimingFormat) | - SPI_MCR_ROOE(masterConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(masterConfig->samplePoint) | - SPI_MCR_DIS_TXF(0U) | SPI_MCR_DIS_RXF(0U); - - if (0U == DSPI_MasterSetBaudRate(base, masterConfig->whichCtar, masterConfig->ctarConfig.baudRate, srcClock_Hz)) - { - assert(false); - } - - temp = base->CTAR[masterConfig->whichCtar] & - ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK); - - base->CTAR[masterConfig->whichCtar] = temp | SPI_CTAR_FMSZ(masterConfig->ctarConfig.bitsPerFrame - 1U) | - SPI_CTAR_CPOL(masterConfig->ctarConfig.cpol) | - SPI_CTAR_CPHA(masterConfig->ctarConfig.cpha) | - SPI_CTAR_LSBFE(masterConfig->ctarConfig.direction); - - (void)DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_PcsToSck, srcClock_Hz, - masterConfig->ctarConfig.pcsToSckDelayInNanoSec); - (void)DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_LastSckToPcs, srcClock_Hz, - masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec); - (void)DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz, - masterConfig->ctarConfig.betweenTransferDelayInNanoSec); - - DSPI_SetDummyData(base, DSPI_DUMMY_DATA); - DSPI_StartTransfer(base); -} - -/*! - * brief Sets the dspi_master_config_t structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit(). - * Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure - * before calling the DSPI_MasterInit(). - * Example: - * code - * dspi_master_config_t masterConfig; - * DSPI_MasterGetDefaultConfig(&masterConfig); - * endcode - * param masterConfig pointer to dspi_master_config_t structure - */ -void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig) -{ - assert(NULL != masterConfig); - - /* Initializes the configure structure to zero. */ - (void)memset(masterConfig, 0, sizeof(*masterConfig)); - - masterConfig->whichCtar = kDSPI_Ctar0; - masterConfig->ctarConfig.baudRate = 500000; - masterConfig->ctarConfig.bitsPerFrame = 8; - masterConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - masterConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - masterConfig->ctarConfig.direction = kDSPI_MsbFirst; - - masterConfig->ctarConfig.pcsToSckDelayInNanoSec = 1000; - masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec = 1000; - masterConfig->ctarConfig.betweenTransferDelayInNanoSec = 1000; - - masterConfig->whichPcs = kDSPI_Pcs0; - masterConfig->pcsActiveHighOrLow = kDSPI_PcsActiveLow; - - masterConfig->enableContinuousSCK = false; - masterConfig->enableRxFifoOverWrite = false; - masterConfig->enableModifiedTimingFormat = false; - masterConfig->samplePoint = kDSPI_SckToSin0Clock; -} - -/*! - * brief DSPI slave configuration. - * - * This function initializes the DSPI slave configuration. This is an example use case. - * code - * dspi_slave_config_t slaveConfig; - * slaveConfig->whichCtar = kDSPI_Ctar0; - * slaveConfig->ctarConfig.bitsPerFrame = 8; - * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - * slaveConfig->enableContinuousSCK = false; - * slaveConfig->enableRxFifoOverWrite = false; - * slaveConfig->enableModifiedTimingFormat = false; - * slaveConfig->samplePoint = kDSPI_SckToSin0Clock; - * DSPI_SlaveInit(base, &slaveConfig); - * endcode - * - * param base DSPI peripheral address. - * param slaveConfig Pointer to the structure dspi_master_config_t. - */ -void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig) -{ - assert(NULL != slaveConfig); - - uint32_t temp = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable DSPI clock */ - CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - DSPI_Enable(base, true); - DSPI_StopTransfer(base); - - DSPI_SetMasterSlaveMode(base, kDSPI_Slave); - - temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK | - SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK)); - - base->MCR = temp | SPI_MCR_CONT_SCKE(slaveConfig->enableContinuousSCK) | - SPI_MCR_MTFE(slaveConfig->enableModifiedTimingFormat) | - SPI_MCR_ROOE(slaveConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(slaveConfig->samplePoint) | - SPI_MCR_DIS_TXF(0U) | SPI_MCR_DIS_RXF(0U); - - DSPI_SetOnePcsPolarity(base, kDSPI_Pcs0, kDSPI_PcsActiveLow); - - temp = base->CTAR[slaveConfig->whichCtar] & - ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK); - - base->CTAR[slaveConfig->whichCtar] = temp | SPI_CTAR_SLAVE_FMSZ(slaveConfig->ctarConfig.bitsPerFrame - 1U) | - SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) | - SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha); - - DSPI_SetDummyData(base, DSPI_DUMMY_DATA); - - DSPI_StartTransfer(base); -} - -/*! - * brief Sets the dspi_slave_config_t structure to a default value. - * - * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit(). - * Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure - * before calling the DSPI_SlaveInit(). - * This is an example. - * code - * dspi_slave_config_t slaveConfig; - * DSPI_SlaveGetDefaultConfig(&slaveConfig); - * endcode - * param slaveConfig Pointer to the dspi_slave_config_t structure. - */ -void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig) -{ - assert(NULL != slaveConfig); - - /* Initializes the configure structure to zero. */ - (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); - - slaveConfig->whichCtar = kDSPI_Ctar0; - slaveConfig->ctarConfig.bitsPerFrame = 8; - slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - - slaveConfig->enableContinuousSCK = false; - slaveConfig->enableRxFifoOverWrite = false; - slaveConfig->enableModifiedTimingFormat = false; - slaveConfig->samplePoint = kDSPI_SckToSin0Clock; -} - -/*! - * brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock. - * param base DSPI peripheral address. - */ -void DSPI_Deinit(SPI_Type *base) -{ - DSPI_StopTransfer(base); - DSPI_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* disable DSPI clock */ - CLOCK_DisableClock(s_dspiClock[DSPI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh) -{ - uint32_t temp; - - temp = base->MCR; - - if (activeLowOrHigh == kDSPI_PcsActiveLow) - { - temp |= SPI_MCR_PCSIS(pcs); - } - else - { - temp &= ~SPI_MCR_PCSIS(pcs); - } - - base->MCR = temp; -} - -/*! - * brief Sets the DSPI baud rate in bits per second. - * - * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without - * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the - * caller also provide the frequency of the module source clock (in Hertz). - * - * param base DSPI peripheral address. - * param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t - * param baudRate_Bps The desired baud rate in bits per second - * param srcClock_Hz Module source input clock in Hertz - * return The actual calculated baud rate - */ -uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, - dspi_ctar_selection_t whichCtar, - uint32_t baudRate_Bps, - uint32_t srcClock_Hz) -{ - /* for master mode configuration, if slave mode detected, return 0*/ - if (!DSPI_IsMaster(base)) - { - return 0; - } - uint32_t temp; - uint32_t prescaler, bestPrescaler; - uint32_t scaler, bestScaler; - uint32_t dbr, bestDbr; - uint32_t realBaudrate, bestBaudrate; - uint32_t diff, min_diff; - uint32_t baudrate = baudRate_Bps; - - /* find combination of prescaler and scaler resulting in baudrate closest to the requested value */ - min_diff = 0xFFFFFFFFU; - bestPrescaler = 0; - bestScaler = 0; - bestDbr = 1; - bestBaudrate = 0; /* required to avoid compilation warning */ - - /* In all for loops, if min_diff = 0, the exit for loop*/ - for (prescaler = 0U; prescaler < 4U; prescaler++) - { - for (scaler = 0U; scaler < 16U; scaler++) - { - for (dbr = 1U; dbr < 3U; dbr++) - { - realBaudrate = ((srcClock_Hz * dbr) / (s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler]))); - - /* calculate the baud rate difference based on the conditional statement that states that the calculated - * baud rate must not exceed the desired baud rate. - */ - if (baudrate >= realBaudrate) - { - diff = baudrate - realBaudrate; - if (min_diff > diff) - { - /* a better match found */ - min_diff = diff; - bestPrescaler = prescaler; - bestScaler = scaler; - bestBaudrate = realBaudrate; - bestDbr = dbr; - } - } - if (0U == min_diff) - { - break; - } - } - - if (0U == min_diff) - { - break; - } - } - if (0U == min_diff) - { - break; - } - } - - /* write the best dbr, prescalar, and baud rate scalar to the CTAR */ - temp = base->CTAR[whichCtar] & ~(SPI_CTAR_DBR_MASK | SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK); - - base->CTAR[whichCtar] = temp | ((bestDbr - 1U) << SPI_CTAR_DBR_SHIFT) | (bestPrescaler << SPI_CTAR_PBR_SHIFT) | - (bestScaler << SPI_CTAR_BR_SHIFT); - - /* return the actual calculated baud rate */ - return bestBaudrate; -} - -/*! - * brief Manually configures the delay prescaler and scaler for a particular CTAR. - * - * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar - * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT). - * - * These delay names are available in the type dspi_delay_type_t. - * - * The user passes the delay to the configuration along with the prescaler and scaler value. - * This allows the user to directly set the prescaler/scaler values if pre-calculated or - * to manually increment either value. - * - * param base DSPI peripheral address. - * param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. - * param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3). - * param scaler The scaler delay value (can be any integer between 0 to 15). - * param whichDelay The desired delay to configure; must be of type dspi_delay_type_t - */ -void DSPI_MasterSetDelayScaler( - SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay) -{ - /* these settings are only relevant in master mode */ - if (DSPI_IsMaster(base)) - { - switch (whichDelay) - { - case kDSPI_PcsToSck: - base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PCSSCK_MASK) & (~SPI_CTAR_CSSCK_MASK)) | - SPI_CTAR_PCSSCK(prescaler) | SPI_CTAR_CSSCK(scaler); - break; - case kDSPI_LastSckToPcs: - base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PASC_MASK) & (~SPI_CTAR_ASC_MASK)) | - SPI_CTAR_PASC(prescaler) | SPI_CTAR_ASC(scaler); - break; - case kDSPI_BetweenTransfer: - base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PDT_MASK) & (~SPI_CTAR_DT_MASK)) | - SPI_CTAR_PDT(prescaler) | SPI_CTAR_DT(scaler); - break; - default: - /* All cases have been listed above, the default clause should not be reached. */ - assert(false); - break; - } - } -} - -/*! - * brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. - * - * This function calculates the values for the following. - * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or - * After SCK delay pre-scalar (PASC) and scalar (ASC), or - * Delay after transfer pre-scalar (PDT) and scalar (DT). - * - * These delay names are available in the type dspi_delay_type_t. - * - * The user passes which delay to configure along with the desired delay value in nanoseconds. The function - * calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact - * delay match may not be possible. In this case, the closest match is calculated without going below the desired - * delay value input. - * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum - * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay - * input. - * - * param base DSPI peripheral address. - * param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. - * param whichDelay The desired delay to configure, must be of type dspi_delay_type_t - * param srcClock_Hz Module source input clock in Hertz - * param delayTimeInNanoSec The desired delay value in nanoseconds. - * return The actual calculated delay value. - */ -uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, - dspi_ctar_selection_t whichCtar, - dspi_delay_type_t whichDelay, - uint32_t srcClock_Hz, - uint32_t delayTimeInNanoSec) -{ - /* for master mode configuration, if slave mode detected, return 0 */ - if (!DSPI_IsMaster(base)) - { - return 0; - } - - uint32_t prescaler, bestPrescaler; - uint32_t scaler, bestScaler; - uint32_t realDelay, bestDelay; - uint32_t diff, min_diff; - uint32_t initialDelayNanoSec; - - /* find combination of prescaler and scaler resulting in the delay closest to the - * requested value - */ - min_diff = 0xFFFFFFFFU; - /* Initialize prescaler and scaler to their max values to generate the max delay */ - bestPrescaler = 0x3; - bestScaler = 0xF; - bestDelay = (((1000000000U * 4U) / srcClock_Hz) * s_delayPrescaler[bestPrescaler] * s_delayScaler[bestScaler]) / 4U; - - /* First calculate the initial, default delay */ - initialDelayNanoSec = 1000000000U / srcClock_Hz * 2U; - - /* If the initial, default delay is already greater than the desired delay, then - * set the delays to their initial value (0) and return the delay. In other words, - * there is no way to decrease the delay value further. - */ - if (initialDelayNanoSec >= delayTimeInNanoSec) - { - DSPI_MasterSetDelayScaler(base, whichCtar, 0, 0, whichDelay); - return initialDelayNanoSec; - } - - /* In all for loops, if min_diff = 0, the exit for loop */ - for (prescaler = 0; prescaler < 4U; prescaler++) - { - for (scaler = 0; scaler < 16U; scaler++) - { - realDelay = ((4000000000U / srcClock_Hz) * s_delayPrescaler[prescaler] * s_delayScaler[scaler]) / 4U; - - /* calculate the delay difference based on the conditional statement - * that states that the calculated delay must not be less then the desired delay - */ - if (realDelay >= delayTimeInNanoSec) - { - diff = realDelay - delayTimeInNanoSec; - if (min_diff > diff) - { - /* a better match found */ - min_diff = diff; - bestPrescaler = prescaler; - bestScaler = scaler; - bestDelay = realDelay; - } - } - - if (0U == min_diff) - { - break; - } - } - if (0U == min_diff) - { - break; - } - } - - /* write the best dbr, prescalar, and baud rate scalar to the CTAR */ - DSPI_MasterSetDelayScaler(base, whichCtar, bestPrescaler, bestScaler, whichDelay); - - /* return the actual calculated baud rate */ - return bestDelay; -} - -/*! - * brief Sets the dspi_command_data_config_t structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx(). - * Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or modify the structure - * before calling the DSPI_MasterWrite_xx(). - * This is an example. - * code - * dspi_command_data_config_t command; - * DSPI_GetDefaultDataCommandConfig(&command); - * endcode - * param command Pointer to the dspi_command_data_config_t structure. - */ -void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command) -{ - assert(NULL != command); - - /* Initializes the configure structure to zero. */ - (void)memset(command, 0, sizeof(*command)); - - command->isPcsContinuous = false; - command->whichCtar = kDSPI_Ctar0; - command->whichPcs = kDSPI_Pcs0; - command->isEndOfQueue = false; - command->clearTransferCount = false; -} - -/*! - * brief Writes data into the data buffer master mode and waits till complete to return. - * - * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion - * provides characteristics of the data, such as the optional continuous chip select - * operation between transfers, the desired Clock and Transfer Attributes register to use for the - * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current - * transfer is the last in the queue, and whether to clear the transfer count (normally needed when - * sending the first frame of a data packet). This is an example. - * code - * dspi_command_config_t commandConfig; - * commandConfig.isPcsContinuous = true; - * commandConfig.whichCtar = kDSPICtar0; - * commandConfig.whichPcs = kDSPIPcs1; - * commandConfig.clearTransferCount = false; - * commandConfig.isEndOfQueue = false; - * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord); - * endcode - * - * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be - * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol, - * the received data is available when the transmit completes. - * - * param base DSPI peripheral address. - * param command Pointer to the command structure. - * param data The data word to be sent. - */ -void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) -{ - assert(NULL != command); - - /* First, clear Transmit Complete Flag (TCF) */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxCompleteFlag); - - while (0U == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - } - - base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | - SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | - SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - /* Wait till TCF sets */ - while (0U == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxCompleteFlag)) - { - } -} - -/*! - * brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data - * buffer master mode and waits till complete to return. - * - * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total - * 32-bit word - * as the data to send. - * The command portion provides characteristics of the data, such as the optional continuous chip select operation - * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the - * desired PCS - * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the - * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for - * appending this command with the data to send. This is an example: - * code - * dataWord = <16-bit command> | <16-bit data>; - * DSPI_MasterWriteCommandDataBlocking(base, dataWord); - * endcode - * - * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be - * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). - * Because the SPI is a synchronous protocol, the received data is available when the transmit completes. - * - * For a blocking polling transfer, see methods below. - * Option 1: - * uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command); - * uint32_t data0 = command_to_send | data_need_to_send_0; - * uint32_t data1 = command_to_send | data_need_to_send_1; - * uint32_t data2 = command_to_send | data_need_to_send_2; - * - * DSPI_MasterWriteCommandDataBlocking(base,data0); - * DSPI_MasterWriteCommandDataBlocking(base,data1); - * DSPI_MasterWriteCommandDataBlocking(base,data2); - * - * Option 2: - * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0); - * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1); - * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2); - * - * param base DSPI peripheral address. - * param data The data word (command and data combined) to be sent. - */ -void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data) -{ - /* First, clear Transmit Complete Flag (TCF) */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxCompleteFlag); - - while (0U == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - } - - base->PUSHR = data; - - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - /* Wait till TCF sets */ - while (0U == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxCompleteFlag)) - { - } -} - -/*! - * brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns. - * - * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data - * into data register, and finally waits until the data is transmitted. - * - * param base DSPI peripheral address. - * param data The data to send. - */ -void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data) -{ - /* First, clear Transmit Complete Flag (TCF) */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxCompleteFlag); - - while (0U == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - } - - base->PUSHR_SLAVE = data; - - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - /* Wait till TCF sets */ - while (0U == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxCompleteFlag)) - { - } -} - -/*! - * brief Enables the DSPI interrupts. - * - * This function configures the various interrupt masks of the DSPI. The parameters are a base and an interrupt mask. - * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request. - * Do not use this API(write to RSER register) while DSPI is in running state. - * - * code - * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); - * endcode - * - * param base DSPI peripheral address. - * param mask The interrupt mask; use the enum _dspi_interrupt_enable. - */ -void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask) -{ - if (0U != (mask & SPI_RSER_TFFF_RE_MASK)) - { - base->RSER &= ~SPI_RSER_TFFF_DIRS_MASK; - } - if (0U != (mask & SPI_RSER_RFDF_RE_MASK)) - { - base->RSER &= ~SPI_RSER_RFDF_DIRS_MASK; - } - base->RSER |= mask; -} - -/*Transactional APIs -- Master*/ - -/*! - * brief Initializes the DSPI master handle. - * - * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a - * specified DSPI instance, call this API once to get the initialized handle. - * - * param base DSPI peripheral base address. - * param handle DSPI handle pointer to dspi_master_handle_t. - * param callback DSPI callback. - * param userData Callback function parameter. - */ -void DSPI_MasterTransferCreateHandle(SPI_Type *base, - dspi_master_handle_t *handle, - dspi_master_transfer_callback_t callback, - void *userData) -{ - assert(NULL != handle); - - /* Zero the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - g_dspiHandle[DSPI_GetInstance(base)] = handle; - - handle->callback = callback; - handle->userData = userData; -} - -/*! - * brief DSPI master transfer data using polling. - * - * This function transfers data using polling. This is a blocking function, which does not return until all transfers - * have been completed. - * - * param base DSPI peripheral base address. - * param transfer Pointer to the dspi_transfer_t structure. - * return status of status_t. - */ -status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer) -{ - assert(NULL != transfer); - - uint16_t wordToSend = 0; - uint16_t wordReceived = 0; - uint8_t dummyData = DSPI_GetDummyDataInstance(base); - uint8_t bitsPerFrame; - - uint32_t command; - uint32_t lastCommand; - - uint8_t *txData; - uint8_t *rxData; - uint32_t remainingSendByteCount; - uint32_t remainingReceiveByteCount; - - uint32_t fifoSize; - uint32_t tmpMCR = 0; - dspi_command_data_config_t commandStruct; - - /* If the transfer count is zero, then return immediately.*/ - if (transfer->dataSize == 0U) - { - return kStatus_InvalidArgument; - } - - DSPI_StopTransfer(base); - DSPI_DisableInterrupts(base, (uint32_t)kDSPI_AllInterruptEnable); - DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag); - - /*Calculate the command and lastCommand*/ - commandStruct.whichPcs = - (dspi_which_pcs_t)((uint32_t)1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); - commandStruct.isEndOfQueue = false; - commandStruct.clearTransferCount = false; - commandStruct.whichCtar = - (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); - commandStruct.isPcsContinuous = - (0U != (transfer->configFlags & (uint32_t)kDSPI_MasterPcsContinuous)) ? true : false; - - command = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - commandStruct.isEndOfQueue = true; - commandStruct.isPcsContinuous = - (0U != (transfer->configFlags & (uint32_t)kDSPI_MasterActiveAfterTransfer)) ? true : false; - lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - /*Calculate the bitsPerFrame*/ - bitsPerFrame = (uint8_t)(((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1U); - - txData = transfer->txData; - rxData = transfer->rxData; - remainingSendByteCount = transfer->dataSize; - remainingReceiveByteCount = transfer->dataSize; - - tmpMCR = base->MCR; - if ((0U != (tmpMCR & SPI_MCR_DIS_RXF_MASK)) || (0U != (tmpMCR & SPI_MCR_DIS_TXF_MASK))) - { - fifoSize = 1U; - } - else - { - fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); - } - - DSPI_StartTransfer(base); - - if (bitsPerFrame <= 8U) - { - while (remainingSendByteCount > 0U) - { - if (remainingSendByteCount == 1U) - { - while (0U == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - } - - if (txData != NULL) - { - base->PUSHR = (*txData) | (lastCommand); - txData++; - } - else - { - base->PUSHR = (lastCommand) | (dummyData); - } - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - remainingSendByteCount--; - - while (remainingReceiveByteCount > 0U) - { - if ((uint32_t)kDSPI_RxFifoDrainRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_RxFifoDrainRequestFlag)) - { - if (rxData != NULL) - { - /* Read data from POPR*/ - *(rxData) = (uint8_t)DSPI_ReadData(base); - rxData++; - } - else - { - (void)DSPI_ReadData(base); - } - remainingReceiveByteCount--; - - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_RxFifoDrainRequestFlag); - } - } - } - else - { - /*Wait until Tx Fifo is not full*/ - while (0U == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - } - if (txData != NULL) - { - base->PUSHR = command | (uint16_t)(*txData); - txData++; - } - else - { - base->PUSHR = command | dummyData; - } - remainingSendByteCount--; - - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - while ((remainingReceiveByteCount - remainingSendByteCount) >= fifoSize) - { - if ((uint32_t)kDSPI_RxFifoDrainRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_RxFifoDrainRequestFlag)) - { - if (rxData != NULL) - { - *(rxData) = (uint8_t)DSPI_ReadData(base); - rxData++; - } - else - { - (void)DSPI_ReadData(base); - } - remainingReceiveByteCount--; - - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_RxFifoDrainRequestFlag); - } - } - } - } - } - else - { - while (remainingSendByteCount > 0U) - { - if (remainingSendByteCount <= 2U) - { - while (0U == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - } - - if (txData != NULL) - { - wordToSend = *(txData); - ++txData; - - if (remainingSendByteCount > 1U) - { - wordToSend |= (uint16_t)(*(txData)) << 8U; - ++txData; - } - } - else - { - wordToSend = dummyData; - } - - base->PUSHR = lastCommand | wordToSend; - - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - remainingSendByteCount = 0; - - while (remainingReceiveByteCount > 0U) - { - if ((uint32_t)kDSPI_RxFifoDrainRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_RxFifoDrainRequestFlag)) - { - wordReceived = (uint16_t)DSPI_ReadData(base); - - if (remainingReceiveByteCount != 1U) - { - if (rxData != NULL) - { - *(rxData) = (uint8_t)wordReceived; - ++rxData; - *(rxData) = (uint8_t)(wordReceived >> 8U); - ++rxData; - } - remainingReceiveByteCount -= 2U; - } - else - { - if (rxData != NULL) - { - *(rxData) = (uint8_t)wordReceived; - ++rxData; - } - remainingReceiveByteCount--; - } - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_RxFifoDrainRequestFlag); - } - } - } - else - { - /*Wait until Tx Fifo is not full*/ - while (0U == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - } - - if (txData != NULL) - { - wordToSend = *(txData); - ++txData; - wordToSend |= (uint16_t)(*(txData)) << 8U; - ++txData; - } - else - { - wordToSend = dummyData; - } - base->PUSHR = command | wordToSend; - remainingSendByteCount -= 2U; - - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - while (((remainingReceiveByteCount - remainingSendByteCount) / 2U) >= fifoSize) - { - if ((uint32_t)kDSPI_RxFifoDrainRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_RxFifoDrainRequestFlag)) - { - wordReceived = (uint16_t)DSPI_ReadData(base); - - if (rxData != NULL) - { - *rxData = (uint8_t)wordReceived; - ++rxData; - *rxData = (uint8_t)(wordReceived >> 8U); - ++rxData; - } - remainingReceiveByteCount -= 2U; - - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_RxFifoDrainRequestFlag); - } - } - } - } - } - - return kStatus_Success; -} - -static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) -{ - assert(NULL != handle); - assert(NULL != transfer); - - uint32_t tmpMCR = 0; - dspi_command_data_config_t commandStruct = {false, kDSPI_Ctar0, kDSPI_Pcs0, false, false}; - - DSPI_StopTransfer(base); - DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag); - - commandStruct.whichPcs = - (dspi_which_pcs_t)((uint32_t)1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); - commandStruct.isEndOfQueue = false; - commandStruct.clearTransferCount = false; - commandStruct.whichCtar = - (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); - commandStruct.isPcsContinuous = - (0U != (transfer->configFlags & (uint32_t)kDSPI_MasterPcsContinuous)) ? true : false; - handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - commandStruct.isEndOfQueue = true; - commandStruct.isPcsContinuous = - (0U != (transfer->configFlags & (uint32_t)kDSPI_MasterActiveAfterTransfer)) ? true : false; - handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1U; - - tmpMCR = base->MCR; - if ((0U != (tmpMCR & SPI_MCR_DIS_RXF_MASK)) || (0U != (tmpMCR & SPI_MCR_DIS_TXF_MASK))) - { - handle->fifoSize = 1; - } - else - { - handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); - } - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->remainingSendByteCount = transfer->dataSize; - handle->remainingReceiveByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; -} - -/*! - * brief DSPI master transfer data using interrupts. - * - * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all - * data is transferred, the callback function is called. - - * param base DSPI peripheral base address. - * param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - * param transfer Pointer to the dspi_transfer_t structure. - * return status of status_t. - */ -status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) -{ - assert(NULL != handle); - assert(NULL != transfer); - - /* If the transfer count is zero, then return immediately.*/ - if (transfer->dataSize == 0U) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == (uint8_t)kDSPI_Busy) - { - return kStatus_DSPI_Busy; - } - - handle->state = (uint8_t)kDSPI_Busy; - - /* Disable the NVIC for DSPI peripheral. */ - (void)DisableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); - - DSPI_MasterTransferPrepare(base, handle, transfer); - - /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt - * Since SPI is a synchronous interface, we only need to enable the RX interrupt. - * The IRQ handler will get the status of RX and TX interrupt flags. - */ - s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ; - - DSPI_EnableInterrupts(base, (uint32_t)kDSPI_RxFifoDrainRequestInterruptEnable); - DSPI_StartTransfer(base); - - /* Fill up the Tx FIFO to trigger the transfer. */ - DSPI_MasterTransferFillUpTxFifo(base, handle); - - /* Enable the NVIC for DSPI peripheral. */ - (void)EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); - - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for DSPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer will be half-duplex, - * users can set transmit first or receive first. - * - * param base DSPI base pointer - * param xfer pointer to dspi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t DSPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, dspi_half_duplex_transfer_t *xfer) -{ - assert(NULL != xfer); - - dspi_transfer_t tempXfer = {0}; - status_t status; - - if (true == xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (true == xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kDSPI_MasterActiveAfterTransfer; - } - else - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kDSPI_MasterActiveAfterTransfer); - } - - status = DSPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (true == xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - /* DSPI transfer blocking. */ - status = DSPI_MasterTransferBlocking(base, &tempXfer); - - return status; -} - -/*! - * brief Performs a non-blocking DSPI interrupt transfer. - * - * This function transfers data using interrupts, the transfer mechanism is half-duplex. This is a non-blocking - * function, - * which returns right away. When all data is transferred, the callback function is called. - * - * param base DSPI peripheral base address. - * param handle pointer to dspi_master_handle_t structure which stores the transfer state - * param xfer pointer to dspi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t DSPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - dspi_master_handle_t *handle, - dspi_half_duplex_transfer_t *xfer) -{ - assert(NULL != xfer); - assert(NULL != handle); - dspi_transfer_t tempXfer = {0}; - status_t status; - - if (true == xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (true == xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kDSPI_MasterActiveAfterTransfer; - } - else - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kDSPI_MasterActiveAfterTransfer); - } - - status = DSPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (true == xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = DSPI_MasterTransferNonBlocking(base, handle, &tempXfer); - - return status; -} - -/*! - * brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * param base DSPI peripheral base address. - * param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - * param count The number of bytes transferred by using the non-blocking transaction. - * return status of status_t. - */ -status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint8_t)kDSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->remainingReceiveByteCount; - return kStatus_Success; -} - -static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupt requests*/ - DSPI_DisableInterrupts( - base, ((uint32_t)kDSPI_RxFifoDrainRequestInterruptEnable | (uint32_t)kDSPI_TxFifoFillRequestInterruptEnable)); - - status_t status = 0; - if (handle->state == (uint8_t)kDSPI_Error) - { - status = kStatus_DSPI_Error; - } - else - { - status = kStatus_Success; - } - - if ((NULL != handle->callback) && ((uint8_t)kDSPI_Idle != handle->state)) - { - handle->state = (uint8_t)kDSPI_Idle; - handle->callback(base, handle, status, handle->userData); - } -} - -static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle) -{ - assert(NULL != handle); - - uint16_t wordToSend = 0; - uint8_t dummyData = DSPI_GetDummyDataInstance(base); - size_t tmpRemainingSendByteCount = handle->remainingSendByteCount; - size_t tmpRemainingReceiveByteCount = handle->remainingReceiveByteCount; - uint8_t tmpFifoSize = handle->fifoSize; - - /* If bits/frame is greater than one byte */ - if (handle->bitsPerFrame > 8U) - { - /* Fill the fifo until it is full or until the send word count is 0 or until the difference - * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth. - * The reason for checking the difference is to ensure we only send as much as the - * RX FIFO can receive. - * For this case where bitsPerFrame > 8, each entry in the FIFO contains 2 bytes of the - * send data, hence the difference between the remainingReceiveByteCount and - * remainingSendByteCount must be divided by 2 to convert this difference into a - * 16-bit (2 byte) value. - */ - while ((0U != (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) && - (((tmpRemainingReceiveByteCount - tmpRemainingSendByteCount) / 2U) < tmpFifoSize)) - { - if (handle->remainingSendByteCount <= 2U) - { - if (NULL != handle->txData) - { - if (handle->remainingSendByteCount == 1U) - { - wordToSend = *(handle->txData); - } - else - { - wordToSend = *(handle->txData); - ++handle->txData; /* increment to next data byte */ - wordToSend |= (uint16_t)(*(handle->txData)) << 8U; - } - } - else - { - wordToSend = dummyData; - } - handle->remainingSendByteCount = 0; - base->PUSHR = handle->lastCommand | wordToSend; - } - /* For all words except the last word */ - else - { - if (NULL != handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; /* increment to next data byte */ - wordToSend |= (unsigned)(*(handle->txData)) << 8U; - ++handle->txData; /* increment to next data byte */ - } - else - { - wordToSend = dummyData; - } - handle->remainingSendByteCount -= 2U; /* decrement remainingSendByteCount by 2 */ - base->PUSHR = handle->command | wordToSend; - } - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - /* exit loop if send count is zero, else update local variables for next loop. - * If this is the first time write to the PUSHR, write only once. - */ - tmpRemainingSendByteCount = handle->remainingSendByteCount; - if ((tmpRemainingSendByteCount == 0U) || (tmpRemainingSendByteCount == handle->totalByteCount - 2U)) - { - break; - } - tmpRemainingReceiveByteCount = handle->remainingReceiveByteCount; - tmpRemainingSendByteCount = handle->remainingSendByteCount; - tmpFifoSize = handle->fifoSize; - } /* End of TX FIFO fill while loop */ - } - /* Optimized for bits/frame less than or equal to one byte. */ - else - { - /* Fill the fifo until it is full or until the send word count is 0 or until the difference - * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth. - * The reason for checking the difference is to ensure we only send as much as the - * RX FIFO can receive. - */ - while ((0U != (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) && - ((tmpRemainingReceiveByteCount - tmpRemainingSendByteCount) < tmpFifoSize)) - { - if (NULL != handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; - } - else - { - wordToSend = dummyData; - } - - if (handle->remainingSendByteCount == 1U) - { - base->PUSHR = handle->lastCommand | wordToSend; - } - else - { - base->PUSHR = handle->command | wordToSend; - } - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - --handle->remainingSendByteCount; - - /* exit loop if send count is zero, else update local variables for next loop - * If this is the first time write to the PUSHR, write only once. - */ - tmpRemainingSendByteCount = handle->remainingSendByteCount; - if ((tmpRemainingSendByteCount == 0U) || (tmpRemainingSendByteCount == (handle->totalByteCount - 1U))) - { - break; - } - tmpRemainingReceiveByteCount = handle->remainingReceiveByteCount; - tmpRemainingSendByteCount = handle->remainingSendByteCount; - tmpFifoSize = handle->fifoSize; - } - } -} - -/*! - * brief DSPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * param base DSPI peripheral base address. - * param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - */ -void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle) -{ - assert(NULL != handle); - - DSPI_StopTransfer(base); - - /* Disable interrupt requests*/ - DSPI_DisableInterrupts( - base, ((uint32_t)kDSPI_RxFifoDrainRequestInterruptEnable | (uint32_t)kDSPI_TxFifoFillRequestInterruptEnable)); - - handle->state = (uint8_t)kDSPI_Idle; -} - -/*! - * brief DSPI Master IRQ handler function. - * - * This function processes the DSPI transmit and receive IRQ. - - * param base DSPI peripheral base address. - * param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - */ -void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle) -{ - assert(NULL != handle); - - /* RECEIVE IRQ handler: Check read buffer only if there are remaining bytes to read. */ - if (0U != (handle->remainingReceiveByteCount)) - { - /* Check read buffer.*/ - uint16_t wordReceived; /* Maximum supported data bit length in master mode is 16-bits */ - - /* If bits/frame is greater than one byte */ - if (handle->bitsPerFrame > 8U) - { - while ((uint32_t)kDSPI_RxFifoDrainRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_RxFifoDrainRequestFlag)) - { - wordReceived = (uint16_t)DSPI_ReadData(base); - /* clear the rx fifo drain request, needed for non-DMA applications as this flag - * will remain set even if the rx fifo is empty. By manually clearing this flag, it - * either remain clear if no more data is in the fifo, or it will set if there is - * more data in the fifo. - */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_RxFifoDrainRequestFlag); - - /* Store read bytes into rx buffer only if a buffer pointer was provided */ - if (NULL != handle->rxData) - { - /* For the last word received, if there is an extra byte due to the odd transfer - * byte count, only save the last byte and discard the upper byte - */ - if (handle->remainingReceiveByteCount == 1U) - { - *handle->rxData = (uint8_t)wordReceived; /* Write first data byte */ - --handle->remainingReceiveByteCount; - } - else - { - *handle->rxData = (uint8_t)wordReceived; /* Write first data byte */ - ++handle->rxData; /* increment to next data byte */ - *handle->rxData = (uint8_t)(wordReceived >> 8U); /* Write second data byte */ - ++handle->rxData; /* increment to next data byte */ - handle->remainingReceiveByteCount -= 2U; - } - } - else - { - if (handle->remainingReceiveByteCount == 1U) - { - --handle->remainingReceiveByteCount; - } - else - { - handle->remainingReceiveByteCount -= 2U; - } - } - if (handle->remainingReceiveByteCount == 0U) - { - break; - } - } /* End of RX FIFO drain while loop */ - } - /* Optimized for bits/frame less than or equal to one byte. */ - else - { - while ((uint32_t)kDSPI_RxFifoDrainRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_RxFifoDrainRequestFlag)) - { - wordReceived = (uint16_t)DSPI_ReadData(base); - /* clear the rx fifo drain request, needed for non-DMA applications as this flag - * will remain set even if the rx fifo is empty. By manually clearing this flag, it - * either remain clear if no more data is in the fifo, or it will set if there is - * more data in the fifo. - */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_RxFifoDrainRequestFlag); - - /* Store read bytes into rx buffer only if a buffer pointer was provided */ - if (NULL != handle->rxData) - { - *handle->rxData = (uint8_t)wordReceived; - ++handle->rxData; - } - - --handle->remainingReceiveByteCount; - - if (handle->remainingReceiveByteCount == 0U) - { - break; - } - } /* End of RX FIFO drain while loop */ - } - } - - /* Check write buffer. We always have to send a word in order to keep the transfer - * moving. So if the caller didn't provide a send buffer, we just send a zero. - */ - if (0U != (handle->remainingSendByteCount)) - { - DSPI_MasterTransferFillUpTxFifo(base, handle); - } - - /* Check if we're done with this transfer.*/ - if (handle->remainingSendByteCount == 0U) - { - if (handle->remainingReceiveByteCount == 0U) - { - /* Complete the transfer and disable the interrupts */ - DSPI_MasterTransferComplete(base, handle); - } - } -} - -/*Transactional APIs -- Slave*/ -/*! - * brief Initializes the DSPI slave handle. - * - * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a - * specified DSPI instance, call this API once to get the initialized handle. - * - * param handle DSPI handle pointer to the dspi_slave_handle_t. - * param base DSPI peripheral base address. - * param callback DSPI callback. - * param userData Callback function parameter. - */ -void DSPI_SlaveTransferCreateHandle(SPI_Type *base, - dspi_slave_handle_t *handle, - dspi_slave_transfer_callback_t callback, - void *userData) -{ - assert(NULL != handle); - - /* Zero the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - g_dspiHandle[DSPI_GetInstance(base)] = handle; - - handle->callback = callback; - handle->userData = userData; -} - -/*! - * brief DSPI slave transfers data using an interrupt. - * - * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all - * data is transferred, the callback function is called. - * - * param base DSPI peripheral base address. - * param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. - * param transfer Pointer to the dspi_transfer_t structure. - * return status of status_t. - */ -status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer) -{ - assert(NULL != handle); - assert(NULL != transfer); - - /* If receive length is zero */ - if (transfer->dataSize == 0U) - { - return kStatus_InvalidArgument; - } - - /* If both send buffer and receive buffer is null */ - if ((NULL == (transfer->txData)) && (NULL == (transfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == (uint8_t)kDSPI_Busy) - { - return kStatus_DSPI_Busy; - } - handle->state = (uint8_t)kDSPI_Busy; - - /* Enable the NVIC for DSPI peripheral. */ - (void)EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); - - /* Store transfer information */ - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->remainingSendByteCount = transfer->dataSize; - handle->remainingReceiveByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - handle->errorCount = 0; - - uint8_t whichCtar = (uint8_t)((transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT); - handle->bitsPerFrame = - (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1U; - - DSPI_StopTransfer(base); - - DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag); - - s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ; - - /* Enable RX FIFO drain request, the slave only use this interrupt */ - DSPI_EnableInterrupts(base, (uint32_t)kDSPI_RxFifoDrainRequestInterruptEnable); - - if (NULL != handle->rxData) - { - /* RX FIFO overflow request enable */ - DSPI_EnableInterrupts(base, (uint32_t)kDSPI_RxFifoOverflowInterruptEnable); - } - if (NULL != handle->txData) - { - /* TX FIFO underflow request enable */ - DSPI_EnableInterrupts(base, (uint32_t)kDSPI_TxFifoUnderflowInterruptEnable); - } - - DSPI_StartTransfer(base); - - /* Prepare data to transmit */ - DSPI_SlaveTransferFillUpTxFifo(base, handle); - - return kStatus_Success; -} - -/*! - * brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * param base DSPI peripheral base address. - * param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - * param count The number of bytes transferred by using the non-blocking transaction. - * return status of status_t. - */ -status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint8_t)kDSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->remainingReceiveByteCount; - return kStatus_Success; -} - -static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle) -{ - assert(NULL != handle); - - uint16_t transmitData = 0; - uint8_t dummyPattern = DSPI_GetDummyDataInstance(base); - - /* Service the transmitter, if transmit buffer provided, transmit the data, - * else transmit dummy pattern - */ - while ((uint32_t)kDSPI_TxFifoFillRequestFlag == (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - /* Transmit data */ - if (handle->remainingSendByteCount > 0U) - { - /* Have data to transmit, update the transmit data and push to FIFO */ - if (handle->bitsPerFrame <= 8U) - { - /* bits/frame is 1 byte */ - if (NULL != handle->txData) - { - /* Update transmit data and transmit pointer */ - transmitData = *handle->txData; - handle->txData++; - } - else - { - transmitData = dummyPattern; - } - - /* Decrease remaining dataSize */ - --handle->remainingSendByteCount; - } - /* bits/frame is 2 bytes */ - else - { - /* With multibytes per frame transmission, the transmit frame contains data from - * transmit buffer until sent dataSize matches user request. Other bytes will set to - * dummy pattern value. - */ - if (NULL != handle->txData) - { - /* Update first byte of transmit data and transmit pointer */ - transmitData = *handle->txData; - handle->txData++; - - if (handle->remainingSendByteCount == 1U) - { - /* Decrease remaining dataSize */ - --handle->remainingSendByteCount; - /* Update second byte of transmit data to second byte of dummy pattern */ - transmitData = transmitData | (uint16_t)(((uint16_t)dummyPattern) << 8U); - } - else - { - /* Update second byte of transmit data and transmit pointer */ - transmitData = transmitData | (uint16_t)((uint16_t)(*handle->txData) << 8U); - handle->txData++; - handle->remainingSendByteCount -= 2U; - } - } - else - { - if (handle->remainingSendByteCount == 1U) - { - --handle->remainingSendByteCount; - } - else - { - handle->remainingSendByteCount -= 2U; - } - transmitData = (uint16_t)((uint16_t)(dummyPattern) << 8U) | dummyPattern; - } - } - } - else - { - break; - } - - /* Write the data to the DSPI data register */ - base->PUSHR_SLAVE = transmitData; - - /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - } -} - -static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupt requests */ - DSPI_DisableInterrupts( - base, ((uint32_t)kDSPI_TxFifoUnderflowInterruptEnable | (uint32_t)kDSPI_TxFifoFillRequestInterruptEnable | - (uint32_t)kDSPI_RxFifoOverflowInterruptEnable | (uint32_t)kDSPI_RxFifoDrainRequestInterruptEnable)); - - /* The transfer is complete. */ - handle->txData = NULL; - handle->rxData = NULL; - handle->remainingReceiveByteCount = 0; - handle->remainingSendByteCount = 0; - - status_t status = 0; - if (handle->state == (uint8_t)kDSPI_Error) - { - status = kStatus_DSPI_Error; - } - else - { - status = kStatus_Success; - } - - handle->state = (uint8_t)kDSPI_Idle; - - if (NULL != handle->callback) - { - handle->callback(base, handle, status, handle->userData); - } -} - -/*! - * brief DSPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * param base DSPI peripheral base address. - * param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. - */ -void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle) -{ - assert(NULL != handle); - - DSPI_StopTransfer(base); - - /* Disable interrupt requests */ - DSPI_DisableInterrupts( - base, ((uint32_t)kDSPI_TxFifoUnderflowInterruptEnable | (uint32_t)kDSPI_TxFifoFillRequestInterruptEnable | - (uint32_t)kDSPI_RxFifoOverflowInterruptEnable | (uint32_t)kDSPI_RxFifoDrainRequestInterruptEnable)); - - handle->state = (uint8_t)kDSPI_Idle; - handle->remainingSendByteCount = 0; - handle->remainingReceiveByteCount = 0; -} - -/*! - * brief DSPI Master IRQ handler function. - * - * This function processes the DSPI transmit and receive IRQ. - * - * param base DSPI peripheral base address. - * param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. - */ -void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle) -{ - assert(NULL != handle); - - uint8_t dummyPattern = DSPI_GetDummyDataInstance(base); - uint32_t dataReceived; - uint32_t dataSend = 0; - uint32_t tmpRemainingReceiveByteCount = 0; - - /* Because SPI protocol is synchronous, the number of bytes that that slave received from the - * master is the actual number of bytes that the slave transmitted to the master. So we only - * monitor the received dataSize to know when the transfer is complete. - */ - if (handle->remainingReceiveByteCount > 0U) - { - while ((uint32_t)kDSPI_RxFifoDrainRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_RxFifoDrainRequestFlag)) - { - /* Have received data in the buffer. */ - dataReceived = base->POPR; - /*Clear the rx fifo drain request, needed for non-DMA applications as this flag - * will remain set even if the rx fifo is empty. By manually clearing this flag, it - * either remain clear if no more data is in the fifo, or it will set if there is - * more data in the fifo. - */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_RxFifoDrainRequestFlag); - - /* If bits/frame is one byte */ - if (handle->bitsPerFrame <= 8U) - { - if (NULL != handle->rxData) - { - /* Receive buffer is not null, store data into it */ - *handle->rxData = (uint8_t)dataReceived; - ++handle->rxData; - } - /* Descrease remaining receive byte count */ - --handle->remainingReceiveByteCount; - - if (handle->remainingSendByteCount > 0U) - { - if (NULL != handle->txData) - { - dataSend = *handle->txData; - ++handle->txData; - } - else - { - dataSend = dummyPattern; - } - - --handle->remainingSendByteCount; - /* Write the data to the DSPI data register */ - base->PUSHR_SLAVE = dataSend; - } - } - else /* If bits/frame is 2 bytes */ - { - /* With multibytes frame receiving, we only receive till the received dataSize - * matches user request. Other bytes will be ignored. - */ - if (NULL != handle->rxData) - { - /* Receive buffer is not null, store first byte into it */ - *handle->rxData = (uint8_t)dataReceived; - ++handle->rxData; - - if (handle->remainingReceiveByteCount == 1U) - { - /* Decrease remaining receive byte count */ - --handle->remainingReceiveByteCount; - } - else - { - /* Receive buffer is not null, store second byte into it */ - *handle->rxData = (uint8_t)(dataReceived >> 8U); - ++handle->rxData; - handle->remainingReceiveByteCount -= 2U; - } - } - /* If no handle->rxData*/ - else - { - if (handle->remainingReceiveByteCount == 1U) - { - /* Decrease remaining receive byte count */ - --handle->remainingReceiveByteCount; - } - else - { - handle->remainingReceiveByteCount -= 2U; - } - } - - if (handle->remainingSendByteCount > 0U) - { - if (NULL != handle->txData) - { - dataSend = *handle->txData; - ++handle->txData; - - if (handle->remainingSendByteCount == 1U) - { - --handle->remainingSendByteCount; - dataSend |= (uint16_t)((uint16_t)(dummyPattern) << 8U); - } - else - { - dataSend |= (uint32_t)(*handle->txData) << 8U; - ++handle->txData; - handle->remainingSendByteCount -= 2U; - } - } - /* If no handle->txData*/ - else - { - if (handle->remainingSendByteCount == 1U) - { - --handle->remainingSendByteCount; - } - else - { - handle->remainingSendByteCount -= 2U; - } - dataSend = ((uint32_t)(dummyPattern) << 8U) | dummyPattern; - } - /* Write the data to the DSPI data register */ - base->PUSHR_SLAVE = dataSend; - } - } - /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - if (handle->remainingReceiveByteCount == 0U) - { - break; - } - } - } - /* Check if remaining receive byte count matches user request */ - tmpRemainingReceiveByteCount = handle->remainingReceiveByteCount; - if ((handle->state == (uint8_t)(kDSPI_Error)) || (tmpRemainingReceiveByteCount == 0U)) - { - /* Other cases, stop the transfer. */ - DSPI_SlaveTransferComplete(base, handle); - return; - } - - /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ - if (0U != (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoUnderflowFlag)) - { - if (0U != (base->RSER & SPI_RSER_TFUF_RE_MASK)) - { - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoUnderflowFlag); - /* Change state to error and clear flag */ - if (NULL != handle->txData) - { - handle->state = kDSPI_Error; - } - handle->errorCount++; - } - } - - /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ - if (0U != (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_RxFifoOverflowFlag)) - { - if (0U != (base->RSER & SPI_RSER_RFOF_RE_MASK)) - { - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_RxFifoOverflowFlag); - /* Change state to error and clear flag */ - if (NULL != handle->txData) - { - handle->state = kDSPI_Error; - } - handle->errorCount++; - } - } -} - -static void DSPI_CommonIRQHandler(SPI_Type *base, void *param) -{ - if (DSPI_IsMaster(base)) - { - s_dspiMasterIsr(base, (dspi_master_handle_t *)param); - } - else - { - s_dspiSlaveIsr(base, (dspi_slave_handle_t *)param); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if defined(SPI0) -void SPI0_DriverIRQHandler(void) -{ - assert(NULL != g_dspiHandle[0]); - DSPI_CommonIRQHandler(SPI0, g_dspiHandle[0]); -} -#endif - -#if defined(SPI1) -void SPI1_DriverIRQHandler(void) -{ - assert(NULL != g_dspiHandle[1]); - DSPI_CommonIRQHandler(SPI1, g_dspiHandle[1]); -} -#endif - -#if defined(SPI2) -void SPI2_DriverIRQHandler(void) -{ - assert(NULL != g_dspiHandle[2]); - DSPI_CommonIRQHandler(SPI2, g_dspiHandle[2]); -} -#endif - -#if defined(SPI3) -void SPI3_DriverIRQHandler(void) -{ - assert(NULL != g_dspiHandle[3]); - DSPI_CommonIRQHandler(SPI3, g_dspiHandle[3]); -} -#endif - -#if defined(SPI4) -void SPI4_DriverIRQHandler(void) -{ - assert(NULL != g_dspiHandle[4]); - DSPI_CommonIRQHandler(SPI4, g_dspiHandle[4]); -} -#endif - -#if defined(SPI5) -void SPI5_DriverIRQHandler(void) -{ - assert(NULL != g_dspiHandle[5]); - DSPI_CommonIRQHandler(SPI5, g_dspiHandle[5]); -} -#endif - -#if (FSL_FEATURE_SOC_DSPI_COUNT > 6) -#error "Should write the SPIx_DriverIRQHandler function that instance greater than 5 !" -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi.h deleted file mode 100644 index 43416fb..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi.h +++ /dev/null @@ -1,1235 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_DSPI_H_ -#define _FSL_DSPI_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dspi_driver - * @{ - */ - -/********************************************************************************************************************** - * Definitions - *********************************************************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DSPI driver version 2.2.2. */ -#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) -/*@}*/ - -#ifndef DSPI_DUMMY_DATA -/*! @brief DSPI dummy data if there is no Tx data.*/ -#define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for Tx if there is no txData. */ -#endif - -/*! @brief Status for the DSPI driver.*/ -enum _dspi_status -{ - kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /*!< DSPI transfer is busy.*/ - kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /*!< DSPI driver error. */ - kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /*!< DSPI is idle.*/ - kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out of range. */ -}; - -/*! @brief DSPI status flags in SPIx_SR register.*/ -enum _dspi_flags -{ - kDSPI_TxCompleteFlag = (int)SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */ - kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /*!< End of Queue Flag.*/ - kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /*!< Transmit FIFO Underflow Flag.*/ - kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/ - kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /*!< Receive FIFO Overflow Flag.*/ - kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/ - kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /*!< The module is in Stopped/Running state.*/ - kDSPI_AllStatusFlag = (int)(SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | - SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK) /*!< All statuses above.*/ -}; - -/*! @brief DSPI interrupt source.*/ -enum _dspi_interrupt_enable -{ - kDSPI_TxCompleteInterruptEnable = (int)SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/ - kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /*!< EOQF interrupt enable.*/ - kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /*!< TFUF interrupt enable.*/ - kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, DMA disable.*/ - kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /*!< RFOF interrupt enable.*/ - kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/ - kDSPI_AllInterruptEnable = (int)(SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK | - SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK) - /*!< All above interrupts enable.*/ -}; - -/*! @brief DSPI DMA source.*/ -enum _dspi_dma_enable -{ - kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests. - No Tx interrupt request. */ - kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests. - No Rx interrupt request. */ -}; - -/*! @brief DSPI master or slave mode configuration.*/ -typedef enum _dspi_master_slave_mode -{ - kDSPI_Master = 1U, /*!< DSPI peripheral operates in master mode.*/ - kDSPI_Slave = 0U /*!< DSPI peripheral operates in slave mode.*/ -} dspi_master_slave_mode_t; - -/*! - * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is - * valid - * only when the CPHA bit in the CTAR register is 0. - */ -typedef enum _dspi_master_sample_point -{ - kDSPI_SckToSin0Clock = 0U, /*!< 0 system clocks between SCK edge and SIN sample.*/ - kDSPI_SckToSin1Clock = 1U, /*!< 1 system clock between SCK edge and SIN sample.*/ - kDSPI_SckToSin2Clock = 2U /*!< 2 system clocks between SCK edge and SIN sample.*/ -} dspi_master_sample_point_t; - -/*! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).*/ -typedef enum _dspi_which_pcs_config -{ - kDSPI_Pcs0 = 1U << 0, /*!< Pcs[0] */ - kDSPI_Pcs1 = 1U << 1, /*!< Pcs[1] */ - kDSPI_Pcs2 = 1U << 2, /*!< Pcs[2] */ - kDSPI_Pcs3 = 1U << 3, /*!< Pcs[3] */ - kDSPI_Pcs4 = 1U << 4, /*!< Pcs[4] */ - kDSPI_Pcs5 = 1U << 5 /*!< Pcs[5] */ -} dspi_which_pcs_t; - -/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration.*/ -typedef enum _dspi_pcs_polarity_config -{ - kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */ - kDSPI_PcsActiveLow = 1U /*!< Pcs Active Low (idles high). */ -} dspi_pcs_polarity_config_t; - -/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity.*/ -enum _dspi_pcs_polarity -{ - kDSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ - kDSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ - kDSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ - kDSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ - kDSPI_Pcs4ActiveLow = 1U << 4, /*!< Pcs4 Active Low (idles high). */ - kDSPI_Pcs5ActiveLow = 1U << 5, /*!< Pcs5 Active Low (idles high). */ - kDSPI_PcsAllActiveLow = 0xFFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ -}; - -/*! @brief DSPI clock polarity configuration for a given CTAR.*/ -typedef enum _dspi_clock_polarity -{ - kDSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high DSPI clock (idles low).*/ - kDSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low DSPI clock (idles high).*/ -} dspi_clock_polarity_t; - -/*! @brief DSPI clock phase configuration for a given CTAR.*/ -typedef enum _dspi_clock_phase -{ - kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the - following edge.*/ - kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the - following edge.*/ -} dspi_clock_phase_t; - -/*! @brief DSPI data shifter direction options for a given CTAR.*/ -typedef enum _dspi_shift_direction -{ - kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ - kDSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. - Shifting out of LSB is not supported for slave */ -} dspi_shift_direction_t; - -/*! @brief DSPI delay type selection.*/ -typedef enum _dspi_delay_type -{ - kDSPI_PcsToSck = 1U, /*!< Pcs-to-SCK delay. */ - kDSPI_LastSckToPcs, /*!< The last SCK edge to Pcs delay. */ - kDSPI_BetweenTransfer /*!< Delay between transfers. */ -} dspi_delay_type_t; - -/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/ -typedef enum _dspi_ctar_selection -{ - kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode; note that CTAR0 and CTAR0_SLAVE are the - same register address. */ - kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */ - kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only; note that some devices do not support CTAR2. */ - kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only; note that some devices do not support CTAR3. */ - kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only; note that some devices do not support CTAR4. */ - kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only; note that some devices do not support CTAR5. */ - kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only; note that some devices do not support CTAR6. */ - kDSPI_Ctar7 = 7U /*!< CTAR7 selection option for master mode only; note that some devices do not support CTAR7. */ -} dspi_ctar_selection_t; - -#define DSPI_MASTER_CTAR_SHIFT (0U) /*!< DSPI master CTAR shift macro; used internally. */ -#define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro; used internally. */ -#define DSPI_MASTER_PCS_SHIFT (4U) /*!< DSPI master PCS shift macro; used internally. */ -#define DSPI_MASTER_PCS_MASK (0xF0U) /*!< DSPI master PCS mask macro; used internally. */ -/*! @brief Use this enumeration for the DSPI master transfer configFlags. */ -enum _dspi_transfer_config_flag_for_master -{ - kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */ - kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */ - kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */ - kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */ - kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */ - kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */ - kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */ - kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */ - - kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */ - kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */ - kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/ - kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */ - kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */ - kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */ - - kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */ - kDSPI_MasterActiveAfterTransfer = - 1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ -}; - -#define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro; used internally. */ -#define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro; used internally. */ -/*! @brief Use this enumeration for the DSPI slave transfer configFlags. */ -enum _dspi_transfer_config_flag_for_slave -{ - kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */ - /*!< DSPI slave can only use PCS0. */ -}; - -/*! @brief DSPI transfer state, which is used for DSPI transactional API state machine. */ -enum _dspi_transfer_state -{ - kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ - kDSPI_Busy, /*!< Transfer queue is not finished. */ - kDSPI_Error /*!< Transfer error. */ -}; - -/*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/ -typedef struct _dspi_command_data_config -{ - bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/ - dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes - Register (CTAR) to use for CTAS.*/ - dspi_which_pcs_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/ - bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue.*/ - bool clearTransferCount; /*!< Clears the SPI Transfer Counter (SPI_TCNT) before transmission starts.*/ -} dspi_command_data_config_t; - -/*! @brief DSPI master ctar configuration structure.*/ -typedef struct _dspi_master_ctar_config -{ - uint32_t baudRate; /*!< Baud Rate for DSPI. */ - uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ - dspi_clock_polarity_t cpol; /*!< Clock polarity. */ - dspi_clock_phase_t cpha; /*!< Clock phase. */ - dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ - - uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum - delay. It also sets the boundary value if out of range.*/ - uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the - minimum delay. It also sets the boundary value if out of range.*/ - - uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum - delay. It also sets the boundary value if out of range.*/ -} dspi_master_ctar_config_t; - -/*! @brief DSPI master configuration structure.*/ -typedef struct _dspi_master_config -{ - dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */ - dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ - - dspi_which_pcs_t whichPcs; /*!< The desired Peripheral Chip Select (pcs). */ - dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< The desired PCS active high or low. */ - - bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only - supported for CPHA = 1.*/ - bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming - data is ignored and the data from the transfer that generated the overflow - is also ignored. If ROOE = 1, the incoming data is shifted to the - shift register. */ - - bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/ - dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer - Format. It's valid only when CPHA=0. */ -} dspi_master_config_t; - -/*! @brief DSPI slave ctar configuration structure.*/ -typedef struct _dspi_slave_ctar_config -{ - uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ - dspi_clock_polarity_t cpol; /*!< Clock polarity. */ - dspi_clock_phase_t cpha; /*!< Clock phase. */ - /*!< Slave only supports MSB and does not support LSB.*/ -} dspi_slave_ctar_config_t; - -/*! @brief DSPI slave configuration structure.*/ -typedef struct _dspi_slave_config -{ - dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */ - dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ - - bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only - supported for CPHA = 1.*/ - bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming - data is ignored and the data from the transfer that generated the overflow - is also ignored. If ROOE = 1, the incoming data is shifted to the - shift register. */ - bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/ - dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer - Format. It's valid only when CPHA=0. */ -} dspi_slave_config_t; - -/*! - * @brief Forward declaration of the _dspi_master_handle typedefs. - */ -typedef struct _dspi_master_handle dspi_master_handle_t; - -/*! - * @brief Forward declaration of the _dspi_slave_handle typedefs. - */ -typedef struct _dspi_slave_handle dspi_slave_handle_t; - -/*! - * @brief Completion callback function pointer type. - * - * @param base DSPI peripheral address. - * @param handle Pointer to the handle for the DSPI master. - * @param status Success or error code describing whether the transfer completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base, - dspi_master_handle_t *handle, - status_t status, - void *userData); -/*! - * @brief Completion callback function pointer type. - * - * @param base DSPI peripheral address. - * @param handle Pointer to the handle for the DSPI slave. - * @param status Success or error code describing whether the transfer completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base, - dspi_slave_handle_t *handle, - status_t status, - void *userData); - -/*! @brief DSPI master/slave transfer structure.*/ -typedef struct _dspi_transfer -{ - uint8_t *txData; /*!< Send buffer. */ - uint8_t *rxData; /*!< Receive buffer. */ - volatile size_t dataSize; /*!< Transfer bytes. */ - - uint32_t configFlags; /*!< Transfer transfer configuration flags; set from _dspi_transfer_config_flag_for_master if - the transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the - transfer is used for slave.*/ -} dspi_transfer_t; - -/*! @brief DSPI half-duplex(master) transfer structure */ -typedef struct _dspi_half_duplex_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - size_t txDataSize; /*!< Transfer bytes for transmit */ - size_t rxDataSize; /*!< Transfer bytes */ - uint32_t configFlags; /*!< Transfer configuration flags; set from _dspi_transfer_config_flag_for_master. */ - bool isPcsAssertInTransfer; /*!< If Pcs pin keep assert between transmit and receive. true for assert and false for - deassert. */ - bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ -} dspi_half_duplex_transfer_t; - -/*! @brief DSPI master transfer handle structure used for transactional API. */ -struct _dspi_master_handle -{ - uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ - volatile uint32_t command; /*!< The desired data command. */ - volatile uint32_t lastCommand; /*!< The desired last data command. */ - - uint8_t fifoSize; /*!< FIFO dataSize. */ - - volatile bool - isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ - volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ - volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ - size_t totalByteCount; /*!< A number of transfer bytes*/ - - volatile uint8_t state; /*!< DSPI transfer state, see _dspi_transfer_state.*/ - - dspi_master_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ -}; - -/*! @brief DSPI slave transfer handle structure used for the transactional API. */ -struct _dspi_slave_handle -{ - uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ - volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ - volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ - size_t totalByteCount; /*!< A number of transfer bytes*/ - - volatile uint8_t state; /*!< DSPI transfer state.*/ - - volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ - - dspi_slave_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ -}; - -/********************************************************************************************************************** - * API - *********************************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the DSPI master. - * - * This function initializes the DSPI master configuration. This is an example use case. - * @code - * dspi_master_config_t masterConfig; - * masterConfig.whichCtar = kDSPI_Ctar0; - * masterConfig.ctarConfig.baudRate = 500000000U; - * masterConfig.ctarConfig.bitsPerFrame = 8; - * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - * masterConfig.ctarConfig.direction = kDSPI_MsbFirst; - * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; - * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; - * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; - * masterConfig.whichPcs = kDSPI_Pcs0; - * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow; - * masterConfig.enableContinuousSCK = false; - * masterConfig.enableRxFifoOverWrite = false; - * masterConfig.enableModifiedTimingFormat = false; - * masterConfig.samplePoint = kDSPI_SckToSin0Clock; - * DSPI_MasterInit(base, &masterConfig, srcClock_Hz); - * @endcode - * - * @param base DSPI peripheral address. - * @param masterConfig Pointer to the structure dspi_master_config_t. - * @param srcClock_Hz Module source input clock in Hertz. - */ -void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Sets the dspi_master_config_t structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit(). - * Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure - * before calling the DSPI_MasterInit(). - * Example: - * @code - * dspi_master_config_t masterConfig; - * DSPI_MasterGetDefaultConfig(&masterConfig); - * @endcode - * @param masterConfig pointer to dspi_master_config_t structure - */ -void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig); - -/*! - * @brief DSPI slave configuration. - * - * This function initializes the DSPI slave configuration. This is an example use case. - * @code - * dspi_slave_config_t slaveConfig; - * slaveConfig->whichCtar = kDSPI_Ctar0; - * slaveConfig->ctarConfig.bitsPerFrame = 8; - * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - * slaveConfig->enableContinuousSCK = false; - * slaveConfig->enableRxFifoOverWrite = false; - * slaveConfig->enableModifiedTimingFormat = false; - * slaveConfig->samplePoint = kDSPI_SckToSin0Clock; - * DSPI_SlaveInit(base, &slaveConfig); - * @endcode - * - * @param base DSPI peripheral address. - * @param slaveConfig Pointer to the structure dspi_master_config_t. - */ -void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig); - -/*! - * @brief Sets the dspi_slave_config_t structure to a default value. - * - * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit(). - * Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure - * before calling the DSPI_SlaveInit(). - * This is an example. - * @code - * dspi_slave_config_t slaveConfig; - * DSPI_SlaveGetDefaultConfig(&slaveConfig); - * @endcode - * @param slaveConfig Pointer to the dspi_slave_config_t structure. - */ -void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig); - -/*! - * @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock. - * @param base DSPI peripheral address. - */ -void DSPI_Deinit(SPI_Type *base); - -/*! - * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0. - * - * @param base DSPI peripheral address. - * @param enable Pass true to enable module, false to disable module. - */ -static inline void DSPI_Enable(SPI_Type *base, bool enable) -{ - if (enable) - { - base->MCR &= ~SPI_MCR_MDIS_MASK; - } - else - { - base->MCR |= SPI_MCR_MDIS_MASK; - } -} - -/*! - *@} - */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the DSPI status flag state. - * @param base DSPI peripheral address. - * @return DSPI status (in SR register). - */ -static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base) -{ - return (base->SR); -} - -/*! - * @brief Clears the DSPI status flag. - * - * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the - * desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The - * function uses these bit positions in its algorithm to clear the desired flag state. - * This is an example. - * @code - * DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag); - * @endcode - * - * @param base DSPI peripheral address. - * @param statusFlags The status flag used from the type dspi_flags. - */ -static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags) -{ - base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ -} - -/*! - *@} - */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the DSPI interrupts. - * - * This function configures the various interrupt masks of the DSPI. The parameters are a base and an interrupt mask. - * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request. - * Do not use this API(write to RSER register) while DSPI is in running state. - * - * @code - * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); - * @endcode - * - * @param base DSPI peripheral address. - * @param mask The interrupt mask; use the enum _dspi_interrupt_enable. - */ -void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask); - -/*! - * @brief Disables the DSPI interrupts. - * - * @code - * DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); - * @endcode - * - * @param base DSPI peripheral address. - * @param mask The interrupt mask; use the enum _dspi_interrupt_enable. - */ -static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask) -{ - base->RSER &= ~mask; -} - -/*! - *@} - */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the DSPI DMA request. - * - * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask. - * @code - * DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); - * @endcode - * - * @param base DSPI peripheral address. - * @param mask The interrupt mask; use the enum dspi_dma_enable. - */ -static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask) -{ - base->RSER |= mask; -} - -/*! - * @brief Disables the DSPI DMA request. - * - * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask. - * @code - * SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); - * @endcode - * - * @param base DSPI peripheral address. - * @param mask The interrupt mask; use the enum dspi_dma_enable. - */ -static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask) -{ - base->RSER &= ~mask; -} - -/*! - * @brief Gets the DSPI master PUSHR data register address for the DMA operation. - * - * This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation. - * - * @param base DSPI peripheral address. - * @return The DSPI master PUSHR data register address. - */ -static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base) -{ - return (uint32_t) & (base->PUSHR); -} - -/*! - * @brief Gets the DSPI slave PUSHR data register address for the DMA operation. - * - * This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation. - * - * @param base DSPI peripheral address. - * @return The DSPI slave PUSHR data register address. - */ -static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base) -{ - return (uint32_t) & (base->PUSHR_SLAVE); -} - -/*! - * @brief Gets the DSPI POPR data register address for the DMA operation. - * - * This function gets the DSPI POPR data register address as this value is needed for the DMA operation. - * - * @param base DSPI peripheral address. - * @return The DSPI POPR data register address. - */ -static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base) -{ - return (uint32_t) & (base->POPR); -} - -/*! - *@} - */ - -/*! - * @name Bus Operations - * @{ - */ -/*! - * @brief Get instance number for DSPI module. - * - * @param base DSPI peripheral base address. - */ -uint32_t DSPI_GetInstance(SPI_Type *base); - -/*! - * @brief Configures the DSPI for master or slave. - * - * @param base DSPI peripheral address. - * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t. - */ -static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode) -{ - base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode); -} - -/*! - * @brief Returns whether the DSPI module is in master mode. - * - * @param base DSPI peripheral address. - * @return Returns true if the module is in master mode or false if the module is in slave mode. - */ -static inline bool DSPI_IsMaster(SPI_Type *base) -{ - if (0U != ((base->MCR) & SPI_MCR_MSTR_MASK)) - { - return true; - } - else - { - return false; - } -} -/*! - * @brief Starts the DSPI transfers and clears HALT bit in MCR. - * - * This function sets the module to start data transfer in either master or slave mode. - * - * @param base DSPI peripheral address. - */ -static inline void DSPI_StartTransfer(SPI_Type *base) -{ - base->MCR &= ~SPI_MCR_HALT_MASK; -} -/*! - * @brief Stops DSPI transfers and sets the HALT bit in MCR. - * - * This function stops data transfers in either master or slave modes. - * - * @param base DSPI peripheral address. - */ -static inline void DSPI_StopTransfer(SPI_Type *base) -{ - base->MCR |= SPI_MCR_HALT_MASK; -} - -/*! - * @brief Enables or disables the DSPI FIFOs. - * - * This function allows the caller to disable/enable the Tx and Rx FIFOs independently. - * Note that to disable, pass in a logic 0 (false) for the particular FIFO configuration. To enable, - * pass in a logic 1 (true). - * - * @param base DSPI peripheral address. - * @param enableTxFifo Disables (false) the TX FIFO; Otherwise, enables (true) the TX FIFO - * @param enableRxFifo Disables (false) the RX FIFO; Otherwise, enables (true) the RX FIFO - */ -static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo) -{ - base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | - SPI_MCR_DIS_TXF((false == enableTxFifo ? 1U : 0U)) | SPI_MCR_DIS_RXF((false == enableRxFifo ? 1U : 0U)); -} - -/*! - * @brief Flushes the DSPI FIFOs. - * - * @param base DSPI peripheral address. - * @param flushTxFifo Flushes (true) the Tx FIFO; Otherwise, does not flush (false) the Tx FIFO - * @param flushRxFifo Flushes (true) the Rx FIFO; Otherwise, does not flush (false) the Rx FIFO - */ -static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo) -{ - base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | - SPI_MCR_CLR_TXF((true == flushTxFifo ? 1U : 0U)) | SPI_MCR_CLR_RXF((true == flushRxFifo ? 1U : 0U)); -} - -/*! - * @brief Configures the DSPI peripheral chip select polarity simultaneously. - * For example, PCS0 and PCS1 are set to active low and other PCS is set to active high. Note that the number of - * PCSs is specific to the device. - * @code - * DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow); - @endcode - * @param base DSPI peripheral address. - * @param mask The PCS polarity mask; use the enum _dspi_pcs_polarity. - */ -static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask) -{ - base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask); -} - -/*! - * @brief Sets the DSPI baud rate in bits per second. - * - * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without - * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the - * caller also provide the frequency of the module source clock (in Hertz). - * - * @param base DSPI peripheral address. - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t - * @param baudRate_Bps The desired baud rate in bits per second - * @param srcClock_Hz Module source input clock in Hertz - * @return The actual calculated baud rate - */ -uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, - dspi_ctar_selection_t whichCtar, - uint32_t baudRate_Bps, - uint32_t srcClock_Hz); - -/*! - * @brief Manually configures the delay prescaler and scaler for a particular CTAR. - * - * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar - * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT). - * - * These delay names are available in the type dspi_delay_type_t. - * - * The user passes the delay to the configuration along with the prescaler and scaler value. - * This allows the user to directly set the prescaler/scaler values if pre-calculated or - * to manually increment either value. - * - * @param base DSPI peripheral address. - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. - * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3). - * @param scaler The scaler delay value (can be any integer between 0 to 15). - * @param whichDelay The desired delay to configure; must be of type dspi_delay_type_t - */ -void DSPI_MasterSetDelayScaler( - SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay); - -/*! - * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. - * - * This function calculates the values for the following. - * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or - * After SCK delay pre-scalar (PASC) and scalar (ASC), or - * Delay after transfer pre-scalar (PDT) and scalar (DT). - * - * These delay names are available in the type dspi_delay_type_t. - * - * The user passes which delay to configure along with the desired delay value in nanoseconds. The function - * calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact - * delay match may not be possible. In this case, the closest match is calculated without going below the desired - * delay value input. - * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum - * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay - * input. - * - * @param base DSPI peripheral address. - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. - * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t - * @param srcClock_Hz Module source input clock in Hertz - * @param delayTimeInNanoSec The desired delay value in nanoseconds. - * @return The actual calculated delay value. - */ -uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, - dspi_ctar_selection_t whichCtar, - dspi_delay_type_t whichDelay, - uint32_t srcClock_Hz, - uint32_t delayTimeInNanoSec); - -/*! - * @brief Writes data into the data buffer for master mode. - * - * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion - * provides characteristics of the data, such as the optional continuous chip select - * operation between transfers, the desired Clock and Transfer Attributes register to use for the - * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current - * transfer is the last in the queue, and whether to clear the transfer count (normally needed when - * sending the first frame of a data packet). This is an example. - * @code - * dspi_command_data_config_t commandConfig; - * commandConfig.isPcsContinuous = true; - * commandConfig.whichCtar = kDSPICtar0; - * commandConfig.whichPcs = kDSPIPcs0; - * commandConfig.clearTransferCount = false; - * commandConfig.isEndOfQueue = false; - * DSPI_MasterWriteData(base, &commandConfig, dataWord); - @endcode - * - * @param base DSPI peripheral address. - * @param command Pointer to the command structure. - * @param data The data word to be sent. - */ -static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) -{ - base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | - SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | - SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); -} - -/*! - * @brief Sets the dspi_command_data_config_t structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx(). - * Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or modify the structure - * before calling the DSPI_MasterWrite_xx(). - * This is an example. - * @code - * dspi_command_data_config_t command; - * DSPI_GetDefaultDataCommandConfig(&command); - * @endcode - * @param command Pointer to the dspi_command_data_config_t structure. - */ -void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command); - -/*! - * @brief Writes data into the data buffer master mode and waits till complete to return. - * - * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion - * provides characteristics of the data, such as the optional continuous chip select - * operation between transfers, the desired Clock and Transfer Attributes register to use for the - * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current - * transfer is the last in the queue, and whether to clear the transfer count (normally needed when - * sending the first frame of a data packet). This is an example. - * @code - * dspi_command_config_t commandConfig; - * commandConfig.isPcsContinuous = true; - * commandConfig.whichCtar = kDSPICtar0; - * commandConfig.whichPcs = kDSPIPcs1; - * commandConfig.clearTransferCount = false; - * commandConfig.isEndOfQueue = false; - * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord); - * @endcode - * - * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be - * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol, - * the received data is available when the transmit completes. - * - * @param base DSPI peripheral address. - * @param command Pointer to the command structure. - * @param data The data word to be sent. - */ -void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data); - -/*! - * @brief Returns the DSPI command word formatted to the PUSHR data register bit field. - * - * This function allows the caller to pass in the data command structure and returns the command word formatted - * according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the - * desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or - * DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps - * improve performance in cases where the command structure is constant. For example, the user calls this function - * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR - * this formatted command word with the desired data to transmit. This process increases transmit performance when - * compared to calling send functions, such as DSPI_HAL_WriteDataMastermode, which format the command word each time a - * data word is to be sent. - * - * @param command Pointer to the command structure. - * @return The command word formatted to the PUSHR data register bit field. - */ -static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command) -{ - /* Format the 16-bit command word according to the PUSHR data register bit field*/ - return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | - SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | - SPI_PUSHR_CTCNT(command->clearTransferCount)); -} - -/*! - * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data - * buffer master mode and waits till complete to return. - * - * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total - * 32-bit word - * as the data to send. - * The command portion provides characteristics of the data, such as the optional continuous chip select operation - * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the - * desired PCS - * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the - * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for - * appending this command with the data to send. This is an example: - * @code - * dataWord = <16-bit command> | <16-bit data>; - * DSPI_MasterWriteCommandDataBlocking(base, dataWord); - * @endcode - * - * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be - * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). - * Because the SPI is a synchronous protocol, the received data is available when the transmit completes. - * - * For a blocking polling transfer, see methods below. - * Option 1: - * uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command); - * uint32_t data0 = command_to_send | data_need_to_send_0; - * uint32_t data1 = command_to_send | data_need_to_send_1; - * uint32_t data2 = command_to_send | data_need_to_send_2; - * - * DSPI_MasterWriteCommandDataBlocking(base,data0); - * DSPI_MasterWriteCommandDataBlocking(base,data1); - * DSPI_MasterWriteCommandDataBlocking(base,data2); - * - * Option 2: - * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0); - * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1); - * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2); - * - * @param base DSPI peripheral address. - * @param data The data word (command and data combined) to be sent. - */ -void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data); - -/*! - * @brief Writes data into the data buffer in slave mode. - * - * In slave mode, up to 16-bit words may be written. - * - * @param base DSPI peripheral address. - * @param data The data to send. - */ -static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data) -{ - base->PUSHR_SLAVE = data; -} - -/*! - * @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns. - * - * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data - * into data register, and finally waits until the data is transmitted. - * - * @param base DSPI peripheral address. - * @param data The data to send. - */ -void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data); - -/*! - * @brief Reads data from the data buffer. - * - * @param base DSPI peripheral address. - * @return The data from the read data buffer. - */ -static inline uint32_t DSPI_ReadData(SPI_Type *base) -{ - return (base->POPR); -} - -/*! - * @brief Set up the dummy data. - * - * @param base DSPI peripheral address. - * @param dummyData Data to be transferred when tx buffer is NULL. - */ -void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData); - -/*! - *@} - */ - -/*! - * @name Transactional - * @{ - */ -/*Transactional APIs*/ - -/*! - * @brief Initializes the DSPI master handle. - * - * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a - * specified DSPI instance, call this API once to get the initialized handle. - * - * @param base DSPI peripheral base address. - * @param handle DSPI handle pointer to dspi_master_handle_t. - * @param callback DSPI callback. - * @param userData Callback function parameter. - */ -void DSPI_MasterTransferCreateHandle(SPI_Type *base, - dspi_master_handle_t *handle, - dspi_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief DSPI master transfer data using polling. - * - * This function transfers data using polling. This is a blocking function, which does not return until all transfers - * have been completed. - * - * @param base DSPI peripheral base address. - * @param transfer Pointer to the dspi_transfer_t structure. - * @return status of status_t. - */ -status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer); - -/*! - * @brief DSPI master transfer data using interrupts. - * - * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all - * data is transferred, the callback function is called. - - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - * @param transfer Pointer to the dspi_transfer_t structure. - * @return status of status_t. - */ -status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); - -/*! - * @brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for DSPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer will be half-duplex, - * users can set transmit first or receive first. - * - * @param base DSPI base pointer - * @param xfer pointer to dspi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t DSPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, dspi_half_duplex_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking DSPI interrupt transfer. - * - * This function transfers data using interrupts, the transfer mechanism is half-duplex. This is a non-blocking - * function, - * which returns right away. When all data is transferred, the callback function is called. - * - * @param base DSPI peripheral base address. - * @param handle pointer to dspi_master_handle_t structure which stores the transfer state - * @param xfer pointer to dspi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t DSPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - dspi_master_handle_t *handle, - dspi_half_duplex_transfer_t *xfer); - -/*! - * @brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count); - -/*! - * @brief DSPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - */ -void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle); - -/*! - * @brief DSPI Master IRQ handler function. - * - * This function processes the DSPI transmit and receive IRQ. - - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - */ -void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle); - -/*! - * @brief Initializes the DSPI slave handle. - * - * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a - * specified DSPI instance, call this API once to get the initialized handle. - * - * @param handle DSPI handle pointer to the dspi_slave_handle_t. - * @param base DSPI peripheral base address. - * @param callback DSPI callback. - * @param userData Callback function parameter. - */ -void DSPI_SlaveTransferCreateHandle(SPI_Type *base, - dspi_slave_handle_t *handle, - dspi_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief DSPI slave transfers data using an interrupt. - * - * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all - * data is transferred, the callback function is called. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. - * @param transfer Pointer to the dspi_transfer_t structure. - * @return status of status_t. - */ -status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer); - -/*! - * @brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count); - -/*! - * @brief DSPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. - */ -void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle); - -/*! - * @brief DSPI Master IRQ handler function. - * - * This function processes the DSPI transmit and receive IRQ. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. - */ -void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle); - -/*! - * brief Dummy data for each instance. - * - * The purpose of this API is to avoid MISRA rule8.5 : Multiple declarations of - * externally-linked object or function g_dspiDummyData. - * - * param base DSPI peripheral base address. - */ -uint8_t DSPI_GetDummyDataInstance(SPI_Type *base); - -/*! - *@} - */ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ - /*! - *@} - */ - -#endif /*_FSL_DSPI_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi_edma.c deleted file mode 100644 index 7e535a3..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi_edma.c +++ /dev/null @@ -1,1557 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dspi_edma.h" - -/*********************************************************************************************************************** - * Definitions - ***********************************************************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.dspi_edma" -#endif - -/*! - * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. - */ -typedef struct _dspi_master_edma_private_handle -{ - SPI_Type *base; /*!< DSPI peripheral base address. */ - dspi_master_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */ -} dspi_master_edma_private_handle_t; - -/*! - * @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. - */ -typedef struct _dspi_slave_edma_private_handle -{ - SPI_Type *base; /*!< DSPI peripheral base address. */ - dspi_slave_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */ -} dspi_slave_edma_private_handle_t; - -/*********************************************************************************************************************** - * Prototypes - ***********************************************************************************************************************/ -/*! - * @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA. - * This is not a public API. - */ -static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, - void *g_dspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds); - -/*! - * @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA. - * This is not a public API. - */ -static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, - void *g_dspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds); - -/*********************************************************************************************************************** - * Variables - ***********************************************************************************************************************/ - -/*! @brief Pointers to dspi edma handles for each instance. */ -static dspi_master_edma_private_handle_t s_dspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT]; -static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT]; - -/*********************************************************************************************************************** - * Code - ***********************************************************************************************************************/ - -/*! - * brief Initializes the DSPI master eDMA handle. - * - * This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs. Usually, for a - * specified DSPI instance, call this API once to get the initialized handle. - * - * Note that DSPI eDMA has separated (RX and TX as two sources) or shared (RX and TX are the same source) DMA request - * source. - * (1) For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and - * TX DMAMUX source for edmaIntermediaryToTxRegHandle. - * (2) For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle. - * - * param base DSPI peripheral base address. - * param handle DSPI handle pointer to dspi_master_edma_handle_t. - * param callback DSPI callback. - * param userData A callback function parameter. - * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. - * param edmaTxDataToIntermediaryHandle edmaTxDataToIntermediaryHandle pointer to edma_handle_t. - * param edmaIntermediaryToTxRegHandle edmaIntermediaryToTxRegHandle pointer to edma_handle_t. - */ -void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base, - dspi_master_edma_handle_t *handle, - dspi_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaRxRegToRxDataHandle, - edma_handle_t *edmaTxDataToIntermediaryHandle, - edma_handle_t *edmaIntermediaryToTxRegHandle) -{ - assert(NULL != handle); - assert(NULL != edmaRxRegToRxDataHandle); -#if (!(defined(FSL_FEATURE_DSPI_HAS_GASKET) && FSL_FEATURE_DSPI_HAS_GASKET)) - assert(NULL != edmaTxDataToIntermediaryHandle); -#endif - assert(NULL != edmaIntermediaryToTxRegHandle); - - /* Zero the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - uint32_t instance = DSPI_GetInstance(base); - - s_dspiMasterEdmaPrivateHandle[instance].base = base; - s_dspiMasterEdmaPrivateHandle[instance].handle = handle; - - handle->callback = callback; - handle->userData = userData; - - handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; - handle->edmaTxDataToIntermediaryHandle = edmaTxDataToIntermediaryHandle; - handle->edmaIntermediaryToTxRegHandle = edmaIntermediaryToTxRegHandle; -} - -/*! - * brief DSPI master transfer data using eDMA. - * - * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data - * is transferred, the callback function is called. - * - * param base DSPI peripheral base address. - * param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state. - * param transfer A pointer to the dspi_transfer_t structure. - * return status of status_t. - */ -status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer) -{ - assert(NULL != handle); - assert(NULL != transfer); - - /* If the transfer count is zero, then return immediately.*/ - if (transfer->dataSize == 0U) - { - return kStatus_InvalidArgument; - } - - /* If both send buffer and receive buffer is null */ - if ((NULL == (transfer->txData)) && (NULL == (transfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == (uint8_t)kDSPI_Busy) - { - return kStatus_DSPI_Busy; - } - - handle->state = (uint8_t)kDSPI_Busy; - - uint32_t instance = DSPI_GetInstance(base); - uint16_t wordToSend = 0; - uint8_t dummyData = DSPI_GetDummyDataInstance(base); - uint8_t dataAlreadyFed = 0; - uint8_t dataFedMax = 2; - uint32_t tmpMCR = 0; - size_t tmpRemainingSendByteCount = 0; - - uint32_t rxAddr = DSPI_GetRxRegisterAddress(base); - uint32_t txAddr = DSPI_MasterGetTxRegisterAddress(base); - - edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU)); - - edma_transfer_config_t transferConfigA; - edma_transfer_config_t transferConfigB; - - handle->txBuffIfNull = ((uint32_t)dummyData << 8U) | dummyData; - - dspi_command_data_config_t commandStruct; - DSPI_StopTransfer(base); - DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag); - - commandStruct.whichPcs = - (dspi_which_pcs_t)((uint32_t)1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); - commandStruct.isEndOfQueue = false; - commandStruct.clearTransferCount = false; - commandStruct.whichCtar = - (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); - commandStruct.isPcsContinuous = - (0U != (transfer->configFlags & (uint32_t)kDSPI_MasterPcsContinuous)) ? true : false; - handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - commandStruct.isEndOfQueue = true; - commandStruct.isPcsContinuous = - (0U != (transfer->configFlags & (uint32_t)kDSPI_MasterActiveAfterTransfer)) ? true : false; - handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1U; - - tmpMCR = base->MCR; - if ((0U != (tmpMCR & SPI_MCR_DIS_RXF_MASK)) || (0U != (tmpMCR & SPI_MCR_DIS_TXF_MASK))) - { - handle->fifoSize = 1; - } - else - { - handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); - } - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->remainingSendByteCount = transfer->dataSize; - handle->remainingReceiveByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer - * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame - */ - uint32_t limited_size = 0; - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - limited_size = 32767u; - } - else - { - limited_size = 511u; - } - - if (handle->bitsPerFrame > 8U) - { - if (transfer->dataSize > (limited_size << 1u)) - { - handle->state = (uint8_t)kDSPI_Idle; - return kStatus_DSPI_OutOfRange; - } - } - else - { - if (transfer->dataSize > limited_size) - { - handle->state = (uint8_t)kDSPI_Idle; - return kStatus_DSPI_OutOfRange; - } - } - - /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */ - if ((0U != (transfer->dataSize & 0x1U)) && (handle->bitsPerFrame > 8U)) - { - handle->state = (uint8_t)kDSPI_Idle; - return kStatus_InvalidArgument; - } - - DSPI_DisableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable); - - EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback, - &s_dspiMasterEdmaPrivateHandle[instance]); - - /* - (1)For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C. - channel_A minor link to channel_B , channel_B minor link to channel_C. - - Already pushed 1 or 2 data in SPI_PUSHR , then start the DMA tansfer. - channel_A:SPI_POPR to rxData, - channel_B:next txData to handle->command (low 16 bits), - channel_C:handle->command (32 bits) to SPI_PUSHR, and use the scatter/gather to transfer the last data - (handle->lastCommand to SPI_PUSHR). - - (2)For DSPI instances with separate RX and TX DMA requests: - Rx DMA request -> channel_A - Tx DMA request -> channel_C -> channel_B . - channel_C major link to channel_B. - So need prepare the first data in "intermediary" before the DMA - transfer and then channel_B is used to prepare the next data to "intermediary" - - channel_A:SPI_POPR to rxData, - channel_C: handle->command (32 bits) to SPI_PUSHR, - channel_B: next txData to handle->command (low 16 bits), and use the scatter/gather to prepare the last data - (handle->lastCommand to handle->Command). - */ - - /*If dspi has separate dma request , prepare the first data in "intermediary" . - else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/ - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - /* For DSPI instances with separate RX/TX DMA requests, we'll use the TX DMA request to - * trigger the TX DMA channel and RX DMA request to trigger the RX DMA channel - */ - - /*Prepare the firt data*/ - if (handle->bitsPerFrame > 8U) - { - /* If it's the last word */ - if (handle->remainingSendByteCount <= 2U) - { - if (NULL != handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; /* increment to next data byte */ - wordToSend |= (uint16_t)(*(handle->txData)) << 8U; - } - else - { - wordToSend = (((uint16_t)dummyData << 8U) | (uint16_t)dummyData); - } - handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; - handle->command = handle->lastCommand; - } - else /* For all words except the last word , frame > 8bits */ - { - if (NULL != handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; /* increment to next data byte */ - wordToSend |= (uint16_t)(*(handle->txData)) << 8U; - ++handle->txData; /* increment to next data byte */ - } - else - { - wordToSend = (((uint16_t)dummyData << 8U) | (uint16_t)dummyData); - } - handle->command = (handle->command & 0xffff0000U) | wordToSend; - } - } - else /* Optimized for bits/frame less than or equal to one byte. */ - { - if (NULL != handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; /* increment to next data word*/ - } - else - { - wordToSend = dummyData; - } - - if (handle->remainingSendByteCount == 1U) - { - handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; - handle->command = handle->lastCommand; - } - else - { - handle->command = (handle->command & 0xffff0000U) | wordToSend; - } - } - } - - else /*dspi has shared dma request*/ - { - /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to - * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. - */ - - /* If bits/frame is greater than one byte */ - if (handle->bitsPerFrame > 8U) - { - while ((uint32_t)kDSPI_TxFifoFillRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - if (handle->remainingSendByteCount <= 2U) - { - if (NULL != handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; - wordToSend |= (uint16_t)(*(handle->txData)) << 8U; - } - else - { - wordToSend = (((uint16_t)dummyData << 8U) | (uint16_t)dummyData); - } - handle->remainingSendByteCount = 0; - base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend; - } - /* For all words except the last word */ - else - { - if (NULL != handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; - wordToSend |= (uint16_t)(*(handle->txData)) << 8U; - ++handle->txData; - } - else - { - wordToSend = (((uint16_t)dummyData << 8U) | (uint16_t)dummyData); - } - handle->remainingSendByteCount -= 2U; - base->PUSHR = (handle->command & 0xffff0000U) | wordToSend; - } - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - dataAlreadyFed += 2U; - - /* exit loop if send count is zero, else update local variables for next loop */ - if ((handle->remainingSendByteCount == 0U) || (dataAlreadyFed == (dataFedMax * 2U))) - { - break; - } - } /* End of TX FIFO fill while loop */ - } - else /* Optimized for bits/frame less than or equal to one byte. */ - { - while ((uint32_t)kDSPI_TxFifoFillRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - if (NULL != handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; - } - else - { - wordToSend = dummyData; - } - - if (handle->remainingSendByteCount == 1U) - { - base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend; - } - else - { - base->PUSHR = (handle->command & 0xffff0000U) | wordToSend; - } - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - --handle->remainingSendByteCount; - - dataAlreadyFed++; - - /* exit loop if send count is zero, else update local variables for next loop */ - if ((handle->remainingSendByteCount == 0U) || (dataAlreadyFed == dataFedMax)) - { - break; - } - } /* End of TX FIFO fill while loop */ - } - } - - /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer(rxData)*/ - EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); - - transferConfigA.srcAddr = (uint32_t)rxAddr; - transferConfigA.srcOffset = 0; - - if (NULL != handle->rxData) - { - transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]); - transferConfigA.destOffset = 1; - } - else - { - transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull); - transferConfigA.destOffset = 0; - } - - transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes; - - if (handle->bitsPerFrame <= 8U) - { - transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigA.minorLoopBytes = 1; - transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount; - } - else - { - transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfigA.minorLoopBytes = 2; - transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2U; - } - - /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ - handle->nbytes = (uint8_t)(transferConfigA.minorLoopBytes); - - EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - (const edma_transfer_config_t *)(uint32_t)&transferConfigA, NULL); - EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - (uint32_t)kEDMA_MajorInterruptEnable); - - tmpRemainingSendByteCount = handle->remainingSendByteCount; - /*Calculate the last data : handle->lastCommand*/ - if (((tmpRemainingSendByteCount > 0U) && (1U != (uint8_t)FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) || - ((((tmpRemainingSendByteCount > 1U) && (handle->bitsPerFrame <= 8U)) || - ((tmpRemainingSendByteCount > 2U) && (handle->bitsPerFrame > 8U))) && - (1U == (uint8_t)FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))) - { - if (NULL != handle->txData) - { - uint32_t bufferIndex = 0; - - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - if (handle->bitsPerFrame <= 8U) - { - bufferIndex = handle->remainingSendByteCount - 1U; - } - else - { - bufferIndex = handle->remainingSendByteCount - 2U; - } - } - else - { - bufferIndex = handle->remainingSendByteCount; - } - - uint32_t tmpLastCommand = handle->lastCommand; - uint8_t *tmpTxData = handle->txData; - - if (handle->bitsPerFrame <= 8U) - { - tmpLastCommand = (tmpLastCommand & 0xffff0000U) | tmpTxData[bufferIndex - 1U]; - } - else - { - tmpLastCommand = (tmpLastCommand & 0xffff0000U) | ((uint32_t)tmpTxData[bufferIndex - 1U] << 8U) | - tmpTxData[bufferIndex - 2U]; - } - - handle->lastCommand = tmpLastCommand; - } - else - { - if (handle->bitsPerFrame <= 8U) - { - wordToSend = dummyData; - } - else - { - wordToSend = (((uint16_t)dummyData << 8U) | (uint16_t)dummyData); - } - handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; - } - } - -/* The feature of GASKET is that the SPI supports 8-bit or 16-bit writes to the PUSH TX FIFO, - * allowing a single write to the command word followed by multiple writes to the transmit word. - * The TX FIFO will save the last command word written, and convert a 8-bit/16-bit write to the - * transmit word into a 32-bit write that pushes both the command word and transmit word into - * the TX FIFO (PUSH TX FIFO Register In Master Mode) - * So, if this feature is supported, we can use use one channel to carry the receive data from - * receive regsiter to user data buffer, use the other channel to carry the data from user data buffer - * to transmit register,and use the scatter/gather function to prepare the last data. - * That is to say, if GASKET feature is supported, we can use only two channels for tansferring data. - */ -#if defined(FSL_FEATURE_DSPI_HAS_GASKET) && FSL_FEATURE_DSPI_HAS_GASKET - /* For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data - * (handle->lastCommand) to PUSHR register. - */ - - EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel); - - if ((1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) || - ((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))) - { - transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand); - transferConfigB.destAddr = (uint32_t)txAddr; - transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigB.srcOffset = 0; - transferConfigB.destOffset = 0; - transferConfigB.minorLoopBytes = 4; - transferConfigB.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD); - EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL); - } - - /*User_Send_Buffer(txData) to PUSHR register. */ - if (((handle->remainingSendByteCount > 2U) && (handle->bitsPerFrame <= 8U)) || - ((handle->remainingSendByteCount > 4U) && (handle->bitsPerFrame > 8U))) - { - if (handle->txData) - { - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - /* For DSPI with separate RX and TX DMA requests, one frame data has been carry - * to handle->command, so need to reduce the pointer of txData. - */ - transferConfigB.srcAddr = - (uint32_t)((uint8_t *)(handle->txData) - ((handle->bitsPerFrame <= 8U) ? (1U) : (2U))); - transferConfigB.srcOffset = 1; - } - else - { - /* For DSPI with shared RX and TX DMA requests, one or two frame data have been carry - * to PUSHR register, so no need to change the pointer of txData. - */ - transferConfigB.srcAddr = (uint32_t)((uint8_t *)(handle->txData)); - transferConfigB.srcOffset = 1; - } - } - else - { - transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigB.srcOffset = 0; - } - - transferConfigB.destAddr = (uint32_t)txAddr; - transferConfigB.destOffset = 0; - - transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes; - - if (handle->bitsPerFrame <= 8U) - { - transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigB.minorLoopBytes = 1; - - transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1U; - } - else - { - transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigB.minorLoopBytes = 2; - transferConfigB.majorLoopCounts = (handle->remainingSendByteCount / 2U) - 1U; - } - - EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigB, softwareTCD); - } - /* If only one word to transmit, only carry the lastcommand. */ - else - { - EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigB, NULL); - } - - /*Start the EDMA channel_A , channel_C. */ - EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle); - - /* Set the channel link. - * For DSPI instances with shared TX and RX DMA requests, setup channel minor link, first receive data from the - * receive register, and then carry transmit data to PUSHER register. - * For DSPI instance with separate TX and RX DMA requests, there is no need to set up channel link. - */ - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - /*Set channel priority*/ - uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; - uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel; - uint8_t t = 0; - - if (channelPriorityLow > channelPriorityHigh) - { - t = channelPriorityLow; - channelPriorityLow = channelPriorityHigh; - channelPriorityHigh = t; - } - - edma_channel_Preemption_config_t preemption_config_t; - preemption_config_t.enableChannelPreemption = true; - preemption_config_t.enablePreemptAbility = true; - preemption_config_t.channelPriority = channelPriorityLow; - - EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityHigh; - EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t); - /*if there is Rx DMA request , carry the 32bits data (handle->command) to user data first , then link to - channelC to carry the next data to PUSHER register.(txData to PUSHER) */ - if (handle->remainingSendByteCount > 0U) - { - EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MinorLink, handle->edmaIntermediaryToTxRegHandle->channel); - } - } - - DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); - - /* Setup control info to PUSHER register. */ - *((uint16_t *)&(base->PUSHR) + 1) = (handle->command >> 16U); -#else - - /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should - write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the - SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */ - - EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel); - - /*For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data - * (handle->lastCommand) to handle->Command*/ - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand); - transferConfigB.destAddr = (uint32_t) & (handle->command); - transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigB.srcOffset = 0; - transferConfigB.destOffset = 0; - transferConfigB.minorLoopBytes = 4; - transferConfigB.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD); - EDMA_TcdSetTransferConfig(softwareTCD, (const edma_transfer_config_t *)(uint32_t)&transferConfigB, NULL); - } - - tmpRemainingSendByteCount = handle->remainingSendByteCount; - /*User_Send_Buffer(txData) to intermediary(handle->command)*/ - if (((((tmpRemainingSendByteCount > 2U) && (handle->bitsPerFrame <= 8U)) || - ((tmpRemainingSendByteCount > 4U) && (handle->bitsPerFrame > 8U))) && - (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) || - (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) - { - if (NULL != handle->txData) - { - transferConfigB.srcAddr = (uint32_t)(handle->txData); - transferConfigB.srcOffset = 1; - } - else - { - transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigB.srcOffset = 0; - } - - transferConfigB.destAddr = (uint32_t)(&handle->command); - transferConfigB.destOffset = 0; - - transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes; - - if (handle->bitsPerFrame <= 8U) - { - transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigB.minorLoopBytes = 1; - - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 2U; - } - else - { - /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is - majorlink , the majorlink would not trigger the channel_C*/ - transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1U; - } - } - else - { - transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigB.minorLoopBytes = 2; - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2U - 2U; - } - else - { - /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is - * majorlink*/ - transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2U + 1U; - } - } - - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, - (const edma_transfer_config_t *)(uint32_t)&transferConfigB, softwareTCD); - EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, false); - } - else - { - EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, - (const edma_transfer_config_t *)(uint32_t)&transferConfigB, NULL); - } - } - else - { - EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, - (const edma_transfer_config_t *)(uint32_t)&transferConfigB, NULL); - } - - /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to - handle the last data */ - - edma_transfer_config_t transferConfigC; - EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel); - - tmpRemainingSendByteCount = handle->remainingSendByteCount; - /*For DSPI instances with shared RX/TX DMA requests: use the scatter/gather to prepare the last data - * (handle->lastCommand) to SPI_PUSHR*/ - if (((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (tmpRemainingSendByteCount > 0U))) - { - transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand); - transferConfigC.destAddr = (uint32_t)txAddr; - transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigC.srcOffset = 0; - transferConfigC.destOffset = 0; - transferConfigC.minorLoopBytes = 4; - transferConfigC.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD); - EDMA_TcdSetTransferConfig(softwareTCD, (const edma_transfer_config_t *)(uint32_t)&transferConfigC, NULL); - } - - tmpRemainingSendByteCount = handle->remainingSendByteCount; - if (((tmpRemainingSendByteCount > 1U) && (handle->bitsPerFrame <= 8U)) || - ((tmpRemainingSendByteCount > 2U) && (handle->bitsPerFrame > 8U)) || - (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) - { - transferConfigC.srcAddr = (uint32_t)(&(handle->command)); - transferConfigC.destAddr = (uint32_t)txAddr; - - transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigC.srcOffset = 0; - transferConfigC.destOffset = 0; - transferConfigC.minorLoopBytes = 4; - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - if (handle->bitsPerFrame <= 8U) - { - transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1U; - } - else - { - transferConfigC.majorLoopCounts = (handle->remainingSendByteCount / 2U) - 1U; - } - - EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, - (const edma_transfer_config_t *)(uint32_t)&transferConfigC, softwareTCD); - } - else - { - transferConfigC.majorLoopCounts = 1; - - EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, - (const edma_transfer_config_t *)(uint32_t)&transferConfigC, NULL); - } - - EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, false); - } - else - { - EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, - (const edma_transfer_config_t *)(uint32_t)&transferConfigC, NULL); - } - - /*Start the EDMA channel_A , channel_B , channel_C transfer*/ - EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_StartTransfer(handle->edmaTxDataToIntermediaryHandle); - EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle); - - /*Set channel priority*/ - uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; - uint8_t channelPriorityMid = handle->edmaTxDataToIntermediaryHandle->channel; - uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel; - uint8_t t = 0; - if (channelPriorityLow > channelPriorityMid) - { - t = channelPriorityLow; - channelPriorityLow = channelPriorityMid; - channelPriorityMid = t; - } - - if (channelPriorityLow > channelPriorityHigh) - { - t = channelPriorityLow; - channelPriorityLow = channelPriorityHigh; - channelPriorityHigh = t; - } - - if (channelPriorityMid > channelPriorityHigh) - { - t = channelPriorityMid; - channelPriorityMid = channelPriorityHigh; - channelPriorityHigh = t; - } - edma_channel_Preemption_config_t preemption_config_t; - preemption_config_t.enableChannelPreemption = true; - preemption_config_t.enablePreemptAbility = true; - preemption_config_t.channelPriority = channelPriorityLow; - - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - (const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityMid; - EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, - (const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityHigh; - EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, - (const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t); - } - else - { - EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, - (const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityMid; - EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, - (const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityHigh; - EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - (const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t); - } - - /*Set the channel link.*/ - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - /*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB - to prepare the next 32bits data (txData to handle->command) */ - if (handle->remainingSendByteCount > 1U) - { - EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MajorLink, - handle->edmaTxDataToIntermediaryHandle->channel); - } - - DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable); - } - else - { - if (handle->remainingSendByteCount > 0U) - { - EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MinorLink, handle->edmaTxDataToIntermediaryHandle->channel); - - EDMA_SetChannelLink(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, kEDMA_MinorLink, - handle->edmaIntermediaryToTxRegHandle->channel); - } - - DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable); - } -#endif - DSPI_StartTransfer(base); - - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a eDMA method. - * - * This function transfers data using eDNA, the transfer mechanism is half-duplex. This is a non-blocking function, - * which returns right away. When all data is transferred, the callback function is called. - * - * param base DSPI base pointer - * param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state. - * param transfer A pointer to the dspi_half_duplex_transfer_t structure. - * return status of status_t. - */ -status_t DSPI_MasterHalfDuplexTransferEDMA(SPI_Type *base, - dspi_master_edma_handle_t *handle, - dspi_half_duplex_transfer_t *xfer) -{ - assert(NULL != xfer); - assert(NULL != handle); - dspi_transfer_t tempXfer = {0}; - status_t status; - - if (true == xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (true == xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kDSPI_MasterActiveAfterTransfer; - } - else - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kDSPI_MasterActiveAfterTransfer); - } - - status = DSPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (true == xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = DSPI_MasterTransferEDMA(base, handle, &tempXfer); - - return status; -} -static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, - void *g_dspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds) -{ - assert(NULL != edmaHandle); - assert(NULL != g_dspiEdmaPrivateHandle); - - dspi_master_edma_private_handle_t *dspiEdmaPrivateHandle; - - dspiEdmaPrivateHandle = (dspi_master_edma_private_handle_t *)g_dspiEdmaPrivateHandle; - - DSPI_DisableDMA((dspiEdmaPrivateHandle->base), (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable); - - dspiEdmaPrivateHandle->handle->state = (uint8_t)kDSPI_Idle; - - if (NULL != dspiEdmaPrivateHandle->handle->callback) - { - dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle, - kStatus_Success, dspiEdmaPrivateHandle->handle->userData); - } -} - -/*! - * brief DSPI master aborts a transfer which is using eDMA. - * - * This function aborts a transfer which is using eDMA. - * - * param base DSPI peripheral base address. - * param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state. - */ -void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle) -{ - assert(NULL != handle); - - DSPI_StopTransfer(base); - - DSPI_DisableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable); - - EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_AbortTransfer(handle->edmaTxDataToIntermediaryHandle); - EDMA_AbortTransfer(handle->edmaIntermediaryToTxRegHandle); - - handle->state = (uint8_t)kDSPI_Idle; -} - -/*! - * brief Gets the master eDMA transfer count. - * - * This function gets the master eDMA transfer count. - * - * param base DSPI peripheral base address. - * param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state. - * param count A number of bytes transferred by the non-blocking transaction. - * return status of status_t. - */ -status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint8_t)kDSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, - handle->edmaRxRegToRxDataHandle->channel); - - *count = handle->totalByteCount - bytes; - - return kStatus_Success; -} - -/*! - * brief Initializes the DSPI slave eDMA handle. - * - * This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs. Usually, for a - * specified DSPI instance, call this API once to get the initialized handle. - * - * Note that DSPI eDMA has separated (RN and TX in 2 sources) or shared (RX and TX are the same source) DMA request - * source. - * (1)For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and - * TX DMAMUX source for edmaTxDataToTxRegHandle. - * (2)For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle. - * - * param base DSPI peripheral base address. - * param handle DSPI handle pointer to dspi_slave_edma_handle_t. - * param callback DSPI callback. - * param userData A callback function parameter. - * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. - * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. - */ -void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base, - dspi_slave_edma_handle_t *handle, - dspi_slave_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaRxRegToRxDataHandle, - edma_handle_t *edmaTxDataToTxRegHandle) -{ - assert(NULL != handle); - assert(NULL != edmaRxRegToRxDataHandle); - assert(NULL != edmaTxDataToTxRegHandle); - - /* Zero the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - uint32_t instance = DSPI_GetInstance(base); - - s_dspiSlaveEdmaPrivateHandle[instance].base = base; - s_dspiSlaveEdmaPrivateHandle[instance].handle = handle; - - handle->callback = callback; - handle->userData = userData; - - handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; - handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; -} - -/*! - * brief DSPI slave transfer data using eDMA. - * - * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data - * is transferred, the callback function is called. - * Note that the slave eDMA transfer doesn't support transfer_size is 1 when the bitsPerFrame is greater - * than eight. - - * param base DSPI peripheral base address. - * param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state. - * param transfer A pointer to the dspi_transfer_t structure. - * return status of status_t. - */ -status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer) -{ - assert(NULL != handle); - assert(NULL != transfer); - - /* If send/receive length is zero */ - if (transfer->dataSize == 0U) - { - return kStatus_InvalidArgument; - } - - /* If both send buffer and receive buffer is null */ - if ((NULL == (transfer->txData)) && (NULL == (transfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == (uint8_t)kDSPI_Busy) - { - return kStatus_DSPI_Busy; - } - - handle->state = (uint8_t)kDSPI_Busy; - - uint32_t instance = DSPI_GetInstance(base); - uint8_t whichCtar = (uint8_t)((transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT); - handle->bitsPerFrame = - (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1U; - - /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer - * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame - */ - uint32_t limited_size = 0; - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - limited_size = 32767u; - } - else - { - limited_size = 511u; - } - - if (handle->bitsPerFrame > 8U) - { - if (transfer->dataSize > (limited_size << 1u)) - { - handle->state = (uint8_t)kDSPI_Idle; - return kStatus_DSPI_OutOfRange; - } - } - else - { - if (transfer->dataSize > limited_size) - { - handle->state = (uint8_t)kDSPI_Idle; - return kStatus_DSPI_OutOfRange; - } - } - - /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */ - if ((0U != (transfer->dataSize & 0x1U)) && (handle->bitsPerFrame > 8U)) - { - handle->state = (uint8_t)kDSPI_Idle; - return kStatus_InvalidArgument; - } - - EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]); - - /* Store transfer information */ - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->remainingSendByteCount = transfer->dataSize; - handle->remainingReceiveByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - uint32_t wordToSend = 0; - uint8_t dummyData = DSPI_GetDummyDataInstance(base); - uint8_t dataAlreadyFed = 0; - uint8_t dataFedMax = 2; - - uint32_t rxAddr = DSPI_GetRxRegisterAddress(base); - uint32_t txAddr = DSPI_SlaveGetTxRegisterAddress(base); - - edma_transfer_config_t transferConfigA; - edma_transfer_config_t transferConfigC; - - DSPI_StopTransfer(base); - - DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag); - - DSPI_DisableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable); - - DSPI_StartTransfer(base); - - /*if dspi has separate dma request , need not prepare data first . - else (dspi has shared dma request) , send first 2 data into fifo if there is fifo or send first 1 data to - slaveGetTxRegister if there is no fifo*/ - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to - * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. - */ - /* If bits/frame is greater than one byte */ - if (handle->bitsPerFrame > 8U) - { - while ((uint32_t)kDSPI_TxFifoFillRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - if (NULL != handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; /* Increment to next data byte */ - - wordToSend |= (unsigned)(*(handle->txData)) << 8U; - ++handle->txData; /* Increment to next data byte */ - } - else - { - wordToSend = ((uint32_t)dummyData << 8U) | dummyData; - } - handle->remainingSendByteCount -= 2U; /* decrement remainingSendByteCount by 2 */ - base->PUSHR_SLAVE = wordToSend; - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - - dataAlreadyFed += 2U; - - /* Exit loop if send count is zero, else update local variables for next loop */ - if ((handle->remainingSendByteCount == 0U) || (dataAlreadyFed == (dataFedMax * 2U))) - { - break; - } - } /* End of TX FIFO fill while loop */ - } - else /* Optimized for bits/frame less than or equal to one byte. */ - { - while ((uint32_t)kDSPI_TxFifoFillRequestFlag == - (DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag)) - { - if (NULL != handle->txData) - { - wordToSend = *(handle->txData); - /* Increment to next data word*/ - ++handle->txData; - } - else - { - wordToSend = dummyData; - } - - base->PUSHR_SLAVE = wordToSend; - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag); - /* Decrement remainingSendByteCount*/ - --handle->remainingSendByteCount; - - dataAlreadyFed++; - - /* Exit loop if send count is zero, else update local variables for next loop */ - if ((handle->remainingSendByteCount == 0U) || (dataAlreadyFed == dataFedMax)) - { - break; - } - } /* End of TX FIFO fill while loop */ - } - } - - /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/ - if (handle->remainingReceiveByteCount > 0U) - { - EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); - - transferConfigA.srcAddr = (uint32_t)rxAddr; - transferConfigA.srcOffset = 0; - - if (NULL != handle->rxData) - { - transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]); - transferConfigA.destOffset = 1; - } - else - { - transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull); - transferConfigA.destOffset = 0; - } - - transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes; - - if (handle->bitsPerFrame <= 8U) - { - transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigA.minorLoopBytes = 1; - transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount; - } - else - { - transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfigA.minorLoopBytes = 2; - transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2U; - } - - /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ - handle->nbytes = (uint8_t)(transferConfigA.minorLoopBytes); - - EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - (const edma_transfer_config_t *)(uint32_t)&transferConfigA, NULL); - EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - (uint32_t)kEDMA_MajorInterruptEnable); - } - - if (handle->remainingSendByteCount > 0U) - { - /***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/ - EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); - - transferConfigC.destAddr = (uint32_t)txAddr; - transferConfigC.destOffset = 0; - - if (NULL != handle->txData) - { - transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0])); - transferConfigC.srcOffset = 1; - } - else - { - transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigC.srcOffset = 0; - if (handle->bitsPerFrame <= 8U) - { - handle->txBuffIfNull = dummyData; - } - else - { - handle->txBuffIfNull = ((uint32_t)dummyData << 8U) | dummyData; - } - } - - transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes; - - if (handle->bitsPerFrame <= 8U) - { - transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigC.minorLoopBytes = 1; - transferConfigC.majorLoopCounts = handle->remainingSendByteCount; - } - else - { - transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigC.minorLoopBytes = 2; - transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2U; - } - - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - (const edma_transfer_config_t *)(uint32_t)&transferConfigC, NULL); - - EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); - } - - EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); - - /*Set channel priority*/ - uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; - uint8_t channelPriorityHigh = handle->edmaTxDataToTxRegHandle->channel; - uint8_t t = 0; - - if (channelPriorityLow > channelPriorityHigh) - { - t = channelPriorityLow; - channelPriorityLow = channelPriorityHigh; - channelPriorityHigh = t; - } - - edma_channel_Preemption_config_t preemption_config_t; - preemption_config_t.enableChannelPreemption = true; - preemption_config_t.enablePreemptAbility = true; - preemption_config_t.channelPriority = channelPriorityLow; - - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - (const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityHigh; - EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - (const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t); - } - else - { - EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - (const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityHigh; - EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - (const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t); - } - - /*Set the channel link. - For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_C. - For DSPI instances with separate RX and TX DMA requests: - Rx DMA request -> channel_A - Tx DMA request -> channel_C */ - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - if (handle->remainingSendByteCount > 0U) - { - EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MinorLink, handle->edmaTxDataToTxRegHandle->channel); - } - DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable); - } - else - { - DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable); - } - - return kStatus_Success; -} - -static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, - void *g_dspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds) -{ - assert(NULL != edmaHandle); - assert(NULL != g_dspiEdmaPrivateHandle); - - dspi_slave_edma_private_handle_t *dspiEdmaPrivateHandle; - - dspiEdmaPrivateHandle = (dspi_slave_edma_private_handle_t *)g_dspiEdmaPrivateHandle; - - DSPI_DisableDMA((dspiEdmaPrivateHandle->base), (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable); - - dspiEdmaPrivateHandle->handle->state = (uint8_t)kDSPI_Idle; - - if (NULL != dspiEdmaPrivateHandle->handle->callback) - { - dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle, - kStatus_Success, dspiEdmaPrivateHandle->handle->userData); - } -} - -/*! - * brief DSPI slave aborts a transfer which is using eDMA. - * - * This function aborts a transfer which is using eDMA. - * - * param base DSPI peripheral base address. - * param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state. - */ -void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle) -{ - assert(NULL != handle); - - DSPI_StopTransfer(base); - - DSPI_DisableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable); - - EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); - - handle->state = (uint8_t)kDSPI_Idle; -} - -/*! - * brief Gets the slave eDMA transfer count. - * - * This function gets the slave eDMA transfer count. - * - * param base DSPI peripheral base address. - * param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state. - * param count A number of bytes transferred so far by the non-blocking transaction. - * return status of status_t. - */ -status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint8_t)kDSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, - handle->edmaRxRegToRxDataHandle->channel); - - *count = handle->totalByteCount - bytes; - - return kStatus_Success; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi_edma.h deleted file mode 100644 index 8f4ffe9..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi_edma.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_DSPI_EDMA_H_ -#define _FSL_DSPI_EDMA_H_ - -#include "fsl_dspi.h" -#include "fsl_edma.h" -/*! - * @addtogroup dspi_edma_driver - * @{ - */ - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DSPI EDMA driver version 2.2.2. */ -#define FSL_DSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) -/*@}*/ - -/*! - * @brief Forward declaration of the DSPI eDMA master handle typedefs. - */ -typedef struct _dspi_master_edma_handle dspi_master_edma_handle_t; - -/*! - * @brief Forward declaration of the DSPI eDMA slave handle typedefs. - */ -typedef struct _dspi_slave_edma_handle dspi_slave_edma_handle_t; - -/*! - * @brief Completion callback function pointer type. - * - * @param base DSPI peripheral base address. - * @param handle A pointer to the handle for the DSPI master. - * @param status Success or error code describing whether the transfer completed. - * @param userData An arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*dspi_master_edma_transfer_callback_t)(SPI_Type *base, - dspi_master_edma_handle_t *handle, - status_t status, - void *userData); -/*! - * @brief Completion callback function pointer type. - * - * @param base DSPI peripheral base address. - * @param handle A pointer to the handle for the DSPI slave. - * @param status Success or error code describing whether the transfer completed. - * @param userData An arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*dspi_slave_edma_transfer_callback_t)(SPI_Type *base, - dspi_slave_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief DSPI master eDMA transfer handle structure used for the transactional API. */ -struct _dspi_master_edma_handle -{ - uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ - volatile uint32_t command; /*!< The desired data command. */ - volatile uint32_t lastCommand; /*!< The desired last data command. */ - - uint8_t fifoSize; /*!< FIFO dataSize. */ - - volatile bool - isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal keeps active after the last frame transfer.*/ - - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ - volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ - size_t totalByteCount; /*!< A number of transfer bytes*/ - - uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ - uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ - - dspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ - - edma_handle_t *edmaRxRegToRxDataHandle; /*!TCD[channel].SADDR = tcd->SADDR; - base->TCD[channel].SOFF = tcd->SOFF; - base->TCD[channel].ATTR = tcd->ATTR; - base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; - base->TCD[channel].SLAST = tcd->SLAST; - base->TCD[channel].DADDR = tcd->DADDR; - base->TCD[channel].DOFF = tcd->DOFF; - base->TCD[channel].CITER_ELINKNO = tcd->CITER; - base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; - /* Clear DONE bit first, otherwise ESG cannot be set */ - base->TCD[channel].CSR = 0; - base->TCD[channel].CSR = tcd->CSR; - base->TCD[channel].BITER_ELINKNO = tcd->BITER; -} - -void EDMA_Init(DMA_Type *base, const edma_config_t *config) -{ - assert(config != NULL); - - uint32_t tmpreg; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate EDMA periphral clock */ - CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Configure EDMA peripheral according to the configuration structure. */ - tmpreg = base->CR; - tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); - tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | - DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true)); - base->CR = tmpreg; -} - -void EDMA_Deinit(DMA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate EDMA periphral clock */ - CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void EDMA_GetDefaultConfig(edma_config_t *config) -{ - assert(config != NULL); - - config->enableRoundRobinArbitration = false; - config->enableHaltOnError = true; - config->enableContinuousLinkMode = false; - config->enableDebugMode = false; -} - -void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); -} - -void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0); - - EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); -} - -void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - - uint32_t tmpreg; - - tmpreg = base->TCD[channel].NBYTES_MLOFFYES; - tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); - tmpreg |= - (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | - DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); - base->TCD[channel].NBYTES_MLOFFYES = tmpreg; -} - -void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); -} - -void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); -} - -void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t tmpreg; - - tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); -} - -void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Enable error interrupt */ - if (mask & kEDMA_ErrorInterruptEnable) - { - base->EEI |= (0x1U << channel); - } - - /* Enable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; - } - - /* Enable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Disable error interrupt */ - if (mask & kEDMA_ErrorInterruptEnable) - { - base->EEI &= ~(0x1U << channel); - } - - /* Disable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; - } - - /* Disable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_TcdReset(edma_tcd_t *tcd) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - /* Reset channel TCD */ - tcd->SADDR = 0U; - tcd->SOFF = 0U; - tcd->ATTR = 0U; - tcd->NBYTES = 0U; - tcd->SLAST = 0U; - tcd->DADDR = 0U; - tcd->DOFF = 0U; - tcd->CITER = 0U; - tcd->DLAST_SGA = 0U; - /* Enable auto disable request feature */ - tcd->CSR = DMA_CSR_DREQ(true); - tcd->BITER = 0U; -} - -void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0); - - /* source address */ - tcd->SADDR = config->srcAddr; - /* destination address */ - tcd->DADDR = config->destAddr; - /* Source data and destination data transfer size */ - tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); - /* Source address signed offset */ - tcd->SOFF = config->srcOffset; - /* Destination address signed offset */ - tcd->DOFF = config->destOffset; - /* Minor byte transfer count */ - tcd->NBYTES = config->minorLoopBytes; - /* Current major iteration count */ - tcd->CITER = config->majorLoopCounts; - /* Starting major iteration count */ - tcd->BITER = config->majorLoopCounts; - /* Enable scatter/gather processing */ - if (nextTcd != NULL) - { - tcd->DLAST_SGA = (uint32_t)nextTcd; - /* - Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, - user must call EDMA_TcdReset or EDMA_ResetChannel which will set - DREQ, so must use "|" or "&" rather than "=". - - Clear the DREQ bit because scatter gather has been enabled, so the - previous transfer is not the last transfer, and channel request should - be enabled at the next transfer(the next TCD). - */ - tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - } -} - -void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - uint32_t tmpreg; - - tmpreg = tcd->NBYTES & - ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); - tmpreg |= - (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | - DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); - tcd->NBYTES = tmpreg; -} - -void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if (type == kEDMA_MinorLink) /* Minor link config */ - { - uint32_t tmpreg; - - /* Enable minor link */ - tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; - /* Set likned channel */ - tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK); - tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); - tcd->CITER = tmpreg; - tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK); - tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); - tcd->BITER = tmpreg; - } - else if (type == kEDMA_MajorLink) /* Major link config */ - { - uint32_t tmpreg; - - /* Enable major link */ - tcd->CSR |= DMA_CSR_MAJORELINK_MASK; - /* Set major linked channel */ - tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK); - tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); - } - else /* Link none */ - { - tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK; - tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK; - } -} - -void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - uint32_t tmpreg; - - tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); -} - -void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) -{ - assert(tcd != NULL); - - /* Enable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - tcd->CSR |= DMA_CSR_INTMAJOR_MASK; - } - - /* Enable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - tcd->CSR |= DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) -{ - assert(tcd != NULL); - - /* Disable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK; - } - - /* Disable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - tcd->CSR &= ~DMA_CSR_INTHALF_MASK; - } -} - -uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t remainingCount = 0; - - if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR) - { - remainingCount = 0; - } - else - { - /* Calculate the unfinished bytes */ - if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK) - { - remainingCount = - (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT; - } - else - { - remainingCount = - (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT; - } - } - - return remainingCount; -} - -uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t retval = 0; - - /* Get DONE bit flag */ - retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); - /* Get ERROR bit flag */ - retval |= (((base->ERR >> channel) & 0x1U) << 1U); - /* Get INT bit flag */ - retval |= (((base->INT >> channel) & 0x1U) << 2U); - - return retval; -} - -void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Clear DONE bit flag */ - if (mask & kEDMA_DoneFlag) - { - base->CDNE = channel; - } - /* Clear ERROR bit flag */ - if (mask & kEDMA_ErrorFlag) - { - base->CERR = channel; - } - /* Clear INT bit flag */ - if (mask & kEDMA_InterruptFlag) - { - base->CINT = channel; - } -} - -void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert(handle != NULL); - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t edmaInstance; - uint32_t channelIndex; - edma_tcd_t *tcdRegs; - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - handle->base = base; - handle->channel = channel; - /* Get the DMA instance number */ - edmaInstance = EDMA_GetInstance(base); - channelIndex = (edmaInstance * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; - s_EDMAHandle[channelIndex] = handle; - - /* Enable NVIC interrupt */ - EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); - - /* - Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), - CSR will be 0. Because in order to suit EDMA busy check mechanism in - EDMA_SubmitTransfer, CSR must be set 0. - */ - tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - tcdRegs->SADDR = 0; - tcdRegs->SOFF = 0; - tcdRegs->ATTR = 0; - tcdRegs->NBYTES = 0; - tcdRegs->SLAST = 0; - tcdRegs->DADDR = 0; - tcdRegs->DOFF = 0; - tcdRegs->CITER = 0; - tcdRegs->DLAST_SGA = 0; - tcdRegs->CSR = 0; - tcdRegs->BITER = 0; -} - -void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) -{ - assert(handle != NULL); - assert(((uint32_t)tcdPool & 0x1FU) == 0); - - /* Initialize tcd queue attibute. */ - handle->header = 0; - handle->tail = 0; - handle->tcdUsed = 0; - handle->tcdSize = tcdSize; - handle->flags = 0; - handle->tcdPool = tcdPool; -} - -void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -void EDMA_PrepareTransfer(edma_transfer_config_t *config, - void *srcAddr, - uint32_t srcWidth, - void *destAddr, - uint32_t destWidth, - uint32_t bytesEachRequest, - uint32_t transferBytes, - edma_transfer_type_t type) -{ - assert(config != NULL); - assert(srcAddr != NULL); - assert(destAddr != NULL); - assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U)); - assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U)); - assert(transferBytes % bytesEachRequest == 0); - - config->destAddr = (uint32_t)destAddr; - config->srcAddr = (uint32_t)srcAddr; - config->minorLoopBytes = bytesEachRequest; - config->majorLoopCounts = transferBytes / bytesEachRequest; - switch (srcWidth) - { - case 1U: - config->srcTransferSize = kEDMA_TransferSize1Bytes; - break; - case 2U: - config->srcTransferSize = kEDMA_TransferSize2Bytes; - break; - case 4U: - config->srcTransferSize = kEDMA_TransferSize4Bytes; - break; - case 16U: - config->srcTransferSize = kEDMA_TransferSize16Bytes; - break; - case 32U: - config->srcTransferSize = kEDMA_TransferSize32Bytes; - break; - default: - break; - } - switch (destWidth) - { - case 1U: - config->destTransferSize = kEDMA_TransferSize1Bytes; - break; - case 2U: - config->destTransferSize = kEDMA_TransferSize2Bytes; - break; - case 4U: - config->destTransferSize = kEDMA_TransferSize4Bytes; - break; - case 16U: - config->destTransferSize = kEDMA_TransferSize16Bytes; - break; - case 32U: - config->destTransferSize = kEDMA_TransferSize32Bytes; - break; - default: - break; - } - switch (type) - { - case kEDMA_MemoryToMemory: - config->destOffset = destWidth; - config->srcOffset = srcWidth; - break; - case kEDMA_MemoryToPeripheral: - config->destOffset = 0U; - config->srcOffset = srcWidth; - break; - case kEDMA_PeripheralToMemory: - config->destOffset = destWidth; - config->srcOffset = 0U; - break; - default: - break; - } -} - -status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) -{ - assert(handle != NULL); - assert(config != NULL); - - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - - if (handle->tcdPool == NULL) - { - /* - Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because - if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit - this check mechanism, EDMA_CreatHandle will clear CSR register. - */ - if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0)) - { - return kStatus_EDMA_Busy; - } - else - { - EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL); - /* Enable auto disable request feature */ - handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK; - /* Enable major interrupt */ - handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK; - - return kStatus_Success; - } - } - else /* Use the TCD queue. */ - { - uint32_t primask; - uint32_t csr; - int8_t currentTcd; - int8_t previousTcd; - int8_t nextTcd; - - /* Check if tcd pool is full. */ - primask = DisableGlobalIRQ(); - if (handle->tcdUsed >= handle->tcdSize) - { - EnableGlobalIRQ(primask); - - return kStatus_EDMA_QueueFull; - } - currentTcd = handle->tail; - handle->tcdUsed++; - /* Calculate index of next TCD */ - nextTcd = currentTcd + 1U; - if (nextTcd == handle->tcdSize) - { - nextTcd = 0U; - } - /* Advance queue tail index */ - handle->tail = nextTcd; - EnableGlobalIRQ(primask); - /* Calculate index of previous TCD */ - previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; - /* Configure current TCD block. */ - EDMA_TcdReset(&handle->tcdPool[currentTcd]); - EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); - /* Enable major interrupt */ - handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; - /* Link current TCD with next TCD for identification of current TCD */ - handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; - /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ - if (currentTcd != previousTcd) - { - /* Enable scatter/gather feature in the previous TCD block. */ - csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - handle->tcdPool[previousTcd].CSR = csr; - /* - Check if the TCD blcok in the registers is the previous one (points to current TCD block). It - is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to - link the TCD register in case link the current TCD with the dead chain when TCD loading occurs - before link the previous TCD block. - */ - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) - { - /* Enable scatter/gather also in the TCD registers. */ - csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ - tcdRegs->CSR = csr; - /* - It is very important to check the ESG bit! - Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can - be used to check if the dynamic TCD link operation is successful. If ESG bit is not set - and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and - the current TCD block has been loaded into TCD registers), it means transfer finished - and TCD link operation fail, so must install TCD content into TCD registers and enable - transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic - link succeed. - */ - if (tcdRegs->CSR & DMA_CSR_ESG_MASK) - { - return kStatus_Success; - } - /* - Check whether the current TCD block is already loaded in the TCD registers. It is another - condition when ESG bit is not set: it means the dynamic TCD link succeed and the current - TCD block has been loaded into TCD registers. - */ - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) - { - return kStatus_Success; - } - /* - If go to this, means the previous transfer finished, and the DONE bit is set. - So shall configure TCD registers. - */ - } - else if (tcdRegs->DLAST_SGA != 0) - { - /* The current TCD block has been linked successfully. */ - return kStatus_Success; - } - else - { - /* - DLAST_SGA is 0 and it means the first submit transfer, so shall configure - TCD registers. - */ - } - } - /* There is no live chain, TCD block need to be installed in TCD registers. */ - EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); - /* Enable channel request again. */ - if (handle->flags & EDMA_TRANSFER_ENABLED_MASK) - { - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - - return kStatus_Success; - } -} - -void EDMA_StartTransfer(edma_handle_t *handle) -{ - assert(handle != NULL); - - if (handle->tcdPool == NULL) - { - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - else /* Use the TCD queue. */ - { - uint32_t primask; - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - - handle->flags |= EDMA_TRANSFER_ENABLED_MASK; - - /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ - if (tcdRegs->DLAST_SGA != 0U) - { - primask = DisableGlobalIRQ(); - /* Check if channel request is actually disable. */ - if ((handle->base->ERQ & (1U << handle->channel)) == 0U) - { - /* Check if transfer is paused. */ - if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK)) - { - /* - Re-enable channel request must be as soon as possible, so must put it into - critical section to avoid task switching or interrupt service routine. - */ - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - } - EnableGlobalIRQ(primask); - } - } -} - -void EDMA_StopTransfer(edma_handle_t *handle) -{ - assert(handle != NULL); - - handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK); - handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); -} - -void EDMA_AbortTransfer(edma_handle_t *handle) -{ - handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); - /* - Clear CSR to release channel. Because if the given channel started transfer, - CSR will be not zero. Because if it is the last transfer, DREQ will be set. - If not, ESG will be set. - */ - handle->base->TCD[handle->channel].CSR = 0; - /* Cancel all next TCD transfer. */ - handle->base->TCD[handle->channel].DLAST_SGA = 0; -} - -void EDMA_HandleIRQ(edma_handle_t *handle) -{ - assert(handle != NULL); - - /* Clear EDMA interrupt flag */ - handle->base->CINT = handle->channel; - if ((handle->tcdPool == NULL) && (handle->callback != NULL)) - { - (handle->callback)(handle, handle->userData, true, 0); - } - else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ - { - uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA; - uint32_t sga_index; - int32_t tcds_done; - uint8_t new_header; - bool transfer_done; - - /* Check if transfer is already finished. */ - transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0); - /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */ - sga -= (uint32_t)handle->tcdPool; - /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */ - sga_index = sga / sizeof(edma_tcd_t); - /* Adjust header positions. */ - if (transfer_done) - { - /* New header shall point to the next TCD to be loaded (current one is already finished) */ - new_header = sga_index; - } - else - { - /* New header shall point to this descriptor currently loaded (not finished yet) */ - new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U; - } - /* Calculate the number of finished TCDs */ - if (new_header == handle->header) - { - if (handle->tcdUsed == handle->tcdSize) - { - tcds_done = handle->tcdUsed; - } - else - { - /* No TCD in the memory are going to be loaded or internal error occurs. */ - tcds_done = 0; - } - } - else - { - tcds_done = new_header - handle->header; - if (tcds_done < 0) - { - tcds_done += handle->tcdSize; - } - } - /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ - handle->header = new_header; - /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ - handle->tcdUsed -= tcds_done; - /* Invoke callback function. */ - if (handle->callback) - { - (handle->callback)(handle, handle->userData, transfer_done, tcds_done); - } - } -} - -/* 8 channels (Shared): kl28 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U - -void DMA0_04_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } -} - -void DMA0_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } -} - -void DMA0_26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } -} - -void DMA0_37_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } -} - -#if defined(DMA1) -void DMA1_04_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } -} - -void DMA1_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } -} - -void DMA1_26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } -} - -void DMA1_37_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } -} -#endif -#endif /* 8 channels (Shared) */ - -/* 16 channels (Shared): K32H844P */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U - -void DMA0_08_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } -} - -void DMA0_19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } -} - -void DMA0_210_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } -} - -void DMA0_311_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } -} - -void DMA0_412_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } -} - -void DMA0_513_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } -} - -void DMA0_614_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } -} - -void DMA0_715_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } -} - -#if defined(DMA1) -void DMA1_08_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } -} - -void DMA1_19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } -} - -void DMA1_210_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } -} - -void DMA1_311_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } -} - -void DMA1_412_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } -} - -void DMA1_513_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } -} - -void DMA1_614_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } -} - -void DMA1_715_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } -} -#endif -#endif /* 16 channels (Shared) */ - -/* 32 channels (Shared): k80 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U - -void DMA0_DMA16_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } -} - -void DMA1_DMA17_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } -} - -void DMA2_DMA18_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } -} - -void DMA3_DMA19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } -} - -void DMA4_DMA20_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } -} - -void DMA5_DMA21_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } -} - -void DMA6_DMA22_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } -} - -void DMA7_DMA23_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } -} - -void DMA8_DMA24_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } -} - -void DMA9_DMA25_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } -} - -void DMA10_DMA26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } -} - -void DMA11_DMA27_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } -} - -void DMA12_DMA28_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } -} - -void DMA13_DMA29_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } -} - -void DMA14_DMA30_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } -} - -void DMA15_DMA31_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } -} -#endif /* 32 channels (Shared) */ - -/* 32 channels (Shared): MCIMX7U5_M4 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U - -void DMA0_0_4_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } -} - -void DMA0_1_5_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } -} - -void DMA0_2_6_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } -} - -void DMA0_3_7_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } -} - -void DMA0_8_12_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } -} - -void DMA0_9_13_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } -} - -void DMA0_10_14_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } -} - -void DMA0_11_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } -} - -void DMA0_16_20_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } -} - -void DMA0_17_21_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } -} - -void DMA0_18_22_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } -} - -void DMA0_19_23_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } -} - -void DMA0_24_28_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } -} - -void DMA0_25_29_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } -} - -void DMA0_26_30_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } -} - -void DMA0_27_31_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } -} -#endif /* 32 channels (Shared): MCIMX7U5 */ - -/* 4 channels (No Shared): kv10 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0 - -void DMA0_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[0]); -} - -void DMA1_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[1]); -} - -void DMA2_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[2]); -} - -void DMA3_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[3]); -} - -/* 8 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U - -void DMA4_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[4]); -} - -void DMA5_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[5]); -} - -void DMA6_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[6]); -} - -void DMA7_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[7]); -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */ - -/* 16 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U - -void DMA8_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[8]); -} - -void DMA9_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[9]); -} - -void DMA10_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[10]); -} - -void DMA11_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[11]); -} - -void DMA12_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[12]); -} - -void DMA13_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[13]); -} - -void DMA14_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[14]); -} - -void DMA15_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[15]); -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */ - -/* 32 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U - -void DMA16_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[16]); -} - -void DMA17_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[17]); -} - -void DMA18_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[18]); -} - -void DMA19_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[19]); -} - -void DMA20_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[20]); -} - -void DMA21_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[21]); -} - -void DMA22_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[22]); -} - -void DMA23_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[23]); -} - -void DMA24_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[24]); -} - -void DMA25_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[25]); -} - -void DMA26_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[26]); -} - -void DMA27_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[27]); -} - -void DMA28_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[28]); -} - -void DMA29_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[29]); -} - -void DMA30_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[30]); -} - -void DMA31_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[31]); -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */ - -#endif /* 4/8/16/32 channels (No Shared) */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_edma.h deleted file mode 100644 index a97622d..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_edma.h +++ /dev/null @@ -1,910 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_EDMA_H_ -#define _FSL_EDMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup edma - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */ -/*@}*/ - -/*! @brief Compute the offset unit from DCHPRI3 */ -#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) - -/*! @brief Get the pointer of DCHPRIn */ -#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] - -/*! @brief eDMA transfer configuration */ -typedef enum _edma_transfer_size -{ - kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ - kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ - kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ - kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ - kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ -} edma_transfer_size_t; - -/*! @brief eDMA modulo configuration */ -typedef enum _edma_modulo -{ - kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ - kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ - kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ - kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ - kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ - kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ - kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ - kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ - kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ - kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ - kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */ - kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */ - kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */ - kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */ - kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */ - kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */ - kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */ - kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */ - kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */ - kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */ - kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */ - kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */ - kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */ - kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */ - kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */ - kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */ - kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */ - kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */ - kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */ - kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */ - kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */ - kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */ -} edma_modulo_t; - -/*! @brief Bandwidth control */ -typedef enum _edma_bandwidth -{ - kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ - kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ - kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ -} edma_bandwidth_t; - -/*! @brief Channel link type */ -typedef enum _edma_channel_link_type -{ - kEDMA_LinkNone = 0x0U, /*!< No channel link */ - kEDMA_MinorLink, /*!< Channel link after each minor loop */ - kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ -} edma_channel_link_type_t; - -/*!@brief eDMA channel status flags. */ -enum _edma_channel_status_flags -{ - kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ - kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ - kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ -}; - -/*! @brief eDMA channel error status flags. */ -enum _edma_error_status_flags -{ - kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ - kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ - kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ - kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ - kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ - kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ - kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ - kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ - kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ - kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ - kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ -#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 - kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ -#endif - kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ -}; - -/*! @brief eDMA interrupt source */ -typedef enum _edma_interrupt_enable -{ - kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ - kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ - kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ -} edma_interrupt_enable_t; - -/*! @brief eDMA transfer type */ -typedef enum _edma_transfer_type -{ - kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ - kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ - kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ -} edma_transfer_type_t; - -/*! @brief eDMA transfer status */ -enum _edma_transfer_status -{ - kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ - kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief eDMA global configuration structure.*/ -typedef struct _edma_config -{ - bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel - activates again if that channel has a minor loop channel link enabled and - the link channel is itself. */ - bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. - Subsequently, all service requests are ignored until the HALT bit is cleared.*/ - bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method or fixed priority - arbitration is used for channel selection */ - bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of - a new channel. Executing channels are allowed to complete. */ -} edma_config_t; - -/*! - * @brief eDMA transfer configuration - * - * This structure configures the source/destination transfer attribute. - * This figure shows the eDMA's transfer model: - * _________________________________________________ - * | Transfer Size | | - * Minor Loop |_______________| Major loop Count 1 | - * Bytes | Transfer Size | | - * ____________|_______________|____________________|--> Minor loop complete - * ____________________________________ - * | | | - * |_______________| Major Loop Count 2 | - * | | | - * |_______________|____________________|--> Minor loop Complete - * - * ---------------------------------------------------------> Transfer complete - */ -typedef struct _edma_transfer_config -{ - uint32_t srcAddr; /*!< Source data address. */ - uint32_t destAddr; /*!< Destination data address. */ - edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ - edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ - int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to - form the next-state value as each source read is completed. */ - int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to - form the next-state value as each destination write is completed. */ - uint32_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/ - uint32_t majorLoopCounts; /*!< Major loop iteration count. */ -} edma_transfer_config_t; - -/*! @brief eDMA channel priority configuration */ -typedef struct _edma_channel_Preemption_config -{ - bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */ - bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */ - uint8_t channelPriority; /*!< Channel priority */ -} edma_channel_Preemption_config_t; - -/*! @brief eDMA minor offset configuration */ -typedef struct _edma_minor_offset_config -{ - bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ - bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ - uint32_t minorOffset; /*!< Offset for a minor loop mapping. */ -} edma_minor_offset_config_t; - -/*! - * @brief eDMA TCD. - * - * This structure is same as TCD register which is described in reference manual, - * and is used to configure the scatter/gather feature as a next hardware TCD. - */ -typedef struct _edma_tcd -{ - __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ - __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ - __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ - __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ - __IO uint32_t SLAST; /*!< SLAST register */ - __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ - __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ - __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ - __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */ - __IO uint16_t CSR; /*!< CSR register, for TCD control status */ - __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ -} edma_tcd_t; - -/*! @brief Callback for eDMA */ -struct _edma_handle; - -/*! @brief Define callback function for eDMA. */ -typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! @brief eDMA transfer handle structure */ -typedef struct _edma_handle -{ - edma_callback callback; /*!< Callback function for major count exhausted. */ - void *userData; /*!< Callback function parameter. */ - DMA_Type *base; /*!< eDMA peripheral base address. */ - edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ - uint8_t channel; /*!< eDMA channel number. */ - volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ - volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ - volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in - the memory. */ - volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ - uint8_t flags; /*!< The status of the current channel. */ -} edma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name eDMA initialization and de-initialization - * @{ - */ - -/*! - * @brief Initializes the eDMA peripheral. - * - * This function ungates the eDMA clock and configures the eDMA peripheral according - * to the configuration structure. - * - * @param base eDMA peripheral base address. - * @param config A pointer to the configuration structure, see "edma_config_t". - * @note This function enables the minor loop map feature. - */ -void EDMA_Init(DMA_Type *base, const edma_config_t *config); - -/*! - * @brief Deinitializes the eDMA peripheral. - * - * This function gates the eDMA clock. - * - * @param base eDMA peripheral base address. - */ -void EDMA_Deinit(DMA_Type *base); - -/*! - * @brief Gets the eDMA default configuration structure. - * - * This function sets the configuration structure to default values. - * The default configuration is set to the following values. - * @code - * config.enableContinuousLinkMode = false; - * config.enableHaltOnError = true; - * config.enableRoundRobinArbitration = false; - * config.enableDebugMode = false; - * @endcode - * - * @param config A pointer to the eDMA configuration structure. - */ -void EDMA_GetDefaultConfig(edma_config_t *config); - -/* @} */ -/*! - * @name eDMA Channel Operation - * @{ - */ - -/*! - * @brief Sets all TCD registers to default values. - * - * This function sets TCD registers for this channel to default values. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @note This function must not be called while the channel transfer is ongoing - * or it causes unpredictable results. - * @note This function enables the auto stop request feature. - */ -void EDMA_ResetChannel(DMA_Type *base, uint32_t channel); - -/*! - * @brief Configures the eDMA transfer attribute. - * - * This function configures the transfer attribute, including source address, destination address, - * transfer size, address offset, and so on. It also configures the scatter gather feature if the - * user supplies the TCD address. - * Example: - * @code - * edma_transfer_t config; - * edma_tcd_t tcd; - * config.srcAddr = ..; - * config.destAddr = ..; - * ... - * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); - * @endcode - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param config Pointer to eDMA transfer configuration structure. - * @param nextTcd Point to TCD structure. It can be NULL if users - * do not want to enable scatter/gather feature. - * @note If nextTcd is not NULL, it means scatter gather feature is enabled - * and DREQ bit is cleared in the previous transfer configuration, which - * is set in the eDMA_ResetChannel. - */ -void EDMA_SetTransferConfig(DMA_Type *base, - uint32_t channel, - const edma_transfer_config_t *config, - edma_tcd_t *nextTcd); - -/*! - * @brief Configures the eDMA minor offset feature. - * - * The minor offset means that the signed-extended value is added to the source address or destination - * address after each minor loop. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param config A pointer to the minor offset configuration structure. - */ -void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); - -/*! - * @brief Configures the eDMA channel preemption feature. - * - * This function configures the channel preemption attribute and the priority of the channel. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number - * @param config A pointer to the channel preemption configuration structure. - */ -static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base, - uint32_t channel, - const edma_channel_Preemption_config_t *config) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - - DMA_DCHPRIn(base, channel) = - (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) | - DMA_DCHPRI0_CHPRI(config->channelPriority)); -} - -/*! - * @brief Sets the channel link for the eDMA transfer. - * - * This function configures either the minor link or the major link mode. The minor link means that the channel link is - * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is - * exhausted. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param type A channel link type, which can be one of the following: - * @arg kEDMA_LinkNone - * @arg kEDMA_MinorLink - * @arg kEDMA_MajorLink - * @param linkedChannel The linked channel number. - * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. - */ -void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); - -/*! - * @brief Sets the bandwidth for the eDMA transfer. - * - * Because the eDMA processes the minor loop, it continuously generates read/write sequences - * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of - * each read/write access to control the bus request bandwidth seen by the crossbar switch. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param bandWidth A bandwidth setting, which can be one of the following: - * @arg kEDMABandwidthStallNone - * @arg kEDMABandwidthStall4Cycle - * @arg kEDMABandwidthStall8Cycle - */ -void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); - -/*! - * @brief Sets the source modulo and the destination modulo for the eDMA transfer. - * - * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) - * calculation is performed or the original register value. It provides the ability to implement a circular data - * queue easily. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param srcModulo A source modulo value. - * @param destModulo A destination modulo value. - */ -void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); - -#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT -/*! - * @brief Enables an async request for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel); -} -#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */ - -/*! - * @brief Enables an auto stop request for the eDMA transfer. - * - * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); -} - -/*! - * @brief Enables the interrupt source for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); - -/*! - * @brief Disables the interrupt source for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of the interrupt source to be set. Use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); - -/* @} */ -/*! - * @name eDMA TCD Operation - * @{ - */ - -/*! - * @brief Sets all fields to default values for the TCD structure. - * - * This function sets all fields for this TCD structure to default value. - * - * @param tcd Pointer to the TCD structure. - * @note This function enables the auto stop request feature. - */ -void EDMA_TcdReset(edma_tcd_t *tcd); - -/*! - * @brief Configures the eDMA TCD transfer attribute. - * - * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. - * The STCD is used in the scatter-gather mode. - * This function configures the TCD transfer attribute, including source address, destination address, - * transfer size, address offset, and so on. It also configures the scatter gather feature if the - * user supplies the next TCD address. - * Example: - * @code - * edma_transfer_t config = { - * ... - * } - * edma_tcd_t tcd __aligned(32); - * edma_tcd_t nextTcd __aligned(32); - * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); - * @endcode - * - * @param tcd Pointer to the TCD structure. - * @param config Pointer to eDMA transfer configuration structure. - * @param nextTcd Pointer to the next TCD structure. It can be NULL if users - * do not want to enable scatter/gather feature. - * @note TCD address should be 32 bytes aligned or it causes an eDMA error. - * @note If the nextTcd is not NULL, the scatter gather feature is enabled - * and DREQ bit is cleared in the previous transfer configuration, which - * is set in the EDMA_TcdReset. - */ -void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); - -/*! - * @brief Configures the eDMA TCD minor offset feature. - * - * A minor offset is a signed-extended value added to the source address or a destination - * address after each minor loop. - * - * @param tcd A point to the TCD structure. - * @param config A pointer to the minor offset configuration structure. - */ -void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); - -/*! - * @brief Sets the channel link for the eDMA TCD. - * - * This function configures either a minor link or a major link. The minor link means the channel link is - * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is - * exhausted. - * - * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. - * @param tcd Point to the TCD structure. - * @param type Channel link type, it can be one of: - * @arg kEDMA_LinkNone - * @arg kEDMA_MinorLink - * @arg kEDMA_MajorLink - * @param linkedChannel The linked channel number. - */ -void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); - -/*! - * @brief Sets the bandwidth for the eDMA TCD. - * - * Because the eDMA processes the minor loop, it continuously generates read/write sequences - * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of - * each read/write access to control the bus request bandwidth seen by the crossbar switch. - * @param tcd A pointer to the TCD structure. - * @param bandWidth A bandwidth setting, which can be one of the following: - * @arg kEDMABandwidthStallNone - * @arg kEDMABandwidthStall4Cycle - * @arg kEDMABandwidthStall8Cycle - */ -static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); -} - -/*! - * @brief Sets the source modulo and the destination modulo for the eDMA TCD. - * - * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) - * calculation is performed or the original register value. It provides the ability to implement a circular data - * queue easily. - * - * @param tcd A pointer to the TCD structure. - * @param srcModulo A source modulo value. - * @param destModulo A destination modulo value. - */ -void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); - -/*! - * @brief Sets the auto stop request for the eDMA TCD. - * - * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. - * - * @param tcd A pointer to the TCD structure. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); -} - -/*! - * @brief Enables the interrupt source for the eDMA TCD. - * - * @param tcd Point to the TCD structure. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); - -/*! - * @brief Disables the interrupt source for the eDMA TCD. - * - * @param tcd Point to the TCD structure. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); - -/*! @} */ -/*! - * @name eDMA Channel Transfer Operation - * @{ - */ - -/*! - * @brief Enables the eDMA hardware channel request. - * - * This function enables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->SERQ = DMA_SERQ_SERQ(channel); -} - -/*! - * @brief Disables the eDMA hardware channel request. - * - * This function disables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CERQ = DMA_CERQ_CERQ(channel); -} - -/*! - * @brief Starts the eDMA transfer by using the software trigger. - * - * This function starts a minor loop transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->SSRT = DMA_SSRT_SSRT(channel); -} - -/*! @} */ -/*! - * @name eDMA Channel Status Operation - * @{ - */ - -/*! - * @brief Gets the remaining major loop count from the eDMA current channel TCD. - * - * This function checks the TCD (Task Control Descriptor) status for a specified - * eDMA channel and returns the the number of major loop count that has not finished. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @return Major loop count which has not been transferred yet for the current TCD. - * @note 1. This function can only be used to get unfinished major loop count of transfer without - * the next TCD, or it might be inaccuracy. - * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while - * the channel is running. - * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO - * register is needed while the eDMA IP does not support getting it while a channel is active. - * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine - * is working with while a channel is running. - * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example - * copied before enabling the channel) is needed. The formula to calculate it is shown below: - * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) - */ -uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel); - -/*! - * @brief Gets the eDMA channel error status flags. - * - * @param base eDMA peripheral base address. - * @return The mask of error status flags. Users need to use the -* _edma_error_status_flags type to decode the return variables. - */ -static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base) -{ - return base->ES; -} - -/*! - * @brief Gets the eDMA channel status flags. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @return The mask of channel status flags. Users need to use the - * _edma_channel_status_flags type to decode the return variables. - */ -uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel); - -/*! - * @brief Clears the eDMA channel status flags. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of channel status to be cleared. Users need to use - * the defined _edma_channel_status_flags type. - */ -void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask); - -/*! @} */ -/*! - * @name eDMA Transactional Operation - */ - -/*! - * @brief Creates the eDMA handle. - * - * This function is called if using the transactional API for eDMA. This function - * initializes the internal state of the eDMA handle. - * - * @param handle eDMA handle pointer. The eDMA handle stores callback function and - * parameters. - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs the TCDs memory pool into the eDMA handle. - * - * This function is called after the EDMA_CreateHandle to use scatter/gather feature. - * - * @param handle eDMA handle pointer. - * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. - * @param tcdSize The number of TCD slots. - */ -void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); - -/*! - * @brief Installs a callback function for the eDMA transfer. - * - * This callback is called in the eDMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle eDMA handle pointer. - * @param callback eDMA callback function pointer. - * @param userData A parameter for the callback function. - */ -void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); - -/*! - * @brief Prepares the eDMA transfer structure. - * - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type edma_transfer_t. - * @param srcAddr eDMA transfer source address. - * @param srcWidth eDMA transfer source address width(bytes). - * @param destAddr eDMA transfer destination address. - * @param destWidth eDMA transfer destination address width(bytes). - * @param bytesEachRequest eDMA transfer bytes per channel request. - * @param transferBytes eDMA transfer bytes to be transferred. - * @param type eDMA transfer type. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, the source address must be 4 bytes aligned, or it results in - * source address error (SAE). - */ -void EDMA_PrepareTransfer(edma_transfer_config_t *config, - void *srcAddr, - uint32_t srcWidth, - void *destAddr, - uint32_t destWidth, - uint32_t bytesEachRequest, - uint32_t transferBytes, - edma_transfer_type_t type); - -/*! - * @brief Submits the eDMA transfer request. - * - * This function submits the eDMA transfer request according to the transfer configuration structure. - * If submitting the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle eDMA handle pointer. - * @param config Pointer to eDMA transfer configuration structure. - * @retval kStatus_EDMA_Success It means submit transfer request succeed. - * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); - -/*! - * @brief eDMA starts transfer. - * - * This function enables the channel request. Users can call this function after submitting the transfer request - * or before submitting the transfer request. - * - * @param handle eDMA handle pointer. - */ -void EDMA_StartTransfer(edma_handle_t *handle); - -/*! - * @brief eDMA stops transfer. - * - * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() - * again to resume the transfer. - * - * @param handle eDMA handle pointer. - */ -void EDMA_StopTransfer(edma_handle_t *handle); - -/*! - * @brief eDMA aborts transfer. - * - * This function disables the channel request and clear transfer status bits. - * Users can submit another transfer after calling this API. - * - * @param handle DMA handle pointer. - */ -void EDMA_AbortTransfer(edma_handle_t *handle); - -/*! - * @brief eDMA IRQ handler for the current major loop transfer completion. - * - * This function clears the channel major interrupt flag and calls - * the callback function if it is not NULL. - * - * Note: - * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. - * These include the final address adjustments and reloading of the BITER field into the CITER. - * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from - * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). - * - * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. - * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index - * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be - * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have - * been loaded into the eDMA engine at this point already.). - * - * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not - * load a new TCD) from the memory pool to the eDMA engine when major loop completes. - * Therefore, ensure that the header and tcdUsed updated are identical for them. - * tcdUsed are both 0 in this case as no TCD to be loaded. - * - * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for - * further details. - * - * @param handle eDMA handle pointer. - */ -void EDMA_HandleIRQ(edma_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_EDMA_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_ewm.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_ewm.c deleted file mode 100644 index 1a71a07..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_ewm.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_ewm.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -void EWM_Init(EWM_Type *base, const ewm_config_t *config) -{ - assert(config); - - uint32_t value = 0U; - - CLOCK_EnableClock(kCLOCK_Ewm0); - value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) | - EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt); -#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER - base->CLKPRESCALER = config->prescaler; -#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ - -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT - base->CLKCTRL = config->clockSource; -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ - - base->CMPL = config->compareLowValue; - base->CMPH = config->compareHighValue; - base->CTRL = value; -} - -void EWM_Deinit(EWM_Type *base) -{ - EWM_DisableInterrupts(base, kEWM_InterruptEnable); - CLOCK_DisableClock(kCLOCK_Ewm0); -} - -void EWM_GetDefaultConfig(ewm_config_t *config) -{ - assert(config); - - config->enableEwm = true; - config->enableEwmInput = false; - config->setInputAssertLogic = false; - config->enableInterrupt = false; -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT - config->clockSource = kEWM_LpoClockSource0; -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ -#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER - config->prescaler = 0U; -#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ - config->compareLowValue = 0U; - config->compareHighValue = 0xFEU; -} - -void EWM_Refresh(EWM_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->SERV = (uint8_t)0xB4U; - base->SERV = (uint8_t)0x2CU; - EnableGlobalIRQ(primaskValue); -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_ewm.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_ewm.h deleted file mode 100644 index 180575e..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_ewm.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_EWM_H_ -#define _FSL_EWM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ewm - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief EWM driver version 2.0.1. */ -#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief Describes EWM clock source. */ -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT -typedef enum _ewm_lpo_clock_source -{ - kEWM_LpoClockSource0 = 0U, /*!< EWM clock sourced from lpo_clk[0]*/ - kEWM_LpoClockSource1 = 1U, /*!< EWM clock sourced from lpo_clk[1]*/ - kEWM_LpoClockSource2 = 2U, /*!< EWM clock sourced from lpo_clk[2]*/ - kEWM_LpoClockSource3 = 3U, /*!< EWM clock sourced from lpo_clk[3]*/ -} ewm_lpo_clock_source_t; -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ - -/*! -* @brief Data structure for EWM configuration. -* -* This structure is used to configure the EWM. -*/ -typedef struct _ewm_config -{ - bool enableEwm; /*!< Enable EWM module */ - bool enableEwmInput; /*!< Enable EWM_in input */ - bool setInputAssertLogic; /*!< EWM_in signal assertion state */ - bool enableInterrupt; /*!< Enable EWM interrupt */ -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT - ewm_lpo_clock_source_t clockSource; /*!< Clock source select */ -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ -#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER - uint8_t prescaler; /*!< Clock prescaler value */ -#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ - uint8_t compareLowValue; /*!< Compare low-register value */ - uint8_t compareHighValue; /*!< Compare high-register value */ -} ewm_config_t; - -/*! - * @brief EWM interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the EWM interrupt configurations. - */ -enum _ewm_interrupt_enable_t -{ - kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable EWM to generate an interrupt*/ -}; - -/*! - * @brief EWM status flags. - * - * This structure contains the constants for the EWM status flags for use in the EWM functions. - */ -enum _ewm_status_flags_t -{ - kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when EWM is enabled*/ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name EWM Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes the EWM peripheral. - * - * This function is used to initialize the EWM. After calling, the EWM - * runs immediately according to the configuration. - * Note that except for interrupt enable control bit, other control bits and registers are write once after a - * CPU reset. Modifying them more than once generates a bus transfer error. - * - * Example: - * @code - * ewm_config_t config; - * EWM_GetDefaultConfig(&config); - * config.compareHighValue = 0xAAU; - * EWM_Init(ewm_base,&config); - * @endcode - * - * @param base EWM peripheral base address - * @param config The configuration of EWM -*/ -void EWM_Init(EWM_Type *base, const ewm_config_t *config); - -/*! - * @brief Deinitializes the EWM peripheral. - * - * This function is used to shut down the EWM. - * - * @param base EWM peripheral base address -*/ -void EWM_Deinit(EWM_Type *base); - -/*! - * @brief Initializes the EWM configuration structure. - * - * This function initializes the EWM configuration structure to default values. The default - * values are: - * @code - * ewmConfig->enableEwm = true; - * ewmConfig->enableEwmInput = false; - * ewmConfig->setInputAssertLogic = false; - * ewmConfig->enableInterrupt = false; - * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; - * ewmConfig->prescaler = 0; - * ewmConfig->compareLowValue = 0; - * ewmConfig->compareHighValue = 0xFEU; - * @endcode - * - * @param config Pointer to EWM configuration structure. - * @see ewm_config_t - */ -void EWM_GetDefaultConfig(ewm_config_t *config); - -/* @} */ - -/*! - * @name EWM functional Operation - * @{ - */ - -/*! - * @brief Enables the EWM interrupt. - * - * This function enables the EWM interrupt. - * - * @param base EWM peripheral base address - * @param mask The interrupts to enable - * The parameter can be combination of the following source if defined: - * @arg kEWM_InterruptEnable - */ -static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask) -{ - base->CTRL |= mask; -} - -/*! - * @brief Disables the EWM interrupt. - * - * This function enables the EWM interrupt. - * - * @param base EWM peripheral base address - * @param mask The interrupts to disable - * The parameter can be combination of the following source if defined: - * @arg kEWM_InterruptEnable - */ -static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask) -{ - base->CTRL &= ~mask; -} - -/*! - * @brief Gets EWM all status flags. - * - * This function gets all status flags. - * - * Example for getting Running Flag: - * @code - * uint32_t status; - * status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag; - * @endcode - * @param base EWM peripheral base address - * @return State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t - * - true: a related status flag has been set. - * - false: a related status flag is not set. - */ -static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) -{ - return (base->CTRL & EWM_CTRL_EWMEN_MASK); -} - -/*! - * @brief Services the EWM. - * - * This function reset EWM counter to zero. - * - * @param base EWM peripheral base address -*/ -void EWM_Refresh(EWM_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_EWM_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_flash.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_flash.c deleted file mode 100644 index c9de4ec..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_flash.c +++ /dev/null @@ -1,3265 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flash.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @name Misc utility defines - * @{ - */ -#ifndef ALIGN_DOWN -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif -#ifndef ALIGN_UP -#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) -#endif - -#define BYTES_JOIN_TO_WORD_1_3(x, y) ((((uint32_t)(x)&0xFFU) << 24) | ((uint32_t)(y)&0xFFFFFFU)) -#define BYTES_JOIN_TO_WORD_2_2(x, y) ((((uint32_t)(x)&0xFFFFU) << 16) | ((uint32_t)(y)&0xFFFFU)) -#define BYTES_JOIN_TO_WORD_3_1(x, y) ((((uint32_t)(x)&0xFFFFFFU) << 8) | ((uint32_t)(y)&0xFFU)) -#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) \ - ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | ((uint32_t)(z)&0xFFFFU)) -#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) \ - ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFFFU) << 8) | ((uint32_t)(z)&0xFFU)) -#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) \ - ((((uint32_t)(x)&0xFFFFU) << 16) | (((uint32_t)(y)&0xFFU) << 8) | ((uint32_t)(z)&0xFFU)) -#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) \ - ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | (((uint32_t)(z)&0xFFU) << 8) | \ - ((uint32_t)(w)&0xFFU)) -/*@}*/ - -/*! @brief Data flash IFR map Field*/ -#if defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE -#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8003F8U -#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ -#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8000F8U -#endif - -/*! - * @name Reserved FlexNVM size (For a variety of purposes) defines - * @{ - */ -#define FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED 0xFFFFFFFFU -#define FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED 0xFFFFU -/*@}*/ - -/*! - * @name Flash Program Once Field defines - * @{ - */ -#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA -/* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */ -#define FLASH_PROGRAM_ONCE_MIN_ID_8BYTES \ - 0x10U /* Minimum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ -#define FLASH_PROGRAM_ONCE_MAX_ID_8BYTES \ - 0x13U /* Maximum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 -#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE -/* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 0 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 -#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL -/* FTFL parts(eg. K20) only support 4-bytes unit size */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 0 -#endif -/*@}*/ - -/*! - * @name Flash security status defines - * @{ - */ -#define FLASH_SECURITY_STATE_KEYEN 0x80U -#define FLASH_SECURITY_STATE_UNSECURED 0x02U -#define FLASH_NOT_SECURE 0x01U -#define FLASH_SECURE_BACKDOOR_ENABLED 0x02U -#define FLASH_SECURE_BACKDOOR_DISABLED 0x04U -/*@}*/ - -/*! - * @name Flash controller command numbers - * @{ - */ -#define FTFx_VERIFY_BLOCK 0x00U /*!< RD1BLK*/ -#define FTFx_VERIFY_SECTION 0x01U /*!< RD1SEC*/ -#define FTFx_PROGRAM_CHECK 0x02U /*!< PGMCHK*/ -#define FTFx_READ_RESOURCE 0x03U /*!< RDRSRC*/ -#define FTFx_PROGRAM_LONGWORD 0x06U /*!< PGM4*/ -#define FTFx_PROGRAM_PHRASE 0x07U /*!< PGM8*/ -#define FTFx_ERASE_BLOCK 0x08U /*!< ERSBLK*/ -#define FTFx_ERASE_SECTOR 0x09U /*!< ERSSCR*/ -#define FTFx_PROGRAM_SECTION 0x0BU /*!< PGMSEC*/ -#define FTFx_GENERATE_CRC 0x0CU /*!< CRCGEN*/ -#define FTFx_VERIFY_ALL_BLOCK 0x40U /*!< RD1ALL*/ -#define FTFx_READ_ONCE 0x41U /*!< RDONCE or RDINDEX*/ -#define FTFx_PROGRAM_ONCE 0x43U /*!< PGMONCE or PGMINDEX*/ -#define FTFx_ERASE_ALL_BLOCK 0x44U /*!< ERSALL*/ -#define FTFx_SECURITY_BY_PASS 0x45U /*!< VFYKEY*/ -#define FTFx_SWAP_CONTROL 0x46U /*!< SWAP*/ -#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U /*!< ERSALLU*/ -#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/ -#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU /*!< ERSXA*/ -#define FTFx_PROGRAM_PARTITION 0x80U /*!< PGMPART)*/ -#define FTFx_SET_FLEXRAM_FUNCTION 0x81U /*!< SETRAM*/ - /*@}*/ - -/*! - * @name Common flash register info defines - * @{ - */ -#if defined(FTFA) -#define FTFx FTFA -#define FTFx_BASE FTFA_BASE -#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#elif defined(FTFE) -#define FTFx FTFE -#define FTFx_BASE FTFE_BASE -#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#elif defined(FTFL) -#define FTFx FTFL -#define FTFx_BASE FTFL_BASE -#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#else -#error "Unknown flash controller" -#endif -/*@}*/ - -/*! - * @name Common flash register access info defines - * @{ - */ -#if defined(FTFA_FCCOB_CCOBn_MASK) || defined(FTFE_FCCOB_CCOBn_MASK) || defined(FTFL_FCCOB_CCOBn_MASK) -#define FTFx_FCCOB3_REG (FTFx->FCCOB[0]) -#define FTFx_FCCOB5_REG (FTFx->FCCOB[6]) -#define FTFx_FCCOB6_REG (FTFx->FCCOB[5]) -#define FTFx_FCCOB7_REG (FTFx->FCCOB[4]) -#else -#define FTFx_FCCOB3_REG (FTFx->FCCOB3) -#define FTFx_FCCOB5_REG (FTFx->FCCOB5) -#define FTFx_FCCOB6_REG (FTFx->FCCOB6) -#define FTFx_FCCOB7_REG (FTFx->FCCOB7) -#endif - -#if defined(FTFA_FPROT_PROT_MASK) || defined(FTFE_FPROT_PROT_MASK) || defined(FTFL_FPROT_PROT_MASK) -#define FTFx_FPROT_LOW_REG (FTFx->FPROT[4]) -#define FTFx_FPROTL3_REG (FTFx->FPROT[4]) -#define FTFx_FPROTL2_REG (FTFx->FPROT[5]) -#define FTFx_FPROTL1_REG (FTFx->FPROT[6]) -#define FTFx_FPROTL0_REG (FTFx->FPROT[7]) -#define FTFx_FPROT_HIGH_REG (FTFx->FPROT[0]) -#define FTFx_FPROTH3_REG (FTFx->FPROT[0]) -#define FTFx_FPROTH2_REG (FTFx->FPROT[1]) -#define FTFx_FPROTH1_REG (FTFx->FPROT[2]) -#define FTFx_FPROTH0_REG (FTFx->FPROT[3]) -#else -#define FTFx_FPROT_LOW_REG (FTFx->FPROT3) -#define FTFx_FPROTL3_REG (FTFx->FPROT3) -#define FTFx_FPROTL2_REG (FTFx->FPROT2) -#define FTFx_FPROTL1_REG (FTFx->FPROT1) -#define FTFx_FPROTL0_REG (FTFx->FPROT0) -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER -#if defined(FTFA_FPROTS_PROTS_MASK) || defined(FTFE_FPROTS_PROTS_MASK) || defined(FTFL_FPROTS_PROTS_MASK) -#define FTFx_FPROTSH_REG (FTFx->FPROTS[1]) -#define FTFx_FPROTSL_REG (FTFx->FPROTS[0]) -#else -#define FTFx_FPROTSH_REG (FTFx->FPROTSH) -#define FTFx_FPROTSL_REG (FTFx->FPROTSL) -#endif -#endif - -#if defined(FTFA_XACC_XA_MASK) || defined(FTFE_XACC_XA_MASK) || defined(FTFL_XACC_XA_MASK) -#define FTFx_XACCH3_REG (FTFx->XACC[0]) -#define FTFx_XACCL3_REG (FTFx->XACC[4]) -#else -#define FTFx_XACCH3_REG (FTFx->XACCH3) -#define FTFx_XACCL3_REG (FTFx->XACCL3) -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER -#if defined(FTFA_XACCS_XA_S_MASK) || defined(FTFE_XACCS_XA_S_MASK) || defined(FTFL_XACCS_XA_S_MASK) -#define FTFx_XACCSH_REG (FTFx->XACCS[1]) -#define FTFx_XACCSL_REG (FTFx->XACCS[0]) -#else -#define FTFx_XACCSH_REG (FTFx->XACCSH) -#define FTFx_XACCSL_REG (FTFx->XACCSL) -#endif -#endif -/*@}*/ - -/*! - * @brief Enumeration for access segment property. - */ -enum _flash_access_segment_property -{ - kFLASH_AccessSegmentBase = 256UL, -}; - -/*! - * @brief Enumeration for flash config area. - */ -enum _flash_config_area_range -{ - kFLASH_ConfigAreaStart = 0x400U, - kFLASH_ConfigAreaEnd = 0x40FU -}; - -/*! - * @name Flash register access type defines - * @{ - */ -#define FTFx_REG8_ACCESS_TYPE volatile uint8_t * -#define FTFx_REG32_ACCESS_TYPE volatile uint32_t * -/*@}*/ - -/*! - * @brief MSCM prefetch speculation defines. - */ -#define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U) -#define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U) - -#define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U) -#define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief Copy flash_run_command() to RAM*/ -static void copy_flash_run_command(uint32_t *flashRunCommand); -/*! @brief Copy flash_cache_clear_command() to RAM*/ -static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation); -/*! @brief Check whether flash execute-in-ram functions are ready*/ -static status_t flash_check_execute_in_ram_function_info(flash_config_t *config); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! @brief Internal function Flash command sequence. Called by driver APIs only*/ -static status_t flash_command_sequence(flash_config_t *config); - -/*! @brief Perform the cache clear to the flash*/ -void flash_cache_clear(flash_config_t *config); - -/*! @brief Validates the range and alignment of the given address range.*/ -static status_t flash_check_range(flash_config_t *config, - uint32_t startAddress, - uint32_t lengthInBytes, - uint32_t alignmentBaseline); -/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ -static status_t flash_get_matched_operation_info(flash_config_t *config, - uint32_t address, - flash_operation_config_t *info); -/*! @brief Validates the given user key for flash erase APIs.*/ -static status_t flash_check_user_key(uint32_t key); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ -static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config); -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -/*! @brief Validates the range of the given resource address.*/ -static status_t flash_check_resource_range(uint32_t start, - uint32_t lengthInBytes, - uint32_t alignmentBaseline, - flash_read_resource_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -/*! @brief Validates the gived swap control option.*/ -static status_t flash_check_swap_control_option(flash_swap_control_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ -static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address); -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -/*! @brief Validates the gived flexram function option.*/ -static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -/*! @brief Gets the flash protection information (region size, region count).*/ -static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info); - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/ -static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info); -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Access to FTFx->FCCOB */ -volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFx_FCCOB3_REG; -/*! @brief Access to FTFx->FPROT */ -volatile uint32_t *const kFPROTL = (volatile uint32_t *)&FTFx_FPROT_LOW_REG; -#if defined(FTFx_FPROT_HIGH_REG) -volatile uint32_t *const kFPROTH = (volatile uint32_t *)&FTFx_FPROT_HIGH_REG; -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER -volatile uint8_t *const kFPROTSL = (volatile uint8_t *)&FTFx_FPROTSL_REG; -volatile uint8_t *const kFPROTSH = (volatile uint8_t *)&FTFx_FPROTSH_REG; -#endif - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief A function pointer used to point to relocated flash_run_command() */ -static void (*callFlashRunCommand)(FTFx_REG8_ACCESS_TYPE ftfx_fstat); -/*! @brief A function pointer used to point to relocated flash_common_bit_operation() */ -static void (*callFlashCommonBitOperation)(FTFx_REG32_ACCESS_TYPE base, - uint32_t bitMask, - uint32_t bitShift, - uint32_t bitValue); - -/*! - * @brief Position independent code of flash_run_command() - * - * Note1: The prototype of C function is shown as below: - * @code - * void flash_run_command(FTFx_REG8_ACCESS_TYPE ftfx_fstat) - * { - * // clear CCIF bit - * *ftfx_fstat = FTFx_FSTAT_CCIF_MASK; - * - * // Check CCIF bit of the flash status register, wait till it is set. - * // IP team indicates that this loop will always complete. - * while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK)) - * { - * } - * } - * @endcode - * Note2: The binary code is generated by IAR 7.70.1 - */ -static const uint16_t s_flashRunCommandFunctionCode[] = { - 0x2180, /* MOVS R1, #128 ; 0x80 */ - 0x7001, /* STRB R1, [R0] */ - /* @4: */ - 0x7802, /* LDRB R2, [R0] */ - 0x420a, /* TST R2, R1 */ - 0xd0fc, /* BEQ.N @4 */ - 0x4770 /* BX LR */ -}; - -/*! - * @brief Position independent code of flash_common_bit_operation() - * - * Note1: The prototype of C function is shown as below: - * @code - * void flash_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t - * bitValue) - * { - * if (bitMask) - * { - * uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask); - * *base = (*base & (~bitMask)) | value; - * } - * - * __ISB(); - * __DSB(); - * } - * @endcode - * Note2: The binary code is generated by IAR 7.70.1 - */ -static const uint16_t s_flashCommonBitOperationFunctionCode[] = { - 0xb510, /* PUSH {R4, LR} */ - 0x2900, /* CMP R1, #0 */ - 0xd005, /* BEQ.N @12 */ - 0x6804, /* LDR R4, [R0] */ - 0x438c, /* BICS R4, R4, R1 */ - 0x4093, /* LSLS R3, R3, R2 */ - 0x4019, /* ANDS R1, R1, R3 */ - 0x4321, /* ORRS R1, R1, R4 */ - 0x6001, /* STR R1, [R0] */ - /* @12: */ - 0xf3bf, 0x8f6f, /* ISB */ - 0xf3bf, 0x8f4f, /* DSB */ - 0xbd10 /* POP {R4, PC} */ -}; -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) -/*! @brief A static buffer used to hold flash_run_command() */ -static uint32_t s_flashRunCommand[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; -/*! @brief A static buffer used to hold flash_common_bit_operation() */ -static uint32_t s_flashCommonBitOperation[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; -/*! @brief Flash execute-in-ram function information */ -static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo; -#endif - -/*! - * @brief Table of pflash sizes. - * - * The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield. - * - * The values in this table have been right shifted 10 bits so that they will all fit within - * an 16-bit integer. To get the actual flash density, you must left shift the looked up value - * by 10 bits. - * - * Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is - * reserved. - * - * Code to use the table: - * @code - * uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; - * flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - * @endcode - */ -const uint16_t kPFlashDensities[] = { - 8, /* 0x0 - 8192, 8KB */ - 16, /* 0x1 - 16384, 16KB */ - 24, /* 0x2 - 24576, 24KB */ - 32, /* 0x3 - 32768, 32KB */ - 48, /* 0x4 - 49152, 48KB */ - 64, /* 0x5 - 65536, 64KB */ - 96, /* 0x6 - 98304, 96KB */ - 128, /* 0x7 - 131072, 128KB */ - 192, /* 0x8 - 196608, 192KB */ - 256, /* 0x9 - 262144, 256KB */ - 384, /* 0xa - 393216, 384KB */ - 512, /* 0xb - 524288, 512KB */ - 768, /* 0xc - 786432, 768KB */ - 1024, /* 0xd - 1048576, 1MB */ - 1536, /* 0xe - 1572864, 1.5MB */ - /* 2048, 0xf - 2097152, 2MB */ -}; - -/******************************************************************************* - * Code - ******************************************************************************/ - -status_t FLASH_Init(flash_config_t *config) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED - if (config->FlashMemoryIndex == (uint32_t)kFLASH_MemoryIndexSecondaryFlash) - { -/* calculate the flash density from SIM_FCFG1.PFSIZE */ -#if defined(SIM_FCFG1_CORE1_PFSIZE_MASK) - uint32_t flashDensity; - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE1_PFSIZE_MASK) >> SIM_FCFG1_CORE1_PFSIZE_SHIFT; - if (pfsize == 0xf) - { - flashDensity = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; - } - else - { - flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - } - config->PFlashTotalSize = flashDensity; -#else - /* Unused code to solve MISRA-C issue*/ - config->PFlashBlockBase = kPFlashDensities[0]; - config->PFlashTotalSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; -#endif - config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS; - config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT; - config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE; - } - else -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED */ - { - uint32_t flashDensity; - -/* calculate the flash density from SIM_FCFG1.PFSIZE */ -#if defined(SIM_FCFG1_CORE0_PFSIZE_MASK) - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE0_PFSIZE_MASK) >> SIM_FCFG1_CORE0_PFSIZE_SHIFT; -#elif defined(SIM_FCFG1_PFSIZE_MASK) - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; -#else -#error "Unknown flash size" -#endif - /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed. - * We just use the pre-defined flash size in feature file here to support pre-production parts */ - if (pfsize == 0xf) - { - flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE; - } - else - { - flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - } - - /* fill out a few of the structure members */ - config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; - config->PFlashTotalSize = flashDensity; - config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; - config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE; - } - - { -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - if (config->FlashMemoryIndex == (uint32_t)kFLASH_MemoryIndexSecondaryFlash) - { - config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSSS; - config->PFlashAccessSegmentCount = FTFx->FACSNS; - } - else -#endif - { - config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSS; - config->PFlashAccessSegmentCount = FTFx->FACSN; - } -#else - config->PFlashAccessSegmentSize = 0; - config->PFlashAccessSegmentCount = 0; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - } - - config->PFlashCallback = NULL; - -/* copy required flash commands to RAM */ -#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) - if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config)) - { - s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0; - s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand; - s_flashExecuteInRamFunctionInfo.flashCommonBitOperation = s_flashCommonBitOperation; - config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount; - FLASH_PrepareExecuteInRamFunctions(config); - } -#endif - - config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; - config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE; - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - { - status_t returnCode; - config->DFlashBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS; - returnCode = flash_update_flexnvm_memory_partition_status(config); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - } -#endif - - return kStatus_FLASH_Success; -} - -status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - config->PFlashCallback = callback; - - return kStatus_FLASH_Success; -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) -{ - flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; - - copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand); - copy_flash_common_bit_operation(flashExecuteInRamFunctionInfo->flashCommonBitOperation); - flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_ExecuteInRamFunctionTotalNum; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to erase all flash blocks */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be erased by erase all command, so we need to - * update FlexNVM memory partition status synchronously */ - if (returnCode == kStatus_FLASH_Success) - { - returnCode = flash_update_flexnvm_memory_partition_status(config); - } -#endif - - return returnCode; -} - -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - uint32_t sectorSize; - flash_operation_config_t flashOperationInfo; - uint32_t endAddress; /* storing end address */ - uint32_t numberOfSectors; /* number of sectors calculated by endAddress */ - status_t returnCode; - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectorCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - sectorSize = flashOperationInfo.activeSectorSize; - - /* calculating Flash end address */ - endAddress = start + lengthInBytes - 1; - - /* re-calculate the endAddress and align it to the start of the next sector - * which will be used in the comparison below */ - if (endAddress % sectorSize) - { - numberOfSectors = endAddress / sectorSize + 1; - endAddress = numberOfSectors * sectorSize - 1; - } - - /* the start address will increment to the next sector address - * until it reaches the endAdddress */ - while (start <= endAddress) - { - /* preparing passing parameter to erase a flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* calling flash callback function if it is available */ - if (config->PFlashCallback) - { - config->PFlashCallback(); - } - - /* checking the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - break; - } - else - { - /* Increment to the next sector */ - start += sectorSize; - } - } - - flash_cache_clear(config); - - return (returnCode); -} - -#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD -status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Prepare passing parameter to erase all flash blocks (unsecure). */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be erased by erase all unsecure command, so we need to - * update FlexNVM memory partition status synchronously */ - if (returnCode == kStatus_FLASH_Success) - { - returnCode = flash_update_flexnvm_memory_partition_status(config); - } -#endif - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */ - -status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to erase all execute-only segments - * 1st element for the FCCOB register */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - - return returnCode; -} - -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if (src == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.blockWriteUnitSize); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - - while (lengthInBytes > 0) - { - /* preparing passing parameter to program the flash block */ - kFCCOBx[1] = *src++; - if (4 == flashOperationInfo.blockWriteUnitSize) - { - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start); - } - else if (8 == flashOperationInfo.blockWriteUnitSize) - { - kFCCOBx[2] = *src++; - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start); - } - else - { - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* calling flash callback function if it is available */ - if (config->PFlashCallback) - { - config->PFlashCallback(); - } - - /* checking for the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - break; - } - else - { - /* update start address for next iteration */ - start += flashOperationInfo.blockWriteUnitSize; - - /* update lengthInBytes for next iteration */ - lengthInBytes -= flashOperationInfo.blockWriteUnitSize; - } - } - - flash_cache_clear(config); - - return (returnCode); -} - -status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - - if ((config == NULL) || (src == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* pass paramters to FTFx */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU); - - kFCCOBx[1] = *src; - -/* Note: Have to seperate the first index from the rest if it equals 0 - * to avoid a pointless comparison of unsigned int to 0 compiler warning */ -#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT -#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT - if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || - /* Range check */ - ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && - (lengthInBytes == 8)) -#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ - { - kFCCOBx[2] = *(src + 1); - } -#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - - return returnCode; -} - -#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD -status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - uint32_t sectorSize; - flash_operation_config_t flashOperationInfo; -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - bool needSwitchFlexRamMode = false; -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - if (src == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - sectorSize = flashOperationInfo.activeSectorSize; - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - /* Switch function of FlexRAM if needed */ - if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK)) - { - needSwitchFlexRamMode = true; - - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_SetFlexramAsRamError; - } - } -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - while (lengthInBytes > 0) - { - /* Make sure the write operation doesn't span two sectors */ - uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize); - uint32_t lengthTobeProgrammedOfCurrentSector; - uint32_t currentOffset = 0; - - if (endAddressOfCurrentSector == start) - { - endAddressOfCurrentSector += sectorSize; - } - - if (lengthInBytes + start > endAddressOfCurrentSector) - { - lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start; - } - else - { - lengthTobeProgrammedOfCurrentSector = lengthInBytes; - } - - /* Program Current Sector */ - while (lengthTobeProgrammedOfCurrentSector > 0) - { - /* Make sure the program size doesn't exceeds Acceleration RAM size */ - uint32_t programSizeOfCurrentPass; - uint32_t numberOfPhases; - - if (lengthTobeProgrammedOfCurrentSector > kFLASH_AccelerationRamSize) - { - programSizeOfCurrentPass = kFLASH_AccelerationRamSize; - } - else - { - programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector; - } - - /* Copy data to FlexRAM */ - memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass); - /* Set start address of the data to be programmed */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset); - /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */ - numberOfPhases = programSizeOfCurrentPass / flashOperationInfo.sectionCmdAddressAligment; - - kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU); - - /* Peform command sequence */ - returnCode = flash_command_sequence(config); - - /* calling flash callback function if it is available */ - if (config->PFlashCallback) - { - config->PFlashCallback(); - } - - if (returnCode != kStatus_FLASH_Success) - { - flash_cache_clear(config); - return returnCode; - } - - lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass; - currentOffset += programSizeOfCurrentPass; - } - - src += currentOffset / 4; - start += currentOffset; - lengthInBytes -= currentOffset; - } - - flash_cache_clear(config); - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - /* Restore function of FlexRAM if needed. */ - if (needSwitchFlexRamMode) - { - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_RecoverFlexramAsEepromError; - } - } -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - bool needSwitchFlexRamMode = false; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Validates the range of the given address */ - if ((start < config->FlexRAMBlockBase) || - ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize))) - { - return kStatus_FLASH_AddressError; - } - - returnCode = kStatus_FLASH_Success; - - /* Switch function of FlexRAM if needed */ - if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) - { - needSwitchFlexRamMode = true; - - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_SetFlexramAsEepromError; - } - } - - /* Write data to FlexRAM when it is used as EEPROM emulator */ - while (lengthInBytes > 0) - { - if ((!(start & 0x3U)) && (lengthInBytes >= 4)) - { - *(uint32_t *)start = *(uint32_t *)src; - start += 4; - src += 4; - lengthInBytes -= 4; - } - else if ((!(start & 0x1U)) && (lengthInBytes >= 2)) - { - *(uint16_t *)start = *(uint16_t *)src; - start += 2; - src += 2; - lengthInBytes -= 2; - } - else - { - *(uint8_t *)start = *src; - start += 1; - src += 1; - lengthInBytes -= 1; - } - /* Wait till EEERDY bit is set */ - while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) - { - } - - /* Check for protection violation error */ - if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK) - { - return kStatus_FLASH_ProtectionViolation; - } - } - - /* Switch function of FlexRAM if needed */ - if (needSwitchFlexRamMode) - { - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_RecoverFlexramAsRamError; - } - } - - return returnCode; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -status_t FLASH_ReadResource( - flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if ((config == NULL) || (dst == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = - flash_check_resource_range(start, lengthInBytes, flashOperationInfo.resourceCmdAddressAligment, option); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - - while (lengthInBytes > 0) - { - /* preparing passing parameter */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start); - if (flashOperationInfo.resourceCmdAddressAligment == 4) - { - kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - } - else if (flashOperationInfo.resourceCmdAddressAligment == 8) - { - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - } - else - { - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - if (kStatus_FLASH_Success != returnCode) - { - break; - } - - /* fetch data */ - *dst++ = kFCCOBx[1]; - if (flashOperationInfo.resourceCmdAddressAligment == 8) - { - *dst++ = kFCCOBx[2]; - } - /* update start address for next iteration */ - start += flashOperationInfo.resourceCmdAddressAligment; - /* update lengthInBytes for next iteration */ - lengthInBytes -= flashOperationInfo.resourceCmdAddressAligment; - } - - return (returnCode); -} -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes) -{ - status_t returnCode; - - if ((config == NULL) || (dst == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* pass paramters to FTFx */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - if (kStatus_FLASH_Success == returnCode) - { - *dst = kFCCOBx[1]; -/* Note: Have to seperate the first index from the rest if it equals 0 - * to avoid a pointless comparison of unsigned int to 0 compiler warning */ -#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT -#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT - if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || - /* Range check */ - ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && - (lengthInBytes == 8)) -#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ - { - *(dst + 1) = kFCCOBx[2]; - } -#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ - } - - return returnCode; -} - -status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state) -{ - /* store data read from flash register */ - uint8_t registerValue; - - if ((config == NULL) || (state == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Get flash security register value */ - registerValue = FTFx->FSEC; - - /* check the status of the flash security bits in the security register */ - if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK)) - { - /* Flash in unsecured state */ - *state = kFLASH_SecurityStateNotSecure; - } - else - { - /* Flash in secured state - * check for backdoor key security enable bit */ - if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK)) - { - /* Backdoor key security enabled */ - *state = kFLASH_SecurityStateBackdoorEnabled; - } - else - { - /* Backdoor key security disabled */ - *state = kFLASH_SecurityStateBackdoorDisabled; - } - } - - return (kStatus_FLASH_Success); -} - -status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey) -{ - uint8_t registerValue; /* registerValue */ - status_t returnCode; /* return code variable */ - - if ((config == NULL) || (backdoorKey == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* set the default return code as kStatus_Success */ - returnCode = kStatus_FLASH_Success; - - /* Get flash security register value */ - registerValue = FTFx->FSEC; - - /* Check to see if flash is in secure state (any state other than 0x2) - * If not, then skip this since flash is not secure */ - if (0x02 != (registerValue & 0x03)) - { - /* preparing passing parameter to erase a flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]); - kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - } - - return (returnCode); -} - -status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to verify all block command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} - -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin) -{ - /* Check arguments. */ - uint32_t blockSize; - flash_operation_config_t flashOperationInfo; - uint32_t nextBlockStartAddress; - uint32_t remainingBytes; - status_t returnCode; - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - start = flashOperationInfo.convertedAddress; - blockSize = flashOperationInfo.activeBlockSize; - - nextBlockStartAddress = ALIGN_UP(start, blockSize); - if (nextBlockStartAddress == start) - { - nextBlockStartAddress += blockSize; - } - - remainingBytes = lengthInBytes; - - while (remainingBytes) - { - uint32_t numberOfPhrases; - uint32_t verifyLength = nextBlockStartAddress - start; - if (verifyLength > remainingBytes) - { - verifyLength = remainingBytes; - } - - numberOfPhrases = verifyLength / flashOperationInfo.sectionCmdAddressAligment; - - /* Fill in verify section command parameters. */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_1_1(numberOfPhrases, margin, 0xFFU); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - if (returnCode) - { - return returnCode; - } - - remainingBytes -= verifyLength; - start += verifyLength; - nextBlockStartAddress += blockSize; - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint32_t *expectedData, - flash_margin_value_t margin, - uint32_t *failedAddress, - uint32_t *failedData) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if (expectedData == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.checkCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - - while (lengthInBytes) - { - /* preparing passing parameter to program check the flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_CHECK, start); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(margin, 0xFFFFFFU); - kFCCOBx[2] = *expectedData; - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* checking for the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - if (failedAddress) - { - *failedAddress = start; - } - if (failedData) - { - *failedData = 0; - } - break; - } - - lengthInBytes -= flashOperationInfo.checkCmdAddressAligment; - expectedData += flashOperationInfo.checkCmdAddressAligment / sizeof(*expectedData); - start += flashOperationInfo.checkCmdAddressAligment; - } - - return (returnCode); -} - -status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to verify erase all execute-only segments command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} - -status_t FLASH_IsProtected(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - flash_protection_state_t *protection_state) -{ - uint32_t endAddress; /* end address for protection check */ - uint32_t regionCheckedCounter; /* increments each time the flash address was checked for - * protection status */ - uint32_t regionCounter; /* incrementing variable used to increment through the flash - * protection regions */ - uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */ - - uint8_t flashRegionProtectStatus[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT]; /* array of the protection - * status for each - * protection region */ - uint32_t flashRegionAddress[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT + - 1]; /* array of the start addresses for each flash - * protection region. Note this is REGION_COUNT+1 - * due to requiring the next start address after - * the end of flash for loop-check purposes below */ - flash_protection_config_t flashProtectionInfo; /* flash protection information */ - status_t returnCode; - - if (protection_state == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); - if (returnCode) - { - return returnCode; - } - - /* Get necessary flash protection information. */ - returnCode = flash_get_protection_info(config, &flashProtectionInfo); - if (returnCode) - { - return returnCode; - } - - /* calculating Flash end address */ - endAddress = start + lengthInBytes; - - /* populate the flashRegionAddress array with the start address of each flash region */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - - /* populate up to 33rd element of array, this is the next address after end of flash array */ - while (regionCounter <= flashProtectionInfo.regionCount) - { - flashRegionAddress[regionCounter] = - flashProtectionInfo.regionBase + flashProtectionInfo.regionSize * regionCounter; - regionCounter++; - } - - /* populate flashRegionProtectStatus array with status information - * Protection status for each region is stored in the FPROT[3:0] registers - * Each bit represents one region of flash - * 4 registers * 8-bits-per-register = 32-bits (32-regions) - * The convention is: - * FPROT3[bit 0] is the first protection region (start of flash memory) - * FPROT0[bit 7] is the last protection region (end of flash memory) - * regionCounter is used to determine which FPROT[3:0] register to check for protection status - * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - while (regionCounter < flashProtectionInfo.regionCount) - { -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint32_t)kFLASH_MemoryIndexSecondaryFlash) - { - if (regionCounter < 8) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSL_REG >> regionCounter) & (0x01u); - } - else if ((regionCounter >= 8) && (regionCounter < 16)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSH_REG >> (regionCounter - 8)) & (0x01u); - } - else - { - break; - } - } - else -#endif - { - /* Note: So far protection region count may be 16/20/24/32/64 */ - if (regionCounter < 8) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL3_REG >> regionCounter) & (0x01u); - } - else if ((regionCounter >= 8) && (regionCounter < 16)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL2_REG >> (regionCounter - 8)) & (0x01u); - } -#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 16) -#if (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20) - else if ((regionCounter >= 16) && (regionCounter < 20)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); - } -#else - else if ((regionCounter >= 16) && (regionCounter < 24)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); - } -#endif /* (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20) */ -#endif -#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 24) - else if ((regionCounter >= 24) && (regionCounter < 32)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL0_REG >> (regionCounter - 24)) & (0x01u); - } -#endif -#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && \ - (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 64) - else if (regionCounter < 40) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH3_REG >> (regionCounter - 32)) & (0x01u); - } - else if (regionCounter < 48) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH2_REG >> (regionCounter - 40)) & (0x01u); - } - else if (regionCounter < 56) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH1_REG >> (regionCounter - 48)) & (0x01u); - } - else if (regionCounter < 64) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH0_REG >> (regionCounter - 56)) & (0x01u); - } -#endif - else - { - break; - } - } - - regionCounter++; - } - - /* loop through the flash regions and check - * desired flash address range for protection status - * loop stops when it is detected that start has exceeded the endAddress */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - regionCheckedCounter = 0; - protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */ - while (start < endAddress) - { - /* check to see if the address falls within this protection region - * Note that if the entire flash is to be checked, the last protection - * region checked would consist of the last protection start address and - * the start address following the end of flash */ - if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1])) - { - /* increment regionCheckedCounter to indicate this region was checked */ - regionCheckedCounter++; - - /* check the protection status of this region - * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ - if (!flashRegionProtectStatus[regionCounter]) - { - /* increment protectStatusCounter to indicate this region is protected */ - protectStatusCounter++; - } - start += flashProtectionInfo.regionSize; /* increment to an address within the next region */ - } - regionCounter++; /* increment regionCounter to check for the next flash protection region */ - } - - /* if protectStatusCounter == 0, then no region of the desired flash region is protected */ - if (protectStatusCounter == 0) - { - *protection_state = kFLASH_ProtectionStateUnprotected; - } - /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */ - else if (protectStatusCounter == regionCheckedCounter) - { - *protection_state = kFLASH_ProtectionStateProtected; - } - /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed - * In other words, some regions are protected while others are unprotected */ - else - { - *protection_state = kFLASH_ProtectionStateMixed; - } - - return (returnCode); -} - -status_t FLASH_IsExecuteOnly(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - flash_execute_only_access_state_t *access_state) -{ -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL - flash_access_config_t flashAccessInfo; /* flash Execute-Only information */ -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - status_t returnCode; - - if (access_state == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); - if (returnCode) - { - return returnCode; - } - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL - /* Get necessary flash Execute-Only information. */ - returnCode = flash_get_access_info(config, &flashAccessInfo); - if (returnCode) - { - return returnCode; - } - - { - uint32_t executeOnlySegmentCounter = 0; - - /* calculating end address */ - uint32_t endAddress = start + lengthInBytes; - - /* Aligning start address and end address */ - uint32_t alignedStartAddress = ALIGN_DOWN(start, flashAccessInfo.SegmentSize); - uint32_t alignedEndAddress = ALIGN_UP(endAddress, flashAccessInfo.SegmentSize); - - uint32_t segmentIndex = 0; - uint32_t maxSupportedExecuteOnlySegmentCount = - (alignedEndAddress - alignedStartAddress) / flashAccessInfo.SegmentSize; - - while (start < endAddress) - { - uint32_t xacc; - - segmentIndex = (start - flashAccessInfo.SegmentBase) / flashAccessInfo.SegmentSize; - -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - if (config->FlashMemoryIndex == (uint32_t)kFLASH_MemoryIndexSecondaryFlash) - { - /* For secondary flash, The two XACCS registers allow up to 16 restricted segments of equal memory size. - */ - if (segmentIndex < 8) - { - xacc = *(const volatile uint8_t *)&FTFx_XACCSL_REG; - } - else if (segmentIndex < flashAccessInfo.SegmentCount) - { - xacc = *(const volatile uint8_t *)&FTFx_XACCSH_REG; - segmentIndex -= 8; - } - else - { - break; - } - } - else -#endif - { - /* For primary flash, The eight XACC registers allow up to 64 restricted segments of equal memory size. - */ - if (segmentIndex < 32) - { - xacc = *(const volatile uint32_t *)&FTFx_XACCL3_REG; - } - else if (segmentIndex < flashAccessInfo.SegmentCount) - { - xacc = *(const volatile uint32_t *)&FTFx_XACCH3_REG; - segmentIndex -= 32; - } - else - { - break; - } - } - - /* Determine if this address range is in a execute-only protection flash segment. */ - if ((~xacc) & (1u << segmentIndex)) - { - executeOnlySegmentCounter++; - } - - start += flashAccessInfo.SegmentSize; - } - - if (executeOnlySegmentCounter < 1u) - { - *access_state = kFLASH_AccessStateUnLimited; - } - else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount) - { - *access_state = kFLASH_AccessStateMixed; - } - else - { - *access_state = kFLASH_AccessStateExecuteOnly; - } - } -#else - *access_state = kFLASH_AccessStateUnLimited; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - - return (returnCode); -} - -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -{ - if ((config == NULL) || (value == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - switch (whichProperty) - { - case kFLASH_PropertyPflashSectorSize: - *value = config->PFlashSectorSize; - break; - - case kFLASH_PropertyPflashTotalSize: - *value = config->PFlashTotalSize; - break; - - case kFLASH_PropertyPflashBlockSize: - *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; - break; - - case kFLASH_PropertyPflashBlockCount: - *value = config->PFlashBlockCount; - break; - - case kFLASH_PropertyPflashBlockBaseAddr: - *value = config->PFlashBlockBase; - break; - - case kFLASH_PropertyPflashFacSupport: -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) - *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; -#else - *value = 0; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - break; - - case kFLASH_PropertyPflashAccessSegmentSize: - *value = config->PFlashAccessSegmentSize; - break; - - case kFLASH_PropertyPflashAccessSegmentCount: - *value = config->PFlashAccessSegmentCount; - break; - - case kFLASH_PropertyFlexRamBlockBaseAddr: - *value = config->FlexRAMBlockBase; - break; - - case kFLASH_PropertyFlexRamTotalSize: - *value = config->FlexRAMTotalSize; - break; - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - case kFLASH_PropertyDflashSectorSize: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; - break; - case kFLASH_PropertyDflashTotalSize: - *value = config->DFlashTotalSize; - break; - case kFLASH_PropertyDflashBlockSize: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE; - break; - case kFLASH_PropertyDflashBlockCount: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; - break; - case kFLASH_PropertyDflashBlockBaseAddr: - *value = config->DFlashBlockBase; - break; - case kFLASH_PropertyEepromTotalSize: - *value = config->EEpromTotalSize; - break; -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - - default: /* catch inputs that are not recognized */ - return kStatus_FLASH_UnknownProperty; - } - - return kStatus_FLASH_Success; -} - -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED -status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value) -{ - status_t status = kStatus_FLASH_Success; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - switch (whichProperty) - { - case kFLASH_PropertyFlashMemoryIndex: - if ((value != (uint32_t)kFLASH_MemoryIndexPrimaryFlash) && - (value != (uint32_t)kFLASH_MemoryIndexSecondaryFlash)) - { - return kStatus_FLASH_InvalidPropertyValue; - } - config->FlashMemoryIndex = value; - break; - - case kFLASH_PropertyPflashSectorSize: - case kFLASH_PropertyPflashTotalSize: - case kFLASH_PropertyPflashBlockSize: - case kFLASH_PropertyPflashBlockCount: - case kFLASH_PropertyPflashBlockBaseAddr: - case kFLASH_PropertyPflashFacSupport: - case kFLASH_PropertyPflashAccessSegmentSize: - case kFLASH_PropertyPflashAccessSegmentCount: - case kFLASH_PropertyFlexRamBlockBaseAddr: - case kFLASH_PropertyFlexRamTotalSize: -#if FLASH_SSD_IS_FLEXNVM_ENABLED - case kFLASH_PropertyDflashSectorSize: - case kFLASH_PropertyDflashTotalSize: - case kFLASH_PropertyDflashBlockSize: - case kFLASH_PropertyDflashBlockCount: - case kFLASH_PropertyDflashBlockBaseAddr: - case kFLASH_PropertyEepromTotalSize: -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - status = kStatus_FLASH_ReadOnlyProperty; - break; - default: /* catch inputs that are not recognized */ - status = kStatus_FLASH_UnknownProperty; - break; - } - - return status; -} -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED */ - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option) -{ - status_t status; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - status = flasn_check_flexram_function_option_range(option); - if (status != kStatus_FLASH_Success) - { - return status; - } - - /* preparing passing parameter to verify all block command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -status_t FLASH_SwapControl(flash_config_t *config, - uint32_t address, - flash_swap_control_option_t option, - flash_swap_state_config_t *returnInfo) -{ - status_t returnCode; - - if ((config == NULL) || (returnInfo == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1)) - { - return kStatus_FLASH_AlignmentError; - } - - /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */ - if ((address >= (config->PFlashTotalSize / 2)) || - ((address >= kFLASH_ConfigAreaStart) && (address <= kFLASH_ConfigAreaEnd))) - { - return kStatus_FLASH_SwapIndicatorAddressError; - } - - /* Check the option. */ - returnCode = flash_check_swap_control_option(option); - if (returnCode) - { - return returnCode; - } - - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - - returnCode = flash_command_sequence(config); - - returnInfo->flashSwapState = (flash_swap_state_t)FTFx_FCCOB5_REG; - returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB6_REG; - returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB7_REG; - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option) -{ - flash_swap_state_config_t returnInfo; - status_t returnCode; - - memset(&returnInfo, 0xFFU, sizeof(returnInfo)); - - do - { - returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionReportStatus, &returnInfo); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - - if (kFLASH_SwapFunctionOptionDisable == option) - { - if (returnInfo.flashSwapState == kFLASH_SwapStateDisabled) - { - return kStatus_FLASH_Success; - } - else if (returnInfo.flashSwapState == kFLASH_SwapStateUninitialized) - { - /* The swap system changed to the DISABLED state with Program flash block 0 - * located at relative flash address 0x0_0000 */ - returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionDisableSystem, &returnInfo); - } - else - { - /* Swap disable should be requested only when swap system is in the uninitialized state */ - return kStatus_FLASH_SwapSystemNotInUninitialized; - } - } - else - { - /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset, - * the swap procedure should be Uninitialized -> Update-Erased -> Complete. - * After the first swap has been completed, the flash swap inidicator address cannot be modified - * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased -> - * Complete. */ - switch (returnInfo.flashSwapState) - { - case kFLASH_SwapStateUninitialized: - /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionIntializeSystem, &returnInfo); - break; - case kFLASH_SwapStateReady: - /* Validate whether the address provided to the swap system is matched to - * swap indicator address in the IFR */ - returnCode = flash_validate_swap_indicator_address(config, address); - if (returnCode == kStatus_FLASH_Success) - { - /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInUpdateState, &returnInfo); - } - break; - case kFLASH_SwapStateUpdate: - /* If current swap mode is Update, Erase indicator sector in non active block - * to proceed swap system to update-erased state */ - returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1), - FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_ApiEraseKey); - break; - case kFLASH_SwapStateUpdateErased: - /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInCompleteState, &returnInfo); - break; - case kFLASH_SwapStateComplete: - break; - case kFLASH_SwapStateDisabled: - /* When swap system is in disabled state, We need to clear swap system back to uninitialized - * by issuing EraseAllBlocks command */ - returnCode = kStatus_FLASH_SwapSystemNotInUninitialized; - break; - default: - returnCode = kStatus_FLASH_InvalidArgument; - break; - } - } - if (returnCode != kStatus_FLASH_Success) - { - break; - } - } while (!((kFLASH_SwapStateComplete == returnInfo.flashSwapState) && (kFLASH_SwapFunctionOptionEnable == option))); - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD -status_t FLASH_ProgramPartition(flash_config_t *config, - flash_partition_flexram_load_option_t option, - uint32_t eepromDataSizeCode, - uint32_t flexnvmPartitionCode) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0 - * or it will cause access error. */ - /* eepromDataSizeCode &= 0x3FU; */ - /* flexnvmPartitionCode &= 0x0FU; */ - - /* preparing passing parameter to program the flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be updated by program partition command during reset sequence, - * so we just set reserved values for partitioned FlexNVM size here */ - config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif - - return (returnCode); -} -#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */ - -status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint32_t)kFLASH_MemoryIndexSecondaryFlash) - { - *kFPROTSL = protectStatus->valueLow32b.prots16b.protsl; - if (protectStatus->valueLow32b.prots16b.protsl != *kFPROTSL) - { - return kStatus_FLASH_CommandFailure; - } - - *kFPROTSH = protectStatus->valueLow32b.prots16b.protsh; - if (protectStatus->valueLow32b.prots16b.protsh != *kFPROTSH) - { - return kStatus_FLASH_CommandFailure; - } - } - else -#endif - { - *kFPROTL = protectStatus->valueLow32b.protl32b; - if (protectStatus->valueLow32b.protl32b != *kFPROTL) - { - return kStatus_FLASH_CommandFailure; - } - -#if defined(FTFx_FPROT_HIGH_REG) - *kFPROTH = protectStatus->valueHigh32b.proth32b; - if (protectStatus->valueHigh32b.proth32b != *kFPROTH) - { - return kStatus_FLASH_CommandFailure; - } -#endif - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint32_t)kFLASH_MemoryIndexSecondaryFlash) - { - protectStatus->valueLow32b.prots16b.protsl = *kFPROTSL; - protectStatus->valueLow32b.prots16b.protsh = *kFPROTSH; - } - else -#endif - { - protectStatus->valueLow32b.protl32b = *kFPROTL; -#if defined(FTFx_FPROT_HIGH_REG) - protectStatus->valueHigh32b.proth32b = *kFPROTH; -#endif - } - - return kStatus_FLASH_Success; -} - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - FTFx->FDPROT = protectStatus; - - if (FTFx->FDPROT != protectStatus) - { - return kStatus_FLASH_CommandFailure; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - *protectStatus = FTFx->FDPROT; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - FTFx->FEPROT = protectStatus; - - if (FTFx->FEPROT != protectStatus) - { - return kStatus_FLASH_CommandFailure; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - *protectStatus = FTFx->FEPROT; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -status_t FLASH_PflashSetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - void (*flashCommonBitOperationCallback)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, - uint32_t bitValue); - uint32_t flashCommonBitOperationBuffer[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; - - assert(sizeof(s_flashCommonBitOperationFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); - - memcpy((void *)flashCommonBitOperationBuffer, (void *)s_flashCommonBitOperationFunctionCode, - sizeof(s_flashCommonBitOperationFunctionCode)); - flashCommonBitOperationCallback = (void (*)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, - uint32_t bitValue))((uint32_t)flashCommonBitOperationBuffer + 1); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS - { - FTFx_REG32_ACCESS_TYPE regBase; -#if defined(MCM) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM->PLACR; -#elif defined(MCM0) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR; -#endif - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable) - { - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - return kStatus_FLASH_InvalidSpeculationOption; - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, MCM_PLACR_DFCS_MASK, MCM_PLACR_DFCS_SHIFT, 1U); -#else - *regBase |= MCM_PLACR_DFCS_MASK; -#endif - } - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, MCM_PLACR_DFCS_MASK, MCM_PLACR_DFCS_SHIFT, 0U); -#else - *regBase &= ~MCM_PLACR_DFCS_MASK; -#endif - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, MCM_PLACR_EFDS_MASK, MCM_PLACR_EFDS_SHIFT, 1U); -#else - *regBase |= MCM_PLACR_EFDS_MASK; -#endif - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, MCM_PLACR_EFDS_MASK, MCM_PLACR_EFDS_SHIFT, 0U); -#else - *regBase &= ~MCM_PLACR_EFDS_MASK; -#endif - } - } - } -#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS - { - FTFx_REG32_ACCESS_TYPE regBase; - uint32_t b0dpeMask, b0ipeMask; -#if FLASH_DRIVER_IS_FLASH_RESIDENT - uint32_t b0dpeShift, b0ipeShift; -#endif -#if defined(FMC_PFB01CR_B0DPE_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - b0dpeMask = FMC_PFB01CR_B0DPE_MASK; - b0ipeMask = FMC_PFB01CR_B0IPE_MASK; -#if FLASH_DRIVER_IS_FLASH_RESIDENT - b0dpeShift = FMC_PFB01CR_B0DPE_SHIFT; - b0ipeShift = FMC_PFB01CR_B0IPE_SHIFT; -#endif -#elif defined(FMC_PFB0CR_B0DPE_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - b0dpeMask = FMC_PFB0CR_B0DPE_MASK; - b0ipeMask = FMC_PFB0CR_B0IPE_MASK; -#if FLASH_DRIVER_IS_FLASH_RESIDENT - b0dpeShift = FMC_PFB0CR_B0DPE_SHIFT; - b0ipeShift = FMC_PFB0CR_B0IPE_SHIFT; -#endif -#endif - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionEnable) - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, b0ipeMask, b0ipeShift, 1U); -#else - *regBase |= b0ipeMask; -#endif - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, b0ipeMask, b0ipeShift, 0U); -#else - *regBase &= ~b0ipeMask; -#endif - } - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, b0dpeMask, b0dpeShift, 1U); -#else - *regBase |= b0dpeMask; -#endif - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, b0dpeMask, b0dpeShift, 0U); -#else - *regBase &= ~b0dpeMask; -#endif - } - -/* Invalidate Prefetch Speculation Buffer */ -#if defined(FMC_PFB01CR_S_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK; -#elif defined(FMC_PFB0CR_S_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK; -#endif - } -#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS - { - FTFx_REG32_ACCESS_TYPE regBase; - uint32_t flashSpeculationMask, dataPrefetchMask; -#if FLASH_DRIVER_IS_FLASH_RESIDENT - uint32_t flashSpeculationShift, dataPrefetchShift; - flashSpeculationShift = MSCM_OCMDR_OCMC1_DFCS_SHIFT; - dataPrefetchShift = MSCM_OCMDR_OCMC1_DFDS_SHIFT; -#endif - - regBase = (FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]; - flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK; - dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK; - - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable) - { - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - return kStatus_FLASH_InvalidSpeculationOption; - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, flashSpeculationMask, flashSpeculationShift, 1U); -#else - *regBase |= flashSpeculationMask; -#endif - } - } - else - { - *regBase &= ~flashSpeculationMask; - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, dataPrefetchMask, dataPrefetchShift, 0U); -#else - *regBase &= ~dataPrefetchMask; -#endif - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback(regBase, dataPrefetchMask, dataPrefetchShift, 1U); -#else - *regBase |= dataPrefetchMask; -#endif - } - } - } -#else -#if FLASH_DRIVER_IS_FLASH_RESIDENT - flashCommonBitOperationCallback((FTFx_REG32_ACCESS_TYPE)0, 0, 0, 0); -#endif -#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ - - return kStatus_FLASH_Success; -} - -status_t FLASH_PflashGetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus) -{ - memset(speculationStatus, 0, sizeof(flash_prefetch_speculation_status_t)); - - /* Assuming that all speculation options are enabled. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionEnable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionEnable; - -#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS - { - uint32_t value; -#if defined(MCM) - value = MCM->PLACR; -#elif defined(MCM0) - value = MCM0->PLACR; -#endif - if (value & MCM_PLACR_DFCS_MASK) - { - /* Speculation buffer is off. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - else - { - /* Speculation buffer is on for instruction. */ - if (!(value & MCM_PLACR_EFDS_MASK)) - { - /* Speculation buffer is off for data. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - } - } -#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS - { - uint32_t value; - uint32_t b0dpeMask, b0ipeMask; -#if defined(FMC_PFB01CR_B0DPE_MASK) - value = FMC->PFB01CR; - b0dpeMask = FMC_PFB01CR_B0DPE_MASK; - b0ipeMask = FMC_PFB01CR_B0IPE_MASK; -#elif defined(FMC_PFB0CR_B0DPE_MASK) - value = FMC->PFB0CR; - b0dpeMask = FMC_PFB0CR_B0DPE_MASK; - b0ipeMask = FMC_PFB0CR_B0IPE_MASK; -#endif - if (!(value & b0dpeMask)) - { - /* Do not prefetch in response to data references. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - if (!(value & b0ipeMask)) - { - /* Do not prefetch in response to instruction fetches. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - } - } -#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS - { - uint32_t value; - uint32_t flashSpeculationMask, dataPrefetchMask; - value = MSCM->OCMDR[0]; - flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK; - dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK; - - if (value & flashSpeculationMask) - { - /* Speculation buffer is off. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - else - { - /* Speculation buffer is on for instruction. */ - if (value & dataPrefetchMask) - { - /* Speculation buffer is off for data. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - } - } -#endif - - return kStatus_FLASH_Success; -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! - * @brief Copy PIC of flash_run_command() to RAM - */ -static void copy_flash_run_command(uint32_t *flashRunCommand) -{ - assert(sizeof(s_flashRunCommandFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); - - /* Since the value of ARM function pointer is always odd, but the real start address - * of function memory should be even, that's why +1 operation exist. */ - memcpy((void *)flashRunCommand, (void *)s_flashRunCommandFunctionCode, sizeof(s_flashRunCommandFunctionCode)); - callFlashRunCommand = (void (*)(FTFx_REG8_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1); -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! - * @brief Flash Command Sequence - * - * This function is used to perform the command write sequence to the flash. - * - * @param driver Pointer to storage for the driver runtime state. - * @return An error code or kStatus_FLASH_Success - */ -static status_t flash_command_sequence(flash_config_t *config) -{ - uint8_t registerValue; - -#if FLASH_DRIVER_IS_FLASH_RESIDENT - /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ - FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; - - status_t returnCode = flash_check_execute_in_ram_function_info(config); - if (kStatus_FLASH_Success != returnCode) - { - return returnCode; - } - - /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using - * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() - * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ - callFlashRunCommand((FTFx_REG8_ACCESS_TYPE)(&FTFx->FSTAT)); -#else - /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ - FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; - - /* clear CCIF bit */ - FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK; - - /* Check CCIF bit of the flash status register, wait till it is set. - * IP team indicates that this loop will always complete. */ - while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK)) - { - } -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - - /* Check error bits */ - /* Get flash status register value */ - registerValue = FTFx->FSTAT; - - /* checking access error */ - if (registerValue & FTFx_FSTAT_ACCERR_MASK) - { - return kStatus_FLASH_AccessError; - } - /* checking protection error */ - else if (registerValue & FTFx_FSTAT_FPVIOL_MASK) - { - return kStatus_FLASH_ProtectionViolation; - } - /* checking MGSTAT0 non-correctable error */ - else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK) - { - return kStatus_FLASH_CommandFailure; - } - else - { - return kStatus_FLASH_Success; - } -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! - * @brief Copy PIC of flash_common_bit_operation() to RAM - * - */ -static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation) -{ - assert(sizeof(s_flashCommonBitOperationFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); - - /* Since the value of ARM function pointer is always odd, but the real start address - * of function memory should be even, that's why +1 operation exist. */ - memcpy((void *)flashCommonBitOperation, (void *)s_flashCommonBitOperationFunctionCode, - sizeof(s_flashCommonBitOperationFunctionCode)); - callFlashCommonBitOperation = (void (*)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, - uint32_t bitValue))((uint32_t)flashCommonBitOperation + 1); -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! - * @brief Flash Cache Clear - * - * This function is used to perform the cache clear to the flash. - */ -#if (defined(__GNUC__)) -/* #pragma GCC push_options */ -/* #pragma GCC optimize("O0") */ -void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config) -#else -#if (defined(__ICCARM__)) -#pragma optimize = none -#endif -#if (defined(__CC_ARM)) -#pragma push -#pragma O0 -#endif -void flash_cache_clear(flash_config_t *config) -#endif -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0; - status_t returnCode = flash_check_execute_in_ram_function_info(config); - if (kStatus_FLASH_Success != returnCode) - { - return; - } - -/* We pass the ftfx register address as a parameter to flash_common_bit_operation() instead of using - * pre-processed MACROs or a global variable in flash_common_bit_operation() - * to make sure that flash_common_bit_operation() will be compiled into position-independent code (PIC). */ -#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS -#if defined(MCM) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM->PLACR; - callFlashCommonBitOperation(regBase, MCM_PLACR_CFCC_MASK, MCM_PLACR_CFCC_SHIFT, 1U); -#endif -#if defined(MCM0) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR; - callFlashCommonBitOperation(regBase, MCM_PLACR_CFCC_MASK, MCM_PLACR_CFCC_SHIFT, 1U); -#endif -#if defined(MCM1) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1->PLACR; - callFlashCommonBitOperation(regBase, MCM_PLACR_CFCC_MASK, MCM_PLACR_CFCC_SHIFT, 1U); -#endif -#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS -#if defined(FMC_PFB01CR_CINV_WAY_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - callFlashCommonBitOperation(regBase, FMC_PFB01CR_CINV_WAY_MASK, FMC_PFB01CR_CINV_WAY_SHIFT, 0xFU); -#else - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY_SHIFT, 0xFU); -#endif -#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS - regBase = (FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]; -#if defined(MSCM_OCMDR_OCM1_MASK) - callFlashCommonBitOperation(regBase, MSCM_OCMDR_OCM1_MASK, MSCM_OCMDR_OCM1_SHIFT, 0x3U); -#else - callFlashCommonBitOperation(regBase, MSCM_OCMDR_OCMC1_MASK, MSCM_OCMDR_OCMC1_SHIFT, 0x3U); -#endif -#if FLASH_SSD_IS_FLEXNVM_ENABLED - regBase = (FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[1]; -#if defined(MSCM_OCMDR_OCM1_MASK) - callFlashCommonBitOperation(regBase, MSCM_OCMDR_OCM1_MASK, MSCM_OCMDR_OCM1_SHIFT, 0x3U); -#else - callFlashCommonBitOperation(regBase, MSCM_OCMDR_OCMC1_MASK, MSCM_OCMDR_OCMC1_SHIFT, 0x3U); -#endif -#endif -#else -#if defined(FMC_PFB0CR_S_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_INV_MASK, FMC_PFB0CR_S_INV_SHIFT, 1U); -#elif defined(FMC_PFB01CR_S_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_INV_MASK, FMC_PFB01CR_S_INV_SHIFT, 1U); -#endif -/* #error "Unknown flash cache controller" */ -#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ - - callFlashCommonBitOperation(regBase, 0, 0, 0); -#else - -#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS -#if defined(MCM) - MCM->PLACR |= MCM_PLACR_CFCC_MASK; -#endif -#if defined(MCM0) - MCM0->PLACR |= MCM_PLACR_CFCC_MASK; -#endif -#if defined(MCM1) - MCM1->PLACR |= MCM_PLACR_CFCC_MASK; -#endif -#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS -#if defined(FMC_PFB01CR_CINV_WAY_MASK) - FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); -#else - FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); -#endif -#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS -#if defined(MSCM_OCMDR_OCM1_MASK) - MSCM->OCMDR[0] |= MSCM_OCMDR_OCM1(3); -#else - MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(3); -#endif -#if FLASH_SSD_IS_FLEXNVM_ENABLED -#if defined(MSCM_OCMDR_OCM1_MASK) - MSCM->OCMDR[1] |= MSCM_OCMDR_OCM1(3); -#else - MSCM->OCMDR[1] |= MSCM_OCMDR_OCMC1(3); -#endif -#endif -#else -#if defined(FMC_PFB0CR_S_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK; -#elif defined(FMC_PFB01CR_S_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK; -#endif -/* #error "Unknown flash cache controller" */ -#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ - - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#if (defined(__GNUC__)) -/* #pragma GCC pop_options */ -#else -#if (defined(__CC_ARM)) -#pragma pop -#endif -#endif - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief Check whether flash execute-in-ram functions are ready */ -static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) -{ - flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; - - if ((config->flashExecuteInRamFunctionInfo) && - (kFLASH_ExecuteInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount)) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_ExecuteInRamFunctionNotReady; -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! @brief Validates the range and alignment of the given address range.*/ -static status_t flash_check_range(flash_config_t *config, - uint32_t startAddress, - uint32_t lengthInBytes, - uint32_t alignmentBaseline) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Verify the start and length are alignmentBaseline aligned. */ - if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) - { - return kStatus_FLASH_AlignmentError; - } - - /* check for valid range of the target addresses */ - if ( -#if FLASH_SSD_IS_FLEXNVM_ENABLED - ((startAddress >= config->DFlashBlockBase) && - ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize))) || -#endif - ((startAddress >= config->PFlashBlockBase) && - ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize)))) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_AddressError; -} - -/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ -static status_t flash_get_matched_operation_info(flash_config_t *config, - uint32_t address, - flash_operation_config_t *info) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_operation_config_t)); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize))) - { - /* When required by the command, address bit 23 selects between program flash memory - * (=0) and data flash memory (=1).*/ - info->convertedAddress = address - config->DFlashBlockBase + 0x800000U; - info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; - info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; - - info->blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE; - info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT; - info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT; - info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT; - info->checkCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT; - } - else -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - { - info->convertedAddress = address - config->PFlashBlockBase; - info->activeSectorSize = config->PFlashSectorSize; - info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount; -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED - if (config->FlashMemoryIndex == (uint32_t)kFLASH_MemoryIndexSecondaryFlash) - { -#if FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER || FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - /* When required by the command, address bit 23 selects between main flash memory - * (=0) and secondary flash memory (=1).*/ - info->convertedAddress += 0x800000U; -#endif - info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE; - } - else -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED */ - { - info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE; - } - - info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; - info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; - info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT; - info->checkCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT; - } - - return kStatus_FLASH_Success; -} - -/*! @brief Validates the given user key for flash erase APIs.*/ -static status_t flash_check_user_key(uint32_t key) -{ - /* Validate the user key */ - if (key != kFLASH_ApiEraseKey) - { - return kStatus_FLASH_EraseKeyError; - } - - return kStatus_FLASH_Success; -} - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ -static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config) -{ - struct - { - uint32_t reserved0; - uint8_t FlexNVMPartitionCode; - uint8_t EEPROMDataSetSize; - uint16_t reserved1; - } dataIFRReadOut; - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Get FlexNVM memory partition info from data flash IFR */ - returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut, - sizeof(dataIFRReadOut), kFLASH_ResourceOptionFlashIfr); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_PartitionStatusUpdateFailure; - } - - /* Fill out partitioned EEPROM size */ - dataIFRReadOut.EEPROMDataSetSize &= 0x0FU; - switch (dataIFRReadOut.EEPROMDataSetSize) - { - case 0x00U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000; - break; - case 0x01U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001; - break; - case 0x02U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010; - break; - case 0x03U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011; - break; - case 0x04U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100; - break; - case 0x05U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101; - break; - case 0x06U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110; - break; - case 0x07U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111; - break; - case 0x08U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000; - break; - case 0x09U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001; - break; - case 0x0AU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010; - break; - case 0x0BU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011; - break; - case 0x0CU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100; - break; - case 0x0DU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101; - break; - case 0x0EU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110; - break; - case 0x0FU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111; - break; - default: - config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; - break; - } - - /* Fill out partitioned DFlash size */ - dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU; - switch (dataIFRReadOut.FlexNVMPartitionCode) - { - case 0x00U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */ - break; - case 0x01U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */ - break; - case 0x02U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */ - break; - case 0x03U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */ - break; - case 0x04U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */ - break; - case 0x05U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */ - break; - case 0x06U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */ - break; - case 0x07U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */ - break; - case 0x08U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */ - break; - case 0x09U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */ - break; - case 0x0AU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */ - break; - case 0x0BU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */ - break; - case 0x0CU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */ - break; - case 0x0DU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */ - break; - case 0x0EU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */ - break; - case 0x0FU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */ - break; - default: - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; - break; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -/*! @brief Validates the range of the given resource address.*/ -static status_t flash_check_resource_range(uint32_t start, - uint32_t lengthInBytes, - uint32_t alignmentBaseline, - flash_read_resource_option_t option) -{ - status_t status; - uint32_t maxReadbleAddress; - - if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) - { - return kStatus_FLASH_AlignmentError; - } - - status = kStatus_FLASH_Success; - - maxReadbleAddress = start + lengthInBytes - 1; - if (option == kFLASH_ResourceOptionVersionId) - { - if ((start != kFLASH_ResourceRangeVersionIdStart) || - ((start + lengthInBytes - 1) != kFLASH_ResourceRangeVersionIdEnd)) - { - status = kStatus_FLASH_InvalidArgument; - } - } - else if (option == kFLASH_ResourceOptionFlashIfr) - { - if (maxReadbleAddress < kFLASH_ResourceRangePflashIfrSizeInBytes) - { - } -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP - else if ((start >= kFLASH_ResourceRangePflashSwapIfrStart) && - (maxReadbleAddress <= kFLASH_ResourceRangePflashSwapIfrEnd)) - { - } -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - else if ((start >= kFLASH_ResourceRangeDflashIfrStart) && - (maxReadbleAddress <= kFLASH_ResourceRangeDflashIfrEnd)) - { - } - else - { - status = kStatus_FLASH_InvalidArgument; - } - } - else - { - status = kStatus_FLASH_InvalidArgument; - } - - return status; -} -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -/*! @brief Validates the gived swap control option.*/ -static status_t flash_check_swap_control_option(flash_swap_control_option_t option) -{ - if ((option == kFLASH_SwapControlOptionIntializeSystem) || (option == kFLASH_SwapControlOptionSetInUpdateState) || - (option == kFLASH_SwapControlOptionSetInCompleteState) || (option == kFLASH_SwapControlOptionReportStatus) || - (option == kFLASH_SwapControlOptionDisableSystem)) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_InvalidArgument; -} -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ -static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address) -{ - flash_swap_ifr_field_data_t flashSwapIfrFieldData; - uint32_t swapIndicatorAddress; - - status_t returnCode; - returnCode = - FLASH_ReadResource(config, kFLASH_ResourceRangePflashSwapIfrStart, flashSwapIfrFieldData.flashSwapIfrData, - sizeof(flashSwapIfrFieldData.flashSwapIfrData), kFLASH_ResourceOptionFlashIfr); - - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - - /* The high bits value of Swap Indicator Address is stored in Program Flash Swap IFR Field, - * the low severval bit value of Swap Indicator Address is always 1'b0 */ - swapIndicatorAddress = (uint32_t)flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress * - FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT; - if (address != swapIndicatorAddress) - { - return kStatus_FLASH_SwapIndicatorAddressError; - } - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -/*! @brief Validates the gived flexram function option.*/ -static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option) -{ - if ((option != kFLASH_FlexramFunctionOptionAvailableAsRam) && - (option != kFLASH_FlexramFunctionOptionAvailableForEeprom)) - { - return kStatus_FLASH_InvalidArgument; - } - - return kStatus_FLASH_Success; -} -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -/*! @brief Gets the flash protection information (region size, region count).*/ -static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info) -{ - uint32_t pflashTotalSize; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_protection_config_t)); - -/* Note: KW40 has a secondary flash, but it doesn't have independent protection register*/ -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER) - pflashTotalSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE + - FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; - info->regionBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; -#else - pflashTotalSize = config->PFlashTotalSize; - info->regionBase = config->PFlashBlockBase; -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint32_t)kFLASH_MemoryIndexSecondaryFlash) - { - info->regionCount = FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT; - } - else -#endif - { - info->regionCount = FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT; - } - - /* Calculate the size of the flash protection region - * If the flash density is > 32KB, then protection region is 1/32 of total flash density - * Else if flash density is < 32KB, then flash protection region is set to 1KB */ - if (pflashTotalSize > info->regionCount * 1024) - { - info->regionSize = (pflashTotalSize) / info->regionCount; - } - else - { - info->regionSize = 1024; - } - - return kStatus_FLASH_Success; -} - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/ -static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_access_config_t)); - -/* Note: KW40 has a secondary flash, but it doesn't have independent access register*/ -#if FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER) - info->SegmentBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; -#else - info->SegmentBase = config->PFlashBlockBase; -#endif - info->SegmentSize = config->PFlashAccessSegmentSize; - info->SegmentCount = config->PFlashAccessSegmentCount; - - return kStatus_FLASH_Success; -} -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_flash.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_flash.h deleted file mode 100644 index 457309c..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_flash.h +++ /dev/null @@ -1,1368 +0,0 @@ -/* - * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_FLASH_H_ -#define _FSL_FLASH_H_ - -#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM)) -#include -#include -#include "fsl_device_registers.h" -#include "bootloader_common.h" -#else -#include "fsl_common.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup flash_driver - * @{ - */ - -/*! - * @name Flash version - * @{ - */ -/*! @brief Constructs the version number for drivers. */ -#if !defined(MAKE_VERSION) -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#endif - -/*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*!< Version 2.2.0. */ - -/*! @brief Flash driver version for ROM*/ -enum _flash_driver_version_constants -{ - kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ - kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 2, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ -}; -/*@}*/ - -/*! - * @name Flash configuration - * @{ - */ -/*! @brief Indicates whether to support FlexNVM in the Flash driver */ -#if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT) -#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enables the FlexNVM support by default. */ -#endif - -/*! @brief Indicates whether the FlexNVM is enabled in the Flash driver */ -#define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM) - -/*! @brief Indicates whether the secondary flash is supported in the Flash driver */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) -#define FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED (1) -#else -#define FLASH_SSD_IS_SECONDARY_FLASH_SUPPORTED (0) -#endif - -/*! @brief Indicates whether the secondary flash has its own protection register in flash module */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FPROTS_PROTS_MASK) -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (1) -#else -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (0) -#endif - -/*! @brief Indicates whether the secondary flash has its own Execute-Only access register in flash module */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FACSSS_SGSIZE_S_MASK) -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (1) -#else -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (0) -#endif - -/*! @brief Flash driver location. */ -#if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT) -#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM)) -#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for the flash resident application. */ -#else -#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for the non-flash resident application. */ -#endif -#endif - -/*! @brief Flash Driver Export option */ -#if !defined(FLASH_DRIVER_IS_EXPORTED) -#if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH)) -#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for the ROM bootloader. */ -#else -#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for the KSDK application. */ -#endif -#endif -/*@}*/ - -/*! - * @name Flash status - * @{ - */ -/*! @brief Flash driver status group. */ -#if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FlashDriver -#elif defined(kStatusGroup_FLASH) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FLASH -#else -#define kStatusGroupGeneric 0 -#define kStatusGroupFlashDriver 1 -#endif - -/*! @brief Constructs a status code value from a group and a code number. */ -#if !defined(MAKE_STATUS) -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) -#endif - -/*! - * @brief Flash driver status codes. - */ -enum _flash_status -{ - kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ - kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ - kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ - kStatus_FLASH_AlignmentError = - MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ - kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ - kStatus_FLASH_AccessError = - MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ - kStatus_FLASH_ProtectionViolation = MAKE_STATUS( - kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ - kStatus_FLASH_CommandFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ - kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ - kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ - kStatus_FLASH_RegionExecuteOnly = - MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ - kStatus_FLASH_ExecuteInRamFunctionNotReady = - MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ - kStatus_FLASH_PartitionStatusUpdateFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/ - kStatus_FLASH_SetFlexramAsEepromError = - MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set FlexRAM as EEPROM.*/ - kStatus_FLASH_RecoverFlexramAsRamError = - MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover FlexRAM as RAM.*/ - kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set FlexRAM as RAM.*/ - kStatus_FLASH_RecoverFlexramAsEepromError = - MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover FlexRAM as EEPROM.*/ - kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash API is not supported.*/ - kStatus_FLASH_SwapSystemNotInUninitialized = - MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in an uninitialzed state.*/ - kStatus_FLASH_SwapIndicatorAddressError = - MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< The swap indicator address is invalid.*/ - kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 18), /*!< The flash property is read-only.*/ - kStatus_FLASH_InvalidPropertyValue = - MAKE_STATUS(kStatusGroupFlashDriver, 19), /*!< The flash property value is out of range.*/ - kStatus_FLASH_InvalidSpeculationOption = - MAKE_STATUS(kStatusGroupFlashDriver, 20), /*!< The option of flash prefetch speculation is invalid.*/ -}; -/*@}*/ - -/*! - * @name Flash API key - * @{ - */ -/*! @brief Constructs the four character code for the Flash driver API key. */ -#if !defined(FOUR_CHAR_CODE) -#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) -#endif - -/*! - * @brief Enumeration for Flash driver API keys. - * - * @note The resulting value is built with a byte order such that the string - * being readable in expected order when viewed in a hex editor, if the value - * is treated as a 32-bit little endian value. - */ -enum _flash_driver_api_keys -{ - kFLASH_ApiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ -}; -/*@}*/ - -/*! - * @brief Enumeration for supported flash margin levels. - */ -typedef enum _flash_margin_value -{ - kFLASH_MarginValueNormal, /*!< Use the 'normal' read level for 1s.*/ - kFLASH_MarginValueUser, /*!< Apply the 'User' margin to the normal read-1 level.*/ - kFLASH_MarginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/ - kFLASH_MarginValueInvalid /*!< Not real margin level, Used to determine the range of valid margin level. */ -} flash_margin_value_t; - -/*! - * @brief Enumeration for the three possible flash security states. - */ -typedef enum _flash_security_state -{ - kFLASH_SecurityStateNotSecure, /*!< Flash is not secure.*/ - kFLASH_SecurityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/ - kFLASH_SecurityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/ -} flash_security_state_t; - -/*! - * @brief Enumeration for the three possible flash protection levels. - */ -typedef enum _flash_protection_state -{ - kFLASH_ProtectionStateUnprotected, /*!< Flash region is not protected.*/ - kFLASH_ProtectionStateProtected, /*!< Flash region is protected.*/ - kFLASH_ProtectionStateMixed /*!< Flash is mixed with protected and unprotected region.*/ -} flash_protection_state_t; - -/*! - * @brief Enumeration for the three possible flash execute access levels. - */ -typedef enum _flash_execute_only_access_state -{ - kFLASH_AccessStateUnLimited, /*!< Flash region is unlimited.*/ - kFLASH_AccessStateExecuteOnly, /*!< Flash region is execute only.*/ - kFLASH_AccessStateMixed /*!< Flash is mixed with unlimited and execute only region.*/ -} flash_execute_only_access_state_t; - -/*! - * @brief Enumeration for various flash properties. - */ -typedef enum _flash_property_tag -{ - kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ - kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ - kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ - kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ - kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - kFLASH_PropertyPflashFacSupport = 0x05U, /*!< Pflash fac support property.*/ - kFLASH_PropertyPflashAccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ - kFLASH_PropertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ - kFLASH_PropertyFlexRamBlockBaseAddr = 0x08U, /*!< FlexRam block base address property.*/ - kFLASH_PropertyFlexRamTotalSize = 0x09U, /*!< FlexRam total size property.*/ - kFLASH_PropertyDflashSectorSize = 0x10U, /*!< Dflash sector size property.*/ - kFLASH_PropertyDflashTotalSize = 0x11U, /*!< Dflash total size property.*/ - kFLASH_PropertyDflashBlockSize = 0x12U, /*!< Dflash block size property.*/ - kFLASH_PropertyDflashBlockCount = 0x13U, /*!< Dflash block count property.*/ - kFLASH_PropertyDflashBlockBaseAddr = 0x14U, /*!< Dflash block base address property.*/ - kFLASH_PropertyEepromTotalSize = 0x15U, /*!< EEPROM total size property.*/ - kFLASH_PropertyFlashMemoryIndex = 0x20U /*!< Flash memory index property.*/ -} flash_property_tag_t; - -/*! - * @brief Constants for execute-in-RAM flash function. - */ -enum _flash_execute_in_ram_function_constants -{ - kFLASH_ExecuteInRamFunctionMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/ - kFLASH_ExecuteInRamFunctionTotalNum = 2U /*!< Total number of execute-in-RAM functions.*/ -}; - -/*! - * @brief Flash execute-in-RAM function information. - */ -typedef struct _flash_execute_in_ram_function_config -{ - uint32_t activeFunctionCount; /*!< Number of available execute-in-RAM functions.*/ - uint32_t *flashRunCommand; /*!< Execute-in-RAM function: flash_run_command.*/ - uint32_t *flashCommonBitOperation; /*!< Execute-in-RAM function: flash_common_bit_operation.*/ -} flash_execute_in_ram_function_config_t; - -/*! - * @brief Enumeration for the two possible options of flash read resource command. - */ -typedef enum _flash_read_resource_option -{ - kFLASH_ResourceOptionFlashIfr = - 0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */ - kFLASH_ResourceOptionVersionId = 0x01U /*!< Select code for the version ID*/ -} flash_read_resource_option_t; - -/*! - * @brief Enumeration for the range of special-purpose flash resource - */ -enum _flash_read_resource_range -{ -#if (FSL_FEATURE_FLASH_IS_FTFE == 1) - kFLASH_ResourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdStart = 0x08U, /*!< Version ID IFR start address.*/ - kFLASH_ResourceRangeVersionIdEnd = 0x0FU, /*!< Version ID IFR end address.*/ - kFLASH_ResourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/ - kFLASH_ResourceRangePflashSwapIfrEnd = - (kFLASH_ResourceRangePflashSwapIfrStart + 0x3FFU), /*!< Pflash swap IFR end address.*/ -#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ - kFLASH_ResourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdStart = 0x00U, /*!< Version ID IFR start address.*/ - kFLASH_ResourceRangeVersionIdEnd = 0x07U, /*!< Version ID IFR end address.*/ -#if 0x20000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x8000U, /*!< Pflash swap IFR start address.*/ -#elif 0x40000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x10000U, /*!< Pflash swap IFR start address.*/ -#elif 0x80000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x20000U, /*!< Pflash swap IFR start address.*/ -#else - kFLASH_ResourceRangePflashSwapIfrStart = 0, -#endif - kFLASH_ResourceRangePflashSwapIfrEnd = - (kFLASH_ResourceRangePflashSwapIfrStart + 0xFFU), /*!< Pflash swap IFR end address.*/ -#endif - kFLASH_ResourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/ - kFLASH_ResourceRangeDflashIfrEnd = 0x8003FFU, /*!< Dflash IFR end address.*/ -}; - -/*! - * @brief Enumeration for the two possilbe options of set FlexRAM function command. - */ -typedef enum _flash_flexram_function_option -{ - kFLASH_FlexramFunctionOptionAvailableAsRam = 0xFFU, /*!< An option used to make FlexRAM available as RAM */ - kFLASH_FlexramFunctionOptionAvailableForEeprom = 0x00U /*!< An option used to make FlexRAM available for EEPROM */ -} flash_flexram_function_option_t; - -/*! - * @brief Enumeration for acceleration RAM property. - */ -enum _flash_acceleration_ram_property -{ - kFLASH_AccelerationRamSize = 0x400U -}; - -/*! - * @brief Enumeration for the possible options of Swap function - */ -typedef enum _flash_swap_function_option -{ - kFLASH_SwapFunctionOptionEnable = 0x00U, /*!< An option used to enable the Swap function */ - kFLASH_SwapFunctionOptionDisable = 0x01U /*!< An option used to disable the Swap function */ -} flash_swap_function_option_t; - -/*! - * @brief Enumeration for the possible options of Swap control commands - */ -typedef enum _flash_swap_control_option -{ - kFLASH_SwapControlOptionIntializeSystem = 0x01U, /*!< An option used to initialize the Swap system */ - kFLASH_SwapControlOptionSetInUpdateState = 0x02U, /*!< An option used to set the Swap in an update state */ - kFLASH_SwapControlOptionSetInCompleteState = 0x04U, /*!< An option used to set the Swap in a complete state */ - kFLASH_SwapControlOptionReportStatus = 0x08U, /*!< An option used to report the Swap status */ - kFLASH_SwapControlOptionDisableSystem = 0x10U /*!< An option used to disable the Swap status */ -} flash_swap_control_option_t; - -/*! - * @brief Enumeration for the possible flash Swap status. - */ -typedef enum _flash_swap_state -{ - kFLASH_SwapStateUninitialized = 0x00U, /*!< Flash Swap system is in an uninitialized state.*/ - kFLASH_SwapStateReady = 0x01U, /*!< Flash Swap system is in a ready state.*/ - kFLASH_SwapStateUpdate = 0x02U, /*!< Flash Swap system is in an update state.*/ - kFLASH_SwapStateUpdateErased = 0x03U, /*!< Flash Swap system is in an updateErased state.*/ - kFLASH_SwapStateComplete = 0x04U, /*!< Flash Swap system is in a complete state.*/ - kFLASH_SwapStateDisabled = 0x05U /*!< Flash Swap system is in a disabled state.*/ -} flash_swap_state_t; - -/*! - * @breif Enumeration for the possible flash Swap block status - */ -typedef enum _flash_swap_block_status -{ - kFLASH_SwapBlockStatusLowerHalfProgramBlocksAtZero = - 0x00U, /*!< Swap block status is that lower half program block at zero.*/ - kFLASH_SwapBlockStatusUpperHalfProgramBlocksAtZero = - 0x01U, /*!< Swap block status is that upper half program block at zero.*/ -} flash_swap_block_status_t; - -/*! - * @brief Flash Swap information - */ -typedef struct _flash_swap_state_config -{ - flash_swap_state_t flashSwapState; /*!SYNC; - /* Enable PWM synchronization of output mask register */ - syncReg |= FTM_SYNC_SYNCHOM_MASK; - - reg = base->COMBINE; - for (chnlNumber = 0; chnlNumber < (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2); chnlNumber++) - { - /* Enable PWM synchronization of registers C(n)V and C(n+1)V */ - reg |= (1U << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber))); - } - base->COMBINE = reg; - - reg = base->SYNCONF; - - /* Use enhanced PWM synchronization method. Use PWM sync to update register values */ - reg |= (FTM_SYNCONF_SYNCMODE_MASK | FTM_SYNCONF_CNTINC_MASK | FTM_SYNCONF_INVC_MASK | FTM_SYNCONF_SWOC_MASK); - - if (syncMethod & FTM_SYNC_SWSYNC_MASK) - { - /* Enable needed bits for software trigger to update registers with its buffer value */ - reg |= (FTM_SYNCONF_SWRSTCNT_MASK | FTM_SYNCONF_SWWRBUF_MASK | FTM_SYNCONF_SWINVC_MASK | - FTM_SYNCONF_SWSOC_MASK | FTM_SYNCONF_SWOM_MASK); - } - - if (syncMethod & (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK)) - { - /* Enable needed bits for hardware trigger to update registers with its buffer value */ - reg |= (FTM_SYNCONF_HWRSTCNT_MASK | FTM_SYNCONF_HWWRBUF_MASK | FTM_SYNCONF_HWINVC_MASK | - FTM_SYNCONF_HWSOC_MASK | FTM_SYNCONF_HWOM_MASK); - - /* Enable the appropriate hardware trigger that is used for PWM sync */ - if (syncMethod & FTM_SYNC_TRIG0_MASK) - { - syncReg |= FTM_SYNC_TRIG0_MASK; - } - if (syncMethod & FTM_SYNC_TRIG1_MASK) - { - syncReg |= FTM_SYNC_TRIG1_MASK; - } - if (syncMethod & FTM_SYNC_TRIG2_MASK) - { - syncReg |= FTM_SYNC_TRIG2_MASK; - } - } - - /* Write back values to the SYNC register */ - base->SYNC = syncReg; - - /* Write the PWM synch values to the SYNCONF register */ - base->SYNCONF = reg; -} - -static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints) -{ - uint32_t chnlNumber = 0; - uint32_t reg = 0; - - /* Need CNTINC bit to be 1 for CNTIN register to update with its buffer value on reload */ - base->SYNCONF |= FTM_SYNCONF_CNTINC_MASK; - - reg = base->COMBINE; - for (chnlNumber = 0; chnlNumber < (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2); chnlNumber++) - { - /* Need SYNCEN bit to be 1 for CnV reg to update with its buffer value on reload */ - reg |= (1U << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber))); - } - base->COMBINE = reg; - - /* Set the reload points */ - reg = base->PWMLOAD; - - /* Enable the selected channel match reload points */ - reg &= ~((1U << FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) - 1); - reg |= (reloadPoints & ((1U << FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) - 1)); - -#if defined(FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD) && (FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD) - /* Enable half cycle match as a reload point */ - if (reloadPoints & kFTM_HalfCycMatch) - { - reg |= FTM_PWMLOAD_HCSEL_MASK; - } - else - { - reg &= ~FTM_PWMLOAD_HCSEL_MASK; - } -#endif /* FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD */ - - base->PWMLOAD = reg; - - /* These reload points are used when counter is in up-down counting mode */ - reg = base->SYNC; - if (reloadPoints & kFTM_CntMax) - { - /* Reload when counter turns from up to down */ - reg |= FTM_SYNC_CNTMAX_MASK; - } - else - { - reg &= ~FTM_SYNC_CNTMAX_MASK; - } - - if (reloadPoints & kFTM_CntMin) - { - /* Reload when counter turns from down to up */ - reg |= FTM_SYNC_CNTMIN_MASK; - } - else - { - reg &= ~FTM_SYNC_CNTMIN_MASK; - } - base->SYNC = reg; -} - -status_t FTM_Init(FTM_Type *base, const ftm_config_t *config) -{ - assert(config); - - uint32_t reg; - - if (!(config->pwmSyncMode & - (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK | FTM_SYNC_SWSYNC_MASK))) - { - /* Invalid PWM sync mode */ - return kStatus_Fail; - } - - /* Ungate the FTM clock*/ - CLOCK_EnableClock(s_ftmClocks[FTM_GetInstance(base)]); - - /* Configure the fault mode, enable FTM mode and disable write protection */ - base->MODE = FTM_MODE_FAULTM(config->faultMode) | FTM_MODE_FTMEN_MASK | FTM_MODE_WPDIS_MASK; - - /* Configure the update mechanism for buffered registers */ - FTM_SetPwmSync(base, config->pwmSyncMode); - - /* Setup intermediate register reload points */ - FTM_SetReloadPoints(base, config->reloadPoints); - - /* Set the clock prescale factor */ - base->SC = FTM_SC_PS(config->prescale); - - /* Setup the counter operation */ - base->CONF = (FTM_CONF_BDMMODE(config->bdmMode) | FTM_CONF_GTBEEN(config->useGlobalTimeBase)); - - /* Initial state of channel output */ - base->OUTINIT = config->chnlInitState; - - /* Channel polarity */ - base->POL = config->chnlPolarity; - - /* Set the external trigger sources */ - base->EXTTRIG = config->extTriggers; -#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) && (FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) - if (config->extTriggers & kFTM_ReloadInitTrigger) - { - base->CONF |= FTM_CONF_ITRIGR_MASK; - } - else - { - base->CONF &= ~FTM_CONF_ITRIGR_MASK; - } -#endif /* FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER */ - - /* FTM deadtime insertion control */ - base->DEADTIME = (FTM_DEADTIME_DTPS(config->deadTimePrescale) | FTM_DEADTIME_DTVAL(config->deadTimeValue)); - - /* FTM fault filter value */ - reg = base->FLTCTRL; - reg &= ~FTM_FLTCTRL_FFVAL_MASK; - reg |= FTM_FLTCTRL_FFVAL(config->faultFilterValue); - base->FLTCTRL = reg; - - return kStatus_Success; -} - -void FTM_Deinit(FTM_Type *base) -{ - /* Set clock source to none to disable counter */ - base->SC &= ~(FTM_SC_CLKS_MASK); - - /* Gate the FTM clock */ - CLOCK_DisableClock(s_ftmClocks[FTM_GetInstance(base)]); -} - -void FTM_GetDefaultConfig(ftm_config_t *config) -{ - assert(config); - - /* Divide FTM clock by 1 */ - config->prescale = kFTM_Prescale_Divide_1; - /* FTM behavior in BDM mode */ - config->bdmMode = kFTM_BdmMode_0; - /* Software trigger will be used to update registers */ - config->pwmSyncMode = kFTM_SoftwareTrigger; - /* No intermediate register load */ - config->reloadPoints = 0; - /* Fault control disabled for all channels */ - config->faultMode = kFTM_Fault_Disable; - /* Disable the fault filter */ - config->faultFilterValue = 0; - /* Divide the system clock by 1 */ - config->deadTimePrescale = kFTM_Deadtime_Prescale_1; - /* No counts are inserted */ - config->deadTimeValue = 0; - /* No external trigger */ - config->extTriggers = 0; - /* Initialization value is 0 for all channels */ - config->chnlInitState = 0; - /* Active high polarity for all channels */ - config->chnlPolarity = 0; - /* Use internal FTM counter as timebase */ - config->useGlobalTimeBase = false; -} - -status_t FTM_SetupPwm(FTM_Type *base, - const ftm_chnl_pwm_signal_param_t *chnlParams, - uint8_t numOfChnls, - ftm_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz) -{ - assert(chnlParams); - assert(srcClock_Hz); - assert(pwmFreq_Hz); - assert(numOfChnls); - - uint32_t mod, reg; - uint32_t ftmClock = (srcClock_Hz / (1U << (base->SC & FTM_SC_PS_MASK))); - uint16_t cnv, cnvFirstEdge; - uint8_t i; - - switch (mode) - { - case kFTM_EdgeAlignedPwm: - case kFTM_CombinedPwm: - base->SC &= ~FTM_SC_CPWMS_MASK; - mod = (ftmClock / pwmFreq_Hz) - 1; - break; - case kFTM_CenterAlignedPwm: - base->SC |= FTM_SC_CPWMS_MASK; - mod = ftmClock / (pwmFreq_Hz * 2); - break; - default: - return kStatus_Fail; - } - - /* Return an error in case we overflow the registers, probably would require changing - * clock source to get the desired frequency */ - if (mod > 65535U) - { - return kStatus_Fail; - } - /* Set the PWM period */ - base->MOD = mod; - - /* Setup each FTM channel */ - for (i = 0; i < numOfChnls; i++) - { - /* Return error if requested dutycycle is greater than the max allowed */ - if (chnlParams->dutyCyclePercent > 100) - { - return kStatus_Fail; - } - - if ((mode == kFTM_EdgeAlignedPwm) || (mode == kFTM_CenterAlignedPwm)) - { - /* Clear the current mode and edge level bits */ - reg = base->CONTROLS[chnlParams->chnlNumber].CnSC; - reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); - - /* Setup the active level */ - reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT); - - /* Edge-aligned mode needs MSB to be 1, don't care for Center-aligned mode */ - reg |= FTM_CnSC_MSB(1U); - - /* Update the mode and edge level */ - base->CONTROLS[chnlParams->chnlNumber].CnSC = reg; - - if (chnlParams->dutyCyclePercent == 0) - { - /* Signal stays low */ - cnv = 0; - } - else - { - cnv = (mod * chnlParams->dutyCyclePercent) / 100; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - } - - base->CONTROLS[chnlParams->chnlNumber].CnV = cnv; -#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) - /* Set to output mode */ - FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true); -#endif - } - else - { - /* This check is added for combined mode as the channel number should be the pair number */ - if (chnlParams->chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2)) - { - return kStatus_Fail; - } - - /* Return error if requested value is greater than the max allowed */ - if (chnlParams->firstEdgeDelayPercent > 100) - { - return kStatus_Fail; - } - - /* Configure delay of the first edge */ - if (chnlParams->firstEdgeDelayPercent == 0) - { - /* No delay for the first edge */ - cnvFirstEdge = 0; - } - else - { - cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100; - } - - /* Configure dutycycle */ - if (chnlParams->dutyCyclePercent == 0) - { - /* Signal stays low */ - cnv = 0; - cnvFirstEdge = 0; - } - else - { - cnv = (mod * chnlParams->dutyCyclePercent) / 100; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - } - - /* Clear the current mode and edge level bits for channel n */ - reg = base->CONTROLS[chnlParams->chnlNumber * 2].CnSC; - reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); - - /* Setup the active level for channel n */ - reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT); - - /* Update the mode and edge level for channel n */ - base->CONTROLS[chnlParams->chnlNumber * 2].CnSC = reg; - - /* Clear the current mode and edge level bits for channel n + 1 */ - reg = base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC; - reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); - - /* Setup the active level for channel n + 1 */ - reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT); - - /* Update the mode and edge level for channel n + 1*/ - base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC = reg; - - /* Set the combine bit for the channel pair */ - base->COMBINE |= - (1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlParams->chnlNumber))); - - /* Set the channel pair values */ - base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge; - base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; - -#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) - /* Set to output mode */ - FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2), true); - FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2 + 1), true); -#endif - } - chnlParams++; - } - - return kStatus_Success; -} - -void FTM_UpdatePwmDutycycle(FTM_Type *base, - ftm_chnl_t chnlNumber, - ftm_pwm_mode_t currentPwmMode, - uint8_t dutyCyclePercent) -{ - uint16_t cnv, cnvFirstEdge = 0, mod; - - mod = base->MOD; - if ((currentPwmMode == kFTM_EdgeAlignedPwm) || (currentPwmMode == kFTM_CenterAlignedPwm)) - { - cnv = (mod * dutyCyclePercent) / 100; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - base->CONTROLS[chnlNumber].CnV = cnv; - } - else - { - /* This check is added for combined mode as the channel number should be the pair number */ - if (chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2)) - { - return; - } - - cnv = (mod * dutyCyclePercent) / 100; - cnvFirstEdge = base->CONTROLS[chnlNumber * 2].CnV; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - base->CONTROLS[(chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; - } -} - -void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level) -{ - uint32_t reg = base->CONTROLS[chnlNumber].CnSC; - - /* Clear the field and write the new level value */ - reg &= ~(FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); - reg |= ((uint32_t)level << FTM_CnSC_ELSA_SHIFT) & (FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); - - base->CONTROLS[chnlNumber].CnSC = reg; -} - -void FTM_SetupInputCapture(FTM_Type *base, - ftm_chnl_t chnlNumber, - ftm_input_capture_edge_t captureMode, - uint32_t filterValue) -{ - uint32_t reg; - - /* Clear the combine bit for the channel pair */ - base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); - /* Clear the dual edge capture mode because it's it's higher priority */ - base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); - /* Clear the quadrature decoder mode beacause it's higher priority */ - base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK; - - reg = base->CONTROLS[chnlNumber].CnSC; - reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); - reg |= captureMode; - - /* Set the requested input capture mode */ - base->CONTROLS[chnlNumber].CnSC = reg; - /* Input filter available only for channels 0, 1, 2, 3 */ - if (chnlNumber < kFTM_Chnl_4) - { - reg = base->FILTER; - reg &= ~(FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * chnlNumber)); - reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * chnlNumber)); - base->FILTER = reg; - } -#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) - /* Set to input mode */ - FTM_SetPwmOutputEnable(base, chnlNumber, false); -#endif -} - -void FTM_SetupOutputCompare(FTM_Type *base, - ftm_chnl_t chnlNumber, - ftm_output_compare_mode_t compareMode, - uint32_t compareValue) -{ - uint32_t reg; - - /* Clear the combine bit for the channel pair */ - base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); - /* Clear the dual edge capture mode because it's it's higher priority */ - base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); - /* Clear the quadrature decoder mode beacause it's higher priority */ - base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK; - - reg = base->CONTROLS[chnlNumber].CnSC; - reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); - reg |= compareMode; - /* Setup the channel output behaviour when a match occurs with the compare value */ - base->CONTROLS[chnlNumber].CnSC = reg; - - /* Set output on match to the requested level */ - base->CONTROLS[chnlNumber].CnV = compareValue; - -#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) - /* Set to output mode */ - FTM_SetPwmOutputEnable(base, chnlNumber, true); -#endif -} - -void FTM_SetupDualEdgeCapture(FTM_Type *base, - ftm_chnl_t chnlPairNumber, - const ftm_dual_edge_capture_param_t *edgeParam, - uint32_t filterValue) -{ - assert(edgeParam); - - uint32_t reg; - - reg = base->COMBINE; - /* Clear the combine bit for the channel pair */ - reg &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); - /* Enable the DECAPEN bit */ - reg |= (1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); - reg |= (1U << (FTM_COMBINE_DECAP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); - base->COMBINE = reg; - - /* Setup the edge detection from channel n and n + 1 */ - reg = base->CONTROLS[chnlPairNumber * 2].CnSC; - reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); - reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->currChanEdgeMode); - base->CONTROLS[chnlPairNumber * 2].CnSC = reg; - - reg = base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC; - reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); - reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->nextChanEdgeMode); - base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC = reg; - - /* Input filter available only for channels 0, 1, 2, 3 */ - if (chnlPairNumber < kFTM_Chnl_4) - { - reg = base->FILTER; - reg &= ~(FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); - reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); - base->FILTER = reg; - } - -#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) - /* Set to input mode */ - FTM_SetPwmOutputEnable(base, chnlPairNumber, false); -#endif -} - -void FTM_SetupQuadDecode(FTM_Type *base, - const ftm_phase_params_t *phaseAParams, - const ftm_phase_params_t *phaseBParams, - ftm_quad_decode_mode_t quadMode) -{ - assert(phaseAParams); - assert(phaseBParams); - - uint32_t reg; - - /* Set Phase A filter value if phase filter is enabled */ - if (phaseAParams->enablePhaseFilter) - { - reg = base->FILTER; - reg &= ~(FTM_FILTER_CH0FVAL_MASK); - reg |= FTM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal); - base->FILTER = reg; - } - - /* Set Phase B filter value if phase filter is enabled */ - if (phaseBParams->enablePhaseFilter) - { - reg = base->FILTER; - reg &= ~(FTM_FILTER_CH1FVAL_MASK); - reg |= FTM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal); - base->FILTER = reg; - } - - /* Set Quadrature decode properties */ - reg = base->QDCTRL; - reg &= ~(FTM_QDCTRL_QUADMODE_MASK | FTM_QDCTRL_PHAFLTREN_MASK | FTM_QDCTRL_PHBFLTREN_MASK | FTM_QDCTRL_PHAPOL_MASK | - FTM_QDCTRL_PHBPOL_MASK); - reg |= (FTM_QDCTRL_QUADMODE(quadMode) | FTM_QDCTRL_PHAFLTREN(phaseAParams->enablePhaseFilter) | - FTM_QDCTRL_PHBFLTREN(phaseBParams->enablePhaseFilter) | FTM_QDCTRL_PHAPOL(phaseAParams->phasePolarity) | - FTM_QDCTRL_PHBPOL(phaseBParams->phasePolarity)); - base->QDCTRL = reg; - /* Enable Quad decode */ - base->QDCTRL |= FTM_QDCTRL_QUADEN_MASK; -} - -void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams) -{ - assert(faultParams); - - uint32_t reg; - - reg = base->FLTCTRL; - if (faultParams->enableFaultInput) - { - /* Enable the fault input */ - reg |= (FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); - } - else - { - /* Disable the fault input */ - reg &= ~(FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); - } - - if (faultParams->useFaultFilter) - { - /* Enable the fault filter */ - reg |= (FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); - } - else - { - /* Disable the fault filter */ - reg &= ~(FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); - } - base->FLTCTRL = reg; - - if (faultParams->faultLevel) - { - /* Active low polarity for the fault input pin */ - base->FLTPOL |= (1U << faultNumber); - } - else - { - /* Active high polarity for the fault input pin */ - base->FLTPOL &= ~(1U << faultNumber); - } -} - -void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask) -{ - uint32_t chnlInts = (mask & 0xFFU); - uint8_t chnlNumber = 0; - - /* Enable the timer overflow interrupt */ - if (mask & kFTM_TimeOverflowInterruptEnable) - { - base->SC |= FTM_SC_TOIE_MASK; - } - - /* Enable the fault interrupt */ - if (mask & kFTM_FaultInterruptEnable) - { - base->MODE |= FTM_MODE_FAULTIE_MASK; - } - -#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) - /* Enable the reload interrupt available only on certain SoC's */ - if (mask & kFTM_ReloadInterruptEnable) - { - base->SC |= FTM_SC_RIE_MASK; - } -#endif - - /* Enable the channel interrupts */ - while (chnlInts) - { - if (chnlInts & 0x1) - { - base->CONTROLS[chnlNumber].CnSC |= FTM_CnSC_CHIE_MASK; - } - chnlNumber++; - chnlInts = chnlInts >> 1U; - } -} - -void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask) -{ - uint32_t chnlInts = (mask & 0xFF); - uint8_t chnlNumber = 0; - - /* Disable the timer overflow interrupt */ - if (mask & kFTM_TimeOverflowInterruptEnable) - { - base->SC &= ~FTM_SC_TOIE_MASK; - } - /* Disable the fault interrupt */ - if (mask & kFTM_FaultInterruptEnable) - { - base->MODE &= ~FTM_MODE_FAULTIE_MASK; - } - -#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) - /* Disable the reload interrupt available only on certain SoC's */ - if (mask & kFTM_ReloadInterruptEnable) - { - base->SC &= ~FTM_SC_RIE_MASK; - } -#endif - - /* Disable the channel interrupts */ - while (chnlInts) - { - if (chnlInts & 0x1) - { - base->CONTROLS[chnlNumber].CnSC &= ~FTM_CnSC_CHIE_MASK; - } - chnlNumber++; - chnlInts = chnlInts >> 1U; - } -} - -uint32_t FTM_GetEnabledInterrupts(FTM_Type *base) -{ - uint32_t enabledInterrupts = 0; - int8_t chnlCount = FSL_FEATURE_FTM_CHANNEL_COUNTn(base); - - /* The CHANNEL_COUNT macro returns -1 if it cannot match the FTM instance */ - assert(chnlCount != -1); - - /* Check if timer overflow interrupt is enabled */ - if (base->SC & FTM_SC_TOIE_MASK) - { - enabledInterrupts |= kFTM_TimeOverflowInterruptEnable; - } - /* Check if fault interrupt is enabled */ - if (base->MODE & FTM_MODE_FAULTIE_MASK) - { - enabledInterrupts |= kFTM_FaultInterruptEnable; - } - -#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) - /* Check if the reload interrupt is enabled */ - if (base->SC & FTM_SC_RIE_MASK) - { - enabledInterrupts |= kFTM_ReloadInterruptEnable; - } -#endif - - /* Check if the channel interrupts are enabled */ - while (chnlCount > 0) - { - chnlCount--; - if (base->CONTROLS[chnlCount].CnSC & FTM_CnSC_CHIE_MASK) - { - enabledInterrupts |= (1U << chnlCount); - } - } - - return enabledInterrupts; -} - -uint32_t FTM_GetStatusFlags(FTM_Type *base) -{ - uint32_t statusFlags = 0; - - /* Check the timer flag */ - if (base->SC & FTM_SC_TOF_MASK) - { - statusFlags |= kFTM_TimeOverflowFlag; - } - /* Check fault flag */ - if (base->FMS & FTM_FMS_FAULTF_MASK) - { - statusFlags |= kFTM_FaultFlag; - } - /* Check channel trigger flag */ - if (base->EXTTRIG & FTM_EXTTRIG_TRIGF_MASK) - { - statusFlags |= kFTM_ChnlTriggerFlag; - } -#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) - /* Check reload flag */ - if (base->SC & FTM_SC_RF_MASK) - { - statusFlags |= kFTM_ReloadFlag; - } -#endif - - /* Lower 8 bits contain the channel status flags */ - statusFlags |= (base->STATUS & 0xFFU); - - return statusFlags; -} - -void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask) -{ - /* Clear the timer overflow flag by writing a 0 to the bit while it is set */ - if (mask & kFTM_TimeOverflowFlag) - { - base->SC &= ~FTM_SC_TOF_MASK; - } - /* Clear fault flag by writing a 0 to the bit while it is set */ - if (mask & kFTM_FaultFlag) - { - base->FMS &= ~FTM_FMS_FAULTF_MASK; - } - /* Clear channel trigger flag */ - if (mask & kFTM_ChnlTriggerFlag) - { - base->EXTTRIG &= ~FTM_EXTTRIG_TRIGF_MASK; - } - -#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) - /* Check reload flag by writing a 0 to the bit while it is set */ - if (mask & kFTM_ReloadFlag) - { - base->SC &= ~FTM_SC_RF_MASK; - } -#endif - /* Clear the channel status flags by writing a 0 to the bit */ - base->STATUS &= ~(mask & 0xFFU); -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_ftm.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_ftm.h deleted file mode 100644 index 7643635..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_ftm.h +++ /dev/null @@ -1,861 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FTM_H_ -#define _FSL_FTM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ftm - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! - * @brief List of FTM channels - * @note Actual number of available channels is SoC dependent - */ -typedef enum _ftm_chnl -{ - kFTM_Chnl_0 = 0U, /*!< FTM channel number 0*/ - kFTM_Chnl_1, /*!< FTM channel number 1 */ - kFTM_Chnl_2, /*!< FTM channel number 2 */ - kFTM_Chnl_3, /*!< FTM channel number 3 */ - kFTM_Chnl_4, /*!< FTM channel number 4 */ - kFTM_Chnl_5, /*!< FTM channel number 5 */ - kFTM_Chnl_6, /*!< FTM channel number 6 */ - kFTM_Chnl_7 /*!< FTM channel number 7 */ -} ftm_chnl_t; - -/*! @brief List of FTM faults */ -typedef enum _ftm_fault_input -{ - kFTM_Fault_0 = 0U, /*!< FTM fault 0 input pin */ - kFTM_Fault_1, /*!< FTM fault 1 input pin */ - kFTM_Fault_2, /*!< FTM fault 2 input pin */ - kFTM_Fault_3 /*!< FTM fault 3 input pin */ -} ftm_fault_input_t; - -/*! @brief FTM PWM operation modes */ -typedef enum _ftm_pwm_mode -{ - kFTM_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ - kFTM_CenterAlignedPwm, /*!< Center-aligned PWM */ - kFTM_CombinedPwm /*!< Combined PWM */ -} ftm_pwm_mode_t; - -/*! @brief FTM PWM output pulse mode: high-true, low-true or no output */ -typedef enum _ftm_pwm_level_select -{ - kFTM_NoPwmSignal = 0U, /*!< No PWM output on pin */ - kFTM_LowTrue, /*!< Low true pulses */ - kFTM_HighTrue /*!< High true pulses */ -} ftm_pwm_level_select_t; - -/*! @brief Options to configure a FTM channel's PWM signal */ -typedef struct _ftm_chnl_pwm_signal_param -{ - ftm_chnl_t chnlNumber; /*!< The channel/channel pair number. - In combined mode, this represents the channel pair number. */ - ftm_pwm_level_select_t level; /*!< PWM output active level select. */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0 = inactive signal(0% duty cycle)... - 100 = always active signal (100% duty cycle).*/ - uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate an asymmetrical PWM. - Specifies the delay to the first edge in a PWM period. - If unsure leave as 0; Should be specified as a - percentage of the PWM period */ -} ftm_chnl_pwm_signal_param_t; - -/*! @brief FlexTimer output compare mode */ -typedef enum _ftm_output_compare_mode -{ - kFTM_NoOutputSignal = (1U << FTM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */ - kFTM_ToggleOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (1U << FTM_CnSC_ELSA_SHIFT)), /*!< Toggle output */ - kFTM_ClearOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (2U << FTM_CnSC_ELSA_SHIFT)), /*!< Clear output */ - kFTM_SetOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (3U << FTM_CnSC_ELSA_SHIFT)) /*!< Set output */ -} ftm_output_compare_mode_t; - -/*! @brief FlexTimer input capture edge */ -typedef enum _ftm_input_capture_edge -{ - kFTM_RisingEdge = (1U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only*/ - kFTM_FallingEdge = (2U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only*/ - kFTM_RiseAndFallEdge = (3U << FTM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */ -} ftm_input_capture_edge_t; - -/*! @brief FlexTimer dual edge capture modes */ -typedef enum _ftm_dual_edge_capture_mode -{ - kFTM_OneShot = 0U, /*!< One-shot capture mode */ - kFTM_Continuous = (1U << FTM_CnSC_MSA_SHIFT) /*!< Continuous capture mode */ -} ftm_dual_edge_capture_mode_t; - -/*! @brief FlexTimer dual edge capture parameters */ -typedef struct _ftm_dual_edge_capture_param -{ - ftm_dual_edge_capture_mode_t mode; /*!< Dual Edge Capture mode */ - ftm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */ - ftm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */ -} ftm_dual_edge_capture_param_t; - -/*! @brief FlexTimer quadrature decode modes */ -typedef enum _ftm_quad_decode_mode -{ - kFTM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */ - kFTM_QuadCountAndDir /*!< Count and direction encoding mode */ -} ftm_quad_decode_mode_t; - -/*! @brief FlexTimer quadrature phase polarities */ -typedef enum _ftm_phase_polarity -{ - kFTM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */ - kFTM_QuadPhaseInvert /*!< Phase input signal is inverted */ -} ftm_phase_polarity_t; - -/*! @brief FlexTimer quadrature decode phase parameters */ -typedef struct _ftm_phase_param -{ - bool enablePhaseFilter; /*!< True: enable phase filter; false: disable filter */ - uint32_t phaseFilterVal; /*!< Filter value, used only if phase filter is enabled */ - ftm_phase_polarity_t phasePolarity; /*!< Phase polarity */ -} ftm_phase_params_t; - -/*! @brief Structure is used to hold the parameters to configure a FTM fault */ -typedef struct _ftm_fault_param -{ - bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */ - bool faultLevel; /*!< True: Fault polarity is active low i.e., '0' indicates a fault; - False: Fault polarity is active high */ - bool useFaultFilter; /*!< True: Use the filtered fault signal; - False: Use the direct path from fault input */ -} ftm_fault_param_t; - -/*! @brief FlexTimer pre-scaler factor for the dead time insertion*/ -typedef enum _ftm_deadtime_prescale -{ - kFTM_Deadtime_Prescale_1 = 1U, /*!< Divide by 1 */ - kFTM_Deadtime_Prescale_4, /*!< Divide by 4 */ - kFTM_Deadtime_Prescale_16 /*!< Divide by 16 */ -} ftm_deadtime_prescale_t; - -/*! @brief FlexTimer clock source selection*/ -typedef enum _ftm_clock_source -{ - kFTM_SystemClock = 1U, /*!< System clock selected */ - kFTM_FixedClock, /*!< Fixed frequency clock */ - kFTM_ExternalClock /*!< External clock */ -} ftm_clock_source_t; - -/*! @brief FlexTimer pre-scaler factor selection for the clock source*/ -typedef enum _ftm_clock_prescale -{ - kFTM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */ - kFTM_Prescale_Divide_2, /*!< Divide by 2 */ - kFTM_Prescale_Divide_4, /*!< Divide by 4 */ - kFTM_Prescale_Divide_8, /*!< Divide by 8 */ - kFTM_Prescale_Divide_16, /*!< Divide by 16 */ - kFTM_Prescale_Divide_32, /*!< Divide by 32 */ - kFTM_Prescale_Divide_64, /*!< Divide by 64 */ - kFTM_Prescale_Divide_128 /*!< Divide by 128 */ -} ftm_clock_prescale_t; - -/*! @brief Options for the FlexTimer behaviour in BDM Mode */ -typedef enum _ftm_bdm_mode -{ - kFTM_BdmMode_0 = 0U, - /*!< FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V - registers bypass the register buffers */ - kFTM_BdmMode_1, - /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to - MOD,CNTIN and C(n)V registers bypass the register buffers */ - kFTM_BdmMode_2, - /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode, - writes to MOD,CNTIN and C(n)V registers bypass the register buffers */ - kFTM_BdmMode_3 - /*!< FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and - C(n)V registers is in fully functional mode */ -} ftm_bdm_mode_t; - -/*! @brief Options for the FTM fault control mode */ -typedef enum _ftm_fault_mode -{ - kFTM_Fault_Disable = 0U, /*!< Fault control is disabled for all channels */ - kFTM_Fault_EvenChnls, /*!< Enabled for even channels only(0,2,4,6) with manual fault clearing */ - kFTM_Fault_AllChnlsMan, /*!< Enabled for all channels with manual fault clearing */ - kFTM_Fault_AllChnlsAuto /*!< Enabled for all channels with automatic fault clearing */ -} ftm_fault_mode_t; - -/*! - * @brief FTM external trigger options - * @note Actual available external trigger sources are SoC-specific - */ -typedef enum _ftm_external_trigger -{ - kFTM_Chnl0Trigger = (1U << 4), /*!< Generate trigger when counter equals chnl 0 CnV reg */ - kFTM_Chnl1Trigger = (1U << 5), /*!< Generate trigger when counter equals chnl 1 CnV reg */ - kFTM_Chnl2Trigger = (1U << 0), /*!< Generate trigger when counter equals chnl 2 CnV reg */ - kFTM_Chnl3Trigger = (1U << 1), /*!< Generate trigger when counter equals chnl 3 CnV reg */ - kFTM_Chnl4Trigger = (1U << 2), /*!< Generate trigger when counter equals chnl 4 CnV reg */ - kFTM_Chnl5Trigger = (1U << 3), /*!< Generate trigger when counter equals chnl 5 CnV reg */ - kFTM_Chnl6Trigger = - (1U << 8), /*!< Available on certain SoC's, generate trigger when counter equals chnl 6 CnV reg */ - kFTM_Chnl7Trigger = - (1U << 9), /*!< Available on certain SoC's, generate trigger when counter equals chnl 7 CnV reg */ - kFTM_InitTrigger = (1U << 6), /*!< Generate Trigger when counter is updated with CNTIN */ - kFTM_ReloadInitTrigger = (1U << 7) /*!< Available on certain SoC's, trigger on reload point */ -} ftm_external_trigger_t; - -/*! @brief FlexTimer PWM sync options to update registers with buffer */ -typedef enum _ftm_pwm_sync_method -{ - kFTM_SoftwareTrigger = FTM_SYNC_SWSYNC_MASK, /*!< Software triggers PWM sync */ - kFTM_HardwareTrigger_0 = FTM_SYNC_TRIG0_MASK, /*!< Hardware trigger 0 causes PWM sync */ - kFTM_HardwareTrigger_1 = FTM_SYNC_TRIG1_MASK, /*!< Hardware trigger 1 causes PWM sync */ - kFTM_HardwareTrigger_2 = FTM_SYNC_TRIG2_MASK /*!< Hardware trigger 2 causes PWM sync */ -} ftm_pwm_sync_method_t; - -/*! - * @brief FTM options available as loading point for register reload - * @note Actual available reload points are SoC-specific - */ -typedef enum _ftm_reload_point -{ - kFTM_Chnl0Match = (1U << 0), /*!< Channel 0 match included as a reload point */ - kFTM_Chnl1Match = (1U << 1), /*!< Channel 1 match included as a reload point */ - kFTM_Chnl2Match = (1U << 2), /*!< Channel 2 match included as a reload point */ - kFTM_Chnl3Match = (1U << 3), /*!< Channel 3 match included as a reload point */ - kFTM_Chnl4Match = (1U << 4), /*!< Channel 4 match included as a reload point */ - kFTM_Chnl5Match = (1U << 5), /*!< Channel 5 match included as a reload point */ - kFTM_Chnl6Match = (1U << 6), /*!< Channel 6 match included as a reload point */ - kFTM_Chnl7Match = (1U << 7), /*!< Channel 7 match included as a reload point */ - kFTM_CntMax = (1U << 8), /*!< Use in up-down count mode only, reload when counter reaches the maximum value */ - kFTM_CntMin = (1U << 9), /*!< Use in up-down count mode only, reload when counter reaches the minimum value */ - kFTM_HalfCycMatch = (1U << 10) /*!< Available on certain SoC's, half cycle match reload point */ -} ftm_reload_point_t; - -/*! - * @brief List of FTM interrupts - * @note Actual available interrupts are SoC-specific - */ -typedef enum _ftm_interrupt_enable -{ - kFTM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt */ - kFTM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt */ - kFTM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt */ - kFTM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt */ - kFTM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt */ - kFTM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt */ - kFTM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt */ - kFTM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt */ - kFTM_FaultInterruptEnable = (1U << 8), /*!< Fault interrupt */ - kFTM_TimeOverflowInterruptEnable = (1U << 9), /*!< Time overflow interrupt */ - kFTM_ReloadInterruptEnable = (1U << 10) /*!< Reload interrupt; Available only on certain SoC's */ -} ftm_interrupt_enable_t; - -/*! - * @brief List of FTM flags - * @note Actual available flags are SoC-specific - */ -typedef enum _ftm_status_flags -{ - kFTM_Chnl0Flag = (1U << 0), /*!< Channel 0 Flag */ - kFTM_Chnl1Flag = (1U << 1), /*!< Channel 1 Flag */ - kFTM_Chnl2Flag = (1U << 2), /*!< Channel 2 Flag */ - kFTM_Chnl3Flag = (1U << 3), /*!< Channel 3 Flag */ - kFTM_Chnl4Flag = (1U << 4), /*!< Channel 4 Flag */ - kFTM_Chnl5Flag = (1U << 5), /*!< Channel 5 Flag */ - kFTM_Chnl6Flag = (1U << 6), /*!< Channel 6 Flag */ - kFTM_Chnl7Flag = (1U << 7), /*!< Channel 7 Flag */ - kFTM_FaultFlag = (1U << 8), /*!< Fault Flag */ - kFTM_TimeOverflowFlag = (1U << 9), /*!< Time overflow Flag */ - kFTM_ChnlTriggerFlag = (1U << 10), /*!< Channel trigger Flag */ - kFTM_ReloadFlag = (1U << 11) /*!< Reload Flag; Available only on certain SoC's */ -} ftm_status_flags_t; - -/*! - * @brief FTM configuration structure - * - * This structure holds the configuration settings for the FTM peripheral. To initialize this - * structure to reasonable defaults, call the FTM_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _ftm_config -{ - ftm_clock_prescale_t prescale; /*!< FTM clock prescale value */ - ftm_bdm_mode_t bdmMode; /*!< FTM behavior in BDM mode */ - uint32_t pwmSyncMode; /*!< Synchronization methods to use to update buffered registers; Multiple - update modes can be used by providing an OR'ed list of options - available in enumeration ::ftm_pwm_sync_method_t. */ - uint32_t reloadPoints; /*!< FTM reload points; When using this, the PWM - synchronization is not required. Multiple reload points can be used by providing - an OR'ed list of options available in - enumeration ::ftm_reload_point_t. */ - ftm_fault_mode_t faultMode; /*!< FTM fault control mode */ - uint8_t faultFilterValue; /*!< Fault input filter value */ - ftm_deadtime_prescale_t deadTimePrescale; /*!< The dead time prescalar value */ - uint8_t deadTimeValue; /*!< The dead time value */ - uint32_t extTriggers; /*!< External triggers to enable. Multiple trigger sources can be - enabled by providing an OR'ed list of options available in - enumeration ::ftm_external_trigger_t. */ - uint8_t chnlInitState; /*!< Defines the initialization value of the channels in OUTINT register */ - uint8_t chnlPolarity; /*!< Defines the output polarity of the channels in POL register */ - bool useGlobalTimeBase; /*!< True: Use of an external global time base is enabled; - False: disabled */ -} ftm_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the FTM clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the FTM driver. - * - * @param base FTM peripheral base address - * @param config Pointer to the user configuration structure. - * - * @return kStatus_Success indicates success; Else indicates failure. - */ -status_t FTM_Init(FTM_Type *base, const ftm_config_t *config); - -/*! - * @brief Gates the FTM clock. - * - * @param base FTM peripheral base address - */ -void FTM_Deinit(FTM_Type *base); - -/*! - * @brief Fills in the FTM configuration structure with the default settings. - * - * The default values are: - * @code - * config->prescale = kFTM_Prescale_Divide_1; - * config->bdmMode = kFTM_BdmMode_0; - * config->pwmSyncMode = kFTM_SoftwareTrigger; - * config->reloadPoints = 0; - * config->faultMode = kFTM_Fault_Disable; - * config->faultFilterValue = 0; - * config->deadTimePrescale = kFTM_Deadtime_Prescale_1; - * config->deadTimeValue = 0; - * config->extTriggers = 0; - * config->chnlInitState = 0; - * config->chnlPolarity = 0; - * config->useGlobalTimeBase = false; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void FTM_GetDefaultConfig(ftm_config_t *config); - -/*! @}*/ - -/*! - * @name Channel mode operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this - * function to configure all FTM channels that are used to output a PWM signal. - * - * @param base FTM peripheral base address - * @param chnlParams Array of PWM channel parameters to configure the channel(s) - * @param numOfChnls Number of channels to configure; This should be the size of the array passed in - * @param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz FTM counter clock in Hz - * - * @return kStatus_Success if the PWM setup was successful - * kStatus_Error on failure - */ -status_t FTM_SetupPwm(FTM_Type *base, - const ftm_chnl_pwm_signal_param_t *chnlParams, - uint8_t numOfChnls, - ftm_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz); - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @param base FTM peripheral base address - * @param chnlNumber The channel/channel pair number. In combined mode, this represents - * the channel pair number - * @param currentPwmMode The current PWM mode set during PWM setup - * @param dutyCyclePercent New PWM pulse width; The value should be between 0 to 100 - * 0=inactive signal(0% duty cycle)... - * 100=active signal (100% duty cycle) - */ -void FTM_UpdatePwmDutycycle(FTM_Type *base, - ftm_chnl_t chnlNumber, - ftm_pwm_mode_t currentPwmMode, - uint8_t dutyCyclePercent); - -/*! - * @brief Updates the edge level selection for a channel. - * - * @param base FTM peripheral base address - * @param chnlNumber The channel number - * @param level The level to be set to the ELSnB:ELSnA field; Valid values are 00, 01, 10, 11. - * See the Kinetis SoC reference manual for details about this field. - */ -void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level); - -/*! - * @brief Enables capturing an input signal on the channel using the function parameters. - * - * When the edge specified in the captureMode argument occurs on the channel, the FTM counter is - * captured into the CnV register. The user has to read the CnV register separately to get this - * value. The filter function is disabled if the filterVal argument passed in is 0. The filter - * function is available only for channels 0, 1, 2, 3. - * - * @param base FTM peripheral base address - * @param chnlNumber The channel number - * @param captureMode Specifies which edge to capture - * @param filterValue Filter value, specify 0 to disable filter. Available only for channels 0-3. - */ -void FTM_SetupInputCapture(FTM_Type *base, - ftm_chnl_t chnlNumber, - ftm_input_capture_edge_t captureMode, - uint32_t filterValue); - -/*! - * @brief Configures the FTM to generate timed pulses. - * - * When the FTM counter matches the value of compareVal argument (this is written into CnV reg), - * the channel output is changed based on what is specified in the compareMode argument. - * - * @param base FTM peripheral base address - * @param chnlNumber The channel number - * @param compareMode Action to take on the channel output when the compare condition is met - * @param compareValue Value to be programmed in the CnV register. - */ -void FTM_SetupOutputCompare(FTM_Type *base, - ftm_chnl_t chnlNumber, - ftm_output_compare_mode_t compareMode, - uint32_t compareValue); - -/*! - * @brief Configures the dual edge capture mode of the FTM. - * - * This function sets up the dual edge capture mode on a channel pair. The capture edge for the - * channel pair and the capture mode (one-shot or continuous) is specified in the parameter - * argument. The filter function is disabled if the filterVal argument passed is zero. The filter - * function is available only on channels 0 and 2. The user has to read the channel CnV registers - * separately to get the capture values. - * - * @param base FTM peripheral base address - * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 - * @param edgeParam Sets up the dual edge capture function - * @param filterValue Filter value, specify 0 to disable filter. Available only for channel pair 0 and 1. - */ -void FTM_SetupDualEdgeCapture(FTM_Type *base, - ftm_chnl_t chnlPairNumber, - const ftm_dual_edge_capture_param_t *edgeParam, - uint32_t filterValue); - -/*! @}*/ - -/*! - * @brief Configures the parameters and activates the quadrature decoder mode. - * - * @param base FTM peripheral base address - * @param phaseAParams Phase A configuration parameters - * @param phaseBParams Phase B configuration parameters - * @param quadMode Selects encoding mode used in quadrature decoder mode - */ -void FTM_SetupQuadDecode(FTM_Type *base, - const ftm_phase_params_t *phaseAParams, - const ftm_phase_params_t *phaseBParams, - ftm_quad_decode_mode_t quadMode); - -/*! - * @brief Sets up the working of the FTM fault protection. - * - * FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and a filter. - * - * @param base FTM peripheral base address - * @param faultNumber FTM fault to configure. - * @param faultParams Parameters passed in to set up the fault - */ -void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected FTM interrupts. - * - * @param base FTM peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ftm_interrupt_enable_t - */ -void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask); - -/*! - * @brief Disables the selected FTM interrupts. - * - * @param base FTM peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ftm_interrupt_enable_t - */ -void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask); - -/*! - * @brief Gets the enabled FTM interrupts. - * - * @param base FTM peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::ftm_interrupt_enable_t - */ -uint32_t FTM_GetEnabledInterrupts(FTM_Type *base); - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the FTM status flags. - * - * @param base FTM peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::ftm_status_flags_t - */ -uint32_t FTM_GetStatusFlags(FTM_Type *base); - -/*! - * @brief Clears the FTM status flags. - * - * @param base FTM peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::ftm_status_flags_t - */ -void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask); - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the FTM counter. - * - * @param base FTM peripheral base address - * @param clockSource FTM clock source; After the clock source is set, the counter starts running. - */ -static inline void FTM_StartTimer(FTM_Type *base, ftm_clock_source_t clockSource) -{ - uint32_t reg = base->SC; - - reg &= ~(FTM_SC_CLKS_MASK); - reg |= FTM_SC_CLKS(clockSource); - base->SC = reg; -} - -/*! - * @brief Stops the FTM counter. - * - * @param base FTM peripheral base address - */ -static inline void FTM_StopTimer(FTM_Type *base) -{ - /* Set clock source to none to disable counter */ - base->SC &= ~(FTM_SC_CLKS_MASK); -} - -/*! @}*/ - -/*! - * @name Software output control - * @{ - */ - -/*! - * @brief Enables or disables the channel software output control. - * - * @param base FTM peripheral base address - * @param chnlNumber Channel to be enabled or disabled - * @param value true: channel output is affected by software output control - false: channel output is unaffected by software output control - */ -static inline void FTM_SetSoftwareCtrlEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) -{ - if (value) - { - base->SWOCTRL |= (1U << chnlNumber); - } - else - { - base->SWOCTRL &= ~(1U << chnlNumber); - } -} - -/*! - * @brief Sets the channel software output control value. - * - * @param base FTM peripheral base address. - * @param chnlNumber Channel to be configured - * @param value true to set 1, false to set 0 - */ -static inline void FTM_SetSoftwareCtrlVal(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) -{ - if (value) - { - base->SWOCTRL |= (1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT)); - } - else - { - base->SWOCTRL &= ~(1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT)); - } -} - -/*! @}*/ - -/*! - * @brief Enables or disables the FTM global time base signal generation to other FTMs. - * - * @param base FTM peripheral base address - * @param enable true to enable, false to disable - */ -static inline void FTM_SetGlobalTimeBaseOutputEnable(FTM_Type *base, bool enable) -{ - if (enable) - { - base->CONF |= FTM_CONF_GTBEOUT_MASK; - } - else - { - base->CONF &= ~FTM_CONF_GTBEOUT_MASK; - } -} - -/*! - * @brief Sets the FTM peripheral timer channel output mask. - * - * @param base FTM peripheral base address - * @param chnlNumber Channel to be configured - * @param mask true: masked, channel is forced to its inactive state; false: unmasked - */ -static inline void FTM_SetOutputMask(FTM_Type *base, ftm_chnl_t chnlNumber, bool mask) -{ - if (mask) - { - base->OUTMASK |= (1U << chnlNumber); - } - else - { - base->OUTMASK &= ~(1U << chnlNumber); - } -} - -#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) -/*! - * @brief Allows user to enable an output on an FTM channel. - * - * To enable the PWM channel output call this function with val=true. For input mode, - * call this function with val=false. - * - * @param base FTM peripheral base address - * @param chnlNumber Channel to be configured - * @param value true: enable output; false: output is disabled, used in input mode - */ -static inline void FTM_SetPwmOutputEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) -{ - if (value) - { - base->SC |= (1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT)); - } - else - { - base->SC &= ~(1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT)); - } -} -#endif - -/*! - * @name Channel pair operations - * @{ - */ - -/*! - * @brief This function enables/disables the fault control in a channel pair. - * - * @param base FTM peripheral base address - * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 - * @param value true: Enable fault control for this channel pair; false: No fault control - */ -static inline void FTM_SetFaultControlEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) -{ - if (value) - { - base->COMBINE |= (1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); - } - else - { - base->COMBINE &= ~(1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); - } -} - -/*! - * @brief This function enables/disables the dead time insertion in a channel pair. - * - * @param base FTM peripheral base address - * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 - * @param value true: Insert dead time in this channel pair; false: No dead time inserted - */ -static inline void FTM_SetDeadTimeEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) -{ - if (value) - { - base->COMBINE |= (1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); - } - else - { - base->COMBINE &= ~(1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); - } -} - -/*! - * @brief This function enables/disables complementary mode in a channel pair. - * - * @param base FTM peripheral base address - * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 - * @param value true: enable complementary mode; false: disable complementary mode - */ -static inline void FTM_SetComplementaryEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) -{ - if (value) - { - base->COMBINE |= (1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); - } - else - { - base->COMBINE &= ~(1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); - } -} - -/*! - * @brief This function enables/disables inverting control in a channel pair. - * - * @param base FTM peripheral base address - * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 - * @param value true: enable inverting; false: disable inverting - */ -static inline void FTM_SetInvertEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) -{ - if (value) - { - base->INVCTRL |= (1U << chnlPairNumber); - } - else - { - base->INVCTRL &= ~(1U << chnlPairNumber); - } -} - -/*! @}*/ - -/*! - * @brief Enables or disables the FTM software trigger for PWM synchronization. - * - * @param base FTM peripheral base address - * @param enable true: software trigger is selected, false: software trigger is not selected - */ -static inline void FTM_SetSoftwareTrigger(FTM_Type *base, bool enable) -{ - if (enable) - { - base->SYNC |= FTM_SYNC_SWSYNC_MASK; - } - else - { - base->SYNC &= ~FTM_SYNC_SWSYNC_MASK; - } -} - -/*! - * @brief Enables or disables the FTM write protection. - * - * @param base FTM peripheral base address - * @param enable true: Write-protection is enabled, false: Write-protection is disabled - */ -static inline void FTM_SetWriteProtection(FTM_Type *base, bool enable) -{ - /* Configure write protection */ - if (enable) - { - base->FMS |= FTM_FMS_WPEN_MASK; - } - else - { - base->MODE |= FTM_MODE_WPDIS_MASK; - } -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_FTM_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_gpio.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_gpio.c deleted file mode 100644 index 8fc068f..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_gpio.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_gpio.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ -static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; -static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; - -/******************************************************************************* -* Prototypes -******************************************************************************/ - -/*! -* @brief Gets the GPIO instance according to the GPIO base -* -* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) -* @retval GPIO instance -*/ -static uint32_t GPIO_GetInstance(GPIO_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GPIO_GetInstance(GPIO_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_GPIO_COUNT; instance++) - { - if (s_gpioBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_GPIO_COUNT); - - return instance; -} - -void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) -{ - assert(config); - - if (config->pinDirection == kGPIO_DigitalInput) - { - base->PDDR &= ~(1U << pin); - } - else - { - GPIO_WritePinOutput(base, pin, config->outputLogic); - base->PDDR |= (1U << pin); - } -} - -uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) -{ - uint8_t instance; - PORT_Type *portBase; - instance = GPIO_GetInstance(base); - portBase = s_portBases[instance]; - return portBase->ISFR; -} - -void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) -{ - uint8_t instance; - PORT_Type *portBase; - instance = GPIO_GetInstance(base); - portBase = s_portBases[instance]; - portBase->ISFR = mask; -} - -#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT - -/******************************************************************************* - * Variables - ******************************************************************************/ -static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; - -/******************************************************************************* -* Prototypes -******************************************************************************/ -/*! -* @brief Gets the FGPIO instance according to the GPIO base -* -* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) -* @retval FGPIO instance -*/ -static uint32_t FGPIO_GetInstance(FGPIO_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t FGPIO_GetInstance(FGPIO_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_FGPIO_COUNT; instance++) - { - if (s_fgpioBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_FGPIO_COUNT); - - return instance; -} - -void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) -{ - assert(config); - - if (config->pinDirection == kGPIO_DigitalInput) - { - base->PDDR &= ~(1U << pin); - } - else - { - FGPIO_WritePinOutput(base, pin, config->outputLogic); - base->PDDR |= (1U << pin); - } -} - -uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) -{ - uint8_t instance; - instance = FGPIO_GetInstance(base); - PORT_Type *portBase; - portBase = s_portBases[instance]; - return portBase->ISFR; -} - -void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) -{ - uint8_t instance; - instance = FGPIO_GetInstance(base); - PORT_Type *portBase; - portBase = s_portBases[instance]; - portBase->ISFR = mask; -} - -#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_gpio.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_gpio.h deleted file mode 100644 index d62545f..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_gpio.h +++ /dev/null @@ -1,389 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_GPIO_H_ -#define _FSL_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gpio - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief GPIO driver version 2.1.0. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -/*! @brief GPIO direction definition*/ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/*! - * @brief The GPIO pin configuration structure. - * - * Every pin can only be configured as either output pin or input pin at a time. - * If configured as a input pin, then leave the outputConfig unused - * Note : In some use cases, the corresponding port property should be configured in advance - * with the PORT_SetPinConfig() - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations, please ignore if configured as a input one */ - uint8_t outputLogic; /*!< Set default output logic, no use in input */ -} gpio_pin_config_t; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup gpio_driver - * @{ - */ - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param pin GPIO port pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) -{ - if (output == 0U) - { - base->PCOR = 1 << pin; - } - else - { - base->PSOR = 1 << pin; - } -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) -{ - base->PSOR = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) -{ - base->PCOR = mask; -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) -{ - base->PTOR = mask; -} -/*@}*/ - -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the whole GPIO port. - * - * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) -{ - return (((base->PDIR) >> pin) & 0x01U); -} -/*@}*/ - -/*! @name GPIO Interrupt */ -/*@{*/ - -/*! - * @brief Reads whole GPIO port interrupt status flag. - * - * If a pin is configured to generate the DMA request, the corresponding flag - * is cleared automatically at the completion of the requested DMA transfer. - * Otherwise, the flag remains set until a logic one is written to that flag. - * If configured for a level sensitive interrupt that remains asserted, the flag - * is set again immediately. - * - * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @retval Current GPIO port interrupt status flag, for example, 0x00010001 means the - * pin 0 and 17 have the interrupt. - */ -uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); - -/*! - * @brief Clears multiple GPIO pin interrupt status flag. - * - * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); - -/*@}*/ -/*! @} */ - -/*! - * @addtogroup fgpio_driver - * @{ - */ - -/* - * Introduce the FGPIO feature. - * - * The FGPIO features are only support on some of Kinetis chips. The FGPIO registers are aliased to the IOPORT - * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore - * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. - */ - -#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT - -/*! @name FGPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes a FGPIO pin used by the board. - * - * To initialize the FGPIO driver, define a pin configuration, either input or output, in the user file. - * Then, call the FGPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param pin FGPIO port pin number - * @param config FGPIO pin configuration pointer - */ -void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name FGPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. - * - * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param pin FGPIO pin number - * @param output FGPIOpin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) -{ - if (output == 0U) - { - base->PCOR = 1 << pin; - } - else - { - base->PSOR = 1 << pin; - } -} - -/*! - * @brief Sets the output level of the multiple FGPIO pins to the logic 1. - * - * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) -{ - base->PSOR = mask; -} - -/*! - * @brief Sets the output level of the multiple FGPIO pins to the logic 0. - * - * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) -{ - base->PCOR = mask; -} - -/*! - * @brief Reverses current output logic of the multiple FGPIO pins. - * - * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) -{ - base->PTOR = mask; -} -/*@}*/ - -/*! @name FGPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the whole FGPIO port. - * - * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param pin FGPIO pin number - * @retval FGPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) -{ - return (((base->PDIR) >> pin) & 0x01U); -} -/*@}*/ - -/*! @name FGPIO Interrupt */ -/*@{*/ - -/*! - * @brief Reads the whole FGPIO port interrupt status flag. - * - * If a pin is configured to generate the DMA request, the corresponding flag - * is cleared automatically at the completion of the requested DMA transfer. - * Otherwise, the flag remains set until a logic one is written to that flag. - * If configured for a level sensitive interrupt that remains asserted, the flag - * is set again immediately. - * - * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @retval Current FGPIO port interrupt status flags, for example, 0x00010001 means the - * pin 0 and 17 have the interrupt. - */ -uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); - -/*! - * @brief Clears the multiple FGPIO pin interrupt status flag. - * - * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); - -/*@}*/ - -#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _FSL_GPIO_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c.c deleted file mode 100644 index 6c9770a..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c.c +++ /dev/null @@ -1,1757 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_i2c.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief i2c transfer state. */ -enum _i2c_transfer_states -{ - kIdleState = 0x0U, /*!< I2C bus idle. */ - kCheckAddressState = 0x1U, /*!< 7-bit address check state. */ - kSendCommandState = 0x2U, /*!< Send command byte phase. */ - kSendDataState = 0x3U, /*!< Send data transfer phase. */ - kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */ - kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */ -}; - -/*! @brief Common sets of flags used by the driver. */ -enum _i2c_flag_constants -{ -/*! All flags which are cleared by the driver upon starting a transfer. */ -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag, - kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StartStopDetectInterruptEnable, -#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag, - kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StopDetectInterruptEnable, -#else - kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag, - kIrqFlags = kI2C_GlobalInterruptEnable, -#endif - -}; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for I2C module. - * - * @param base I2C peripheral base address. - */ -uint32_t I2C_GetInstance(I2C_Type *base); - -/*! -* @brief Set SCL/SDA hold time, this API receives SCL stop hold time, calculate the -* closest SCL divider and MULT value for the SDA hold time, SCL start and SCL stop -* hold time. To reduce the ROM size, SDA/SCL hold value mapping table is not provided, -* assume SCL divider = SCL stop hold value *2 to get the closest SCL divider value and MULT -* value, then the related SDA hold time, SCL start and SCL stop hold time is used. -* -* @param base I2C peripheral base address. -* @param sourceClock_Hz I2C functional clock frequency in Hertz. -* @param sclStopHoldTime_ns SCL stop hold time in ns. -*/ -static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz); - -/*! - * @brief Set up master transfer, send slave address and decide the initial - * transfer state. - * - * @param base I2C peripheral base address. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. - * @param xfer pointer to i2c_master_transfer_t structure. - */ -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Check and clear status operation. - * - * @param base I2C peripheral base address. - * @param status current i2c hardware status. - * @retval kStatus_Success No error found. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStatus_I2C_Nak Received Nak error. - */ -static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status); - -/*! - * @brief Master run transfer state machine to perform a byte of transfer. - * - * @param base I2C peripheral base address. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state - * @param isDone input param to get whether the thing is done, true is done - * @retval kStatus_Success No error found. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStatus_I2C_Nak Received Nak error. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - */ -static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); - -/*! - * @brief I2C common interrupt handler. - * - * @param base I2C peripheral base address. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state - */ -static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to i2c handles for each instance. */ -static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL}; - -/*! @brief SCL clock divider used to calculate baudrate. */ -static const uint16_t s_i2cDividerTable[] = { - 20, 22, 24, 26, 28, 30, 34, 40, 28, 32, 36, 40, 44, 48, 56, 68, - 48, 56, 64, 72, 80, 88, 104, 128, 80, 96, 112, 128, 144, 160, 192, 240, - 160, 192, 224, 256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960, - 640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840}; - -/*! @brief Pointers to i2c bases for each instance. */ -static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; - -/*! @brief Pointers to i2c IRQ number for each instance. */ -static const IRQn_Type s_i2cIrqs[] = I2C_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to i2c clocks for each instance. */ -static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointer to master IRQ handler for each instance. */ -static i2c_isr_t s_i2cMasterIsr; - -/*! @brief Pointer to slave IRQ handler for each instance. */ -static i2c_isr_t s_i2cSlaveIsr; - -/******************************************************************************* - * Codes - ******************************************************************************/ - -uint32_t I2C_GetInstance(I2C_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++) - { - if (s_i2cBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_i2cBases)); - - return instance; -} - -static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz) -{ - uint32_t multiplier; - uint32_t computedSclHoldTime; - uint32_t absError; - uint32_t bestError = UINT32_MAX; - uint32_t bestMult = 0u; - uint32_t bestIcr = 0u; - uint8_t mult; - uint8_t i; - - /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, - * and ranges from 0-2. It selects the multiplier factor for the divider. */ - /* SDA hold time = bus period (s) * mul * SDA hold value. */ - /* SCL start hold time = bus period (s) * mul * SCL start hold value. */ - /* SCL stop hold time = bus period (s) * mul * SCL stop hold value. */ - - for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult) - { - multiplier = 1u << mult; - - /* Scan table to find best match. */ - for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i) - { - /* Assume SCL hold(stop) value = s_i2cDividerTable[i]/2. */ - computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000000U) / sourceClock_Hz; - absError = sclStopHoldTime_ns > computedSclHoldTime ? (sclStopHoldTime_ns - computedSclHoldTime) : - (computedSclHoldTime - sclStopHoldTime_ns); - - if (absError < bestError) - { - bestMult = mult; - bestIcr = i; - bestError = absError; - - /* If the error is 0, then we can stop searching because we won't find a better match. */ - if (absError == 0) - { - break; - } - } - } - } - - /* Set frequency register based on best settings. */ - base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); -} - -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result = kStatus_Success; - i2c_direction_t direction = xfer->direction; - - /* Initialize the handle transfer information. */ - handle->transfer = *xfer; - - /* Save total transfer size. */ - handle->transferSize = xfer->dataSize; - - /* Initial transfer state. */ - if (handle->transfer.subaddressSize > 0) - { - if (xfer->direction == kI2C_Read) - { - direction = kI2C_Write; - } - } - - handle->state = kCheckAddressState; - - /* Clear all status before transfer. */ - I2C_MasterClearStatusFlags(base, kClearFlags); - - /* If repeated start is requested, send repeated start. */ - if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) - { - result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); - } - else /* For normal transfer, send start. */ - { - result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); - } - - return result; -} - -static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check arbitration lost. */ - if (status & kI2C_ArbitrationLostFlag) - { - /* Clear arbitration lost flag. */ - base->S = kI2C_ArbitrationLostFlag; - result = kStatus_I2C_ArbitrationLost; - } - /* Check NAK */ - else if (status & kI2C_ReceiveNakFlag) - { - result = kStatus_I2C_Nak; - } - else - { - } - - return result; -} - -static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) -{ - status_t result = kStatus_Success; - uint32_t statusFlags = base->S; - *isDone = false; - volatile uint8_t dummy = 0; - bool ignoreNak = ((handle->state == kSendDataState) && (handle->transfer.dataSize == 0U)) || - ((handle->state == kReceiveDataState) && (handle->transfer.dataSize == 1U)); - - /* Add this to avoid build warning. */ - dummy++; - - /* Check & clear error flags. */ - result = I2C_CheckAndClearError(base, statusFlags); - - /* Ignore Nak when it's appeared for last byte. */ - if ((result == kStatus_I2C_Nak) && ignoreNak) - { - result = kStatus_Success; - } - - /* Handle Check address state to check the slave address is Acked in slave - probe application. */ - if (handle->state == kCheckAddressState) - { - if (statusFlags & kI2C_ReceiveNakFlag) - { - result = kStatus_I2C_Addr_Nak; - } - else - { - if (handle->transfer.subaddressSize > 0) - { - handle->state = kSendCommandState; - } - else - { - if (handle->transfer.direction == kI2C_Write) - { - /* Next state, send data. */ - handle->state = kSendDataState; - } - else - { - /* Next state, receive data begin. */ - handle->state = kReceiveDataBeginState; - } - } - } - } - - if (result) - { - return result; - } - - /* Run state machine. */ - switch (handle->state) - { - /* Send I2C command. */ - case kSendCommandState: - if (handle->transfer.subaddressSize) - { - handle->transfer.subaddressSize--; - base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); - } - else - { - if (handle->transfer.direction == kI2C_Write) - { - /* Next state, send data. */ - handle->state = kSendDataState; - - /* Send first byte of data. */ - if (handle->transfer.dataSize > 0) - { - base->D = *handle->transfer.data; - handle->transfer.data++; - handle->transfer.dataSize--; - } - } - else - { - /* Send repeated start and slave address. */ - result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); - - /* Next state, receive data begin. */ - handle->state = kReceiveDataBeginState; - } - } - break; - - /* Send I2C data. */ - case kSendDataState: - /* Send one byte of data. */ - if (handle->transfer.dataSize > 0) - { - base->D = *handle->transfer.data; - handle->transfer.data++; - handle->transfer.dataSize--; - } - else - { - *isDone = true; - } - break; - - /* Start I2C data receive. */ - case kReceiveDataBeginState: - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Send nak at the last receive byte. */ - if (handle->transfer.dataSize == 1) - { - base->C1 |= I2C_C1_TXAK_MASK; - } - - /* Read dummy to release the bus. */ - dummy = base->D; - - /* Next state, receive data. */ - handle->state = kReceiveDataState; - break; - - /* Receive I2C data. */ - case kReceiveDataState: - /* Receive one byte of data. */ - if (handle->transfer.dataSize--) - { - if (handle->transfer.dataSize == 0) - { - *isDone = true; - - /* Send stop if kI2C_TransferNoStop is not asserted. */ - if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) - { - result = I2C_MasterStop(base); - } - else - { - base->C1 |= I2C_C1_TX_MASK; - } - } - - /* Send NAK at the last receive byte. */ - if (handle->transfer.dataSize == 1) - { - base->C1 |= I2C_C1_TXAK_MASK; - } - - /* Read the data byte into the transfer buffer. */ - *handle->transfer.data = base->D; - handle->transfer.data++; - } - break; - - default: - break; - } - - return result; -} - -static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) -{ - /* Check if master interrupt. */ - if ((base->S & kI2C_ArbitrationLostFlag) || (base->C1 & I2C_C1_MST_MASK)) - { - s_i2cMasterIsr(base, handle); - } - else - { - s_i2cSlaveIsr(base, handle); - } - __DSB(); -} - -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - assert(masterConfig && srcClock_Hz); - - /* Temporary register for filter read. */ - uint8_t fltReg; -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - uint8_t s2Reg; -#endif -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable I2C clock. */ - CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - base->A1 = 0; - base->F = 0; - base->C1 = 0; - base->S = 0xFFU; - base->C2 = 0; -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - base->FLT = 0x50U; -#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - base->FLT = 0x40U; -#endif - base->RA = 0; - - /* Disable I2C prior to configuring it. */ - base->C1 &= ~(I2C_C1_IICEN_MASK); - - /* Clear all flags. */ - I2C_MasterClearStatusFlags(base, kClearFlags); - - /* Configure baud rate. */ - I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); - - /* Read out the FLT register. */ - fltReg = base->FLT; - -#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF - /* Configure the stop / hold enable. */ - fltReg &= ~(I2C_FLT_SHEN_MASK); - fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold); -#endif - - /* Configure the glitch filter value. */ - fltReg &= ~(I2C_FLT_FLT_MASK); - fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth); - - /* Write the register value back to the filter register. */ - base->FLT = fltReg; - -/* Enable/Disable double buffering. */ -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - s2Reg = base->S2 & (~I2C_S2_DFEN_MASK); - base->S2 = s2Reg | I2C_S2_DFEN(masterConfig->enableDoubleBuffering); -#endif - - /* Enable the I2C peripheral based on the configuration. */ - base->C1 = I2C_C1_IICEN(masterConfig->enableMaster); -} - -void I2C_MasterDeinit(I2C_Type *base) -{ - /* Disable I2C module. */ - I2C_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable I2C clock. */ - CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) -{ - assert(masterConfig); - - /* Default baud rate at 100kbps. */ - masterConfig->baudRate_Bps = 100000U; - -/* Default stop hold enable is disabled. */ -#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF - masterConfig->enableStopHold = false; -#endif - - /* Default glitch filter value is no filter. */ - masterConfig->glitchFilterWidth = 0U; - -/* Default enable double buffering. */ -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - masterConfig->enableDoubleBuffering = true; -#endif - - /* Enable the I2C peripheral. */ - masterConfig->enableMaster = true; -} - -void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) -{ -#ifdef I2C_HAS_STOP_DETECT - uint8_t fltReg; -#endif - - if (mask & kI2C_GlobalInterruptEnable) - { - base->C1 |= I2C_C1_IICIE_MASK; - } - -#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - if (mask & kI2C_StopDetectInterruptEnable) - { - fltReg = base->FLT; - - /* Keep STOPF flag. */ - fltReg &= ~I2C_FLT_STOPF_MASK; - - /* Stop detect enable. */ - fltReg |= I2C_FLT_STOPIE_MASK; - base->FLT = fltReg; - } -#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - if (mask & kI2C_StartStopDetectInterruptEnable) - { - fltReg = base->FLT; - - /* Keep STARTF and STOPF flags. */ - fltReg &= ~(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK); - - /* Start and stop detect enable. */ - fltReg |= I2C_FLT_SSIE_MASK; - base->FLT = fltReg; - } -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ -} - -void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) -{ - if (mask & kI2C_GlobalInterruptEnable) - { - base->C1 &= ~I2C_C1_IICIE_MASK; - } - -#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - if (mask & kI2C_StopDetectInterruptEnable) - { - base->FLT &= ~(I2C_FLT_STOPIE_MASK | I2C_FLT_STOPF_MASK); - } -#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - if (mask & kI2C_StartStopDetectInterruptEnable) - { - base->FLT &= ~(I2C_FLT_SSIE_MASK | I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK); - } -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ -} - -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint32_t multiplier; - uint32_t computedRate; - uint32_t absError; - uint32_t bestError = UINT32_MAX; - uint32_t bestMult = 0u; - uint32_t bestIcr = 0u; - uint8_t mult; - uint8_t i; - - /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, - * and ranges from 0-2. It selects the multiplier factor for the divider. */ - for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult) - { - multiplier = 1u << mult; - - /* Scan table to find best match. */ - for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i) - { - computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]); - absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps); - - if (absError < bestError) - { - bestMult = mult; - bestIcr = i; - bestError = absError; - - /* If the error is 0, then we can stop searching because we won't find a better match. */ - if (absError == 0) - { - break; - } - } - } - } - - /* Set frequency register based on best settings. */ - base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); -} - -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result = kStatus_Success; - uint32_t statusFlags = I2C_MasterGetStatusFlags(base); - - /* Return an error if the bus is already in use. */ - if (statusFlags & kI2C_BusBusyFlag) - { - result = kStatus_I2C_Busy; - } - else - { - /* Send the START signal. */ - base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; - -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING - while (!(base->S2 & I2C_S2_EMPTY_MASK)) - { - } -#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ - - base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); - } - - return result; -} - -status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result = kStatus_Success; - uint8_t savedMult; - uint32_t statusFlags = I2C_MasterGetStatusFlags(base); - uint8_t timeDelay = 6; - - /* Return an error if the bus is already in use, but not by us. */ - if ((statusFlags & kI2C_BusBusyFlag) && ((base->C1 & I2C_C1_MST_MASK) == 0)) - { - result = kStatus_I2C_Busy; - } - else - { - savedMult = base->F; - base->F = savedMult & (~I2C_F_MULT_MASK); - - /* We are already in a transfer, so send a repeated start. */ - base->C1 |= I2C_C1_RSTA_MASK | I2C_C1_TX_MASK; - - /* Restore the multiplier factor. */ - base->F = savedMult; - - /* Add some delay to wait the Re-Start signal. */ - while (timeDelay--) - { - __NOP(); - } - -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING - while (!(base->S2 & I2C_S2_EMPTY_MASK)) - { - } -#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ - - base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); - } - - return result; -} - -status_t I2C_MasterStop(I2C_Type *base) -{ - status_t result = kStatus_Success; - uint16_t timeout = UINT16_MAX; - - /* Issue the STOP command on the bus. */ - base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Wait until data transfer complete. */ - while ((base->S & kI2C_BusBusyFlag) && (--timeout)) - { - } - - if (timeout == 0) - { - result = kStatus_I2C_Timeout; - } - - return result; -} - -uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) -{ - uint32_t statusFlags = base->S; - -#ifdef I2C_HAS_STOP_DETECT - /* Look up the STOPF bit from the filter register. */ - if (base->FLT & I2C_FLT_STOPF_MASK) - { - statusFlags |= kI2C_StopDetectFlag; - } -#endif - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - /* Look up the STARTF bit from the filter register. */ - if (base->FLT & I2C_FLT_STARTF_MASK) - { - statusFlags |= kI2C_StartDetectFlag; - } -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ - - return statusFlags; -} - -status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags) -{ - status_t result = kStatus_Success; - uint8_t statusFlags = 0; - - /* Wait until the data register is ready for transmit. */ - while (!(base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Setup the I2C peripheral to transmit data. */ - base->C1 |= I2C_C1_TX_MASK; - - while (txSize--) - { - /* Send a byte of data. */ - base->D = *txBuff++; - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - statusFlags = base->S; - - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */ - if (statusFlags & kI2C_ArbitrationLostFlag) - { - base->S = kI2C_ArbitrationLostFlag; - result = kStatus_I2C_ArbitrationLost; - } - - if ((statusFlags & kI2C_ReceiveNakFlag) && txSize) - { - base->S = kI2C_ReceiveNakFlag; - result = kStatus_I2C_Nak; - } - - if (result != kStatus_Success) - { - /* Breaking out of the send loop. */ - break; - } - } - - if (((result == kStatus_Success) && (!(flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak)) - { - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Send stop. */ - result = I2C_MasterStop(base); - } - - return result; -} - -status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags) -{ - status_t result = kStatus_Success; - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - - /* Wait until the data register is ready for transmit. */ - while (!(base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Setup the I2C peripheral to receive data. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* If rxSize equals 1, configure to send NAK. */ - if (rxSize == 1) - { - /* Issue NACK on read. */ - base->C1 |= I2C_C1_TXAK_MASK; - } - - /* Do dummy read. */ - dummy = base->D; - - while ((rxSize--)) - { - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Single byte use case. */ - if (rxSize == 0) - { - if (!(flags & kI2C_TransferNoStopFlag)) - { - /* Issue STOP command before reading last byte. */ - result = I2C_MasterStop(base); - } - else - { - /* Change direction to Tx to avoid extra clocks. */ - base->C1 |= I2C_C1_TX_MASK; - } - } - - if (rxSize == 1) - { - /* Issue NACK on read. */ - base->C1 |= I2C_C1_TXAK_MASK; - } - - /* Read from the data register. */ - *rxBuff++ = base->D; - } - - return result; -} - -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) -{ - assert(xfer); - - i2c_direction_t direction = xfer->direction; - status_t result = kStatus_Success; - - /* Clear all status before transfer. */ - I2C_MasterClearStatusFlags(base, kClearFlags); - - /* Wait until ready to complete. */ - while (!(base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Change to send write address when it's a read operation with command. */ - if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) - { - direction = kI2C_Write; - } - - /* If repeated start is requested, send repeated start. */ - if (xfer->flags & kI2C_TransferRepeatedStartFlag) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); - } - else /* For normal transfer, send start. */ - { - result = I2C_MasterStart(base, xfer->slaveAddress, direction); - } - - /* Return if error. */ - if (result) - { - return result; - } - - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - /* Return if error. */ - if (result) - { - if (result == kStatus_I2C_Nak) - { - result = kStatus_I2C_Addr_Nak; - - I2C_MasterStop(base); - } - - return result; - } - - /* Send subaddress. */ - if (xfer->subaddressSize) - { - do - { - /* Clear interrupt pending flag. */ - base->S = kI2C_IntPendingFlag; - - xfer->subaddressSize--; - base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize)); - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - if (result) - { - if (result == kStatus_I2C_Nak) - { - I2C_MasterStop(base); - } - - return result; - } - - } while ((xfer->subaddressSize > 0) && (result == kStatus_Success)); - - if (xfer->direction == kI2C_Read) - { - /* Clear pending flag. */ - base->S = kI2C_IntPendingFlag; - - /* Send repeated start and slave address. */ - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read); - - /* Return if error. */ - if (result) - { - return result; - } - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - if (result) - { - if (result == kStatus_I2C_Nak) - { - result = kStatus_I2C_Addr_Nak; - - I2C_MasterStop(base); - } - - return result; - } - } - } - - /* Transmit data. */ - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) - { - /* Send Data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - - /* Receive Data. */ - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) - { - result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - - return result; -} - -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - uint32_t instance = I2C_GetInstance(base); - - /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Save the context in global variables to support the double weak mechanism. */ - s_i2cHandle[instance] = handle; - - /* Save master interrupt handler. */ - s_i2cMasterIsr = I2C_MasterTransferHandleIRQ; - - /* Enable NVIC interrupt. */ - EnableIRQ(s_i2cIrqs[instance]); -} - -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - status_t result = kStatus_Success; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (handle->state != kIdleState) - { - result = kStatus_I2C_Busy; - } - else - { - /* Start up the master transfer state machine. */ - result = I2C_InitTransferStateMachine(base, handle, xfer); - - if (result == kStatus_Success) - { - /* Enable the I2C interrupts. */ - I2C_EnableInterrupts(base, kI2C_GlobalInterruptEnable); - } - } - - return result; -} - -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) -{ - assert(handle); - - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - - /* Disable interrupt. */ - I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); - - /* Reset the state to idle. */ - handle->state = kIdleState; - - /* Send STOP signal. */ - if (handle->transfer.direction == kI2C_Read) - { - base->C1 |= I2C_C1_TXAK_MASK; - while (!(base->S & kI2C_IntPendingFlag)) - { - } - base->S = kI2C_IntPendingFlag; - - base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - dummy = base->D; - } - else - { - while (!(base->S & kI2C_IntPendingFlag)) - { - } - base->S = kI2C_IntPendingFlag; - base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - } -} - -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - *count = handle->transferSize - handle->transfer.dataSize; - - return kStatus_Success; -} - -void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) -{ - assert(i2cHandle); - - i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle; - status_t result = kStatus_Success; - bool isDone; - - /* Clear the interrupt flag. */ - base->S = kI2C_IntPendingFlag; - - /* Check transfer complete flag. */ - result = I2C_MasterTransferRunStateMachine(base, handle, &isDone); - - if (isDone || result) - { - /* Send stop command if transfer done or received Nak. */ - if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) || - (result == kStatus_I2C_Addr_Nak)) - { - /* Ensure stop command is a need. */ - if ((base->C1 & I2C_C1_MST_MASK)) - { - if (I2C_MasterStop(base) != kStatus_Success) - { - result = kStatus_I2C_Timeout; - } - } - } - - /* Restore handle to idle state. */ - handle->state = kIdleState; - - /* Disable interrupt. */ - I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); - - /* Call the callback function after the function has completed. */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) -{ - assert(slaveConfig); - - uint8_t tmpReg; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - base->A1 = 0; - base->F = 0; - base->C1 = 0; - base->S = 0xFFU; - base->C2 = 0; -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - base->FLT = 0x50U; -#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - base->FLT = 0x40U; -#endif - base->RA = 0; - - /* Configure addressing mode. */ - switch (slaveConfig->addressingMode) - { - case kI2C_Address7bit: - base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; - break; - - case kI2C_RangeMatch: - assert(slaveConfig->slaveAddress < slaveConfig->upperAddress); - base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; - base->RA = ((uint32_t)(slaveConfig->upperAddress)) << 1U; - base->C2 |= I2C_C2_RMEN_MASK; - break; - - default: - break; - } - - /* Configure low power wake up feature. */ - tmpReg = base->C1; - tmpReg &= ~I2C_C1_WUEN_MASK; - base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave); - - /* Configure general call & baud rate control. */ - tmpReg = base->C2; - tmpReg &= ~(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK); - tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall); - base->C2 = tmpReg; - -/* Enable/Disable double buffering. */ -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - tmpReg = base->S2 & (~I2C_S2_DFEN_MASK); - base->S2 = tmpReg | I2C_S2_DFEN(slaveConfig->enableDoubleBuffering); -#endif - - /* Set hold time. */ - I2C_SetHoldTime(base, slaveConfig->sclStopHoldTime_ns, srcClock_Hz); -} - -void I2C_SlaveDeinit(I2C_Type *base) -{ - /* Disable I2C module. */ - I2C_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable I2C clock. */ - CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - /* By default slave is addressed with 7-bit address. */ - slaveConfig->addressingMode = kI2C_Address7bit; - - /* General call mode is disabled by default. */ - slaveConfig->enableGeneralCall = false; - - /* Slave address match waking up MCU from low power mode is disabled. */ - slaveConfig->enableWakeUp = false; - - /* Independent slave mode baud rate at maximum frequency is disabled. */ - slaveConfig->enableBaudRateCtl = false; - -/* Default enable double buffering. */ -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - slaveConfig->enableDoubleBuffering = true; -#endif - - /* Set default SCL stop hold time to 4us which is minimum requirement in I2C spec. */ - slaveConfig->sclStopHoldTime_ns = 4000; - - /* Enable the I2C peripheral. */ - slaveConfig->enableSlave = true; -} - -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) -{ - status_t result = kStatus_Success; - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - /* Check start flag. */ - while (!(base->FLT & I2C_FLT_STARTF_MASK)) - { - } - /* Clear STARTF flag. */ - base->FLT |= I2C_FLT_STARTF_MASK; - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ - - /* Wait for address match flag. */ - while (!(base->S & kI2C_AddressMatchFlag)) - { - } - - /* Read dummy to release bus. */ - dummy = base->D; - - result = I2C_MasterWriteBlocking(base, txBuff, txSize, kI2C_TransferDefaultFlag); - - /* Switch to receive mode. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Read dummy to release bus. */ - dummy = base->D; - - return result; -} - -void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) -{ - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - -/* Wait until address match. */ -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - /* Check start flag. */ - while (!(base->FLT & I2C_FLT_STARTF_MASK)) - { - } - /* Clear STARTF flag. */ - base->FLT |= I2C_FLT_STARTF_MASK; - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ - - /* Wait for address match and int pending flag. */ - while (!(base->S & kI2C_AddressMatchFlag)) - { - } - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Read dummy to release bus. */ - dummy = base->D; - - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Setup the I2C peripheral to receive data. */ - base->C1 &= ~(I2C_C1_TX_MASK); - - while (rxSize--) - { - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Read from the data register. */ - *rxBuff++ = base->D; - } -} - -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - uint32_t instance = I2C_GetInstance(base); - - /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set callback and userData. */ - handle->callback = callback; - handle->userData = userData; - - /* Save the context in global variables to support the double weak mechanism. */ - s_i2cHandle[instance] = handle; - - /* Save slave interrupt handler. */ - s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ; - - /* Enable NVIC interrupt. */ - EnableIRQ(s_i2cIrqs[instance]); -} - -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) -{ - assert(handle); - - /* Check if the I2C bus is idle - if not return busy status. */ - if (handle->isBusy) - { - return kStatus_I2C_Busy; - } - else - { - /* Disable LPI2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kIrqFlags); - - /* Clear transfer in handle. */ - memset(&handle->transfer, 0, sizeof(handle->transfer)); - - /* Record that we're busy. */ - handle->isBusy = true; - - /* Set up event mask. tx and rx are always enabled. */ - handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | kI2C_SlaveGenaralcallEvent; - - /* Clear all flags. */ - I2C_SlaveClearStatusFlags(base, kClearFlags); - - /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ - I2C_EnableInterrupts(base, kIrqFlags); - } - - return kStatus_Success; -} - -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) -{ - assert(handle); - - if (handle->isBusy) - { - /* Disable interrupts. */ - I2C_DisableInterrupts(base, kIrqFlags); - - /* Reset transfer info. */ - memset(&handle->transfer, 0, sizeof(handle->transfer)); - - /* Reset the state to idle. */ - handle->isBusy = false; - } -} - -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transfer.transferredCount; - - return kStatus_Success; -} - -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) -{ - assert(i2cHandle); - - uint16_t status; - bool doTransmit = false; - i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle; - i2c_slave_transfer_t *xfer; - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - - status = I2C_SlaveGetStatusFlags(base); - xfer = &(handle->transfer); - -#ifdef I2C_HAS_STOP_DETECT - /* Check stop flag. */ - if (status & kI2C_StopDetectFlag) - { - I2C_MasterClearStatusFlags(base, kI2C_StopDetectFlag); - - /* Clear the interrupt flag. */ - base->S = kI2C_IntPendingFlag; - - /* Call slave callback if this is the STOP of the transfer. */ - if (handle->isBusy) - { - xfer->event = kI2C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_Success; - handle->isBusy = false; - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - - if (!(status & kI2C_AddressMatchFlag)) - { - return; - } - } -#endif /* I2C_HAS_STOP_DETECT */ - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - /* Check start flag. */ - if (status & kI2C_StartDetectFlag) - { - I2C_MasterClearStatusFlags(base, kI2C_StartDetectFlag); - - /* Clear the interrupt flag. */ - base->S = kI2C_IntPendingFlag; - - xfer->event = kI2C_SlaveStartEvent; - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - - if (!(status & kI2C_AddressMatchFlag)) - { - return; - } - } -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ - - /* Clear the interrupt flag. */ - base->S = kI2C_IntPendingFlag; - - /* Check NAK */ - if (status & kI2C_ReceiveNakFlag) - { - /* Set receive mode. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Read dummy. */ - dummy = base->D; - - if (handle->transfer.dataSize != 0) - { - xfer->event = kI2C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_I2C_Nak; - handle->isBusy = false; - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - else - { -#ifndef I2C_HAS_STOP_DETECT - xfer->event = kI2C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_Success; - handle->isBusy = false; - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } -#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ - } - } - /* Check address match. */ - else if (status & kI2C_AddressMatchFlag) - { - handle->isBusy = true; - xfer->event = kI2C_SlaveAddressMatchEvent; - - /* Slave transmit, master reading from slave. */ - if (status & kI2C_TransferDirectionFlag) - { - /* Change direction to send data. */ - base->C1 |= I2C_C1_TX_MASK; - - doTransmit = true; - } - else - { - /* Slave receive, master writing to slave. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Read dummy to release the bus. */ - dummy = base->D; - - if (dummy == 0) - { - xfer->event = kI2C_SlaveGenaralcallEvent; - } - } - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - /* Check transfer complete flag. */ - else if (status & kI2C_TransferCompleteFlag) - { - /* Slave transmit, master reading from slave. */ - if (status & kI2C_TransferDirectionFlag) - { - doTransmit = true; - } - else - { - /* If we're out of data, invoke callback to get more. */ - if ((!xfer->data) || (!xfer->dataSize)) - { - xfer->event = kI2C_SlaveReceiveEvent; - - if (handle->callback) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clear the transferred count now that we have a new buffer. */ - xfer->transferredCount = 0; - } - - /* Slave receive, master writing to slave. */ - uint8_t data = base->D; - - if (handle->transfer.dataSize) - { - /* Receive data. */ - *handle->transfer.data++ = data; - handle->transfer.dataSize--; - xfer->transferredCount++; - if (!handle->transfer.dataSize) - { -#ifndef I2C_HAS_STOP_DETECT - xfer->event = kI2C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_Success; - handle->isBusy = false; - - /* Proceed receive complete event. */ - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } -#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ - } - } - } - } - else - { - /* Read dummy to release bus. */ - dummy = base->D; - } - - /* Send data if there is the need. */ - if (doTransmit) - { - /* If we're out of data, invoke callback to get more. */ - if ((!xfer->data) || (!xfer->dataSize)) - { - xfer->event = kI2C_SlaveTransmitEvent; - - if (handle->callback) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clear the transferred count now that we have a new buffer. */ - xfer->transferredCount = 0; - } - - if (handle->transfer.dataSize) - { - /* Send data. */ - base->D = *handle->transfer.data++; - handle->transfer.dataSize--; - xfer->transferredCount++; - } - else - { - /* Switch to receive mode. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Read dummy to release bus. */ - dummy = base->D; - -#ifndef I2C_HAS_STOP_DETECT - xfer->event = kI2C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_Success; - handle->isBusy = false; - - /* Proceed txdone event. */ - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } -#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ - } - } -} - -#if defined(I2C0) -void I2C0_DriverIRQHandler(void) -{ - I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]); -} -#endif - -#if defined(I2C1) -void I2C1_DriverIRQHandler(void) -{ - I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]); -} -#endif - -#if defined(I2C2) -void I2C2_DriverIRQHandler(void) -{ - I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]); -} -#endif - -#if defined(I2C3) -void I2C3_DriverIRQHandler(void) -{ - I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]); -} -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c.h deleted file mode 100644 index d55fd1d..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c.h +++ /dev/null @@ -1,794 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2C_H_ -#define _FSL_I2C_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C driver version 2.0.3. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -#if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \ - defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT) -#define I2C_HAS_STOP_DETECT -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ - -/*! @brief I2C status return codes. */ -enum _i2c_status -{ - kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */ - kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ - kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ - kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ - kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Wait event timeout. */ - kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5), /*!< NAK received during the address probe. */ -}; - -/*! - * @brief I2C peripheral flags - * - * The following status register flags can be cleared: - * - #kI2C_ArbitrationLostFlag - * - #kI2C_IntPendingFlag - * - #kI2C_StartDetectFlag - * - #kI2C_StopDetectFlag - * - * @note These enumerations are meant to be OR'd together to form a bit mask. - * - */ -enum _i2c_flags -{ - kI2C_ReceiveNakFlag = I2C_S_RXAK_MASK, /*!< I2C receive NAK flag. */ - kI2C_IntPendingFlag = I2C_S_IICIF_MASK, /*!< I2C interrupt pending flag. */ - kI2C_TransferDirectionFlag = I2C_S_SRW_MASK, /*!< I2C transfer direction flag. */ - kI2C_RangeAddressMatchFlag = I2C_S_RAM_MASK, /*!< I2C range address match flag. */ - kI2C_ArbitrationLostFlag = I2C_S_ARBL_MASK, /*!< I2C arbitration lost flag. */ - kI2C_BusBusyFlag = I2C_S_BUSY_MASK, /*!< I2C bus busy flag. */ - kI2C_AddressMatchFlag = I2C_S_IAAS_MASK, /*!< I2C address match flag. */ - kI2C_TransferCompleteFlag = I2C_S_TCF_MASK, /*!< I2C transfer complete flag. */ -#ifdef I2C_HAS_STOP_DETECT - kI2C_StopDetectFlag = I2C_FLT_STOPF_MASK << 8, /*!< I2C stop detect flag. */ -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - kI2C_StartDetectFlag = I2C_FLT_STARTF_MASK << 8, /*!< I2C start detect flag. */ -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ -}; - -/*! @brief I2C feature interrupt source. */ -enum _i2c_interrupt_enable -{ - kI2C_GlobalInterruptEnable = I2C_C1_IICIE_MASK, /*!< I2C global interrupt. */ - -#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - kI2C_StopDetectInterruptEnable = I2C_FLT_STOPIE_MASK, /*!< I2C stop detect interrupt. */ -#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - kI2C_StartStopDetectInterruptEnable = I2C_FLT_SSIE_MASK, /*!< I2C start&stop detect interrupt. */ -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ -}; - -/*! @brief The direction of master and slave transfers. */ -typedef enum _i2c_direction -{ - kI2C_Write = 0x0U, /*!< Master transmits to the slave. */ - kI2C_Read = 0x1U, /*!< Master receives from the slave. */ -} i2c_direction_t; - -/*! @brief Addressing mode. */ -typedef enum _i2c_slave_address_mode -{ - kI2C_Address7bit = 0x0U, /*!< 7-bit addressing mode. */ - kI2C_RangeMatch = 0X2U, /*!< Range address match addressing mode. */ -} i2c_slave_address_mode_t; - -/*! @brief I2C transfer control flag. */ -enum _i2c_master_transfer_flags -{ - kI2C_TransferDefaultFlag = 0x0U, /*!< A transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x1U, /*!< A transfer starts without a start signal. */ - kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */ - kI2C_TransferNoStopFlag = 0x4U, /*!< A transfer ends without a stop signal. */ -}; - -/*! - * @brief Set of events sent to the callback for nonblocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _i2c_slave_transfer_event -{ - kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kI2C_SlaveTransmitEvent = 0x02U, /*!< A callback is requested to provide data to transmit - (slave-transmitter role). */ - kI2C_SlaveReceiveEvent = 0x04U, /*!< A callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kI2C_SlaveTransmitAckEvent = 0x08U, /*!< A callback needs to either transmit an ACK or NACK. */ -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - kI2C_SlaveStartEvent = 0x10U, /*!< A start/repeated start was detected. */ -#endif - kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */ - kI2C_SlaveGenaralcallEvent = 0x40U, /*!< Received the general call address after a start or repeated start. */ - - /*! A bit mask of all available events. */ - kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - kI2C_SlaveStartEvent | -#endif - kI2C_SlaveCompletionEvent | kI2C_SlaveGenaralcallEvent, -} i2c_slave_transfer_event_t; - -/*! @brief I2C master user configuration. */ -typedef struct _i2c_master_config -{ - bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */ -#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF - bool enableStopHold; /*!< Controls the stop hold enable. */ -#endif -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - bool enableDoubleBuffering; /*!< Controls double buffer enable; notice that - enabling the double buffer disables the clock stretch. */ -#endif - uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */ - uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */ -} i2c_master_config_t; - -/*! @brief I2C slave user configuration. */ -typedef struct _i2c_slave_config -{ - bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */ - bool enableGeneralCall; /*!< Enables the general call addressing mode. */ - bool enableWakeUp; /*!< Enables/disables waking up MCU from low-power mode. */ -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - bool enableDoubleBuffering; /*!< Controls a double buffer enable; notice that - enabling the double buffer disables the clock stretch. */ -#endif - bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */ - uint16_t slaveAddress; /*!< A slave address configuration. */ - uint16_t upperAddress; /*!< A maximum boundary slave address used in a range matching mode. */ - i2c_slave_address_mode_t - addressingMode; /*!< An addressing mode configuration of i2c_slave_address_mode_config_t. */ - uint32_t sclStopHoldTime_ns; /*!< the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C - data) while SCL is high (stop condition), SDA hold time and SCL start hold time - are also configured according to the SCL stop hold time. */ -} i2c_slave_config_t; - -/*! @brief I2C master handle typedef. */ -typedef struct _i2c_master_handle i2c_master_handle_t; - -/*! @brief I2C master transfer callback typedef. */ -typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, - i2c_master_handle_t *handle, - status_t status, - void *userData); - -/*! @brief I2C slave handle typedef. */ -typedef struct _i2c_slave_handle i2c_slave_handle_t; - -/*! @brief I2C master transfer structure. */ -typedef struct _i2c_master_transfer -{ - uint32_t flags; /*!< A transfer flag which controls the transfer. */ - uint8_t slaveAddress; /*!< 7-bit slave address. */ - i2c_direction_t direction; /*!< A transfer direction, read or write. */ - uint32_t subaddress; /*!< A sub address. Transferred MSB first. */ - uint8_t subaddressSize; /*!< A size of the command buffer. */ - uint8_t *volatile data; /*!< A transfer buffer. */ - volatile size_t dataSize; /*!< A transfer size. */ -} i2c_master_transfer_t; - -/*! @brief I2C master handle structure. */ -struct _i2c_master_handle -{ - i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */ - size_t transferSize; /*!< Total bytes to be transferred. */ - uint8_t state; /*!< A transfer state maintained during transfer. */ - i2c_master_transfer_callback_t completionCallback; /*!< A callback function called when the transfer is finished. */ - void *userData; /*!< A callback parameter passed to the callback function. */ -}; - -/*! @brief I2C slave transfer structure. */ -typedef struct _i2c_slave_transfer -{ - i2c_slave_transfer_event_t event; /*!< A reason that the callback is invoked. */ - uint8_t *volatile data; /*!< A transfer buffer. */ - volatile size_t dataSize; /*!< A transfer size. */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kI2C_SlaveCompletionEvent. */ - size_t transferredCount; /*!< A number of bytes actually transferred since the start or since the last repeated - start. */ -} i2c_slave_transfer_t; - -/*! @brief I2C slave transfer callback typedef. */ -typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData); - -/*! @brief I2C slave handle structure. */ -struct _i2c_slave_handle -{ - volatile bool isBusy; /*!< Indicates whether a transfer is busy. */ - i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */ - uint32_t eventMask; /*!< A mask of enabled events. */ - i2c_slave_transfer_callback_t callback; /*!< A callback function called at the transfer event. */ - void *userData; /*!< A callback parameter passed to the callback. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock - * and configure the I2C with master configuration. - * - * @note This API should be called at the beginning of the application. - * Otherwise, any operation to the I2C module can cause a hard fault - * because the clock is not enabled. The configuration structure can be custom filled - * or it can be set with default values by using the I2C_MasterGetDefaultConfig(). - * After calling this API, the master is ready to transfer. - * This is an example. - * @code - * i2c_master_config_t config = { - * .enableMaster = true, - * .enableStopHold = false, - * .highDrive = false, - * .baudRate_Bps = 100000, - * .glitchFilterWidth = 0 - * }; - * I2C_MasterInit(I2C0, &config, 12000000U); - * @endcode - * - * @param base I2C base pointer - * @param masterConfig A pointer to the master configuration structure - * @param srcClock_Hz I2C peripheral clock frequency in Hz - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock - * and initialize the I2C with the slave configuration. - * - * @note This API should be called at the beginning of the application. - * Otherwise, any operation to the I2C module can cause a hard fault - * because the clock is not enabled. The configuration structure can partly be set - * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. - * This is an example. - * @code - * i2c_slave_config_t config = { - * .enableSlave = true, - * .enableGeneralCall = false, - * .addressingMode = kI2C_Address7bit, - * .slaveAddress = 0x1DU, - * .enableWakeUp = false, - * .enablehighDrive = false, - * .enableBaudRateCtl = false, - * .sclStopHoldTime_ns = 4000 - * }; - * I2C_SlaveInit(I2C0, &config, 12000000U); - * @endcode - * - * @param base I2C base pointer - * @param slaveConfig A pointer to the slave configuration structure - * @param srcClock_Hz I2C peripheral clock frequency in Hz - */ -void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); - -/*! - * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. - * The I2C master module can't work unless the I2C_MasterInit is called. - * @param base I2C base pointer - */ -void I2C_MasterDeinit(I2C_Type *base); - -/*! - * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. - * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. - * @param base I2C base pointer - */ -void I2C_SlaveDeinit(I2C_Type *base); - -/*! - * @brief Sets the I2C master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure(). - * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify - * the structure before calling the I2C_MasterConfigure(). - * This is an example. - * @code - * i2c_master_config_t config; - * I2C_MasterGetDefaultConfig(&config); - * @endcode - * @param masterConfig A pointer to the master configuration structure. -*/ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); - -/*! - * @brief Sets the I2C slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure(). - * Modify fields of the structure before calling the I2C_SlaveConfigure(). - * This is an example. - * @code - * i2c_slave_config_t config; - * I2C_SlaveGetDefaultConfig(&config); - * @endcode - * @param slaveConfig A pointer to the slave configuration structure. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); - -/*! - * @brief Enables or disabless the I2C peripheral operation. - * - * @param base I2C base pointer - * @param enable Pass true to enable and false to disable the module. - */ -static inline void I2C_Enable(I2C_Type *base, bool enable) -{ - if (enable) - { - base->C1 |= I2C_C1_IICEN_MASK; - } - else - { - base->C1 &= ~I2C_C1_IICEN_MASK; - } -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the I2C status flags. - * - * @param base I2C base pointer - * @return status flag, use status flag to AND #_i2c_flags to get the related status. - */ -uint32_t I2C_MasterGetStatusFlags(I2C_Type *base); - -/*! - * @brief Gets the I2C status flags. - * - * @param base I2C base pointer - * @return status flag, use status flag to AND #_i2c_flags to get the related status. - */ -static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base) -{ - return I2C_MasterGetStatusFlags(base); -} - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag. - * - * @param base I2C base pointer - * @param statusMask The status flag mask, defined in type i2c_status_flag_t. - * The parameter can be any combination of the following values: - * @arg kI2C_StartDetectFlag (if available) - * @arg kI2C_StopDetectFlag (if available) - * @arg kI2C_ArbitrationLostFlag - * @arg kI2C_IntPendingFlagFlag - */ -static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ -/* Must clear the STARTF / STOPF bits prior to clearing IICIF */ -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - if (statusMask & kI2C_StartDetectFlag) - { - /* Shift the odd-ball flags back into place. */ - base->FLT |= (uint8_t)(statusMask >> 8U); - } -#endif - -#ifdef I2C_HAS_STOP_DETECT - if (statusMask & kI2C_StopDetectFlag) - { - /* Shift the odd-ball flags back into place. */ - base->FLT |= (uint8_t)(statusMask >> 8U); - } -#endif - - base->S = (uint8_t)statusMask; -} - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag - * - * @param base I2C base pointer - * @param statusMask The status flag mask, defined in type i2c_status_flag_t. - * The parameter can be any combination of the following values: - * @arg kI2C_StartDetectFlag (if available) - * @arg kI2C_StopDetectFlag (if available) - * @arg kI2C_ArbitrationLostFlag - * @arg kI2C_IntPendingFlagFlag - */ -static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - I2C_MasterClearStatusFlags(base, statusMask); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables I2C interrupt requests. - * - * @param base I2C base pointer - * @param mask interrupt source - * The parameter can be combination of the following source if defined: - * @arg kI2C_GlobalInterruptEnable - * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable - * @arg kI2C_SdaTimeoutInterruptEnable - */ -void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask); - -/*! - * @brief Disables I2C interrupt requests. - * - * @param base I2C base pointer - * @param mask interrupt source - * The parameter can be combination of the following source if defined: - * @arg kI2C_GlobalInterruptEnable - * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable - * @arg kI2C_SdaTimeoutInterruptEnable - */ -void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask); - -/*! - * @name DMA Control - * @{ - */ -#if defined(FSL_FEATURE_I2C_HAS_DMA_SUPPORT) && FSL_FEATURE_I2C_HAS_DMA_SUPPORT -/*! - * @brief Enables/disables the I2C DMA interrupt. - * - * @param base I2C base pointer - * @param enable true to enable, false to disable -*/ -static inline void I2C_EnableDMA(I2C_Type *base, bool enable) -{ - if (enable) - { - base->C1 |= I2C_C1_DMAEN_MASK; - } - else - { - base->C1 &= ~I2C_C1_DMAEN_MASK; - } -} - -#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */ - -/*! - * @brief Gets the I2C tx/rx data register address. This API is used to provide a transfer address - * for I2C DMA transfer configuration. - * - * @param base I2C base pointer - * @return data register address - */ -static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base) -{ - return (uint32_t)(&(base->D)); -} - -/* @} */ -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Sets the I2C master transfer baud rate. - * - * @param base I2C base pointer - * @param baudRate_Bps the baud rate value in bps - * @param srcClock_Hz Source clock - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * @retval kStatus_Success Successfully send the stop signal. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base); - -/*! - * @brief Sends a REPEATED START on the I2C bus. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. - */ -status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Performs a polling send transaction on the I2C bus. - * - * @param base The I2C peripheral base pointer. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag -* to issue a stop and kI2C_TransferNoStop to not send a stop. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transaction on the I2C bus. - * - * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte. - * Without stopping the bus prior for the final read, the bus issues another read, resulting - * in garbage data being read into the data register. - * - * @param base I2C peripheral base pointer. - * @param rxBuff The pointer to the data to store the received data. - * @param rxSize The length in bytes of the data to be received. - * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag -* to issue a stop and kI2C_TransferNoStop to not send a stop. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Performs a polling send transaction on the I2C bus. - * - * @param base The I2C peripheral base pointer. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transaction on the I2C bus. - * - * @param base I2C peripheral base pointer. - * @param rxBuff The pointer to the data to store the received data. - * @param rxSize The length in bytes of the data to be received. - */ -void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * @param base I2C peripheral base address. - * @param xfer Pointer to the transfer structure. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the I2C handle which is used in transactional functions. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_master_handle_t structure to store the transfer state. - * @param callback pointer to user callback function. - * @param userData user parameter passed to the callback function. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a master interrupt non-blocking transfer on the I2C bus. - * - * @note Calling the API returns immediately after transfer initiates. The user needs - * to call I2C_MasterGetTransferCount to poll the transfer status to check whether - * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer - * is finished. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. - * @param xfer pointer to i2c_master_transfer_t structure. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Gets the master transfer status during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Aborts an interrupt non-blocking transfer early. - * - * @note This API can be called at any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state - */ -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); - -/*! - * @brief Master interrupt handler. - * - * @param base I2C base pointer. - * @param i2cHandle pointer to i2c_master_handle_t structure. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle); - -/*! - * @brief Initializes the I2C handle which is used in transactional functions. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure to store the transfer state. - * @param callback pointer to user callback function. - * @param userData user parameter passed to the callback function. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Aborts the slave transfer. - * - * @note This API can be called at any time to stop slave for handling the bus events. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); - -/*! - * @brief Slave interrupt handler. - * - * @param base I2C base pointer. - * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ - -#endif /* _FSL_I2C_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c_edma.c deleted file mode 100644 index 28a415e..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c_edma.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2c_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*base, false); - - /* Send stop if kI2C_TransferNoStop flag is not asserted. */ - if (!(i2cPrivateHandle->handle->transfer.flags & kI2C_TransferNoStopFlag)) - { - if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read) - { - /* Change to send NAK at the last byte. */ - i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK; - - /* Wait the last data to be received. */ - while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Send stop signal. */ - result = I2C_MasterStop(i2cPrivateHandle->base); - - /* Read the last data byte. */ - *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) = - i2cPrivateHandle->base->D; - } - else - { - /* Wait the last data to be sent. */ - while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Send stop signal. */ - result = I2C_MasterStop(i2cPrivateHandle->base); - } - } - else - { - if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read) - { - /* Change to send NAK at the last byte. */ - i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK; - - /* Wait the last data to be received. */ - while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Change direction to send. */ - i2cPrivateHandle->base->C1 |= I2C_C1_TX_MASK; - - /* Read the last data byte. */ - *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) = - i2cPrivateHandle->base->D; - } - } - - i2cPrivateHandle->handle->state = kIdleState; - - if (i2cPrivateHandle->handle->completionCallback) - { - i2cPrivateHandle->handle->completionCallback(i2cPrivateHandle->base, i2cPrivateHandle->handle, result, - i2cPrivateHandle->handle->userData); - } -} - -static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check arbitration lost. */ - if (status & kI2C_ArbitrationLostFlag) - { - /* Clear arbitration lost flag. */ - base->S = kI2C_ArbitrationLostFlag; - result = kStatus_I2C_ArbitrationLost; - } - /* Check NAK */ - else if (status & kI2C_ReceiveNakFlag) - { - result = kStatus_I2C_Nak; - } - else - { - } - - return result; -} - -static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base, - i2c_master_edma_handle_t *handle, - i2c_master_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - status_t result = kStatus_Success; - - if (handle->state != kIdleState) - { - return kStatus_I2C_Busy; - } - else - { - i2c_direction_t direction = xfer->direction; - - /* Init the handle member. */ - handle->transfer = *xfer; - - /* Save total transfer size. */ - handle->transferSize = xfer->dataSize; - - handle->state = kTransferDataState; - - /* Clear all status before transfer. */ - I2C_MasterClearStatusFlags(base, kClearFlags); - - /* Change to send write address when it's a read operation with command. */ - if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) - { - direction = kI2C_Write; - } - - /* If repeated start is requested, send repeated start. */ - if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) - { - result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); - } - else /* For normal transfer, send start. */ - { - result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); - } - - if (result) - { - return result; - } - - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - /* Return if error. */ - if (result) - { - if (result == kStatus_I2C_Nak) - { - result = kStatus_I2C_Addr_Nak; - - if (I2C_MasterStop(base) != kStatus_Success) - { - result = kStatus_I2C_Timeout; - } - - if (handle->completionCallback) - { - (handle->completionCallback)(base, handle, result, handle->userData); - } - } - - return result; - } - - /* Send subaddress. */ - if (handle->transfer.subaddressSize) - { - do - { - /* Clear interrupt pending flag. */ - base->S = kI2C_IntPendingFlag; - - handle->transfer.subaddressSize--; - base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - if (result) - { - return result; - } - - } while ((handle->transfer.subaddressSize > 0) && (result == kStatus_Success)); - - if (handle->transfer.direction == kI2C_Read) - { - /* Clear pending flag. */ - base->S = kI2C_IntPendingFlag; - - /* Send repeated start and slave address. */ - result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); - - if (result) - { - return result; - } - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - if (result) - { - return result; - } - } - } - - /* Clear pending flag. */ - base->S = kI2C_IntPendingFlag; - } - - return result; -} - -static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_t *handle) -{ - edma_transfer_config_t transfer_config; - - if (handle->transfer.direction == kI2C_Read) - { - transfer_config.srcAddr = (uint32_t)I2C_GetDataRegAddr(base); - transfer_config.destAddr = (uint32_t)(handle->transfer.data); - transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1); - transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes; - transfer_config.srcOffset = 0; - transfer_config.destTransferSize = kEDMA_TransferSize1Bytes; - transfer_config.destOffset = 1; - transfer_config.minorLoopBytes = 1; - } - else - { - transfer_config.srcAddr = (uint32_t)(handle->transfer.data + 1); - transfer_config.destAddr = (uint32_t)I2C_GetDataRegAddr(base); - transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1); - transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes; - transfer_config.srcOffset = 1; - transfer_config.destTransferSize = kEDMA_TransferSize1Bytes; - transfer_config.destOffset = 0; - transfer_config.minorLoopBytes = 1; - } - - /* Store the initially configured eDMA minor byte transfer count into the I2C handle */ - handle->nbytes = transfer_config.minorLoopBytes; - - EDMA_SubmitTransfer(handle->dmaHandle, &transfer_config); - EDMA_StartTransfer(handle->dmaHandle); -} - -void I2C_MasterCreateEDMAHandle(I2C_Type *base, - i2c_master_edma_handle_t *handle, - i2c_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaHandle) -{ - assert(handle); - assert(edmaHandle); - - uint32_t instance = I2C_GetInstance(base); - - /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set the user callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Set the base for the handle. */ - base = base; - - /* Set the handle for EDMA. */ - handle->dmaHandle = edmaHandle; - - s_edmaPrivateHandle[instance].base = base; - s_edmaPrivateHandle[instance].handle = handle; - - EDMA_SetCallback(edmaHandle, (edma_callback)I2C_MasterTransferCallbackEDMA, &s_edmaPrivateHandle[instance]); -} - -status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - status_t result; - uint8_t tmpReg; - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - - /* Disable dma xfer. */ - I2C_EnableDMA(base, false); - - /* Send address and command buffer(if there is), until senddata phase or receive data phase. */ - result = I2C_InitTransferStateMachineEDMA(base, handle, xfer); - - if (result) - { - /* Send stop if received Nak. */ - if (result == kStatus_I2C_Nak) - { - if (I2C_MasterStop(base) != kStatus_Success) - { - result = kStatus_I2C_Timeout; - } - } - - /* Reset the state to idle state. */ - handle->state = kIdleState; - - return result; - } - - /* Configure dma transfer. */ - /* For i2c send, need to send 1 byte first to trigger the dma, for i2c read, - need to send stop before reading the last byte, so the dma transfer size should - be (xSize - 1). */ - if (handle->transfer.dataSize > 1) - { - I2C_MasterTransferEDMAConfig(base, handle); - if (handle->transfer.direction == kI2C_Read) - { - /* Change direction for receive. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Read dummy to release the bus. */ - dummy = base->D; - - /* Enabe dma transfer. */ - I2C_EnableDMA(base, true); - } - else - { - /* Enabe dma transfer. */ - I2C_EnableDMA(base, true); - - /* Send the first data. */ - base->D = *handle->transfer.data; - } - } - else /* If transfer size is 1, use polling method. */ - { - if (handle->transfer.direction == kI2C_Read) - { - tmpReg = base->C1; - - /* Change direction to Rx. */ - tmpReg &= ~I2C_C1_TX_MASK; - - /* Configure send NAK */ - tmpReg |= I2C_C1_TXAK_MASK; - - base->C1 = tmpReg; - - /* Read dummy to release the bus. */ - dummy = base->D; - } - else - { - base->D = *handle->transfer.data; - } - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Clear pending flag. */ - base->S = kI2C_IntPendingFlag; - - /* Send stop if kI2C_TransferNoStop flag is not asserted. */ - if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) - { - result = I2C_MasterStop(base); - } - else - { - /* Change direction to send. */ - base->C1 |= I2C_C1_TX_MASK; - } - - /* Read the last byte of data. */ - if (handle->transfer.direction == kI2C_Read) - { - *handle->transfer.data = base->D; - } - - /* Reset the state to idle. */ - handle->state = kIdleState; - } - - return result; -} - -status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count) -{ - assert(handle->dmaHandle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - if (kIdleState != handle->state) - { - *count = (handle->transferSize - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); - } - else - { - *count = handle->transferSize; - } - - return kStatus_Success; -} - -void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle) -{ - EDMA_AbortTransfer(handle->dmaHandle); - - /* Disable dma transfer. */ - I2C_EnableDMA(base, false); - - /* Reset the state to idle. */ - handle->state = kIdleState; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c_edma.h deleted file mode 100644 index 40cb648..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_i2c_edma.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2C_DMA_H_ -#define _FSL_I2C_DMA_H_ - -#include "fsl_i2c.h" -#include "fsl_dmamux.h" -#include "fsl_edma.h" - -/*! - * @addtogroup i2c_edma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief I2C master eDMA handle typedef. */ -typedef struct _i2c_master_edma_handle i2c_master_edma_handle_t; - -/*! @brief I2C master eDMA transfer callback typedef. */ -typedef void (*i2c_master_edma_transfer_callback_t)(I2C_Type *base, - i2c_master_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief I2C master eDMA transfer structure. */ -struct _i2c_master_edma_handle -{ - i2c_master_transfer_t transfer; /*!< I2C master transfer structure. */ - size_t transferSize; /*!< Total bytes to be transferred. */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint8_t state; /*!< I2C master transfer status. */ - edma_handle_t *dmaHandle; /*!< The eDMA handler used. */ - i2c_master_edma_transfer_callback_t - completionCallback; /*!< A callback function called after the eDMA transfer is finished. */ - void *userData; /*!< A callback parameter passed to the callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name I2C Block eDMA Transfer Operation - * @{ - */ - -/*! - * @brief Initializes the I2C handle which is used in transcational functions. - * - * @param base I2C peripheral base address. - * @param handle A pointer to the i2c_master_edma_handle_t structure. - * @param callback A pointer to the user callback function. - * @param userData A user parameter passed to the callback function. - * @param edmaHandle eDMA handle pointer. - */ -void I2C_MasterCreateEDMAHandle(I2C_Type *base, - i2c_master_edma_handle_t *handle, - i2c_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaHandle); - -/*! - * @brief Performs a master eDMA non-blocking transfer on the I2C bus. - * - * @param base I2C peripheral base address. - * @param handle A pointer to the i2c_master_edma_handle_t structure. - * @param xfer A pointer to the transfer structure of i2c_master_transfer_t. - * @retval kStatus_Success Sucessfully completed the data transmission. - * @retval kStatus_I2C_Busy A previous transmission is still not finished. - * @retval kStatus_I2C_Timeout Transfer error, waits for a signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Gets a master transfer status during the eDMA non-blocking transfer. - * - * @param base I2C peripheral base address. - * @param handle A pointer to the i2c_master_edma_handle_t structure. - * @param count A number of bytes transferred by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count); - -/*! - * @brief Aborts a master eDMA non-blocking transfer early. - * - * @param base I2C peripheral base address. - * @param handle A pointer to the i2c_master_edma_handle_t structure. - */ -void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ -#endif /*_FSL_I2C_DMA_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_llwu.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_llwu.c deleted file mode 100644 index c27b91e..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_llwu.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_llwu.h" - -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) -void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - volatile uint32_t *regBase; - uint32_t regOffset; - uint32_t reg; - - switch (pinIndex >> 4U) - { - case 0U: - regBase = &base->PE1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 1U: - regBase = &base->PE2; - break; -#endif - default: - regBase = NULL; - break; - } -#else - volatile uint8_t *regBase; - uint8_t regOffset; - uint8_t reg; - switch (pinIndex >> 2U) - { - case 0U: - regBase = &base->PE1; - break; - case 1U: - regBase = &base->PE2; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 2U: - regBase = &base->PE3; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12)) - case 3U: - regBase = &base->PE4; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 4U: - regBase = &base->PE5; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20)) - case 5U: - regBase = &base->PE6; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 6U: - regBase = &base->PE7; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28)) - case 7U: - regBase = &base->PE8; - break; -#endif - default: - regBase = NULL; - break; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */ - - if (regBase) - { - reg = *regBase; -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - regOffset = ((pinIndex & 0x0FU) << 1U); -#else - regOffset = ((pinIndex & 0x03U) << 1U); -#endif - reg &= ~(0x3U << regOffset); - reg |= ((uint32_t)pinMode << regOffset); - *regBase = reg; - } -} - -bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - return (bool)(base->PF & (1U << pinIndex)); -#else - volatile uint8_t *regBase; - - switch (pinIndex >> 3U) - { -#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) - case 0U: - regBase = &base->PF1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->PF2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->PF3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->PF4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#else - case 0U: - regBase = &base->F1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->F2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->F3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->F4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#endif /* FSL_FEATURE_LLWU_HAS_PF */ - default: - regBase = NULL; - break; - } - - if (regBase) - { - return (bool)(*regBase & (1U << pinIndex % 8)); - } - else - { - return false; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} - -void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - base->PF = (1U << pinIndex); -#else - volatile uint8_t *regBase; - switch (pinIndex >> 3U) - { -#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) - case 0U: - regBase = &base->PF1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->PF2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->PF3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->PF4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#else - case 0U: - regBase = &base->F1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->F2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->F3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->F4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#endif /* FSL_FEATURE_LLWU_HAS_PF */ - default: - regBase = NULL; - break; - } - if (regBase) - { - *regBase = (1U << pinIndex % 8U); - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) -void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - uint32_t reg; - - reg = base->FILT; - reg &= ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << (filterIndex * 8U - 1U)); - reg |= (((filterMode.pinIndex << LLWU_FILT_FILTSEL1_SHIFT) | (filterMode.filterMode << LLWU_FILT_FILTE1_SHIFT) - /* Clear the Filter Detect Flag */ - | LLWU_FILT_FILTF1_MASK) - << (filterIndex * 8U - 1U)); - base->FILT = reg; -#else - volatile uint8_t *regBase; - uint8_t reg; - - switch (filterIndex) - { - case 1: - regBase = &base->FILT1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2: - regBase = &base->FILT2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3: - regBase = &base->FILT3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4: - regBase = &base->FILT4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - default: - regBase = NULL; - break; - } - - if (regBase) - { - reg = *regBase; - reg &= ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK); - reg |= ((uint32_t)filterMode.pinIndex << LLWU_FILT1_FILTSEL_SHIFT); - reg |= ((uint32_t)filterMode.filterMode << LLWU_FILT1_FILTE_SHIFT); - /* Clear the Filter Detect Flag */ - reg |= LLWU_FILT1_FILTF_MASK; - *regBase = reg; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} - -bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - return (bool)(base->FILT & (1U << (filterIndex * 8U - 1))); -#else - bool status = false; - - switch (filterIndex) - { - case 1: - status = (base->FILT1 & LLWU_FILT1_FILTF_MASK); - break; -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2: - status = (base->FILT2 & LLWU_FILT2_FILTF_MASK); - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3: - status = (base->FILT3 & LLWU_FILT3_FILTF_MASK); - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4: - status = (base->FILT4 & LLWU_FILT4_FILTF_MASK); - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - default: - break; - } - - return status; -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} - -void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - uint32_t reg; - - reg = base->FILT; - switch (filterIndex) - { - case 1: - reg |= LLWU_FILT_FILTF1_MASK; - break; - case 2: - reg |= LLWU_FILT_FILTF2_MASK; - break; - case 3: - reg |= LLWU_FILT_FILTF3_MASK; - break; - case 4: - reg |= LLWU_FILT_FILTF4_MASK; - break; - default: - break; - } - base->FILT = reg; -#else - volatile uint8_t *regBase; - uint8_t reg; - - switch (filterIndex) - { - case 1: - regBase = &base->FILT1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2: - regBase = &base->FILT2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3: - regBase = &base->FILT3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4: - regBase = &base->FILT4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - default: - regBase = NULL; - break; - } - - if (regBase) - { - reg = *regBase; - reg |= LLWU_FILT1_FILTF_MASK; - *regBase = reg; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - -#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) -void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode) -{ - uint8_t reg; - - reg = base->RST; - reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK); - reg |= - (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)enableInLowLeakageMode << LLWU_RST_RSTFILT_SHIFT)); - base->RST = reg; -} -#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_llwu.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_llwu.h deleted file mode 100644 index 1384d51..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_llwu.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LLWU_H_ -#define _FSL_LLWU_H_ - -#include "fsl_common.h" - -/*! @addtogroup llwu */ -/*! @{ */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LLWU driver version 2.0.1. */ -#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief External input pin control modes - */ -typedef enum _llwu_external_pin_mode -{ - kLLWU_ExternalPinDisable = 0U, /*!< Pin disabled as wakeup input. */ - kLLWU_ExternalPinRisingEdge = 1U, /*!< Pin enabled with rising edge detection. */ - kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with falling edge detection.*/ - kLLWU_ExternalPinAnyEdge = 3U /*!< Pin enabled with any change detection. */ -} llwu_external_pin_mode_t; - -/*! - * @brief Digital filter control modes - */ -typedef enum _llwu_pin_filter_mode -{ - kLLWU_PinFilterDisable = 0U, /*!< Filter disabled. */ - kLLWU_PinFilterRisingEdge = 1U, /*!< Filter positive edge detection.*/ - kLLWU_PinFilterFallingEdge = 2U, /*!< Filter negative edge detection.*/ - kLLWU_PinFilterAnyEdge = 3U /*!< Filter any edge detection. */ -} llwu_pin_filter_mode_t; - -#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) -/*! - * @brief IP version ID definition. - */ -typedef struct _llwu_version_id -{ - uint16_t feature; /*!< Feature Specification Number. */ - uint8_t minor; /*!< Minor version number. */ - uint8_t major; /*!< Major version number. */ -} llwu_version_id_t; -#endif /* FSL_FEATURE_LLWU_HAS_VERID */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) -/*! - * @brief IP parameter definition. - */ -typedef struct _llwu_param -{ - uint8_t filters; /*!< Number of pin filter. */ - uint8_t dmas; /*!< Number of wakeup DMA. */ - uint8_t modules; /*!< Number of wakeup module. */ - uint8_t pins; /*!< Number of wake up pin. */ -} llwu_param_t; -#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) -/*! - * @brief External input pin filter control structure - */ -typedef struct _llwu_external_pin_filter_mode -{ - uint32_t pinIndex; /*!< Pin number */ - llwu_pin_filter_mode_t filterMode; /*!< Filter mode */ -} llwu_external_pin_filter_mode_t; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Low-Leakage Wakeup Unit Control APIs - * @{ - */ - -#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) -/*! - * @brief Gets the LLWU version ID. - * - * This function gets the LLWU version ID, including major version number, - * minor version number, and feature specification number. - * - * @param base LLWU peripheral base address. - * @param versionId Pointer to version ID structure. - */ -static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId) -{ - *((uint32_t *)versionId) = base->VERID; -} -#endif /* FSL_FEATURE_LLWU_HAS_VERID */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) -/*! - * @brief Gets the LLWU parameter. - * - * This function gets the LLWU parameter, including wakeup pin number, module - * number, DMA number, and pin filter number. - * - * @param base LLWU peripheral base address. - * @param param Pointer to LLWU param structure. - */ -static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param) -{ - *((uint32_t *)param) = base->PARAM; -} -#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ - -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) -/*! - * @brief Sets the external input pin source mode. - * - * This function sets the external input pin source mode that is used - * as a wake up source. - * - * @param base LLWU peripheral base address. - * @param pinIndex pin index which to be enabled as external wakeup source, start from 1. - * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t - */ -void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode); - -/*! - * @brief Gets the external wakeup source flag. - * - * This function checks the external pin flag to detect whether the MCU is - * woke up by the specific pin. - * - * @param base LLWU peripheral base address. - * @param pinIndex pin index, start from 1. - * @return true if the specific pin is wake up source. - */ -bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); - -/*! - * @brief Clears the external wakeup source flag. - * - * This function clears the external wakeup source flag for a specific pin. - * - * @param base LLWU peripheral base address. - * @param pinIndex pin index, start from 1. - */ -void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ - -#if (defined(FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) && FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) -/*! - * @brief Enables/disables the internal module source. - * - * This function enables/disables the internal module source mode that is used - * as a wake up source. - * - * @param base LLWU peripheral base address. - * @param moduleIndex module index which to be enabled as internal wakeup source, start from 1. - * @param enable enable or disable setting - */ -static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) -{ - if (enable) - { - base->ME |= 1U << moduleIndex; - } - else - { - base->ME &= ~(1U << moduleIndex); - } -} - -/*! - * @brief Gets the external wakeup source flag. - * - * This function checks the external pin flag to detect whether the system is - * woke up by the specific pin. - * - * @param base LLWU peripheral base address. - * @param moduleIndex module index, start from 1. - * @return true if the specific pin is wake up source. - */ -static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex) -{ -#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF) -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - return (bool)(base->MF & (1U << moduleIndex)); -#else - return (bool)(base->MF5 & (1U << moduleIndex)); -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -#else -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - return (bool)(base->F5 & (1U << moduleIndex)); -#else -#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) - return (bool)(base->PF3 & (1U << moduleIndex)); -#else - return (bool)(base->F3 & (1U << moduleIndex)); -#endif /* FSL_FEATURE_LLWU_HAS_PF */ -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#endif /* FSL_FEATURE_LLWU_HAS_MF */ -} -#endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */ - -#if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) -/*! - * @brief Enables/disables the internal module DMA wakeup source. - * - * This function enables/disables the internal DMA that is used as a wake up source. - * - * @param base LLWU peripheral base address. - * @param moduleIndex Internal module index which used as DMA request source, start from 1. - * @param enable Enable or disable DMA request source - */ -static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) -{ - if (enable) - { - base->DE |= 1U << moduleIndex; - } - else - { - base->DE &= ~(1U << moduleIndex); - } -} -#endif /* FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) -/*! - * @brief Sets the pin filter configuration. - * - * This function sets the pin filter configuration. - * - * @param base LLWU peripheral base address. - * @param filterIndex pin filter index which used to enable/disable the digital filter, start from 1. - * @param filterMode filter mode configuration - */ -void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode); - -/*! - * @brief Gets the pin filter configuration. - * - * This function gets the pin filter flag. - * - * @param base LLWU peripheral base address. - * @param filterIndex pin filter index, start from 1. - * @return true if the flag is a source of existing a low-leakage power mode. - */ -bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); - -/*! - * @brief Clear the pin filter configuration. - * - * This function clear the pin filter flag. - * - * @param base LLWU peripheral base address. - * @param filterIndex pin filter index which to be clear the flag, start from 1. - */ -void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); - -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - -#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) -/*! - * @brief Sets the reset pin mode. - * - * This function sets how the reset pin is used as a low leakage mode exit source. - * - * @param pinEnable Enable reset pin filter - * @param pinFilterEnable Specify whether pin filter is enabled in Low-Leakage power mode. - */ -void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode); -#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ -#endif /* _FSL_LLWU_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_lptmr.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_lptmr.c deleted file mode 100644 index b3dcc89..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_lptmr.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lptmr.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address to be used to gate or ungate the module clock - * - * @param base LPTMR peripheral base address - * - * @return The LPTMR instance - */ -static uint32_t LPTMR_GetInstance(LPTMR_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to LPTMR bases for each instance. */ -static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS; - -/*! @brief Pointers to LPTMR clocks for each instance. */ -static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LPTMR_GetInstance(LPTMR_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_LPTMR_COUNT; instance++) - { - if (s_lptmrBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_LPTMR_COUNT); - - return instance; -} - -void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) -{ - assert(config); - - /* Ungate the LPTMR clock*/ - CLOCK_EnableClock(s_lptmrClocks[LPTMR_GetInstance(base)]); - - /* Configure the timers operation mode and input pin setup */ - base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | - LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect)); - - /* Configure the prescale value and clock source */ - base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | - LPTMR_PSR_PCS(config->prescalerClockSource)); -} - -void LPTMR_Deinit(LPTMR_Type *base) -{ - /* Disable the LPTMR and reset the internal logic */ - base->CSR &= ~LPTMR_CSR_TEN_MASK; - /* Gate the LPTMR clock*/ - CLOCK_DisableClock(s_lptmrClocks[LPTMR_GetInstance(base)]); -} - -void LPTMR_GetDefaultConfig(lptmr_config_t *config) -{ - assert(config); - - /* Use time counter mode */ - config->timerMode = kLPTMR_TimerModeTimeCounter; - /* Use input 0 as source in pulse counter mode */ - config->pinSelect = kLPTMR_PinSelectInput_0; - /* Pulse input pin polarity is active-high */ - config->pinPolarity = kLPTMR_PinPolarityActiveHigh; - /* Counter resets whenever TCF flag is set */ - config->enableFreeRunning = false; - /* Bypass the prescaler */ - config->bypassPrescaler = true; - /* LPTMR clock source */ - config->prescalerClockSource = kLPTMR_PrescalerClock_1; - /* Divide the prescaler clock by 2 */ - config->value = kLPTMR_Prescale_Glitch_0; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_lptmr.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_lptmr.h deleted file mode 100644 index d022cbb..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_lptmr.h +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LPTMR_H_ -#define _FSL_LPTMR_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lptmr - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief LPTMR pin selection, used in pulse counter mode.*/ -typedef enum _lptmr_pin_select -{ - kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */ - kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */ - kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */ - kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */ -} lptmr_pin_select_t; - -/*! @brief LPTMR pin polarity, used in pulse counter mode.*/ -typedef enum _lptmr_pin_polarity -{ - kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */ - kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */ -} lptmr_pin_polarity_t; - -/*! @brief LPTMR timer mode selection.*/ -typedef enum _lptmr_timer_mode -{ - kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */ - kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */ -} lptmr_timer_mode_t; - -/*! @brief LPTMR prescaler/glitch filter values*/ -typedef enum _lptmr_prescaler_glitch_value -{ - kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */ - kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */ - kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */ - kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */ - kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */ - kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */ - kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */ - kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */ - kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */ - kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/ - kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */ - kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */ - kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */ - kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */ - kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */ - kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */ -} lptmr_prescaler_glitch_value_t; - -/*! - * @brief LPTMR prescaler/glitch filter clock select. - * @note Clock connections are SoC-specific - */ -typedef enum _lptmr_prescaler_clock_select -{ - kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ - kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ - kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ - kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ -} lptmr_prescaler_clock_select_t; - -/*! @brief List of LPTMR interrupts */ -typedef enum _lptmr_interrupt_enable -{ - kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */ -} lptmr_interrupt_enable_t; - -/*! @brief List of LPTMR status flags */ -typedef enum _lptmr_status_flags -{ - kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */ -} lptmr_status_flags_t; - -/*! - * @brief LPTMR config structure - * - * This structure holds the configuration settings for the LPTMR peripheral. To initialize this - * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _lptmr_config -{ - lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */ - lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */ - lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */ - bool enableFreeRunning; /*!< true: enable free running, counter is reset on overflow - false: counter is reset when the compare flag is set */ - bool bypassPrescaler; /*!< true: bypass prescaler; false: use clock from prescaler */ - lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */ - lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ -} lptmr_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungate the LPTMR clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the LPTMR driver. - * - * @param base LPTMR peripheral base address - * @param config Pointer to user's LPTMR config structure. - */ -void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config); - -/*! - * @brief Gate the LPTMR clock - * - * @param base LPTMR peripheral base address - */ -void LPTMR_Deinit(LPTMR_Type *base); - -/*! - * @brief Fill in the LPTMR config struct with the default settings - * - * The default values are: - * @code - * config->timerMode = kLPTMR_TimerModeTimeCounter; - * config->pinSelect = kLPTMR_PinSelectInput_0; - * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; - * config->enableFreeRunning = false; - * config->bypassPrescaler = true; - * config->prescalerClockSource = kLPTMR_PrescalerClock_1; - * config->value = kLPTMR_Prescale_Glitch_0; - * @endcode - * @param config Pointer to user's LPTMR config structure. - */ -void LPTMR_GetDefaultConfig(lptmr_config_t *config); - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected LPTMR interrupts. - * - * @param base LPTMR peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::lptmr_interrupt_enable_t - */ -static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg |= mask; - base->CSR = reg; -} - -/*! - * @brief Disables the selected LPTMR interrupts. - * - * @param base LPTMR peripheral base address - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::lptmr_interrupt_enable_t - */ -static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg &= ~mask; - base->CSR = reg; -} - -/*! - * @brief Gets the enabled LPTMR interrupts. - * - * @param base LPTMR peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::lptmr_interrupt_enable_t - */ -static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) -{ - return (base->CSR & LPTMR_CSR_TIE_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the LPTMR status flags - * - * @param base LPTMR peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::lptmr_status_flags_t - */ -static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base) -{ - return (base->CSR & LPTMR_CSR_TCF_MASK); -} - -/*! - * @brief Clears the LPTMR status flags - * - * @param base LPTMR peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::lptmr_status_flags_t - */ -static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) -{ - base->CSR |= mask; -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in units of count. - * - * Timers counts from 0 till it equals the count value set here. The count value is written to - * the CMR register. - * - * @note - * 1. The TCF flag is set with the CNR equals the count provided here and then increments. - * 2. User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base LPTMR peripheral base address - * @param ticks Timer period in units of ticks - */ -static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint16_t ticks) -{ - base->CMR = ticks; -} - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base LPTMR peripheral base address - * - * @return Current counter value in ticks - */ -static inline uint16_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base) -{ - /* Must first write any value to the CNR. This synchronizes and registers the current value - * of the CNR into a temporary register which can then be read - */ - base->CNR = 0U; - return (uint16_t)base->CNR; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, the timer counts up to the CMR register value. - * Each time the timer reaches CMR value and then increments, it generates a - * trigger pulse and sets the timeout interrupt flag. An interrupt is also - * triggered if the timer interrupt is enabled. - * - * @param base LPTMR peripheral base address - */ -static inline void LPTMR_StartTimer(LPTMR_Type *base) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg |= LPTMR_CSR_TEN_MASK; - base->CSR = reg; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops the timer counting and resets the timer's counter register - * - * @param base LPTMR peripheral base address - */ -static inline void LPTMR_StopTimer(LPTMR_Type *base) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg &= ~LPTMR_CSR_TEN_MASK; - base->CSR = reg; -} - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_LPTMR_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pdb.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pdb.c deleted file mode 100644 index dcc03ba..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pdb.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pdb.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for PDB module. - * - * @param base PDB peripheral base address - */ -static uint32_t PDB_GetInstance(PDB_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PDB bases for each instance. */ -static PDB_Type *const s_pdbBases[] = PDB_BASE_PTRS; -/*! @brief Pointers to PDB clocks for each instance. */ -static const clock_ip_name_t s_pdbClocks[] = PDB_CLOCKS; - -/******************************************************************************* - * Codes - ******************************************************************************/ -static uint32_t PDB_GetInstance(PDB_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_PDB_COUNT; instance++) - { - if (s_pdbBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_PDB_COUNT); - - return instance; -} - -void PDB_Init(PDB_Type *base, const pdb_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - - /* Enable the clock. */ - CLOCK_EnableClock(s_pdbClocks[PDB_GetInstance(base)]); - - /* Configure. */ - /* PDBx_SC. */ - tmp32 = base->SC & - ~(PDB_SC_LDMOD_MASK | PDB_SC_PRESCALER_MASK | PDB_SC_TRGSEL_MASK | PDB_SC_MULT_MASK | PDB_SC_CONT_MASK); - - tmp32 |= PDB_SC_LDMOD(config->loadValueMode) | PDB_SC_PRESCALER(config->prescalerDivider) | - PDB_SC_TRGSEL(config->triggerInputSource) | PDB_SC_MULT(config->dividerMultiplicationFactor); - if (config->enableContinuousMode) - { - tmp32 |= PDB_SC_CONT_MASK; - } - base->SC = tmp32; - - PDB_Enable(base, true); /* Enable the PDB module. */ -} - -void PDB_Deinit(PDB_Type *base) -{ - PDB_Enable(base, false); /* Disable the PDB module. */ - - /* Disable the clock. */ - CLOCK_DisableClock(s_pdbClocks[PDB_GetInstance(base)]); -} - -void PDB_GetDefaultConfig(pdb_config_t *config) -{ - assert(NULL != config); - - config->loadValueMode = kPDB_LoadValueImmediately; - config->prescalerDivider = kPDB_PrescalerDivider1; - config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1; - config->triggerInputSource = kPDB_TriggerSoftware; - config->enableContinuousMode = false; -} - -#if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC -void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config) -{ - assert(channel < PDB_INTC_COUNT); - assert(NULL != config); - - uint32_t tmp32 = 0U; - - /* PDBx_DACINTC. */ - if (config->enableExternalTriggerInput) - { - tmp32 |= PDB_INTC_EXT_MASK; - } - if (config->enableIntervalTrigger) - { - tmp32 |= PDB_INTC_TOE_MASK; - } - base->DAC[channel].INTC = tmp32; -} -#endif /* FSL_FEATURE_PDB_HAS_DAC */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pdb.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pdb.h deleted file mode 100644 index 5fed10a..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pdb.h +++ /dev/null @@ -1,575 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_PDB_H_ -#define _FSL_PDB_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pdb - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief PDB driver version 2.0.1. */ -#define FSL_PDB_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief PDB flags. - */ -enum _pdb_status_flags -{ - kPDB_LoadOKFlag = PDB_SC_LDOK_MASK, /*!< This flag is automatically cleared when the values in buffers are - loaded into the internal registers after the LDOK bit is set or the - PDBEN is cleared. */ - kPDB_DelayEventFlag = PDB_SC_PDBIF_MASK, /*!< PDB timer delay event flag. */ -}; - -/*! - * @brief PDB ADC PreTrigger channel flags. - */ -enum _pdb_adc_pretrigger_flags -{ - /* PDB PreTrigger channel match flags. */ - kPDB_ADCPreTriggerChannel0Flag = PDB_S_CF(1U << 0), /*!< Pre-Trigger 0 flag. */ - kPDB_ADCPreTriggerChannel1Flag = PDB_S_CF(1U << 1), /*!< Pre-Trigger 1 flag. */ -#if (PDB_DLY_COUNT > 2) - kPDB_ADCPreTriggerChannel2Flag = PDB_S_CF(1U << 2), /*!< Pre-Trigger 2 flag. */ - kPDB_ADCPreTriggerChannel3Flag = PDB_S_CF(1U << 3), /*!< Pre-Trigger 3 flag. */ -#endif /* PDB_DLY_COUNT > 2 */ -#if (PDB_DLY_COUNT > 4) - kPDB_ADCPreTriggerChannel4Flag = PDB_S_CF(1U << 4), /*!< Pre-Trigger 4 flag. */ - kPDB_ADCPreTriggerChannel5Flag = PDB_S_CF(1U << 5), /*!< Pre-Trigger 5 flag. */ - kPDB_ADCPreTriggerChannel6Flag = PDB_S_CF(1U << 6), /*!< Pre-Trigger 6 flag. */ - kPDB_ADCPreTriggerChannel7Flag = PDB_S_CF(1U << 7), /*!< Pre-Trigger 7 flag. */ -#endif /* PDB_DLY_COUNT > 4 */ - - /* PDB PreTrigger channel error flags. */ - kPDB_ADCPreTriggerChannel0ErrorFlag = PDB_S_ERR(1U << 0), /*!< Pre-Trigger 0 Error. */ - kPDB_ADCPreTriggerChannel1ErrorFlag = PDB_S_ERR(1U << 1), /*!< Pre-Trigger 1 Error. */ -#if (PDB_DLY_COUNT > 2) - kPDB_ADCPreTriggerChannel2ErrorFlag = PDB_S_ERR(1U << 2), /*!< Pre-Trigger 2 Error. */ - kPDB_ADCPreTriggerChannel3ErrorFlag = PDB_S_ERR(1U << 3), /*!< Pre-Trigger 3 Error. */ -#endif /* PDB_DLY_COUNT > 2 */ -#if (PDB_DLY_COUNT > 4) - kPDB_ADCPreTriggerChannel4ErrorFlag = PDB_S_ERR(1U << 4), /*!< Pre-Trigger 4 Error. */ - kPDB_ADCPreTriggerChannel5ErrorFlag = PDB_S_ERR(1U << 5), /*!< Pre-Trigger 5 Error. */ - kPDB_ADCPreTriggerChannel6ErrorFlag = PDB_S_ERR(1U << 6), /*!< Pre-Trigger 6 Error. */ - kPDB_ADCPreTriggerChannel7ErrorFlag = PDB_S_ERR(1U << 7), /*!< Pre-Trigger 7 Error. */ -#endif /* PDB_DLY_COUNT > 4 */ -}; - -/*! - * @brief PDB buffer interrupts. - */ -enum _pdb_interrupt_enable -{ - kPDB_SequenceErrorInterruptEnable = PDB_SC_PDBEIE_MASK, /*!< PDB sequence error interrupt enable. */ - kPDB_DelayInterruptEnable = PDB_SC_PDBIE_MASK, /*!< PDB delay interrupt enable. */ -}; - -/*! - * @brief PDB load value mode. - * - * Selects the mode to load the internal values after doing the load operation (write 1 to PDBx_SC[LDOK]). - * These values are for: - * - PDB counter (PDBx_MOD, PDBx_IDLY) - * - ADC trigger (PDBx_CHnDLYm) - * - DAC trigger (PDBx_DACINTx) - * - CMP trigger (PDBx_POyDLY) - */ -typedef enum _pdb_load_value_mode -{ - kPDB_LoadValueImmediately = 0U, /*!< Load immediately after 1 is written to LDOK. */ - kPDB_LoadValueOnCounterOverflow = 1U, /*!< Load when the PDB counter overflows (reaches the MOD - register value). */ - kPDB_LoadValueOnTriggerInput = 2U, /*!< Load a trigger input event is detected. */ - kPDB_LoadValueOnCounterOverflowOrTriggerInput = 3U, /*!< Load either when the PDB counter overflows or a trigger - input is detected. */ -} pdb_load_value_mode_t; - -/*! - * @brief Prescaler divider. - * - * Counting uses the peripheral clock divided by multiplication factor selected by times of MULT. - */ -typedef enum _pdb_prescaler_divider -{ - kPDB_PrescalerDivider1 = 0U, /*!< Divider x1. */ - kPDB_PrescalerDivider2 = 1U, /*!< Divider x2. */ - kPDB_PrescalerDivider4 = 2U, /*!< Divider x4. */ - kPDB_PrescalerDivider8 = 3U, /*!< Divider x8. */ - kPDB_PrescalerDivider16 = 4U, /*!< Divider x16. */ - kPDB_PrescalerDivider32 = 5U, /*!< Divider x32. */ - kPDB_PrescalerDivider64 = 6U, /*!< Divider x64. */ - kPDB_PrescalerDivider128 = 7U, /*!< Divider x128. */ -} pdb_prescaler_divider_t; - -/*! - * @brief Multiplication factor select for prescaler. - * - * Selects the multiplication factor of the prescaler divider for the counter clock. - */ -typedef enum _pdb_divider_multiplication_factor -{ - kPDB_DividerMultiplicationFactor1 = 0U, /*!< Multiplication factor is 1. */ - kPDB_DividerMultiplicationFactor10 = 1U, /*!< Multiplication factor is 10. */ - kPDB_DividerMultiplicationFactor20 = 2U, /*!< Multiplication factor is 20. */ - kPDB_DividerMultiplicationFactor40 = 3U, /*!< Multiplication factor is 40. */ -} pdb_divider_multiplication_factor_t; - -/*! - * @brief Trigger input source - * - * Selects the trigger input source for the PDB. The trigger input source can be internal or external (EXTRG pin), or - * the software trigger. See chip configuration details for the actual PDB input trigger connections. - */ -typedef enum _pdb_trigger_input_source -{ - kPDB_TriggerInput0 = 0U, /*!< Trigger-In 0. */ - kPDB_TriggerInput1 = 1U, /*!< Trigger-In 1. */ - kPDB_TriggerInput2 = 2U, /*!< Trigger-In 2. */ - kPDB_TriggerInput3 = 3U, /*!< Trigger-In 3. */ - kPDB_TriggerInput4 = 4U, /*!< Trigger-In 4. */ - kPDB_TriggerInput5 = 5U, /*!< Trigger-In 5. */ - kPDB_TriggerInput6 = 6U, /*!< Trigger-In 6. */ - kPDB_TriggerInput7 = 7U, /*!< Trigger-In 7. */ - kPDB_TriggerInput8 = 8U, /*!< Trigger-In 8. */ - kPDB_TriggerInput9 = 9U, /*!< Trigger-In 9. */ - kPDB_TriggerInput10 = 10U, /*!< Trigger-In 10. */ - kPDB_TriggerInput11 = 11U, /*!< Trigger-In 11. */ - kPDB_TriggerInput12 = 12U, /*!< Trigger-In 12. */ - kPDB_TriggerInput13 = 13U, /*!< Trigger-In 13. */ - kPDB_TriggerInput14 = 14U, /*!< Trigger-In 14. */ - kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15, software trigger. */ -} pdb_trigger_input_source_t; - -/*! - * @brief PDB module configuration. - */ -typedef struct _pdb_config -{ - pdb_load_value_mode_t loadValueMode; /*!< Select the load value mode. */ - pdb_prescaler_divider_t prescalerDivider; /*!< Select the prescaler divider. */ - pdb_divider_multiplication_factor_t dividerMultiplicationFactor; /*!< Multiplication factor select for prescaler. */ - pdb_trigger_input_source_t triggerInputSource; /*!< Select the trigger input source. */ - bool enableContinuousMode; /*!< Enable the PDB operation in Continuous mode.*/ -} pdb_config_t; - -/*! - * @brief PDB ADC Pre-Trigger configuration. - */ -typedef struct _pdb_adc_pretrigger_config -{ - uint32_t enablePreTriggerMask; /*!< PDB Channel Pre-Trigger Enable. */ - uint32_t enableOutputMask; /*!< PDB Channel Pre-Trigger Output Select. - PDB channel's corresponding pre-trigger asserts when the counter - reaches the channel delay register. */ - uint32_t enableBackToBackOperationMask; /*!< PDB Channel Pre-Trigger Back-to-Back Operation Enable. - Back-to-back operation enables the ADC conversions complete to trigger - the next PDB channel pre-trigger and trigger output, so that the ADC - conversions can be triggered on next set of configuration and results - registers.*/ -} pdb_adc_pretrigger_config_t; - -/*! - * @brief PDB DAC trigger configuration. - */ -typedef struct _pdb_dac_trigger_config -{ - bool enableExternalTriggerInput; /*!< Enables the external trigger for DAC interval counter. */ - bool enableIntervalTrigger; /*!< Enables the DAC interval trigger. */ -} pdb_dac_trigger_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the PDB module. - * - * This function is to make the initialization for PDB module. The operations includes are: - * - Enable the clock for PDB instance. - * - Configure the PDB module. - * - Enable the PDB module. - * - * @param base PDB peripheral base address. - * @param config Pointer to configuration structure. See "pdb_config_t". - */ -void PDB_Init(PDB_Type *base, const pdb_config_t *config); - -/*! - * @brief De-initializes the PDB module. - * - * @param base PDB peripheral base address. - */ -void PDB_Deinit(PDB_Type *base); - -/*! - * @brief Initializes the PDB user configuration structure. - * - * This function initializes the user configuration structure to default value. The default values are: - * @code - * config->loadValueMode = kPDB_LoadValueImmediately; - * config->prescalerDivider = kPDB_PrescalerDivider1; - * config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1; - * config->triggerInputSource = kPDB_TriggerSoftware; - * config->enableContinuousMode = false; - * @endcode - * @param config Pointer to configuration structure. See "pdb_config_t". - */ -void PDB_GetDefaultConfig(pdb_config_t *config); - -/*! - * @brief Enables the PDB module. - * - * @param base PDB peripheral base address. - * @param enable Enable the module or not. - */ -static inline void PDB_Enable(PDB_Type *base, bool enable) -{ - if (enable) - { - base->SC |= PDB_SC_PDBEN_MASK; - } - else - { - base->SC &= ~PDB_SC_PDBEN_MASK; - } -} - -/* @} */ - -/*! - * @name Basic Counter - * @{ - */ - -/*! - * @brief Triggers the PDB counter by software. - * - * @param base PDB peripheral base address. - */ -static inline void PDB_DoSoftwareTrigger(PDB_Type *base) -{ - base->SC |= PDB_SC_SWTRIG_MASK; -} - -/*! - * @brief Loads the counter values. - * - * This function is to load the counter values from their internal buffer. - * See "pdb_load_value_mode_t" about PDB's load mode. - * - * @param base PDB peripheral base address. - */ -static inline void PDB_DoLoadValues(PDB_Type *base) -{ - base->SC |= PDB_SC_LDOK_MASK; -} - -/*! - * @brief Enables the DMA for the PDB module. - * - * @param base PDB peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PDB_EnableDMA(PDB_Type *base, bool enable) -{ - if (enable) - { - base->SC |= PDB_SC_DMAEN_MASK; - } - else - { - base->SC &= ~PDB_SC_DMAEN_MASK; - } -} - -/*! - * @brief Enables the interrupts for the PDB module. - * - * @param base PDB peripheral base address. - * @param mask Mask value for interrupts. See "_pdb_interrupt_enable". - */ -static inline void PDB_EnableInterrupts(PDB_Type *base, uint32_t mask) -{ - assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK))); - - base->SC |= mask; -} - -/*! - * @brief Disables the interrupts for the PDB module. - * - * @param base PDB peripheral base address. - * @param mask Mask value for interrupts. See "_pdb_interrupt_enable". - */ -static inline void PDB_DisableInterrupts(PDB_Type *base, uint32_t mask) -{ - assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK))); - - base->SC &= ~mask; -} - -/*! - * @brief Gets the status flags of the PDB module. - * - * @param base PDB peripheral base address. - * - * @return Mask value for asserted flags. See "_pdb_status_flags". - */ -static inline uint32_t PDB_GetStatusFlags(PDB_Type *base) -{ - return base->SC & (PDB_SC_PDBIF_MASK | PDB_SC_LDOK_MASK); -} - -/*! - * @brief Clears the status flags of the PDB module. - * - * @param base PDB peripheral base address. - * @param mask Mask value of flags. See "_pdb_status_flags". - */ -static inline void PDB_ClearStatusFlags(PDB_Type *base, uint32_t mask) -{ - assert(0U == (mask & ~PDB_SC_PDBIF_MASK)); - - base->SC &= ~mask; -} - -/*! - * @brief Specifies the period of the counter. - * - * @param base PDB peripheral base address. - * @param value Setting value for the modulus. 16-bit is available. - */ -static inline void PDB_SetModulusValue(PDB_Type *base, uint32_t value) -{ - base->MOD = PDB_MOD_MOD(value); -} - -/*! - * @brief Gets the PDB counter's current value. - * - * @param base PDB peripheral base address. - * - * @return PDB counter's current value. - */ -static inline uint32_t PDB_GetCounterValue(PDB_Type *base) -{ - return base->CNT; -} - -/*! - * @brief Sets the value for PDB counter delay event. - * - * @param base PDB peripheral base address. - * @param value Setting value for PDB counter delay event. 16-bit is available. - */ -static inline void PDB_SetCounterDelayValue(PDB_Type *base, uint32_t value) -{ - base->IDLY = PDB_IDLY_IDLY(value); -} -/* @} */ - -/*! - * @name ADC Pre-Trigger - * @{ - */ - -/*! - * @brief Configures the ADC PreTrigger in PDB module. - * - * @param base PDB peripheral base address. - * @param channel Channel index for ADC instance. - * @param config Pointer to configuration structure. See "pdb_adc_pretrigger_config_t". - */ -static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel, pdb_adc_pretrigger_config_t *config) -{ - assert(channel < PDB_C1_COUNT); - assert(NULL != config); - - base->CH[channel].C1 = PDB_C1_BB(config->enableBackToBackOperationMask) | PDB_C1_TOS(config->enableOutputMask) | - PDB_C1_EN(config->enablePreTriggerMask); -} - -/*! - * @brief Sets the value for ADC Pre-Trigger delay event. - * - * This function is to set the value for ADC Pre-Trigger delay event. IT Specifies the delay value for the channel's - * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the setting value here. - * - * @param base PDB peripheral base address. - * @param channel Channel index for ADC instance. - * @param preChannel Channel group index for ADC instance. - * @param value Setting value for ADC Pre-Trigger delay event. 16-bit is available. - */ -static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t preChannel, uint32_t value) -{ - assert(channel < PDB_C1_COUNT); - assert(preChannel < PDB_DLY_COUNT); - - base->CH[channel].DLY[preChannel] = PDB_DLY_DLY(value); -} - -/*! - * @brief Gets the ADC Pre-Trigger's status flags. - * - * @param base PDB peripheral base address. - * @param channel Channel index for ADC instance. - * - * @return Mask value for asserted flags. See "_pdb_adc_pretrigger_flags". - */ -static inline uint32_t PDB_GetADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel) -{ - assert(channel < PDB_C1_COUNT); - - return base->CH[channel].S; -} - -/*! - * @brief Clears the ADC Pre-Trigger's status flags. - * - * @param base PDB peripheral base address. - * @param channel Channel index for ADC instance. - * @param mask Mask value for flags. See "_pdb_adc_pretrigger_flags". - */ -static inline void PDB_ClearADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < PDB_C1_COUNT); - - base->CH[channel].S &= ~mask; -} - -/* @} */ - -#if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC -/*! - * @name DAC Interval Trigger - * @{ - */ - -/*! - * @brief Configures the DAC trigger in PDB module. - * - * @param base PDB peripheral base address. - * @param channel Channel index for DAC instance. - * @param config Pointer to configuration structure. See "pdb_dac_trigger_config_t". - */ -void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config); - -/*! - * @brief Sets the value for the DAC interval event. - * - * This fucntion is to set the value for DAC interval event. DAC interval trigger would trigger the DAC module to update - * buffer when the DAC interval counter is equal to the setting value here. - * - * @param base PDB peripheral base address. - * @param channel Channel index for DAC instance. - * @param value Setting value for the DAC interval event. - */ -static inline void PDB_SetDACTriggerIntervalValue(PDB_Type *base, uint32_t channel, uint32_t value) -{ - assert(channel < PDB_INT_COUNT); - - base->DAC[channel].INT = PDB_INT_INT(value); -} - -/* @} */ -#endif /* FSL_FEATURE_PDB_HAS_DAC */ - -/*! - * @name Pulse-Out Trigger - * @{ - */ - -/*! - * @brief Enables the pulse out trigger channels. - * - * @param base PDB peripheral base address. - * @param channelMask Channel mask value for multiple pulse out trigger channel. - * @param enable Enable the feature or not. - */ -static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMask, bool enable) -{ - if (enable) - { - base->POEN |= PDB_POEN_POEN(channelMask); - } - else - { - base->POEN &= ~(PDB_POEN_POEN(channelMask)); - } -} - -/*! - * @brief Sets event values for pulse out trigger. - * - * This function is used to set event values for pulse output trigger. - * These pulse output trigger delay values specify the delay for the PDB Pulse-Out. Pulse-Out goes high when the PDB - * counter is equal to the pulse output high value (value1). Pulse-Out goes low when the PDB counter is equal to the - * pulse output low value (value2). - * - * @param base PDB peripheral base address. - * @param channel Channel index for pulse out trigger channel. - * @param value1 Setting value for pulse out high. - * @param value2 Setting value for pulse out low. - */ -static inline void PDB_SetPulseOutTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t value1, uint32_t value2) -{ - assert(channel < PDB_PODLY_COUNT); - - base->PODLY[channel] = PDB_PODLY_DLY1(value1) | PDB_PODLY_DLY2(value2); -} - -/* @} */ -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_PDB_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pit.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pit.c deleted file mode 100644 index 1f2fdfe..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pit.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pit.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address to be used to gate or ungate the module clock - * - * @param base PIT peripheral base address - * - * @return The PIT instance - */ -static uint32_t PIT_GetInstance(PIT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PIT bases for each instance. */ -static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS; - -/*! @brief Pointers to PIT clocks for each instance. */ -static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t PIT_GetInstance(PIT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_PIT_COUNT; instance++) - { - if (s_pitBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_PIT_COUNT); - - return instance; -} - -void PIT_Init(PIT_Type *base, const pit_config_t *config) -{ - assert(config); - - /* Ungate the PIT clock*/ - CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]); - - /* Enable PIT timers */ - base->MCR &= ~PIT_MCR_MDIS_MASK; - - /* Config timer operation when in debug mode */ - if (config->enableRunInDebug) - { - base->MCR &= ~PIT_MCR_FRZ_MASK; - } - else - { - base->MCR |= PIT_MCR_FRZ_MASK; - } -} - -void PIT_Deinit(PIT_Type *base) -{ - /* Disable PIT timers */ - base->MCR |= PIT_MCR_MDIS_MASK; - - /* Gate the PIT clock*/ - CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]); -} - -#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER - -uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) -{ - uint32_t valueH = 0U; - uint32_t valueL = 0U; - - /* LTMR64H should be read before LTMR64L */ - valueH = base->LTMR64H; - valueL = base->LTMR64L; - - return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); -} - -#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pit.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pit.h deleted file mode 100644 index f94c14a..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pit.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_PIT_H_ -#define _FSL_PIT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pit - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! - * @brief List of PIT channels - * @note Actual number of available channels is SoC dependent - */ -typedef enum _pit_chnl -{ - kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/ - kPIT_Chnl_1, /*!< PIT channel number 1 */ - kPIT_Chnl_2, /*!< PIT channel number 2 */ - kPIT_Chnl_3, /*!< PIT channel number 3 */ -} pit_chnl_t; - -/*! @brief List of PIT interrupts */ -typedef enum _pit_interrupt_enable -{ - kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/ -} pit_interrupt_enable_t; - -/*! @brief List of PIT status flags */ -typedef enum _pit_status_flags -{ - kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */ -} pit_status_flags_t; - -/*! - * @brief PIT config structure - * - * This structure holds the configuration settings for the PIT peripheral. To initialize this - * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _pit_config -{ - bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ -} pit_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the PIT clock, enables the PIT module and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the PIT driver. - * - * @param base PIT peripheral base address - * @param config Pointer to user's PIT config structure - */ -void PIT_Init(PIT_Type *base, const pit_config_t *config); - -/*! - * @brief Gate the PIT clock and disable the PIT module - * - * @param base PIT peripheral base address - */ -void PIT_Deinit(PIT_Type *base); - -/*! - * @brief Fill in the PIT config struct with the default settings - * - * The default values are: - * @code - * config->enableRunInDebug = false; - * @endcode - * @param config Pointer to user's PIT config structure. - */ -static inline void PIT_GetDefaultConfig(pit_config_t *config) -{ - assert(config); - - /* Timers are stopped in Debug mode */ - config->enableRunInDebug = false; -} - -#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE - -/*! - * @brief Enables or disables chaining a timer with the previous timer. - * - * When a timer has a chain mode enabled, it only counts after the previous - * timer has expired. If the timer n-1 has counted down to 0, counter n - * decrements the value by one. Each timer is 32-bits, this allows the developers - * to chain timers together and form a longer timer (64-bits and larger). The first timer - * (timer 0) cannot be chained to any other timer. - * - * @param base PIT peripheral base address - * @param channel Timer channel number which is chained with the previous timer - * @param enable Enable or disable chain. - * true: Current timer is chained with the previous timer. - * false: Timer doesn't chain with other timers. - */ -static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable) -{ - if (enable) - { - base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; - } - else - { - base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; - } -} - -#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */ - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected PIT interrupts. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::pit_interrupt_enable_t - */ -static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].TCTRL |= mask; -} - -/*! - * @brief Disables the selected PIT interrupts. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::pit_interrupt_enable_t - */ -static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].TCTRL &= ~mask; -} - -/*! - * @brief Gets the enabled PIT interrupts. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::pit_interrupt_enable_t - */ -static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel) -{ - return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the PIT status flags - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::pit_status_flags_t - */ -static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel) -{ - return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK); -} - -/*! - * @brief Clears the PIT status flags. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::pit_status_flags_t - */ -static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].TFLG = mask; -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in units of count. - * - * Timers begin counting from the value set by this function until it reaches 0, - * then it generates an interrupt and load this register value again. - * Writing a new value to this register does not restart the timer. Instead, the value - * is loaded after the timer expires. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - */ -static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count) -{ - base->CHANNEL[channel].LDVAL = count; -} - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel) -{ - return base->CHANNEL[channel].CVAL; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, count down to 0 and - * then load the respective start value again. Each time a timer reaches 0, - * it generates a trigger pulse and sets the timeout interrupt flag. - * - * @param base PIT peripheral base address - * @param channel Timer channel number. - */ -static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel) -{ - base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops every timer counting. Timers reload their periods - * respectively after the next time they call the PIT_DRV_StartTimer. - * - * @param base PIT peripheral base address - * @param channel Timer channel number. - */ -static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel) -{ - base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; -} - -/*! @}*/ - -#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER - -/*! - * @brief Reads the current lifetime counter value. - * - * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. - * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. - * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". - * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit - * has the value of timer 0. - * - * @param base PIT peripheral base address - * - * @return Current lifetime timer value - */ -uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base); - -#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PIT_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pmc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pmc.c deleted file mode 100644 index 82d7b7a..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pmc.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_pmc.h" - -#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) -void PMC_GetParam(PMC_Type *base, pmc_param_t *param) -{ - uint32_t reg = base->PARAM; - ; - param->vlpoEnable = (bool)(reg & PMC_PARAM_VLPOE_MASK); - param->hvdEnable = (bool)(reg & PMC_PARAM_HVDE_MASK); -} -#endif /* FSL_FEATURE_PMC_HAS_PARAM */ - -void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config) -{ - base->LVDSC1 = (0U | -#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) - ((uint32_t)config->voltSelect << PMC_LVDSC1_LVDV_SHIFT) | -#endif - ((uint32_t)config->enableInt << PMC_LVDSC1_LVDIE_SHIFT) | - ((uint32_t)config->enableReset << PMC_LVDSC1_LVDRE_SHIFT) - /* Clear the Low Voltage Detect Flag with previouse power detect setting */ - | PMC_LVDSC1_LVDACK_MASK); -} - -void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config) -{ - base->LVDSC2 = (0U | -#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) - ((uint32_t)config->voltSelect << PMC_LVDSC2_LVWV_SHIFT) | -#endif - ((uint32_t)config->enableInt << PMC_LVDSC2_LVWIE_SHIFT) - /* Clear the Low Voltage Warning Flag with previouse power detect setting */ - | PMC_LVDSC2_LVWACK_MASK); -} - -#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) -void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config) -{ - base->HVDSC1 = (((uint32_t)config->voltSelect << PMC_HVDSC1_HVDV_SHIFT) | - ((uint32_t)config->enableInt << PMC_HVDSC1_HVDIE_SHIFT) | - ((uint32_t)config->enableReset << PMC_HVDSC1_HVDRE_SHIFT) - /* Clear the High Voltage Detect Flag with previouse power detect setting */ - | PMC_HVDSC1_HVDACK_MASK); -} -#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ - -#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ - (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ - (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) -void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config) -{ - base->REGSC = (0U -#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) - | ((uint32_t)config->enable << PMC_REGSC_BGBE_SHIFT) -#endif /* FSL_FEATURE_PMC_HAS_BGBE */ -#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) - | (((uint32_t)config->enableInLowPowerMode << PMC_REGSC_BGEN_SHIFT)) -#endif /* FSL_FEATURE_PMC_HAS_BGEN */ -#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) - | ((uint32_t)config->drive << PMC_REGSC_BGBDS_SHIFT) -#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ - ); -} -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pmc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pmc.h deleted file mode 100644 index f39a22f..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_pmc.h +++ /dev/null @@ -1,421 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_PMC_H_ -#define _FSL_PMC_H_ - -#include "fsl_common.h" - -/*! @addtogroup pmc */ -/*! @{ */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief PMC driver version */ -#define FSL_PMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) -/*! - * @brief Low-Voltage Detect Voltage Select - */ -typedef enum _pmc_low_volt_detect_volt_select -{ - kPMC_LowVoltDetectLowTrip = 0U, /*!< Low trip point selected (VLVD = VLVDL )*/ - kPMC_LowVoltDetectHighTrip = 1U /*!< High trip point selected (VLVD = VLVDH )*/ -} pmc_low_volt_detect_volt_select_t; -#endif - -#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) -/*! - * @brief Low-Voltage Warning Voltage Select - */ -typedef enum _pmc_low_volt_warning_volt_select -{ - kPMC_LowVoltWarningLowTrip = 0U, /*!< Low trip point selected (VLVW = VLVW1)*/ - kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/ - kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/ - kPMC_LowVoltWarningHighTrip = 3U /*!< High trip point selected (VLVW = VLVW4)*/ -} pmc_low_volt_warning_volt_select_t; -#endif - -#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) -/*! - * @brief High-Voltage Detect Voltage Select - */ -typedef enum _pmc_high_volt_detect_volt_select -{ - kPMC_HighVoltDetectLowTrip = 0U, /*!< Low trip point selected (VHVD = VHVDL )*/ - kPMC_HighVoltDetectHighTrip = 1U /*!< High trip point selected (VHVD = VHVDH )*/ -} pmc_high_volt_detect_volt_select_t; -#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ - -#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) -/*! - * @brief Bandgap Buffer Drive Select. - */ -typedef enum _pmc_bandgap_buffer_drive_select -{ - kPMC_BandgapBufferDriveLow = 0U, /*!< Low drive. */ - kPMC_BandgapBufferDriveHigh = 1U /*!< High drive. */ -} pmc_bandgap_buffer_drive_select_t; -#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ - -#if (defined(FSL_FEATURE_PMC_HAS_VLPO) && FSL_FEATURE_PMC_HAS_VLPO) -/*! - * @brief VLPx Option - */ -typedef enum _pmc_vlp_freq_option -{ - kPMC_FreqRestrict = 0U, /*!< Frequency is restricted in VLPx mode. */ - kPMC_FreqUnrestrict = 1U /*!< Frequency is unrestricted in VLPx mode. */ -} pmc_vlp_freq_mode_t; -#endif /* FSL_FEATURE_PMC_HAS_VLPO */ - -#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) -/*! - @brief IP version ID definition. - */ -typedef struct _pmc_version_id -{ - uint16_t feature; /*!< Feature Specification Number. */ - uint8_t minor; /*!< Minor version number. */ - uint8_t major; /*!< Major version number. */ -} pmc_version_id_t; -#endif /* FSL_FEATURE_PMC_HAS_VERID */ - -#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) -/*! @brief IP parameter definition. */ -typedef struct _pmc_param -{ - bool vlpoEnable; /*!< VLPO enable. */ - bool hvdEnable; /*!< HVD enable. */ -} pmc_param_t; -#endif /* FSL_FEATURE_PMC_HAS_PARAM */ - -/*! - * @brief Low-Voltage Detect Configuration Structure - */ -typedef struct _pmc_low_volt_detect_config -{ - bool enableInt; /*!< Enable interrupt when low-voltage detect*/ - bool enableReset; /*!< Enable system reset when low-voltage detect*/ -#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) - pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low-voltage detect trip point voltage selection*/ -#endif -} pmc_low_volt_detect_config_t; - -/*! - * @brief Low-Voltage Warning Configuration Structure - */ -typedef struct _pmc_low_volt_warning_config -{ - bool enableInt; /*!< Enable interrupt when low-voltage warning*/ -#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) - pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low-voltage warning trip point voltage selection*/ -#endif -} pmc_low_volt_warning_config_t; - -#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) -/*! - * @brief High-Voltage Detect Configuration Structure - */ -typedef struct _pmc_high_volt_detect_config -{ - bool enableInt; /*!< Enable interrupt when high-voltage detect*/ - bool enableReset; /*!< Enable system reset when high-voltage detect*/ - pmc_high_volt_detect_volt_select_t voltSelect; /*!< High-voltage detect trip point voltage selection*/ -} pmc_high_volt_detect_config_t; -#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ - -#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ - (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ - (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) -/*! - * @brief Bandgap Buffer configuration. - */ -typedef struct _pmc_bandgap_buffer_config -{ -#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) - bool enable; /*!< Enable bandgap buffer. */ -#endif -#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) - bool enableInLowPowerMode; /*!< Enable bandgap buffer in low-power mode. */ -#endif /* FSL_FEATURE_PMC_HAS_BGEN */ -#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) - pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select. */ -#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ -} pmc_bandgap_buffer_config_t; -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name Power Management Controller Control APIs*/ -/*@{*/ - -#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) -/*! - * @brief Gets the PMC version ID. - * - * This function gets the PMC version ID, including major version number, - * minor version number and feature specification number. - * - * @param base PMC peripheral base address. - * @param versionId Pointer to version ID structure. - */ -static inline void PMC_GetVersionId(PMC_Type *base, pmc_version_id_t *versionId) -{ - *((uint32_t *)versionId) = base->VERID; -} -#endif /* FSL_FEATURE_PMC_HAS_VERID */ - -#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) -/*! - * @brief Gets the PMC parameter. - * - * This function gets the PMC parameter, including VLPO enable and HVD enable. - * - * @param base PMC peripheral base address. - * @param param Pointer to PMC param structure. - */ -void PMC_GetParam(PMC_Type *base, pmc_param_t *param); -#endif - -/*! - * @brief Configure the low-voltage detect setting. - * - * This function configures the low-voltage detect setting, including the trip - * point voltage setting, enable interrupt or not, enable system reset or not. - * - * @param base PMC peripheral base address. - * @param config Low-Voltage detect configuration structure. - */ -void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config); - -/*! - * @brief Get Low-Voltage Detect Flag status - * - * This function reads the current LVDF status. If it returns 1, a low-voltage event is detected. - * - * @param base PMC peripheral base address. - * @return Current low-voltage detect flag - * - true: Low-voltage detected - * - false: Low-voltage not detected - */ -static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base) -{ - return (bool)(base->LVDSC1 & PMC_LVDSC1_LVDF_MASK); -} - -/*! - * @brief Acknowledge to clear the Low-voltage Detect flag - * - * This function acknowledges the low-voltage detection errors (write 1 to - * clear LVDF). - * - * @param base PMC peripheral base address. - */ -static inline void PMC_ClearLowVoltDetectFlag(PMC_Type *base) -{ - base->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; -} - -/*! - * @brief Configure the low-voltage warning setting. - * - * This function configures the low-voltage warning setting, including the trip - * point voltage setting and enable interrupt or not. - * - * @param base PMC peripheral base address. - * @param config Low-Voltage warning configuration structure. - */ -void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config); - -/*! - * @brief Get Low-Voltage Warning Flag status - * - * This function polls the current LVWF status. When 1 is returned, it - * indicates a low-voltage warning event. LVWF is set when V Supply transitions - * below the trip point or after reset and V Supply is already below the V LVW. - * - * @param base PMC peripheral base address. - * @return Current LVWF status - * - true: Low-Voltage Warning Flag is set. - * - false: the Low-Voltage Warning does not happen. - */ -static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base) -{ - return (bool)(base->LVDSC2 & PMC_LVDSC2_LVWF_MASK); -} - -/*! - * @brief Acknowledge to Low-Voltage Warning flag - * - * This function acknowledges the low voltage warning errors (write 1 to - * clear LVWF). - * - * @param base PMC peripheral base address. - */ -static inline void PMC_ClearLowVoltWarningFlag(PMC_Type *base) -{ - base->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; -} - -#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) -/*! - * @brief Configure the high-voltage detect setting. - * - * This function configures the high-voltage detect setting, including the trip - * point voltage setting, enable interrupt or not, enable system reset or not. - * - * @param base PMC peripheral base address. - * @param config High-voltage detect configuration structure. - */ -void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config); - -/*! - * @brief Get High-Voltage Detect Flag status - * - * This function reads the current HVDF status. If it returns 1, a low - * voltage event is detected. - * - * @param base PMC peripheral base address. - * @return Current high-voltage detect flag - * - true: High-Voltage detected - * - false: High-Voltage not detected - */ -static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base) -{ - return (bool)(base->HVDSC1 & PMC_HVDSC1_HVDF_MASK); -} - -/*! - * @brief Acknowledge to clear the High-Voltage Detect flag - * - * This function acknowledges the high-voltage detection errors (write 1 to - * clear HVDF). - * - * @param base PMC peripheral base address. - */ -static inline void PMC_ClearHighVoltDetectFlag(PMC_Type *base) -{ - base->HVDSC1 |= PMC_HVDSC1_HVDACK_MASK; -} -#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ - -#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ - (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ - (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) -/*! - * @brief Configure the PMC bandgap - * - * This function configures the PMC bandgap, including the drive select and - * behavior in low-power mode. - * - * @param base PMC peripheral base address. - * @param config Pointer to the configuration structure - */ -void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config); -#endif - -#if (defined(FSL_FEATURE_PMC_HAS_ACKISO) && FSL_FEATURE_PMC_HAS_ACKISO) -/*! - * @brief Gets the acknowledge Peripherals and I/O pads isolation flag. - * - * This function reads the Acknowledge Isolation setting that indicates - * whether certain peripherals and the I/O pads are in a latched state as - * a result of having been in the VLLS mode. - * - * @param base PMC peripheral base address. - * @param base Base address for current PMC instance. - * @return ACK isolation - * 0 - Peripherals and I/O pads are in a normal run state. - * 1 - Certain peripherals and I/O pads are in an isolated and - * latched state. - */ -static inline bool PMC_GetPeriphIOIsolationFlag(PMC_Type *base) -{ - return (bool)(base->REGSC & PMC_REGSC_ACKISO_MASK); -} - -/*! - * @brief Acknowledge to Peripherals and I/O pads isolation flag. - * - * This function clears the ACK Isolation flag. Writing one to this setting - * when it is set releases the I/O pads and certain peripherals to their normal - * run mode state. - * - * @param base PMC peripheral base address. - */ -static inline void PMC_ClearPeriphIOIsolationFlag(PMC_Type *base) -{ - base->REGSC |= PMC_REGSC_ACKISO_MASK; -} -#endif /* FSL_FEATURE_PMC_HAS_ACKISO */ - -#if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS) -/*! - * @brief Gets the Regulator regulation status. - * - * This function returns the regulator to a run regulation status. It provides - * the current status of the internal voltage regulator. - * - * @param base PMC peripheral base address. - * @param base Base address for current PMC instance. - * @return Regulation status - * 0 - Regulator is in a stop regulation or in transition to/from the regulation. - * 1 - Regulator is in a run regulation. - * - */ -static inline bool PMC_IsRegulatorInRunRegulation(PMC_Type *base) -{ - return (bool)(base->REGSC & PMC_REGSC_REGONS_MASK); -} -#endif /* FSL_FEATURE_PMC_HAS_REGONS */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* _FSL_PMC_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_port.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_port.h deleted file mode 100644 index 935b032..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_port.h +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_PORT_H_ -#define _FSL_PORT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup port - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! Version 2.0.1. */ -#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief Internal resistor pull feature selection */ -enum _port_pull -{ - kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */ - kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */ - kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */ -}; - -/*! @brief Slew rate selection */ -enum _port_slew_rate -{ - kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */ - kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */ -}; - -#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN -/*! @brief Internal resistor pull feature enable/disable */ -enum _port_open_drain_enable -{ - kPORT_OpenDrainDisable = 0U, /*!< Internal pull-down resistor is disabled. */ - kPORT_OpenDrainEnable = 1U, /*!< Internal pull-up resistor is enabled. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ - -/*! @brief Passive filter feature enable/disable */ -enum _port_passive_filter_enable -{ - kPORT_PassiveFilterDisable = 0U, /*!< Fast slew rate is configured. */ - kPORT_PassiveFilterEnable = 1U, /*!< Slow slew rate is configured. */ -}; - -/*! @brief Configures the drive strength. */ -enum _port_drive_strength -{ - kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */ - kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */ -}; - -#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK -/*! @brief Unlock/lock the pin control register field[15:0] */ -enum _port_lock_register -{ - kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ - kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ - -/*! @brief Pin mux selection */ -typedef enum _port_mux -{ - kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */ - kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */ - kPORT_MuxAlt2 = 2U, /*!< Chip-specific */ - kPORT_MuxAlt3 = 3U, /*!< Chip-specific */ - kPORT_MuxAlt4 = 4U, /*!< Chip-specific */ - kPORT_MuxAlt5 = 5U, /*!< Chip-specific */ - kPORT_MuxAlt6 = 6U, /*!< Chip-specific */ - kPORT_MuxAlt7 = 7U, /*!< Chip-specific */ -} port_mux_t; - -/*! @brief Configures the interrupt generation condition. */ -typedef enum _port_interrupt -{ - kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ -#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST - kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ - kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ - kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ -#endif -#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG - kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ - kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ - kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ -#endif - kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ - kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ - kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ - kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ - kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ -#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER - kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ - kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ -#endif -} port_interrupt_t; - -#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER -/*! @brief Digital filter clock source selection */ -typedef enum _port_digital_filter_clock_source -{ - kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ - kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ -} port_digital_filter_clock_source_t; - -/*! @brief PORT digital filter feature configuration definition */ -typedef struct _port_digital_filter_config -{ - uint32_t digitalFilterWidth; /*!< Set digital filter width */ - port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ -} port_digital_filter_config_t; -#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ - -/*! @brief PORT pin configuration structure */ -typedef struct _port_pin_config -{ - uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */ - uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */ - uint16_t : 1; - uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */ -#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN - uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */ -#else - uint16_t : 1; -#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ - uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */ - uint16_t : 1; - uint16_t mux : 3; /*!< Pin mux Configure */ - uint16_t : 4; -#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK - uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */ -#else - uint16_t : 1; -#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ -} port_pin_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name Configuration */ -/*@{*/ - -/*! - * @brief Sets the port PCR register. - * - * This is an example to define an input pin or output pin PCR configuration: - * @code - * // Define a digital input pin PCR configuration - * port_pin_config_t config = { - * kPORT_PullUp, - * kPORT_FastSlewRate, - * kPORT_PassiveFilterDisable, - * kPORT_OpenDrainDisable, - * kPORT_LowDriveStrength, - * kPORT_MuxAsGpio, - * kPORT_UnLockRegister, - * }; - * @endcode - * - * @param base PORT peripheral base pointer. - * @param pin PORT pin number. - * @param config PORT PCR register configuration structure. - */ -static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) -{ - assert(config); - uint32_t addr = (uint32_t)&base->PCR[pin]; - *(volatile uint16_t *)(addr) = *((const uint16_t *)config); -} - -/*! - * @brief Sets the port PCR register for multiple pins. - * - * This is an example to define input pins or output pins PCR configuration: - * @code - * // Define a digital input pin PCR configuration - * port_pin_config_t config = { - * kPORT_PullUp , - * kPORT_PullEnable, - * kPORT_FastSlewRate, - * kPORT_PassiveFilterDisable, - * kPORT_OpenDrainDisable, - * kPORT_LowDriveStrength, - * kPORT_MuxAsGpio, - * kPORT_UnlockRegister, - * }; - * @endcode - * - * @param base PORT peripheral base pointer. - * @param mask PORT pin number macro. - * @param config PORT PCR register configuration structure. - */ -static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) -{ - assert(config); - - uint16_t pcrl = *((const uint16_t *)config); - - if (mask & 0xffffU) - { - base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; - } - if (mask >> 16) - { - base->GPCHR = (mask & 0xffff0000U) | pcrl; - } -} - -/*! - * @brief Configures the pin muxing. - * - * @param base PORT peripheral base pointer. - * @param pin PORT pin number. - * @param mux pin muxing slot selection. - * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. - * - #kPORT_MuxAsGpio : Set as GPIO. - * - #kPORT_MuxAlt2 : chip-specific. - * - #kPORT_MuxAlt3 : chip-specific. - * - #kPORT_MuxAlt4 : chip-specific. - * - #kPORT_MuxAlt5 : chip-specific. - * - #kPORT_MuxAlt6 : chip-specific. - * - #kPORT_MuxAlt7 : chip-specific. - * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because - * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is - * reset to zero : kPORT_PinDisabledOrAnalog). - * This function is recommended to use to reset the pin mux - * - */ -static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) -{ - base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); -} - -#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER - -/*! - * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. - * - * @param base PORT peripheral base pointer. - * @param mask PORT pin number macro. - */ -static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) -{ - if (enable == true) - { - base->DFER |= mask; - } - else - { - base->DFER &= ~mask; - } -} - -/*! - * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. - * - * @param base PORT peripheral base pointer. - * @param config PORT digital filter configuration structure. - */ -static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) -{ - assert(config); - - base->DFCR = PORT_DFCR_CS(config->clockSource); - base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); -} - -#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ - -/*@}*/ - -/*! @name Interrupt */ -/*@{*/ - -/*! - * @brief Configures the port pin interrupt/DMA request. - * - * @param base PORT peripheral base pointer. - * @param pin PORT pin number. - * @param config PORT pin interrupt configuration. - * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. - * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). - * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). - * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). - * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). - * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). - * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). - * - #kPORT_InterruptLogicZero : Interrupt when logic zero. - * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. - * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. - * - #kPORT_InterruptEitherEdge : Interrupt on either edge. - * - #kPORT_InterruptLogicOne : Interrupt when logic one. - * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). - * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). - */ -static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) -{ - base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); -} - -/*! - * @brief Reads the whole port status flag. - * - * If a pin is configured to generate the DMA request, the corresponding flag - * is cleared automatically at the completion of the requested DMA transfer. - * Otherwise, the flag remains set until a logic one is written to that flag. - * If configured for a level sensitive interrupt that remains asserted, the flag - * is set again immediately. - * - * @param base PORT peripheral base pointer. - * @return Current port interrupt status flags, for example, 0x00010001 means the - * pin 0 and 17 have the interrupt. - */ -static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) -{ - return base->ISFR; -} - -/*! - * @brief Clears the multiple pin interrupt status flag. - * - * @param base PORT peripheral base pointer. - * @param mask PORT pin number macro. - */ -static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) -{ - base->ISFR = mask; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PORT_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rcm.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rcm.c deleted file mode 100644 index 9cf7479..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rcm.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rcm.h" - -void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config) -{ - assert(config); - -#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) - uint32_t reg; - - reg = (((uint32_t)config->enableFilterInStop << RCM_RPC_RSTFLTSS_SHIFT) | (uint32_t)config->filterInRunWait); - if (config->filterInRunWait == kRCM_FilterBusClock) - { - reg |= ((uint32_t)config->busClockFilterCount << RCM_RPC_RSTFLTSEL_SHIFT); - } - base->RPC = reg; -#else - base->RPFC = ((uint8_t)(config->enableFilterInStop << RCM_RPFC_RSTFLTSS_SHIFT) | (uint8_t)config->filterInRunWait); - if (config->filterInRunWait == kRCM_FilterBusClock) - { - base->RPFW = config->busClockFilterCount; - } -#endif /* FSL_FEATURE_RCM_REG_WIDTH */ -} - -#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) -void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config) -{ - uint32_t reg; - - reg = base->FM; - reg &= ~RCM_FM_FORCEROM_MASK; - reg |= ((uint32_t)config << RCM_FM_FORCEROM_SHIFT); - base->FM = reg; -} -#endif /* #if FSL_FEATURE_RCM_HAS_BOOTROM */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rcm.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rcm.h deleted file mode 100644 index fbc5169..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rcm.h +++ /dev/null @@ -1,431 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_RCM_H_ -#define _FSL_RCM_H_ - -#include "fsl_common.h" - -/*! @addtogroup rcm */ -/*! @{*/ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief RCM driver version 2.0.1. */ -#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief System Reset Source Name definitions - */ -typedef enum _rcm_reset_source -{ -#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) -/* RCM register bit width is 32. */ -#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) - kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ -#endif - kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< Low-voltage detect reset */ -#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) - kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */ -#endif /* FSL_FEATURE_RCM_HAS_LOC */ -#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) - kRCM_SourceLol = RCM_SRS_LOL_MASK, /*!< Loss of lock reset */ -#endif /* FSL_FEATURE_RCM_HAS_LOL */ - kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */ - kRCM_SourcePin = RCM_SRS_PIN_MASK, /*!< External pin reset */ - kRCM_SourcePor = RCM_SRS_POR_MASK, /*!< Power on reset */ -#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) - kRCM_SourceJtag = RCM_SRS_JTAG_MASK, /*!< JTAG generated reset */ -#endif /* FSL_FEATURE_RCM_HAS_JTAG */ - kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */ - kRCM_SourceSw = RCM_SRS_SW_MASK, /*!< Software reset */ -#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) - kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */ -#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ -#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) - kRCM_SourceEzpt = RCM_SRS_EZPT_MASK, /*!< EzPort reset */ -#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ - kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */ - -#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ -/* RCM register bit width is 8. */ -#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) - kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ -#endif - kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< Low-voltage detect reset */ -#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) - kRCM_SourceLoc = RCM_SRS0_LOC_MASK, /*!< Loss of clock reset */ -#endif /* FSL_FEATURE_RCM_HAS_LOC */ -#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) - kRCM_SourceLol = RCM_SRS0_LOL_MASK, /*!< Loss of lock reset */ -#endif /* FSL_FEATURE_RCM_HAS_LOL */ - kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */ - kRCM_SourcePin = RCM_SRS0_PIN_MASK, /*!< External pin reset */ - kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */ -#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) - kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */ -#endif /* FSL_FEATURE_RCM_HAS_JTAG */ - kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */ - kRCM_SourceSw = RCM_SRS1_SW_MASK << 8U, /*!< Software reset */ -#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) - kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset */ -#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ -#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) - kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */ -#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ - kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */ -#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ - kRCM_SourceAll = 0xffffffffU, -} rcm_reset_source_t; - -/*! - * @brief Reset pin filter select in Run and Wait modes - */ -typedef enum _rcm_run_wait_filter_mode -{ - kRCM_FilterDisable = 0U, /*!< All filtering disabled */ - kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */ - kRCM_FilterLpoClock = 2U /*!< LPO clock filter enabled */ -} rcm_run_wait_filter_mode_t; - -#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) -/*! - * @brief Boot from ROM configuration. - */ -typedef enum _rcm_boot_rom_config -{ - kRCM_BootFlash = 0U, /*!< Boot from flash */ - kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */ - kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */ - kRCM_BootRomBoth = 3U /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */ -} rcm_boot_rom_config_t; -#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ - -#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) -/*! - * @brief Max delay time from interrupt asserts to system reset. - */ -typedef enum _rcm_reset_delay -{ - kRCM_ResetDelay8Lpo = 0U, /*!< Delay 8 LPO cycles. */ - kRCM_ResetDelay32Lpo = 1U, /*!< Delay 32 LPO cycles. */ - kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */ - kRCM_ResetDelay512Lpo = 3U /*!< Delay 512 LPO cycles. */ -} rcm_reset_delay_t; - -/*! - * @brief System reset interrupt enable bit definitions. - */ -typedef enum _rcm_interrupt_enable -{ - kRCM_IntNone = 0U, /*!< No interrupt enabled. */ - kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK, /*!< Loss of clock interrupt. */ - kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK, /*!< Loss of lock interrupt. */ - kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK, /*!< Watch dog interrupt. */ - kRCM_IntExternalPin = RCM_SRIE_PIN_MASK, /*!< External pin interrupt. */ - kRCM_IntGlobal = RCM_SRIE_GIE_MASK, /*!< Global interrupts. */ - kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK, /*!< Core lock up interrupt */ - kRCM_IntSoftware = RCM_SRIE_SW_MASK, /*!< software interrupt */ - kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt. */ -#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) - kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt. */ -#endif - kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts. */ - | - RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK | - RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK -#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) - | - RCM_SRIE_CORE1_MASK -#endif -} rcm_interrupt_enable_t; -#endif /* FSL_FEATURE_RCM_HAS_SRIE */ - -#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) -/*! - * @brief IP version ID definition. - */ -typedef struct _rcm_version_id -{ - uint16_t feature; /*!< Feature Specification Number. */ - uint8_t minor; /*!< Minor version number. */ - uint8_t major; /*!< Major version number. */ -} rcm_version_id_t; -#endif - -/*! - * @brief Reset pin filter configuration - */ -typedef struct _rcm_reset_pin_filter_config -{ - bool enableFilterInStop; /*!< Reset pin filter select in stop mode. */ - rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */ - uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */ -} rcm_reset_pin_filter_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name Reset Control Module APIs*/ -/*@{*/ - -#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) -/*! - * @brief Gets the RCM version ID. - * - * This function gets the RCM version ID including the major version number, - * the minor version number, and the feature specification number. - * - * @param base RCM peripheral base address. - * @param versionId Pointer to version ID structure. - */ -static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId) -{ - *((uint32_t *)versionId) = base->VERID; -} -#endif - -#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) -/*! - * @brief Gets the reset source implemented status. - * - * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented. - * Use source masks defined in the rcm_reset_source_t to get the desired source status. - * - * Example: - @code - uint32_t status; - - // To test whether the MCU is reset using Watchdog. - status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); - @endcode - * - * @param base RCM peripheral base address. - * @return All reset source implemented status bit map. - */ -static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base) -{ - return base->PARAM; -} -#endif /* FSL_FEATURE_RCM_HAS_PARAM */ - -/*! - * @brief Gets the reset source status which caused a previous reset. - * - * This function gets the current reset source status. Use source masks - * defined in the rcm_reset_source_t to get the desired source status. - * - * Example: - @code - uint32_t resetStatus; - - // To get all reset source statuses. - resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll; - - // To test whether the MCU is reset using Watchdog. - resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog; - - // To test multiple reset sources. - resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); - @endcode - * - * @param base RCM peripheral base address. - * @return All reset source status bit map. - */ -static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base) -{ -#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) - return base->SRS; -#else - return (uint32_t)((uint32_t)base->SRS0 | ((uint32_t)base->SRS1 << 8U)); -#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ -} - -#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS) -/*! - * @brief Gets the sticky reset source status. - * - * This function gets the current reset source status that has not been cleared - * by software for some specific source. - * - * Example: - @code - uint32_t resetStatus; - - // To get all reset source statuses. - resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll; - - // To test whether the MCU is reset using Watchdog. - resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog; - - // To test multiple reset sources. - resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); - @endcode - * - * @param base RCM peripheral base address. - * @return All reset source status bit map. - */ -static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base) -{ -#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) - return base->SSRS; -#else - return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U)); -#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ -} - -/*! - * @brief Clears the sticky reset source status. - * - * This function clears the sticky system reset flags indicated by source masks. - * - * Example: - @code - // Clears multiple reset sources. - RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin); - @endcode - * - * @param base RCM peripheral base address. - * @param sourceMasks reset source status bit map - */ -static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks) -{ -#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) - base->SSRS = sourceMasks; -#else - base->SSRS0 = (sourceMasks & 0xffU); - base->SSRS1 = ((sourceMasks >> 8U) & 0xffU); -#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ -} -#endif /* FSL_FEATURE_RCM_HAS_SSRS */ - -/*! - * @brief Configures the reset pin filter. - * - * This function sets the reset pin filter including the filter source, filter - * width, and so on. - * - * @param base RCM peripheral base address. - * @param config Pointer to the configuration structure. - */ -void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config); - -#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS) -/*! - * @brief Gets the EZP_MS_B pin assert status. - * - * This function gets the easy port mode status (EZP_MS_B) pin assert status. - * - * @param base RCM peripheral base address. - * @return status true - asserted, false - reasserted - */ -static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base) -{ - return (bool)(base->MR & RCM_MR_EZP_MS_MASK); -} -#endif /* FSL_FEATURE_RCM_HAS_EZPMS */ - -#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) -/*! - * @brief Gets the ROM boot source. - * - * This function gets the ROM boot source during the last chip reset. - * - * @param base RCM peripheral base address. - * @return The ROM boot source. - */ -static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base) -{ - return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT); -} - -/*! - * @brief Clears the ROM boot source flag. - * - * This function clears the ROM boot source flag. - * - * @param base Register base address of RCM - */ -static inline void RCM_ClearBootRomSource(RCM_Type *base) -{ - base->MR |= RCM_MR_BOOTROM_MASK; -} - -/*! - * @brief Forces the boot from ROM. - * - * This function forces booting from ROM during all subsequent system resets. - * - * @param base RCM peripheral base address. - * @param config Boot configuration. - */ -void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config); -#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ - -#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) -/*! - * @brief Sets the system reset interrupt configuration. - * - * For a graceful shut down, the RCM supports delaying the assertion of the system - * reset for a period of time when the reset interrupt is generated. This function - * can be used to enable the interrupt and the delay period. The interrupts - * are passed in as bit mask. See rcm_int_t for details. For example, to - * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs, - * configure as follows: - * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo); - * - * @param base RCM peripheral base address. - * @param intMask Bit mask of the system reset interrupts to enable. See - * rcm_interrupt_enable_t for details. - * @param Delay Bit mask of the system reset interrupts to enable. - */ -static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay) -{ - base->SRIE = (intMask | delay); -} -#endif /* FSL_FEATURE_RCM_HAS_SRIE */ -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* _FSL_RCM_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rnga.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rnga.c deleted file mode 100644 index 9be2749..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rnga.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rnga.h" - -#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/******************************************************************************* - * RNG_CR - RNGA Control Register - ******************************************************************************/ -/*! - * @brief RNG_CR - RNGA Control Register (RW) - * - * Reset value: 0x00000000U - * - * Controls the operation of RNGA. - */ -/*! - * @name Constants and macros for entire RNG_CR register - */ -/*@{*/ -#define RNG_CR_REG(base) ((base)->CR) -#define RNG_RD_CR(base) (RNG_CR_REG(base)) -#define RNG_WR_CR(base, value) (RNG_CR_REG(base) = (value)) -#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register RNG_CR, field GO[0] (RW) - * - * Specifies whether random-data generation and loading (into OR[RANDOUT]) is - * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading - * OR[RANDOUT] with data. - * - * Values: - * - 0b0 - Disabled - * - 0b1 - Enabled - */ -/*@{*/ -/*! @brief Read current value of the RNG_CR_GO field. */ -#define RNG_RD_CR_GO(base) ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT) - -/*! @brief Set the GO field to a new value. */ -#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value))) -/*@}*/ - -/*! - * @name Register RNG_CR, field SLP[4] (RW) - * - * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep - * mode by asserting the DOZE signal. - * - * Values: - * - 0b0 - Normal mode - * - 0b1 - Sleep (low-power) mode - */ -/*@{*/ -/*! @brief Read current value of the RNG_CR_SLP field. */ -#define RNG_RD_CR_SLP(base) ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT) - -/*! @brief Set the SLP field to a new value. */ -#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value))) -/*@}*/ - -/******************************************************************************* - * RNG_SR - RNGA Status Register - ******************************************************************************/ -#define RNG_SR_REG(base) ((base)->SR) - -/*! - * @name Register RNG_SR, field OREG_LVL[15:8] (RO) - * - * Indicates the number of random-data words that are in OR[RANDOUT], which - * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL] - * is not 0, then the contents of a random number contained in OR[RANDOUT] are - * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. - * - * Values: - * - 0b00000000 - No words (empty) - * - 0b00000001 - One word (valid) - */ -/*@{*/ -/*! @brief Read current value of the RNG_SR_OREG_LVL field. */ -#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT) -/*@}*/ - -/*! - * @name Register RNG_SR, field SLP[4] (RO) - * - * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep - * mode by asserting the DOZE signal. - * - * Values: - * - 0b0 - Normal mode - * - 0b1 - Sleep (low-power) mode - */ -/*@{*/ -/*! @brief Read current value of the RNG_SR_SLP field. */ -#define RNG_RD_SR_SLP(base) ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT) -/*@}*/ - -/******************************************************************************* - * RNG_OR - RNGA Output Register - ******************************************************************************/ -/*! - * @brief RNG_OR - RNGA Output Register (RO) - * - * Reset value: 0x00000000U - * - * Stores a random-data word generated by RNGA. - */ -/*! - * @name Constants and macros for entire RNG_OR register - */ -/*@{*/ -#define RNG_OR_REG(base) ((base)->OR) -#define RNG_RD_OR(base) (RNG_OR_REG(base)) -/*@}*/ - -/******************************************************************************* - * RNG_ER - RNGA Entropy Register - ******************************************************************************/ -/*! - * @brief RNG_ER - RNGA Entropy Register (WORZ) - * - * Reset value: 0x00000000U - * - * Specifies an entropy value that RNGA uses in addition to its ring oscillators - * to seed its pseudorandom algorithm. This is a write-only register; reads - * return all zeros. - */ -/*! - * @name Constants and macros for entire RNG_ER register - */ -/*@{*/ -#define RNG_ER_REG(base) ((base)->ER) -#define RNG_RD_ER(base) (RNG_ER_REG(base)) -#define RNG_WR_ER(base, value) (RNG_ER_REG(base) = (value)) -/*@}*/ - -/******************************************************************************* - * Prototypes - *******************************************************************************/ - -static uint32_t rnga_ReadEntropy(RNG_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -void RNGA_Init(RNG_Type *base) -{ - /* Enable the clock gate. */ - CLOCK_EnableClock(kCLOCK_Rnga0); - CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */ - CLOCK_EnableClock(kCLOCK_Rnga0); - - /* Reset the registers for RNGA module to reset state. */ - RNG_WR_CR(base, 0); - /* Enables the RNGA random data generation and loading.*/ - RNG_WR_CR_GO(base, 1); -} - -void RNGA_Deinit(RNG_Type *base) -{ - /* Disable the clock for RNGA module.*/ - CLOCK_DisableClock(kCLOCK_Rnga0); -} - -/*! - * @brief Get a random data from RNGA. - * - * @param base RNGA base address - */ -static uint32_t rnga_ReadEntropy(RNG_Type *base) -{ - uint32_t data = 0; - if (RNGA_GetMode(base) == kRNGA_ModeNormal) /* Is in normal mode.*/ - { - /* Wait for valid random-data.*/ - while (RNG_RD_SR_OREG_LVL(base) == 0) - { - } - data = RNG_RD_OR(base); - } - /* Get random-data word generated by RNGA.*/ - return data; -} - -status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size) -{ - status_t result = kStatus_Success; - uint32_t random_32; - uint8_t *random_p; - uint32_t random_size; - uint8_t *data_p = (uint8_t *)data; - uint32_t i; - - /* Check input parameters.*/ - if (base && data && data_size) - { - do - { - /* Read Entropy.*/ - random_32 = rnga_ReadEntropy(base); - - random_p = (uint8_t *)&random_32; - - if (data_size < sizeof(random_32)) - { - random_size = data_size; - } - else - { - random_size = sizeof(random_32); - } - - for (i = 0; i < random_size; i++) - { - *data_p++ = *random_p++; - } - - data_size -= random_size; - } while (data_size > 0); - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode) -{ - RNG_WR_CR_SLP(base, (uint32_t)mode); -} - -rnga_mode_t RNGA_GetMode(RNG_Type *base) -{ - return (rnga_mode_t)RNG_RD_SR_SLP(base); -} - -void RNGA_Seed(RNG_Type *base, uint32_t seed) -{ - /* Write to RNGA Entropy Register.*/ - RNG_WR_ER(base, seed); -} - -#endif /* FSL_FEATURE_SOC_RNG_COUNT */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rnga.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rnga.h deleted file mode 100644 index 31ecda7..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rnga.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_RNGA_DRIVER_H_ -#define _FSL_RNGA_DRIVER_H_ - -#include "fsl_common.h" - -#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT -/*! - * @addtogroup rnga - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief RNGA driver version 2.0.1. */ -#define FSL_RNGA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief RNGA working mode */ -typedef enum _rnga_mode -{ - kRNGA_ModeNormal = 0U, /*!< Normal Mode. The ring-oscillator clocks are active; RNGA generates entropy - (randomness) from the clocks and stores it in shift registers.*/ - kRNGA_ModeSleep = 1U, /*!< Sleep Mode. The ring-oscillator clocks are inactive; RNGA does not generate entropy.*/ -} rnga_mode_t; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the RNGA. - * - * This function initializes the RNGA. - * When called, the RNGA entropy generation starts immediately. - * - * @param base RNGA base address - */ -void RNGA_Init(RNG_Type *base); - -/*! - * @brief Shuts down the RNGA. - * - * This function shuts down the RNGA. - * - * @param base RNGA base address - */ -void RNGA_Deinit(RNG_Type *base); - -/*! - * @brief Gets random data. - * - * This function gets random data from the RNGA. - * - * @param base RNGA base address - * @param data pointer to user buffer to be filled by random data - * @param data_size size of data in bytes - * @return RNGA status - */ -status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size); - -/*! - * @brief Feeds the RNGA module. - * - * This function inputs an entropy value that the RNGA uses to seed its - * pseudo-random algorithm. - * - * @param base RNGA base address - * @param seed input seed value - */ -void RNGA_Seed(RNG_Type *base, uint32_t seed); - -/*! - * @brief Sets the RNGA in normal mode or sleep mode. - * - * This function sets the RNGA in sleep mode or normal mode. - * - * @param base RNGA base address - * @param mode normal mode or sleep mode - */ -void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode); - -/*! - * @brief Gets the RNGA working mode. - * - * This function gets the RNGA working mode. - * - * @param base RNGA base address - * @return normal mode or sleep mode - */ -rnga_mode_t RNGA_GetMode(RNG_Type *base); - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* FSL_FEATURE_SOC_RNG_COUNT */ -#endif /* _FSL_RNGA_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rtc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rtc.c deleted file mode 100644 index db6a2fa..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rtc.c +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Checks whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += ((datetime->year / 4) - (1970U / 4)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += (datetime->day - 1); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t x; - uint32_t secondsRemaining, days; - uint16_t daysInYear; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = secondsRemaining / 60U; - datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if (datetime->year & 3U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1; - } - } - - /* Adjust the days in February for a leap year */ - if (!(datetime->year & 3U)) - { - daysPerMonth[2] = 29U; - } - - for (x = 1U; x <= 12U; x++) - { - if (days <= daysPerMonth[x]) - { - datetime->month = x; - break; - } - else - { - days -= daysPerMonth[x]; - } - } - - datetime->day = days; -} - -void RTC_Init(RTC_Type *base, const rtc_config_t *config) -{ - assert(config); - - uint32_t reg; - - CLOCK_EnableClock(kCLOCK_Rtc0); - - /* Issue a software reset if timer is invalid */ - if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag) - { - RTC_Reset(RTC); - } - - reg = base->CR; - /* Setup the update mode and supervisor access mode */ - reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK); - reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess); -#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION - /* Setup the wakeup pin select */ - reg &= ~(RTC_CR_WPS_MASK); - reg |= RTC_CR_WPS(config->wakeupSelect); -#endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */ - base->CR = reg; - - /* Configure the RTC time compensation register */ - base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime)); -} - -void RTC_GetDefaultConfig(rtc_config_t *config) -{ - assert(config); - - /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */ - config->wakeupSelect = false; - /* Registers cannot be written when locked */ - config->updateMode = false; - /* Non-supervisor mode write accesses are not supported and will generate a bus error */ - config->supervisorAccess = false; - /* Compensation interval used by the crystal compensation logic */ - config->compensationInterval = 0; - /* Compensation time used by the crystal compensation logic */ - config->compensationTime = 0; -} - -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Return error if the time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - base->TSR = RTC_ConvertDatetimeToSeconds(datetime); - - return kStatus_Success; -} - -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0; - - seconds = base->TSR; - RTC_ConvertSecondsToDatetime(seconds, datetime); -} - -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) -{ - assert(alarmTime); - - uint32_t alarmSeconds = 0; - uint32_t currSeconds = 0; - - /* Return error if the alarm time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); - - /* Get the current time */ - currSeconds = base->TSR; - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* Set alarm in seconds*/ - base->TAR = alarmSeconds; - - return kStatus_Success; -} - -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0; - - /* Get alarm in seconds */ - alarmSeconds = base->TAR; - - RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); -} - -void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - /* The alarm flag is cleared by writing to the TAR register */ - if (mask & kRTC_AlarmFlag) - { - base->TAR = 0U; - } - - /* The timer overflow flag is cleared by initializing the TSR register. - * The time counter should be disabled for this write to be successful - */ - if (mask & kRTC_TimeOverflowFlag) - { - base->TSR = 1U; - } - - /* The timer overflow flag is cleared by initializing the TSR register. - * The time counter should be disabled for this write to be successful - */ - if (mask & kRTC_TimeInvalidFlag) - { - base->TSR = 1U; - } -} - -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - -void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter) -{ - assert(counter); - - *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR)); -} - -void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter) -{ - /* Prepare to initialize the register with the new value written */ - base->MER &= ~RTC_MER_MCE_MASK; - - base->MCHR = (uint32_t)((counter) >> 32); - base->MCLR = (uint32_t)(counter); -} - -status_t RTC_IncrementMonotonicCounter(RTC_Type *base) -{ - if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK)) - { - return kStatus_Fail; - } - - /* Prepare to switch to increment mode */ - base->MER |= RTC_MER_MCE_MASK; - /* Write anything so the counter increments*/ - base->MCLR = 1U; - - return kStatus_Success; -} - -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rtc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rtc.h deleted file mode 100644 index 4357c2e..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_rtc.h +++ /dev/null @@ -1,412 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_RTC_H_ -#define _FSL_RTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtc - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of RTC interrupts */ -typedef enum _rtc_interrupt_enable -{ - kRTC_TimeInvalidInterruptEnable = RTC_IER_TIIE_MASK, /*!< Time invalid interrupt.*/ - kRTC_TimeOverflowInterruptEnable = RTC_IER_TOIE_MASK, /*!< Time overflow interrupt.*/ - kRTC_AlarmInterruptEnable = RTC_IER_TAIE_MASK, /*!< Alarm interrupt.*/ - kRTC_SecondsInterruptEnable = RTC_IER_TSIE_MASK /*!< Seconds interrupt.*/ -} rtc_interrupt_enable_t; - -/*! @brief List of RTC flags */ -typedef enum _rtc_status_flags -{ - kRTC_TimeInvalidFlag = RTC_SR_TIF_MASK, /*!< Time invalid flag */ - kRTC_TimeOverflowFlag = RTC_SR_TOF_MASK, /*!< Time overflow flag */ - kRTC_AlarmFlag = RTC_SR_TAF_MASK /*!< Alarm flag*/ -} rtc_status_flags_t; - -#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP) - -/*! @brief List of RTC Oscillator capacitor load settings */ -typedef enum _rtc_osc_cap_load -{ - kRTC_Capacitor_2p = RTC_CR_SC2P_MASK, /*!< 2pF capacitor load */ - kRTC_Capacitor_4p = RTC_CR_SC4P_MASK, /*!< 4pF capacitor load */ - kRTC_Capacitor_8p = RTC_CR_SC8P_MASK, /*!< 8pF capacitor load */ - kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16pF capacitor load */ -} rtc_osc_cap_load_t; - -#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */ - -/*! @brief Structure is used to hold the date and time */ -typedef struct _rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -/*! - * @brief RTC config structure - * - * This structure holds the configuration settings for the RTC peripheral. To initialize this - * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _rtc_config -{ - bool wakeupSelect; /*!< true: Wakeup pin outputs the 32 KHz clock; - false:Wakeup pin used to wakeup the chip */ - bool updateMode; /*!< true: Registers can be written even when locked under certain - conditions, false: No writes allowed when registers are locked */ - bool supervisorAccess; /*!< true: Non-supervisor accesses are allowed; - false: Non-supervisor accesses are not supported */ - uint32_t compensationInterval; /*!< Compensation interval that is written to the CIR field in RTC TCR Register */ - uint32_t compensationTime; /*!< Compensation time that is written to the TCR field in RTC TCR Register */ -} rtc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the RTC clock and configures the peripheral for basic operation. - * - * This function will issue a software reset if the timer invalid flag is set. - * - * @note This API should be called at the beginning of the application using the RTC driver. - * - * @param base RTC peripheral base address - * @param config Pointer to user's RTC config structure. - */ -void RTC_Init(RTC_Type *base, const rtc_config_t *config); - -/*! - * @brief Stop the timer and gate the RTC clock - * - * @param base RTC peripheral base address - */ -static inline void RTC_Deinit(RTC_Type *base) -{ - /* Stop the RTC timer */ - base->SR &= ~RTC_SR_TCE_MASK; - - /* Gate the module clock */ - CLOCK_DisableClock(kCLOCK_Rtc0); -} - -/*! - * @brief Fill in the RTC config struct with the default settings - * - * The default values are: - * @code - * config->wakeupSelect = false; - * config->updateMode = false; - * config->supervisorAccess = false; - * config->compensationInterval = 0; - * config->compensationTime = 0; - * @endcode - * @param config Pointer to user's RTC config structure. - */ -void RTC_GetDefaultConfig(rtc_config_t *config); - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Sets the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details to set are stored - * - * @return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); - -/*! - * @brief Gets the RTC time and stores it in the given time structure. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); - -/*! - * @brief Sets the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); - -/*! - * @brief Returns the RTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - base->IER |= mask; -} - -/*! - * @brief Disables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - base->IER &= ~mask; -} - -/*! - * @brief Gets the enabled RTC interrupts. - * - * @param base RTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - return (base->IER & (RTC_IER_TIIE_MASK | RTC_IER_TOIE_MASK | RTC_IER_TAIE_MASK | RTC_IER_TSIE_MASK)); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the RTC status flags - * - * @param base RTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - return (base->SR & (RTC_SR_TIF_MASK | RTC_SR_TOF_MASK | RTC_SR_TAF_MASK)); -} - -/*! - * @brief Clears the RTC status flags. - * - * @param base RTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask); - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the RTC time counter. - * - * After calling this function, the timer counter increments once a second provided SR[TOF] or - * SR[TIF] are not set. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StartTimer(RTC_Type *base) -{ - base->SR |= RTC_SR_TCE_MASK; -} - -/*! - * @brief Stops the RTC time counter. - * - * RTC's seconds register can be written to only when the timer is stopped. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StopTimer(RTC_Type *base) -{ - base->SR &= ~RTC_SR_TCE_MASK; -} - -/*! @}*/ - -#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP) - -/*! - * @brief This function sets the specified capacitor configuration for the RTC oscillator. - * - * @param base RTC peripheral base address - * @param capLoad Oscillator loads to enable. This is a logical OR of members of the - * enumeration ::rtc_osc_cap_load_t - */ -static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad) -{ - uint32_t reg = base->CR; - - reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK); - reg |= capLoad; - - base->CR = reg; -} - -#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */ - -/*! - * @brief Performs a software reset on the RTC module. - * - * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR - * registers. The SWR bit is cleared by software explicitly clearing it. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Reset(RTC_Type *base) -{ - base->CR |= RTC_CR_SWR_MASK; - base->CR &= ~RTC_CR_SWR_MASK; - - /* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being set in the SR register */ - base->TSR = 1U; -} - -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - -/*! - * @name Monotonic counter functions - * @{ - */ - -/*! - * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns - * them as a single value. - * - * @param base RTC peripheral base address - * @param counter Pointer to variable where the value is stored. - */ -void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter); - -/*! - * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing - * the given single value. - * - * @param base RTC peripheral base address - * @param counter Counter value - */ -void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter); - -/*! - * @brief Increments the Monotonic Counter by one. - * - * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting - * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the - * monotonic counter low that causes it to overflow also increments the monotonic counter high. - * - * @param base RTC peripheral base address - * - * @return kStatus_Success: success - * kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found - */ -status_t RTC_IncrementMonotonicCounter(RTC_Type *base); - -/*! @}*/ - -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RTC_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c deleted file mode 100644 index c38165e..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c +++ /dev/null @@ -1,1066 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sai.h" - -/******************************************************************************* - * Definitations - ******************************************************************************/ -enum _sai_transfer_state -{ - kSAI_Busy = 0x0U, /*!< SAI is busy */ - kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ -}; - -/*! @brief Typedef for sai tx interrupt handler. */ -typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); - -/*! @brief Typedef for sai rx interrupt handler. */ -typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - -/*! - * @brief Set the master clock divider. - * - * This API will compute the master clock divider according to master clock frequency and master - * clock source clock source frequency. - * - * @param base SAI base pointer. - * @param mclk_Hz Mater clock frequency in Hz. - * @param mclkSrcClock_Hz Master clock source frequency in Hz. - */ -static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz); -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - -/*! - * @brief Get the instance number for SAI. - * - * @param base SAI base pointer. - */ -uint32_t SAI_GetInstance(I2S_Type *base); - -/*! - * @brief sends a piece of data in non-blocking way. - * - * @param base SAI base pointer - * @param channel Data channel used. - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param buffer Pointer to the data to be written. - * @param size Bytes to be written. - */ -static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); - -/*! - * @brief Receive a piece of data in non-blocking way. - * - * @param base SAI base pointer - * @param channel Data channel used. - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param buffer Pointer to the data to be read. - * @param size Bytes to be read. - */ -static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); -/******************************************************************************* - * Variables - ******************************************************************************/ -/*!@brief SAI handle pointer */ -sai_handle_t *s_saiHandle[FSL_FEATURE_SOC_I2S_COUNT][2]; -/* Base pointer array */ -static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; -/* IRQ number array */ -static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; -static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; -/* Clock name array */ -static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; -/*! @brief Pointer to tx IRQ handler for each instance. */ -static sai_tx_isr_t s_saiTxIsr; -/*! @brief Pointer to tx IRQ handler for each instance. */ -static sai_rx_isr_t s_saiRxIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) -static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz) -{ - uint32_t freq = mclkSrcClock_Hz; - uint16_t fract, divide; - uint32_t remaind = 0; - uint32_t current_remainder = 0xFFFFFFFFU; - uint16_t current_fract = 0; - uint16_t current_divide = 0; - uint32_t mul_freq = 0; - uint32_t max_fract = 256; - - /*In order to prevent overflow */ - freq /= 100; - mclk_Hz /= 100; - - /* Compute the max fract number */ - max_fract = mclk_Hz * 4096 / freq + 1; - if (max_fract > 256) - { - max_fract = 256; - } - - /* Looking for the closet frequency */ - for (fract = 1; fract < max_fract; fract++) - { - mul_freq = freq * fract; - remaind = mul_freq % mclk_Hz; - divide = mul_freq / mclk_Hz; - - /* Find the exactly frequency */ - if (remaind == 0) - { - current_fract = fract; - current_divide = mul_freq / mclk_Hz; - break; - } - - /* Closer to next one, set the closest to next data */ - if (remaind > mclk_Hz / 2) - { - remaind = mclk_Hz - remaind; - divide += 1; - } - - /* Update the closest div and fract */ - if (remaind < current_remainder) - { - current_fract = fract; - current_divide = divide; - current_remainder = remaind; - } - } - - /* Fill the computed fract and divider to registers */ - base->MDR = I2S_MDR_DIVIDE(current_divide - 1) | I2S_MDR_FRACT(current_fract - 1); - - /* Waiting for the divider updated */ - while (base->MCR & I2S_MCR_DUF_MASK) - { - } -} -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - -uint32_t SAI_GetInstance(I2S_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_I2S_COUNT; instance++) - { - if (s_saiBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_I2S_COUNT); - - return instance; -} - -static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) -{ - uint32_t i = 0; - uint8_t j = 0; - uint8_t bytesPerWord = bitWidth / 8U; - uint32_t data = 0; - uint32_t temp = 0; - - for (i = 0; i < size / bytesPerWord; i++) - { - for (j = 0; j < bytesPerWord; j++) - { - temp = (uint32_t)(*buffer); - data |= (temp << (8U * j)); - buffer++; - } - base->TDR[channel] = data; - data = 0; - } -} - -static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) -{ - uint32_t i = 0; - uint8_t j = 0; - uint8_t bytesPerWord = bitWidth / 8U; - uint32_t data = 0; - - for (i = 0; i < size / bytesPerWord; i++) - { - data = base->RDR[channel]; - for (j = 0; j < bytesPerWord; j++) - { - *buffer = (data >> (8U * j)) & 0xFF; - buffer++; - } - } -} - -void SAI_TxInit(I2S_Type *base, const sai_config_t *config) -{ - uint32_t val = 0; - - /* Enable the SAI clock */ - CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); - -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Master clock source setting */ - val = (base->MCR & ~I2S_MCR_MICS_MASK); - base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); - - /* Configure Master clock output enable */ - val = (base->MCR & ~I2S_MCR_MOE_MASK); - base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - - /* Configure audio protocol */ - switch (config->protocol) - { - case kSAI_BusLeftJustified: - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - break; - - case kSAI_BusRightJustified: - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - break; - - case kSAI_BusI2S: - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U); - break; - - case kSAI_BusPCMA: - base->TCR2 &= ~I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - break; - - case kSAI_BusPCMB: - base->TCR2 &= ~I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - break; - - default: - break; - } - - /* Set master or slave */ - if (config->masterSlave == kSAI_Master) - { - base->TCR2 |= I2S_TCR2_BCD_MASK; - base->TCR4 |= I2S_TCR4_FSD_MASK; - - /* Bit clock source setting */ - val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); - base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); - } - else - { - base->TCR2 &= ~I2S_TCR2_BCD_MASK; - base->TCR4 &= ~I2S_TCR4_FSD_MASK; - } - - /* Set Sync mode */ - switch (config->syncMode) - { - case kSAI_ModeAsync: - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(0U)); - break; - case kSAI_ModeSync: - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(1U)); - /* If sync with Rx, should set Rx to async mode */ - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(0U)); - break; - case kSAI_ModeSyncWithOtherTx: - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(2U)); - break; - case kSAI_ModeSyncWithOtherRx: - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(3U)); - break; - default: - break; - } -} - -void SAI_RxInit(I2S_Type *base, const sai_config_t *config) -{ - uint32_t val = 0; - - /* Enable SAI clock first. */ - CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); - -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Master clock source setting */ - val = (base->MCR & ~I2S_MCR_MICS_MASK); - base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); - - /* Configure Master clock output enable */ - val = (base->MCR & ~I2S_MCR_MOE_MASK); - base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - - /* Configure audio protocol */ - switch (config->protocol) - { - case kSAI_BusLeftJustified: - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - break; - - case kSAI_BusRightJustified: - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - break; - - case kSAI_BusI2S: - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U); - break; - - case kSAI_BusPCMA: - base->RCR2 &= ~I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - break; - - case kSAI_BusPCMB: - base->RCR2 &= ~I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - break; - - default: - break; - } - - /* Set master or slave */ - if (config->masterSlave == kSAI_Master) - { - base->RCR2 |= I2S_RCR2_BCD_MASK; - base->RCR4 |= I2S_RCR4_FSD_MASK; - - /* Bit clock source setting */ - val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); - base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); - } - else - { - base->RCR2 &= ~I2S_RCR2_BCD_MASK; - base->RCR4 &= ~I2S_RCR4_FSD_MASK; - } - - /* Set Sync mode */ - switch (config->syncMode) - { - case kSAI_ModeAsync: - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(0U)); - break; - case kSAI_ModeSync: - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(1U)); - /* If sync with Tx, should set Tx to async mode */ - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(0U)); - break; - case kSAI_ModeSyncWithOtherTx: - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(2U)); - break; - case kSAI_ModeSyncWithOtherRx: - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(3U)); - break; - default: - break; - } -} - -void SAI_Deinit(I2S_Type *base) -{ - SAI_TxEnable(base, false); - SAI_RxEnable(base, false); - CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]); -} - -void SAI_TxGetDefaultConfig(sai_config_t *config) -{ - config->bclkSource = kSAI_BclkSourceMclkDiv; - config->masterSlave = kSAI_Master; - config->mclkSource = kSAI_MclkSourceSysclk; - config->protocol = kSAI_BusLeftJustified; - config->syncMode = kSAI_ModeAsync; -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - config->mclkOutputEnable = true; -#endif /* FSL_FEATURE_SAI_HAS_MCR */ -} - -void SAI_RxGetDefaultConfig(sai_config_t *config) -{ - config->bclkSource = kSAI_BclkSourceMclkDiv; - config->masterSlave = kSAI_Master; - config->mclkSource = kSAI_MclkSourceSysclk; - config->protocol = kSAI_BusLeftJustified; - config->syncMode = kSAI_ModeSync; -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - config->mclkOutputEnable = true; -#endif /* FSL_FEATURE_SAI_HAS_MCR */ -} - -void SAI_TxReset(I2S_Type *base) -{ - /* Set the software reset and FIFO reset to clear internal state */ - base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK; - - /* Clear software reset bit, this should be done by software */ - base->TCSR &= ~I2S_TCSR_SR_MASK; - - /* Reset all Tx register values */ - base->TCR2 = 0; - base->TCR3 = 0; - base->TCR4 = 0; - base->TCR5 = 0; - base->TMR = 0; -} - -void SAI_RxReset(I2S_Type *base) -{ - /* Set the software reset and FIFO reset to clear internal state */ - base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK; - - /* Clear software reset bit, this should be done by software */ - base->RCSR &= ~I2S_RCSR_SR_MASK; - - /* Reset all Rx register values */ - base->RCR2 = 0; - base->RCR3 = 0; - base->RCR4 = 0; - base->RCR5 = 0; - base->RMR = 0; -} - -void SAI_TxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - /* If clock is sync with Rx, should enable RE bit. */ - if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U) - { - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); - } - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); - } - else - { - /* Should not close RE even sync with Rx */ - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK)); - } -} - -void SAI_RxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - /* If clock is sync with Tx, should enable TE bit. */ - if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U) - { - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); - } - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); - } - else - { - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK)); - } -} - -void SAI_TxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - uint32_t bclk = format->sampleRate_Hz * 32U * 2U; - -/* Compute the mclk */ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - /* Check if master clock divider enabled, then set master clock divider */ - if (base->MCR & I2S_MCR_MOE_MASK) - { - SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); - } -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - - /* Set bclk if needed */ - if (base->TCR2 & I2S_TCR2_BCD_MASK) - { - base->TCR2 &= ~I2S_TCR2_DIV_MASK; - base->TCR2 |= I2S_TCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); - } - - /* Set bitWidth */ - if (format->protocol == kSAI_BusRightJustified) - { - base->TCR5 = I2S_TCR5_WNW(31U) | I2S_TCR5_W0W(31U) | I2S_TCR5_FBT(31U); - } - else - { - base->TCR5 = I2S_TCR5_WNW(31U) | I2S_TCR5_W0W(31U) | I2S_TCR5_FBT(format->bitWidth - 1); - } - - /* Set mono or stereo */ - base->TMR = (uint32_t)format->stereo; - - /* Set data channel */ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; - base->TCR3 |= I2S_TCR3_TCE(1U << format->channel); - -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Set watermark */ - base->TCR1 = format->watermark; -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -} - -void SAI_RxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - uint32_t bclk = format->sampleRate_Hz * 32U * 2U; - -/* Compute the mclk */ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - /* Check if master clock divider enabled */ - if (base->MCR & I2S_MCR_MOE_MASK) - { - SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); - } -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - - /* Set bclk if needed */ - if (base->RCR2 & I2S_RCR2_BCD_MASK) - { - base->RCR2 &= ~I2S_RCR2_DIV_MASK; - base->RCR2 |= I2S_RCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); - } - - /* Set bitWidth */ - if (format->protocol == kSAI_BusRightJustified) - { - base->RCR5 = I2S_RCR5_WNW(31U) | I2S_RCR5_W0W(31U) | I2S_RCR5_FBT(31U); - } - else - { - base->RCR5 = I2S_RCR5_WNW(31U) | I2S_RCR5_W0W(31U) | I2S_RCR5_FBT(format->bitWidth - 1); - } - - /* Set mono or stereo */ - base->RMR = (uint32_t)format->stereo; - - /* Set data channel */ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; - base->RCR3 |= I2S_RCR3_RCE(1U << format->channel); - -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Set watermark */ - base->RCR1 = format->watermark; -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -} - -void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) -{ - uint32_t i = 0; - uint8_t bytesPerWord = bitWidth / 8U; - - for (i = 0; i < size; i++) - { - /* Wait until it can write data */ - while (!(base->TCSR & I2S_TCSR_FWF_MASK)) - { - } - - SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); - buffer += bytesPerWord; - } - - /* Wait until the last data is sent */ - while (!(base->TCSR & I2S_TCSR_FWF_MASK)) - { - } -} - -void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) -{ - uint32_t i = 0; - uint8_t bytesPerWord = bitWidth / 8U; - - for (i = 0; i < size; i++) - { - /* Wait until data is received */ - while (!(base->RCSR & I2S_RCSR_FWF_MASK)) - { - } - - SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); - buffer += bytesPerWord; - } -} - -void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) -{ - assert(handle); - - s_saiHandle[SAI_GetInstance(base)][0] = handle; - - handle->callback = callback; - handle->userData = userData; - - /* Set the isr pointer */ - s_saiTxIsr = SAI_TransferTxHandleIRQ; - - /* Enable Tx irq */ - EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); -} - -void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) -{ - assert(handle); - - s_saiHandle[SAI_GetInstance(base)][1] = handle; - - handle->callback = callback; - handle->userData = userData; - - /* Set the isr pointer */ - s_saiRxIsr = SAI_TransferRxHandleIRQ; - - /* Enable Rx irq */ - EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); -} - -status_t SAI_TransferTxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle); - - if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) - { - return kStatus_InvalidArgument; - } - - /* Copy format to handle */ - handle->bitWidth = format->bitWidth; -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - handle->watermark = format->watermark; -#endif - handle->channel = format->channel; - - SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - return kStatus_Success; -} - -status_t SAI_TransferRxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle); - - if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) - { - return kStatus_InvalidArgument; - } - - /* Copy format to handle */ - handle->bitWidth = format->bitWidth; -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - handle->watermark = format->watermark; -#endif - handle->channel = format->channel; - - SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - return kStatus_Success; -} - -status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) -{ - assert(handle); - - /* Check if the queue is full */ - if (handle->saiQueue[handle->queueUser].data) - { - return kStatus_SAI_QueueFull; - } - - /* Add into queue */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; - handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; - - /* Set the state to busy */ - handle->state = kSAI_Busy; - -/* Enable interrupt */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Use FIFO request interrupt and fifo error*/ - SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); -#else - SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - /* Enable Tx transfer */ - SAI_TxEnable(base, true); - - return kStatus_Success; -} - -status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) -{ - assert(handle); - - /* Check if the queue is full */ - if (handle->saiQueue[handle->queueUser].data) - { - return kStatus_SAI_QueueFull; - } - - /* Add into queue */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; - handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; - - /* Set state to busy */ - handle->state = kSAI_Busy; - -/* Enable interrupt */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Use FIFO request interrupt and fifo error*/ - SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); -#else - SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - /* Enable Rx transfer */ - SAI_RxEnable(base, true); - - return kStatus_Success; -} - -status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSAI_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); - } - - return status; -} - -status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSAI_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); - } - - return status; -} - -void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) -{ - assert(handle); - - /* Stop Tx transfer and disable interrupt */ - SAI_TxEnable(base, false); -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Use FIFO request interrupt and fifo error */ - SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); -#else - SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - handle->state = kSAI_Idle; - - /* Clear the queue */ - memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); - handle->queueDriver = 0; - handle->queueUser = 0; -} - -void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) -{ - assert(handle); - - /* Stop Tx transfer and disable interrupt */ - SAI_RxEnable(base, false); -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Use FIFO request interrupt and fifo error */ - SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); -#else - SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - handle->state = kSAI_Idle; - - /* Clear the queue */ - memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); - handle->queueDriver = 0; - handle->queueUser = 0; -} - -void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) -{ - assert(handle); - - uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; - - /* Handle Error */ - if (base->TCSR & I2S_TCSR_FEF_MASK) - { - /* Clear FIFO error flag to continue transfer */ - SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); - - /* Call the callback */ - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData); - } - } - -/* Handle transfer */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if (base->TCSR & I2S_TCSR_FRF_MASK) - { - /* Judge if the data need to transmit is less than space */ - uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), - (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize)); - - /* Copy the data from sai buffer to FIFO */ - SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); - - /* Update the internal counter */ - handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data += size; - } -#else - if (base->TCSR & I2S_TCSR_FWF_MASK) - { - uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); - - SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); - - /* Update internal counter */ - handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data += size; - } -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - /* If finished a blcok, call the callback function */ - if (handle->saiQueue[handle->queueDriver].dataSize == 0U) - { - memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData); - } - } - - /* If all data finished, just stop the transfer */ - if (handle->saiQueue[handle->queueDriver].data == NULL) - { - SAI_TransferAbortSend(base, handle); - } -} - -void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) -{ - assert(handle); - - uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; - - /* Handle Error */ - if (base->RCSR & I2S_RCSR_FEF_MASK) - { - /* Clear FIFO error flag to continue transfer */ - SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); - - /* Call the callback */ - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData); - } - } - -/* Handle transfer */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if (base->RCSR & I2S_RCSR_FRF_MASK) - { - /* Judge if the data need to transmit is less than space */ - uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize)); - - /* Copy the data from sai buffer to FIFO */ - SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); - - /* Update the internal counter */ - handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data += size; - } -#else - if (base->RCSR & I2S_RCSR_FWF_MASK) - { - uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); - - SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); - - /* Update internal state */ - handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data += size; - } -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - /* If finished a blcok, call the callback function */ - if (handle->saiQueue[handle->queueDriver].dataSize == 0U) - { - memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData); - } - } - - /* If all data finished, just stop the transfer */ - if (handle->saiQueue[handle->queueDriver].data == NULL) - { - SAI_TransferAbortReceive(base, handle); - } -} - -#if defined(I2S0) -#if defined(FSL_FEATURE_SAI_INT_SOURCE_NUM) && (FSL_FEATURE_SAI_INT_SOURCE_NUM == 1) -void I2S0_DriverIRQHandler(void) -{ - if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) - { - s_saiRxIsr(I2S0, s_saiHandle[0][1]); - } - if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) - { - s_saiTxIsr(I2S0, s_saiHandle[0][0]); - } -} -#else -void I2S0_Tx_DriverIRQHandler(void) -{ - assert(s_saiHandle[0][0]); - s_saiTxIsr(I2S0, s_saiHandle[0][0]); -} - -void I2S0_Rx_DriverIRQHandler(void) -{ - assert(s_saiHandle[0][1]); - s_saiRxIsr(I2S0, s_saiHandle[0][1]); -} -#endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ -#endif /* I2S0*/ - -#if defined(I2S1) -void I2S1_Tx_DriverIRQHandler(void) -{ - assert(s_saiHandle[1][0]); - s_saiTxIsr(I2S1, s_saiHandle[1][0]); -} - -void I2S1_Rx_DriverIRQHandler(void) -{ - assert(s_saiHandle[1][1]); - s_saiRxIsr(I2S1, s_saiHandle[1][1]); -} -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.h deleted file mode 100644 index d40c575..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.h +++ /dev/null @@ -1,849 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SAI_H_ -#define _FSL_SAI_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sai - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ -/*@}*/ - -/*! @brief SAI return status*/ -enum _sai_status_t -{ - kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ - kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ - kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ - kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ - kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */ - kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ - kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ -}; - -/*! @brief Define the SAI bus type */ -typedef enum _sai_protocol -{ - kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/ - kSAI_BusRightJustified, /*!< Uses right justified format. */ - kSAI_BusI2S, /*!< Uses I2S format. */ - kSAI_BusPCMA, /*!< Uses I2S PCM A format.*/ - kSAI_BusPCMB /*!< Uses I2S PCM B format. */ -} sai_protocol_t; - -/*! @brief Master or slave mode */ -typedef enum _sai_master_slave -{ - kSAI_Master = 0x0U, /*!< Master mode */ - kSAI_Slave = 0x1U /*!< Slave mode */ -} sai_master_slave_t; - -/*! @brief Mono or stereo audio format */ -typedef enum _sai_mono_stereo -{ - kSAI_Stereo = 0x0U, /*!< Stereo sound. */ - kSAI_MonoLeft, /*!< Only left channel have sound. */ - kSAI_MonoRight /*!< Only Right channel have sound. */ -} sai_mono_stereo_t; - -/*! @brief Synchronous or asynchronous mode */ -typedef enum _sai_sync_mode -{ - kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ - kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ - kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */ - kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ -} sai_sync_mode_t; - -/*! @brief Mater clock source */ -typedef enum _sai_mclk_source -{ - kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */ - kSAI_MclkSourceSelect1, /*!< Master clock from source 1 */ - kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ - kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ -} sai_mclk_source_t; - -/*! @brief Bit clock source */ -typedef enum _sai_bclk_source -{ - kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ - kSAI_BclkSourceMclkDiv, /*!< Bit clock using master clock divider */ - kSAI_BclkSourceOtherSai0, /*!< Bit clock from other SAI device */ - kSAI_BclkSourceOtherSai1 /*!< Bit clock from other SAI device */ -} sai_bclk_source_t; - -/*! @brief The SAI interrupt enable flag */ -enum _sai_interrupt_enable_t -{ - kSAI_WordStartInterruptEnable = - I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */ - kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ - kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */ - kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */ -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -}; - -/*! @brief The DMA request sources */ -enum _sai_dma_enable_t -{ - kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */ -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -}; - -/*! @brief The SAI status flag */ -enum _sai_flags -{ - kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */ - kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */ - kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */ -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */ -}; - -/*! @brief The reset type */ -typedef enum _sai_reset_type -{ - kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ - kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ - kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ -} sai_reset_type_t; - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING -/*! - * @brief The SAI packing mode - * The mode includes 8 bit and 16 bit packing. - */ -typedef enum _sai_fifo_packing -{ - kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */ - kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ - kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ -} sai_fifo_packing_t; -#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ - -/*! @brief SAI user configuration structure */ -typedef struct _sai_config -{ - sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ - sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - sai_mclk_source_t mclkSource; /*!< Master Clock source */ - sai_bclk_source_t bclkSource; /*!< Bit Clock source */ - sai_master_slave_t masterSlave; /*!< Master or slave */ -} sai_config_t; - -/*!@brief SAI transfer queue size, user can refine it according to use case. */ -#define SAI_XFER_QUEUE_SIZE (4) - -/*! @brief Audio sample rate */ -typedef enum _sai_sample_rate -{ - kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ - kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ - kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ - kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ - kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ - kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ - kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ - kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ - kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ - kSAI_SampleRate96KHz = 96000U /*!< Sample rate 96000 Hz */ -} sai_sample_rate_t; - -/*! @brief Audio word width */ -typedef enum _sai_word_width -{ - kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ - kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ - kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ - kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */ -} sai_word_width_t; - -/*! @brief sai transfer format */ -typedef struct _sai_transfer_format -{ - uint32_t sampleRate_Hz; /*!< Sample rate of audio data */ - uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32 bits */ - sai_mono_stereo_t stereo; /*!< Mono or stereo */ - uint32_t masterClockHz; /*!< Master clock frequency in Hz */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - uint8_t watermark; /*!< Watermark value */ -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - uint8_t channel; /*!< Data channel used in transfer.*/ - sai_protocol_t protocol; /*!< Which audio protocol used */ -} sai_transfer_format_t; - -/*! @brief SAI transfer structure */ -typedef struct _sai_transfer -{ - uint8_t *data; /*!< Data start address to transfer. */ - size_t dataSize; /*!< Transfer size. */ -} sai_transfer_t; - -typedef struct _sai_handle sai_handle_t; - -/*! @brief SAI transfer callback prototype */ -typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData); - -/*! @brief SAI handle structure */ -struct _sai_handle -{ - uint32_t state; /*!< Transfer status */ - sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ - void *userData; /*!< Callback parameter passed to callback function*/ - uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ - uint8_t channel; /*!< Transfer channel */ - sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ - size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ - volatile uint8_t queueUser; /*!< Index for user to queue transfer */ - volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - uint8_t watermark; /*!< Watermark value */ -#endif -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the SAI Tx peripheral. - * - * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault - * because the clock is not enabled. - * - * @param base SAI base pointer - * @param config SAI configuration structure. -*/ -void SAI_TxInit(I2S_Type *base, const sai_config_t *config); - -/*! - * @brief Initializes the the SAI Rx peripheral. - * - * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault - * because the clock is not enabled. - * - * @param base SAI base pointer - * @param config SAI configuration structure. - */ -void SAI_RxInit(I2S_Type *base, const sai_config_t *config); - -/*! - * @brief Sets the SAI Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in SAI_TxConfig(). - * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified - * before calling SAI_TxConfig(). - * Example: - @code - sai_config_t config; - SAI_TxGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master configuration structure - */ -void SAI_TxGetDefaultConfig(sai_config_t *config); - -/*! - * @brief Sets the SAI Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in SAI_RxConfig(). - * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified - * before calling SAI_RxConfig(). - * Example: - @code - sai_config_t config; - SAI_RxGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master configuration structure - */ -void SAI_RxGetDefaultConfig(sai_config_t *config); - -/*! - * @brief De-initializes the SAI peripheral. - * - * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit - * or SAI_RxInit is called to enable the clock. - * - * @param base SAI base pointer -*/ -void SAI_Deinit(I2S_Type *base); - -/*! - * @brief Resets the SAI Tx. - * - * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. - * - * @param base SAI base pointer - */ -void SAI_TxReset(I2S_Type *base); - -/*! - * @brief Resets the SAI Rx. - * - * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. - * - * @param base SAI base pointer - */ -void SAI_RxReset(I2S_Type *base); - -/*! - * @brief Enables/disables SAI Tx. - * - * @param base SAI base pointer - * @param enable True means enable SAI Tx, false means disable. - */ -void SAI_TxEnable(I2S_Type *base, bool enable); - -/*! - * @brief Enables/disables SAI Rx. - * - * @param base SAI base pointer - * @param enable True means enable SAI Rx, false means disable. - */ -void SAI_RxEnable(I2S_Type *base, bool enable); - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the SAI Tx status flag state. - * - * @param base SAI base pointer - * @return SAI Tx status flag value. Use the Status Mask to get the status value needed. - */ -static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base) -{ - return base->TCSR; -} - -/*! - * @brief Clears the SAI Tx status flag state. - * - * @param base SAI base pointer - * @param mask State mask. It can be a combination of the following source if defined: - * @arg kSAI_WordStartFlag - * @arg kSAI_SyncErrorFlag - * @arg kSAI_FIFOErrorFlag - */ -static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask) -{ - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); -} - -/*! - * @brief Gets the SAI Tx status flag state. - * - * @param base SAI base pointer - * @return SAI Rx status flag value. Use the Status Mask to get the status value needed. - */ -static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base) -{ - return base->RCSR; -} - -/*! - * @brief Clears the SAI Rx status flag state. - * - * @param base SAI base pointer - * @param mask State mask. It can be a combination of the following source if defined: - * @arg kSAI_WordStartFlag - * @arg kSAI_SyncErrorFlag - * @arg kSAI_FIFOErrorFlag - */ -static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) -{ - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables SAI Tx interrupt requests. - * - * @param base SAI base pointer - * @param mask interrupt source - * The parameter can be a combination of the following source if defined: - * @arg kSAI_WordStartInterruptEnable - * @arg kSAI_SyncErrorInterruptEnable - * @arg kSAI_FIFOWarningInterruptEnable - * @arg kSAI_FIFORequestInterruptEnable - * @arg kSAI_FIFOErrorInterruptEnable - */ -static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask) -{ - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); -} - -/*! - * @brief Enables SAI Rx interrupt requests. - * - * @param base SAI base pointer - * @param mask interrupt source - * The parameter can be a combination of the following source if defined: - * @arg kSAI_WordStartInterruptEnable - * @arg kSAI_SyncErrorInterruptEnable - * @arg kSAI_FIFOWarningInterruptEnable - * @arg kSAI_FIFORequestInterruptEnable - * @arg kSAI_FIFOErrorInterruptEnable - */ -static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask) -{ - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); -} - -/*! - * @brief Disables SAI Tx interrupt requests. - * - * @param base SAI base pointer - * @param mask interrupt source - * The parameter can be a combination of the following source if defined: - * @arg kSAI_WordStartInterruptEnable - * @arg kSAI_SyncErrorInterruptEnable - * @arg kSAI_FIFOWarningInterruptEnable - * @arg kSAI_FIFORequestInterruptEnable - * @arg kSAI_FIFOErrorInterruptEnable - */ -static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask) -{ - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); -} - -/*! - * @brief Disables SAI Rx interrupt requests. - * - * @param base SAI base pointer - * @param mask interrupt source - * The parameter can be a combination of the following source if defined: - * @arg kSAI_WordStartInterruptEnable - * @arg kSAI_SyncErrorInterruptEnable - * @arg kSAI_FIFOWarningInterruptEnable - * @arg kSAI_FIFORequestInterruptEnable - * @arg kSAI_FIFOErrorInterruptEnable - */ -static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask) -{ - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables/disables SAI Tx DMA requests. - * @param base SAI base pointer - * @param mask DMA source - * The parameter can be combination of the following source if defined: - * @arg kSAI_FIFOWarningDMAEnable - * @arg kSAI_FIFORequestDMAEnable - * @param enable True means enable DMA, false means disable DMA. - */ -static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); - } - else - { - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); - } -} - -/*! - * @brief Enables/disables SAI Rx DMA requests. - * @param base SAI base pointer - * @param mask DMA source - * The parameter can be a combination of the following source if defined: - * @arg kSAI_FIFOWarningDMAEnable - * @arg kSAI_FIFORequestDMAEnable - * @param enable True means enable DMA, false means disable DMA. - */ -static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); - } - else - { - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); - } -} - -/*! - * @brief Gets the SAI Tx data register address. - * - * This API is used to provide a transfer address for SAI DMA transfer configuration. - * - * @param base SAI base pointer. - * @param channel Which data channel used. - * @return data register address. - */ -static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) -{ - return (uint32_t)(&(base->TDR)[channel]); -} - -/*! - * @brief Gets the SAI Rx data register address. - * - * This API is used to provide a transfer address for SAI DMA transfer configuration. - * - * @param base SAI base pointer. - * @param channel Which data channel used. - * @return data register address. - */ -static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) -{ - return (uint32_t)(&(base->RDR)[channel]); -} - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Configures the SAI Tx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master - * clock, this value should equals to masterClockHz in format. -*/ -void SAI_TxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master - * clock, this value should equals to masterClockHz in format. -*/ -void SAI_RxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Sends data using a blocking method. - * - * @note This function blocks by polling until data is ready to be sent. - * - * @param base SAI base pointer. - * @param channel Data channel used. - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param buffer Pointer to the data to be written. - * @param size Bytes to be written. - */ -void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); - -/*! - * @brief Writes data into SAI FIFO. - * - * @param base SAI base pointer. - * @param channel Data channel used. - * @param data Data needs to be written. - */ -static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data) -{ - base->TDR[channel] = data; -} - -/*! - * @brief Receives data using a blocking method. - * - * @note This function blocks by polling until data is ready to be sent. - * - * @param base SAI base pointer. - * @param channel Data channel used. - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param buffer Pointer to the data to be read. - * @param size Bytes to be read. - */ -void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); - -/*! - * @brief Reads data from SAI FIFO. - * - * @param base SAI base pointer. - * @param channel Data channel used. - * @return Data in SAI FIFO. - */ -static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel) -{ - return base->RDR[channel]; -} - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SAI Tx handle. - * - * This function initializes the Tx handle for SAI Tx transactional APIs. Call - * this function one time to get the handle initialized. - * - * @param base SAI base pointer - * @param handle SAI handle pointer. - * @param callback pointer to user callback function - * @param userData user parameter passed to the callback function - */ -void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); - -/*! - * @brief Initializes the SAI Rx handle. - * - * This function initializes the Rx handle for SAI Rx transactional APIs. Call - * this function one time to get the handle initialized. - * - * @param base SAI base pointer. - * @param handle SAI handle pointer. - * @param callback pointer to user callback function - * @param userData user parameter passed to the callback function - */ -void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); - -/*! - * @brief Configures the SAI Tx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param handle SAI handle pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal to masterClockHz in format. - * @return Status of this function. Return value is one of status_t. -*/ -status_t SAI_TransferTxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param handle SAI handle pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master - * clock, this value should equals to masterClockHz in format. - * @return Status of this function. Return value is one of status_t. -*/ -status_t SAI_TransferRxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Performs an interrupt non-blocking send transfer on SAI. - * - * @note This API returns immediately after the transfer initiates. - * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether - * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer - * is finished. - * - * @param base SAI base pointer - * @param handle pointer to sai_handle_t structure which stores the transfer state - * @param xfer pointer to sai_transfer_t structure - * @retval kStatus_Success Successfully started the data receive. - * @retval kStatus_SAI_TxBusy Previous receive still not finished. - * @retval kStatus_InvalidArgument The input parameter is invalid. - */ -status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); - -/*! - * @brief Performs an interrupt non-blocking receive transfer on SAI. - * - * @note This API returns immediately after the transfer initiates. - * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether - * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer - * is finished. - * - * @param base SAI base pointer - * @param handle pointer to sai_handle_t structure which stores the transfer state - * @param xfer pointer to sai_transfer_t structure - * @retval kStatus_Success Successfully started the data receive. - * @retval kStatus_SAI_RxBusy Previous receive still not finished. - * @retval kStatus_InvalidArgument The input parameter is invalid. - */ -status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); - -/*! - * @brief Gets a set byte count. - * - * @param base SAI base pointer. - * @param handle pointer to sai_handle_t structure which stores the transfer state. - * @param count Bytes count sent. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count); - -/*! - * @brief Gets a received byte count. - * - * @param base SAI base pointer. - * @param handle pointer to sai_handle_t structure which stores the transfer state. - * @param count Bytes count received. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count); - -/*! - * @brief Aborts the current send. - * - * @note This API can be called any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base SAI base pointer. - * @param handle pointer to sai_handle_t structure which stores the transfer state. - */ -void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); - -/*! - * @brief Aborts the the current IRQ receive. - * - * @note This API can be called any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base SAI base pointer - * @param handle pointer to sai_handle_t structure which stores the transfer state. - */ -void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle); - -/*! - * @brief Tx interrupt handler. - * - * @param base SAI base pointer. - * @param handle pointer to sai_handle_t structure. - */ -void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle); - -/*! - * @brief Tx interrupt handler. - * - * @param base SAI base pointer. - * @param handle pointer to sai_handle_t structure. - */ -void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); - -/*! @} */ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ - -/*! @} */ - -#endif /* _FSL_SAI_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai_edma.c deleted file mode 100644 index 116d088..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai_edma.c +++ /dev/null @@ -1,619 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sai_edma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sai_edma" -#endif - -/******************************************************************************* - * Definitations - ******************************************************************************/ -/* Used for 32byte aligned */ -#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) - -static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; - -/*handle; - - /* If finished a blcok, call the callback function */ - memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); - saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - if (saiHandle->callback) - { - (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_TxIdle, saiHandle->userData); - } - - /* If all data finished, just stop the transfer */ - if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) - { - /* Disable DMA enable bit */ - SAI_TxEnableDMA(privHandle->base, kSAI_FIFORequestDMAEnable, false); - EDMA_AbortTransfer(handle); - } -} - -static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) -{ - sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData; - sai_edma_handle_t *saiHandle = privHandle->handle; - - /* If finished a blcok, call the callback function */ - memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); - saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - if (saiHandle->callback) - { - (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_RxIdle, saiHandle->userData); - } - - /* If all data finished, just stop the transfer */ - if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) - { - /* Disable DMA enable bit */ - SAI_RxEnableDMA(privHandle->base, kSAI_FIFORequestDMAEnable, false); - EDMA_AbortTransfer(handle); - } -} - -/*! - * brief Initializes the SAI eDMA handle. - * - * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. - * Usually, for a specified SAI instance, call this API once to get the initialized handle. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - * param base SAI peripheral base address. - * param callback Pointer to user callback function. - * param userData User parameter passed to the callback function. - * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. - */ -void SAI_TransferTxCreateHandleEDMA( - I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) -{ - assert(handle && dmaHandle); - - uint32_t instance = SAI_GetInstance(base); - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - /* Set sai base to handle */ - handle->dmaHandle = dmaHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SAI state to idle */ - handle->state = kSAI_Idle; - - s_edmaPrivateHandle[instance][0].base = base; - s_edmaPrivateHandle[instance][0].handle = handle; - - /* Need to use scatter gather */ - EDMA_InstallTCDMemory(dmaHandle, (edma_tcd_t *)(STCD_ADDR(handle->tcd)), SAI_XFER_QUEUE_SIZE); - - /* Install callback for Tx dma channel */ - EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); -} - -/*! - * brief Initializes the SAI Rx eDMA handle. - * - * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. - * Usually, for a specified SAI instance, call this API once to get the initialized handle. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - * param base SAI peripheral base address. - * param callback Pointer to user callback function. - * param userData User parameter passed to the callback function. - * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. - */ -void SAI_TransferRxCreateHandleEDMA( - I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) -{ - assert(handle && dmaHandle); - - uint32_t instance = SAI_GetInstance(base); - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - /* Set sai base to handle */ - handle->dmaHandle = dmaHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SAI state to idle */ - handle->state = kSAI_Idle; - - s_edmaPrivateHandle[instance][1].base = base; - s_edmaPrivateHandle[instance][1].handle = handle; - - /* Need to use scatter gather */ - EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); - - /* Install callback for Tx dma channel */ - EDMA_SetCallback(dmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); -} - -/*! - * brief Configures the SAI Tx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - * param format Pointer to SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master - * clock, this value should equals to masterClockHz in format. - * retval kStatus_Success Audio format set successfully. - * retval kStatus_InvalidArgument The input argument is invalid. -*/ -void SAI_TransferTxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle && format); - - /* Configure the audio format to SAI registers */ - SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - /* Get the tranfer size from format, this should be used in EDMA configuration */ - if (format->bitWidth == 24U) - { - handle->bytesPerFrame = 4U; - } - else - { - handle->bytesPerFrame = format->bitWidth / 8U; - } - - /* Update the data channel SAI used */ - handle->channel = format->channel; - - /* Clear the channel enable bits unitl do a send/receive */ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - handle->count = FSL_FEATURE_SAI_FIFO_COUNT - format->watermark; -#else - handle->count = 1U; -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -} - -/*! - * brief Configures the SAI Rx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - * param format Pointer to SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master - * clock, this value should equal to masterClockHz in format. - * retval kStatus_Success Audio format set successfully. - * retval kStatus_InvalidArgument The input argument is invalid. -*/ -void SAI_TransferRxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle && format); - - /* Configure the audio format to SAI registers */ - SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - /* Get the tranfer size from format, this should be used in EDMA configuration */ - if (format->bitWidth == 24U) - { - handle->bytesPerFrame = 4U; - } - else - { - handle->bytesPerFrame = format->bitWidth / 8U; - } - - /* Update the data channel SAI used */ - handle->channel = format->channel; - - /* Clear the channel enable bits unitl do a send/receive */ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - handle->count = format->watermark; -#else - handle->count = 1U; -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -} - -/*! - * brief Performs a non-blocking SAI transfer using DMA. - * - * note This interface returns immediately after the transfer initiates. Call - * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - * param xfer Pointer to the DMA transfer structure. - * retval kStatus_Success Start a SAI eDMA send successfully. - * retval kStatus_InvalidArgument The input argument is invalid. - * retval kStatus_TxBusy SAI is busy sending data. - */ -status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) -{ - assert(handle && xfer); - - edma_transfer_config_t config = {0}; - uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); - - /* Check if input parameter invalid */ - if ((xfer->data == NULL) || (xfer->dataSize == 0U)) - { - return kStatus_InvalidArgument; - } - - if (handle->saiQueue[handle->queueUser].data) - { - return kStatus_SAI_QueueFull; - } - - /* Change the state of handle */ - handle->state = kSAI_Busy; - - /* Update the queue state */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; - handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; - - /* Prepare edma configure */ - EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, - handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral); - - /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ - handle->nbytes = handle->count * handle->bytesPerFrame; - - EDMA_SubmitTransfer(handle->dmaHandle, &config); - - /* Start DMA transfer */ - EDMA_StartTransfer(handle->dmaHandle); - - /* Enable DMA enable bit */ - SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); - - /* Enable SAI Tx clock */ - SAI_TxEnable(base, true); - - /* Enable the channel FIFO */ - base->TCR3 |= I2S_TCR3_TCE(1U << handle->channel); - - return kStatus_Success; -} - -/*! - * brief Performs a non-blocking SAI receive using eDMA. - * - * note This interface returns immediately after the transfer initiates. Call - * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. - * - * param base SAI base pointer - * param handle SAI eDMA handle pointer. - * param xfer Pointer to DMA transfer structure. - * retval kStatus_Success Start a SAI eDMA receive successfully. - * retval kStatus_InvalidArgument The input argument is invalid. - * retval kStatus_RxBusy SAI is busy receiving data. - */ -status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) -{ - assert(handle && xfer); - - edma_transfer_config_t config = {0}; - uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); - - /* Check if input parameter invalid */ - if ((xfer->data == NULL) || (xfer->dataSize == 0U)) - { - return kStatus_InvalidArgument; - } - - if (handle->saiQueue[handle->queueUser].data) - { - return kStatus_SAI_QueueFull; - } - - /* Change the state of handle */ - handle->state = kSAI_Busy; - - /* Update queue state */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; - handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; - - /* Prepare edma configure */ - EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, - handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory); - - /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ - handle->nbytes = handle->count * handle->bytesPerFrame; - - EDMA_SubmitTransfer(handle->dmaHandle, &config); - - /* Start DMA transfer */ - EDMA_StartTransfer(handle->dmaHandle); - - /* Enable DMA enable bit */ - SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); - - /* Enable the channel FIFO */ - base->RCR3 |= I2S_RCR3_RCE(1U << handle->channel); - - /* Enable SAI Rx clock */ - SAI_RxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts a SAI transfer using eDMA. - * - * This function only aborts the current transfer slots, the other transfer slots' information still kept - * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - */ -void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) -{ - assert(handle); - - /* Disable dma */ - EDMA_AbortTransfer(handle->dmaHandle); - - /* Disable the channel FIFO */ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; - - /* Disable DMA enable bit */ - SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); - - /* Disable Tx */ - SAI_TxEnable(base, false); - - /* Reset the FIFO pointer, at the same time clear all error flags if set */ - base->TCSR |= (I2S_TCSR_FR_MASK | I2S_TCSR_SR_MASK); - base->TCSR &= ~I2S_TCSR_SR_MASK; - - /* Handle the queue index */ - memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - - /* Set the handle state */ - handle->state = kSAI_Idle; -} - -/*! - * brief Aborts a SAI receive using eDMA. - * - * This function only aborts the current transfer slots, the other transfer slots' information still kept - * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA. - * - * param base SAI base pointer - * param handle SAI eDMA handle pointer. - */ -void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) -{ - assert(handle); - - /* Disable dma */ - EDMA_AbortTransfer(handle->dmaHandle); - - /* Disable the channel FIFO */ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; - - /* Disable DMA enable bit */ - SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); - - /* Disable Rx */ - SAI_RxEnable(base, false); - - /* Reset the FIFO pointer, at the same time clear all error flags if set */ - base->RCSR |= (I2S_RCSR_FR_MASK | I2S_RCSR_SR_MASK); - base->RCSR &= ~I2S_RCSR_SR_MASK; - - /* Handle the queue index */ - memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - - /* Set the handle state */ - handle->state = kSAI_Idle; -} - -/*! - * brief Terminate all SAI send. - * - * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the - * current transfer slot, please call SAI_TransferAbortSendEDMA. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - */ -void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) -{ - assert(handle); - - /* Abort the current transfer */ - SAI_TransferAbortSendEDMA(base, handle); - - /* Clear all the internal information */ - memset(handle->tcd, 0U, sizeof(handle->tcd)); - memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); - memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; - handle->queueDriver = 0U; -} - -/*! - * brief Terminate all SAI receive. - * - * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the - * current transfer slot, please call SAI_TransferAbortReceiveEDMA. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - */ -void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) -{ - assert(handle); - - /* Abort the current transfer */ - SAI_TransferAbortReceiveEDMA(base, handle); - - /* Clear all the internal information */ - memset(handle->tcd, 0U, sizeof(handle->tcd)); - memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); - memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; - handle->queueDriver = 0U; -} - -/*! - * brief Gets byte count sent by SAI. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - * param count Bytes count sent by SAI. - * retval kStatus_Success Succeed get the transfer count. - * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. - */ -status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSAI_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); - } - - return status; -} - -/*! - * brief Gets byte count received by SAI. - * - * param base SAI base pointer - * param handle SAI eDMA handle pointer. - * param count Bytes count received by SAI. - * retval kStatus_Success Succeed get the transfer count. - * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. - */ -status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSAI_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); - } - - return status; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai_edma.h deleted file mode 100644 index b3d9139..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai_edma.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SAI_EDMA_H_ -#define _FSL_SAI_EDMA_H_ - -#include "fsl_sai.h" -#include "fsl_edma.h" - -/*! - * @addtogroup sai_edma - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*!< Version 2.1.5 */ -/*@}*/ - -typedef struct _sai_edma_handle sai_edma_handle_t; - -/*! @brief SAI eDMA transfer callback function for finish and error */ -typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData); - -/*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ -struct _sai_edma_handle -{ - edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint8_t bytesPerFrame; /*!< Bytes in a frame */ - uint8_t channel; /*!< Which data channel */ - uint8_t count; /*!< The transfer data count in a DMA request */ - uint32_t state; /*!< Internal state for SAI eDMA transfer */ - sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ - void *userData; /*!< User callback parameter */ - uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */ - sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ - size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ - volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ - volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA Transactional - * @{ - */ - -/*! - * @brief Initializes the SAI eDMA handle. - * - * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. - * Usually, for a specified SAI instance, call this API once to get the initialized handle. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param base SAI peripheral base address. - * @param callback Pointer to user callback function. - * @param userData User parameter passed to the callback function. - * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. - */ -void SAI_TransferTxCreateHandleEDMA( - I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); - -/*! - * @brief Initializes the SAI Rx eDMA handle. - * - * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. - * Usually, for a specified SAI instance, call this API once to get the initialized handle. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param base SAI peripheral base address. - * @param callback Pointer to user callback function. - * @param userData User parameter passed to the callback function. - * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. - */ -void SAI_TransferRxCreateHandleEDMA( - I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); - -/*! - * @brief Configures the SAI Tx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master - * clock, this value should equals to masterClockHz in format. - * @retval kStatus_Success Audio format set successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. -*/ -void SAI_TransferTxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master - * clock, this value should equal to masterClockHz in format. - * @retval kStatus_Success Audio format set successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. -*/ -void SAI_TransferRxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Performs a non-blocking SAI transfer using DMA. - * - * @note This interface returns immediately after the transfer initiates. Call - * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param xfer Pointer to the DMA transfer structure. - * @retval kStatus_Success Start a SAI eDMA send successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. - * @retval kStatus_TxBusy SAI is busy sending data. - */ -status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SAI receive using eDMA. - * - * @note This interface returns immediately after the transfer initiates. Call - * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. - * - * @param base SAI base pointer - * @param handle SAI eDMA handle pointer. - * @param xfer Pointer to DMA transfer structure. - * @retval kStatus_Success Start a SAI eDMA receive successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. - * @retval kStatus_RxBusy SAI is busy receiving data. - */ -status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); - -/*! - * @brief Terminate all SAI send. - * - * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the - * current transfer slot, please call SAI_TransferAbortSendEDMA. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - */ -void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); - -/*! - * @brief Terminate all SAI receive. - * - * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the - * current transfer slot, please call SAI_TransferAbortReceiveEDMA. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - */ -void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); - -/*! - * @brief Aborts a SAI transfer using eDMA. - * - * This function only aborts the current transfer slots, the other transfer slots' information still kept - * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - */ -void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); - -/*! - * @brief Aborts a SAI receive using eDMA. - * - * This function only aborts the current transfer slots, the other transfer slots' information still kept - * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA. - * - * @param base SAI base pointer - * @param handle SAI eDMA handle pointer. - */ -void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); - -/*! - * @brief Gets byte count sent by SAI. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param count Bytes count sent by SAI. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. - */ -status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); - -/*! - * @brief Gets byte count received by SAI. - * - * @param base SAI base pointer - * @param handle SAI eDMA handle pointer. - * @param count Bytes count received by SAI. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. - */ -status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sim.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sim.c deleted file mode 100644 index 3a4b801..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sim.c +++ /dev/null @@ -1,53 +0,0 @@ -/* -* Copyright (c) 2015, Freescale Semiconductor, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_sim.h" - -/******************************************************************************* - * Codes - ******************************************************************************/ -#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) -void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask) -{ - SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK); - - SIM->SOPT1 = (SIM->SOPT1 & ~kSIM_UsbVoltRegEnableInAllModes) | mask; -} -#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ - -void SIM_GetUniqueId(sim_uid_t *uid) -{ -#if defined(SIM_UIDH) - uid->H = SIM->UIDH; -#endif - uid->MH = SIM->UIDMH; - uid->ML = SIM->UIDML; - uid->L = SIM->UIDL; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sim.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sim.h deleted file mode 100644 index 77958f8..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sim.h +++ /dev/null @@ -1,127 +0,0 @@ -/* -* Copyright (c) 2015, Freescale Semiconductor, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _FSL_SIM_H_ -#define _FSL_SIM_H_ - -#include "fsl_common.h" - -/*! @addtogroup sim */ -/*! @{*/ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Driver version 2.0.0 */ -/*@}*/ - -#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) -/*!@brief USB voltage regulator enable setting. */ -enum _sim_usb_volt_reg_enable_mode -{ - kSIM_UsbVoltRegEnable = SIM_SOPT1_USBREGEN_MASK, /*!< Enable voltage regulator. */ - kSIM_UsbVoltRegEnableInLowPower = SIM_SOPT1_USBVSTBY_MASK, /*!< Enable voltage regulator in VLPR/VLPW modes. */ - kSIM_UsbVoltRegEnableInStop = SIM_SOPT1_USBSSTBY_MASK, /*!< Enable voltage regulator in STOP/VLPS/LLS/VLLS modes. */ - kSIM_UsbVoltRegEnableInAllModes = SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK | - SIM_SOPT1_USBVSTBY_MASK /*!< Enable voltage regulator in all power modes. */ -}; -#endif /* (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) */ - -/*!@brief Unique ID. */ -typedef struct _sim_uid -{ -#if defined(SIM_UIDH) - uint32_t H; /*!< UIDH. */ -#endif - uint32_t MH; /*!< UIDMH. */ - uint32_t ML; /*!< UIDML. */ - uint32_t L; /*!< UIDL. */ -} sim_uid_t; - -/*!@brief Flash enable mode. */ -enum _sim_flash_mode -{ - kSIM_FlashDisableInWait = SIM_FCFG1_FLASHDOZE_MASK, /*!< Disable flash in wait mode. */ - kSIM_FlashDisable = SIM_FCFG1_FLASHDIS_MASK /*!< Disable flash in normal mode. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) -/*! - * @brief Sets the USB voltage regulator setting. - * - * This function configures whether the USB voltage regulator is enabled in - * normal RUN mode, STOP/VLPS/LLS/VLLS modes and VLPR/VLPW modes. The configurations - * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, enable - * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode, - * please use: - * - * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower); - * - * @param mask USB voltage regulator enable setting. - */ -void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask); -#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ - -/*! - * @brief Get the unique identification register value. - * - * @param uid Pointer to the structure to save the UID value. - */ -void SIM_GetUniqueId(sim_uid_t *uid); - -/*! - * @brief Set the flash enable mode. - * - * @param mode The mode to set, see \ref _sim_flash_mode for mode details. - */ -static inline void SIM_SetFlashMode(uint8_t mode) -{ - SIM->FCFG1 = mode; -} - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* _FSL_SIM_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_smc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_smc.c deleted file mode 100644 index b3998d0..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_smc.c +++ /dev/null @@ -1,511 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_smc.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.smc" -#endif - -typedef void (*smc_stop_ram_func_t)(void); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static void SMC_EnterStopRamFunc(void); - -/******************************************************************************* - * Variables - ******************************************************************************/ -static uint32_t g_savedPrimask; - -/* - * The ram function code is: - * - * uint32_t i; - * for (i=0; i<0x8; i++) - * { - * __NOP(); - * } - * __DSB(); - * __WFI(); - * __ISB(); - * - * When entring the stop modes, the flash prefetch might be interrupted, thus - * the prefetched code or data might be broken. To make sure the flash is idle - * when entring the stop modes, the code is moved to ram. And delay for a while - * before WFI to make sure previous flash prefetch is finished. - * - * Only need to do like this when code is in flash, if code is in rom or ram, - * this is not necessary. - */ -static uint16_t s_stopRamFuncArray[] = { - 0x2000, /* MOVS R0, #0 */ - 0x2808, /* CMP R0, #8 */ - 0xD202, /* BCS.N */ - 0xBF00, /* NOP */ - 0x1C40, /* ADDS R0, R0, #1 */ - 0xE7FA, /* B.N */ - 0xF3BF, 0x8F4F, /* DSB */ - 0xBF30, /* WFI */ - 0xF3BF, 0x8F6F, /* ISB */ - 0x4770, /* BX LR */ -}; - -/******************************************************************************* - * Code - ******************************************************************************/ -static void SMC_EnterStopRamFunc(void) -{ - uint32_t ramFuncEntry = ((uint32_t)(s_stopRamFuncArray)) + 1U; - smc_stop_ram_func_t stopRamFunc = (smc_stop_ram_func_t)ramFuncEntry; - stopRamFunc(); -} - -#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) -/*! - * brief Gets the SMC parameter. - * - * This function gets the SMC parameter including the enabled power mdoes. - * - * param base SMC peripheral base address. - * param param Pointer to the SMC param structure. - */ -void SMC_GetParam(SMC_Type *base, smc_param_t *param) -{ - uint32_t reg = base->PARAM; - param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK); - param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK); - param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK); - param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK); -} -#endif /* FSL_FEATURE_SMC_HAS_PARAM */ - -/*! - * brief Prepares to enter stop modes. - * - * This function should be called before entering STOP/VLPS/LLS/VLLS modes. - */ -void SMC_PreEnterStopModes(void) -{ - g_savedPrimask = DisableGlobalIRQ(); - __ISB(); -} - -/*! - * brief Recovers after wake up from stop modes. - * - * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes. - * It is used with ref SMC_PreEnterStopModes. - */ -void SMC_PostExitStopModes(void) -{ - EnableGlobalIRQ(g_savedPrimask); - __ISB(); -} - -/*! - * brief Prepares to enter wait modes. - * - * This function should be called before entering WAIT/VLPW modes. - */ -void SMC_PreEnterWaitModes(void) -{ - g_savedPrimask = DisableGlobalIRQ(); - __ISB(); -} - -/*! - * brief Recovers after wake up from stop modes. - * - * This function should be called after wake up from WAIT/VLPW modes. - * It is used with ref SMC_PreEnterWaitModes. - */ -void SMC_PostExitWaitModes(void) -{ - EnableGlobalIRQ(g_savedPrimask); - __ISB(); -} - -/*! - * brief Configures the system to RUN power mode. - * - * param base SMC peripheral base address. - * return SMC configuration error code. - */ -status_t SMC_SetPowerModeRun(SMC_Type *base) -{ - uint8_t reg; - - reg = base->PMCTRL; - /* configure Normal RUN mode */ - reg &= ~(uint8_t)SMC_PMCTRL_RUNM_MASK; - reg |= ((uint8_t)kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); - base->PMCTRL = reg; - - return kStatus_Success; -} - -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) -/*! - * brief Configures the system to HSRUN power mode. - * - * param base SMC peripheral base address. - * return SMC configuration error code. - */ -status_t SMC_SetPowerModeHsrun(SMC_Type *base) -{ - uint8_t reg; - - reg = base->PMCTRL; - /* configure High Speed RUN mode */ - reg &= ~SMC_PMCTRL_RUNM_MASK; - reg |= ((uint8_t)kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); - base->PMCTRL = reg; - - return kStatus_Success; -} -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ - -/*! - * brief Configures the system to WAIT power mode. - * - * param base SMC peripheral base address. - * return SMC configuration error code. - */ -status_t SMC_SetPowerModeWait(SMC_Type *base) -{ - /* configure Normal Wait mode */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __WFI(); - __ISB(); - - return kStatus_Success; -} - -/*! - * brief Configures the system to Stop power mode. - * - * param base SMC peripheral base address. - * param option Partial Stop mode option. - * return SMC configuration error code. - */ -status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) -{ - uint8_t reg; - -#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO) - /* configure the Partial Stop mode in Normal Stop mode */ - reg = base->STOPCTRL; - reg &= ~(uint8_t)SMC_STOPCTRL_PSTOPO_MASK; - reg |= ((uint8_t)option << SMC_STOPCTRL_PSTOPO_SHIFT); - base->STOPCTRL = reg; -#endif - - /* configure Normal Stop mode */ - reg = base->PMCTRL; - reg &= ~(uint8_t)SMC_PMCTRL_STOPM_MASK; - reg |= ((uint8_t)kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - - /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - SMC_EnterStopRamFunc(); - - /* check whether the power mode enter Stop mode succeed */ - if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -} - -/*! - * brief Configures the system to VLPR power mode. - * - * param base SMC peripheral base address. - * return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlpr(SMC_Type *base -#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) - , - bool wakeupMode -#endif -) -{ - uint8_t reg; - - reg = base->PMCTRL; -#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) - /* configure whether the system remains in VLP mode on an interrupt */ - if (wakeupMode) - { - /* exits to RUN mode on an interrupt */ - reg |= SMC_PMCTRL_LPWUI_MASK; - } - else - { - /* remains in VLP mode on an interrupt */ - reg &= ~(uint8_t)SMC_PMCTRL_LPWUI_MASK; - } -#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ - - /* configure VLPR mode */ - reg &= ~(uint8_t)SMC_PMCTRL_RUNM_MASK; - reg |= ((uint8_t)kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); - base->PMCTRL = reg; - - return kStatus_Success; -} - -/*! - * brief Configures the system to VLPW power mode. - * - * param base SMC peripheral base address. - * return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlpw(SMC_Type *base) -{ - /* configure VLPW mode */ - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __WFI(); - __ISB(); - - return kStatus_Success; -} - -/*! - * brief Configures the system to VLPS power mode. - * - * param base SMC peripheral base address. - * return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlps(SMC_Type *base) -{ - uint8_t reg; - - /* configure VLPS mode */ - reg = base->PMCTRL; - reg &= ~(uint8_t)SMC_PMCTRL_STOPM_MASK; - reg |= ((uint8_t)kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - SMC_EnterStopRamFunc(); - - /* check whether the power mode enter VLPS mode succeed */ - if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -} - -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) -/*! - * brief Configures the system to LLS power mode. - * - * param base SMC peripheral base address. - * return SMC configuration error code. - */ -status_t SMC_SetPowerModeLls(SMC_Type *base -#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ - (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) - , - const smc_power_mode_lls_config_t *config -#endif -) -{ - uint8_t reg; - - /* configure to LLS mode */ - reg = base->PMCTRL; - reg &= ~(uint8_t)SMC_PMCTRL_STOPM_MASK; - reg |= ((uint8_t)kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - -/* configure LLS sub-mode*/ -#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) - reg = base->STOPCTRL; - reg &= ~(uint8_t)SMC_STOPCTRL_LLSM_MASK; - reg |= ((uint8_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); - base->STOPCTRL = reg; -#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ - -#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) - if (config->enableLpoClock) - { - base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; - } - else - { - base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; - } -#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ - - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - SMC_EnterStopRamFunc(); - - /* check whether the power mode enter LLS mode succeed */ - if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -} -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ - -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) -/*! - * brief Configures the system to VLLS power mode. - * - * param base SMC peripheral base address. - * param config The VLLS power mode configuration structure. - * return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config) -{ - uint8_t reg; - -#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ - (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ - (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) - if (config->subMode == kSMC_StopSub0) -#endif - { - /* configure whether the Por Detect work in Vlls0 mode */ - if (true == config->enablePorDetectInVlls0) - { -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) - base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK; -#else - base->STOPCTRL &= ~(uint8_t)SMC_STOPCTRL_PORPO_MASK; -#endif - } - else - { -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) - base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK; -#else - base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK; -#endif - } - } -#endif /* FSL_FEATURE_SMC_HAS_PORPO */ - -#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) - else if (config->subMode == kSMC_StopSub2) - { - /* configure whether the Por Detect work in Vlls0 mode */ - if (true == config->enableRam2InVlls2) - { -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) - base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK; -#else - base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK; -#endif - } - else - { -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) - base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK; -#else - base->STOPCTRL &= ~(uint8_t)SMC_STOPCTRL_RAM2PO_MASK; -#endif - } - } - else - { - /* Add this to fix MISRA C2012 rule15.7 issue: Empty else without comment. */ - } -#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */ - - /* configure to VLLS mode */ - reg = base->PMCTRL; - reg &= ~(uint8_t)SMC_PMCTRL_STOPM_MASK; - reg |= ((uint8_t)kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - -/* configure the VLLS sub-mode */ -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) - reg = base->VLLSCTRL; - reg &= ~SMC_VLLSCTRL_VLLSM_MASK; - reg |= ((uint8_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT); - base->VLLSCTRL = reg; -#else -#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) - reg = base->STOPCTRL; - reg &= ~(uint8_t)SMC_STOPCTRL_LLSM_MASK; - reg |= ((uint8_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); - base->STOPCTRL = reg; -#else - reg = base->STOPCTRL; - reg &= ~SMC_STOPCTRL_VLLSM_MASK; - reg |= ((uint8_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT); - base->STOPCTRL = reg; -#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ -#endif - -#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) - if (config->enableLpoClock) - { - base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; - } - else - { - base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; - } -#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ - - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - SMC_EnterStopRamFunc(); - - /* check whether the power mode enter LLS mode succeed */ - if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -} -#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_smc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_smc.h deleted file mode 100644 index e5c318e..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_smc.h +++ /dev/null @@ -1,421 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SMC_H_ -#define _FSL_SMC_H_ - -#include "fsl_common.h" - -/*! @addtogroup smc */ -/*! @{ */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SMC driver version 2.0.5. */ -#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) -/*@}*/ - -/*! - * @brief Power Modes Protection - */ -typedef enum _smc_power_mode_protection -{ -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) - kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-low-leakage Stop Mode. */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) - kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-leakage Stop Mode. */ -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ - kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-power Mode. */ -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) - kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High-speed Run mode. */ -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ - kSMC_AllowPowerModeAll = (0U -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) - | SMC_PMPROT_AVLLS_MASK -#endif -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) - | SMC_PMPROT_ALLS_MASK -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ - | SMC_PMPROT_AVLP_MASK -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) - | kSMC_AllowPowerModeHsrun -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ - ) /*!< Allow all power mode. */ -} smc_power_mode_protection_t; - -/*! - * @brief Power Modes in PMSTAT - */ -typedef enum _smc_power_state -{ - kSMC_PowerStateRun = 0x01U << 0U, /*!< 0000_0001 - Current power mode is RUN */ - kSMC_PowerStateStop = 0x01U << 1U, /*!< 0000_0010 - Current power mode is STOP */ - kSMC_PowerStateVlpr = 0x01U << 2U, /*!< 0000_0100 - Current power mode is VLPR */ - kSMC_PowerStateVlpw = 0x01U << 3U, /*!< 0000_1000 - Current power mode is VLPW */ - kSMC_PowerStateVlps = 0x01U << 4U, /*!< 0001_0000 - Current power mode is VLPS */ -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) - kSMC_PowerStateLls = 0x01U << 5U, /*!< 0010_0000 - Current power mode is LLS */ -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) - kSMC_PowerStateVlls = 0x01U << 6U, /*!< 0100_0000 - Current power mode is VLLS */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) - kSMC_PowerStateHsrun = 0x01U << 7U /*!< 1000_0000 - Current power mode is HSRUN */ -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ -} smc_power_state_t; - -/*! - * @brief Run mode definition - */ -typedef enum _smc_run_mode -{ - kSMC_RunNormal = 0U, /*!< Normal RUN mode. */ - kSMC_RunVlpr = 2U, /*!< Very-low-power RUN mode. */ -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) - kSMC_Hsrun = 3U /*!< High-speed Run mode (HSRUN). */ -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ -} smc_run_mode_t; - -/*! - * @brief Stop mode definition - */ -typedef enum _smc_stop_mode -{ - kSMC_StopNormal = 0U, /*!< Normal STOP mode. */ - kSMC_StopVlps = 2U, /*!< Very-low-power STOP mode. */ -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) - kSMC_StopLls = 3U, /*!< Low-leakage Stop mode. */ -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) - kSMC_StopVlls = 4U /*!< Very-low-leakage Stop mode. */ -#endif -} smc_stop_mode_t; - -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ - (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ - (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) -/*! - * @brief VLLS/LLS stop sub mode definition - */ -typedef enum _smc_stop_submode -{ - kSMC_StopSub0 = 0U, /*!< Stop submode 0, for VLLS0/LLS0. */ - kSMC_StopSub1 = 1U, /*!< Stop submode 1, for VLLS1/LLS1. */ - kSMC_StopSub2 = 2U, /*!< Stop submode 2, for VLLS2/LLS2. */ - kSMC_StopSub3 = 3U /*!< Stop submode 3, for VLLS3/LLS3. */ -} smc_stop_submode_t; -#endif - -/*! - * @brief Partial STOP option - */ -typedef enum _smc_partial_stop_mode -{ - kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/ - kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/ - kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/ -} smc_partial_stop_option_t; - -/*! - * @brief SMC configuration status. - */ -enum _smc_status -{ - kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0) /*!< Entering Stop mode is abort*/ -}; - -#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) -/*! - * @brief IP version ID definition. - */ -typedef struct _smc_version_id -{ - uint16_t feature; /*!< Feature Specification Number. */ - uint8_t minor; /*!< Minor version number. */ - uint8_t major; /*!< Major version number. */ -} smc_version_id_t; -#endif /* FSL_FEATURE_SMC_HAS_VERID */ - -#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) -/*! - * @brief IP parameter definition. - */ -typedef struct _smc_param -{ - bool hsrunEnable; /*!< HSRUN mode enable. */ - bool llsEnable; /*!< LLS mode enable. */ - bool lls2Enable; /*!< LLS2 mode enable. */ - bool vlls0Enable; /*!< VLLS0 mode enable. */ -} smc_param_t; -#endif /* FSL_FEATURE_SMC_HAS_PARAM */ - -#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ - (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) -/*! - * @brief SMC Low-Leakage Stop power mode configuration. - */ -typedef struct _smc_power_mode_lls_config -{ -#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) - smc_stop_submode_t subMode; /*!< Low-leakage Stop sub-mode */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) - bool enableLpoClock; /*!< Enable LPO clock in LLS mode */ -#endif -} smc_power_mode_lls_config_t; -#endif /* (FSL_FEATURE_SMC_HAS_LLS_SUBMODE || FSL_FEATURE_SMC_HAS_LPOPO) */ - -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) -/*! - * @brief SMC Very Low-Leakage Stop power mode configuration. - */ -typedef struct _smc_power_mode_vlls_config -{ -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ - (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ - (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) - smc_stop_submode_t subMode; /*!< Very Low-leakage Stop sub-mode */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) - bool enablePorDetectInVlls0; /*!< Enable Power on reset detect in VLLS mode */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) - bool enableRam2InVlls2; /*!< Enable RAM2 power in VLLS2 */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) - bool enableLpoClock; /*!< Enable LPO clock in VLLS mode */ -#endif -} smc_power_mode_vlls_config_t; -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! @name System mode controller APIs*/ -/*@{*/ - -#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) -/*! - * @brief Gets the SMC version ID. - * - * This function gets the SMC version ID, including major version number, - * minor version number, and feature specification number. - * - * @param base SMC peripheral base address. - * @param versionId Pointer to the version ID structure. - */ -static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId) -{ - *((uint32_t *)versionId) = base->VERID; -} -#endif /* FSL_FEATURE_SMC_HAS_VERID */ - -#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) -/*! - * @brief Gets the SMC parameter. - * - * This function gets the SMC parameter including the enabled power mdoes. - * - * @param base SMC peripheral base address. - * @param param Pointer to the SMC param structure. - */ -void SMC_GetParam(SMC_Type *base, smc_param_t *param); -#endif - -/*! - * @brief Configures all power mode protection settings. - * - * This function configures the power mode protection settings for - * supported power modes in the specified chip family. The available power modes - * are defined in the smc_power_mode_protection_t. This should be done at an early - * system level initialization stage. See the reference manual for details. - * This register can only write once after the power reset. - * - * The allowed modes are passed as bit map. For example, to allow LLS and VLLS, - * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps). - * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll). - * - * @param base SMC peripheral base address. - * @param allowedModes Bitmap of the allowed power modes. - */ -static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes) -{ - base->PMPROT = allowedModes; -} - -/*! - * @brief Gets the current power mode status. - * - * This function returns the current power mode status. After the application - * switches the power mode, it should always check the status to check whether it - * runs into the specified mode or not. The application should check - * this mode before switching to a different mode. The system requires that - * only certain modes can switch to other specific modes. See the - * reference manual for details and the smc_power_state_t for information about - * the power status. - * - * @param base SMC peripheral base address. - * @return Current power mode status. - */ -static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base) -{ - return (smc_power_state_t)base->PMSTAT; -} - -/*! - * @brief Prepares to enter stop modes. - * - * This function should be called before entering STOP/VLPS/LLS/VLLS modes. - */ -void SMC_PreEnterStopModes(void); - -/*! - * @brief Recovers after wake up from stop modes. - * - * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes. - * It is used with @ref SMC_PreEnterStopModes. - */ -void SMC_PostExitStopModes(void); - -/*! - * @brief Prepares to enter wait modes. - * - * This function should be called before entering WAIT/VLPW modes. - */ -void SMC_PreEnterWaitModes(void); - -/*! - * @brief Recovers after wake up from stop modes. - * - * This function should be called after wake up from WAIT/VLPW modes. - * It is used with @ref SMC_PreEnterWaitModes. - */ -void SMC_PostExitWaitModes(void); - -/*! - * @brief Configures the system to RUN power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeRun(SMC_Type *base); - -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) -/*! - * @brief Configures the system to HSRUN power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeHsrun(SMC_Type *base); -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ - -/*! - * @brief Configures the system to WAIT power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeWait(SMC_Type *base); - -/*! - * @brief Configures the system to Stop power mode. - * - * @param base SMC peripheral base address. - * @param option Partial Stop mode option. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option); - -#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) -/*! - * @brief Configures the system to VLPR power mode. - * - * @param base SMC peripheral base address. - * @param wakeupMode Enter Normal Run mode if true, else stay in VLPR mode. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode); -#else -/*! - * @brief Configures the system to VLPR power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlpr(SMC_Type *base); -#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ - -/*! - * @brief Configures the system to VLPW power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlpw(SMC_Type *base); - -/*! - * @brief Configures the system to VLPS power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlps(SMC_Type *base); - -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) -#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ - (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) -/*! - * @brief Configures the system to LLS power mode. - * - * @param base SMC peripheral base address. - * @param config The LLS power mode configuration structure - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config); -#else -/*! - * @brief Configures the system to LLS power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeLls(SMC_Type *base); -#endif -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ - -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) -/*! - * @brief Configures the system to VLLS power mode. - * - * @param base SMC peripheral base address. - * @param config The VLLS power mode configuration structure. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config); -#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_SMC_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart.c deleted file mode 100644 index 121be44..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart.c +++ /dev/null @@ -1,1128 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_uart.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* UART transfer state. */ -enum _uart_tansfer_states -{ - kUART_TxIdle, /* TX idle. */ - kUART_TxBusy, /* TX busy. */ - kUART_RxIdle, /* RX idle. */ - kUART_RxBusy /* RX busy. */ -}; - -/* Typedef for interrupt handler. */ -typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the UART instance from peripheral base address. - * - * @param base UART peripheral base address. - * @return UART instance. - */ -uint32_t UART_GetInstance(UART_Type *base); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @param handle UART handle pointer. - * @return Length of received data in RX ring buffer. - */ -static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); - -/*! - * @brief Check whether the RX ring buffer is full. - * - * @param handle UART handle pointer. - * @retval true RX ring buffer is full. - * @retval false RX ring buffer is not full. - */ -static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle); - -/*! - * @brief Read RX register using non-blocking method. - * - * This function reads data from the TX register directly, upper layer must make - * sure the RX register is full or TX FIFO has data before calling this function. - * - * @param base UART peripheral base address. - * @param data Start addresss of the buffer to store the received data. - * @param length Size of the buffer. - */ -static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length); - -/*! - * @brief Write to TX register using non-blocking method. - * - * This function writes data to the TX register directly, upper layer must make - * sure the TX register is empty or TX FIFO has empty room before calling this function. - * - * @note This function does not check whether all the data has been sent out to bus, - * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is - * finished. - * - * @param base UART peripheral base address. - * @param data Start addresss of the data to write. - * @param length Size of the buffer to be sent. - */ -static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of UART handle. */ -#if (defined(UART5)) -#define UART_HANDLE_ARRAY_SIZE 6 -#else /* UART5 */ -#if (defined(UART4)) -#define UART_HANDLE_ARRAY_SIZE 5 -#else /* UART4 */ -#if (defined(UART3)) -#define UART_HANDLE_ARRAY_SIZE 4 -#else /* UART3 */ -#if (defined(UART2)) -#define UART_HANDLE_ARRAY_SIZE 3 -#else /* UART2 */ -#if (defined(UART1)) -#define UART_HANDLE_ARRAY_SIZE 2 -#else /* UART1 */ -#if (defined(UART0)) -#define UART_HANDLE_ARRAY_SIZE 1 -#else /* UART0 */ -#error No UART instance. -#endif /* UART 0 */ -#endif /* UART 1 */ -#endif /* UART 2 */ -#endif /* UART 3 */ -#endif /* UART 4 */ -#endif /* UART 5 */ -static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE]; -/* Array of UART peripheral base address. */ -static UART_Type *const s_uartBases[] = UART_BASE_PTRS; - -/* Array of UART IRQ number. */ -static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS; -/* Array of UART clock name. */ -static const clock_ip_name_t s_uartClock[] = UART_CLOCKS; - -/* UART ISR for transactional APIs. */ -static uart_isr_t s_uartIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ - -uint32_t UART_GetInstance(UART_Type *base) -{ - uint32_t instance; - uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < uartArrayCount; instance++) - { - if (s_uartBases[instance] == base) - { - break; - } - } - - assert(instance < uartArrayCount); - - return instance; -} - -static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) -{ - assert(handle); - - size_t size; - - if (handle->rxRingBufferTail > handle->rxRingBufferHead) - { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); - } - else - { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); - } - - return size; -} - -static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle) -{ - assert(handle); - - bool full; - - if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - - return full; -} - -status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz) -{ - assert(config); - assert(config->baudRate_Bps); -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark); - assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark); -#endif - - uint16_t sbr = 0; - uint8_t temp = 0; - uint32_t baudDiff = 0; - - /* Calculate the baud rate modulo divisor, sbr*/ - sbr = srcClock_Hz / (config->baudRate_Bps * 16); - /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */ - if (sbr == 0) - { - sbr = 1; - } -#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT - /* Determine if a fractional divider is needed to fine tune closer to the - * desired baud, each value of brfa is in 1/32 increments, - * hence the multiply-by-32. */ - uint16_t brfa = (32 * srcClock_Hz / (config->baudRate_Bps * 16)) - 32 * sbr; - - /* Calculate the baud rate based on the temporary SBR values and BRFA */ - baudDiff = (srcClock_Hz * 2 / ((sbr * 32 + brfa))) - config->baudRate_Bps; - -#else - /* Calculate the baud rate based on the temporary SBR values */ - baudDiff = (srcClock_Hz / (sbr * 16)) - config->baudRate_Bps; - - /* Select the better value between sbr and (sbr + 1) */ - if (baudDiff > (config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1))))) - { - baudDiff = config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1))); - sbr++; - } -#endif - - /* next, check to see if actual baud rate is within 3% of desired baud rate - * based on the calculate SBR value */ - if (baudDiff > ((config->baudRate_Bps / 100) * 3)) - { - /* Unacceptable baud rate difference of more than 3%*/ - return kStatus_UART_BaudrateNotSupport; - } - - /* Enable uart clock */ - CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]); - - /* Disable UART TX RX before setting. */ - base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); - - /* Write the sbr value to the BDH and BDL registers*/ - base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); - base->BDL = (uint8_t)sbr; - -#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT - /* Write the brfa value to the register*/ - base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); -#endif - - /* Set bit count and parity mode. */ - temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); - - if (kUART_ParityDisabled != config->parityMode) - { - temp |= (UART_C1_M_MASK | (uint8_t)config->parityMode); - } - - base->C1 = temp; - -#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT - /* Set stop bit per char */ - base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)config->stopBitCount); -#endif - -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - /* Set tx/rx FIFO watermark */ - base->TWFIFO = config->txFifoWatermark; - base->RWFIFO = config->rxFifoWatermark; - - /* Enable tx/rx FIFO */ - base->PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK); - - /* Flush FIFO */ - base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK); -#endif - - /* Enable TX/RX base on configure structure. */ - temp = base->C2; - - if (config->enableTx) - { - temp |= UART_C2_TE_MASK; - } - - if (config->enableRx) - { - temp |= UART_C2_RE_MASK; - } - - base->C2 = temp; - - return kStatus_Success; -} - -void UART_Deinit(UART_Type *base) -{ -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - /* Wait tx FIFO send out*/ - while (0 != base->TCFIFO) - { - } -#endif - /* Wait last char shoft out */ - while (0 == (base->S1 & UART_S1_TC_MASK)) - { - } - - /* Disable the module. */ - base->C2 = 0; - - /* Disable uart clock */ - CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]); -} - -void UART_GetDefaultConfig(uart_config_t *config) -{ - assert(config); - - config->baudRate_Bps = 115200U; - config->parityMode = kUART_ParityDisabled; -#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT - config->stopBitCount = kUART_OneStopBit; -#endif -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - config->txFifoWatermark = 0; - config->rxFifoWatermark = 1; -#endif - config->enableTx = false; - config->enableRx = false; -} - -status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - assert(baudRate_Bps); - - uint16_t sbr = 0; - uint32_t baudDiff = 0; - uint8_t oldCtrl; - - /* Calculate the baud rate modulo divisor, sbr*/ - sbr = srcClock_Hz / (baudRate_Bps * 16); - /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */ - if (sbr == 0) - { - sbr = 1; - } -#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT - /* Determine if a fractional divider is needed to fine tune closer to the - * desired baud, each value of brfa is in 1/32 increments, - * hence the multiply-by-32. */ - uint16_t brfa = (32 * srcClock_Hz / (baudRate_Bps * 16)) - 32 * sbr; - - /* Calculate the baud rate based on the temporary SBR values and BRFA */ - baudDiff = (srcClock_Hz * 2 / ((sbr * 32 + brfa))) - baudRate_Bps; - -#else - /* Calculate the baud rate based on the temporary SBR values */ - baudDiff = (srcClock_Hz / (sbr * 16)) - baudRate_Bps; - - /* Select the better value between sbr and (sbr + 1) */ - if (baudDiff > (baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1))))) - { - baudDiff = baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1))); - sbr++; - } -#endif - - /* next, check to see if actual baud rate is within 3% of desired baud rate - * based on the calculate SBR value */ - if (baudDiff < ((baudRate_Bps / 100) * 3)) - { - /* Store C2 before disable Tx and Rx */ - oldCtrl = base->C2; - - /* Disable UART TX RX before setting. */ - base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); - - /* Write the sbr value to the BDH and BDL registers*/ - base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); - base->BDL = (uint8_t)sbr; - -#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT - /* Write the brfa value to the register*/ - base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); -#endif - /* Restore C2. */ - base->C2 = oldCtrl; - - return kStatus_Success; - } - else - { - /* Unacceptable baud rate difference of more than 3%*/ - return kStatus_UART_BaudrateNotSupport; - } -} - -void UART_EnableInterrupts(UART_Type *base, uint32_t mask) -{ - mask &= kUART_AllInterruptsEnable; - - /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) - */ - base->BDH |= mask; - base->C2 |= (mask >> 8); - base->C3 |= (mask >> 16); - -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - base->CFIFO |= (mask >> 24); -#endif -} - -void UART_DisableInterrupts(UART_Type *base, uint32_t mask) -{ - mask &= kUART_AllInterruptsEnable; - - /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) - */ - base->BDH &= ~mask; - base->C2 &= ~(mask >> 8); - base->C3 &= ~(mask >> 16); - -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - base->CFIFO &= ~(mask >> 24); -#endif -} - -uint32_t UART_GetEnabledInterrupts(UART_Type *base) -{ - uint32_t temp; - - temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16); - -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - temp |= ((uint32_t)(base->CFIFO) << 24); -#endif - - return temp & kUART_AllInterruptsEnable; -} - -uint32_t UART_GetStatusFlags(UART_Type *base) -{ - uint32_t status_flag; - - status_flag = base->S1 | ((uint32_t)(base->S2) << 8); - -#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS - status_flag |= ((uint32_t)(base->ED) << 16); -#endif - -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - status_flag |= ((uint32_t)(base->SFIFO) << 24); -#endif - - return status_flag; -} - -status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask) -{ - uint8_t reg = base->S2; - status_t status; - -#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT - reg &= ~(UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK); -#else - reg &= ~UART_S2_RXEDGIF_MASK; -#endif - - base->S2 = reg | (uint8_t)(mask >> 8); - -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - base->SFIFO = (uint8_t)(mask >> 24); -#endif - - if (mask & (kUART_IdleLineFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | - kUART_ParityErrorFlag)) - { - /* Read base->D to clear the flags. */ - (void)base->S1; - (void)base->D; - } - - if (mask & kUART_RxOverrunFlag) - { - /* Read base->D to clear the flags and Flush all data in FIFO. */ - (void)base->S1; - (void)base->D; -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */ - base->CFIFO |= UART_CFIFO_RXFLUSH_MASK; -#endif - } - - /* If some flags still pending. */ - if (mask & UART_GetStatusFlags(base)) - { - /* Some flags can only clear or set by the hardware itself, these flags are: kUART_TxDataRegEmptyFlag, - kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, - kUART_ParityErrorInRxDataRegFlag, kUART_TxFifoEmptyFlag, kUART_RxFifoEmptyFlag. */ - status = kStatus_UART_FlagCannotClearManually; - } - else - { - status = kStatus_Success; - } - - return status; -} - -void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length) -{ - /* This API can only ensure that the data is written into the data buffer but can't - ensure all data in the data buffer are sent into the transmit shift buffer. */ - while (length--) - { - while (!(base->S1 & UART_S1_TDRE_MASK)) - { - } - base->D = *(data++); - } -} - -static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length) -{ - assert(data); - - size_t i; - - /* The Non Blocking write data API assume user have ensured there is enough space in - peripheral to write. */ - for (i = 0; i < length; i++) - { - base->D = data[i]; - } -} - -status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length) -{ - assert(data); - - uint32_t statusFlag; - - while (length--) - { -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - while (!base->RCFIFO) -#else - while (!(base->S1 & UART_S1_RDRF_MASK)) -#endif - { - statusFlag = UART_GetStatusFlags(base); - - if (statusFlag & kUART_RxOverrunFlag) - { - return kStatus_UART_RxHardwareOverrun; - } - - if (statusFlag & kUART_NoiseErrorFlag) - { - return kStatus_UART_NoiseError; - } - - if (statusFlag & kUART_FramingErrorFlag) - { - return kStatus_UART_FramingError; - } - - if (statusFlag & kUART_ParityErrorFlag) - { - return kStatus_UART_ParityError; - } - } - *(data++) = base->D; - } - - return kStatus_Success; -} - -static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length) -{ - assert(data); - - size_t i; - - /* The Non Blocking read data API assume user have ensured there is enough space in - peripheral to write. */ - for (i = 0; i < length; i++) - { - data[i] = base->D; - } -} - -void UART_TransferCreateHandle(UART_Type *base, - uart_handle_t *handle, - uart_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - uint32_t instance; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set the TX/RX state. */ - handle->rxState = kUART_RxIdle; - handle->txState = kUART_TxIdle; - - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - /* Note: - Take care of the RX FIFO, RX interrupt request only assert when received bytes - equal or more than RX water mark, there is potential issue if RX water - mark larger than 1. - For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and - 5 bytes are received. the last byte will be saved in FIFO but not trigger - RX interrupt because the water mark is 2. - */ - base->RWFIFO = 1U; -#endif - - /* Get instance from peripheral base address. */ - instance = UART_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_uartHandle[instance] = handle; - - s_uartIsr = UART_TransferHandleIRQ; - - /* Enable interrupt in NVIC. */ - EnableIRQ(s_uartIRQ[instance]); -} - -void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - assert(handle); - assert(ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - - /* Enable the interrupt to accept the data when user need the ring buffer. */ - UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); -} - -void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) -{ - assert(handle); - - if (handle->rxState == kUART_RxIdle) - { - UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); - } - - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - assert(xfer->dataSize); - assert(xfer->data); - - status_t status; - - /* Return error if current TX busy. */ - if (kUART_TxBusy == handle->txState) - { - status = kStatus_UART_TxBusy; - } - else - { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = kUART_TxBusy; - - /* Enable transmiter interrupt. */ - UART_EnableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable); - - status = kStatus_Success; - } - - return status; -} - -void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) -{ - assert(handle); - - UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable); - - handle->txDataSize = 0; - handle->txState = kUART_TxIdle; -} - -status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(count); - - if (kUART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize; - - return kStatus_Success; -} - -status_t UART_TransferReceiveNonBlocking(UART_Type *base, - uart_handle_t *handle, - uart_transfer_t *xfer, - size_t *receivedBytes) -{ - assert(handle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - uint32_t i; - status_t status; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t regPrimask = 0U; - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - - if (kUART_RxBusy == handle->rxState) - { - status = kStatus_UART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) - { - /* Disable IRQ, protect ring buffer. */ - regPrimask = DisableGlobalIRQ(); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = UART_TransferGetRxRingBufferLength(handle); - - if (bytesToCopy) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - - bytesToReceive -= bytesToCopy; - - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUART_RxBusy; - } - - /* Enable IRQ if previously enabled. */ - EnableGlobalIRQ(regPrimask); - - /* Call user callback since all data are received. */ - if (0 == bytesToReceive) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUART_RxBusy; - - /* Enable RX interrupt. */ - UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); - } - - /* Return the how many bytes have read. */ - if (receivedBytes) - { - *receivedBytes = bytesCurrentReceived; - } - - status = kStatus_Success; - } - - return status; -} - -void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) -{ - assert(handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) - { - /* Disable RX interrupt. */ - UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); - } - - handle->rxDataSize = 0U; - handle->rxState = kUART_RxIdle; -} - -status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(count); - - if (kUART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - if (!count) - { - return kStatus_InvalidArgument; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) -{ - assert(handle); - - uint8_t count; - uint8_t tempCount; - - /* If RX overrun. */ - if (UART_S1_OR_MASK & base->S1) - { - /* Read base->D to clear overrun flag, otherwise the RX does not work. */ - (void)base->D; -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */ - base->CFIFO |= UART_CFIFO_RXFLUSH_MASK; -#endif - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData); - } - } - - /* Receive data register full */ - if ((UART_S1_RDRF_MASK & base->S1) && (UART_C2_RIE_MASK & base->C2)) - { -/* Get the size that can be stored into buffer for this interrupt. */ -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - count = base->RCFIFO; -#else - count = 1; -#endif - - /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ - while ((count) && (handle->rxDataSize)) - { -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - tempCount = MIN(handle->rxDataSize, count); -#else - tempCount = 1; -#endif - - /* Using non block API to read the data from the registers. */ - UART_ReadNonBlocking(base, handle->rxData, tempCount); - handle->rxData += tempCount; - handle->rxDataSize -= tempCount; - count -= tempCount; - - /* If all the data required for upper layer is ready, trigger callback. */ - if (!handle->rxDataSize) - { - handle->rxState = kUART_RxIdle; - - if (handle->callback) - { - handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); - } - } - } - - /* If use RX ring buffer, receive data to ring buffer. */ - if (handle->rxRingBuffer) - { - while (count--) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (UART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); - } - } - - /* If ring buffer is still full after callback function, the oldest data is overrided. */ - if (UART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - - /* Read data. */ - handle->rxRingBuffer[handle->rxRingBufferHead] = base->D; - - /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - /* If no receive requst pending, stop RX interrupt. */ - else if (!handle->rxDataSize) - { - UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); - } - else - { - } - } - - /* Send data register empty and the interrupt is enabled. */ - if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK)) - { -/* Get the bytes that available at this moment. */ -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - count = FSL_FEATURE_UART_FIFO_SIZEn(base) - base->TCFIFO; -#else - count = 1; -#endif - - while ((count) && (handle->txDataSize)) - { -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - tempCount = MIN(handle->txDataSize, count); -#else - tempCount = 1; -#endif - - /* Using non block API to write the data to the registers. */ - UART_WriteNonBlocking(base, handle->txData, tempCount); - handle->txData += tempCount; - handle->txDataSize -= tempCount; - count -= tempCount; - - /* If all the data are written to data register, TX finished. */ - if (!handle->txDataSize) - { - handle->txState = kUART_TxIdle; - - /* Disable TX register empty interrupt. */ - base->C2 = (base->C2 & ~UART_C2_TIE_MASK); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData); - } - } - } - } -} - -void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle) -{ - /* To be implemented by User. */ -} - -#if defined(UART0) -#if ((!(defined(FSL_FEATURE_SOC_LPSCI_COUNT))) || \ - ((defined(FSL_FEATURE_SOC_LPSCI_COUNT)) && (FSL_FEATURE_SOC_LPSCI_COUNT == 0))) -void UART0_DriverIRQHandler(void) -{ - s_uartIsr(UART0, s_uartHandle[0]); -} - -void UART0_RX_TX_DriverIRQHandler(void) -{ - UART0_DriverIRQHandler(); -} -#endif -#endif - -#if defined(UART1) -void UART1_DriverIRQHandler(void) -{ - s_uartIsr(UART1, s_uartHandle[1]); -} - -void UART1_RX_TX_DriverIRQHandler(void) -{ - UART1_DriverIRQHandler(); -} -#endif - -#if defined(UART2) -void UART2_DriverIRQHandler(void) -{ - s_uartIsr(UART2, s_uartHandle[2]); -} - -void UART2_RX_TX_DriverIRQHandler(void) -{ - UART2_DriverIRQHandler(); -} - -#endif - -#if defined(UART3) -void UART3_DriverIRQHandler(void) -{ - s_uartIsr(UART3, s_uartHandle[3]); -} - -void UART3_RX_TX_DriverIRQHandler(void) -{ - UART3_DriverIRQHandler(); -} -#endif - -#if defined(UART4) -void UART4_DriverIRQHandler(void) -{ - s_uartIsr(UART4, s_uartHandle[4]); -} - -void UART4_RX_TX_DriverIRQHandler(void) -{ - UART4_DriverIRQHandler(); -} -#endif - -#if defined(UART5) -void UART5_DriverIRQHandler(void) -{ - s_uartIsr(UART5, s_uartHandle[5]); -} - -void UART5_RX_TX_DriverIRQHandler(void) -{ - UART5_DriverIRQHandler(); -} -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart.h deleted file mode 100644 index 16f486a..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart.h +++ /dev/null @@ -1,774 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_UART_H_ -#define _FSL_UART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup uart_driver - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief UART driver version 2.1.1. */ -#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -/*! @brief Error codes for the UART driver. */ -enum _uart_status -{ - kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_UART, 0), /*!< Transmitter is busy. */ - kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_UART, 1), /*!< Receiver is busy. */ - kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_UART, 2), /*!< UART transmitter is idle. */ - kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_UART, 3), /*!< UART receiver is idle. */ - kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 4), /*!< TX FIFO watermark too large */ - kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 5), /*!< RX FIFO watermark too large */ - kStatus_UART_FlagCannotClearManually = - MAKE_STATUS(kStatusGroup_UART, 6), /*!< UART flag can't be manually cleared. */ - kStatus_UART_Error = MAKE_STATUS(kStatusGroup_UART, 7), /*!< Error happens on UART. */ - kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_UART, 8), /*!< UART RX software ring buffer overrun. */ - kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_UART, 9), /*!< UART RX receiver overrun. */ - kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_UART, 10), /*!< UART noise error. */ - kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 11), /*!< UART framing error. */ - kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12), /*!< UART parity error. */ - kStatus_UART_BaudrateNotSupport = MAKE_STATUS(kStatusGroup_UART, 13), /*!< Baudrate is not support in current clock source */ -}; - -/*! @brief UART parity mode. */ -typedef enum _uart_parity_mode -{ - kUART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} uart_parity_mode_t; - -/*! @brief UART stop bit count. */ -typedef enum _uart_stop_bit_count -{ - kUART_OneStopBit = 0U, /*!< One stop bit */ - kUART_TwoStopBit = 1U, /*!< Two stop bits */ -} uart_stop_bit_count_t; - -/*! - * @brief UART interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the UART interrupt configurations. - */ -enum _uart_interrupt_enable -{ -#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT - kUART_LinBreakInterruptEnable = (UART_BDH_LBKDIE_MASK), /*!< LIN break detect interrupt. */ -#endif - kUART_RxActiveEdgeInterruptEnable = (UART_BDH_RXEDGIE_MASK), /*!< RX active edge interrupt. */ - kUART_TxDataRegEmptyInterruptEnable = (UART_C2_TIE_MASK << 8), /*!< Transmit data register empty interrupt. */ - kUART_TransmissionCompleteInterruptEnable = (UART_C2_TCIE_MASK << 8), /*!< Transmission complete interrupt. */ - kUART_RxDataRegFullInterruptEnable = (UART_C2_RIE_MASK << 8), /*!< Receiver data register full interrupt. */ - kUART_IdleLineInterruptEnable = (UART_C2_ILIE_MASK << 8), /*!< Idle line interrupt. */ - kUART_RxOverrunInterruptEnable = (UART_C3_ORIE_MASK << 16), /*!< Receiver overrun interrupt. */ - kUART_NoiseErrorInterruptEnable = (UART_C3_NEIE_MASK << 16), /*!< Noise error flag interrupt. */ - kUART_FramingErrorInterruptEnable = (UART_C3_FEIE_MASK << 16), /*!< Framing error flag interrupt. */ - kUART_ParityErrorInterruptEnable = (UART_C3_PEIE_MASK << 16), /*!< Parity error flag interrupt. */ -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_RXOFE_MASK << 24), /*!< RX FIFO overflow interrupt. */ - kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24), /*!< TX FIFO overflow interrupt. */ - kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */ -#endif - kUART_AllInterruptsEnable = -#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT - kUART_LinBreakInterruptEnable | -#endif - kUART_RxActiveEdgeInterruptEnable | kUART_TxDataRegEmptyInterruptEnable | - kUART_TransmissionCompleteInterruptEnable | kUART_RxDataRegFullInterruptEnable | - kUART_IdleLineInterruptEnable | kUART_RxOverrunInterruptEnable | kUART_NoiseErrorInterruptEnable | - kUART_FramingErrorInterruptEnable | kUART_ParityErrorInterruptEnable -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - | kUART_RxFifoOverflowInterruptEnable | kUART_TxFifoOverflowInterruptEnable - | kUART_RxFifoUnderflowInterruptEnable -#endif - , -}; - -/*! - * @brief UART status flags. - * - * This provides constants for the UART status flags for use in the UART functions. - */ -enum _uart_flags -{ - kUART_TxDataRegEmptyFlag = (UART_S1_TDRE_MASK), /*!< TX data register empty flag. */ - kUART_TransmissionCompleteFlag = (UART_S1_TC_MASK), /*!< Transmission complete flag. */ - kUART_RxDataRegFullFlag = (UART_S1_RDRF_MASK), /*!< RX data register full flag. */ - kUART_IdleLineFlag = (UART_S1_IDLE_MASK), /*!< Idle line detect flag. */ - kUART_RxOverrunFlag = (UART_S1_OR_MASK), /*!< RX overrun flag. */ - kUART_NoiseErrorFlag = (UART_S1_NF_MASK), /*!< RX takes 3 samples of each received bit. - If any of these samples differ, noise flag sets */ - kUART_FramingErrorFlag = (UART_S1_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected - where stop bit expected */ - kUART_ParityErrorFlag = (UART_S1_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ -#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT - kUART_LinBreakFlag = - (UART_S2_LBKDIF_MASK << 8), /*!< LIN break detect interrupt flag, sets when - LIN break char detected and LIN circuit enabled */ -#endif - kUART_RxActiveEdgeFlag = (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag, - sets when active edge detected */ - kUART_RxActiveFlag = (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF), - sets at beginning of valid start bit */ -#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS - kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16), /*!< Noisy bit, sets if noise detected. */ - kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Paritye bit, sets if parity error detected. */ -#endif -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - kUART_TxFifoEmptyFlag = (UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */ - kUART_RxFifoEmptyFlag = (UART_SFIFO_RXEMPT_MASK << 24), /*!< RXEMPT bit, sets if RX buffer is empty */ - kUART_TxFifoOverflowFlag = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */ - kUART_RxFifoOverflowFlag = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */ - kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */ -#endif -}; - -/*! @brief UART configuration structure. */ -typedef struct _uart_config -{ - uint32_t baudRate_Bps; /*!< UART baud rate */ - uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ -#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT - uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ -#endif -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - uint8_t txFifoWatermark; /*!< TX FIFO watermark */ - uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ -#endif - bool enableTx; /*!< Enable TX */ - bool enableRx; /*!< Enable RX */ -} uart_config_t; - -/*! @brief UART transfer structure. */ -typedef struct _uart_transfer -{ - uint8_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} uart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _uart_handle uart_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); - -/*! @brief UART handle structure. */ -struct _uart_handle -{ - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - uart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a UART instance with user configuration structure and peripheral clock. - * - * This function configures the UART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the UART_GetDefaultConfig() function. - * Example below shows how to use this API to configure UART. - * @code - * uart_config_t uartConfig; - * uartConfig.baudRate_Bps = 115200U; - * uartConfig.parityMode = kUART_ParityDisabled; - * uartConfig.stopBitCount = kUART_OneStopBit; - * uartConfig.txFifoWatermark = 0; - * uartConfig.rxFifoWatermark = 1; - * UART_Init(UART1, &uartConfig, 20000000U); - * @endcode - * - * @param base UART peripheral base address. - * @param config Pointer to user-defined configuration structure. - * @param srcClock_Hz UART clock source frequency in HZ. - * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Status UART initialize succeed - */ -status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a UART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the UART clock. - * - * @param base UART peripheral base address. - */ -void UART_Deinit(UART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the UART configuration structure to a default value. The default - * values are: - * uartConfig->baudRate_Bps = 115200U; - * uartConfig->bitCountPerChar = kUART_8BitsPerChar; - * uartConfig->parityMode = kUART_ParityDisabled; - * uartConfig->stopBitCount = kUART_OneStopBit; - * uartConfig->txFifoWatermark = 0; - * uartConfig->rxFifoWatermark = 1; - * uartConfig->enableTx = false; - * uartConfig->enableRx = false; - * - * @param config Pointer to configuration structure. - */ -void UART_GetDefaultConfig(uart_config_t *config); - -/*! - * @brief Sets the UART instance baud rate. - * - * This function configures the UART module baud rate. This function is used to update - * the UART module baud rate after the UART module is initialized by the UART_Init. - * @code - * UART_SetBaudRate(UART1, 115200U, 20000000U); - * @endcode - * - * @param base UART peripheral base address. - * @param baudRate_Bps UART baudrate to be set. - * @param srcClock_Hz UART clock source freqency in HZ. - * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed - */ -status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get UART status flags. - * - * This function get all UART status flags, the flags are returned as the logical - * OR value of the enumerators @ref _uart_flags. To check a specific status, - * compare the return value with enumerators in @ref _uart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1)) - * { - * ... - * } - * @endcode - * - * @param base UART peripheral base address. - * @return UART status flags which are ORed by the enumerators in the _uart_flags. - */ -uint32_t UART_GetStatusFlags(UART_Type *base); - -/*! - * @brief Clears status flags with the provided mask. - * - * This function clears UART status flags with a provided mask. Automatically cleared flag - * can't be cleared by this function. - * Some flags can only be cleared or set by hardware itself. These flags are: - * kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, - * kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag, - * kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag - * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. - * - * @param base UART peripheral base address. - * @param mask The status flags to be cleared, it is logical OR value of @ref _uart_flags. - * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but - * it is cleared automatically by hardware. - * @retval kStatus_Success Status in the mask are cleared. - */ -status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables UART interrupts according to the provided mask. - * - * This function enables the UART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. - * For example, to enable TX empty interrupt and RX full interrupt: - * @code - * UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); - * @endcode - * - * @param base UART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. - */ -void UART_EnableInterrupts(UART_Type *base, uint32_t mask); - -/*! - * @brief Disables the UART interrupts according to the provided mask. - * - * This function disables the UART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. - * For example, to disable TX empty interrupt and RX full interrupt: - * @code - * UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); - * @endcode - * - * @param base UART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable. - */ -void UART_DisableInterrupts(UART_Type *base, uint32_t mask); - -/*! - * @brief Gets the enabled UART interrupts. - * - * This function gets the enabled UART interrupts. The enabled interrupts are returned - * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check - * a specific interrupts enable status, compare the return value with enumerators - * in @ref _uart_interrupt_enable. - * For example, to check whether TX empty interrupt is enabled: - * @code - * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); - * - * if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) - * { - * ... - * } - * @endcode - * - * @param base UART peripheral base address. - * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable. - */ -uint32_t UART_GetEnabledInterrupts(UART_Type *base); - -/* @} */ - -#if defined(FSL_FEATURE_UART_HAS_DMA_SELECT) && FSL_FEATURE_UART_HAS_DMA_SELECT -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Gets the UART data register address. - * - * This function returns the UART data register address, which is mainly used by DMA/eDMA. - * - * @param base UART peripheral base address. - * @return UART data register address which are used both by transmitter and receiver. - */ -static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base) -{ - return (uint32_t) & (base->D); -} - -/*! - * @brief Enables or disables the UART transmitter DMA request. - * - * This function enables or disables the transmit data register empty flag, S1[TDRE], to generate the DMA requests. - * - * @param base UART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void UART_EnableTxDMA(UART_Type *base, bool enable) -{ - if (enable) - { -#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) - base->C4 |= UART_C4_TDMAS_MASK; -#else - base->C5 |= UART_C5_TDMAS_MASK; -#endif - base->C2 |= UART_C2_TIE_MASK; - } - else - { -#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) - base->C4 &= ~UART_C4_TDMAS_MASK; -#else - base->C5 &= ~UART_C5_TDMAS_MASK; -#endif - base->C2 &= ~UART_C2_TIE_MASK; - } -} - -/*! - * @brief Enables or disables the UART receiver DMA. - * - * This function enables or disables the receiver data register full flag, S1[RDRF], to generate DMA requests. - * - * @param base UART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void UART_EnableRxDMA(UART_Type *base, bool enable) -{ - if (enable) - { -#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) - base->C4 |= UART_C4_RDMAS_MASK; -#else - base->C5 |= UART_C5_RDMAS_MASK; -#endif - base->C2 |= UART_C2_RIE_MASK; - } - else - { -#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) - base->C4 &= ~UART_C4_RDMAS_MASK; -#else - base->C5 &= ~UART_C5_RDMAS_MASK; -#endif - base->C2 &= ~UART_C2_RIE_MASK; - } -} - -/* @} */ -#endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Enables or disables the UART transmitter. - * - * This function enables or disables the UART transmitter. - * - * @param base UART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void UART_EnableTx(UART_Type *base, bool enable) -{ - if (enable) - { - base->C2 |= UART_C2_TE_MASK; - } - else - { - base->C2 &= ~UART_C2_TE_MASK; - } -} - -/*! - * @brief Enables or disables the UART receiver. - * - * This function enables or disables the UART receiver. - * - * @param base UART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void UART_EnableRx(UART_Type *base, bool enable) -{ - if (enable) - { - base->C2 |= UART_C2_RE_MASK; - } - else - { - base->C2 &= ~UART_C2_RE_MASK; - } -} - -/*! - * @brief Writes to the TX register. - * - * This function writes data to the TX register directly. The upper layer must ensure - * that the TX register is empty or TX FIFO has empty room before calling this function. - * - * @param base UART peripheral base address. - * @param data The byte to write. - */ -static inline void UART_WriteByte(UART_Type *base, uint8_t data) -{ - base->D = data; -} - -/*! - * @brief Reads the RX register directly. - * - * This function reads data from the TX register directly. The upper layer must - * ensure that the RX register is full or that the TX FIFO has data before calling this function. - * - * @param base UART peripheral base address. - * @return The byte read from UART data register. - */ -static inline uint8_t UART_ReadByte(UART_Type *base) -{ - return base->D; -} - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @note This function does not check whether all the data has been sent out to the bus. - * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is - * finished. - * - * @param base UART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - */ -void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * @param base UART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_UART_RxHardwareOverrun Receiver overrun happened while receiving data. - * @retval kStatus_UART_NoiseError Noise error happened while receiving data. - * @retval kStatus_UART_FramingError Framing error happened while receiving data. - * @retval kStatus_UART_ParityError Parity error happened while receiving data. - * @retval kStatus_Success Successfully received all data. - */ -status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the UART handle. - * - * This function initializes the UART handle which can be used for other UART - * transactional APIs. Usually, for a specified UART instance, - * call this API once to get the initialized handle. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -void UART_TransferCreateHandle(UART_Type *base, - uart_handle_t *handle, - uart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific UART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - */ -void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the ISR, the UART driver calls the callback - * function and passes the @ref kStatus_UART_TxIdle as status parameter. - * - * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - * @param xfer UART transfer structure. See #uart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer); - -/*! - * @brief Aborts the interrupt driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBytes to find out - * how many bytes are still not sent out. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - */ -void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been written to UART TX register. - * - * This function gets the number of bytes that have been written to UART TX - * register by interrupt method. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the UART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the UART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - * @param xfer UART transfer structure, see #uart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into transmit queue. - * @retval kStatus_UART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t UART_TransferReceiveNonBlocking(UART_Type *base, - uart_handle_t *handle, - uart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know - * how many bytes not received yet. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - */ -void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); - -/*! - * @brief UART IRQ handle function. - * - * This function handles the UART transmit and receive IRQ request. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - */ -void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle); - -/*! - * @brief UART Error IRQ handle function. - * - * This function handle the UART error IRQ request. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - */ -void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UART_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart_edma.c deleted file mode 100644 index c51e493..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart_edma.c +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_uart_edma.h" -#include "fsl_dmamux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Array of UART handle. */ -#if (defined(UART5)) -#define UART_HANDLE_ARRAY_SIZE 6 -#else /* UART5 */ -#if (defined(UART4)) -#define UART_HANDLE_ARRAY_SIZE 5 -#else /* UART4 */ -#if (defined(UART3)) -#define UART_HANDLE_ARRAY_SIZE 4 -#else /* UART3 */ -#if (defined(UART2)) -#define UART_HANDLE_ARRAY_SIZE 3 -#else /* UART2 */ -#if (defined(UART1)) -#define UART_HANDLE_ARRAY_SIZE 2 -#else /* UART1 */ -#if (defined(UART0)) -#define UART_HANDLE_ARRAY_SIZE 1 -#else /* UART0 */ -#error No UART instance. -#endif /* UART 0 */ -#endif /* UART 1 */ -#endif /* UART 2 */ -#endif /* UART 3 */ -#endif /* UART 4 */ -#endif /* UART 5 */ - -/*base, uartPrivateHandle->handle); - - if (uartPrivateHandle->handle->callback) - { - uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_TxIdle, - uartPrivateHandle->handle->userData); - } - } -} - -static void UART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) -{ - assert(param); - - uart_edma_private_handle_t *uartPrivateHandle = (uart_edma_private_handle_t *)param; - - /* Avoid warning for unused parameters. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - /* Disable transfer. */ - UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); - - if (uartPrivateHandle->handle->callback) - { - uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_RxIdle, - uartPrivateHandle->handle->userData); - } - } -} - -void UART_TransferCreateHandleEDMA(UART_Type *base, - uart_edma_handle_t *handle, - uart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle) -{ - assert(handle); - - uint32_t instance = UART_GetInstance(base); - - s_edmaPrivateHandle[instance].base = base; - s_edmaPrivateHandle[instance].handle = handle; - - memset(handle, 0, sizeof(*handle)); - - handle->rxState = kUART_RxIdle; - handle->txState = kUART_TxIdle; - - handle->rxEdmaHandle = rxEdmaHandle; - handle->txEdmaHandle = txEdmaHandle; - - handle->callback = callback; - handle->userData = userData; - -#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO - /* Note: - Take care of the RX FIFO, EDMA request only assert when received bytes - equal or more than RX water mark, there is potential issue if RX water - mark larger than 1. - For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and - 5 bytes are received. the last byte will be saved in FIFO but not trigger - EDMA transfer because the water mark is 2. - */ - if (rxEdmaHandle) - { - base->RWFIFO = 1U; - } -#endif - - /* Configure TX. */ - if (txEdmaHandle) - { - EDMA_SetCallback(handle->txEdmaHandle, UART_SendEDMACallback, &s_edmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxEdmaHandle) - { - EDMA_SetCallback(handle->rxEdmaHandle, UART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]); - } -} - -status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer) -{ - assert(handle); - assert(handle->txEdmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - edma_transfer_config_t xferConfig; - status_t status; - - /* If previous TX not finished. */ - if (kUART_TxBusy == handle->txState) - { - status = kStatus_UART_TxBusy; - } - else - { - handle->txState = kUART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)UART_GetDataRegisterAddress(base), - sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral); - - /* Store the initially configured eDMA minor byte transfer count into the UART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->txEdmaHandle); - - /* Enable UART TX EDMA. */ - UART_EnableTxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer) -{ - assert(handle); - assert(handle->rxEdmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - edma_transfer_config_t xferConfig; - status_t status; - - /* If previous RX not finished. */ - if (kUART_RxBusy == handle->rxState) - { - status = kStatus_UART_RxBusy; - } - else - { - handle->rxState = kUART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, (void *)UART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, - sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); - - /* Store the initially configured eDMA minor byte transfer count into the UART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->rxEdmaHandle); - - /* Enable UART RX EDMA. */ - UART_EnableRxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle) -{ - assert(handle); - assert(handle->txEdmaHandle); - - /* Disable UART TX EDMA. */ - UART_EnableTxDMA(base, false); - - /* Stop transfer. */ - EDMA_AbortTransfer(handle->txEdmaHandle); - - handle->txState = kUART_TxIdle; -} - -void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle) -{ - assert(handle); - assert(handle->rxEdmaHandle); - - /* Disable UART RX EDMA. */ - UART_EnableRxDMA(base, false); - - /* Stop transfer. */ - EDMA_AbortTransfer(handle->rxEdmaHandle); - - handle->rxState = kUART_RxIdle; -} - -status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->rxEdmaHandle); - assert(count); - - if (kUART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); - - return kStatus_Success; -} - -status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->txEdmaHandle); - assert(count); - - if (kUART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); - - return kStatus_Success; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart_edma.h deleted file mode 100644 index e411ffd..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_uart_edma.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_UART_EDMA_H_ -#define _FSL_UART_EDMA_H_ - -#include "fsl_uart.h" -#include "fsl_dmamux.h" -#include "fsl_edma.h" - -/*! - * @addtogroup uart_edma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Forward declaration of the handle typedef. */ -typedef struct _uart_edma_handle uart_edma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*uart_edma_transfer_callback_t)(UART_Type *base, - uart_edma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief UART eDMA handle -*/ -struct _uart_edma_handle -{ - uart_edma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ - edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ - - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA transactional - * @{ - */ - -/*! - * @brief Initializes the UART handle which is used in transactional functions. - * @param base UART peripheral base address. - * @param handle Pointer to the uart_edma_handle_t structure. - * @param callback UART callback, NULL means no callback. - * @param userData User callback function data. - * @param rxEdmaHandle User-requested DMA handle for RX DMA transfer. - * @param txEdmaHandle User-requested DMA handle for TX DMA transfer. - */ -void UART_TransferCreateHandleEDMA(UART_Type *base, - uart_edma_handle_t *handle, - uart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle); - -/*! - * @brief Sends data using eDMA. - * - * This function sends data using eDMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - * @param xfer UART eDMA transfer structure. See #uart_transfer_t. - * @retval kStatus_Success if succeeded; otherwise failed. - * @retval kStatus_UART_TxBusy Previous transfer ongoing. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer); - -/*! - * @brief Receives data using eDMA. - * - * This function receives data using eDMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base UART peripheral base address. - * @param handle Pointer to the uart_edma_handle_t structure. - * @param xfer UART eDMA transfer structure. See #uart_transfer_t. - * @retval kStatus_Success if succeeded; otherwise failed. - * @retval kStatus_UART_RxBusy Previous transfer ongoing. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using eDMA. - * - * This function aborts sent data using eDMA. - * - * @param base UART peripheral base address. - * @param handle Pointer to the uart_edma_handle_t structure. - */ -void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle); - -/*! - * @brief Aborts the receive data using eDMA. - * - * This function aborts receive data using eDMA. - * - * @param base UART peripheral base address. - * @param handle Pointer to the uart_edma_handle_t structure. - */ -void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle); - -/*! - * @brief Gets the number of bytes that have been written to UART TX register. - * - * This function gets the number of bytes that have been written to UART TX - * register by DMA. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count); - -/*! - * @brief Gets the number of received bytes. - * - * This function gets the number of received bytes. - * - * @param base UART peripheral base address. - * @param handle UART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UART_EDMA_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_wdog.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_wdog.c deleted file mode 100644 index 489798c..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_wdog.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_wdog.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -void WDOG_GetDefaultConfig(wdog_config_t *config) -{ - assert(config); - - config->enableWdog = true; - config->clockSource = kWDOG_LpoClockSource; - config->prescaler = kWDOG_ClockPrescalerDivide1; -#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN - config->workMode.enableWait = true; -#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ - config->workMode.enableStop = false; - config->workMode.enableDebug = false; - config->enableUpdate = true; - config->enableInterrupt = false; - config->enableWindowMode = false; - config->windowValue = 0U; - config->timeoutValue = 0xFFFFU; -} - -void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) -{ - assert(config); - - uint32_t value = 0U; - uint32_t primaskValue = 0U; - - value = WDOG_STCTRLH_WDOGEN(config->enableWdog) | WDOG_STCTRLH_CLKSRC(config->clockSource) | - WDOG_STCTRLH_IRQRSTEN(config->enableInterrupt) | WDOG_STCTRLH_WINEN(config->enableWindowMode) | - WDOG_STCTRLH_ALLOWUPDATE(config->enableUpdate) | WDOG_STCTRLH_DBGEN(config->workMode.enableDebug) | - WDOG_STCTRLH_STOPEN(config->workMode.enableStop) | -#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN - WDOG_STCTRLH_WAITEN(config->workMode.enableWait) | -#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ - WDOG_STCTRLH_DISTESTWDOG(1U); - - /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence - * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ - primaskValue = DisableGlobalIRQ(); - WDOG_Unlock(base); - /* Wait one bus clock cycle */ - base->RSTCNT = 0U; - /* Set configruation */ - base->PRESC = WDOG_PRESC_PRESCVAL(config->prescaler); - base->WINH = (uint16_t)((config->windowValue >> 16U) & 0xFFFFU); - base->WINL = (uint16_t)((config->windowValue) & 0xFFFFU); - base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU); - base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU); - base->STCTRLH = value; - EnableGlobalIRQ(primaskValue); -} - -void WDOG_Deinit(WDOG_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupts */ - primaskValue = DisableGlobalIRQ(); - WDOG_Unlock(base); - /* Wait one bus clock cycle */ - base->RSTCNT = 0U; - WDOG_Disable(base); - EnableGlobalIRQ(primaskValue); - WDOG_ClearResetCount(base); -} - -void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config) -{ - assert(config); - - uint32_t value = 0U; - uint32_t primaskValue = 0U; - - value = WDOG_STCTRLH_DISTESTWDOG(0U) | WDOG_STCTRLH_TESTWDOG(1U) | WDOG_STCTRLH_TESTSEL(config->testMode) | - WDOG_STCTRLH_BYTESEL(config->testedByte) | WDOG_STCTRLH_IRQRSTEN(0U) | WDOG_STCTRLH_WDOGEN(1U) | - WDOG_STCTRLH_ALLOWUPDATE(1U); - - /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence - * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ - primaskValue = DisableGlobalIRQ(); - WDOG_Unlock(base); - /* Wait one bus clock cycle */ - base->RSTCNT = 0U; - /* Set configruation */ - base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU); - base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU); - base->STCTRLH = value; - EnableGlobalIRQ(primaskValue); -} - -uint32_t WDOG_GetStatusFlags(WDOG_Type *base) -{ - uint32_t status_flag = 0U; - - status_flag |= (base->STCTRLH & WDOG_STCTRLH_WDOGEN_MASK); - status_flag |= (base->STCTRLL & WDOG_STCTRLL_INTFLG_MASK); - - return status_flag; -} - -void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask) -{ - if (mask & kWDOG_TimeoutFlag) - { - base->STCTRLL |= WDOG_STCTRLL_INTFLG_MASK; - } -} - -void WDOG_Refresh(WDOG_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->REFRESH = WDOG_FIRST_WORD_OF_REFRESH; - base->REFRESH = WDOG_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_wdog.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_wdog.h deleted file mode 100644 index f497406..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_wdog.h +++ /dev/null @@ -1,433 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_WDOG_H_ -#define _FSL_WDOG_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wdog - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines WDOG driver version 2.0.0. */ -#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @name Unlock sequence */ -/*@{*/ -#define WDOG_FIRST_WORD_OF_UNLOCK (0xC520U) /*!< First word of unlock sequence */ -#define WDOG_SECOND_WORD_OF_UNLOCK (0xD928U) /*!< Second word of unlock sequence */ -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WDOG_FIRST_WORD_OF_REFRESH (0xA602U) /*!< First word of refresh sequence */ -#define WDOG_SECOND_WORD_OF_REFRESH (0xB480U) /*!< Second word of refresh sequence */ -/*@}*/ - -/*! @brief Describes WDOG clock source. */ -typedef enum _wdog_clock_source -{ - kWDOG_LpoClockSource = 0U, /*!< WDOG clock sourced from LPO*/ - kWDOG_AlternateClockSource = 1U, /*!< WDOG clock sourced from alternate clock source*/ -} wdog_clock_source_t; - -/*! @brief Defines WDOG work mode. */ -typedef struct _wdog_work_mode -{ -#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN - bool enableWait; /*!< Enables or disables WDOG in wait mode */ -#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ - bool enableStop; /*!< Enables or disables WDOG in stop mode */ - bool enableDebug; /*!< Enables or disables WDOG in debug mode */ -} wdog_work_mode_t; - -/*! @brief Describes the selection of the clock prescaler. */ -typedef enum _wdog_clock_prescaler -{ - kWDOG_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ - kWDOG_ClockPrescalerDivide2 = 0x1U, /*!< Divided by 2 */ - kWDOG_ClockPrescalerDivide3 = 0x2U, /*!< Divided by 3 */ - kWDOG_ClockPrescalerDivide4 = 0x3U, /*!< Divided by 4 */ - kWDOG_ClockPrescalerDivide5 = 0x4U, /*!< Divided by 5 */ - kWDOG_ClockPrescalerDivide6 = 0x5U, /*!< Divided by 6 */ - kWDOG_ClockPrescalerDivide7 = 0x6U, /*!< Divided by 7 */ - kWDOG_ClockPrescalerDivide8 = 0x7U, /*!< Divided by 8 */ -} wdog_clock_prescaler_t; - -/*! @brief Describes WDOG configuration structure. */ -typedef struct _wdog_config -{ - bool enableWdog; /*!< Enables or disables WDOG */ - wdog_clock_source_t clockSource; /*!< Clock source select */ - wdog_clock_prescaler_t prescaler; /*!< Clock prescaler value */ - wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */ - bool enableUpdate; /*!< Update write-once register enable */ - bool enableInterrupt; /*!< Enables or disables WDOG interrupt */ - bool enableWindowMode; /*!< Enables or disables WDOG window mode */ - uint32_t windowValue; /*!< Window value */ - uint32_t timeoutValue; /*!< Timeout value */ -} wdog_config_t; - -/*! @brief Describes WDOG test mode. */ -typedef enum _wdog_test_mode -{ - kWDOG_QuickTest = 0U, /*!< Selects quick test */ - kWDOG_ByteTest = 1U, /*!< Selects byte test */ -} wdog_test_mode_t; - -/*! @brief Describes WDOG tested byte selection in byte test mode. */ -typedef enum _wdog_tested_byte -{ - kWDOG_TestByte0 = 0U, /*!< Byte 0 selected in byte test mode */ - kWDOG_TestByte1 = 1U, /*!< Byte 1 selected in byte test mode */ - kWDOG_TestByte2 = 2U, /*!< Byte 2 selected in byte test mode */ - kWDOG_TestByte3 = 3U, /*!< Byte 3 selected in byte test mode */ -} wdog_tested_byte_t; - -/*! @brief Describes WDOG test mode configuration structure. */ -typedef struct _wdog_test_config -{ - wdog_test_mode_t testMode; /*!< Selects test mode */ - wdog_tested_byte_t testedByte; /*!< Selects tested byte in byte test mode */ - uint32_t timeoutValue; /*!< Timeout value */ -} wdog_test_config_t; - -/*! - * @brief WDOG interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the WDOG interrupt configurations. - */ -enum _wdog_interrupt_enable_t -{ - kWDOG_InterruptEnable = WDOG_STCTRLH_IRQRSTEN_MASK, /*!< WDOG timeout generates an interrupt before reset*/ -}; - -/*! - * @brief WDOG status flags. - * - * This structure contains the WDOG status flags for use in the WDOG functions. - */ -enum _wdog_status_flags_t -{ - kWDOG_RunningFlag = WDOG_STCTRLH_WDOGEN_MASK, /*!< Running flag, set when WDOG is enabled*/ - kWDOG_TimeoutFlag = WDOG_STCTRLL_INTFLG_MASK, /*!< Interrupt flag, set when an exception occurs*/ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WDOG Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes WDOG configure sturcture. - * - * This function initializes the WDOG configuration structure to default value. The default - * values are: - * @code - * wdogConfig->enableWdog = true; - * wdogConfig->clockSource = kWDOG_LpoClockSource; - * wdogConfig->prescaler = kWDOG_ClockPrescalerDivide1; - * wdogConfig->workMode.enableWait = true; - * wdogConfig->workMode.enableStop = false; - * wdogConfig->workMode.enableDebug = false; - * wdogConfig->enableUpdate = true; - * wdogConfig->enableInterrupt = false; - * wdogConfig->enableWindowMode = false; - * wdogConfig->windowValue = 0; - * wdogConfig->timeoutValue = 0xFFFFU; - * @endcode - * - * @param config Pointer to WDOG config structure. - * @see wdog_config_t - */ -void WDOG_GetDefaultConfig(wdog_config_t *config); - -/*! - * @brief Initializes the WDOG. - * - * This function initializes the WDOG. When called, the WDOG runs according to the configuration. - * If user wants to reconfigure WDOG without forcing a reset first, enableUpdate must be set to true - * in configuration. - * - * Example: - * @code - * wdog_config_t config; - * WDOG_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * config.enableUpdate = true; - * WDOG_Init(wdog_base,&config); - * @endcode - * - * @param base WDOG peripheral base address - * @param config The configuration of WDOG - */ -void WDOG_Init(WDOG_Type *base, const wdog_config_t *config); - -/*! - * @brief Shuts down the WDOG. - * - * This function shuts down the WDOG. - * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled. - */ -void WDOG_Deinit(WDOG_Type *base); - -/*! - * @brief Configures WDOG functional test. - * - * This function is used to configure the WDOG functional test. When called, the WDOG goes into test mode - * and runs according to the configuration. - * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled. - * - * Example: - * @code - * wdog_test_config_t test_config; - * test_config.testMode = kWDOG_QuickTest; - * test_config.timeoutValue = 0xfffffu; - * WDOG_SetTestModeConfig(wdog_base, &test_config); - * @endcode - * @param base WDOG peripheral base address - * @param config The functional test configuration of WDOG - */ -void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config); - -/* @} */ - -/*! - * @name WDOG Functional Operation - * @{ - */ - -/*! - * @brief Enables the WDOG module. - * - * This function write value into WDOG_STCTRLH register to enable the WDOG, it is a write-once register, - * make sure that the WCT window is still open and this register has not been written in this WCT - * while this function is called. - * - * @param base WDOG peripheral base address - */ -static inline void WDOG_Enable(WDOG_Type *base) -{ - base->STCTRLH |= WDOG_STCTRLH_WDOGEN_MASK; -} - -/*! - * @brief Disables the WDOG module. - * - * This function write value into WDOG_STCTRLH register to disable the WDOG, it is a write-once register, - * make sure that the WCT window is still open and this register has not been written in this WCT - * while this function is called. - * - * @param base WDOG peripheral base address - */ -static inline void WDOG_Disable(WDOG_Type *base) -{ - base->STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK; -} - -/*! - * @brief Enable WDOG interrupt. - * - * This function write value into WDOG_STCTRLH register to enable WDOG interrupt, it is a write-once register, - * make sure that the WCT window is still open and this register has not been written in this WCT - * while this function is called. - * - * @param base WDOG peripheral base address - * @param mask The interrupts to enable - * The parameter can be combination of the following source if defined: - * @arg kWDOG_InterruptEnable - */ -static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint32_t mask) -{ - base->STCTRLH |= mask; -} - -/*! - * @brief Disable WDOG interrupt. - * - * This function write value into WDOG_STCTRLH register to disable WDOG interrupt, it is a write-once register, - * make sure that the WCT window is still open and this register has not been written in this WCT - * while this function is called. - * - * @param base WDOG peripheral base address - * @param mask The interrupts to disable - * The parameter can be combination of the following source if defined: - * @arg kWDOG_InterruptEnable - */ -static inline void WDOG_DisableInterrupts(WDOG_Type *base, uint32_t mask) -{ - base->STCTRLH &= ~mask; -} - -/*! - * @brief Gets WDOG all status flags. - * - * This function gets all status flags. - * - * Example for getting Running Flag: - * @code - * uint32_t status; - * status = WDOG_GetStatusFlags(wdog_base) & kWDOG_RunningFlag; - * @endcode - * @param base WDOG peripheral base address - * @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags_t - * - true: a related status flag has been set. - * - false: a related status flag is not set. - */ -uint32_t WDOG_GetStatusFlags(WDOG_Type *base); - -/*! - * @brief Clear WDOG flag. - * - * This function clears WDOG status flag. - * - * Example for clearing timeout(interrupt) flag: - * @code - * WDOG_ClearStatusFlags(wdog_base,kWDOG_TimeoutFlag); - * @endcode - * @param base WDOG peripheral base address - * @param mask The status flags to clear. - * The parameter could be any combination of the following values: - * kWDOG_TimeoutFlag - */ -void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask); - -/*! - * @brief Set the WDOG timeout value. - * - * This function sets the timeout value. - * It should be ensured that the time-out value for the WDOG is always greater than - * 2xWCT time + 20 bus clock cycles. - * This function write value into WDOG_TOVALH and WDOG_TOVALL registers which are wirte-once. - * Make sure the WCT window is still open and these two registers have not been written in this WCT - * while this function is called. - * - * @param base WDOG peripheral base address - * @param timeoutCount WDOG timeout value, count of WDOG clock tick. - */ -static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint32_t timeoutCount) -{ - base->TOVALH = (uint16_t)((timeoutCount >> 16U) & 0xFFFFU); - base->TOVALL = (uint16_t)((timeoutCount)&0xFFFFU); -} - -/*! - * @brief Sets the WDOG window value. - * - * This function sets the WDOG window value. - * This function write value into WDOG_WINH and WDOG_WINL registers which are wirte-once. - * Make sure the WCT window is still open and these two registers have not been written in this WCT - * while this function is called. - * - * @param base WDOG peripheral base address - * @param windowValue WDOG window value. - */ -static inline void WDOG_SetWindowValue(WDOG_Type *base, uint32_t windowValue) -{ - base->WINH = (uint16_t)((windowValue >> 16U) & 0xFFFFU); - base->WINL = (uint16_t)((windowValue)&0xFFFFU); -} - -/*! - * @brief Unlocks the WDOG register written. - * - * This function unlocks the WDOG register written. - * Before starting the unlock sequence and following congfiguration, disable the global interrupts. - * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire, - * After the configuration finishes, re-enable the global interrupts. - * - * @param base WDOG peripheral base address - */ -static inline void WDOG_Unlock(WDOG_Type *base) -{ - base->UNLOCK = WDOG_FIRST_WORD_OF_UNLOCK; - base->UNLOCK = WDOG_SECOND_WORD_OF_UNLOCK; -} - -/*! - * @brief Refreshes the WDOG timer. - * - * This function feeds the WDOG. - * This function should be called before WDOG timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WDOG peripheral base address - */ -void WDOG_Refresh(WDOG_Type *base); - -/*! - * @brief Gets the WDOG reset count. - * - * This function gets the WDOG reset count value. - * - * @param base WDOG peripheral base address - * @return WDOG reset count value - */ -static inline uint16_t WDOG_GetResetCount(WDOG_Type *base) -{ - return base->RSTCNT; -} -/*! - * @brief Clears the WDOG reset count. - * - * This function clears the WDOG reset count value. - * - * @param base WDOG peripheral base address - */ -static inline void WDOG_ClearResetCount(WDOG_Type *base) -{ - base->RSTCNT |= UINT16_MAX; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WDOG_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/peripheral_clock_defines.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/peripheral_clock_defines.h deleted file mode 100644 index ba26b7b..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/peripheral_clock_defines.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_PERIPHERAL_CLOCK_H_ -#define _FSL_PERIPHERAL_CLOCK_H_ - -#include "fsl_clock.h" - -/* Array for UART module clocks */ -#define UART_CLOCK_FREQS \ - { \ - UART0_CLK_SRC, UART1_CLK_SRC, UART2_CLK_SRC \ - } - -/* Array for I2C module clocks */ -#define I2C_CLOCK_FREQS \ - { \ - I2C0_CLK_SRC, I2C1_CLK_SRC \ - } - -/* Array for DSPI module clocks */ -#define SPI_CLOCK_FREQS \ - { \ - DSPI0_CLK_SRC, DSPI1_CLK_SRC \ - } - -#endif /* _FSL_PERIPHERAL_CLOCK_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/pwmout_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/pwmout_api.c deleted file mode 100644 index 848868e..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/pwmout_api.c +++ /dev/null @@ -1,158 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" - -#if DEVICE_PWMOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "fsl_ftm.h" -#include "PeripheralPins.h" - -static float pwm_clock_mhz; -/* Array of FTM peripheral base address. */ -static FTM_Type *const ftm_addrs[] = FTM_BASE_PTRS; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(pwm != (PWMName)NC); - - obj->pwm_name = pwm; - - uint32_t pwm_base_clock; - pwm_base_clock = CLOCK_GetFreq(kCLOCK_BusClk); - float clkval = (float)pwm_base_clock / 1000000.0f; - uint32_t clkdiv = 0; - while (clkval > 1) { - clkdiv++; - clkval /= 2.0f; - if (clkdiv == 7) { - break; - } - } - - pwm_clock_mhz = clkval; - uint32_t channel = pwm & 0xF; - uint32_t instance = pwm >> TPM_SHIFT; - ftm_config_t ftmInfo; - - FTM_GetDefaultConfig(&ftmInfo); - ftmInfo.prescale = (ftm_clock_prescale_t)clkdiv; - /* Initialize FTM module */ - FTM_Init(ftm_addrs[instance], &ftmInfo); - - ftm_addrs[instance]->CONF |= FTM_CONF_NUMTOF(3); - - ftm_chnl_pwm_signal_param_t config = { - .chnlNumber = (ftm_chnl_t)channel, - .level = kFTM_HighTrue, - .dutyCyclePercent = 0, - .firstEdgeDelayPercent = 0 - }; - // default to 20ms: standard for servos, and fine for e.g. brightness control - FTM_SetupPwm(ftm_addrs[instance], &config, 1, kFTM_EdgeAlignedPwm, 50, pwm_base_clock); - - FTM_StartTimer(ftm_addrs[instance], kFTM_SystemClock); - - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); -} - -void pwmout_free(pwmout_t* obj) -{ - FTM_Deinit(ftm_addrs[obj->pwm_name >> TPM_SHIFT]); -} - -void pwmout_write(pwmout_t* obj, float value) -{ - if (value < 0.0f) { - value = 0.0f; - } else if (value > 1.0f) { - value = 1.0f; - } - - FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; - uint16_t mod = base->MOD & FTM_MOD_MOD_MASK; - uint32_t new_count = (uint32_t)((float)(mod) * value); - // Update of CnV register - base->CONTROLS[obj->pwm_name & 0xF].CnV = new_count; - base->CNT = 0; - /* Software trigger to update registers */ - FTM_SetSoftwareTrigger(base, true); -} - -float pwmout_read(pwmout_t* obj) -{ - FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; - uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & FTM_CnV_VAL_MASK; - uint16_t mod = base->MOD & FTM_MOD_MOD_MASK; - - if (mod == 0) - return 0.0; - float v = (float)(count) / (float)(mod); - return (v > 1.0f) ? (1.0f) : (v); -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t* obj, int us) -{ - FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; - float dc = pwmout_read(obj); - - // Stop FTM clock to ensure instant update of MOD register - base->MOD = FTM_MOD_MOD((pwm_clock_mhz * (float)us) - 1); - pwmout_write(obj, dc); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; - uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us); - - // Update of CnV register - base->CONTROLS[obj->pwm_name & 0xF].CnV = value; - /* Software trigger to update registers */ - FTM_SetSoftwareTrigger(base, true); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/serial_api.c deleted file mode 100644 index 9c2e5d5..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/serial_api.c +++ /dev/null @@ -1,375 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "serial_api.h" - -#if DEVICE_SERIAL - -// math.h required for floating point operations for baud rate calculation -#include -#include "mbed_assert.h" - -#include - -#include "cmsis.h" -#include "pinmap.h" -#include "fsl_uart.h" -#include "peripheral_clock_defines.h" -#include "PeripheralPins.h" -#include "fsl_clock_config.h" - -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0}; -static uart_irq_handler irq_handler; -/* Array of UART peripheral base address. */ -static UART_Type *const uart_addrs[] = UART_BASE_PTRS; -/* Array of UART bus clock frequencies */ -static clock_name_t const uart_clocks[] = UART_CLOCK_FREQS; - - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); - uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); - obj->index = pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)obj->index != NC); - - uart_config_t config; - - UART_GetDefaultConfig(&config); - config.baudRate_Bps = 9600; - config.enableTx = false; - config.enableRx = false; - - UART_Init(uart_addrs[obj->index], &config, CLOCK_GetFreq(uart_clocks[obj->index])); - - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - UART_EnableTx(uart_addrs[obj->index], true); - pin_mode(tx, PullUp); - } - if (rx != NC) { - UART_EnableRx(uart_addrs[obj->index], true); - pin_mode(rx, PullUp); - } - - if (obj->index == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - UART_Deinit(uart_addrs[obj->index]); - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - UART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index])); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - UART_Type *base = uart_addrs[obj->index]; - uint8_t temp; - /* Set bit count and parity mode. */ - temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); - if (parity != ParityNone) - { - /* Enable Parity */ - temp |= (UART_C1_PE_MASK | UART_C1_M_MASK); - if (parity == ParityOdd) { - temp |= UART_C1_PT_MASK; - } else if (parity == ParityEven) { - // PT=0 so nothing more to do - } else { - // Hardware does not support forced parity - MBED_ASSERT(0); - } - } - base->C1 = temp; -#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT - /* Set stop bit per char */ - base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)--stop_bits); -#endif -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) -{ - UART_Type *base = uart_addrs[index]; - - /* If RX overrun. */ - if (UART_S1_OR_MASK & base->S1) - { - /* Read base->D, otherwise the RX does not work. */ - (void)base->D; - } - - if (serial_irq_ids[index] != 0) { - if (transmit_empty && (UART_GetEnabledInterrupts(uart_addrs[index]) & kUART_TxDataRegEmptyInterruptEnable)) - irq_handler(serial_irq_ids[index], TxIrq); - - if (receive_full && (UART_GetEnabledInterrupts(uart_addrs[index]) & kUART_RxDataRegFullInterruptEnable)) - irq_handler(serial_irq_ids[index], RxIrq); - } -} - -void uart0_irq() -{ - uint32_t status_flags = UART0->S1; - uart_irq((status_flags & kUART_TxDataRegEmptyFlag), (status_flags & kUART_RxDataRegFullFlag), 0); -} - -void uart1_irq() -{ - uint32_t status_flags = UART1->S1; - uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 1); -} - -void uart2_irq() -{ - uint32_t status_flags = UART2->S1; - uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 2); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type uart_irqs[] = UART_RX_TX_IRQS; - uint32_t vector = 0; - - switch (obj->index) { - case 0: - vector = (uint32_t)&uart0_irq; - break; - case 1: - vector = (uint32_t)&uart1_irq; - break; - case 2: - vector = (uint32_t)&uart2_irq; - break; - default: - break; - } - - if (enable) { - switch (irq) { - case RxIrq: - UART_EnableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); - break; - case TxIrq: - UART_EnableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); - break; - default: - break; - } - NVIC_SetVector(uart_irqs[obj->index], vector); - NVIC_EnableIRQ(uart_irqs[obj->index]); - - } else { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - switch (irq) { - case RxIrq: - UART_DisableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); - break; - case TxIrq: - UART_DisableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); - break; - default: - break; - } - switch (other_irq) { - case RxIrq: - all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_RxDataRegFullInterruptEnable) == 0); - break; - case TxIrq: - all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_TxDataRegEmptyInterruptEnable) == 0); - break; - default: - break; - } - if (all_disabled) - NVIC_DisableIRQ(uart_irqs[obj->index]); - } -} - -int serial_getc(serial_t *obj) -{ - while (!serial_readable(obj)); - uint8_t data; - data = UART_ReadByte(uart_addrs[obj->index]); - - return data; -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)); - UART_WriteByte(uart_addrs[obj->index], (uint8_t)c); -} - -int serial_readable(serial_t *obj) -{ - uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]); - if (status_flags & kUART_RxOverrunFlag) - UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag); - return (status_flags & kUART_RxDataRegFullFlag); -} - -int serial_writable(serial_t *obj) -{ - uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]); - if (status_flags & kUART_RxOverrunFlag) - UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag); - return (status_flags & kUART_TxDataRegEmptyFlag); -} - -void serial_clear(serial_t *obj) -{ -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - uart_addrs[obj->index]->C2 |= UART_C2_SBK_MASK; -} - -void serial_break_clear(serial_t *obj) -{ - uart_addrs[obj->index]->C2 &= ~UART_C2_SBK_MASK; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ - return PinMap_UART_RTS; -} - -#if DEVICE_SERIAL_FC - -/* - * Only hardware flow control is implemented in this API. - */ -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - switch(type) { - case FlowControlRTS: - pinmap_pinout(rxflow, PinMap_UART_RTS); - uart_addrs[obj->index]->MODEM &= ~UART_MODEM_TXCTSE_MASK; - uart_addrs[obj->index]->MODEM |= UART_MODEM_RXRTSE_MASK; - break; - - case FlowControlCTS: - pinmap_pinout(txflow, PinMap_UART_CTS); - uart_addrs[obj->index]->MODEM &= ~UART_MODEM_RXRTSE_MASK; - uart_addrs[obj->index]->MODEM |= UART_MODEM_TXCTSE_MASK; - break; - - case FlowControlRTSCTS: - pinmap_pinout(rxflow, PinMap_UART_RTS); - pinmap_pinout(txflow, PinMap_UART_CTS); - uart_addrs[obj->index]->MODEM |= UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK; - break; - - case FlowControlNone: - uart_addrs[obj->index]->MODEM &= ~(UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK); - break; - - default: - break; - } -} - -#endif - -static int serial_is_enabled(uint32_t uart_index) -{ - int clock_enabled = 0; - switch (uart_index) { - case 0: - clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT; - break; - case 1: - clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT; - break; - case 2: - clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT; - break; - default: - break; - } - - return clock_enabled; -} - -bool serial_check_tx_ongoing() -{ - UART_Type *base; - int i; - bool uart_tx_ongoing = false; - - for (i = 0; i < FSL_FEATURE_SOC_UART_COUNT; i++) { - /* First check if UART is enabled */ - if (!serial_is_enabled(i)) { - /* UART is not enabled, check the next instance */ - continue; - } - - base = uart_addrs[i]; - - /* Check if data is waiting to be written out of transmit buffer */ - if (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base))) { - uart_tx_ongoing = true; - break; - } - } - - return uart_tx_ongoing; -} - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/spi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/spi_api.c deleted file mode 100644 index 12d3eac..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/spi_api.c +++ /dev/null @@ -1,219 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "mbed_assert.h" - -#include "spi_api.h" - -#if DEVICE_SPI - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "fsl_dspi.h" -#include "peripheral_clock_defines.h" -#include "PeripheralPins.h" - -/* Array of SPI peripheral base address. */ -static SPI_Type *const spi_address[] = SPI_BASE_PTRS; -/* Array of SPI bus clock frequencies */ -static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS; - -SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) -{ - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - - SPIName spi_per; - - // If 3 wire SPI is used, the miso is not connected. - if (miso == NC) { - spi_per = (SPIName)pinmap_merge(spi_mosi, spi_sclk); - } else { - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - spi_per = (SPIName)pinmap_merge(spi_data, spi_sclk); - } - - return spi_per; -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // determine the SPI to use - uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); - uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); - uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); - uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); - uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); - uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); - - obj->instance = pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->instance != NC); - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } -} - -void spi_free(spi_t *obj) -{ - DSPI_Deinit(spi_address[obj->instance]); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - dspi_master_config_t master_config; - dspi_slave_config_t slave_config; - - if (slave) { - /* Slave config */ - DSPI_SlaveGetDefaultConfig(&slave_config); - slave_config.whichCtar = kDSPI_Ctar0; - slave_config.ctarConfig.bitsPerFrame = (uint32_t)bits;; - slave_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh; - slave_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge; - - DSPI_SlaveInit(spi_address[obj->instance], &slave_config); - } else { - /* Master config */ - DSPI_MasterGetDefaultConfig(&master_config); - master_config.ctarConfig.bitsPerFrame = (uint32_t)bits;; - master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh; - master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge; - master_config.ctarConfig.direction = kDSPI_MsbFirst; - master_config.ctarConfig.pcsToSckDelayInNanoSec = 100; - - DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance])); - } -} - -void spi_frequency(spi_t *obj, int hz) -{ - uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]); - DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock); - //Half clock period delay after SPI transfer - DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz); -} - -static inline int spi_readable(spi_t *obj) -{ - return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag); -} - -int spi_master_write(spi_t *obj, int value) -{ - dspi_command_data_config_t command; - uint32_t rx_data; - DSPI_GetDefaultDataCommandConfig(&command); - command.isEndOfQueue = true; - - DSPI_MasterWriteDataBlocking(spi_address[obj->instance], &command, (uint16_t)value); - - DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_TxFifoFillRequestFlag); - - // wait rx buffer full - while (!spi_readable(obj)); - rx_data = DSPI_ReadData(spi_address[obj->instance]); - DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag); - return rx_data & 0xffff; -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) -{ - int total = (tx_length > rx_length) ? tx_length : rx_length; - - // Default write is done in each and every call, in future can create HAL API instead - DSPI_SetDummyData(spi_address[obj->instance], write_fill); - - DSPI_MasterTransferBlocking(spi_address[obj->instance], &(dspi_transfer_t) { - .txData = (uint8_t *)tx_buffer, - .rxData = (uint8_t *)rx_buffer, - .dataSize = total, - .configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous, - }); - - DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag); - - return total; -} - -int spi_slave_receive(spi_t *obj) -{ - return spi_readable(obj); -} - -int spi_slave_read(spi_t *obj) -{ - uint32_t rx_data; - - while (!spi_readable(obj)); - rx_data = DSPI_ReadData(spi_address[obj->instance]); - DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag); - return rx_data & 0xffff; -} - -void spi_slave_write(spi_t *obj, int value) -{ - DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/trng_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/trng_api.c deleted file mode 100644 index 432c6f0..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/trng_api.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Hardware entropy collector for the K64F, using Freescale's RNGA - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -#if DEVICE_TRNG - -#include -#include "cmsis.h" -#include "fsl_common.h" -#include "fsl_clock.h" -#include "trng_api.h" - -void trng_init(trng_t *obj) -{ - (void)obj; - CLOCK_EnableClock(kCLOCK_Rnga0); - CLOCK_DisableClock(kCLOCK_Rnga0); - CLOCK_EnableClock(kCLOCK_Rnga0); -} - -void trng_free(trng_t *obj) -{ - (void)obj; - CLOCK_DisableClock(kCLOCK_Rnga0); -} - -/* - * Get one byte of entropy from the RNG, assuming it is up and running. - * As recommended, get only one bit of each output. - */ -static void trng_get_byte(unsigned char *byte) -{ - *byte = 0; - size_t bit; - - /* 34.5 Steps 3-4-5: poll SR and read from OR when ready */ - for( bit = 0; bit < 8; bit++ ) - { - while((RNG->SR & RNG_SR_OREG_LVL_MASK) == 0 ); - *byte |= (RNG->OR & 1) << bit; - } -} - -int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) -{ - (void)obj; - size_t i; - - /* Set "Interrupt Mask", "High Assurance" and "Go", - * unset "Clear interrupt" and "Sleep" */ - RNG->CR = RNG_CR_INTM_MASK | RNG_CR_HA_MASK | RNG_CR_GO_MASK; - - for (i = 0; i < length; i++) { - trng_get_byte(output + i); - } - - /* Just be extra sure that we didn't do it wrong */ - if ((RNG->SR & RNG_SR_SECV_MASK) != 0) { - return -1; - } - - *output_length = length; - - return 0; -} - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c deleted file mode 100644 index dd2589f..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c +++ /dev/null @@ -1,152 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "us_ticker_defines.h" -#include "PeripheralNames.h" -#include "fsl_pit.h" -#include "fsl_clock_config.h" - -const ticker_info_t* us_ticker_get_info() -{ - static const ticker_info_t info = { - 1000000, // 1 MHz - 32 // 32 bit counter - }; - return &info; -} - -static bool us_ticker_inited = false; - -static void pit_isr(void) -{ - PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); - PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK); - PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_StopTimer(PIT, kPIT_Chnl_3); - - us_ticker_irq_handler(); -} - -/** Initialize the high frequency ticker - * - */ -void us_ticker_init(void) -{ - /* Common for ticker/timer. */ - uint32_t busClock; - /* Structure to initialize PIT. */ - pit_config_t pitConfig; - - PIT_GetDefaultConfig(&pitConfig); - PIT_Init(PIT, &pitConfig); - - busClock = CLOCK_GetFreq(kCLOCK_BusClk); - - /* Let the timer to count if re-init. */ - if (!us_ticker_inited) { - - PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF); - PIT_SetTimerChainMode(PIT, kPIT_Chnl_1, true); - PIT_StartTimer(PIT, kPIT_Chnl_0); - PIT_StartTimer(PIT, kPIT_Chnl_1); - } - - /* Configure interrupt generation counters and disable ticker interrupts. */ - PIT_StopTimer(PIT, kPIT_Chnl_3); - PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); - PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); - NVIC_SetVector(PIT3_IRQn, (uint32_t) pit_isr); - NVIC_EnableIRQ(PIT3_IRQn); - PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); - - us_ticker_inited = true; -} - -/** Read the current counter - * - * @return The current timer's counter value in ticks - */ -uint32_t (us_ticker_read)() -{ - return us_ticker_read(); -} - -/** Disable us ticker interrupt - * - */ -void us_ticker_disable_interrupt(void) -{ - PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); -} - -/** Clear us ticker interrupt - * - */ -void us_ticker_clear_interrupt(void) -{ - PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); -} - -/** Set interrupt for specified timestamp - * - * @param timestamp The time in ticks when interrupt should be generated - */ -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - /* We get here absolute interrupt time which takes into account counter overflow. - * Since we use additional count-down timer to generate interrupt we need to calculate - * load value based on time-stamp. - */ - const uint32_t now_ticks = us_ticker_read(); - uint32_t delta_ticks = - timestamp >= now_ticks ? timestamp - now_ticks : (uint32_t)((uint64_t) timestamp + 0xFFFFFFFF - now_ticks); - - if (delta_ticks == 0) { - /* The requested delay is less than the minimum resolution of this counter. */ - delta_ticks = 1; - } - - PIT_StopTimer(PIT, kPIT_Chnl_3); - PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, delta_ticks); - PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); - PIT_StartTimer(PIT, kPIT_Chnl_3); - PIT_StartTimer(PIT, kPIT_Chnl_2); -} - -/** Fire us ticker interrupt - * - */ -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(PIT3_IRQn); -} - -void us_ticker_free(void) -{ - PIT_StopTimer(PIT, kPIT_Chnl_3); - PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_StopTimer(PIT, kPIT_Chnl_1); - PIT_StopTimer(PIT, kPIT_Chnl_0); - - PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); - NVIC_DisableIRQ(PIT3_IRQn); - - us_ticker_inited = false; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker_defines.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker_defines.h deleted file mode 100644 index 04f5da8..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker_defines.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _FSL_US_TICKER_DEFINES_H_ -#define _FSL_US_TICKER_DEFINES_H_ - -#include "fsl_pit.h" - -#define US_TICKER_PERIOD_NUM 1 -#define US_TICKER_PERIOD_DEN 1 - -#define US_TICKER_MASK 0xFFFFFFFF - -/* Macro-optimised form of us_ticker_read */ -#define us_ticker_read() (~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1))) - -#endif /* _FSL_US_TICKER_DEFINES_H_ */ diff --git a/targets/TARGET_Freescale/mbed_rtx.h b/targets/TARGET_Freescale/mbed_rtx.h index c2550e2..1b0b876 100644 --- a/targets/TARGET_Freescale/mbed_rtx.h +++ b/targets/TARGET_Freescale/mbed_rtx.h @@ -79,12 +79,6 @@ #define INITIAL_SP (0x20030000UL) #endif -#elif defined(TARGET_KW24D) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20008000UL) -#endif - #elif defined(TARGET_KW41Z) #ifndef INITIAL_SP diff --git a/targets/targets.json b/targets/targets.json index e2585fe..07a97f7 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -953,66 +953,6 @@ ], "device_name": "MKL43Z256xxx4" }, - "KW24D": { - "supported_form_factors": [ - "ARDUINO" - ], - "core": "Cortex-M4", - "supported_toolchains": [ - "ARM", - "GCC_ARM", - "IAR" - ], - "extra_labels": [ - "Freescale", - "MCUXpresso_MCUS", - "KSDK2_MCUS", - "FRDM" - ], - "is_disk_virtual": true, - "macros": [ - "CPU_MKW24D512VHA5", - "FSL_RTOS_MBED", - "MBED_TICKLESS" - ], - "inherits": [ - "Target" - ], - "detect_code": [ - "0250" - ], - "device_has": [ - "USTICKER", - "LPTICKER", - "RTC", - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPISLAVE", - "STDIO_MESSAGES", - "TRNG", - "FLASH", - "802_15_4_PHY" - ], - "release_versions": [ - "2", - "5" - ], - "device_name": "MKW24D512xxx5", - "bootloader_supported": true, - "overrides": { - "network-default-interface-type": "MESH" - } - }, "KW41Z": { "supported_form_factors": [ "ARDUINO" diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index 98bf204..43e1104 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -84,9 +84,6 @@ "MKL43Z256xxx4": { "OGChipSelectEditMenu": "MKL43Z256xxx4\tNXP MKL43Z256xxx4" }, - "MKW24D512xxx5": { - "OGChipSelectEditMenu": "MKW24D512xxx5\tNXP MKW24D512xxx5" - }, "MKW41Z512xxx4": { "OGChipSelectEditMenu": "MKW41Z512xxx4\tNXP MKW41Z512xxx4" }, diff --git a/tools/test_configs/NanostackMACTester.json b/tools/test_configs/NanostackMACTester.json index a3590ff..da85ce4 100644 --- a/tools/test_configs/NanostackMACTester.json +++ b/tools/test_configs/NanostackMACTester.json @@ -1,9 +1,6 @@ { "macros": ["MBED_TRACE_LINE_LENGTH=200", "OS_TASKCNT=4", "OS_IDLESTKSIZE=32", "MBED_CONF_MBED_TRACE_ENABLE=1"], "target_overrides": { - "KW24D": { - "mcr20a.provide-default": true - }, "*": { "nanostack.configuration": "lowpan_host", "platform.stdio-convert-newlines": true, diff --git a/tools/test_configs/target_configs.json b/tools/test_configs/target_configs.json index c01a11e..a989c3c 100644 --- a/tools/test_configs/target_configs.json +++ b/tools/test_configs/target_configs.json @@ -27,10 +27,6 @@ "default_test_configuration": "NONE", "test_configurations": ["IDW0XX1_WIFI"] }, - "KW24D": { - "default_test_configuration": "NO_NETWORK", - "test_configurations": ["6LOWPAN_HOST", "6LOWPAN_ROUTER", "THREAD_END_DEVICE", "THREAD_ROUTER"] - }, "KW41Z": { "default_test_configuration": "NO_NETWORK", "test_configurations": ["6LOWPAN_HOST", "6LOWPAN_ROUTER", "THREAD_END_DEVICE", "THREAD_ROUTER"]