diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 1353c30..a78e89a 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -186,8 +186,8 @@ } } if (strcmp(paramTag, "conId") == 0) { - char buf[10]; - std::sprintf(buf, "%d", _cid); + char buf[12]; + std::snprintf(buf, sizeof(buf), "%d", _cid); if (strcmp(paramValue, buf) == 0) { foundConIdType = true; } diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c index c2fa210..0e1c577 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c @@ -1,6 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2022, STMicroelectronics * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause * * SPDX-License-Identifier: Apache-2.0 * @@ -53,7 +54,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -74,8 +75,8 @@ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - /* Configure PG2, PG11 and PG13 */ - GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; + /* Configure PG11 and PG13 */ + GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13; HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); /* Enable the Ethernet global Interrupt */ @@ -103,7 +104,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -111,7 +112,7 @@ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13); /* Disable the Ethernet global Interrupt */ NVIC_DisableIRQ(ETH_IRQn); diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c index f824247..59c233e 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c @@ -2,7 +2,7 @@ * Copyright (c) 2022, STMicroelectronics * All rights reserved. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PB11 RMII_MII_TXD0 ---------------------> PB12 RMII_MII_TXD1 ---------------------> PB13 @@ -96,7 +96,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PB11 RMII_MII_TXD0 ---------------------> PB12 RMII_MII_TXD1 ---------------------> PB13 diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c index 223af59..6423a3f 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c @@ -1,6 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2022, STMicroelectronics * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause * * SPDX-License-Identifier: Apache-2.0 * @@ -53,7 +54,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -74,8 +75,8 @@ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - /* Configure PG2, PG11 and PG13 */ - GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; + /* Configure PG11 and PG13 */ + GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13; HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); /* Enable the Ethernet global Interrupt */ @@ -103,7 +104,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -111,7 +112,7 @@ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13); /* Disable the Ethernet global Interrupt */ NVIC_DisableIRQ(ETH_IRQn); diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c index 223af59..6423a3f 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c @@ -1,6 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2022, STMicroelectronics * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause * * SPDX-License-Identifier: Apache-2.0 * @@ -53,7 +54,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -74,8 +75,8 @@ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - /* Configure PG2, PG11 and PG13 */ - GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; + /* Configure PG11 and PG13 */ + GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13; HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); /* Enable the Ethernet global Interrupt */ @@ -103,7 +104,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -111,7 +112,7 @@ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13); /* Disable the Ethernet global Interrupt */ NVIC_DisableIRQ(ETH_IRQn); diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c index dd5e38e..25f8bf6 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c @@ -1,6 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2022, STMicroelectronics * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +58,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PG14 @@ -74,8 +75,8 @@ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - /* Configure PG2, PG11, PG13 and PG14 */ - GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14; + /* Configure PG11, PG13 and PG14 */ + GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14; HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); /* Enable the Ethernet global Interrupt */ @@ -103,14 +104,14 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PG14 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14); + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14); /* Disable the Ethernet global Interrupt */ NVIC_DisableIRQ(ETH_IRQn); diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c index 90d00bc..b66ca2c 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c @@ -1,6 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2022, STMicroelectronics * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause * * SPDX-License-Identifier: Apache-2.0 * @@ -48,7 +49,6 @@ /* Enable GPIOs clocks */ __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); /** ETH GPIO Configuration @@ -58,7 +58,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PD5 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PG14 @@ -75,10 +75,6 @@ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - /* Configure PD5 */ - GPIO_InitStructure.Pin = GPIO_PIN_5; - HAL_GPIO_Init(GPIOD, &GPIO_InitStructure); - /* Configure PG11, PG13 and PG14 */ GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14; HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); @@ -108,14 +104,13 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PD5 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PG14 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14); /* Disable the Ethernet global Interrupt */ diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c index 064c5a6..ebc2d04 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c @@ -1,6 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2022, STMicroelectronics * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause * * SPDX-License-Identifier: Apache-2.0 * @@ -58,7 +59,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -79,8 +80,8 @@ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - /* Configure PG2, PG11 and PG13 */ - GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; + /* Configure PG11 and PG13 */ + GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13; HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); /* Enable the Ethernet global Interrupt */ @@ -108,7 +109,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -116,7 +117,7 @@ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13); /* Disable the Ethernet global Interrupt */ NVIC_DisableIRQ(ETH_IRQn); diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c index 14bec83..aa12871 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c @@ -1,6 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2022, STMicroelectronics * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause * * SPDX-License-Identifier: Apache-2.0 * @@ -58,7 +59,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -79,8 +80,8 @@ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - /* Configure PG2, PG11 and PG13 */ - GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; + /* Configure PG11 and PG13 */ + GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13; HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); /* Enable the Ethernet global Interrupt */ @@ -108,7 +109,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -116,7 +117,7 @@ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13); /* Disable the Ethernet global Interrupt */ NVIC_DisableIRQ(ETH_IRQn); diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c index 0555987..70eef69 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c @@ -1,6 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2022, STMicroelectronics * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +58,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -78,8 +79,8 @@ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - /* Configure PG2, PG11 and PG13 */ - GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; + /* Configure PG11 and PG13 */ + GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13; HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); /* Enable the Ethernet global Interrupt */ @@ -107,7 +108,7 @@ RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> PG2 + RMII_MII_RXER ---------------------> none RMII_MII_TX_EN --------------------> PG11 RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD1 ---------------------> PB13 @@ -115,7 +116,7 @@ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13); /* Disable the Ethernet global Interrupt */ NVIC_DisableIRQ(ETH_IRQn); diff --git a/connectivity/nanostack/include/nanostack-interface/Nanostack.h b/connectivity/nanostack/include/nanostack-interface/Nanostack.h index f6cc27b..d3677e3 100644 --- a/connectivity/nanostack/include/nanostack-interface/Nanostack.h +++ b/connectivity/nanostack/include/nanostack-interface/Nanostack.h @@ -122,7 +122,7 @@ * NSAPI_ERROR_NO_SOCKET is returned if no socket is available. * * @param handle Destination for the handle to a newly created socket - * @param proto Protocol of socket to open, NSAPI_TCP or NSAPI_UDP + * @param proto Protocol of socket to open, NSAPI_TCP, NSAPI_UDP or NSAPI_ICMP * @return 0 on success, negative error code on failure */ nsapi_error_t socket_open(void **handle, nsapi_protocol_t proto) override; diff --git a/connectivity/nanostack/mbed-mesh-api/source/LoWPANNDInterface.cpp b/connectivity/nanostack/mbed-mesh-api/source/LoWPANNDInterface.cpp index 28c7d41..adb1bd3 100644 --- a/connectivity/nanostack/mbed-mesh-api/source/LoWPANNDInterface.cpp +++ b/connectivity/nanostack/mbed-mesh-api/source/LoWPANNDInterface.cpp @@ -28,7 +28,7 @@ public: nsapi_error_t bringup(bool dhcp, const char *ip, const char *netmask, const char *gw, - nsapi_ip_stack_t stack = IPV6_STACK, + nsapi_ip_stack_t stack = DEFAULT_STACK, bool blocking = true) override; nsapi_error_t bringdown() override; nsapi_error_t get_gateway(SocketAddress *sockAddr) override; diff --git a/connectivity/nanostack/mbed-mesh-api/source/MeshInterfaceNanostack.cpp b/connectivity/nanostack/mbed-mesh-api/source/MeshInterfaceNanostack.cpp index 35eb9ca..cf9a754 100644 --- a/connectivity/nanostack/mbed-mesh-api/source/MeshInterfaceNanostack.cpp +++ b/connectivity/nanostack/mbed-mesh-api/source/MeshInterfaceNanostack.cpp @@ -174,6 +174,7 @@ connect_semaphore.release(); } else if (status == MESH_DISCONNECTED) { disconnect_semaphore.release(); + connect_semaphore.release(); } } diff --git a/connectivity/nanostack/mbed-mesh-api/source/ThreadInterface.cpp b/connectivity/nanostack/mbed-mesh-api/source/ThreadInterface.cpp index 5a3dac8..89cf49d 100644 --- a/connectivity/nanostack/mbed-mesh-api/source/ThreadInterface.cpp +++ b/connectivity/nanostack/mbed-mesh-api/source/ThreadInterface.cpp @@ -27,7 +27,7 @@ public: nsapi_error_t bringup(bool dhcp, const char *ip, const char *netmask, const char *gw, - nsapi_ip_stack_t stack = IPV6_STACK, + nsapi_ip_stack_t stack = DEFAULT_STACK, bool blocking = true) override; nsapi_error_t bringdown() override; friend class Nanostack; diff --git a/connectivity/nanostack/mbed-mesh-api/source/WisunInterface.cpp b/connectivity/nanostack/mbed-mesh-api/source/WisunInterface.cpp index 75f89ee..e9cdb3d 100644 --- a/connectivity/nanostack/mbed-mesh-api/source/WisunInterface.cpp +++ b/connectivity/nanostack/mbed-mesh-api/source/WisunInterface.cpp @@ -34,7 +34,7 @@ public: nsapi_error_t bringup(bool dhcp, const char *ip, const char *netmask, const char *gw, - nsapi_ip_stack_t stack = IPV6_STACK, + nsapi_ip_stack_t stack = DEFAULT_STACK, bool blocking = true) override; nsapi_error_t bringdown() override; nsapi_error_t get_gateway(SocketAddress *address) override; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_socket.c b/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_socket.c index c520c20..a35a5b7 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_socket.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_socket.c @@ -1570,8 +1570,17 @@ } } - /* Try a routing table entry for greater-than-realm scope */ + /* For greater-than-realm scope, use default interface if a default interface ID */ + /* has been set (e.g. using setsockopt), else try a routing table entry */ if (addr_ipv6_scope(buf->dst_sa.address, NULL) > IPV6_SCOPE_REALM_LOCAL) { + if (socket_ptr->default_interface_id != -1) { + cur_interface = protocol_stack_interface_info_get_by_id(socket_ptr->default_interface_id); + if (cur_interface) { + return cur_interface; + } else { + return NULL; + } + } if (ipv6_buffer_route(buf)) { return buf->interface; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/TLS/tls_lib.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/TLS/tls_lib.c index aa70856..f276c30 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/TLS/tls_lib.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/TLS/tls_lib.c @@ -2095,7 +2095,7 @@ { uint8_t *ptr; prf_sec_param_t *prf_ptr = shalib_prf_param_get(); - uint8_t secret_buf[2 + 16 + 2 + 16]; + static uint8_t secret_buf[2 + 16 + 2 + 16]; tr_debug("CAL Master secret:"); //Her have to to be set check is #ifdef ECC diff --git a/connectivity/nanostack/source/Nanostack.cpp b/connectivity/nanostack/source/Nanostack.cpp index c62f2b0..5715be3 100644 --- a/connectivity/nanostack/source/Nanostack.cpp +++ b/connectivity/nanostack/source/Nanostack.cpp @@ -678,6 +678,8 @@ ns_proto = SOCKET_UDP; } else if (NSAPI_TCP == protocol) { ns_proto = SOCKET_TCP; + } else if (NSAPI_ICMP == protocol) { + ns_proto = SOCKET_ICMP; } else { MBED_ASSERT(false); return NSAPI_ERROR_UNSUPPORTED; diff --git a/connectivity/netsocket/source/TLSSocketWrapper.cpp b/connectivity/netsocket/source/TLSSocketWrapper.cpp index cebaf04..29ee132 100644 --- a/connectivity/netsocket/source/TLSSocketWrapper.cpp +++ b/connectivity/netsocket/source/TLSSocketWrapper.cpp @@ -77,7 +77,7 @@ TLSSocketWrapper::~TLSSocketWrapper() { if (_transport) { - close(); + TLSSocketWrapper::close(); } mbedtls_entropy_free(&_entropy); diff --git a/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp b/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp index aa256a7..a3dfcb1 100644 --- a/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp +++ b/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp @@ -218,22 +218,23 @@ Case cases[] = { - Case("TLSSOCKET_ECHOTEST", TLSSOCKET_ECHOTEST), - Case("TLSSOCKET_ECHOTEST_NONBLOCK", TLSSOCKET_ECHOTEST_NONBLOCK), +// Disable tests temporarily till echo server is back on +// Case("TLSSOCKET_ECHOTEST", TLSSOCKET_ECHOTEST), +// Case("TLSSOCKET_ECHOTEST_NONBLOCK", TLSSOCKET_ECHOTEST_NONBLOCK), Case("TLSSOCKET_CONNECT_INVALID", TLSSOCKET_CONNECT_INVALID), - Case("TLSSOCKET_ECHOTEST_BURST", TLSSOCKET_ECHOTEST_BURST), - Case("TLSSOCKET_ECHOTEST_BURST_NONBLOCK", TLSSOCKET_ECHOTEST_BURST_NONBLOCK), - Case("TLSSOCKET_RECV_TIMEOUT", TLSSOCKET_RECV_TIMEOUT), - Case("TLSSOCKET_ENDPOINT_CLOSE", TLSSOCKET_ENDPOINT_CLOSE), +// Case("TLSSOCKET_ECHOTEST_BURST", TLSSOCKET_ECHOTEST_BURST), +// Case("TLSSOCKET_ECHOTEST_BURST_NONBLOCK", TLSSOCKET_ECHOTEST_BURST_NONBLOCK), +// Case("TLSSOCKET_RECV_TIMEOUT", TLSSOCKET_RECV_TIMEOUT), +// Case("TLSSOCKET_ENDPOINT_CLOSE", TLSSOCKET_ENDPOINT_CLOSE), Case("TLSSOCKET_HANDSHAKE_INVALID", TLSSOCKET_HANDSHAKE_INVALID), Case("TLSSOCKET_OPEN_TWICE", TLSSOCKET_OPEN_TWICE), Case("TLSSOCKET_OPEN_LIMIT", TLSSOCKET_OPEN_LIMIT), Case("TLSSOCKET_OPEN_DESTRUCT", TLSSOCKET_OPEN_DESTRUCT), Case("TLSSOCKET_SEND_UNCONNECTED", TLSSOCKET_SEND_UNCONNECTED), - Case("TLSSOCKET_SEND_CLOSED", TLSSOCKET_SEND_CLOSED), - Case("TLSSOCKET_SEND_REPEAT", TLSSOCKET_SEND_REPEAT), - Case("TLSSOCKET_SEND_TIMEOUT", TLSSOCKET_SEND_TIMEOUT), - Case("TLSSOCKET_NO_CERT", TLSSOCKET_NO_CERT), +// Case("TLSSOCKET_SEND_CLOSED", TLSSOCKET_SEND_CLOSED), +// Case("TLSSOCKET_SEND_REPEAT", TLSSOCKET_SEND_REPEAT), +// Case("TLSSOCKET_SEND_TIMEOUT", TLSSOCKET_SEND_TIMEOUT), +// Case("TLSSOCKET_NO_CERT", TLSSOCKET_NO_CERT), // Temporarily removing this test, as TLS library consumes too much memory // and we see frequent memory allocation failures on architectures with less // RAM such as DISCO_L475VG_IOT1A and NUCLEO_F207ZG (both have 128 kB RAM) diff --git a/drivers/source/CAN.cpp b/drivers/source/CAN.cpp index f8aa18e..07ea344 100644 --- a/drivers/source/CAN.cpp +++ b/drivers/source/CAN.cpp @@ -19,6 +19,7 @@ #if DEVICE_CAN #include "platform/mbed_power_mgmt.h" +#include "platform/mbed_error.h" namespace mbed { @@ -82,6 +83,9 @@ { lock(); int ret = can_read(&_can, &msg, handle); + if (msg.len > 8) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_CAN, MBED_ERROR_CODE_READ_FAILED), "Read tried to write more than 8 bytes"); + } unlock(); return ret; } @@ -134,7 +138,7 @@ void CAN::attach(Callback func, IrqType type) { - lock(); + CAN::lock(); if (func) { // lock deep sleep only the first time if (!_irq[(CanIrqType)type]) { @@ -150,7 +154,7 @@ _irq[(CanIrqType)type] = nullptr; can_irq_set(&_can, (CanIrqType)type, 0); } - unlock(); + CAN::unlock(); } void CAN::_irq_handler(uintptr_t context, CanIrqType type) diff --git a/drivers/source/SPI.cpp b/drivers/source/SPI.cpp index cec9518..76e2b74 100644 --- a/drivers/source/SPI.cpp +++ b/drivers/source/SPI.cpp @@ -148,12 +148,12 @@ SPI::~SPI() { - lock(); + SPI::lock(); /* Make sure a stale pointer isn't left in peripheral's owner field */ if (_peripheral->owner == this) { _peripheral->owner = nullptr; } - unlock(); + SPI::unlock(); } SPI::spi_peripheral_s *SPI::_lookup(SPI::SPIName name) diff --git a/platform/include/platform/mbed_version.h b/platform/include/platform/mbed_version.h index 55e0c94..90f54ac 100644 --- a/platform/include/platform/mbed_version.h +++ b/platform/include/platform/mbed_version.h @@ -38,7 +38,7 @@ * * @note 99 is default value for development version (master branch) */ -#define MBED_MINOR_VERSION 16 +#define MBED_MINOR_VERSION 17 /** MBED_PATCH_VERSION * Mbed OS patch version diff --git a/storage/filesystem/fat/ChaN/ff.cpp b/storage/filesystem/fat/ChaN/ff.cpp index 70e2d3f..53b23a7 100644 --- a/storage/filesystem/fat/ChaN/ff.cpp +++ b/storage/filesystem/fat/ChaN/ff.cpp @@ -537,7 +537,7 @@ #elif FF_USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */ #if FF_FS_EXFAT #define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer and directory entry block scratchpad buffer */ -#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); } +#define INIT_NAMBUF(fs) { lfn = (WCHAR *)(ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN))); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); } #define FREE_NAMBUF() ff_memfree(lfn) #else #define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer */ @@ -555,6 +555,7 @@ + /*--------------------------------*/ /* Code conversion tables */ /*--------------------------------*/ diff --git a/storage/filesystem/source/Dir.cpp b/storage/filesystem/source/Dir.cpp index 11602aa..d659ad5 100644 --- a/storage/filesystem/source/Dir.cpp +++ b/storage/filesystem/source/Dir.cpp @@ -34,7 +34,7 @@ Dir::~Dir() { if (_fs) { - close(); + Dir::close(); } } diff --git a/storage/filesystem/source/File.cpp b/storage/filesystem/source/File.cpp index 7355cb9..49a1ef1 100644 --- a/storage/filesystem/source/File.cpp +++ b/storage/filesystem/source/File.cpp @@ -34,7 +34,7 @@ File::~File() { if (_fs) { - close(); + File::close(); } } diff --git a/storage/kvstore/securestore/source/SecureStore.cpp b/storage/kvstore/securestore/source/SecureStore.cpp index b3c7929..be14c10 100644 --- a/storage/kvstore/securestore/source/SecureStore.cpp +++ b/storage/kvstore/securestore/source/SecureStore.cpp @@ -789,7 +789,7 @@ mbedtls_entropy_free(_entropy); delete _entropy; delete _ih; - delete _scratch_buf; + delete[] _scratch_buf; _entropy = nullptr; } ret = _underlying_kv->deinit(); diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt b/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt index eb84b0d..3a8f706 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt +++ b/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt @@ -84,7 +84,6 @@ ${MXM_SOURCE_DIR}/FLC/flc_common.c ${MXM_SOURCE_DIR}/FLC/flc_me15.c ${MXM_SOURCE_DIR}/FLC/flc_reva.c - ${MXM_SOURCE_DIR}/FLC/flc_revb.c ${MXM_SOURCE_DIR}/GPIO/gpio_common.c ${MXM_SOURCE_DIR}/GPIO/gpio_me15.c diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h index 148d6d6..27beaf2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h @@ -1,10 +1,11 @@ /** * @file aes_key_regs.h * @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module. + * @note This file is @deprecated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,12 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _AES_KEY_REGS_H_ -#define _AES_KEY_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_KEY_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_KEY_REGS_H_ + +#warning "DEPRECATED(1-10-2023): aes_key_regs.h - Scheduled for removal. Please use aeskeys_regs.h." /* **** Includes **** */ #include @@ -46,11 +48,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,13 +77,18 @@ * @ingroup aes_key * @defgroup aes_key_registers AES_KEY_Registers * @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module. - * @details AES Key Registers. + * @details AES Key Registers. */ /** * @ingroup aes_key_registers * Structure type to access the AES_KEY Registers. */ +#if defined(__GNUC__) +__attribute__((deprecated("mxc_aes_key_regs_t struct and aes_key_regs.h no longer supported. Use aeskeys_regs.h and MXC_AESKEYS (mxc_aeskeys_regs_t) for AES Key Access. 1-10-2023"))) +#else +#warning "mxc_aes_key_regs_t struct and aes_key_regs.h no longer supported. Use aeskeys_regs.h and MXC_AESKEYS (mxc_aeskeys_regs_t) for AES Key Access. 1-10-2023" +#endif typedef struct { __IO uint32_t aes_key0; /**< \b 0x00: AES_KEY AES_KEY0 Register */ __IO uint32_t aes_key1; /**< \b 0x04: AES_KEY AES_KEY1 Register */ @@ -97,21 +104,21 @@ /** * @ingroup aes_key_registers * @defgroup AES_KEY_Register_Offsets Register Offsets - * @brief AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address. + * @brief AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address. * @{ */ - #define MXC_R_AES_KEY_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY Base Address: 0x0000 */ - #define MXC_R_AES_KEY_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY Base Address: 0x0004 */ - #define MXC_R_AES_KEY_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY Base Address: 0x0008 */ - #define MXC_R_AES_KEY_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY Base Address: 0x000C */ - #define MXC_R_AES_KEY_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY Base Address: 0x0010 */ - #define MXC_R_AES_KEY_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY Base Address: 0x0014 */ - #define MXC_R_AES_KEY_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY Base Address: 0x0018 */ - #define MXC_R_AES_KEY_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY Base Address: 0x001C */ +#define MXC_R_AES_KEY_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY Base Address: 0x0000 */ +#define MXC_R_AES_KEY_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY Base Address: 0x0004 */ +#define MXC_R_AES_KEY_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY Base Address: 0x0008 */ +#define MXC_R_AES_KEY_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY Base Address: 0x000C */ +#define MXC_R_AES_KEY_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY Base Address: 0x0010 */ +#define MXC_R_AES_KEY_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY Base Address: 0x0014 */ +#define MXC_R_AES_KEY_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY Base Address: 0x0018 */ +#define MXC_R_AES_KEY_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY Base Address: 0x001C */ /**@} end of group aes_key_registers */ #ifdef __cplusplus } #endif -#endif /* _AES_KEY_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_KEY_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h index cd154f3..1001144 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h @@ -1,10 +1,11 @@ /** * @file aes_regs.h * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _AES_REGS_H_ -#define _AES_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup aes * @defgroup aes_registers AES_Registers * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. - * @details AES Keys. + * @details AES Keys. */ /** @@ -94,14 +94,14 @@ /** * @ingroup aes_registers * @defgroup AES_Register_Offsets Register Offsets - * @brief AES Peripheral Register Offsets from the AES Base Peripheral Address. + * @brief AES Peripheral Register Offsets from the AES Base Peripheral Address. * @{ */ - #define MXC_R_AES_CTRL ((uint32_t)0x00000000UL) /**< Offset from AES Base Address: 0x0000 */ - #define MXC_R_AES_STATUS ((uint32_t)0x00000004UL) /**< Offset from AES Base Address: 0x0004 */ - #define MXC_R_AES_INTFL ((uint32_t)0x00000008UL) /**< Offset from AES Base Address: 0x0008 */ - #define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL) /**< Offset from AES Base Address: 0x000C */ - #define MXC_R_AES_FIFO ((uint32_t)0x00000010UL) /**< Offset from AES Base Address: 0x0010 */ +#define MXC_R_AES_CTRL ((uint32_t)0x00000000UL) /**< Offset from AES Base Address: 0x0000 */ +#define MXC_R_AES_STATUS ((uint32_t)0x00000004UL) /**< Offset from AES Base Address: 0x0004 */ +#define MXC_R_AES_INTFL ((uint32_t)0x00000008UL) /**< Offset from AES Base Address: 0x0008 */ +#define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL) /**< Offset from AES Base Address: 0x000C */ +#define MXC_R_AES_FIFO ((uint32_t)0x00000010UL) /**< Offset from AES Base Address: 0x0010 */ /**@} end of group aes_registers */ /** @@ -110,35 +110,35 @@ * @brief AES Control Register * @{ */ - #define MXC_F_AES_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_AES_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_AES_CTRL_DMA_RX_EN_POS 1 /**< CTRL_DMA_RX_EN Position */ - #define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */ +#define MXC_F_AES_CTRL_DMA_RX_EN_POS 1 /**< CTRL_DMA_RX_EN Position */ +#define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */ - #define MXC_F_AES_CTRL_DMA_TX_EN_POS 2 /**< CTRL_DMA_TX_EN Position */ - #define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */ +#define MXC_F_AES_CTRL_DMA_TX_EN_POS 2 /**< CTRL_DMA_TX_EN Position */ +#define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */ - #define MXC_F_AES_CTRL_START_POS 3 /**< CTRL_START Position */ - #define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS)) /**< CTRL_START Mask */ +#define MXC_F_AES_CTRL_START_POS 3 /**< CTRL_START Position */ +#define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS)) /**< CTRL_START Mask */ - #define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4 /**< CTRL_INPUT_FLUSH Position */ - #define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */ +#define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4 /**< CTRL_INPUT_FLUSH Position */ +#define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */ - #define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5 /**< CTRL_OUTPUT_FLUSH Position */ - #define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */ +#define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5 /**< CTRL_OUTPUT_FLUSH Position */ +#define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */ - #define MXC_F_AES_CTRL_KEY_SIZE_POS 6 /**< CTRL_KEY_SIZE Position */ - #define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */ - #define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */ - #define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */ - #define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */ - #define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */ - #define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */ - #define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */ +#define MXC_F_AES_CTRL_KEY_SIZE_POS 6 /**< CTRL_KEY_SIZE Position */ +#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */ - #define MXC_F_AES_CTRL_TYPE_POS 8 /**< CTRL_TYPE Position */ - #define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */ +#define MXC_F_AES_CTRL_TYPE_POS 8 /**< CTRL_TYPE Position */ +#define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */ /**@} end of group AES_CTRL_Register */ @@ -148,20 +148,20 @@ * @brief AES Status Register * @{ */ - #define MXC_F_AES_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ - #define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ +#define MXC_F_AES_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ - #define MXC_F_AES_STATUS_INPUT_EM_POS 1 /**< STATUS_INPUT_EM Position */ - #define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */ +#define MXC_F_AES_STATUS_INPUT_EM_POS 1 /**< STATUS_INPUT_EM Position */ +#define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */ - #define MXC_F_AES_STATUS_INPUT_FULL_POS 2 /**< STATUS_INPUT_FULL Position */ - #define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */ +#define MXC_F_AES_STATUS_INPUT_FULL_POS 2 /**< STATUS_INPUT_FULL Position */ +#define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */ - #define MXC_F_AES_STATUS_OUTPUT_EM_POS 3 /**< STATUS_OUTPUT_EM Position */ - #define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */ +#define MXC_F_AES_STATUS_OUTPUT_EM_POS 3 /**< STATUS_OUTPUT_EM Position */ +#define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */ - #define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4 /**< STATUS_OUTPUT_FULL Position */ - #define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */ +#define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4 /**< STATUS_OUTPUT_FULL Position */ +#define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */ /**@} end of group AES_STATUS_Register */ @@ -171,17 +171,20 @@ * @brief AES Interrupt Flag Register * @{ */ - #define MXC_F_AES_INTFL_DONE_POS 0 /**< INTFL_DONE Position */ - #define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS)) /**< INTFL_DONE Mask */ +#define MXC_F_AES_INTFL_DONE_POS 0 /**< INTFL_DONE Position */ +#define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS)) /**< INTFL_DONE Mask */ - #define MXC_F_AES_INTFL_KEY_CHANGE_POS 1 /**< INTFL_KEY_CHANGE Position */ - #define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */ +#define MXC_F_AES_INTFL_KEY_CHANGE_POS 1 /**< INTFL_KEY_CHANGE Position */ +#define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */ - #define MXC_F_AES_INTFL_KEY_ZERO_POS 2 /**< INTFL_KEY_ZERO Position */ - #define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */ +#define MXC_F_AES_INTFL_KEY_ZERO_POS 2 /**< INTFL_KEY_ZERO Position */ +#define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */ - #define MXC_F_AES_INTFL_OV_POS 3 /**< INTFL_OV Position */ - #define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */ +#define MXC_F_AES_INTFL_OV_POS 3 /**< INTFL_OV Position */ +#define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */ + +#define MXC_F_AES_INTFL_KEY_ONE_POS 4 /**< INTFL_KEY_ONE Position */ +#define MXC_F_AES_INTFL_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ONE_POS)) /**< INTFL_KEY_ONE Mask */ /**@} end of group AES_INTFL_Register */ @@ -191,17 +194,20 @@ * @brief AES Interrupt Enable Register * @{ */ - #define MXC_F_AES_INTEN_DONE_POS 0 /**< INTEN_DONE Position */ - #define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS)) /**< INTEN_DONE Mask */ +#define MXC_F_AES_INTEN_DONE_POS 0 /**< INTEN_DONE Position */ +#define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS)) /**< INTEN_DONE Mask */ - #define MXC_F_AES_INTEN_KEY_CHANGE_POS 1 /**< INTEN_KEY_CHANGE Position */ - #define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */ +#define MXC_F_AES_INTEN_KEY_CHANGE_POS 1 /**< INTEN_KEY_CHANGE Position */ +#define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */ - #define MXC_F_AES_INTEN_KEY_ZERO_POS 2 /**< INTEN_KEY_ZERO Position */ - #define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */ +#define MXC_F_AES_INTEN_KEY_ZERO_POS 2 /**< INTEN_KEY_ZERO Position */ +#define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */ - #define MXC_F_AES_INTEN_OV_POS 3 /**< INTEN_OV Position */ - #define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */ +#define MXC_F_AES_INTEN_OV_POS 3 /**< INTEN_OV Position */ +#define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */ + +#define MXC_F_AES_INTEN_KEY_ONE_POS 4 /**< INTEN_KEY_ONE Position */ +#define MXC_F_AES_INTEN_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ONE_POS)) /**< INTEN_KEY_ONE Mask */ /**@} end of group AES_INTEN_Register */ @@ -211,8 +217,8 @@ * @brief AES Data Register * @{ */ - #define MXC_F_AES_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ - #define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ +#define MXC_F_AES_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ /**@} end of group AES_FIFO_Register */ @@ -220,4 +226,4 @@ } #endif -#endif /* _AES_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h new file mode 100644 index 0000000..eeaa099 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h @@ -0,0 +1,117 @@ +/** + * @file aeskeys_regs.h + * @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module. + * @note This file is @generated. + */ + +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AESKEYS_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AESKEYS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup aeskeys + * @defgroup aeskeys_registers AESKEYS_Registers + * @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module. + * @details AES Key Registers. + */ + +/** + * @ingroup aeskeys_registers + * Structure type to access the AESKEYS Registers. + */ +typedef struct { + __IO uint32_t key0; /**< \b 0x00: AESKEYS KEY0 Register */ + __IO uint32_t key1; /**< \b 0x04: AESKEYS KEY1 Register */ + __IO uint32_t key2; /**< \b 0x08: AESKEYS KEY2 Register */ + __IO uint32_t key3; /**< \b 0x0C: AESKEYS KEY3 Register */ + __IO uint32_t key4; /**< \b 0x10: AESKEYS KEY4 Register */ + __IO uint32_t key5; /**< \b 0x14: AESKEYS KEY5 Register */ + __IO uint32_t key6; /**< \b 0x18: AESKEYS KEY6 Register */ + __IO uint32_t key7; /**< \b 0x1C: AESKEYS KEY7 Register */ +} mxc_aeskeys_regs_t; + +/* Register offsets for module AESKEYS */ +/** + * @ingroup aeskeys_registers + * @defgroup AESKEYS_Register_Offsets Register Offsets + * @brief AESKEYS Peripheral Register Offsets from the AESKEYS Base Peripheral Address. + * @{ + */ +#define MXC_R_AESKEYS_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AESKEYS Base Address: 0x0000 */ +#define MXC_R_AESKEYS_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AESKEYS Base Address: 0x0004 */ +#define MXC_R_AESKEYS_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AESKEYS Base Address: 0x0008 */ +#define MXC_R_AESKEYS_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AESKEYS Base Address: 0x000C */ +#define MXC_R_AESKEYS_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AESKEYS Base Address: 0x0010 */ +#define MXC_R_AESKEYS_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AESKEYS Base Address: 0x0014 */ +#define MXC_R_AESKEYS_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AESKEYS Base Address: 0x0018 */ +#define MXC_R_AESKEYS_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AESKEYS Base Address: 0x001C */ +/**@} end of group aeskeys_registers */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AESKEYS_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h index 31a19bb..b642e97 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h @@ -1,10 +1,11 @@ /** * @file crc_regs.h * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _CRC_REGS_H_ -#define _CRC_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_CRC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_CRC_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup crc * @defgroup crc_registers CRC_Registers * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module. - * @details CRC Registers. + * @details CRC Registers. */ /** @@ -84,11 +84,11 @@ */ typedef struct { __IO uint32_t ctrl; /**< \b 0x0000: CRC CTRL Register */ - union{ - __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ - __IO uint16_t datain16[2]; /**< \b 0x0004: CRC DATAIN16 Register */ - __IO uint8_t datain8[4]; /**< \b 0x0004: CRC DATAIN8 Register */ - }; + union { + __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ + __IO uint16_t datain16[2]; /**< \b 0x0004: CRC DATAIN16 Register */ + __IO uint8_t datain8[4]; /**< \b 0x0004: CRC DATAIN8 Register */ + }; __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ } mxc_crc_regs_t; @@ -97,15 +97,15 @@ /** * @ingroup crc_registers * @defgroup CRC_Register_Offsets Register Offsets - * @brief CRC Peripheral Register Offsets from the CRC Base Peripheral Address. + * @brief CRC Peripheral Register Offsets from the CRC Base Peripheral Address. * @{ */ - #define MXC_R_CRC_CTRL ((uint32_t)0x00000000UL) /**< Offset from CRC Base Address: 0x0000 */ - #define MXC_R_CRC_DATAIN32 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ - #define MXC_R_CRC_DATAIN16 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ - #define MXC_R_CRC_DATAIN8 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ - #define MXC_R_CRC_POLY ((uint32_t)0x00000008UL) /**< Offset from CRC Base Address: 0x0008 */ - #define MXC_R_CRC_VAL ((uint32_t)0x0000000CUL) /**< Offset from CRC Base Address: 0x000C */ +#define MXC_R_CRC_CTRL ((uint32_t)0x00000000UL) /**< Offset from CRC Base Address: 0x0000 */ +#define MXC_R_CRC_DATAIN32 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ +#define MXC_R_CRC_DATAIN16 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ +#define MXC_R_CRC_DATAIN8 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ +#define MXC_R_CRC_POLY ((uint32_t)0x00000008UL) /**< Offset from CRC Base Address: 0x0008 */ +#define MXC_R_CRC_VAL ((uint32_t)0x0000000CUL) /**< Offset from CRC Base Address: 0x000C */ /**@} end of group crc_registers */ /** @@ -114,23 +114,23 @@ * @brief CRC Control * @{ */ - #define MXC_F_CRC_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_CRC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_CRC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_CRC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_CRC_CTRL_DMA_EN_POS 1 /**< CTRL_DMA_EN Position */ - #define MXC_F_CRC_CTRL_DMA_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_DMA_EN_POS)) /**< CTRL_DMA_EN Mask */ +#define MXC_F_CRC_CTRL_DMA_EN_POS 1 /**< CTRL_DMA_EN Position */ +#define MXC_F_CRC_CTRL_DMA_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_DMA_EN_POS)) /**< CTRL_DMA_EN Mask */ - #define MXC_F_CRC_CTRL_MSB_POS 2 /**< CTRL_MSB Position */ - #define MXC_F_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_MSB_POS)) /**< CTRL_MSB Mask */ +#define MXC_F_CRC_CTRL_MSB_POS 2 /**< CTRL_MSB Position */ +#define MXC_F_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_MSB_POS)) /**< CTRL_MSB Mask */ - #define MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS 3 /**< CTRL_BYTE_SWAP_IN Position */ - #define MXC_F_CRC_CTRL_BYTE_SWAP_IN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS)) /**< CTRL_BYTE_SWAP_IN Mask */ +#define MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS 3 /**< CTRL_BYTE_SWAP_IN Position */ +#define MXC_F_CRC_CTRL_BYTE_SWAP_IN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS)) /**< CTRL_BYTE_SWAP_IN Mask */ - #define MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS 4 /**< CTRL_BYTE_SWAP_OUT Position */ - #define MXC_F_CRC_CTRL_BYTE_SWAP_OUT ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS)) /**< CTRL_BYTE_SWAP_OUT Mask */ +#define MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS 4 /**< CTRL_BYTE_SWAP_OUT Position */ +#define MXC_F_CRC_CTRL_BYTE_SWAP_OUT ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS)) /**< CTRL_BYTE_SWAP_OUT Mask */ - #define MXC_F_CRC_CTRL_BUSY_POS 16 /**< CTRL_BUSY Position */ - #define MXC_F_CRC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ +#define MXC_F_CRC_CTRL_BUSY_POS 16 /**< CTRL_BUSY Position */ +#define MXC_F_CRC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ /**@} end of group CRC_CTRL_Register */ @@ -140,8 +140,8 @@ * @brief CRC Data Input * @{ */ - #define MXC_F_CRC_DATAIN32_DATA_POS 0 /**< DATAIN32_DATA Position */ - #define MXC_F_CRC_DATAIN32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_DATAIN32_DATA_POS)) /**< DATAIN32_DATA Mask */ +#define MXC_F_CRC_DATAIN32_DATA_POS 0 /**< DATAIN32_DATA Position */ +#define MXC_F_CRC_DATAIN32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_DATAIN32_DATA_POS)) /**< DATAIN32_DATA Mask */ /**@} end of group CRC_DATAIN32_Register */ @@ -151,8 +151,8 @@ * @brief CRC Data Input * @{ */ - #define MXC_F_CRC_DATAIN16_DATA_POS 0 /**< DATAIN16_DATA Position */ - #define MXC_F_CRC_DATAIN16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CRC_DATAIN16_DATA_POS)) /**< DATAIN16_DATA Mask */ +#define MXC_F_CRC_DATAIN16_DATA_POS 0 /**< DATAIN16_DATA Position */ +#define MXC_F_CRC_DATAIN16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CRC_DATAIN16_DATA_POS)) /**< DATAIN16_DATA Mask */ /**@} end of group CRC_DATAIN16_Register */ @@ -162,8 +162,8 @@ * @brief CRC Data Input * @{ */ - #define MXC_F_CRC_DATAIN8_DATA_POS 0 /**< DATAIN8_DATA Position */ - #define MXC_F_CRC_DATAIN8_DATA ((uint8_t)(0xFFUL << MXC_F_CRC_DATAIN8_DATA_POS)) /**< DATAIN8_DATA Mask */ +#define MXC_F_CRC_DATAIN8_DATA_POS 0 /**< DATAIN8_DATA Position */ +#define MXC_F_CRC_DATAIN8_DATA ((uint8_t)(0xFFUL << MXC_F_CRC_DATAIN8_DATA_POS)) /**< DATAIN8_DATA Mask */ /**@} end of group CRC_DATAIN8_Register */ @@ -173,8 +173,8 @@ * @brief CRC Polynomial * @{ */ - #define MXC_F_CRC_POLY_POLY_POS 0 /**< POLY_POLY Position */ - #define MXC_F_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_POLY_POLY_POS)) /**< POLY_POLY Mask */ +#define MXC_F_CRC_POLY_POLY_POS 0 /**< POLY_POLY Position */ +#define MXC_F_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_POLY_POLY_POS)) /**< POLY_POLY Mask */ /**@} end of group CRC_POLY_Register */ @@ -184,8 +184,8 @@ * @brief Current CRC Value * @{ */ - #define MXC_F_CRC_VAL_VALUE_POS 0 /**< VAL_VALUE Position */ - #define MXC_F_CRC_VAL_VALUE ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_VAL_VALUE_POS)) /**< VAL_VALUE Mask */ +#define MXC_F_CRC_VAL_VALUE_POS 0 /**< VAL_VALUE Position */ +#define MXC_F_CRC_VAL_VALUE ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_VAL_VALUE_POS)) /**< VAL_VALUE Mask */ /**@} end of group CRC_VAL_Register */ @@ -193,4 +193,4 @@ } #endif -#endif /* _CRC_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_CRC_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h index f467b04..bbbbf14 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h @@ -1,10 +1,11 @@ /** * @file dma_regs.h * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _DMA_REGS_H_ -#define _DMA_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_DMA_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_DMA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,29 +75,25 @@ * @ingroup dma * @defgroup dma_registers DMA_Registers * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. - * @details DMA Controller Fully programmable, chaining capable DMA channels. + * @details DMA Controller Fully programmable, chaining capable DMA channels. */ /** * @ingroup dma_registers - * Structure type to access the DMA Channel Registers. - */ -typedef struct { - __IO uint32_t ctrl; /**< \b 0x100: DMA CTRL Register */ - __IO uint32_t status; /**< \b 0x104: DMA STATUS Register */ - __IO uint32_t src; /**< \b 0x108: DMA SRC Register */ - __IO uint32_t dst; /**< \b 0x10C: DMA DST Register */ - __IO uint32_t cnt; /**< \b 0x110: DMA CNT Register */ - __IO uint32_t srcrld; /**< \b 0x114: DMA SRCRLD Register */ - __IO uint32_t dstrld; /**< \b 0x118: DMA DSTRLD Register */ - __IO uint32_t cntrld; /**< \b 0x11C: DMA CNTRLD Register */ -} mxc_dma_ch_regs_t; - -/** - * @ingroup dma_registers * Structure type to access the DMA Registers. */ typedef struct { + __IO uint32_t ctrl; /**< \b 0x000: DMA CTRL Register */ + __IO uint32_t status; /**< \b 0x004: DMA STATUS Register */ + __IO uint32_t src; /**< \b 0x008: DMA SRC Register */ + __IO uint32_t dst; /**< \b 0x00C: DMA DST Register */ + __IO uint32_t cnt; /**< \b 0x010: DMA CNT Register */ + __IO uint32_t srcrld; /**< \b 0x014: DMA SRCRLD Register */ + __IO uint32_t dstrld; /**< \b 0x018: DMA DSTRLD Register */ + __IO uint32_t cntrld; /**< \b 0x01C: DMA CNTRLD Register */ +} mxc_dma_ch_regs_t; + +typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __I uint32_t rsv_0x8_0xff[62]; @@ -108,20 +104,20 @@ /** * @ingroup dma_registers * @defgroup DMA_Register_Offsets Register Offsets - * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. + * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. * @{ */ - #define MXC_R_DMA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ - #define MXC_R_DMA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: 0x0104 */ - #define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: 0x0108 */ - #define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: 0x010C */ - #define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: 0x0110 */ - #define MXC_R_DMA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: 0x0114 */ - #define MXC_R_DMA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: 0x0118 */ - #define MXC_R_DMA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: 0x011C */ - #define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ - #define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ - #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ +#define MXC_R_DMA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ +#define MXC_R_DMA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ +#define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: 0x0008 */ +#define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: 0x000C */ +#define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: 0x0010 */ +#define MXC_R_DMA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: 0x0014 */ +#define MXC_R_DMA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: 0x0018 */ +#define MXC_R_DMA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: 0x001C */ +#define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ +#define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ +#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ /**@} end of group dma_registers */ /** @@ -130,29 +126,29 @@ * @brief DMA Control Register. * @{ */ - #define MXC_F_DMA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */ - #define MXC_F_DMA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */ +#define MXC_F_DMA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */ +#define MXC_F_DMA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */ - #define MXC_F_DMA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */ - #define MXC_F_DMA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */ +#define MXC_F_DMA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */ +#define MXC_F_DMA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */ - #define MXC_F_DMA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */ - #define MXC_F_DMA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */ +#define MXC_F_DMA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */ +#define MXC_F_DMA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */ - #define MXC_F_DMA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */ - #define MXC_F_DMA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */ +#define MXC_F_DMA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */ +#define MXC_F_DMA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */ - #define MXC_F_DMA_INTEN_CH4_POS 4 /**< INTEN_CH4 Position */ - #define MXC_F_DMA_INTEN_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH4_POS)) /**< INTEN_CH4 Mask */ +#define MXC_F_DMA_INTEN_CH4_POS 4 /**< INTEN_CH4 Position */ +#define MXC_F_DMA_INTEN_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH4_POS)) /**< INTEN_CH4 Mask */ - #define MXC_F_DMA_INTEN_CH5_POS 5 /**< INTEN_CH5 Position */ - #define MXC_F_DMA_INTEN_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH5_POS)) /**< INTEN_CH5 Mask */ +#define MXC_F_DMA_INTEN_CH5_POS 5 /**< INTEN_CH5 Position */ +#define MXC_F_DMA_INTEN_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH5_POS)) /**< INTEN_CH5 Mask */ - #define MXC_F_DMA_INTEN_CH6_POS 6 /**< INTEN_CH6 Position */ - #define MXC_F_DMA_INTEN_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH6_POS)) /**< INTEN_CH6 Mask */ +#define MXC_F_DMA_INTEN_CH6_POS 6 /**< INTEN_CH6 Position */ +#define MXC_F_DMA_INTEN_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH6_POS)) /**< INTEN_CH6 Mask */ - #define MXC_F_DMA_INTEN_CH7_POS 7 /**< INTEN_CH7 Position */ - #define MXC_F_DMA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */ +#define MXC_F_DMA_INTEN_CH7_POS 7 /**< INTEN_CH7 Position */ +#define MXC_F_DMA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */ /**@} end of group DMA_INTEN_Register */ @@ -162,29 +158,29 @@ * @brief DMA Interrupt Register. * @{ */ - #define MXC_F_DMA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */ - #define MXC_F_DMA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */ +#define MXC_F_DMA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */ +#define MXC_F_DMA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */ - #define MXC_F_DMA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */ - #define MXC_F_DMA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */ +#define MXC_F_DMA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */ +#define MXC_F_DMA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */ - #define MXC_F_DMA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */ - #define MXC_F_DMA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */ +#define MXC_F_DMA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */ +#define MXC_F_DMA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */ - #define MXC_F_DMA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */ - #define MXC_F_DMA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */ +#define MXC_F_DMA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */ +#define MXC_F_DMA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */ - #define MXC_F_DMA_INTFL_CH4_POS 4 /**< INTFL_CH4 Position */ - #define MXC_F_DMA_INTFL_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS)) /**< INTFL_CH4 Mask */ +#define MXC_F_DMA_INTFL_CH4_POS 4 /**< INTFL_CH4 Position */ +#define MXC_F_DMA_INTFL_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS)) /**< INTFL_CH4 Mask */ - #define MXC_F_DMA_INTFL_CH5_POS 5 /**< INTFL_CH5 Position */ - #define MXC_F_DMA_INTFL_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS)) /**< INTFL_CH5 Mask */ +#define MXC_F_DMA_INTFL_CH5_POS 5 /**< INTFL_CH5 Position */ +#define MXC_F_DMA_INTFL_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS)) /**< INTFL_CH5 Mask */ - #define MXC_F_DMA_INTFL_CH6_POS 6 /**< INTFL_CH6 Position */ - #define MXC_F_DMA_INTFL_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS)) /**< INTFL_CH6 Mask */ +#define MXC_F_DMA_INTFL_CH6_POS 6 /**< INTFL_CH6 Position */ +#define MXC_F_DMA_INTFL_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS)) /**< INTFL_CH6 Mask */ - #define MXC_F_DMA_INTFL_CH7_POS 7 /**< INTFL_CH7 Position */ - #define MXC_F_DMA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */ +#define MXC_F_DMA_INTFL_CH7_POS 7 /**< INTFL_CH7 Position */ +#define MXC_F_DMA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */ /**@} end of group DMA_INTFL_Register */ @@ -194,147 +190,147 @@ * @brief DMA Channel Control Register. * @{ */ - #define MXC_F_DMA_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_DMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_DMA_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_DMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_DMA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */ - #define MXC_F_DMA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */ +#define MXC_F_DMA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */ +#define MXC_F_DMA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */ - #define MXC_F_DMA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */ - #define MXC_F_DMA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */ - #define MXC_V_DMA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */ - #define MXC_S_DMA_CTRL_PRI_HIGH (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */ - #define MXC_V_DMA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */ - #define MXC_S_DMA_CTRL_PRI_MEDHIGH (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */ - #define MXC_V_DMA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */ - #define MXC_S_DMA_CTRL_PRI_MEDLOW (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */ - #define MXC_V_DMA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */ - #define MXC_S_DMA_CTRL_PRI_LOW (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */ +#define MXC_F_DMA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */ +#define MXC_F_DMA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */ +#define MXC_V_DMA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */ +#define MXC_S_DMA_CTRL_PRI_HIGH (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */ +#define MXC_V_DMA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */ +#define MXC_S_DMA_CTRL_PRI_MEDHIGH (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */ +#define MXC_V_DMA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */ +#define MXC_S_DMA_CTRL_PRI_MEDLOW (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */ +#define MXC_V_DMA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */ +#define MXC_S_DMA_CTRL_PRI_LOW (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */ - #define MXC_F_DMA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */ - #define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ - #define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ - #define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ - #define MXC_V_DMA_CTRL_REQUEST_SPI0RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_SPI2RX ((uint32_t)0x3UL) /**< CTRL_REQUEST_SPI2RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_SPI2RX (MXC_V_DMA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_I2C2RX ((uint32_t)0xAUL) /**< CTRL_REQUEST_I2C2RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_I2C2RX (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_UART2RX (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_SPI3RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_SPI3RX (MXC_V_DMA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */ - #define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_UART3RX ((uint32_t)0x1CUL) /**< CTRL_REQUEST_UART3RX Value */ - #define MXC_S_DMA_CTRL_REQUEST_UART3RX (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3RX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_I2SRX ((uint32_t)0x1EUL) /**< CTRL_REQUEST_I2SRX Value */ - #define MXC_S_DMA_CTRL_REQUEST_I2SRX (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2SRX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_SPI2TX ((uint32_t)0x23UL) /**< CTRL_REQUEST_SPI2TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_SPI2TX (MXC_V_DMA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_I2C2TX ((uint32_t)0x2AUL) /**< CTRL_REQUEST_I2C2TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_I2C2TX (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */ - #define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_UART2TX (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_SPI3TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_SPI3TX (MXC_V_DMA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */ - #define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_UART3TX ((uint32_t)0x3CUL) /**< CTRL_REQUEST_UART3TX Value */ - #define MXC_S_DMA_CTRL_REQUEST_UART3TX (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3TX Setting */ - #define MXC_V_DMA_CTRL_REQUEST_I2STX ((uint32_t)0x3EUL) /**< CTRL_REQUEST_I2STX Value */ - #define MXC_S_DMA_CTRL_REQUEST_I2STX (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2STX Setting */ +#define MXC_F_DMA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */ +#define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ +#define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ +#define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI0RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI2RX ((uint32_t)0x3UL) /**< CTRL_REQUEST_SPI2RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI2RX (MXC_V_DMA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C2RX ((uint32_t)0xAUL) /**< CTRL_REQUEST_I2C2RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C2RX (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART2RX (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI3RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI3RX (MXC_V_DMA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART3RX ((uint32_t)0x1CUL) /**< CTRL_REQUEST_UART3RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART3RX (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2SRX ((uint32_t)0x1EUL) /**< CTRL_REQUEST_I2SRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2SRX (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2SRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI2TX ((uint32_t)0x23UL) /**< CTRL_REQUEST_SPI2TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI2TX (MXC_V_DMA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C2TX ((uint32_t)0x2AUL) /**< CTRL_REQUEST_I2C2TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C2TX (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART2TX (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI3TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI3TX (MXC_V_DMA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART3TX ((uint32_t)0x3CUL) /**< CTRL_REQUEST_UART3TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART3TX (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2STX ((uint32_t)0x3EUL) /**< CTRL_REQUEST_I2STX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2STX (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2STX Setting */ - #define MXC_F_DMA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ - #define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ +#define MXC_F_DMA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ +#define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ - #define MXC_F_DMA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */ - #define MXC_F_DMA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */ - #define MXC_V_DMA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */ - #define MXC_S_DMA_CTRL_TO_PER_TO4 (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */ - #define MXC_V_DMA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */ - #define MXC_S_DMA_CTRL_TO_PER_TO8 (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */ - #define MXC_V_DMA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */ - #define MXC_S_DMA_CTRL_TO_PER_TO16 (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */ - #define MXC_V_DMA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */ - #define MXC_S_DMA_CTRL_TO_PER_TO32 (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */ - #define MXC_V_DMA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */ - #define MXC_S_DMA_CTRL_TO_PER_TO64 (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */ - #define MXC_V_DMA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */ - #define MXC_S_DMA_CTRL_TO_PER_TO128 (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */ - #define MXC_V_DMA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */ - #define MXC_S_DMA_CTRL_TO_PER_TO256 (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */ - #define MXC_V_DMA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */ - #define MXC_S_DMA_CTRL_TO_PER_TO512 (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */ +#define MXC_F_DMA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */ +#define MXC_F_DMA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */ +#define MXC_V_DMA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO4 (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO8 (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO16 (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO32 (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO64 (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO128 (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO256 (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO512 (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */ - #define MXC_F_DMA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */ - #define MXC_F_DMA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */ - #define MXC_V_DMA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */ - #define MXC_S_DMA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */ - #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */ - #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */ - #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */ - #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */ - #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */ - #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */ +#define MXC_F_DMA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */ +#define MXC_F_DMA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */ - #define MXC_F_DMA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */ - #define MXC_F_DMA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */ - #define MXC_V_DMA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */ - #define MXC_S_DMA_CTRL_SRCWD_BYTE (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */ - #define MXC_V_DMA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */ - #define MXC_S_DMA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */ - #define MXC_V_DMA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */ - #define MXC_S_DMA_CTRL_SRCWD_WORD (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */ +#define MXC_F_DMA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */ +#define MXC_F_DMA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */ +#define MXC_V_DMA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */ +#define MXC_S_DMA_CTRL_SRCWD_BYTE (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */ +#define MXC_V_DMA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */ +#define MXC_S_DMA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */ +#define MXC_V_DMA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */ +#define MXC_S_DMA_CTRL_SRCWD_WORD (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */ - #define MXC_F_DMA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */ - #define MXC_F_DMA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */ +#define MXC_F_DMA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */ +#define MXC_F_DMA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */ - #define MXC_F_DMA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */ - #define MXC_F_DMA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */ - #define MXC_V_DMA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */ - #define MXC_S_DMA_CTRL_DSTWD_BYTE (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */ - #define MXC_V_DMA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */ - #define MXC_S_DMA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */ - #define MXC_V_DMA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */ - #define MXC_S_DMA_CTRL_DSTWD_WORD (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */ +#define MXC_F_DMA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */ +#define MXC_F_DMA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */ +#define MXC_V_DMA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */ +#define MXC_S_DMA_CTRL_DSTWD_BYTE (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */ +#define MXC_V_DMA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */ +#define MXC_S_DMA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */ +#define MXC_V_DMA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */ +#define MXC_S_DMA_CTRL_DSTWD_WORD (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */ - #define MXC_F_DMA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */ - #define MXC_F_DMA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */ +#define MXC_F_DMA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */ +#define MXC_F_DMA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */ - #define MXC_F_DMA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */ - #define MXC_F_DMA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */ +#define MXC_F_DMA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */ +#define MXC_F_DMA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */ - #define MXC_F_DMA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */ - #define MXC_F_DMA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */ +#define MXC_F_DMA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */ +#define MXC_F_DMA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */ - #define MXC_F_DMA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */ - #define MXC_F_DMA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */ +#define MXC_F_DMA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */ +#define MXC_F_DMA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */ /**@} end of group DMA_CTRL_Register */ @@ -344,23 +340,23 @@ * @brief DMA Channel Status Register. * @{ */ - #define MXC_F_DMA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */ - #define MXC_F_DMA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ +#define MXC_F_DMA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */ +#define MXC_F_DMA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ - #define MXC_F_DMA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */ - #define MXC_F_DMA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */ +#define MXC_F_DMA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */ +#define MXC_F_DMA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */ - #define MXC_F_DMA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */ - #define MXC_F_DMA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */ +#define MXC_F_DMA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */ +#define MXC_F_DMA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */ - #define MXC_F_DMA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */ - #define MXC_F_DMA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */ +#define MXC_F_DMA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */ +#define MXC_F_DMA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */ - #define MXC_F_DMA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */ - #define MXC_F_DMA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */ +#define MXC_F_DMA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */ +#define MXC_F_DMA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */ - #define MXC_F_DMA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */ - #define MXC_F_DMA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */ +#define MXC_F_DMA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */ +#define MXC_F_DMA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */ /**@} end of group DMA_STATUS_Register */ @@ -374,8 +370,8 @@ * register is reloaded with the contents of DMA_SRC_RLD. * @{ */ - #define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ - #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ +#define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ +#define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ /**@} end of group DMA_SRC_Register */ @@ -389,8 +385,8 @@ * while RLDEN=1, the register is reloaded with DMA_DST_RLD. * @{ */ - #define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ - #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ +#define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ +#define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ /**@} end of group DMA_DST_Register */ @@ -403,8 +399,8 @@ * reaches 0, a count-to-zero condition is triggered. * @{ */ - #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ - #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ +#define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ +#define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ /**@} end of group DMA_CNT_Register */ @@ -415,8 +411,8 @@ * upon a count-to-zero condition. * @{ */ - #define MXC_F_DMA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */ - #define MXC_F_DMA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */ +#define MXC_F_DMA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */ +#define MXC_F_DMA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */ /**@} end of group DMA_SRCRLD_Register */ @@ -427,8 +423,8 @@ * DMA0_DST upon a count-to-zero condition. * @{ */ - #define MXC_F_DMA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */ - #define MXC_F_DMA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */ +#define MXC_F_DMA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */ +#define MXC_F_DMA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */ /**@} end of group DMA_DSTRLD_Register */ @@ -438,11 +434,11 @@ * @brief DMA Channel Count Reload Register. * @{ */ - #define MXC_F_DMA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */ - #define MXC_F_DMA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */ +#define MXC_F_DMA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */ +#define MXC_F_DMA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */ - #define MXC_F_DMA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */ - #define MXC_F_DMA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */ +#define MXC_F_DMA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */ +#define MXC_F_DMA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */ /**@} end of group DMA_CNTRLD_Register */ @@ -450,4 +446,4 @@ } #endif -#endif /* _DMA_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_DMA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h index ba9c390..f4921dc 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h @@ -1,10 +1,11 @@ /** * @file ecc_regs.h * @brief Registers, Bit Masks and Bit Positions for the ECC Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _ECC_REGS_H_ -#define _ECC_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ECC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ECC_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup ecc * @defgroup ecc_registers ECC_Registers * @brief Registers, Bit Masks and Bit Positions for the ECC Peripheral Module. - * @details Error Correction Code + * @details Trim System Initilazation Registers. ECC Registers for MAX32670. */ /** @@ -91,26 +91,26 @@ /** * @ingroup ecc_registers * @defgroup ECC_Register_Offsets Register Offsets - * @brief ECC Peripheral Register Offsets from the ECC Base Peripheral Address. + * @brief ECC Peripheral Register Offsets from the ECC Base Peripheral Address. * @{ */ - #define MXC_R_ECC_EN ((uint32_t)0x00000008UL) /**< Offset from ECC Base Address: 0x0008 */ +#define MXC_R_ECC_EN ((uint32_t)0x00000008UL) /**< Offset from ECC Base Address: 0x0008 */ /**@} end of group ecc_registers */ /** * @ingroup ecc_registers * @defgroup ECC_EN ECC_EN - * @brief ECC Enable Register + * @brief ECC Enable Register. * @{ */ - #define MXC_F_ECC_EN_RAM_POS 8 /**< EN_RAM Position */ - #define MXC_F_ECC_EN_RAM ((uint32_t)(0x1UL << MXC_F_ECC_EN_RAM_POS)) /**< EN_RAM Mask */ +#define MXC_F_ECC_EN_SRAM_POS 8 /**< EN_SRAM Position */ +#define MXC_F_ECC_EN_SRAM ((uint32_t)(0x1UL << MXC_F_ECC_EN_SRAM_POS)) /**< EN_SRAM Mask */ - #define MXC_F_ECC_EN_ICC0_POS 9 /**< EN_ICC0 Position */ - #define MXC_F_ECC_EN_ICC0 ((uint32_t)(0x1UL << MXC_F_ECC_EN_ICC0_POS)) /**< EN_ICC0 Mask */ +#define MXC_F_ECC_EN_ICC_POS 9 /**< EN_ICC Position */ +#define MXC_F_ECC_EN_ICC ((uint32_t)(0x1UL << MXC_F_ECC_EN_ICC_POS)) /**< EN_ICC Mask */ - #define MXC_F_ECC_EN_FLASH_POS 10 /**< EN_FLASH Position */ - #define MXC_F_ECC_EN_FLASH ((uint32_t)(0x1UL << MXC_F_ECC_EN_FLASH_POS)) /**< EN_FLASH Mask */ +#define MXC_F_ECC_EN_FLASH_POS 10 /**< EN_FLASH Position */ +#define MXC_F_ECC_EN_FLASH ((uint32_t)(0x1UL << MXC_F_ECC_EN_FLASH_POS)) /**< EN_FLASH Mask */ /**@} end of group ECC_EN_Register */ @@ -118,4 +118,4 @@ } #endif -#endif /* _ECC_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ECC_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/emcc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/emcc_regs.h deleted file mode 100644 index 8e170a9..0000000 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/emcc_regs.h +++ /dev/null @@ -1,180 +0,0 @@ -/** - * @file emcc_regs.h - * @brief Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module. - */ - -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - * - * - *************************************************************************** */ - -#ifndef _EMCC_REGS_H_ -#define _EMCC_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup emcc - * @defgroup emcc_registers EMCC_Registers - * @brief Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module. - * @details External Memory Cache Controller Registers. - */ - -/** - * @ingroup emcc_registers - * Structure type to access the EMCC Registers. - */ -typedef struct { - __I uint32_t cache_id; /**< \b 0x0000: EMCC CACHE_ID Register */ - __I uint32_t memcfg; /**< \b 0x0004: EMCC MEMCFG Register */ - __I uint32_t rsv_0x8_0xff[62]; - __IO uint32_t cache_ctrl; /**< \b 0x0100: EMCC CACHE_CTRL Register */ - __I uint32_t rsv_0x104_0x6ff[383]; - __IO uint32_t invalidate; /**< \b 0x0700: EMCC INVALIDATE Register */ -} mxc_emcc_regs_t; - -/* Register offsets for module EMCC */ -/** - * @ingroup emcc_registers - * @defgroup EMCC_Register_Offsets Register Offsets - * @brief EMCC Peripheral Register Offsets from the EMCC Base Peripheral Address. - * @{ - */ - #define MXC_R_EMCC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from EMCC Base Address: 0x0000 */ - #define MXC_R_EMCC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from EMCC Base Address: 0x0004 */ - #define MXC_R_EMCC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from EMCC Base Address: 0x0100 */ - #define MXC_R_EMCC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from EMCC Base Address: 0x0700 */ -/**@} end of group emcc_registers */ - -/** - * @ingroup emcc_registers - * @defgroup EMCC_CACHE_ID EMCC_CACHE_ID - * @brief Cache ID Register. - * @{ - */ - #define MXC_F_EMCC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ - #define MXC_F_EMCC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */ - - #define MXC_F_EMCC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ - #define MXC_F_EMCC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_EMCC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */ - - #define MXC_F_EMCC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ - #define MXC_F_EMCC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ - -/**@} end of group EMCC_CACHE_ID_Register */ - -/** - * @ingroup emcc_registers - * @defgroup EMCC_MEMCFG EMCC_MEMCFG - * @brief Memory Configuration Register. - * @{ - */ - #define MXC_F_EMCC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */ - #define MXC_F_EMCC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */ - - #define MXC_F_EMCC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */ - #define MXC_F_EMCC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */ - -/**@} end of group EMCC_MEMCFG_Register */ - -/** - * @ingroup emcc_registers - * @defgroup EMCC_CACHE_CTRL EMCC_CACHE_CTRL - * @brief Cache Control and Status Register. - * @{ - */ - #define MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */ - #define MXC_F_EMCC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */ - - #define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS 1 /**< CACHE_CTRL_WRITE_ALLOC_EN Position */ - #define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS)) /**< CACHE_CTRL_WRITE_ALLOC_EN Mask */ - - #define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS 2 /**< CACHE_CTRL_CWFST_DIS Position */ - #define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS)) /**< CACHE_CTRL_CWFST_DIS Mask */ - - #define MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */ - #define MXC_F_EMCC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */ - -/**@} end of group EMCC_CACHE_CTRL_Register */ - -/** - * @ingroup emcc_registers - * @defgroup EMCC_INVALIDATE EMCC_INVALIDATE - * @brief Invalidate All Cache Contents. Any time this register location is written - * (regardless of the data value), the cache controller immediately begins - * invalidating the entire contents of the cache memory. The cache will be in - * bypass mode until the invalidate operation is complete. System software can - * examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the - * invalidate operation is complete. Note that it is not necessary to disable the - * cache controller prior to beginning this operation. Reads from this register - * always return 0. - * @{ - */ - #define MXC_F_EMCC_INVALIDATE_IA_POS 0 /**< INVALIDATE_IA Position */ - #define MXC_F_EMCC_INVALIDATE_IA ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMCC_INVALIDATE_IA_POS)) /**< INVALIDATE_IA Mask */ - -/**@} end of group EMCC_INVALIDATE_Register */ - -#ifdef __cplusplus -} -#endif - -#endif /* _EMCC_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h index 84c31ba..6467f57 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h @@ -1,10 +1,11 @@ /** * @file fcr_regs.h * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _FCR_REGS_H_ -#define _FCR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FCR_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup fcr * @defgroup fcr_registers FCR_Registers * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. - * @details Function Control Register. + * @details Function Control Register. */ /** @@ -93,13 +93,13 @@ /** * @ingroup fcr_registers * @defgroup FCR_Register_Offsets Register Offsets - * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. + * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. * @{ */ - #define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: 0x0000 */ - #define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: 0x0004 */ - #define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: 0x0008 */ - #define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: 0x000C */ +#define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: 0x0000 */ +#define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: 0x0004 */ +#define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: 0x0008 */ +#define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: 0x000C */ /**@} end of group fcr_registers */ /** @@ -108,26 +108,26 @@ * @brief Register 0. * @{ */ - #define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS 0 /**< FCTRL0_ERFO_RANGE_SEL Position */ - #define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL ((uint32_t)(0x7UL << MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS)) /**< FCTRL0_ERFO_RANGE_SEL Mask */ +#define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS 0 /**< FCTRL0_ERFO_RANGE_SEL Position */ +#define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL ((uint32_t)(0x7UL << MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS)) /**< FCTRL0_ERFO_RANGE_SEL Mask */ - #define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS 20 /**< FCTRL0_I2C0_SDA_FILTER_EN Position */ - #define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C0_SDA_FILTER_EN Mask */ +#define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS 20 /**< FCTRL0_I2C0_SDA_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C0_SDA_FILTER_EN Mask */ - #define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS 21 /**< FCTRL0_I2C0_SCL_FILTER_EN Position */ - #define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C0_SCL_FILTER_EN Mask */ +#define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS 21 /**< FCTRL0_I2C0_SCL_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C0_SCL_FILTER_EN Mask */ - #define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS 22 /**< FCTRL0_I2C1_SDA_FILTER_EN Position */ - #define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C1_SDA_FILTER_EN Mask */ +#define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS 22 /**< FCTRL0_I2C1_SDA_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C1_SDA_FILTER_EN Mask */ - #define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS 23 /**< FCTRL0_I2C1_SCL_FILTER_EN Position */ - #define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C1_SCL_FILTER_EN Mask */ +#define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS 23 /**< FCTRL0_I2C1_SCL_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C1_SCL_FILTER_EN Mask */ - #define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS 24 /**< FCTRL0_I2C2_SDA_FILTER_EN Position */ - #define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C2_SDA_FILTER_EN Mask */ +#define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS 24 /**< FCTRL0_I2C2_SDA_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C2_SDA_FILTER_EN Mask */ - #define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS 25 /**< FCTRL0_I2C2_SCL_FILTER_EN Position */ - #define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C2_SCL_FILTER_EN Mask */ +#define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS 25 /**< FCTRL0_I2C2_SCL_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C2_SCL_FILTER_EN Mask */ /**@} end of group FCR_FCTRL0_Register */ @@ -137,26 +137,26 @@ * @brief Register 1. * @{ */ - #define MXC_F_FCR_AUTOCAL0_SEL_POS 0 /**< AUTOCAL0_SEL Position */ - #define MXC_F_FCR_AUTOCAL0_SEL ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_SEL_POS)) /**< AUTOCAL0_SEL Mask */ +#define MXC_F_FCR_AUTOCAL0_SEL_POS 0 /**< AUTOCAL0_SEL Position */ +#define MXC_F_FCR_AUTOCAL0_SEL ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_SEL_POS)) /**< AUTOCAL0_SEL Mask */ - #define MXC_F_FCR_AUTOCAL0_EN_POS 1 /**< AUTOCAL0_EN Position */ - #define MXC_F_FCR_AUTOCAL0_EN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) /**< AUTOCAL0_EN Mask */ +#define MXC_F_FCR_AUTOCAL0_EN_POS 1 /**< AUTOCAL0_EN Position */ +#define MXC_F_FCR_AUTOCAL0_EN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) /**< AUTOCAL0_EN Mask */ - #define MXC_F_FCR_AUTOCAL0_LOAD_POS 2 /**< AUTOCAL0_LOAD Position */ - #define MXC_F_FCR_AUTOCAL0_LOAD ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_POS)) /**< AUTOCAL0_LOAD Mask */ +#define MXC_F_FCR_AUTOCAL0_LOAD_POS 2 /**< AUTOCAL0_LOAD Position */ +#define MXC_F_FCR_AUTOCAL0_LOAD ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_POS)) /**< AUTOCAL0_LOAD Mask */ - #define MXC_F_FCR_AUTOCAL0_INVERT_POS 3 /**< AUTOCAL0_INVERT Position */ - #define MXC_F_FCR_AUTOCAL0_INVERT ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_INVERT_POS)) /**< AUTOCAL0_INVERT Mask */ +#define MXC_F_FCR_AUTOCAL0_INVERT_POS 3 /**< AUTOCAL0_INVERT Position */ +#define MXC_F_FCR_AUTOCAL0_INVERT ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_INVERT_POS)) /**< AUTOCAL0_INVERT Mask */ - #define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ - #define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ +#define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ +#define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ - #define MXC_F_FCR_AUTOCAL0_GAIN_POS 8 /**< AUTOCAL0_GAIN Position */ - #define MXC_F_FCR_AUTOCAL0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_GAIN_POS)) /**< AUTOCAL0_GAIN Mask */ +#define MXC_F_FCR_AUTOCAL0_GAIN_POS 8 /**< AUTOCAL0_GAIN Position */ +#define MXC_F_FCR_AUTOCAL0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_GAIN_POS)) /**< AUTOCAL0_GAIN Mask */ - #define MXC_F_FCR_AUTOCAL0_TRIM_POS 23 /**< AUTOCAL0_TRIM Position */ - #define MXC_F_FCR_AUTOCAL0_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_POS)) /**< AUTOCAL0_TRIM Mask */ +#define MXC_F_FCR_AUTOCAL0_TRIM_POS 23 /**< AUTOCAL0_TRIM Position */ +#define MXC_F_FCR_AUTOCAL0_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_POS)) /**< AUTOCAL0_TRIM Mask */ /**@} end of group FCR_AUTOCAL0_Register */ @@ -166,8 +166,8 @@ * @brief Register 2. * @{ */ - #define MXC_F_FCR_AUTOCAL1_INITIAL_POS 0 /**< AUTOCAL1_INITIAL Position */ - #define MXC_F_FCR_AUTOCAL1_INITIAL ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITIAL_POS)) /**< AUTOCAL1_INITIAL Mask */ +#define MXC_F_FCR_AUTOCAL1_INITIAL_POS 0 /**< AUTOCAL1_INITIAL Position */ +#define MXC_F_FCR_AUTOCAL1_INITIAL ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITIAL_POS)) /**< AUTOCAL1_INITIAL Mask */ /**@} end of group FCR_AUTOCAL1_Register */ @@ -177,11 +177,11 @@ * @brief Register 3. * @{ */ - #define MXC_F_FCR_AUTOCAL2_RUNTIME_POS 0 /**< AUTOCAL2_RUNTIME Position */ - #define MXC_F_FCR_AUTOCAL2_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) /**< AUTOCAL2_RUNTIME Mask */ +#define MXC_F_FCR_AUTOCAL2_RUNTIME_POS 0 /**< AUTOCAL2_RUNTIME Position */ +#define MXC_F_FCR_AUTOCAL2_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) /**< AUTOCAL2_RUNTIME Mask */ - #define MXC_F_FCR_AUTOCAL2_DIV_POS 8 /**< AUTOCAL2_DIV Position */ - #define MXC_F_FCR_AUTOCAL2_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) /**< AUTOCAL2_DIV Mask */ +#define MXC_F_FCR_AUTOCAL2_DIV_POS 8 /**< AUTOCAL2_DIV Position */ +#define MXC_F_FCR_AUTOCAL2_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) /**< AUTOCAL2_DIV Mask */ /**@} end of group FCR_AUTOCAL2_Register */ @@ -189,4 +189,4 @@ } #endif -#endif /* _FCR_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FCR_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h index 9617e87..6b84288 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h @@ -1,10 +1,11 @@ /** * @file flc_regs.h * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _FLC_REGS_H_ -#define _FLC_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup flc * @defgroup flc_registers FLC_Registers * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. - * @details Flash Memory Control. + * @details Flash Memory Control. */ /** @@ -106,20 +106,20 @@ /** * @ingroup flc_registers * @defgroup FLC_Register_Offsets Register Offsets - * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. + * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. * @{ */ - #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0000 */ - #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0004 */ - #define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0008 */ - #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0024 */ - #define MXC_R_FLC_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC Base Address: 0x0028 */ - #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ - #define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ - #define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: 0x0080 */ - #define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: 0x0088 */ - #define MXC_R_FLC_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: 0x0090 */ - #define MXC_R_FLC_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: 0x0098 */ +#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0000 */ +#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0004 */ +#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0008 */ +#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0024 */ +#define MXC_R_FLC_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC Base Address: 0x0028 */ +#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ +#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ +#define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: 0x0080 */ +#define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: 0x0088 */ +#define MXC_R_FLC_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: 0x0090 */ +#define MXC_R_FLC_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: 0x0098 */ /**@} end of group flc_registers */ /** @@ -128,8 +128,8 @@ * @brief Flash Write Address. * @{ */ - #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ - #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ +#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ +#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ /**@} end of group FLC_ADDR_Register */ @@ -140,8 +140,8 @@ * MHz clock for Flash controller. * @{ */ - #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ - #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ +#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ /**@} end of group FLC_CLKDIV_Register */ @@ -151,36 +151,36 @@ * @brief Flash Control Register. * @{ */ - #define MXC_F_FLC_CTRL_WR_POS 0 /**< CTRL_WR Position */ - #define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */ +#define MXC_F_FLC_CTRL_WR_POS 0 /**< CTRL_WR Position */ +#define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */ - #define MXC_F_FLC_CTRL_ME_POS 1 /**< CTRL_ME Position */ - #define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */ +#define MXC_F_FLC_CTRL_ME_POS 1 /**< CTRL_ME Position */ +#define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */ - #define MXC_F_FLC_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ - #define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ +#define MXC_F_FLC_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ +#define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ - #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ - #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ - #define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ - #define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ - #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ - #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ - #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ - #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ +#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ +#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ +#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ +#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ +#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ - #define MXC_F_FLC_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ - #define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ +#define MXC_F_FLC_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ +#define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ - #define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ - #define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ +#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ +#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ - #define MXC_F_FLC_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ - #define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ - #define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ - #define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ - #define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ - #define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ +#define MXC_F_FLC_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ +#define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ +#define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ +#define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ +#define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ +#define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ /**@} end of group FLC_CTRL_Register */ @@ -190,17 +190,17 @@ * @brief Flash Interrupt Register. * @{ */ - #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ - #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ +#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ +#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ - #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ - #define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ +#define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ +#define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ - #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ - #define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ +#define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ +#define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ - #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ - #define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ +#define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ +#define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ /**@} end of group FLC_INTR_Register */ @@ -210,11 +210,11 @@ * @brief ECC Data Register. * @{ */ - #define MXC_F_FLC_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ - #define MXC_F_FLC_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ +#define MXC_F_FLC_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ +#define MXC_F_FLC_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ - #define MXC_F_FLC_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ - #define MXC_F_FLC_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ +#define MXC_F_FLC_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ +#define MXC_F_FLC_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ /**@} end of group FLC_ECCDATA_Register */ @@ -224,8 +224,8 @@ * @brief Flash Write Data. * @{ */ - #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ - #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ +#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ /**@} end of group FLC_DATA_Register */ @@ -239,8 +239,8 @@ * and user information block. Readback of this register is always zero. * @{ */ - #define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ - #define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ +#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ +#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ /**@} end of group FLC_ACTRL_Register */ @@ -250,8 +250,8 @@ * @brief WELR0 * @{ */ - #define MXC_F_FLC_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */ - #define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */ +#define MXC_F_FLC_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */ +#define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */ /**@} end of group FLC_WELR0_Register */ @@ -261,8 +261,8 @@ * @brief WELR1 * @{ */ - #define MXC_F_FLC_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */ - #define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */ +#define MXC_F_FLC_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */ +#define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */ /**@} end of group FLC_WELR1_Register */ @@ -272,8 +272,8 @@ * @brief RLR0 * @{ */ - #define MXC_F_FLC_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */ - #define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */ +#define MXC_F_FLC_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */ +#define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */ /**@} end of group FLC_RLR0_Register */ @@ -283,8 +283,8 @@ * @brief RLR1 * @{ */ - #define MXC_F_FLC_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */ - #define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */ +#define MXC_F_FLC_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */ +#define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */ /**@} end of group FLC_RLR1_Register */ @@ -292,4 +292,4 @@ } #endif -#endif /* _FLC_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcfr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcfr_regs.h deleted file mode 100644 index 259fd21..0000000 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcfr_regs.h +++ /dev/null @@ -1,189 +0,0 @@ -/** - * @file gcfr_regs.h - * @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module. - */ - -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - * - * - *************************************************************************** */ - -#ifndef _GCFR_REGS_H_ -#define _GCFR_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup gcfr - * @defgroup gcfr_registers GCFR_Registers - * @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module. - * @details Global Control Function Register. - */ - -/** - * @ingroup gcfr_registers - * Structure type to access the GCFR Registers. - */ -typedef struct { - __IO uint32_t reg0; /**< \b 0x00: GCFR REG0 Register */ - __IO uint32_t reg1; /**< \b 0x04: GCFR REG1 Register */ - __IO uint32_t reg2; /**< \b 0x08: GCFR REG2 Register */ - __IO uint32_t reg3; /**< \b 0x0C: GCFR REG3 Register */ -} mxc_gcfr_regs_t; - -/* Register offsets for module GCFR */ -/** - * @ingroup gcfr_registers - * @defgroup GCFR_Register_Offsets Register Offsets - * @brief GCFR Peripheral Register Offsets from the GCFR Base Peripheral Address. - * @{ - */ - #define MXC_R_GCFR_REG0 ((uint32_t)0x00000000UL) /**< Offset from GCFR Base Address: 0x0000 */ - #define MXC_R_GCFR_REG1 ((uint32_t)0x00000004UL) /**< Offset from GCFR Base Address: 0x0004 */ - #define MXC_R_GCFR_REG2 ((uint32_t)0x00000008UL) /**< Offset from GCFR Base Address: 0x0008 */ - #define MXC_R_GCFR_REG3 ((uint32_t)0x0000000CUL) /**< Offset from GCFR Base Address: 0x000C */ -/**@} end of group gcfr_registers */ - -/** - * @ingroup gcfr_registers - * @defgroup GCFR_REG0 GCFR_REG0 - * @brief Register 0. - * @{ - */ - #define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS 0 /**< REG0_CNNX16_0_PWR_EN Position */ - #define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS)) /**< REG0_CNNX16_0_PWR_EN Mask */ - - #define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS 1 /**< REG0_CNNX16_1_PWR_EN Position */ - #define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS)) /**< REG0_CNNX16_1_PWR_EN Mask */ - - #define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS 2 /**< REG0_CNNX16_2_PWR_EN Position */ - #define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS)) /**< REG0_CNNX16_2_PWR_EN Mask */ - - #define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS 3 /**< REG0_CNNX16_3_PWR_EN Position */ - #define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS)) /**< REG0_CNNX16_3_PWR_EN Mask */ - -/**@} end of group GCFR_REG0_Register */ - -/** - * @ingroup gcfr_registers - * @defgroup GCFR_REG1 GCFR_REG1 - * @brief Register 1. - * @{ - */ - #define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS 0 /**< REG1_CNNX16_0_RAM_EN Position */ - #define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS)) /**< REG1_CNNX16_0_RAM_EN Mask */ - - #define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS 1 /**< REG1_CNNX16_1_RAM_EN Position */ - #define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS)) /**< REG1_CNNX16_1_RAM_EN Mask */ - - #define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS 2 /**< REG1_CNNX16_2_RAM_EN Position */ - #define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS)) /**< REG1_CNNX16_2_RAM_EN Mask */ - - #define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS 3 /**< REG1_CNNX16_3_RAM_EN Position */ - #define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS)) /**< REG1_CNNX16_3_RAM_EN Mask */ - -/**@} end of group GCFR_REG1_Register */ - -/** - * @ingroup gcfr_registers - * @defgroup GCFR_REG2 GCFR_REG2 - * @brief Register 2. - * @{ - */ - #define MXC_F_GCFR_REG2_CNNX16_0_ISO_POS 0 /**< REG2_CNNX16_0_ISO Position */ - #define MXC_F_GCFR_REG2_CNNX16_0_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_0_ISO_POS)) /**< REG2_CNNX16_0_ISO Mask */ - - #define MXC_F_GCFR_REG2_CNNX16_1_ISO_POS 1 /**< REG2_CNNX16_1_ISO Position */ - #define MXC_F_GCFR_REG2_CNNX16_1_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_1_ISO_POS)) /**< REG2_CNNX16_1_ISO Mask */ - - #define MXC_F_GCFR_REG2_CNNX16_2_ISO_POS 2 /**< REG2_CNNX16_2_ISO Position */ - #define MXC_F_GCFR_REG2_CNNX16_2_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_2_ISO_POS)) /**< REG2_CNNX16_2_ISO Mask */ - - #define MXC_F_GCFR_REG2_CNNX16_3_ISO_POS 3 /**< REG2_CNNX16_3_ISO Position */ - #define MXC_F_GCFR_REG2_CNNX16_3_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_3_ISO_POS)) /**< REG2_CNNX16_3_ISO Mask */ - -/**@} end of group GCFR_REG2_Register */ - -/** - * @ingroup gcfr_registers - * @defgroup GCFR_REG3 GCFR_REG3 - * @brief Register 3. - * @{ - */ - #define MXC_F_GCFR_REG3_CNNX16_0_RST_POS 0 /**< REG3_CNNX16_0_RST Position */ - #define MXC_F_GCFR_REG3_CNNX16_0_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_0_RST_POS)) /**< REG3_CNNX16_0_RST Mask */ - - #define MXC_F_GCFR_REG3_CNNX16_1_RST_POS 1 /**< REG3_CNNX16_1_RST Position */ - #define MXC_F_GCFR_REG3_CNNX16_1_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_1_RST_POS)) /**< REG3_CNNX16_1_RST Mask */ - - #define MXC_F_GCFR_REG3_CNNX16_2_RST_POS 2 /**< REG3_CNNX16_2_RST Position */ - #define MXC_F_GCFR_REG3_CNNX16_2_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_2_RST_POS)) /**< REG3_CNNX16_2_RST Mask */ - - #define MXC_F_GCFR_REG3_CNNX16_3_RST_POS 3 /**< REG3_CNNX16_3_RST Position */ - #define MXC_F_GCFR_REG3_CNNX16_3_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_3_RST_POS)) /**< REG3_CNNX16_3_RST Mask */ - -/**@} end of group GCFR_REG3_Register */ - -#ifdef __cplusplus -} -#endif - -#endif /* _GCFR_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h index 72b8f0d..ebf4198 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h @@ -1,10 +1,11 @@ /** * @file gcr_regs.h * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _GCR_REGS_H_ -#define _GCR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup gcr * @defgroup gcr_registers GCR_Registers * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. - * @details Global Control Registers. + * @details Global Control Registers. */ /** @@ -111,27 +111,27 @@ /** * @ingroup gcr_registers * @defgroup GCR_Register_Offsets Register Offsets - * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. + * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. * @{ */ - #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: 0x0000 */ - #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: 0x0004 */ - #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: 0x0008 */ - #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: 0x000C */ - #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: 0x0018 */ - #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ - #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ - #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ - #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ - #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ - #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ - #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ - #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ - #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ - #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: 0x0064 */ - #define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: 0x0068 */ - #define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */ - #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */ +#define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: 0x0000 */ +#define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: 0x0004 */ +#define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: 0x0008 */ +#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: 0x000C */ +#define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: 0x0018 */ +#define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ +#define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ +#define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ +#define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ +#define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ +#define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ +#define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ +#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ +#define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ +#define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: 0x0064 */ +#define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: 0x0068 */ +#define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */ +#define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */ /**@} end of group gcr_registers */ /** @@ -140,30 +140,30 @@ * @brief System Control. * @{ */ - #define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1 /**< SYSCTRL_SBUSARB Position */ - #define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */ - #define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */ - #define MXC_S_GCR_SYSCTRL_SBUSARB_FIX (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_FIX Setting */ - #define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */ - #define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */ +#define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1 /**< SYSCTRL_SBUSARB Position */ +#define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */ +#define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */ +#define MXC_S_GCR_SYSCTRL_SBUSARB_FIX (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_FIX Setting */ +#define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */ +#define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */ - #define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5 /**< SYSCTRL_FPU_DIS Position */ - #define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */ +#define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5 /**< SYSCTRL_FPU_DIS Position */ +#define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */ - #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */ - #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */ +#define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */ +#define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */ - #define MXC_F_GCR_SYSCTRL_ROMDONE_POS 12 /**< SYSCTRL_ROMDONE Position */ - #define MXC_F_GCR_SYSCTRL_ROMDONE ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS)) /**< SYSCTRL_ROMDONE Mask */ +#define MXC_F_GCR_SYSCTRL_ROMDONE_POS 12 /**< SYSCTRL_ROMDONE Position */ +#define MXC_F_GCR_SYSCTRL_ROMDONE ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS)) /**< SYSCTRL_ROMDONE Mask */ - #define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ - #define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ +#define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ +#define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ - #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14 /**< SYSCTRL_SWD_DIS Position */ - #define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */ +#define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14 /**< SYSCTRL_SWD_DIS Position */ +#define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */ - #define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ - #define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ +#define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ +#define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ /**@} end of group GCR_SYSCTRL_Register */ @@ -173,65 +173,65 @@ * @brief Reset. * @{ */ - #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ - #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ +#define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ +#define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ - #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ - #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ +#define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ +#define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ - #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ - #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ +#define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ +#define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ - #define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ - #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ +#define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ +#define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ - #define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ - #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ +#define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ +#define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ - #define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ - #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ +#define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ +#define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ - #define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ - #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ +#define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ +#define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ - #define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ - #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ +#define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ +#define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ - #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ - #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ +#define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ +#define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ - #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ - #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ +#define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ +#define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ - #define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ - #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ +#define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ +#define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ - #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ - #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ +#define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ +#define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ - #define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */ - #define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */ +#define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */ +#define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */ - #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ - #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ +#define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ +#define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ - #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ - #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ +#define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ +#define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ - #define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ - #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ +#define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ +#define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ - #define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ - #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ +#define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ +#define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ - #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ - #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ +#define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ +#define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ - #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ - #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ +#define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ +#define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ - #define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ - #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ +#define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ +#define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ /**@} end of group GCR_RST0_Register */ @@ -241,86 +241,86 @@ * @brief Clock Control. * @{ */ - #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ - #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ - #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ - #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ - #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */ - #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */ - #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ - #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ - #define MXC_F_GCR_CLKCTRL_IPO_DIV_POS 14 /**< CLKCTRL_IPO_DIV Position */ - #define MXC_F_GCR_CLKCTRL_IPO_DIV ((uint32_t)(0x3UL << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)) /**< CLKCTRL_IPO_DIV Mask */ - #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_IPO_DIV_DIV1 Value */ - #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV1 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV1 Setting */ - #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_IPO_DIV_DIV2 Value */ - #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV2 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV2 Setting */ - #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_IPO_DIV_DIV4 Value */ - #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV4 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV4 Setting */ - #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_IPO_DIV_DIV8 Value */ - #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV8 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV8 Setting */ +#define MXC_F_GCR_CLKCTRL_IPO_DIV_POS 14 /**< CLKCTRL_IPO_DIV Position */ +#define MXC_F_GCR_CLKCTRL_IPO_DIV ((uint32_t)(0x3UL << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)) /**< CLKCTRL_IPO_DIV Mask */ +#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_IPO_DIV_DIV1 Value */ +#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV1 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV1 Setting */ +#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_IPO_DIV_DIV2 Value */ +#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV2 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV2 Setting */ +#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_IPO_DIV_DIV4 Value */ +#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV4 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV4 Setting */ +#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_IPO_DIV_DIV8 Value */ +#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV8 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV8 Setting */ - #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ - #define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ +#define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ +#define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ - #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ - #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ +#define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ +#define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ - #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ - #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ +#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ +#define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ - #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ - #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ +#define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ +#define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ - #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ - #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ +#define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ +#define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ - #define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 /**< CLKCTRL_ERFO_RDY Position */ - #define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */ +#define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 /**< CLKCTRL_ERFO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */ - #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ - #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ +#define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ - #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ - #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ +#define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ - #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ - #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ +#define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ - #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ - #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ +#define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ - #define MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS 31 /**< CLKCTRL_EXTCLK_RDY Position */ - #define MXC_F_GCR_CLKCTRL_EXTCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS)) /**< CLKCTRL_EXTCLK_RDY Mask */ +#define MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS 31 /**< CLKCTRL_EXTCLK_RDY Position */ +#define MXC_F_GCR_CLKCTRL_EXTCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS)) /**< CLKCTRL_EXTCLK_RDY Mask */ /**@} end of group GCR_CLKCTRL_Register */ @@ -330,41 +330,41 @@ * @brief Power Management. * @{ */ - #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ - #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ - #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ - #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ - #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ - #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ - #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ - #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ +#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ +#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ +#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ +#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ +#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ +#define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ +#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ +#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ - #define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ - #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ +#define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ +#define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ - #define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ - #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ +#define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ +#define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ - #define MXC_F_GCR_PM_LPTMR0_WE_POS 6 /**< PM_LPTMR0_WE Position */ - #define MXC_F_GCR_PM_LPTMR0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR0_WE_POS)) /**< PM_LPTMR0_WE Mask */ +#define MXC_F_GCR_PM_LPTMR0_WE_POS 6 /**< PM_LPTMR0_WE Position */ +#define MXC_F_GCR_PM_LPTMR0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR0_WE_POS)) /**< PM_LPTMR0_WE Mask */ - #define MXC_F_GCR_PM_LPTMR1_WE_POS 7 /**< PM_LPTMR1_WE Position */ - #define MXC_F_GCR_PM_LPTMR1_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR1_WE_POS)) /**< PM_LPTMR1_WE Mask */ +#define MXC_F_GCR_PM_LPTMR1_WE_POS 7 /**< PM_LPTMR1_WE Position */ +#define MXC_F_GCR_PM_LPTMR1_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR1_WE_POS)) /**< PM_LPTMR1_WE Mask */ - #define MXC_F_GCR_PM_LPUART0_WE_POS 8 /**< PM_LPUART0_WE Position */ - #define MXC_F_GCR_PM_LPUART0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPUART0_WE_POS)) /**< PM_LPUART0_WE Mask */ +#define MXC_F_GCR_PM_LPUART0_WE_POS 8 /**< PM_LPUART0_WE Position */ +#define MXC_F_GCR_PM_LPUART0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPUART0_WE_POS)) /**< PM_LPUART0_WE Mask */ - #define MXC_F_GCR_PM_ERFO_PD_POS 14 /**< PM_ERFO_PD Position */ - #define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */ +#define MXC_F_GCR_PM_ERFO_PD_POS 12 /**< PM_ERFO_PD Position */ +#define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */ - #define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ - #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ +#define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ +#define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ - #define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ - #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ +#define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ +#define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ - #define MXC_F_GCR_PM_ERFO_BP_POS 20 /**< PM_ERFO_BP Position */ - #define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */ +#define MXC_F_GCR_PM_ERFO_BP_POS 20 /**< PM_ERFO_BP Position */ +#define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */ /**@} end of group GCR_PM_Register */ @@ -374,22 +374,22 @@ * @brief Peripheral Clock Divider. * @{ */ - #define MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS 0 /**< PCLKDIV_AON_CLKDIV Position */ - #define MXC_F_GCR_PCLKDIV_AON_CLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)) /**< PCLKDIV_AON_CLKDIV Mask */ - #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AON_CLKDIV_DIV4 Value */ - #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV4 Setting */ - #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AON_CLKDIV_DIV8 Value */ - #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV8 Setting */ - #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AON_CLKDIV_DIV16 Value */ - #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV16 Setting */ - #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AON_CLKDIV_DIV32 Value */ - #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV32 Setting */ +#define MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS 0 /**< PCLKDIV_AON_CLKDIV Position */ +#define MXC_F_GCR_PCLKDIV_AON_CLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)) /**< PCLKDIV_AON_CLKDIV Mask */ +#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AON_CLKDIV_DIV4 Value */ +#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV4 Setting */ +#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AON_CLKDIV_DIV8 Value */ +#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV8 Setting */ +#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AON_CLKDIV_DIV16 Value */ +#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV16 Setting */ +#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AON_CLKDIV_DIV32 Value */ +#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV32 Setting */ - #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS 14 /**< PCLKDIV_DIV_CLK_OUT_CTRL Position */ - #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS)) /**< PCLKDIV_DIV_CLK_OUT_CTRL Mask */ +#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS 14 /**< PCLKDIV_DIV_CLK_OUT_CTRL Position */ +#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS)) /**< PCLKDIV_DIV_CLK_OUT_CTRL Mask */ - #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS 16 /**< PCLKDIV_DIV_CLK_OUT_EN Position */ - #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS)) /**< PCLKDIV_DIV_CLK_OUT_EN Mask */ +#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS 16 /**< PCLKDIV_DIV_CLK_OUT_EN Position */ +#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS)) /**< PCLKDIV_DIV_CLK_OUT_EN Mask */ /**@} end of group GCR_PCLKDIV_Register */ @@ -399,47 +399,47 @@ * @brief Peripheral Clock Disable. * @{ */ - #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ - #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ +#define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ +#define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ - #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ - #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ +#define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ +#define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ - #define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ - #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ +#define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ +#define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ - #define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */ - #define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */ +#define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */ +#define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */ - #define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ - #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ +#define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ +#define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ - #define MXC_F_GCR_PCLKDIS0_SPI2_POS 8 /**< PCLKDIS0_SPI2 Position */ - #define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */ +#define MXC_F_GCR_PCLKDIS0_SPI2_POS 8 /**< PCLKDIS0_SPI2 Position */ +#define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */ - #define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ - #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ +#define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ +#define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ - #define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ - #define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ +#define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ +#define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ - #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ - #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ +#define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ +#define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ - #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ - #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ +#define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ - #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ - #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ +#define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ - #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ - #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ +#define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ - #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ - #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ +#define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ - #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ - #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ +#define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ +#define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ /**@} end of group GCR_PCLKDIS0_Register */ @@ -449,29 +449,29 @@ * @brief Memory Clock Control Register. * @{ */ - #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ - #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ +#define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ +#define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ - #define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS 4 /**< MEMCTRL_RAMWS_EN Position */ - #define MXC_F_GCR_MEMCTRL_RAMWS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS)) /**< MEMCTRL_RAMWS_EN Mask */ +#define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS 4 /**< MEMCTRL_RAMWS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAMWS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS)) /**< MEMCTRL_RAMWS_EN Mask */ - #define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 8 /**< MEMCTRL_RAM0LS_EN Position */ - #define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */ +#define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 8 /**< MEMCTRL_RAM0LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */ - #define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 9 /**< MEMCTRL_RAM1LS_EN Position */ - #define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */ +#define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 9 /**< MEMCTRL_RAM1LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */ - #define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 10 /**< MEMCTRL_RAM2LS_EN Position */ - #define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */ +#define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 10 /**< MEMCTRL_RAM2LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */ - #define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 11 /**< MEMCTRL_RAM3LS_EN Position */ - #define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */ +#define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 11 /**< MEMCTRL_RAM3LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */ - #define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS 12 /**< MEMCTRL_ICC0LS_EN Position */ - #define MXC_F_GCR_MEMCTRL_ICC0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS)) /**< MEMCTRL_ICC0LS_EN Mask */ +#define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS 12 /**< MEMCTRL_ICC0LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_ICC0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS)) /**< MEMCTRL_ICC0LS_EN Mask */ - #define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS 13 /**< MEMCTRL_ROMLS_EN Position */ - #define MXC_F_GCR_MEMCTRL_ROMLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS)) /**< MEMCTRL_ROMLS_EN Mask */ +#define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS 13 /**< MEMCTRL_ROMLS_EN Position */ +#define MXC_F_GCR_MEMCTRL_ROMLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS)) /**< MEMCTRL_ROMLS_EN Mask */ /**@} end of group GCR_MEMCTRL_Register */ @@ -481,14 +481,14 @@ * @brief Memory Zeroize Control. * @{ */ - #define MXC_F_GCR_MEMZ_RAM_POS 0 /**< MEMZ_RAM Position */ - #define MXC_F_GCR_MEMZ_RAM ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM_POS)) /**< MEMZ_RAM Mask */ +#define MXC_F_GCR_MEMZ_RAM_POS 0 /**< MEMZ_RAM Position */ +#define MXC_F_GCR_MEMZ_RAM ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM_POS)) /**< MEMZ_RAM Mask */ - #define MXC_F_GCR_MEMZ_RAMCB_POS 1 /**< MEMZ_RAMCB Position */ - #define MXC_F_GCR_MEMZ_RAMCB ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAMCB_POS)) /**< MEMZ_RAMCB Mask */ +#define MXC_F_GCR_MEMZ_RAMCB_POS 1 /**< MEMZ_RAMCB Position */ +#define MXC_F_GCR_MEMZ_RAMCB ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAMCB_POS)) /**< MEMZ_RAMCB Mask */ - #define MXC_F_GCR_MEMZ_ICC0_POS 2 /**< MEMZ_ICC0 Position */ - #define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */ +#define MXC_F_GCR_MEMZ_ICC0_POS 2 /**< MEMZ_ICC0 Position */ +#define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */ /**@} end of group GCR_MEMZ_Register */ @@ -498,8 +498,8 @@ * @brief System Status Register. * @{ */ - #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ - #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ +#define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ +#define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ /**@} end of group GCR_SYSST_Register */ @@ -509,26 +509,26 @@ * @brief Reset 1. * @{ */ - #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ - #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ +#define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ +#define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ - #define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ - #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ +#define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ +#define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ - #define MXC_F_GCR_RST1_CRC_POS 9 /**< RST1_CRC Position */ - #define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */ +#define MXC_F_GCR_RST1_CRC_POS 9 /**< RST1_CRC Position */ +#define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */ - #define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ - #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ +#define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ +#define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ - #define MXC_F_GCR_RST1_AC_POS 14 /**< RST1_AC Position */ - #define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */ +#define MXC_F_GCR_RST1_AC_POS 14 /**< RST1_AC Position */ +#define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */ - #define MXC_F_GCR_RST1_I2C2_POS 17 /**< RST1_I2C2 Position */ - #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ +#define MXC_F_GCR_RST1_I2C2_POS 17 /**< RST1_I2C2 Position */ +#define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ - #define MXC_F_GCR_RST1_I2S_POS 23 /**< RST1_I2S Position */ - #define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ +#define MXC_F_GCR_RST1_I2S_POS 23 /**< RST1_I2S Position */ +#define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ /**@} end of group GCR_RST1_Register */ @@ -538,32 +538,32 @@ * @brief Peripheral Clock Disable. * @{ */ - #define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ - #define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ +#define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ +#define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ - #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ - #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ +#define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ +#define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ - #define MXC_F_GCR_PCLKDIS1_WWDT0_POS 4 /**< PCLKDIS1_WWDT0 Position */ - #define MXC_F_GCR_PCLKDIS1_WWDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT0_POS)) /**< PCLKDIS1_WWDT0 Mask */ +#define MXC_F_GCR_PCLKDIS1_WWDT0_POS 4 /**< PCLKDIS1_WWDT0 Position */ +#define MXC_F_GCR_PCLKDIS1_WWDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT0_POS)) /**< PCLKDIS1_WWDT0 Mask */ - #define MXC_F_GCR_PCLKDIS1_WWDT1_POS 5 /**< PCLKDIS1_WWDT1 Position */ - #define MXC_F_GCR_PCLKDIS1_WWDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT1_POS)) /**< PCLKDIS1_WWDT1 Mask */ +#define MXC_F_GCR_PCLKDIS1_WWDT1_POS 5 /**< PCLKDIS1_WWDT1 Position */ +#define MXC_F_GCR_PCLKDIS1_WWDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT1_POS)) /**< PCLKDIS1_WWDT1 Mask */ - #define MXC_F_GCR_PCLKDIS1_ICC0_POS 11 /**< PCLKDIS1_ICC0 Position */ - #define MXC_F_GCR_PCLKDIS1_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICC0_POS)) /**< PCLKDIS1_ICC0 Mask */ +#define MXC_F_GCR_PCLKDIS1_ICC0_POS 11 /**< PCLKDIS1_ICC0 Position */ +#define MXC_F_GCR_PCLKDIS1_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICC0_POS)) /**< PCLKDIS1_ICC0 Mask */ - #define MXC_F_GCR_PCLKDIS1_CRC_POS 14 /**< PCLKDIS1_CRC Position */ - #define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */ +#define MXC_F_GCR_PCLKDIS1_CRC_POS 14 /**< PCLKDIS1_CRC Position */ +#define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */ - #define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ - #define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ +#define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ +#define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ - #define MXC_F_GCR_PCLKDIS1_I2C2_POS 21 /**< PCLKDIS1_I2C2 Position */ - #define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ +#define MXC_F_GCR_PCLKDIS1_I2C2_POS 21 /**< PCLKDIS1_I2C2 Position */ +#define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ - #define MXC_F_GCR_PCLKDIS1_I2S_POS 23 /**< PCLKDIS1_I2S Position */ - #define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */ +#define MXC_F_GCR_PCLKDIS1_I2S_POS 23 /**< PCLKDIS1_I2S Position */ +#define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */ /**@} end of group GCR_PCLKDIS1_Register */ @@ -573,14 +573,14 @@ * @brief Event Enable Register. * @{ */ - #define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ - #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ +#define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ +#define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ - #define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ - #define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ +#define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ +#define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ - #define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ - #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ +#define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ +#define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ /**@} end of group GCR_EVENTEN_Register */ @@ -590,8 +590,8 @@ * @brief Revision Register. * @{ */ - #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ - #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ +#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ +#define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ /**@} end of group GCR_REVISION_Register */ @@ -601,8 +601,8 @@ * @brief System Status Interrupt Enable Register. * @{ */ - #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ - #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ +#define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ +#define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ /**@} end of group GCR_SYSIE_Register */ @@ -612,14 +612,14 @@ * @brief ECC Error Register * @{ */ - #define MXC_F_GCR_ECCERR_RAM_POS 0 /**< ECCERR_RAM Position */ - #define MXC_F_GCR_ECCERR_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS)) /**< ECCERR_RAM Mask */ +#define MXC_F_GCR_ECCERR_RAM_POS 0 /**< ECCERR_RAM Position */ +#define MXC_F_GCR_ECCERR_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS)) /**< ECCERR_RAM Mask */ - #define MXC_F_GCR_ECCERR_ICC0_POS 1 /**< ECCERR_ICC0 Position */ - #define MXC_F_GCR_ECCERR_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC0_POS)) /**< ECCERR_ICC0 Mask */ +#define MXC_F_GCR_ECCERR_ICC0_POS 1 /**< ECCERR_ICC0 Position */ +#define MXC_F_GCR_ECCERR_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC0_POS)) /**< ECCERR_ICC0 Mask */ - #define MXC_F_GCR_ECCERR_FLASH_POS 2 /**< ECCERR_FLASH Position */ - #define MXC_F_GCR_ECCERR_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH_POS)) /**< ECCERR_FLASH Mask */ +#define MXC_F_GCR_ECCERR_FLASH_POS 2 /**< ECCERR_FLASH Position */ +#define MXC_F_GCR_ECCERR_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH_POS)) /**< ECCERR_FLASH Mask */ /**@} end of group GCR_ECCERR_Register */ @@ -629,14 +629,14 @@ * @brief ECC Not Double Error Detect Register * @{ */ - #define MXC_F_GCR_ECCCED_RAM_POS 0 /**< ECCCED_RAM Position */ - #define MXC_F_GCR_ECCCED_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS)) /**< ECCCED_RAM Mask */ +#define MXC_F_GCR_ECCCED_RAM_POS 0 /**< ECCCED_RAM Position */ +#define MXC_F_GCR_ECCCED_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS)) /**< ECCCED_RAM Mask */ - #define MXC_F_GCR_ECCCED_ICC0_POS 1 /**< ECCCED_ICC0 Position */ - #define MXC_F_GCR_ECCCED_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC0_POS)) /**< ECCCED_ICC0 Mask */ +#define MXC_F_GCR_ECCCED_ICC0_POS 1 /**< ECCCED_ICC0 Position */ +#define MXC_F_GCR_ECCCED_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC0_POS)) /**< ECCCED_ICC0 Mask */ - #define MXC_F_GCR_ECCCED_FLASH_POS 2 /**< ECCCED_FLASH Position */ - #define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */ +#define MXC_F_GCR_ECCCED_FLASH_POS 2 /**< ECCCED_FLASH Position */ +#define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */ /**@} end of group GCR_ECCCED_Register */ @@ -646,14 +646,14 @@ * @brief ECC IRQ Enable Register * @{ */ - #define MXC_F_GCR_ECCIE_RAM_POS 0 /**< ECCIE_RAM Position */ - #define MXC_F_GCR_ECCIE_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS)) /**< ECCIE_RAM Mask */ +#define MXC_F_GCR_ECCIE_RAM_POS 0 /**< ECCIE_RAM Position */ +#define MXC_F_GCR_ECCIE_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS)) /**< ECCIE_RAM Mask */ - #define MXC_F_GCR_ECCIE_ICC0_POS 1 /**< ECCIE_ICC0 Position */ - #define MXC_F_GCR_ECCIE_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICC0_POS)) /**< ECCIE_ICC0 Mask */ +#define MXC_F_GCR_ECCIE_ICC0_POS 1 /**< ECCIE_ICC0 Position */ +#define MXC_F_GCR_ECCIE_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICC0_POS)) /**< ECCIE_ICC0 Mask */ - #define MXC_F_GCR_ECCIE_FLASH_POS 2 /**< ECCIE_FLASH Position */ - #define MXC_F_GCR_ECCIE_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH_POS)) /**< ECCIE_FLASH Mask */ +#define MXC_F_GCR_ECCIE_FLASH_POS 2 /**< ECCIE_FLASH Position */ +#define MXC_F_GCR_ECCIE_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH_POS)) /**< ECCIE_FLASH Mask */ /**@} end of group GCR_ECCIE_Register */ @@ -663,23 +663,23 @@ * @brief ECC Error Address Register * @{ */ - #define MXC_F_GCR_ECCADDR_DATARAMADDR_POS 0 /**< ECCADDR_DATARAMADDR Position */ - #define MXC_F_GCR_ECCADDR_DATARAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DATARAMADDR_POS)) /**< ECCADDR_DATARAMADDR Mask */ +#define MXC_F_GCR_ECCADDR_DATARAMADDR_POS 0 /**< ECCADDR_DATARAMADDR Position */ +#define MXC_F_GCR_ECCADDR_DATARAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DATARAMADDR_POS)) /**< ECCADDR_DATARAMADDR Mask */ - #define MXC_F_GCR_ECCADDR_DATARAMBANK_POS 14 /**< ECCADDR_DATARAMBANK Position */ - #define MXC_F_GCR_ECCADDR_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMBANK_POS)) /**< ECCADDR_DATARAMBANK Mask */ +#define MXC_F_GCR_ECCADDR_DATARAMBANK_POS 14 /**< ECCADDR_DATARAMBANK Position */ +#define MXC_F_GCR_ECCADDR_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMBANK_POS)) /**< ECCADDR_DATARAMBANK Mask */ - #define MXC_F_GCR_ECCADDR_DATARAMERR_POS 15 /**< ECCADDR_DATARAMERR Position */ - #define MXC_F_GCR_ECCADDR_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMERR_POS)) /**< ECCADDR_DATARAMERR Mask */ +#define MXC_F_GCR_ECCADDR_DATARAMERR_POS 15 /**< ECCADDR_DATARAMERR Position */ +#define MXC_F_GCR_ECCADDR_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMERR_POS)) /**< ECCADDR_DATARAMERR Mask */ - #define MXC_F_GCR_ECCADDR_TAGRAMADDR_POS 16 /**< ECCADDR_TAGRAMADDR Position */ - #define MXC_F_GCR_ECCADDR_TAGRAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TAGRAMADDR_POS)) /**< ECCADDR_TAGRAMADDR Mask */ +#define MXC_F_GCR_ECCADDR_TAGRAMADDR_POS 16 /**< ECCADDR_TAGRAMADDR Position */ +#define MXC_F_GCR_ECCADDR_TAGRAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TAGRAMADDR_POS)) /**< ECCADDR_TAGRAMADDR Mask */ - #define MXC_F_GCR_ECCADDR_TAGRAMBANK_POS 30 /**< ECCADDR_TAGRAMBANK Position */ - #define MXC_F_GCR_ECCADDR_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMBANK_POS)) /**< ECCADDR_TAGRAMBANK Mask */ +#define MXC_F_GCR_ECCADDR_TAGRAMBANK_POS 30 /**< ECCADDR_TAGRAMBANK Position */ +#define MXC_F_GCR_ECCADDR_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMBANK_POS)) /**< ECCADDR_TAGRAMBANK Mask */ - #define MXC_F_GCR_ECCADDR_TAGRAMERR_POS 31 /**< ECCADDR_TAGRAMERR Position */ - #define MXC_F_GCR_ECCADDR_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMERR_POS)) /**< ECCADDR_TAGRAMERR Mask */ +#define MXC_F_GCR_ECCADDR_TAGRAMERR_POS 31 /**< ECCADDR_TAGRAMERR Position */ +#define MXC_F_GCR_ECCADDR_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMERR_POS)) /**< ECCADDR_TAGRAMERR Mask */ /**@} end of group GCR_ECCADDR_Register */ @@ -687,4 +687,4 @@ } #endif -#endif /* _GCR_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h index 09714d5..04e6300 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h @@ -1,10 +1,11 @@ /** * @file gpio_regs.h * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _GPIO_REGS_H_ -#define _GPIO_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GPIO_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GPIO_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup gpio * @defgroup gpio_registers GPIO_Registers * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. - * @details Individual I/O for each GPIO + * @details Individual I/O for each GPIO */ /** @@ -127,44 +127,44 @@ /** * @ingroup gpio_registers * @defgroup GPIO_Register_Offsets Register Offsets - * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. + * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. * @{ */ - #define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ - #define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ - #define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ - #define MXC_R_GPIO_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ - #define MXC_R_GPIO_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ - #define MXC_R_GPIO_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ - #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ - #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ - #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ - #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ - #define MXC_R_GPIO_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ - #define MXC_R_GPIO_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ - #define MXC_R_GPIO_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ - #define MXC_R_GPIO_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ - #define MXC_R_GPIO_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ - #define MXC_R_GPIO_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ - #define MXC_R_GPIO_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ - #define MXC_R_GPIO_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ - #define MXC_R_GPIO_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ - #define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ - #define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ - #define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ - #define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ - #define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ - #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ - #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ - #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ - #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ - #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ - #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ - #define MXC_R_GPIO_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ - #define MXC_R_GPIO_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ - #define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ - #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ - #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ +#define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ +#define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ +#define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ +#define MXC_R_GPIO_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ +#define MXC_R_GPIO_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ +#define MXC_R_GPIO_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ +#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ +#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ +#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ +#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ +#define MXC_R_GPIO_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ +#define MXC_R_GPIO_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ +#define MXC_R_GPIO_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ +#define MXC_R_GPIO_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ +#define MXC_R_GPIO_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ +#define MXC_R_GPIO_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ +#define MXC_R_GPIO_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ +#define MXC_R_GPIO_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ +#define MXC_R_GPIO_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ +#define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ +#define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ +#define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ +#define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ +#define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ +#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ +#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ +#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ +#define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ +#define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ +#define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ +#define MXC_R_GPIO_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ +#define MXC_R_GPIO_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ +#define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ +#define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ +#define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ /**@} end of group gpio_registers */ /** @@ -174,12 +174,12 @@ * GPIO pin on the associated port. * @{ */ - #define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ - #define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ - #define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ - #define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ - #define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ - #define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ +#define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ +#define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ +#define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ +#define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ +#define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ +#define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ /**@} end of group GPIO_EN0_Register */ @@ -191,8 +191,8 @@ * other bits in that register. * @{ */ - #define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ - #define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ +#define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ +#define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ /**@} end of group GPIO_EN0_SET_Register */ @@ -204,8 +204,8 @@ * affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ - #define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ +#define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ +#define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ /**@} end of group GPIO_EN0_CLR_Register */ @@ -216,12 +216,12 @@ * GPIO pin in the associated port. * @{ */ - #define MXC_F_GPIO_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ - #define MXC_F_GPIO_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ - #define MXC_V_GPIO_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ - #define MXC_S_GPIO_OUTEN_EN_DIS (MXC_V_GPIO_OUTEN_EN_DIS << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ - #define MXC_V_GPIO_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ - #define MXC_S_GPIO_OUTEN_EN_EN (MXC_V_GPIO_OUTEN_EN_EN << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ +#define MXC_F_GPIO_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ +#define MXC_F_GPIO_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ +#define MXC_V_GPIO_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ +#define MXC_S_GPIO_OUTEN_EN_DIS (MXC_V_GPIO_OUTEN_EN_DIS << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ +#define MXC_V_GPIO_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ +#define MXC_S_GPIO_OUTEN_EN_EN (MXC_V_GPIO_OUTEN_EN_EN << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ /**@} end of group GPIO_OUTEN_Register */ @@ -233,8 +233,8 @@ * without affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ - #define MXC_F_GPIO_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ +#define MXC_F_GPIO_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ +#define MXC_F_GPIO_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ /**@} end of group GPIO_OUTEN_SET_Register */ @@ -246,8 +246,8 @@ * without affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ - #define MXC_F_GPIO_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ +#define MXC_F_GPIO_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ +#define MXC_F_GPIO_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ /**@} end of group GPIO_OUTEN_CLR_Register */ @@ -259,12 +259,12 @@ * GPIO_OUT_SET and GPIO_OUT_CLR registers. * @{ */ - #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ - #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ - #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ - #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ - #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ - #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ +#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ +#define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ +#define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ +#define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ +#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ +#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ /**@} end of group GPIO_OUT_Register */ @@ -276,12 +276,12 @@ * register. * @{ */ - #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ - #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ - #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ - #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ - #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ - #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ +#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ +#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ +#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ +#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ +#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ +#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ /**@} end of group GPIO_OUT_SET_Register */ @@ -293,8 +293,8 @@ * that register. * @{ */ - #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ - #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ +#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ +#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ /**@} end of group GPIO_OUT_CLR_Register */ @@ -305,8 +305,8 @@ * GPIO pins on this port. * @{ */ - #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ - #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ +#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ +#define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ /**@} end of group GPIO_IN_Register */ @@ -317,12 +317,12 @@ * mode setting for the associated GPIO pin on this port. * @{ */ - #define MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ - #define MXC_F_GPIO_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ - #define MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ - #define MXC_S_GPIO_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ - #define MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ - #define MXC_S_GPIO_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ +#define MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ +#define MXC_F_GPIO_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ +#define MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ +#define MXC_S_GPIO_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ +#define MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ +#define MXC_S_GPIO_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ /**@} end of group GPIO_INTMODE_Register */ @@ -333,12 +333,12 @@ * interrupt polarity setting for one GPIO pin in the associated port. * @{ */ - #define MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ - #define MXC_F_GPIO_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ - #define MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ - #define MXC_S_GPIO_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ - #define MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ - #define MXC_S_GPIO_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ +#define MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ +#define MXC_F_GPIO_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ +#define MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ +#define MXC_S_GPIO_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ +#define MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ +#define MXC_S_GPIO_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ /**@} end of group GPIO_INTPOL_Register */ @@ -349,12 +349,12 @@ * interrupt enable for the associated pin on the GPIO port. * @{ */ - #define MXC_F_GPIO_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */ - #define MXC_F_GPIO_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ - #define MXC_V_GPIO_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ - #define MXC_S_GPIO_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ - #define MXC_V_GPIO_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ - #define MXC_S_GPIO_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ +#define MXC_F_GPIO_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */ +#define MXC_F_GPIO_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ +#define MXC_V_GPIO_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ +#define MXC_S_GPIO_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ +#define MXC_V_GPIO_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ +#define MXC_S_GPIO_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ /**@} end of group GPIO_INTEN_Register */ @@ -366,12 +366,12 @@ * in that register. * @{ */ - #define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ - #define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ - #define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ - #define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ - #define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ - #define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ +#define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ +#define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ +#define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ +#define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ +#define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ +#define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ /**@} end of group GPIO_INTEN_SET_Register */ @@ -383,12 +383,12 @@ * other bits in that register. * @{ */ - #define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ - #define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ - #define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ - #define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ - #define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ - #define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ +#define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ +#define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ +#define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ +#define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ +#define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ +#define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ /**@} end of group GPIO_INTEN_CLR_Register */ @@ -399,12 +399,12 @@ * interrupt status for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ - #define MXC_F_GPIO_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ - #define MXC_V_GPIO_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ - #define MXC_S_GPIO_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ - #define MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ - #define MXC_S_GPIO_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ +#define MXC_F_GPIO_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ +#define MXC_F_GPIO_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ +#define MXC_V_GPIO_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ +#define MXC_S_GPIO_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ +#define MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ +#define MXC_S_GPIO_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ /**@} end of group GPIO_INTFL_Register */ @@ -416,8 +416,8 @@ * in that register. * @{ */ - #define MXC_F_GPIO_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ - #define MXC_F_GPIO_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ +#define MXC_F_GPIO_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ +#define MXC_F_GPIO_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ /**@} end of group GPIO_INTFL_CLR_Register */ @@ -428,12 +428,12 @@ * enable for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ - #define MXC_F_GPIO_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ - #define MXC_V_GPIO_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */ - #define MXC_S_GPIO_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ - #define MXC_V_GPIO_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ - #define MXC_S_GPIO_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ +#define MXC_F_GPIO_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ +#define MXC_F_GPIO_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ +#define MXC_V_GPIO_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */ +#define MXC_S_GPIO_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ +#define MXC_V_GPIO_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ +#define MXC_S_GPIO_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ /**@} end of group GPIO_WKEN_Register */ @@ -445,8 +445,8 @@ * that register. * @{ */ - #define MXC_F_GPIO_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ - #define MXC_F_GPIO_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ +#define MXC_F_GPIO_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ +#define MXC_F_GPIO_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ /**@} end of group GPIO_WKEN_SET_Register */ @@ -458,8 +458,8 @@ * bits in that register. * @{ */ - #define MXC_F_GPIO_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ - #define MXC_F_GPIO_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ +#define MXC_F_GPIO_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ +#define MXC_F_GPIO_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ /**@} end of group GPIO_WKEN_CLR_Register */ @@ -470,12 +470,12 @@ * edge mode for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ - #define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ - #define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ - #define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ - #define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ - #define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ +#define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ +#define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ +#define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ +#define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ +#define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ +#define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ /**@} end of group GPIO_DUALEDGE_Register */ @@ -486,14 +486,14 @@ * the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ - #define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ - #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ - #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ - #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ - #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ - #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ - #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ +#define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ +#define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ +#define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ +#define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ +#define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ +#define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ +#define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ +#define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ /**@} end of group GPIO_PADCTRL0_Register */ @@ -504,14 +504,14 @@ * the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ - #define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ - #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ - #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ - #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ - #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ - #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ - #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ +#define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ +#define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ +#define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ +#define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ +#define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ +#define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ +#define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ +#define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ /**@} end of group GPIO_PADCTRL1_Register */ @@ -522,12 +522,12 @@ * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ - #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ - #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ - #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ - #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ - #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ +#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ +#define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ +#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ +#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ +#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ +#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ /**@} end of group GPIO_EN1_Register */ @@ -539,8 +539,8 @@ * bits in that register. * @{ */ - #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ - #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ +#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ +#define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ /**@} end of group GPIO_EN1_SET_Register */ @@ -552,8 +552,8 @@ * bits in that register. * @{ */ - #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ - #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ +#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ +#define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ /**@} end of group GPIO_EN1_CLR_Register */ @@ -564,12 +564,12 @@ * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ - #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ - #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ - #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ - #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ - #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ +#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ +#define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ +#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ +#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ +#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ +#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ /**@} end of group GPIO_EN2_Register */ @@ -581,8 +581,8 @@ * bits in that register. * @{ */ - #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ - #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ +#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ +#define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ /**@} end of group GPIO_EN2_SET_Register */ @@ -594,8 +594,8 @@ * affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ - #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ +#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ +#define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ /**@} end of group GPIO_EN2_CLR_Register */ @@ -605,8 +605,8 @@ * @brief GPIO Input Hysteresis Enable. * @{ */ - #define MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ - #define MXC_F_GPIO_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ +#define MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ +#define MXC_F_GPIO_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ /**@} end of group GPIO_HYSEN_Register */ @@ -616,12 +616,12 @@ * @brief GPIO Slew Rate Enable Register. * @{ */ - #define MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ - #define MXC_F_GPIO_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ - #define MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ - #define MXC_S_GPIO_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ - #define MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ - #define MXC_S_GPIO_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ +#define MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ +#define MXC_F_GPIO_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ +#define MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ +#define MXC_S_GPIO_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ +#define MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ +#define MXC_S_GPIO_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ /**@} end of group GPIO_SRSEL_Register */ @@ -633,12 +633,12 @@ * sink/source current of GPIO pins in each mode. * @{ */ - #define MXC_F_GPIO_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ - #define MXC_F_GPIO_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ - #define MXC_V_GPIO_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ - #define MXC_S_GPIO_DS0_GPIO_DS0_LD (MXC_V_GPIO_DS0_GPIO_DS0_LD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ - #define MXC_V_GPIO_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ - #define MXC_S_GPIO_DS0_GPIO_DS0_HD (MXC_V_GPIO_DS0_GPIO_DS0_HD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ +#define MXC_F_GPIO_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ +#define MXC_F_GPIO_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ +#define MXC_V_GPIO_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ +#define MXC_S_GPIO_DS0_GPIO_DS0_LD (MXC_V_GPIO_DS0_GPIO_DS0_LD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ +#define MXC_V_GPIO_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ +#define MXC_S_GPIO_DS0_GPIO_DS0_HD (MXC_V_GPIO_DS0_GPIO_DS0_HD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ /**@} end of group GPIO_DS0_Register */ @@ -650,8 +650,8 @@ * sink/source current of GPIO pins in each mode. * @{ */ - #define MXC_F_GPIO_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ - #define MXC_F_GPIO_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ +#define MXC_F_GPIO_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ +#define MXC_F_GPIO_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ /**@} end of group GPIO_DS1_Register */ @@ -661,8 +661,8 @@ * @brief GPIO Pull Select Mode. * @{ */ - #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ - #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ +#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ +#define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ /**@} end of group GPIO_PS_Register */ @@ -670,4 +670,4 @@ } #endif -#endif /* _GPIO_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GPIO_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h index 4d67eec..ee812dd 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h @@ -1,10 +1,11 @@ /** * @file i2c_regs.h * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _I2C_REGS_H_ -#define _I2C_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2C_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2C_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup i2c * @defgroup i2c_registers I2C_Registers * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. - * @details Inter-Integrated Circuit. + * @details Inter-Integrated Circuit. */ /** @@ -108,28 +108,28 @@ /** * @ingroup i2c_registers * @defgroup I2C_Register_Offsets Register Offsets - * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. + * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. * @{ */ - #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ - #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ - #define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ - #define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ - #define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ - #define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ - #define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ - #define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ - #define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ - #define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ - #define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ - #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ - #define MXC_R_I2C_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ - #define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ - #define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ - #define MXC_R_I2C_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ - #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ - #define MXC_R_I2C_SLAVE ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: 0x0044 */ - #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ +#define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ +#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ +#define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ +#define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ +#define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ +#define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ +#define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ +#define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ +#define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ +#define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ +#define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ +#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ +#define MXC_R_I2C_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ +#define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ +#define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ +#define MXC_R_I2C_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ +#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ +#define MXC_R_I2C_SLAVE ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: 0x0044 */ +#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ /**@} end of group i2c_registers */ /** @@ -138,47 +138,47 @@ * @brief Control Register0. * @{ */ - #define MXC_F_I2C_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_I2C_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_I2C_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_I2C_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_I2C_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ - #define MXC_F_I2C_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ +#define MXC_F_I2C_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ +#define MXC_F_I2C_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ - #define MXC_F_I2C_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ - #define MXC_F_I2C_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ +#define MXC_F_I2C_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ +#define MXC_F_I2C_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ - #define MXC_F_I2C_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ - #define MXC_F_I2C_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ +#define MXC_F_I2C_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ +#define MXC_F_I2C_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ - #define MXC_F_I2C_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ - #define MXC_F_I2C_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ +#define MXC_F_I2C_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ +#define MXC_F_I2C_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ - #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ - #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ +#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ +#define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ - #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ - #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ +#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ +#define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ - #define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ - #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ +#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ +#define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ - #define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ - #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ +#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ +#define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ - #define MXC_F_I2C_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ - #define MXC_F_I2C_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ +#define MXC_F_I2C_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ +#define MXC_F_I2C_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ - #define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ - #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ +#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ +#define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ - #define MXC_F_I2C_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ - #define MXC_F_I2C_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ +#define MXC_F_I2C_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ +#define MXC_F_I2C_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ - #define MXC_F_I2C_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ - #define MXC_F_I2C_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ +#define MXC_F_I2C_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ +#define MXC_F_I2C_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ - #define MXC_F_I2C_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ - #define MXC_F_I2C_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ +#define MXC_F_I2C_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ +#define MXC_F_I2C_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ /**@} end of group I2C_CTRL_Register */ @@ -188,23 +188,23 @@ * @brief Status Register. * @{ */ - #define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ - #define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ +#define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ - #define MXC_F_I2C_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ - #define MXC_F_I2C_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ +#define MXC_F_I2C_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ +#define MXC_F_I2C_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ - #define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ - #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ +#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ +#define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ - #define MXC_F_I2C_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ - #define MXC_F_I2C_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ +#define MXC_F_I2C_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ +#define MXC_F_I2C_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ - #define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ - #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ +#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ +#define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ - #define MXC_F_I2C_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ - #define MXC_F_I2C_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ +#define MXC_F_I2C_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ +#define MXC_F_I2C_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ /**@} end of group I2C_STATUS_Register */ @@ -214,62 +214,62 @@ * @brief Interrupt Status Register. * @{ */ - #define MXC_F_I2C_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ - #define MXC_F_I2C_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ +#define MXC_F_I2C_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ +#define MXC_F_I2C_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ - #define MXC_F_I2C_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ - #define MXC_F_I2C_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ +#define MXC_F_I2C_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ +#define MXC_F_I2C_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ - #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ - #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ +#define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ - #define MXC_F_I2C_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ - #define MXC_F_I2C_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ +#define MXC_F_I2C_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ +#define MXC_F_I2C_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ - #define MXC_F_I2C_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ - #define MXC_F_I2C_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ +#define MXC_F_I2C_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ +#define MXC_F_I2C_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ - #define MXC_F_I2C_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ - #define MXC_F_I2C_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ +#define MXC_F_I2C_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ +#define MXC_F_I2C_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ - #define MXC_F_I2C_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ - #define MXC_F_I2C_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ +#define MXC_F_I2C_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ +#define MXC_F_I2C_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ - #define MXC_F_I2C_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ - #define MXC_F_I2C_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ +#define MXC_F_I2C_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ +#define MXC_F_I2C_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ - #define MXC_F_I2C_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ - #define MXC_F_I2C_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ +#define MXC_F_I2C_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ +#define MXC_F_I2C_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ - #define MXC_F_I2C_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ - #define MXC_F_I2C_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ +#define MXC_F_I2C_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ +#define MXC_F_I2C_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ - #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ - #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ +#define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ - #define MXC_F_I2C_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ - #define MXC_F_I2C_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ +#define MXC_F_I2C_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ +#define MXC_F_I2C_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ - #define MXC_F_I2C_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ - #define MXC_F_I2C_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ +#define MXC_F_I2C_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ +#define MXC_F_I2C_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ - #define MXC_F_I2C_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ - #define MXC_F_I2C_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ +#define MXC_F_I2C_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ +#define MXC_F_I2C_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ - #define MXC_F_I2C_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ - #define MXC_F_I2C_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ +#define MXC_F_I2C_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ +#define MXC_F_I2C_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ - #define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ - #define MXC_F_I2C_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ +#define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ +#define MXC_F_I2C_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ - #define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ - #define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ +#define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ +#define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ - #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ - #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ +#define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ - #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ - #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ +#define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ /**@} end of group I2C_INTFL0_Register */ @@ -279,62 +279,62 @@ * @brief Interrupt Enable Register. * @{ */ - #define MXC_F_I2C_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ - #define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ +#define MXC_F_I2C_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ +#define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ - #define MXC_F_I2C_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ - #define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ +#define MXC_F_I2C_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ +#define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ - #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ - #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ +#define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ - #define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ - #define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ +#define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ +#define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ - #define MXC_F_I2C_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ - #define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ +#define MXC_F_I2C_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ +#define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ - #define MXC_F_I2C_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ - #define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ +#define MXC_F_I2C_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ +#define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ - #define MXC_F_I2C_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ - #define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ +#define MXC_F_I2C_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ +#define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ - #define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ - #define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ +#define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ +#define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ - #define MXC_F_I2C_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ - #define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ +#define MXC_F_I2C_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ +#define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ - #define MXC_F_I2C_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ - #define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ +#define MXC_F_I2C_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ +#define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ - #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ - #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ +#define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ - #define MXC_F_I2C_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ - #define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ +#define MXC_F_I2C_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ +#define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ - #define MXC_F_I2C_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ - #define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ +#define MXC_F_I2C_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ +#define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ - #define MXC_F_I2C_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ - #define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ +#define MXC_F_I2C_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ +#define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ - #define MXC_F_I2C_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ - #define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ +#define MXC_F_I2C_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ +#define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ - #define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ - #define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ +#define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ +#define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ - #define MXC_F_I2C_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ - #define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ +#define MXC_F_I2C_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ +#define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ - #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ - #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ +#define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ - #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ - #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ +#define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ /**@} end of group I2C_INTEN0_Register */ @@ -344,14 +344,14 @@ * @brief Interrupt Status Register 1. * @{ */ - #define MXC_F_I2C_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ - #define MXC_F_I2C_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ +#define MXC_F_I2C_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ +#define MXC_F_I2C_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ - #define MXC_F_I2C_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ - #define MXC_F_I2C_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ +#define MXC_F_I2C_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ +#define MXC_F_I2C_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ - #define MXC_F_I2C_INTFL1_START_POS 2 /**< INTFL1_START Position */ - #define MXC_F_I2C_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS)) /**< INTFL1_START Mask */ +#define MXC_F_I2C_INTFL1_START_POS 2 /**< INTFL1_START Position */ +#define MXC_F_I2C_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS)) /**< INTFL1_START Mask */ /**@} end of group I2C_INTFL1_Register */ @@ -361,14 +361,14 @@ * @brief Interrupt Staus Register 1. * @{ */ - #define MXC_F_I2C_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ - #define MXC_F_I2C_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ +#define MXC_F_I2C_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ +#define MXC_F_I2C_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ - #define MXC_F_I2C_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ - #define MXC_F_I2C_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ +#define MXC_F_I2C_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ +#define MXC_F_I2C_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ - #define MXC_F_I2C_INTEN1_START_POS 2 /**< INTEN1_START Position */ - #define MXC_F_I2C_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS)) /**< INTEN1_START Mask */ +#define MXC_F_I2C_INTEN1_START_POS 2 /**< INTEN1_START Position */ +#define MXC_F_I2C_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS)) /**< INTEN1_START Mask */ /**@} end of group I2C_INTEN1_Register */ @@ -378,11 +378,11 @@ * @brief FIFO Configuration Register. * @{ */ - #define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ - #define MXC_F_I2C_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ +#define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ +#define MXC_F_I2C_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ - #define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ - #define MXC_F_I2C_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ +#define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ +#define MXC_F_I2C_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ /**@} end of group I2C_FIFOLEN_Register */ @@ -392,14 +392,14 @@ * @brief Receive Control Register 0. * @{ */ - #define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ - #define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ +#define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ +#define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ - #define MXC_F_I2C_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ - #define MXC_F_I2C_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ +#define MXC_F_I2C_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ +#define MXC_F_I2C_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ - #define MXC_F_I2C_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ - #define MXC_F_I2C_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ +#define MXC_F_I2C_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ /**@} end of group I2C_RXCTRL0_Register */ @@ -409,11 +409,11 @@ * @brief Receive Control Register 1. * @{ */ - #define MXC_F_I2C_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ - #define MXC_F_I2C_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ +#define MXC_F_I2C_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ +#define MXC_F_I2C_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ - #define MXC_F_I2C_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ - #define MXC_F_I2C_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ +#define MXC_F_I2C_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ +#define MXC_F_I2C_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ /**@} end of group I2C_RXCTRL1_Register */ @@ -423,29 +423,29 @@ * @brief Transmit Control Register 0. * @{ */ - #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ - #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ +#define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ +#define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ - #define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ - #define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ +#define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ +#define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ - #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ - #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ +#define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ +#define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ - #define MXC_F_I2C_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ - #define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ +#define MXC_F_I2C_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ +#define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ - #define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8 /**< TXCTRL0_THD_VAL Position */ - #define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS)) /**< TXCTRL0_THD_VAL Mask */ +#define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8 /**< TXCTRL0_THD_VAL Position */ +#define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS)) /**< TXCTRL0_THD_VAL Mask */ /**@} end of group I2C_TXCTRL0_Register */ @@ -455,11 +455,11 @@ * @brief Transmit Control Register 1. * @{ */ - #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ - #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ +#define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ +#define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ - #define MXC_F_I2C_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ - #define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ +#define MXC_F_I2C_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ +#define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ /**@} end of group I2C_TXCTRL1_Register */ @@ -469,8 +469,8 @@ * @brief Data Register. * @{ */ - #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ - #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ +#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ /**@} end of group I2C_FIFO_Register */ @@ -480,17 +480,17 @@ * @brief Master Control Register. * @{ */ - #define MXC_F_I2C_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ - #define MXC_F_I2C_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ +#define MXC_F_I2C_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ +#define MXC_F_I2C_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ - #define MXC_F_I2C_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ - #define MXC_F_I2C_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ +#define MXC_F_I2C_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ +#define MXC_F_I2C_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ - #define MXC_F_I2C_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ - #define MXC_F_I2C_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ +#define MXC_F_I2C_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ +#define MXC_F_I2C_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ - #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ - #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ +#define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ +#define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ /**@} end of group I2C_MSTCTRL_Register */ @@ -500,8 +500,8 @@ * @brief Clock Low Register. * @{ */ - #define MXC_F_I2C_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ - #define MXC_F_I2C_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ +#define MXC_F_I2C_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ +#define MXC_F_I2C_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ /**@} end of group I2C_CLKLO_Register */ @@ -511,8 +511,8 @@ * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ - #define MXC_F_I2C_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ +#define MXC_F_I2C_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ +#define MXC_F_I2C_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ /**@} end of group I2C_CLKHI_Register */ @@ -522,11 +522,11 @@ * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ - #define MXC_F_I2C_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ +#define MXC_F_I2C_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ +#define MXC_F_I2C_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ - #define MXC_F_I2C_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ - #define MXC_F_I2C_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ +#define MXC_F_I2C_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ +#define MXC_F_I2C_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ /**@} end of group I2C_HSCLK_Register */ @@ -536,8 +536,8 @@ * @brief Timeout Register * @{ */ - #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ - #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ +#define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ +#define MXC_F_I2C_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ /**@} end of group I2C_TIMEOUT_Register */ @@ -547,11 +547,17 @@ * @brief Slave Address Register. * @{ */ - #define MXC_F_I2C_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ - #define MXC_F_I2C_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ +#define MXC_F_I2C_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ +#define MXC_F_I2C_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ - #define MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ - #define MXC_F_I2C_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ +#define MXC_F_I2C_SLAVE_DIS_POS 10 /**< SLAVE_DIS Position */ +#define MXC_F_I2C_SLAVE_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_DIS_POS)) /**< SLAVE_DIS Mask */ + +#define MXC_F_I2C_SLAVE_IDX_POS 11 /**< SLAVE_IDX Position */ +#define MXC_F_I2C_SLAVE_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_IDX_POS)) /**< SLAVE_IDX Mask */ + +#define MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ +#define MXC_F_I2C_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ /**@} end of group I2C_SLAVE_Register */ @@ -561,11 +567,11 @@ * @brief DMA Register. * @{ */ - #define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ - #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ +#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ +#define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ - #define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ - #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ +#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ +#define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ /**@} end of group I2C_DMA_Register */ @@ -573,4 +579,4 @@ } #endif -#endif /* _I2C_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2C_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h index 065ae5b..472a96f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h @@ -1,10 +1,11 @@ /** * @file i2s_regs.h * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _I2S_REGS_H_ -#define _I2S_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2S_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2S_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup i2s * @defgroup i2s_registers I2S_Registers * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. - * @details Inter-IC Sound Interface. + * @details Inter-IC Sound Interface. */ /** @@ -100,16 +100,16 @@ /** * @ingroup i2s_registers * @defgroup I2S_Register_Offsets Register Offsets - * @brief I2S Peripheral Register Offsets from the I2S Base Peripheral Address. + * @brief I2S Peripheral Register Offsets from the I2S Base Peripheral Address. * @{ */ - #define MXC_R_I2S_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S Base Address: 0x0000 */ - #define MXC_R_I2S_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S Base Address: 0x0010 */ - #define MXC_R_I2S_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S Base Address: 0x0030 */ - #define MXC_R_I2S_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S Base Address: 0x0040 */ - #define MXC_R_I2S_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S Base Address: 0x0050 */ - #define MXC_R_I2S_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S Base Address: 0x0054 */ - #define MXC_R_I2S_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S Base Address: 0x0058 */ +#define MXC_R_I2S_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S Base Address: 0x0000 */ +#define MXC_R_I2S_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S Base Address: 0x0010 */ +#define MXC_R_I2S_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S Base Address: 0x0030 */ +#define MXC_R_I2S_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S Base Address: 0x0040 */ +#define MXC_R_I2S_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S Base Address: 0x0050 */ +#define MXC_R_I2S_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S Base Address: 0x0054 */ +#define MXC_R_I2S_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S Base Address: 0x0058 */ /**@} end of group i2s_registers */ /** @@ -118,47 +118,47 @@ * @brief Global mode channel. * @{ */ - #define MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */ - #define MXC_F_I2S_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */ +#define MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */ +#define MXC_F_I2S_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */ - #define MXC_F_I2S_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */ - #define MXC_F_I2S_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */ +#define MXC_F_I2S_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */ +#define MXC_F_I2S_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */ - #define MXC_F_I2S_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */ - #define MXC_F_I2S_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */ +#define MXC_F_I2S_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */ +#define MXC_F_I2S_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */ - #define MXC_F_I2S_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */ - #define MXC_F_I2S_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */ +#define MXC_F_I2S_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */ +#define MXC_F_I2S_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */ - #define MXC_F_I2S_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */ - #define MXC_F_I2S_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */ +#define MXC_F_I2S_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */ +#define MXC_F_I2S_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */ - #define MXC_F_I2S_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */ - #define MXC_F_I2S_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */ +#define MXC_F_I2S_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */ +#define MXC_F_I2S_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */ - #define MXC_F_I2S_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */ - #define MXC_F_I2S_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */ +#define MXC_F_I2S_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */ +#define MXC_F_I2S_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */ - #define MXC_F_I2S_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */ - #define MXC_F_I2S_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */ +#define MXC_F_I2S_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */ +#define MXC_F_I2S_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */ - #define MXC_F_I2S_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */ - #define MXC_F_I2S_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */ +#define MXC_F_I2S_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */ +#define MXC_F_I2S_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */ - #define MXC_F_I2S_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */ - #define MXC_F_I2S_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */ +#define MXC_F_I2S_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */ +#define MXC_F_I2S_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */ - #define MXC_F_I2S_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */ - #define MXC_F_I2S_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */ +#define MXC_F_I2S_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */ +#define MXC_F_I2S_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */ - #define MXC_F_I2S_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */ - #define MXC_F_I2S_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */ +#define MXC_F_I2S_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */ +#define MXC_F_I2S_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */ - #define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 19 /**< CTRL0CH0_FIFO_LSB Position */ - #define MXC_F_I2S_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */ +#define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 20 /**< CTRL0CH0_FIFO_LSB Position */ +#define MXC_F_I2S_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */ - #define MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */ - #define MXC_F_I2S_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */ +#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */ +#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */ /**@} end of group I2S_CTRL0CH0_Register */ @@ -168,20 +168,20 @@ * @brief Local channel Setup. * @{ */ - #define MXC_F_I2S_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */ - #define MXC_F_I2S_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */ +#define MXC_F_I2S_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */ +#define MXC_F_I2S_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */ - #define MXC_F_I2S_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */ - #define MXC_F_I2S_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */ +#define MXC_F_I2S_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */ +#define MXC_F_I2S_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */ - #define MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */ - #define MXC_F_I2S_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */ +#define MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */ +#define MXC_F_I2S_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */ - #define MXC_F_I2S_CTRL1CH0_ADJST_POS 15 /**< CTRL1CH0_ADJST Position */ - #define MXC_F_I2S_CTRL1CH0_ADJST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_ADJST_POS)) /**< CTRL1CH0_ADJST Mask */ +#define MXC_F_I2S_CTRL1CH0_ADJST_POS 15 /**< CTRL1CH0_ADJST Position */ +#define MXC_F_I2S_CTRL1CH0_ADJST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_ADJST_POS)) /**< CTRL1CH0_ADJST Mask */ - #define MXC_F_I2S_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */ - #define MXC_F_I2S_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */ +#define MXC_F_I2S_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */ +#define MXC_F_I2S_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */ /**@} end of group I2S_CTRL1CH0_Register */ @@ -191,23 +191,23 @@ * @brief DMA Control. * @{ */ - #define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */ - #define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */ +#define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */ +#define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */ - #define MXC_F_I2S_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */ - #define MXC_F_I2S_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */ +#define MXC_F_I2S_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */ +#define MXC_F_I2S_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */ - #define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */ - #define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */ +#define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */ +#define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */ - #define MXC_F_I2S_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */ - #define MXC_F_I2S_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */ +#define MXC_F_I2S_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */ +#define MXC_F_I2S_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */ - #define MXC_F_I2S_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */ - #define MXC_F_I2S_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */ +#define MXC_F_I2S_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */ +#define MXC_F_I2S_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */ - #define MXC_F_I2S_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */ - #define MXC_F_I2S_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */ +#define MXC_F_I2S_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */ +#define MXC_F_I2S_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */ /**@} end of group I2S_DMACH0_Register */ @@ -217,8 +217,8 @@ * @brief I2S Fifo. * @{ */ - #define MXC_F_I2S_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */ - #define MXC_F_I2S_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */ +#define MXC_F_I2S_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */ +#define MXC_F_I2S_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */ /**@} end of group I2S_FIFOCH0_Register */ @@ -228,17 +228,17 @@ * @brief ISR Status. * @{ */ - #define MXC_F_I2S_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */ - #define MXC_F_I2S_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */ +#define MXC_F_I2S_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */ +#define MXC_F_I2S_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */ - #define MXC_F_I2S_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */ - #define MXC_F_I2S_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */ +#define MXC_F_I2S_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */ +#define MXC_F_I2S_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */ - #define MXC_F_I2S_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */ - #define MXC_F_I2S_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */ +#define MXC_F_I2S_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */ +#define MXC_F_I2S_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */ - #define MXC_F_I2S_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */ - #define MXC_F_I2S_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */ +#define MXC_F_I2S_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */ +#define MXC_F_I2S_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */ /**@} end of group I2S_INTFL_Register */ @@ -248,17 +248,17 @@ * @brief Interrupt Enable. * @{ */ - #define MXC_F_I2S_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */ - #define MXC_F_I2S_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */ +#define MXC_F_I2S_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */ +#define MXC_F_I2S_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */ - #define MXC_F_I2S_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */ - #define MXC_F_I2S_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */ +#define MXC_F_I2S_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */ +#define MXC_F_I2S_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */ - #define MXC_F_I2S_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */ - #define MXC_F_I2S_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */ +#define MXC_F_I2S_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */ +#define MXC_F_I2S_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */ - #define MXC_F_I2S_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */ - #define MXC_F_I2S_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */ +#define MXC_F_I2S_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */ +#define MXC_F_I2S_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */ /**@} end of group I2S_INTEN_Register */ @@ -268,8 +268,8 @@ * @brief Ext Control. * @{ */ - #define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */ - #define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */ +#define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */ +#define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */ /**@} end of group I2S_EXTSETUP_Register */ @@ -277,4 +277,4 @@ } #endif -#endif /* _I2S_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2S_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h index c13039d..d2051ec 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h @@ -1,10 +1,11 @@ /** * @file icc_regs.h * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _ICC_REGS_H_ -#define _ICC_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ICC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ICC_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup icc * @defgroup icc_registers ICC_Registers * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. - * @details Instruction Cache Controller Registers + * @details Instruction Cache Controller Registers */ /** @@ -95,13 +95,13 @@ /** * @ingroup icc_registers * @defgroup ICC_Register_Offsets Register Offsets - * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. + * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. * @{ */ - #define MXC_R_ICC_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ - #define MXC_R_ICC_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ - #define MXC_R_ICC_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ - #define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ +#define MXC_R_ICC_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ +#define MXC_R_ICC_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ +#define MXC_R_ICC_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ +#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ /**@} end of group icc_registers */ /** @@ -110,14 +110,14 @@ * @brief Cache ID Register. * @{ */ - #define MXC_F_ICC_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ - #define MXC_F_ICC_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ +#define MXC_F_ICC_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ +#define MXC_F_ICC_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ - #define MXC_F_ICC_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ - #define MXC_F_ICC_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ +#define MXC_F_ICC_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ +#define MXC_F_ICC_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ - #define MXC_F_ICC_INFO_ID_POS 10 /**< INFO_ID Position */ - #define MXC_F_ICC_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_ID_POS)) /**< INFO_ID Mask */ +#define MXC_F_ICC_INFO_ID_POS 10 /**< INFO_ID Position */ +#define MXC_F_ICC_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_ID_POS)) /**< INFO_ID Mask */ /**@} end of group ICC_INFO_Register */ @@ -127,11 +127,11 @@ * @brief Memory Configuration Register. * @{ */ - #define MXC_F_ICC_SZ_CCH_POS 0 /**< SZ_CCH Position */ - #define MXC_F_ICC_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_CCH_POS)) /**< SZ_CCH Mask */ +#define MXC_F_ICC_SZ_CCH_POS 0 /**< SZ_CCH Position */ +#define MXC_F_ICC_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_CCH_POS)) /**< SZ_CCH Mask */ - #define MXC_F_ICC_SZ_MEM_POS 16 /**< SZ_MEM Position */ - #define MXC_F_ICC_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_MEM_POS)) /**< SZ_MEM Mask */ +#define MXC_F_ICC_SZ_MEM_POS 16 /**< SZ_MEM Position */ +#define MXC_F_ICC_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_MEM_POS)) /**< SZ_MEM Mask */ /**@} end of group ICC_SZ_Register */ @@ -141,11 +141,11 @@ * @brief Cache Control and Status Register. * @{ */ - #define MXC_F_ICC_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_ICC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_ICC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_ICC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_ICC_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ - #define MXC_F_ICC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ +#define MXC_F_ICC_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ +#define MXC_F_ICC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ /**@} end of group ICC_CTRL_Register */ @@ -155,8 +155,8 @@ * @brief Invalidate All Registers. * @{ */ - #define MXC_F_ICC_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */ - #define MXC_F_ICC_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */ +#define MXC_F_ICC_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */ +#define MXC_F_ICC_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */ /**@} end of group ICC_INVALIDATE_Register */ @@ -164,4 +164,4 @@ } #endif -#endif /* _ICC_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ICC_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h index 502f213..e74b748 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h @@ -1,5 +1,5 @@ -/******************************************************************************* - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,48 +29,48 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * ******************************************************************************/ -#ifndef _MAX32670_REGS_H_ -#define _MAX32670_REGS_H_ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_ #ifndef TARGET_NUM -#define TARGET_NUM 32670 -#endif +#define TARGET_NUM 32670 +#endif #define MXC_NUMCORES 1 #include -#ifndef FALSE -#define FALSE (0) +#ifndef FALSE +#define FALSE (0) #endif -#ifndef TRUE -#define TRUE (1) +#ifndef TRUE +#define TRUE (1) #endif /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ -#if defined ( __GNUC__ ) +#if defined(__GNUC__) #define __weak __attribute__((weak)) -#elif defined ( __CC_ARM) - +#elif defined(__CC_ARM) + #define inline __inline #pragma anon_unions #endif typedef enum { - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, /* Device-specific interrupt sources (external to ARM core) */ /* table entry number */ @@ -78,146 +78,144 @@ /* |||| table offset address */ /* vvvv vvvvvv */ - PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ - WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ - RSV02_IRQn, /* 0x12 0x0048 18: Reserved */ - RTC_IRQn, /* 0x13 0x004C 19: RTC */ - TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ - TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ - TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ - TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ - TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */ - TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 */ - TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */ - RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ - RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ - I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ - UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ - UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ - SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */ - SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */ - SPI2_IRQn, /* 0x22 0x0088 34: SPI2 */ - RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ - RSV20_IRQn, /* 0x24 0x0090 36: Reserved */ - RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ - RSV22_IRQn, /* 0x26 0x0098 38: Magstripe DSP */ - FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */ - GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ - GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO2 */ - RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */ - RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */ - DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ - DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ - DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ - DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ - RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ - RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ - UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */ - RSV35_IRQn, /* 0x33 0x00CC 51: Contactless Link Control */ - I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ - RSV37_IRQn, /* 0x35 0x00D4 53: Smart Card 1 */ - RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */ - RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */ - RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */ - RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */ - RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */ - RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */ - RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */ - RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */ - RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */ - RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ - RSV48_IRQn, /* 0x40 0x0100 64: Reserved */ - RSV49_IRQn, /* 0x41 0x0104 65: Reserved */ - RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ - RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ - RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ - RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ - GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIOWAKE */ - RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ - RSV56_IRQn, /* 0x48 0x0120 72: Reserved */ - WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */ - RSV57_IRQn, /* 0x4A 0x0128 74: Reserved */ - RSV58_IRQn, /* 0x4B 0x012C 75: Reserved */ - RSV59_IRQn, /* 0x4C 0x0130 76: Reserved */ - RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ - I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */ - RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */ - RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ - RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ - RSV66_IRQn, /* 0x52 0x0148 82: Reserved */ - RSV67_IRQn, /* 0x53 0x014C 83: One Wire Master */ - DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */ - DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */ - DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */ - DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */ - DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */ - DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */ - DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */ - DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */ - DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */ - DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */ - DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */ - DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */ - RSV80_IRQn, /* 0x60 0x0180 96: Reserved */ - RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ - ECC_IRQn, /* 0x62 0x0188 98: Error Correction */ - RSV83_IRQn, /* 0x63 0x018C 99: Reserved */ - RSV84_IRQn, /* 0x64 0x0190 100: Reserved */ - RSV85_IRQn, /* 0x65 0x0194 101: Reserved */ - RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ - RSV87_IRQn, /* 0x67 0x019C 103: Reserved */ - UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */ - RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ - RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ - RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */ - RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ - RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */ - RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */ - RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ - RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */ - AES_IRQn, /* 0x71 0x01C4 113: AES */ - CRC_IRQn, /* 0x72 0x01C8 114: CRC */ - I2S_IRQn, /* 0x73 0x01CC 115: I2S */ + PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ + WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ + RSV02_IRQn, /* 0x12 0x0048 18: Reserved */ + RTC_IRQn, /* 0x13 0x004C 19: RTC */ + TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ + TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ + TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ + TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ + TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */ + TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 */ + TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */ + RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ + RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ + I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ + UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ + UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ + SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */ + SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */ + SPI2_IRQn, /* 0x22 0x0088 34: SPI2 */ + RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ + RSV20_IRQn, /* 0x24 0x0090 36: Reserved */ + RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ + RSV22_IRQn, /* 0x26 0x0098 38: Magstripe DSP */ + FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */ + GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ + GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO2 */ + RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */ + RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */ + DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ + DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ + DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ + DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ + RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ + RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ + UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */ + RSV35_IRQn, /* 0x33 0x00CC 51: Contactless Link Control */ + I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ + RSV37_IRQn, /* 0x35 0x00D4 53: Smart Card 1 */ + RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */ + RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */ + RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */ + RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */ + RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */ + RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */ + RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */ + RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */ + RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */ + RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ + RSV48_IRQn, /* 0x40 0x0100 64: Reserved */ + RSV49_IRQn, /* 0x41 0x0104 65: Reserved */ + RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ + RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ + RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ + RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ + GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIOWAKE */ + RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ + RSV56_IRQn, /* 0x48 0x0120 72: Reserved */ + WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */ + RSV57_IRQn, /* 0x4A 0x0128 74: Reserved */ + RSV58_IRQn, /* 0x4B 0x012C 75: Reserved */ + RSV59_IRQn, /* 0x4C 0x0130 76: Reserved */ + RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ + I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */ + RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */ + RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ + RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ + RSV66_IRQn, /* 0x52 0x0148 82: Reserved */ + RSV67_IRQn, /* 0x53 0x014C 83: One Wire Master */ + DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */ + DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */ + DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */ + DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */ + DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */ + DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */ + DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */ + DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */ + DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */ + DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */ + DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */ + DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */ + RSV80_IRQn, /* 0x60 0x0180 96: Reserved */ + RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ + ECC_IRQn, /* 0x62 0x0188 98: Error Correction */ + RSV83_IRQn, /* 0x63 0x018C 99: Reserved */ + RSV84_IRQn, /* 0x64 0x0190 100: Reserved */ + RSV85_IRQn, /* 0x65 0x0194 101: Reserved */ + RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ + RSV87_IRQn, /* 0x67 0x019C 103: Reserved */ + UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */ + RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ + RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ + RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */ + RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ + RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */ + RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */ + RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ + RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */ + AES_IRQn, /* 0x71 0x01C4 113: AES */ + CRC_IRQn, /* 0x72 0x01C8 114: CRC */ + I2S_IRQn, /* 0x73 0x01CC 115: I2S */ MXC_IRQ_EXT_COUNT, } IRQn_Type; #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) - /* ================================================================================ */ /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ -#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ -#include /*!< Cortex-M4 processor and core peripherals */ -#include "system_max32670.h" /*!< System Header */ - +#include /*!< Cortex-M4 processor and core peripherals */ +#include "system_max32670.h" /*!< System Header */ /* ================================================================================ */ /* ================== Device Specific Memory Section ================== */ /* ================================================================================ */ -#define MXC_ROM_MEM_BASE 0x00000000UL -#define MXC_ROM_MEM_SIZE 0x00020000UL -#define MXC_XIP_MEM_BASE 0x08000000UL -#define MXC_XIP_MEM_SIZE 0x08000000UL -#define MXC_FLASH0_MEM_BASE 0x10000000UL -#define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE -#define MXC_FLASH_PAGE_SIZE 0x00002000UL -#define MXC_FLASH_MEM_SIZE (0x00060000UL - MXC_FLASH_PAGE_SIZE) -#define MXC_INFO0_MEM_BASE 0x10800000UL -#define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE -#define MXC_INFO_MEM_SIZE 0x00004000UL -#define MXC_SRAM_MEM_BASE 0x20000000UL -#define MXC_SRAM_MEM_SIZE 0x00028000UL -#define MXC_XIP_DATA_MEM_BASE 0x80000000UL -#define MXC_XIP_DATA_MEM_SIZE 0x20000000UL +#define MXC_ROM_MEM_BASE 0x00000000UL +#define MXC_ROM_MEM_SIZE 0x00020000UL +#define MXC_XIP_MEM_BASE 0x08000000UL +#define MXC_XIP_MEM_SIZE 0x08000000UL +#define MXC_FLASH0_MEM_BASE 0x10000000UL +#define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE +#define MXC_FLASH_PAGE_SIZE 0x00002000UL +#define MXC_FLASH_MEM_SIZE (0x00060000UL - MXC_FLASH_PAGE_SIZE) +#define MXC_INFO0_MEM_BASE 0x10800000UL +#define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE +#define MXC_INFO_MEM_SIZE 0x00004000UL +#define MXC_SRAM_MEM_BASE 0x20000000UL +#define MXC_SRAM_MEM_SIZE 0x00028000UL +#define MXC_XIP_DATA_MEM_BASE 0x80000000UL +#define MXC_XIP_DATA_MEM_SIZE 0x20000000UL /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ @@ -229,353 +227,331 @@ /******************************************************************************/ /* Global control */ -#define MXC_BASE_GCR ((uint32_t)0x40000000UL) -#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR) +#define MXC_BASE_GCR ((uint32_t)0x40000000UL) +#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) /******************************************************************************/ /* Non-battery backed SI Registers */ -#define MXC_BASE_SIR ((uint32_t)0x40000400UL) -#define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR) +#define MXC_BASE_SIR ((uint32_t)0x40000400UL) +#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) /******************************************************************************/ /* Non-battery backed Function Control */ -#define MXC_BASE_FCR ((uint32_t)0x40000800UL) -#define MXC_FCR ((mxc_fcr_regs_t*)MXC_BASE_FCR) - -/******************************************************************************/ -/* Trim System Initalization Register */ -#define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL) -#define MXC_TRIMSIR ((mxc_trimsir_regs_t*)MXC_BASE_TRIMSIR) - -/******************************************************************************/ -/* Watchdog */ -#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) -#define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0) -#define MXC_BASE_WDT1 ((uint32_t)0x40003400UL) -#define MXC_WDT1 ((mxc_wdt_regs_t*)MXC_BASE_WDT1) - -/******************************************************************************/ -/* Real Time Clock */ -#define MXC_BASE_RTC ((uint32_t)0x40106000UL) -#define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC) - -/******************************************************************************/ -/* Power Sequencer */ -#define MXC_BASE_PWRSEQ ((uint32_t)0x40106800UL) -#define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ) - -/******************************************************************************/ -/* MISC Control */ -#define MXC_BASE_MCR ((uint32_t)0x40106C00UL) -#define MXC_MCR ((mxc_mcr_regs_t*)MXC_BASE_MCR) - - -/******************************************************************************/ -/* Error Correcting Code */ -#define MXC_BASE_ECC ((uint32_t)0x40105400UL) -#define MXC_ECC ((mxc_ecc_regs_t*)MXC_BASE_ECC) - - -/******************************************************************************/ -/* GPIO */ -#define MXC_CFG_GPIO_INSTANCES (2) -#define MXC_CFG_GPIO_PINS_PORT (32) - -#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) -#define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0) -#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL) -#define MXC_GPIO1 ((mxc_gpio_regs_t*)MXC_BASE_GPIO1) - -#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : \ - (p) == MXC_GPIO1 ? 1 : -1) - -#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : \ - (i) == 1 ? MXC_GPIO1 : 0) - -#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : \ - (i) == 1 ? GPIO1_IRQn : 0) - -/******************************************************************************/ - - - - -#define SEC(s) (((unsigned long)s) * 1000000UL) -#define MSEC(ms) (ms * 1000UL) -#define USEC(us) (us) -/* Timer */ -#define MXC_CFG_TMR_INSTANCES (6) - -#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) -#define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0) -#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) -#define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1) -#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) -#define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2) -#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL) -#define MXC_TMR3 ((mxc_tmr_regs_t*)MXC_BASE_TMR3) -#define MXC_BASE_TMR4 ((uint32_t)0x40114000UL) -#define MXC_TMR4 ((mxc_tmr_regs_t*)MXC_BASE_TMR4) -#define MXC_BASE_TMR5 ((uint32_t)0x40115000UL) -#define MXC_TMR5 ((mxc_tmr_regs_t*)MXC_BASE_TMR5) - -#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ - (i) == 1 ? TMR1_IRQn : \ - (i) == 2 ? TMR2_IRQn : \ - (i) == 3 ? TMR3_IRQn : \ - (i) == 4 ? TMR4_IRQn : \ - (i) == 5 ? TMR5_IRQn : 0) - -#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ - (i) == 1 ? MXC_BASE_TMR1 : \ - (i) == 2 ? MXC_BASE_TMR2 : \ - (i) == 3 ? MXC_BASE_TMR3 : \ - (i) == 4 ? MXC_BASE_TMR4 : \ - (i) == 5 ? MXC_BASE_TMR5 : 0) - -#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ - (i) == 1 ? MXC_TMR1 : \ - (i) == 2 ? MXC_TMR2 : \ - (i) == 3 ? MXC_TMR3 : \ - (i) == 4 ? MXC_TMR4 : \ - (i) == 5 ? MXC_TMR5 : 0) - -#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \ - (p) == MXC_TMR1 ? 1 : \ - (p) == MXC_TMR2 ? 2 : \ - (p) == MXC_TMR3 ? 3 : \ - (p) == MXC_TMR4 ? 4 : \ - (p) == MXC_TMR5 ? 5 : -1) - -/******************************************************************************/ -/* I2C */ -#define MXC_I2C_INSTANCES (3) - -#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) -#define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0) -#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) -#define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1) -#define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL) -#define MXC_I2C2 ((mxc_i2c_regs_t*)MXC_BASE_I2C2) - - -#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \ - (i) == 1 ? I2C1_IRQn : \ - (i) == 2 ? I2C2_IRQn : 0) - -#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \ - (i) == 1 ? MXC_BASE_I2C1 : \ - (i) == 2 ? MXC_BASE_I2C2 : 0) - -#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \ - (i) == 1 ? MXC_I2C1 : \ - (i) == 2 ? MXC_I2C2 : 0) - -#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \ - (p) == MXC_I2C1 ? 1 : \ - (p) == MXC_I2C2 ? 2 : -1) -#define MXC_I2C_FIFO_DEPTH (8) - - -/******************************************************************************/ -/* DMA */ -#define MXC_DMA_CHANNELS (8) -#define MXC_DMA_INSTANCES (1) - -#define MXC_BASE_DMA ((uint32_t)0x40028000UL) -#define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA) - -#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) - -/******************************************************************************/ -/* FLC */ -#define MXC_FLC_INSTANCES (1) - -#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL) -#define MXC_FLC0 ((mxc_flc_regs_t*)MXC_BASE_FLC0) - - -#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0) - -#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0) - -#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0) - -#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1) -/******************************************************************************/ -/* Instruction Cache */ - -#define MXC_BASE_ICC ((uint32_t)0x4002A000UL) -#define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC) - -/******************************************************************************/ -/* Data Cache */ -#define MXC_BASE_EMCC ((uint32_t)0x40033000UL) -#define MXC_EMCC ((mxc_emcc_regs_t*)MXC_BASE_EMCC) - -/******************************************************************************/ -/* XXX Actually reserved! */ -#define MXC_BASE_RESERVED ((uint32_t)0x40035000UL) - -/******************************************************************************/ -/* One Wire Master */ -#define MXC_BASE_OWM ((uint32_t)0x4003D000UL) -#define MXC_OWM ((mxc_owm_regs_t*)MXC_BASE_OWM) - -/******************************************************************************/ -/* UART / Serial Port Interface */ - -#define MXC_UART_INSTANCES (4) -#define MXC_UART_FIFO_DEPTH (8) - -#define MXC_BASE_UART0 ((uint32_t)0x40042000UL) -#define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0) -#define MXC_BASE_UART1 ((uint32_t)0x40043000UL) -#define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1) -#define MXC_BASE_UART2 ((uint32_t)0x40044000UL) -#define MXC_UART2 ((mxc_uart_regs_t*)MXC_BASE_UART2) -#define MXC_BASE_UART3 ((uint32_t)0x40145000UL) -#define MXC_UART3 ((mxc_uart_regs_t*)MXC_BASE_UART3) - -#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \ - (i) == 1 ? UART1_IRQn : \ - (i) == 2 ? UART2_IRQn : \ - (i) == 3 ? UART3_IRQn : 0) - -#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ - (i) == 1 ? MXC_BASE_UART1 : \ - (i) == 2 ? MXC_BASE_UART2 : \ - (i) == 3 ? MXC_BASE_UART3 : 0) - -#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ - (i) == 1 ? MXC_UART1 : \ - (i) == 2 ? MXC_UART2 : \ - (i) == 3 ? MXC_UART3 : 0) - -#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \ - (p) == MXC_UART1 ? 1 : \ - (p) == MXC_UART2 ? 2 : \ - (p) == MXC_UART3 ? 3 : -1) - -/******************************************************************************/ -/* SPI */ - -#define MXC_SPI_INSTANCES (3) -#define MXC_SPI_SS_INSTANCES (4) -#define MXC_SPI_FIFO_DEPTH (32) - -#define MXC_BASE_SPI0 ((uint32_t)0x40046000UL) -#define MXC_SPI0 ((mxc_spi_regs_t*)MXC_BASE_SPI0) -#define MXC_BASE_SPI1 ((uint32_t)0x40047000UL) -#define MXC_SPI1 ((mxc_spi_regs_t*)MXC_BASE_SPI1) -#define MXC_BASE_SPI2 ((uint32_t)0x40048000UL) -#define MXC_SPI2 ((mxc_spi_regs_t*)MXC_BASE_SPI2) - - - -#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : \ - (p) == MXC_SPI1 ? 1 : \ - (p) == MXC_SPI2 ? 2 : -1) - -#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \ - (i) == 1 ? MXC_BASE_SPI1 : \ - (i) == 2 ? MXC_BASE_SPI2 : 0) - -#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \ - (i) == 1 ? MXC_SPI1 : \ - (i) == 2 ? MXC_SPI2 : 0) - -#define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI0_IRQn : \ - (i) == 1 ? SPI1_IRQn : \ - (i) == 2 ? SPI2_IRQn : 0) - - -/******************************************************************************/ -/* TRNG */ -#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL) -#define MXC_TRNG ((mxc_trng_regs_t*)MXC_BASE_TRNG) - -/******************************************************************************/ -/* AES */ -#define MXC_BASE_AES ((uint32_t)0x40007400UL) -#define MXC_AES ((mxc_aes_regs_t*)MXC_BASE_AES) +#define MXC_BASE_FCR ((uint32_t)0x40000800UL) +#define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR) /******************************************************************************/ /* AES Keys */ -#define MXC_BASE_AESKEY ((uint32_t)0x40005000UL) -#define MXC_AESKEY ((mxc_aes_key_regs_t*)MXC_BASE_AESKEY) +#define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL) +#define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS) + +// DEPRECATED(1-10-2023): Scheduled for removal. +#define MXC_BASE_AESKEY MXC_BASE_AESKEYS +#define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY) + +/******************************************************************************/ +/* Error Correcting Code */ +/* ECC registers is a subset of TRIMSIR registers */ +#define MXC_BASE_ECC ((uint32_t)0x40105400UL) +#define MXC_ECC ((mxc_ecc_regs_t *)MXC_BASE_ECC) + +/******************************************************************************/ +/* Trim System Initalization Register */ +#define MXC_BASE_TRIMSIR ((uint32_t)0x400105400UL) +#define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR) + +/******************************************************************************/ +/* Watchdog */ +#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) +#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) +#define MXC_BASE_WDT1 ((uint32_t)0x40003400UL) +#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) + +/******************************************************************************/ +/* Real Time Clock */ +#define MXC_BASE_RTC ((uint32_t)0x40106000UL) +#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) + +/******************************************************************************/ +/* Power Sequencer */ +#define MXC_BASE_PWRSEQ ((uint32_t)0x40106800UL) +#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) + +/******************************************************************************/ +/* MISC Control */ +#define MXC_BASE_MCR ((uint32_t)0x40106C00UL) +#define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR) + +/******************************************************************************/ +/* AES */ +#define MXC_BASE_AES ((uint32_t)0x40007400UL) +#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) + +/******************************************************************************/ +/* GPIO */ +#define MXC_CFG_GPIO_INSTANCES (2) +#define MXC_CFG_GPIO_PINS_PORT (32) + +#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) +#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) +#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL) +#define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1) + +#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1) + +#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0) + +#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : 0) /******************************************************************************/ /* CRC */ -#define MXC_BASE_CRC ((uint32_t)0x4000F000UL) -#define MXC_CRC ((mxc_crc_regs_t*)MXC_BASE_CRC) +#define MXC_BASE_CRC ((uint32_t)0x4000F000UL) +#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC) /******************************************************************************/ -#define MXC_BASE_I2S ((uint32_t)0x40060000UL) -#define MXC_I2S ((mxc_i2s_regs_t*)MXC_BASE_I2S) +/* Timer */ +#define SEC(s) (((uint32_t)s) * 1000000UL) +#define MSEC(ms) (ms * 1000UL) +#define USEC(us) (us) + +#define MXC_CFG_TMR_INSTANCES (6) + +#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) +#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) +#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) +#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) +#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) +#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) +#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL) +#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) +#define MXC_BASE_TMR4 ((uint32_t)0x40114000UL) +#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) +#define MXC_BASE_TMR5 ((uint32_t)0x40115000UL) +#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) + +#define MXC_TMR_GET_IRQ(i) \ + (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + (i) == 3 ? TMR3_IRQn : \ + (i) == 4 ? TMR4_IRQn : \ + (i) == 5 ? TMR5_IRQn : \ + 0) + +#define MXC_TMR_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : \ + (i) == 3 ? MXC_BASE_TMR3 : \ + (i) == 4 ? MXC_BASE_TMR4 : \ + (i) == 5 ? MXC_BASE_TMR5 : \ + 0) + +#define MXC_TMR_GET_TMR(i) \ + ((i) == 0 ? MXC_TMR0 : \ + (i) == 1 ? MXC_TMR1 : \ + (i) == 2 ? MXC_TMR2 : \ + (i) == 3 ? MXC_TMR3 : \ + (i) == 4 ? MXC_TMR4 : \ + (i) == 5 ? MXC_TMR5 : \ + 0) + +#define MXC_TMR_GET_IDX(p) \ + ((p) == MXC_TMR0 ? 0 : \ + (p) == MXC_TMR1 ? 1 : \ + (p) == MXC_TMR2 ? 2 : \ + (p) == MXC_TMR3 ? 3 : \ + (p) == MXC_TMR4 ? 4 : \ + (p) == MXC_TMR5 ? 5 : \ + -1) /******************************************************************************/ -/* BBFC */ -#define MXC_BASE_BBFC ((uint32_t)0x40005800UL) -#define MXC_BBFC ((mxc_bbfc_regs_t*)MXC_BASE_BBFC) +/* I2C */ +#define MXC_I2C_INSTANCES (3) +#define MXC_I2C_FIFO_DEPTH (8) +#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) +#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) +#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) +#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) +#define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL) +#define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2) + +#define MXC_I2C_GET_IRQ(i) \ + (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0) + +#define MXC_I2C_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0) + +#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0) + +#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1) + +/******************************************************************************/ +/* DMA */ +#define MXC_DMA_CHANNELS (8) +#define MXC_DMA_INSTANCES (1) + +#define MXC_BASE_DMA ((uint32_t)0x40028000UL) +#define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA) + +#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) + +/******************************************************************************/ +/* FLC */ +#define MXC_FLC_INSTANCES (1) + +#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL) +#define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0) + +#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0) + +#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0) + +#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0) + +#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1) + +/******************************************************************************/ +/* Instruction Cache */ +#define MXC_BASE_ICC ((uint32_t)0x4002A000UL) +#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) + +/******************************************************************************/ +/* Data Cache */ +#define MXC_BASE_EMCC ((uint32_t)0x40033000UL) +#define MXC_EMCC ((mxc_emcc_regs_t *)MXC_BASE_EMCC) + +/******************************************************************************/ +/* XXX Actually reserved! */ +#define MXC_BASE_RESERVED ((uint32_t)0x40035000UL) + +/******************************************************************************/ +/* One Wire Master */ +#define MXC_BASE_OWM ((uint32_t)0x4003D000UL) +#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM) + +/******************************************************************************/ +/* UART / Serial Port Interface */ +#define MXC_UART_INSTANCES (4) +#define MXC_UART_FIFO_DEPTH (8) + +#define MXC_BASE_UART0 ((uint32_t)0x40042000UL) +#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) +#define MXC_BASE_UART1 ((uint32_t)0x40043000UL) +#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) +#define MXC_BASE_UART2 ((uint32_t)0x40044000UL) +#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) +#define MXC_BASE_UART3 ((uint32_t)0x40145000UL) +#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3) + +#define MXC_UART_GET_IRQ(i) \ + (IRQn_Type)((i) == 0 ? UART0_IRQn : \ + (i) == 1 ? UART1_IRQn : \ + (i) == 2 ? UART2_IRQn : \ + (i) == 3 ? UART3_IRQn : \ + 0) + +#define MXC_UART_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_UART0 : \ + (i) == 1 ? MXC_BASE_UART1 : \ + (i) == 2 ? MXC_BASE_UART2 : \ + (i) == 3 ? MXC_BASE_UART3 : \ + 0) + +#define MXC_UART_GET_UART(i) \ + ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0) + +#define MXC_UART_GET_IDX(p) \ + ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1) + +/******************************************************************************/ +/* SPI */ +#define MXC_SPI_INSTANCES (3) +#define MXC_SPI_SS_INSTANCES (4) +#define MXC_SPI_FIFO_DEPTH (32) + +#define MXC_BASE_SPI0 ((uint32_t)0x40046000UL) +#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) +#define MXC_BASE_SPI1 ((uint32_t)0x40047000UL) +#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) +#define MXC_BASE_SPI2 ((uint32_t)0x40048000UL) +#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2) + +#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : -1) + +#define MXC_SPI_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 2 ? MXC_BASE_SPI2 : 0) + +#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : 0) + +#define MXC_SPI_GET_IRQ(i) \ + (IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : (i) == 2 ? SPI2_IRQn : 0) + +/******************************************************************************/ +/* TRNG */ +#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL) +#define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG) + +/******************************************************************************/ +#define MXC_BASE_I2S ((uint32_t)0x40060000UL) +#define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S) /******************************************************************************/ /* Bit Shifting */ - -#define MXC_F_BIT_0 (1 << 0) -#define MXC_F_BIT_1 (1 << 1) -#define MXC_F_BIT_2 (1 << 2) -#define MXC_F_BIT_3 (1 << 3) -#define MXC_F_BIT_4 (1 << 4) -#define MXC_F_BIT_5 (1 << 5) -#define MXC_F_BIT_6 (1 << 6) -#define MXC_F_BIT_7 (1 << 7) -#define MXC_F_BIT_8 (1 << 8) -#define MXC_F_BIT_9 (1 << 9) -#define MXC_F_BIT_10 (1 << 10) -#define MXC_F_BIT_11 (1 << 11) -#define MXC_F_BIT_12 (1 << 12) -#define MXC_F_BIT_13 (1 << 13) -#define MXC_F_BIT_14 (1 << 14) -#define MXC_F_BIT_15 (1 << 15) -#define MXC_F_BIT_16 (1 << 16) -#define MXC_F_BIT_17 (1 << 17) -#define MXC_F_BIT_18 (1 << 18) -#define MXC_F_BIT_19 (1 << 19) -#define MXC_F_BIT_20 (1 << 20) -#define MXC_F_BIT_21 (1 << 21) -#define MXC_F_BIT_22 (1 << 22) -#define MXC_F_BIT_23 (1 << 23) -#define MXC_F_BIT_24 (1 << 24) -#define MXC_F_BIT_25 (1 << 25) -#define MXC_F_BIT_26 (1 << 26) -#define MXC_F_BIT_27 (1 << 27) -#define MXC_F_BIT_28 (1 << 28) -#define MXC_F_BIT_29 (1 << 29) -#define MXC_F_BIT_30 (1 << 30) -#define MXC_F_BIT_31 (1 << 31) +#define MXC_F_BIT_0 (1 << 0) +#define MXC_F_BIT_1 (1 << 1) +#define MXC_F_BIT_2 (1 << 2) +#define MXC_F_BIT_3 (1 << 3) +#define MXC_F_BIT_4 (1 << 4) +#define MXC_F_BIT_5 (1 << 5) +#define MXC_F_BIT_6 (1 << 6) +#define MXC_F_BIT_7 (1 << 7) +#define MXC_F_BIT_8 (1 << 8) +#define MXC_F_BIT_9 (1 << 9) +#define MXC_F_BIT_10 (1 << 10) +#define MXC_F_BIT_11 (1 << 11) +#define MXC_F_BIT_12 (1 << 12) +#define MXC_F_BIT_13 (1 << 13) +#define MXC_F_BIT_14 (1 << 14) +#define MXC_F_BIT_15 (1 << 15) +#define MXC_F_BIT_16 (1 << 16) +#define MXC_F_BIT_17 (1 << 17) +#define MXC_F_BIT_18 (1 << 18) +#define MXC_F_BIT_19 (1 << 19) +#define MXC_F_BIT_20 (1 << 20) +#define MXC_F_BIT_21 (1 << 21) +#define MXC_F_BIT_22 (1 << 22) +#define MXC_F_BIT_23 (1 << 23) +#define MXC_F_BIT_24 (1 << 24) +#define MXC_F_BIT_25 (1 << 25) +#define MXC_F_BIT_26 (1 << 26) +#define MXC_F_BIT_27 (1 << 27) +#define MXC_F_BIT_28 (1 << 28) +#define MXC_F_BIT_29 (1 << 29) +#define MXC_F_BIT_30 (1 << 30) +#define MXC_F_BIT_31 (1 << 31) /******************************************************************************/ /* Bit Banding */ +#define BITBAND(reg, bit) \ + ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ + ((bit) << 2)) -#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \ - (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) +#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) +#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) +#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) -#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) -#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) -#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) - -#define MXC_SETFIELD(reg, mask, setting) (reg = (reg & ~mask) | (setting & mask)) +#define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask))) /******************************************************************************/ /* SCB CPACR */ /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ -#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ -#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ -#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ -#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ +#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ +#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ +#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ +#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ -#endif /* _MAX32670_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h index 609b125..76d8ec0 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h @@ -1,10 +1,11 @@ /** * @file mcr_regs.h * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _MCR_REGS_H_ -#define _MCR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup mcr * @defgroup mcr_registers MCR_Registers * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. - * @details Misc Control. + * @details Miscellaneous Control Registers. */ /** @@ -85,7 +85,9 @@ typedef struct { __I uint32_t rsv_0x0; __IO uint32_t rst; /**< \b 0x04: MCR RST Register */ - __I uint32_t rsv_0x8_0x23[7]; + __I uint32_t rsv_0x8_0xf[2]; + __IO uint32_t lppioctrl; /**< \b 0x10: MCR LPPIOCTRL Register */ + __I uint32_t rsv_0x14_0x23[4]; __IO uint32_t clkdis; /**< \b 0x24: MCR CLKDIS Register */ } mxc_mcr_regs_t; @@ -93,44 +95,80 @@ /** * @ingroup mcr_registers * @defgroup MCR_Register_Offsets Register Offsets - * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. + * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. * @{ */ - #define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: 0x0004 */ - #define MXC_R_MCR_CLKDIS ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: 0x0024 */ +#define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: 0x0004 */ +#define MXC_R_MCR_LPPIOCTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: 0x0010 */ +#define MXC_R_MCR_CLKDIS ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: 0x0024 */ /**@} end of group mcr_registers */ /** * @ingroup mcr_registers * @defgroup MCR_RST MCR_RST - * @brief Reset Control Register + * @brief Reset control register 0. * @{ */ - #define MXC_F_MCR_RST_LPTMR0_POS 0 /**< RST_LPTMR0 Position */ - #define MXC_F_MCR_RST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR0_POS)) /**< RST_LPTMR0 Mask */ +#define MXC_F_MCR_RST_LPTMR0_POS 0 /**< RST_LPTMR0 Position */ +#define MXC_F_MCR_RST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR0_POS)) /**< RST_LPTMR0 Mask */ - #define MXC_F_MCR_RST_LPTMR1_POS 1 /**< RST_LPTMR1 Position */ - #define MXC_F_MCR_RST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR1_POS)) /**< RST_LPTMR1 Mask */ +#define MXC_F_MCR_RST_LPTMR1_POS 1 /**< RST_LPTMR1 Position */ +#define MXC_F_MCR_RST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR1_POS)) /**< RST_LPTMR1 Mask */ - #define MXC_F_MCR_RST_LPUART0_POS 2 /**< RST_LPUART0 Position */ - #define MXC_F_MCR_RST_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPUART0_POS)) /**< RST_LPUART0 Mask */ +#define MXC_F_MCR_RST_LPUART0_POS 2 /**< RST_LPUART0 Position */ +#define MXC_F_MCR_RST_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPUART0_POS)) /**< RST_LPUART0 Mask */ + +#define MXC_F_MCR_RST_RTC_POS 3 /**< RST_RTC Position */ +#define MXC_F_MCR_RST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RST_RTC_POS)) /**< RST_RTC Mask */ /**@} end of group MCR_RST_Register */ /** * @ingroup mcr_registers - * @defgroup MCR_CLKDIS MCR_CLKDIS - * @brief Low Power Peripheral Clock Disable. + * @defgroup MCR_LPPIOCTRL MCR_LPPIOCTRL + * @brief Low-power peripheral IO control. * @{ */ - #define MXC_F_MCR_CLKDIS_LPTMR0_POS 0 /**< CLKDIS_LPTMR0 Position */ - #define MXC_F_MCR_CLKDIS_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR0_POS)) /**< CLKDIS_LPTMR0 Mask */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS 0 /**< LPPIOCTRL_LPTMR0_I Position */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR0_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS)) /**< LPPIOCTRL_LPTMR0_I Mask */ - #define MXC_F_MCR_CLKDIS_LPTMR1_POS 1 /**< CLKDIS_LPTMR1 Position */ - #define MXC_F_MCR_CLKDIS_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR1_POS)) /**< CLKDIS_LPTMR1 Mask */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS 1 /**< LPPIOCTRL_LPTMR0_O Position */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR0_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS)) /**< LPPIOCTRL_LPTMR0_O Mask */ - #define MXC_F_MCR_CLKDIS_LPUART0_POS 2 /**< CLKDIS_LPUART0 Position */ - #define MXC_F_MCR_CLKDIS_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPUART0_POS)) /**< CLKDIS_LPUART0 Mask */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS 2 /**< LPPIOCTRL_LPTMR1_I Position */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR1_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS)) /**< LPPIOCTRL_LPTMR1_I Mask */ + +#define MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS 3 /**< LPPIOCTRL_LPTMR1_O Position */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR1_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS)) /**< LPPIOCTRL_LPTMR1_O Mask */ + +#define MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS 4 /**< LPPIOCTRL_LPUART0_RX Position */ +#define MXC_F_MCR_LPPIOCTRL_LPUART0_RX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS)) /**< LPPIOCTRL_LPUART0_RX Mask */ + +#define MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS 5 /**< LPPIOCTRL_LPUART0_TX Position */ +#define MXC_F_MCR_LPPIOCTRL_LPUART0_TX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS)) /**< LPPIOCTRL_LPUART0_TX Mask */ + +#define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS 6 /**< LPPIOCTRL_LPUART0_CTS Position */ +#define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS)) /**< LPPIOCTRL_LPUART0_CTS Mask */ + +#define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS 7 /**< LPPIOCTRL_LPUART0_RTS Position */ +#define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS)) /**< LPPIOCTRL_LPUART0_RTS Mask */ + +/**@} end of group MCR_LPPIOCTRL_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_CLKDIS MCR_CLKDIS + * @brief Peripheral clock control register. + * @{ + */ +#define MXC_F_MCR_CLKDIS_LPTMR0_POS 0 /**< CLKDIS_LPTMR0 Position */ +#define MXC_F_MCR_CLKDIS_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR0_POS)) /**< CLKDIS_LPTMR0 Mask */ + +#define MXC_F_MCR_CLKDIS_LPTMR1_POS 1 /**< CLKDIS_LPTMR1 Position */ +#define MXC_F_MCR_CLKDIS_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR1_POS)) /**< CLKDIS_LPTMR1 Mask */ + +#define MXC_F_MCR_CLKDIS_LPUART0_POS 2 /**< CLKDIS_LPUART0 Position */ +#define MXC_F_MCR_CLKDIS_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPUART0_POS)) /**< CLKDIS_LPUART0 Mask */ /**@} end of group MCR_CLKDIS_Register */ @@ -138,4 +176,4 @@ } #endif -#endif /* _MCR_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h index 8abbc1a..03a4eab 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h @@ -1,10 +1,11 @@ /** * @file pwrseq_regs.h * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _PWRSEQ_REGS_H_ -#define _PWRSEQ_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_PWRSEQ_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_PWRSEQ_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup pwrseq * @defgroup pwrseq_registers PWRSEQ_Registers * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. - * @details Power Sequencer / Low Power Control Register. + * @details Power Sequencer / Low Power Control Register. */ /** @@ -93,23 +93,28 @@ __IO uint32_t lppwken; /**< \b 0x34: PWRSEQ LPPWKEN Register */ __I uint32_t rsv_0x38_0x3f[2]; __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ + __I uint32_t rsv_0x44; + __IO uint32_t gp0; /**< \b 0x48: PWRSEQ GP0 Register */ + __IO uint32_t gp1; /**< \b 0x4C: PWRSEQ GP1 Register */ } mxc_pwrseq_regs_t; /* Register offsets for module PWRSEQ */ /** * @ingroup pwrseq_registers * @defgroup PWRSEQ_Register_Offsets Register Offsets - * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. + * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. * @{ */ - #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ - #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ - #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ - #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: 0x000C */ - #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: 0x0010 */ - #define MXC_R_PWRSEQ_LPPWKST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: 0x0030 */ - #define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: 0x0034 */ - #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: 0x0040 */ +#define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ +#define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ +#define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ +#define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: 0x000C */ +#define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: 0x0010 */ +#define MXC_R_PWRSEQ_LPPWKST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: 0x0030 */ +#define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: 0x0034 */ +#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: 0x0040 */ +#define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: 0x0048 */ +#define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: 0x004C */ /**@} end of group pwrseq_registers */ /** @@ -118,71 +123,68 @@ * @brief Low Power Control Register. * @{ */ - #define MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS 0 /**< LPCN_RAM0RET_EN Position */ - #define MXC_F_PWRSEQ_LPCN_RAM0RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS)) /**< LPCN_RAM0RET_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS 0 /**< LPCN_RAM0RET_EN Position */ +#define MXC_F_PWRSEQ_LPCN_RAM0RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS)) /**< LPCN_RAM0RET_EN Mask */ - #define MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS 1 /**< LPCN_RAM1RET_EN Position */ - #define MXC_F_PWRSEQ_LPCN_RAM1RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS)) /**< LPCN_RAM1RET_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS 1 /**< LPCN_RAM1RET_EN Position */ +#define MXC_F_PWRSEQ_LPCN_RAM1RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS)) /**< LPCN_RAM1RET_EN Mask */ - #define MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS 2 /**< LPCN_RAM2RET_EN Position */ - #define MXC_F_PWRSEQ_LPCN_RAM2RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS)) /**< LPCN_RAM2RET_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS 2 /**< LPCN_RAM2RET_EN Position */ +#define MXC_F_PWRSEQ_LPCN_RAM2RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS)) /**< LPCN_RAM2RET_EN Mask */ - #define MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS 3 /**< LPCN_RAM3RET_EN Position */ - #define MXC_F_PWRSEQ_LPCN_RAM3RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS)) /**< LPCN_RAM3RET_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS 3 /**< LPCN_RAM3RET_EN Position */ +#define MXC_F_PWRSEQ_LPCN_RAM3RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS)) /**< LPCN_RAM3RET_EN Mask */ - #define MXC_F_PWRSEQ_LPCN_OVR_POS 4 /**< LPCN_OVR Position */ - #define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) /**< LPCN_OVR Mask */ - #define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) /**< LPCN_OVR_0_9V Value */ - #define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_0_9V Setting */ - #define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) /**< LPCN_OVR_1_0V Value */ - #define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_0V Setting */ - #define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) /**< LPCN_OVR_1_1V Value */ - #define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_1V Setting */ +#define MXC_F_PWRSEQ_LPCN_OVR_POS 4 /**< LPCN_OVR Position */ +#define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) /**< LPCN_OVR Mask */ +#define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) /**< LPCN_OVR_0_9V Value */ +#define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_0_9V Setting */ +#define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) /**< LPCN_OVR_1_0V Value */ +#define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_0V Setting */ +#define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) /**< LPCN_OVR_1_1V Value */ +#define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_1V Setting */ - #define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS 6 /**< LPCN_VCORE_DET_BYPASS Position */ - #define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS)) /**< LPCN_VCORE_DET_BYPASS Mask */ +#define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS 6 /**< LPCN_VCORE_DET_BYPASS Position */ +#define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS)) /**< LPCN_VCORE_DET_BYPASS Mask */ - #define MXC_F_PWRSEQ_LPCN_RETREG_EN_POS 8 /**< LPCN_RETREG_EN Position */ - #define MXC_F_PWRSEQ_LPCN_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RETREG_EN_POS)) /**< LPCN_RETREG_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_RETREG_EN_POS 8 /**< LPCN_RETREG_EN Position */ +#define MXC_F_PWRSEQ_LPCN_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RETREG_EN_POS)) /**< LPCN_RETREG_EN Mask */ - #define MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS 9 /**< LPCN_STORAGE_EN Position */ - #define MXC_F_PWRSEQ_LPCN_STORAGE_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS)) /**< LPCN_STORAGE_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS 9 /**< LPCN_STORAGE_EN Position */ +#define MXC_F_PWRSEQ_LPCN_STORAGE_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS)) /**< LPCN_STORAGE_EN Mask */ - #define MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS 10 /**< LPCN_FASTWK_EN Position */ - #define MXC_F_PWRSEQ_LPCN_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS)) /**< LPCN_FASTWK_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS 10 /**< LPCN_FASTWK_EN Position */ +#define MXC_F_PWRSEQ_LPCN_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS)) /**< LPCN_FASTWK_EN Mask */ - #define MXC_F_PWRSEQ_LPCN_BG_DIS_POS 11 /**< LPCN_BG_DIS Position */ - #define MXC_F_PWRSEQ_LPCN_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BG_DIS_POS)) /**< LPCN_BG_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_BG_DIS_POS 11 /**< LPCN_BG_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BG_DIS_POS)) /**< LPCN_BG_DIS Mask */ - #define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS 12 /**< LPCN_VCOREPOR_DIS Position */ - #define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS)) /**< LPCN_VCOREPOR_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS 12 /**< LPCN_VCOREPOR_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS)) /**< LPCN_VCOREPOR_DIS Mask */ - #define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16 /**< LPCN_LDO_DIS Position */ - #define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) /**< LPCN_LDO_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16 /**< LPCN_LDO_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) /**< LPCN_LDO_DIS Mask */ - #define MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS 17 /**< LPCN_VCORE_EXT Position */ - #define MXC_F_PWRSEQ_LPCN_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS)) /**< LPCN_VCORE_EXT Mask */ +#define MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS 17 /**< LPCN_VCORE_EXT Position */ +#define MXC_F_PWRSEQ_LPCN_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS)) /**< LPCN_VCORE_EXT Mask */ - #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS 20 /**< LPCN_VCOREMON_DIS Position */ - #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) /**< LPCN_VCOREMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS 20 /**< LPCN_VCOREMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) /**< LPCN_VCOREMON_DIS Mask */ - #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS 22 /**< LPCN_VDDAMON_DIS Position */ - #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) /**< LPCN_VDDAMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS 22 /**< LPCN_VDDAMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) /**< LPCN_VDDAMON_DIS Mask */ - #define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS 25 /**< LPCN_PORVDDMON_DIS Position */ - #define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS)) /**< LPCN_PORVDDMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS 25 /**< LPCN_PORVDDMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS)) /**< LPCN_PORVDDMON_DIS Mask */ - #define MXC_F_PWRSEQ_LPCN_INRO_EN_POS 28 /**< LPCN_INRO_EN Position */ - #define MXC_F_PWRSEQ_LPCN_INRO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INRO_EN_POS)) /**< LPCN_INRO_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_INRO_EN_POS 28 /**< LPCN_INRO_EN Position */ +#define MXC_F_PWRSEQ_LPCN_INRO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INRO_EN_POS)) /**< LPCN_INRO_EN Mask */ - #define MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS 29 /**< LPCN_ERTCO_EN Position */ - #define MXC_F_PWRSEQ_LPCN_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS)) /**< LPCN_ERTCO_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS 29 /**< LPCN_ERTCO_EN Position */ +#define MXC_F_PWRSEQ_LPCN_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS)) /**< LPCN_ERTCO_EN Mask */ - #define MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS 30 /**< LPCN_TM_LPMODE Position */ - #define MXC_F_PWRSEQ_LPCN_TM_LPMODE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS)) /**< LPCN_TM_LPMODE Mask */ - - #define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS 31 /**< LPCN_TM_PWRSEQ Position */ - #define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS)) /**< LPCN_TM_PWRSEQ Mask */ +#define MXC_F_PWRSEQ_LPCN_ERTCO_PD_POS 31 /**< LPCN_ERTCO_PD Position */ +#define MXC_F_PWRSEQ_LPCN_ERTCO_PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_PD_POS)) /**< LPCN_ERTCO_PD Mask */ /**@} end of group PWRSEQ_LPCN_Register */ @@ -193,8 +195,8 @@ * wakeup status for GPIO0. * @{ */ - #define MXC_F_PWRSEQ_LPWKST0_ST_POS 0 /**< LPWKST0_ST Position */ - #define MXC_F_PWRSEQ_LPWKST0_ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_ST_POS)) /**< LPWKST0_ST Mask */ +#define MXC_F_PWRSEQ_LPWKST0_ST_POS 0 /**< LPWKST0_ST Position */ +#define MXC_F_PWRSEQ_LPWKST0_ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_ST_POS)) /**< LPWKST0_ST Mask */ /**@} end of group PWRSEQ_LPWKST0_Register */ @@ -205,8 +207,8 @@ * functionality for GPIO0. * @{ */ - #define MXC_F_PWRSEQ_LPWKEN0_EN_POS 0 /**< LPWKEN0_EN Position */ - #define MXC_F_PWRSEQ_LPWKEN0_EN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_EN_POS)) /**< LPWKEN0_EN Mask */ +#define MXC_F_PWRSEQ_LPWKEN0_EN_POS 0 /**< LPWKEN0_EN Position */ +#define MXC_F_PWRSEQ_LPWKEN0_EN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_EN_POS)) /**< LPWKEN0_EN Mask */ /**@} end of group PWRSEQ_LPWKEN0_Register */ @@ -216,14 +218,14 @@ * @brief Low Power Peripheral Wakeup Status Register. * @{ */ - #define MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS 0 /**< LPPWKST_LPTMR0 Position */ - #define MXC_F_PWRSEQ_LPPWKST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS)) /**< LPPWKST_LPTMR0 Mask */ +#define MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS 0 /**< LPPWKST_LPTMR0 Position */ +#define MXC_F_PWRSEQ_LPPWKST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS)) /**< LPPWKST_LPTMR0 Mask */ - #define MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS 1 /**< LPPWKST_LPTMR1 Position */ - #define MXC_F_PWRSEQ_LPPWKST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS)) /**< LPPWKST_LPTMR1 Mask */ +#define MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS 1 /**< LPPWKST_LPTMR1 Position */ +#define MXC_F_PWRSEQ_LPPWKST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS)) /**< LPPWKST_LPTMR1 Mask */ - #define MXC_F_PWRSEQ_LPPWKST_LPUART0_POS 2 /**< LPPWKST_LPUART0 Position */ - #define MXC_F_PWRSEQ_LPPWKST_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPUART0_POS)) /**< LPPWKST_LPUART0 Mask */ +#define MXC_F_PWRSEQ_LPPWKST_LPUART0_POS 2 /**< LPPWKST_LPUART0 Position */ +#define MXC_F_PWRSEQ_LPPWKST_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPUART0_POS)) /**< LPPWKST_LPUART0 Mask */ /**@} end of group PWRSEQ_LPPWKST_Register */ @@ -233,14 +235,14 @@ * @brief Low Power Peripheral Wakeup Enable Register. * @{ */ - #define MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS 0 /**< LPPWKEN_LPTMR0 Position */ - #define MXC_F_PWRSEQ_LPPWKEN_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS)) /**< LPPWKEN_LPTMR0 Mask */ +#define MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS 0 /**< LPPWKEN_LPTMR0 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS)) /**< LPPWKEN_LPTMR0 Mask */ - #define MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS 1 /**< LPPWKEN_LPTMR1 Position */ - #define MXC_F_PWRSEQ_LPPWKEN_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS)) /**< LPPWKEN_LPTMR1 Mask */ +#define MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS 1 /**< LPPWKEN_LPTMR1 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS)) /**< LPPWKEN_LPTMR1 Mask */ - #define MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS 2 /**< LPPWKEN_LPUART0 Position */ - #define MXC_F_PWRSEQ_LPPWKEN_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS)) /**< LPPWKEN_LPUART0 Mask */ +#define MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS 2 /**< LPPWKEN_LPUART0 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS)) /**< LPPWKEN_LPUART0 Mask */ /**@} end of group PWRSEQ_LPPWKEN_Register */ @@ -250,17 +252,17 @@ * @brief Low Power Memory Shutdown Control. * @{ */ - #define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */ - #define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */ - #define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */ - #define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */ - #define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */ - #define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */ - #define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ - #define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ /**@} end of group PWRSEQ_LPMEMSD_Register */ @@ -268,4 +270,4 @@ } #endif -#endif /* _PWRSEQ_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_PWRSEQ_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h index cf5c3d1..61699ec 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h @@ -1,10 +1,11 @@ /** * @file rtc_regs.h * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _RTC_REGS_H_ -#define _RTC_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_RTC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_RTC_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup rtc * @defgroup rtc_registers RTC_Registers * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. - * @details Real Time Clock and Alarm. + * @details Real Time Clock and Alarm. */ /** @@ -96,16 +96,16 @@ /** * @ingroup rtc_registers * @defgroup RTC_Register_Offsets Register Offsets - * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. + * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. * @{ */ - #define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: 0x0000 */ - #define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: 0x0004 */ - #define MXC_R_RTC_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: 0x0008 */ - #define MXC_R_RTC_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: 0x000C */ - #define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: 0x0010 */ - #define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: 0x0014 */ - #define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: 0x0018 */ +#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: 0x0000 */ +#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: 0x0004 */ +#define MXC_R_RTC_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: 0x0008 */ +#define MXC_R_RTC_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: 0x000C */ +#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: 0x0010 */ +#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: 0x0014 */ +#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: 0x0018 */ /**@} end of group rtc_registers */ /** @@ -114,8 +114,8 @@ * @brief RTC Second Counter. This register contains the 32-bit second counter. * @{ */ - #define MXC_F_RTC_SEC_SEC_POS 0 /**< SEC_SEC Position */ - #define MXC_F_RTC_SEC_SEC ((uint32_t)(0xFFUL << MXC_F_RTC_SEC_SEC_POS)) /**< SEC_SEC Mask */ +#define MXC_F_RTC_SEC_SEC_POS 0 /**< SEC_SEC Position */ +#define MXC_F_RTC_SEC_SEC ((uint32_t)(0xFFUL << MXC_F_RTC_SEC_SEC_POS)) /**< SEC_SEC Mask */ /**@} end of group RTC_SEC_Register */ @@ -126,8 +126,8 @@ * when this register rolls over from 0xFF to 0x00. * @{ */ - #define MXC_F_RTC_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */ - #define MXC_F_RTC_SSEC_SSEC ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */ +#define MXC_F_RTC_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */ +#define MXC_F_RTC_SSEC_SSEC ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */ /**@} end of group RTC_SSEC_Register */ @@ -137,8 +137,8 @@ * @brief Time-of-day Alarm. * @{ */ - #define MXC_F_RTC_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */ - #define MXC_F_RTC_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */ +#define MXC_F_RTC_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */ +#define MXC_F_RTC_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */ /**@} end of group RTC_TODA_Register */ @@ -149,8 +149,8 @@ * second alarm. * @{ */ - #define MXC_F_RTC_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */ - #define MXC_F_RTC_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */ +#define MXC_F_RTC_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */ +#define MXC_F_RTC_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */ /**@} end of group RTC_SSECA_Register */ @@ -160,49 +160,49 @@ * @brief RTC Control Register. * @{ */ - #define MXC_F_RTC_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_RTC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_RTC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_RTC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_RTC_CTRL_TOD_ALARM_IE_POS 1 /**< CTRL_TOD_ALARM_IE Position */ - #define MXC_F_RTC_CTRL_TOD_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */ +#define MXC_F_RTC_CTRL_TOD_ALARM_IE_POS 1 /**< CTRL_TOD_ALARM_IE Position */ +#define MXC_F_RTC_CTRL_TOD_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */ - #define MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS 2 /**< CTRL_SSEC_ALARM_IE Position */ - #define MXC_F_RTC_CTRL_SSEC_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */ +#define MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS 2 /**< CTRL_SSEC_ALARM_IE Position */ +#define MXC_F_RTC_CTRL_SSEC_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */ - #define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ - #define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ +#define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ +#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ - #define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ - #define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ +#define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ +#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ - #define MXC_F_RTC_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */ - #define MXC_F_RTC_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */ +#define MXC_F_RTC_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */ +#define MXC_F_RTC_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */ - #define MXC_F_RTC_CTRL_TOD_ALARM_POS 6 /**< CTRL_TOD_ALARM Position */ - #define MXC_F_RTC_CTRL_TOD_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_POS)) /**< CTRL_TOD_ALARM Mask */ +#define MXC_F_RTC_CTRL_TOD_ALARM_POS 6 /**< CTRL_TOD_ALARM Position */ +#define MXC_F_RTC_CTRL_TOD_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_POS)) /**< CTRL_TOD_ALARM Mask */ - #define MXC_F_RTC_CTRL_SSEC_ALARM_POS 7 /**< CTRL_SSEC_ALARM Position */ - #define MXC_F_RTC_CTRL_SSEC_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_POS)) /**< CTRL_SSEC_ALARM Mask */ +#define MXC_F_RTC_CTRL_SSEC_ALARM_POS 7 /**< CTRL_SSEC_ALARM Position */ +#define MXC_F_RTC_CTRL_SSEC_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_POS)) /**< CTRL_SSEC_ALARM Mask */ - #define MXC_F_RTC_CTRL_SQW_EN_POS 8 /**< CTRL_SQW_EN Position */ - #define MXC_F_RTC_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */ +#define MXC_F_RTC_CTRL_SQW_EN_POS 8 /**< CTRL_SQW_EN Position */ +#define MXC_F_RTC_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */ - #define MXC_F_RTC_CTRL_SQW_SEL_POS 9 /**< CTRL_SQW_SEL Position */ - #define MXC_F_RTC_CTRL_SQW_SEL ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */ - #define MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */ - #define MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */ - #define MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */ - #define MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */ - #define MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */ - #define MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */ - #define MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_SQW_SEL_CLKDIV8 Value */ - #define MXC_S_RTC_CTRL_SQW_SEL_CLKDIV8 (MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_CLKDIV8 Setting */ +#define MXC_F_RTC_CTRL_SQW_SEL_POS 9 /**< CTRL_SQW_SEL Position */ +#define MXC_F_RTC_CTRL_SQW_SEL ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */ +#define MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */ +#define MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */ +#define MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */ +#define MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */ +#define MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */ +#define MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */ +#define MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_SQW_SEL_CLKDIV8 Value */ +#define MXC_S_RTC_CTRL_SQW_SEL_CLKDIV8 (MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_CLKDIV8 Setting */ - #define MXC_F_RTC_CTRL_RD_EN_POS 14 /**< CTRL_RD_EN Position */ - #define MXC_F_RTC_CTRL_RD_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */ +#define MXC_F_RTC_CTRL_RD_EN_POS 14 /**< CTRL_RD_EN Position */ +#define MXC_F_RTC_CTRL_RD_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */ - #define MXC_F_RTC_CTRL_WR_EN_POS 15 /**< CTRL_WR_EN Position */ - #define MXC_F_RTC_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */ +#define MXC_F_RTC_CTRL_WR_EN_POS 15 /**< CTRL_WR_EN Position */ +#define MXC_F_RTC_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */ /**@} end of group RTC_CTRL_Register */ @@ -212,11 +212,11 @@ * @brief RTC Trim Register. * @{ */ - #define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ - #define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ +#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ +#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ - #define MXC_F_RTC_TRIM_VRTC_TMR_POS 8 /**< TRIM_VRTC_TMR Position */ - #define MXC_F_RTC_TRIM_VRTC_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */ +#define MXC_F_RTC_TRIM_VRTC_TMR_POS 8 /**< TRIM_VRTC_TMR Position */ +#define MXC_F_RTC_TRIM_VRTC_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */ /**@} end of group RTC_TRIM_Register */ @@ -226,11 +226,11 @@ * @brief RTC Oscillator Control Register. * @{ */ - #define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ - #define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ +#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ +#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ - #define MXC_F_RTC_OSCCTRL_SQW_32K_POS 5 /**< OSCCTRL_SQW_32K Position */ - #define MXC_F_RTC_OSCCTRL_SQW_32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */ +#define MXC_F_RTC_OSCCTRL_SQW_32K_POS 5 /**< OSCCTRL_SQW_32K Position */ +#define MXC_F_RTC_OSCCTRL_SQW_32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */ /**@} end of group RTC_OSCCTRL_Register */ @@ -238,4 +238,4 @@ } #endif -#endif /* _RTC_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_RTC_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h index 1142bb9..6fbb32a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h @@ -1,10 +1,11 @@ /** * @file sir_regs.h * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _SIR_REGS_H_ -#define _SIR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SIR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SIR_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup sir * @defgroup sir_registers SIR_Registers * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. - * @details System Initialization Registers. + * @details System Initialization Registers. */ /** @@ -91,11 +91,11 @@ /** * @ingroup sir_registers * @defgroup SIR_Register_Offsets Register Offsets - * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. + * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. * @{ */ - #define MXC_R_SIR_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ - #define MXC_R_SIR_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ +#define MXC_R_SIR_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ +#define MXC_R_SIR_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ /**@} end of group sir_registers */ /** @@ -104,11 +104,11 @@ * @brief System Initialization Status Register. * @{ */ - #define MXC_F_SIR_SIR_STATUS_CFG_VALID_POS 0 /**< SIR_STATUS_CFG_VALID Position */ - #define MXC_F_SIR_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_SIR_STATUS_CFG_VALID_POS)) /**< SIR_STATUS_CFG_VALID Mask */ +#define MXC_F_SIR_SIR_STATUS_CFG_VALID_POS 0 /**< SIR_STATUS_CFG_VALID Position */ +#define MXC_F_SIR_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_SIR_STATUS_CFG_VALID_POS)) /**< SIR_STATUS_CFG_VALID Mask */ - #define MXC_F_SIR_SIR_STATUS_CFG_ERR_POS 1 /**< SIR_STATUS_CFG_ERR Position */ - #define MXC_F_SIR_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_SIR_STATUS_CFG_ERR_POS)) /**< SIR_STATUS_CFG_ERR Mask */ +#define MXC_F_SIR_SIR_STATUS_CFG_ERR_POS 1 /**< SIR_STATUS_CFG_ERR Position */ +#define MXC_F_SIR_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_SIR_STATUS_CFG_ERR_POS)) /**< SIR_STATUS_CFG_ERR Mask */ /**@} end of group SIR_SIR_STATUS_Register */ @@ -120,8 +120,8 @@ * 1). * @{ */ - #define MXC_F_SIR_SIR_ADDR_ADDR_POS 0 /**< SIR_ADDR_ADDR Position */ - #define MXC_F_SIR_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_SIR_ADDR_ADDR_POS)) /**< SIR_ADDR_ADDR Mask */ +#define MXC_F_SIR_SIR_ADDR_ADDR_POS 0 /**< SIR_ADDR_ADDR Position */ +#define MXC_F_SIR_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_SIR_ADDR_ADDR_POS)) /**< SIR_ADDR_ADDR Mask */ /**@} end of group SIR_SIR_ADDR_Register */ @@ -129,4 +129,4 @@ } #endif -#endif /* _SIR_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SIR_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h index 2956020..da60b36 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h @@ -1,10 +1,11 @@ /** * @file spi_regs.h * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _SPI_REGS_H_ -#define _SPI_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SPI_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SPI_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup spi * @defgroup spi_registers SPI_Registers * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. - * @details SPI peripheral. + * @details SPI peripheral. */ /** @@ -83,11 +83,11 @@ * Structure type to access the SPI Registers. */ typedef struct { - union{ - __IO uint32_t fifo32; /**< \b 0x00: SPI FIFO32 Register */ - __IO uint16_t fifo16[2]; /**< \b 0x00: SPI FIFO16 Register */ - __IO uint8_t fifo8[4]; /**< \b 0x00: SPI FIFO8 Register */ - }; + union { + __IO uint32_t fifo32; /**< \b 0x00: SPI FIFO32 Register */ + __IO uint16_t fifo16[2]; /**< \b 0x00: SPI FIFO16 Register */ + __IO uint8_t fifo8[4]; /**< \b 0x00: SPI FIFO8 Register */ + }; __IO uint32_t ctrl0; /**< \b 0x04: SPI CTRL0 Register */ __IO uint32_t ctrl1; /**< \b 0x08: SPI CTRL1 Register */ __IO uint32_t ctrl2; /**< \b 0x0C: SPI CTRL2 Register */ @@ -106,23 +106,23 @@ /** * @ingroup spi_registers * @defgroup SPI_Register_Offsets Register Offsets - * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. + * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. * @{ */ - #define MXC_R_SPI_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ - #define MXC_R_SPI_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ - #define MXC_R_SPI_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ - #define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: 0x0004 */ - #define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: 0x0008 */ - #define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: 0x000C */ - #define MXC_R_SPI_SSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: 0x0010 */ - #define MXC_R_SPI_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: 0x0014 */ - #define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: 0x001C */ - #define MXC_R_SPI_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: 0x0020 */ - #define MXC_R_SPI_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: 0x0024 */ - #define MXC_R_SPI_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: 0x0028 */ - #define MXC_R_SPI_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: 0x002C */ - #define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: 0x0030 */ +#define MXC_R_SPI_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ +#define MXC_R_SPI_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ +#define MXC_R_SPI_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ +#define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: 0x0004 */ +#define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: 0x0008 */ +#define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: 0x000C */ +#define MXC_R_SPI_SSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: 0x0010 */ +#define MXC_R_SPI_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: 0x0014 */ +#define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: 0x001C */ +#define MXC_R_SPI_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: 0x0020 */ +#define MXC_R_SPI_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: 0x0024 */ +#define MXC_R_SPI_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: 0x0028 */ +#define MXC_R_SPI_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: 0x002C */ +#define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: 0x0030 */ /**@} end of group spi_registers */ /** @@ -131,8 +131,8 @@ * @brief Register for reading and writing the FIFO. * @{ */ - #define MXC_F_SPI_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */ - #define MXC_F_SPI_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */ +#define MXC_F_SPI_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */ +#define MXC_F_SPI_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */ /**@} end of group SPI_FIFO32_Register */ @@ -142,8 +142,8 @@ * @brief Register for reading and writing the FIFO. * @{ */ - #define MXC_F_SPI_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */ - #define MXC_F_SPI_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */ +#define MXC_F_SPI_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */ +#define MXC_F_SPI_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */ /**@} end of group SPI_FIFO16_Register */ @@ -153,8 +153,8 @@ * @brief Register for reading and writing the FIFO. * @{ */ - #define MXC_F_SPI_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */ - #define MXC_F_SPI_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */ +#define MXC_F_SPI_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */ +#define MXC_F_SPI_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */ /**@} end of group SPI_FIFO8_Register */ @@ -164,31 +164,31 @@ * @brief Register for controlling SPI peripheral. * @{ */ - #define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ - #define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ +#define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ +#define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ - #define MXC_F_SPI_CTRL0_MST_MODE_POS 1 /**< CTRL0_MST_MODE Position */ - #define MXC_F_SPI_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */ +#define MXC_F_SPI_CTRL0_MST_MODE_POS 1 /**< CTRL0_MST_MODE Position */ +#define MXC_F_SPI_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */ - #define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ - #define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ +#define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ +#define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ - #define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ - #define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ +#define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ +#define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ - #define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ - #define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ +#define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ +#define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ - #define MXC_F_SPI_CTRL0_SS_ACTIVE_POS 16 /**< CTRL0_SS_ACTIVE Position */ - #define MXC_F_SPI_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */ - #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */ - #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */ - #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */ - #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */ - #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */ - #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */ - #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */ - #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */ +#define MXC_F_SPI_CTRL0_SS_ACTIVE_POS 16 /**< CTRL0_SS_ACTIVE Position */ +#define MXC_F_SPI_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */ +#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */ +#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */ +#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */ +#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */ +#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */ +#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */ +#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */ +#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */ /**@} end of group SPI_CTRL0_Register */ @@ -198,11 +198,11 @@ * @brief Register for controlling SPI peripheral. * @{ */ - #define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ - #define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ +#define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ +#define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ - #define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ - #define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ +#define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ +#define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ /**@} end of group SPI_CTRL1_Register */ @@ -212,39 +212,39 @@ * @brief Register for controlling SPI peripheral. * @{ */ - #define MXC_F_SPI_CTRL2_CLKPHA_POS 0 /**< CTRL2_CLKPHA Position */ - #define MXC_F_SPI_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */ +#define MXC_F_SPI_CTRL2_CLKPHA_POS 0 /**< CTRL2_CLKPHA Position */ +#define MXC_F_SPI_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */ - #define MXC_F_SPI_CTRL2_CLKPOL_POS 1 /**< CTRL2_CLKPOL Position */ - #define MXC_F_SPI_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */ +#define MXC_F_SPI_CTRL2_CLKPOL_POS 1 /**< CTRL2_CLKPOL Position */ +#define MXC_F_SPI_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */ - #define MXC_F_SPI_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ - #define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ - #define MXC_V_SPI_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ - #define MXC_S_SPI_CTRL2_NUMBITS_0 (MXC_V_SPI_CTRL2_NUMBITS_0 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ +#define MXC_F_SPI_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ +#define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ +#define MXC_V_SPI_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_0 (MXC_V_SPI_CTRL2_NUMBITS_0 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ - #define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ - #define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ - #define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ - #define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ - #define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ - #define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ - #define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ - #define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ +#define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ +#define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ - #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ - #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ +#define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ +#define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ - #define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ - #define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ - #define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ - #define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ - #define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ - #define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ - #define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ - #define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ - #define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ - #define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ +#define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ +#define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ +#define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ +#define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ +#define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ +#define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ +#define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ +#define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ +#define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ +#define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ /**@} end of group SPI_CTRL2_Register */ @@ -254,20 +254,20 @@ * @brief Register for controlling SPI peripheral/Slave Select Timing. * @{ */ - #define MXC_F_SPI_SSTIME_PRE_POS 0 /**< SSTIME_PRE Position */ - #define MXC_F_SPI_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */ - #define MXC_V_SPI_SSTIME_PRE_256 ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */ - #define MXC_S_SPI_SSTIME_PRE_256 (MXC_V_SPI_SSTIME_PRE_256 << MXC_F_SPI_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */ +#define MXC_F_SPI_SSTIME_PRE_POS 0 /**< SSTIME_PRE Position */ +#define MXC_F_SPI_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */ +#define MXC_V_SPI_SSTIME_PRE_256 ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */ +#define MXC_S_SPI_SSTIME_PRE_256 (MXC_V_SPI_SSTIME_PRE_256 << MXC_F_SPI_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */ - #define MXC_F_SPI_SSTIME_POST_POS 8 /**< SSTIME_POST Position */ - #define MXC_F_SPI_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_POST_POS)) /**< SSTIME_POST Mask */ - #define MXC_V_SPI_SSTIME_POST_256 ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */ - #define MXC_S_SPI_SSTIME_POST_256 (MXC_V_SPI_SSTIME_POST_256 << MXC_F_SPI_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */ +#define MXC_F_SPI_SSTIME_POST_POS 8 /**< SSTIME_POST Position */ +#define MXC_F_SPI_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_POST_POS)) /**< SSTIME_POST Mask */ +#define MXC_V_SPI_SSTIME_POST_256 ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */ +#define MXC_S_SPI_SSTIME_POST_256 (MXC_V_SPI_SSTIME_POST_256 << MXC_F_SPI_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */ - #define MXC_F_SPI_SSTIME_INACT_POS 16 /**< SSTIME_INACT Position */ - #define MXC_F_SPI_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */ - #define MXC_V_SPI_SSTIME_INACT_256 ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */ - #define MXC_S_SPI_SSTIME_INACT_256 (MXC_V_SPI_SSTIME_INACT_256 << MXC_F_SPI_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */ +#define MXC_F_SPI_SSTIME_INACT_POS 16 /**< SSTIME_INACT Position */ +#define MXC_F_SPI_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */ +#define MXC_V_SPI_SSTIME_INACT_256 ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */ +#define MXC_S_SPI_SSTIME_INACT_256 (MXC_V_SPI_SSTIME_INACT_256 << MXC_F_SPI_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */ /**@} end of group SPI_SSTIME_Register */ @@ -277,18 +277,18 @@ * @brief Register for controlling SPI clock rate. * @{ */ - #define MXC_F_SPI_CLKCTRL_LO_POS 0 /**< CLKCTRL_LO Position */ - #define MXC_F_SPI_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */ - #define MXC_V_SPI_CLKCTRL_LO_DIS ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */ - #define MXC_S_SPI_CLKCTRL_LO_DIS (MXC_V_SPI_CLKCTRL_LO_DIS << MXC_F_SPI_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */ +#define MXC_F_SPI_CLKCTRL_LO_POS 0 /**< CLKCTRL_LO Position */ +#define MXC_F_SPI_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */ +#define MXC_V_SPI_CLKCTRL_LO_DIS ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */ +#define MXC_S_SPI_CLKCTRL_LO_DIS (MXC_V_SPI_CLKCTRL_LO_DIS << MXC_F_SPI_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */ - #define MXC_F_SPI_CLKCTRL_HI_POS 8 /**< CLKCTRL_HI Position */ - #define MXC_F_SPI_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */ - #define MXC_V_SPI_CLKCTRL_HI_DIS ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */ - #define MXC_S_SPI_CLKCTRL_HI_DIS (MXC_V_SPI_CLKCTRL_HI_DIS << MXC_F_SPI_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */ +#define MXC_F_SPI_CLKCTRL_HI_POS 8 /**< CLKCTRL_HI Position */ +#define MXC_F_SPI_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */ +#define MXC_V_SPI_CLKCTRL_HI_DIS ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */ +#define MXC_S_SPI_CLKCTRL_HI_DIS (MXC_V_SPI_CLKCTRL_HI_DIS << MXC_F_SPI_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */ - #define MXC_F_SPI_CLKCTRL_CLKDIV_POS 16 /**< CLKCTRL_CLKDIV Position */ - #define MXC_F_SPI_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ +#define MXC_F_SPI_CLKCTRL_CLKDIV_POS 16 /**< CLKCTRL_CLKDIV Position */ +#define MXC_F_SPI_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ /**@} end of group SPI_CLKCTRL_Register */ @@ -298,35 +298,35 @@ * @brief Register for controlling DMA. * @{ */ - #define MXC_F_SPI_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ - #define MXC_F_SPI_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ +#define MXC_F_SPI_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ +#define MXC_F_SPI_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ - #define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ - #define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ +#define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ +#define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ - #define MXC_F_SPI_DMA_TX_FLUSH_POS 7 /**< DMA_TX_FLUSH Position */ - #define MXC_F_SPI_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */ +#define MXC_F_SPI_DMA_TX_FLUSH_POS 7 /**< DMA_TX_FLUSH Position */ +#define MXC_F_SPI_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */ - #define MXC_F_SPI_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */ - #define MXC_F_SPI_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */ +#define MXC_F_SPI_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */ +#define MXC_F_SPI_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */ - #define MXC_F_SPI_DMA_DMA_TX_EN_POS 15 /**< DMA_DMA_TX_EN Position */ - #define MXC_F_SPI_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */ +#define MXC_F_SPI_DMA_DMA_TX_EN_POS 15 /**< DMA_DMA_TX_EN Position */ +#define MXC_F_SPI_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */ - #define MXC_F_SPI_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */ - #define MXC_F_SPI_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ +#define MXC_F_SPI_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */ +#define MXC_F_SPI_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ - #define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ - #define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ +#define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ +#define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ - #define MXC_F_SPI_DMA_RX_FLUSH_POS 23 /**< DMA_RX_FLUSH Position */ - #define MXC_F_SPI_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */ +#define MXC_F_SPI_DMA_RX_FLUSH_POS 23 /**< DMA_RX_FLUSH Position */ +#define MXC_F_SPI_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */ - #define MXC_F_SPI_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */ - #define MXC_F_SPI_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */ +#define MXC_F_SPI_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */ +#define MXC_F_SPI_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */ - #define MXC_F_SPI_DMA_DMA_RX_EN_POS 31 /**< DMA_DMA_RX_EN Position */ - #define MXC_F_SPI_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */ +#define MXC_F_SPI_DMA_DMA_RX_EN_POS 31 /**< DMA_DMA_RX_EN Position */ +#define MXC_F_SPI_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */ /**@} end of group SPI_DMA_Register */ @@ -337,44 +337,44 @@ * clear. * @{ */ - #define MXC_F_SPI_INTFL_TX_THD_POS 0 /**< INTFL_TX_THD Position */ - #define MXC_F_SPI_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */ +#define MXC_F_SPI_INTFL_TX_THD_POS 0 /**< INTFL_TX_THD Position */ +#define MXC_F_SPI_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */ - #define MXC_F_SPI_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */ - #define MXC_F_SPI_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */ +#define MXC_F_SPI_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */ +#define MXC_F_SPI_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */ - #define MXC_F_SPI_INTFL_RX_THD_POS 2 /**< INTFL_RX_THD Position */ - #define MXC_F_SPI_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ +#define MXC_F_SPI_INTFL_RX_THD_POS 2 /**< INTFL_RX_THD Position */ +#define MXC_F_SPI_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ - #define MXC_F_SPI_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */ - #define MXC_F_SPI_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ +#define MXC_F_SPI_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */ +#define MXC_F_SPI_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ - #define MXC_F_SPI_INTFL_SSA_POS 4 /**< INTFL_SSA Position */ - #define MXC_F_SPI_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS)) /**< INTFL_SSA Mask */ +#define MXC_F_SPI_INTFL_SSA_POS 4 /**< INTFL_SSA Position */ +#define MXC_F_SPI_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS)) /**< INTFL_SSA Mask */ - #define MXC_F_SPI_INTFL_SSD_POS 5 /**< INTFL_SSD Position */ - #define MXC_F_SPI_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS)) /**< INTFL_SSD Mask */ +#define MXC_F_SPI_INTFL_SSD_POS 5 /**< INTFL_SSD Position */ +#define MXC_F_SPI_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS)) /**< INTFL_SSD Mask */ - #define MXC_F_SPI_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */ - #define MXC_F_SPI_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */ +#define MXC_F_SPI_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */ +#define MXC_F_SPI_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */ - #define MXC_F_SPI_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ - #define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ +#define MXC_F_SPI_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ +#define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ - #define MXC_F_SPI_INTFL_MST_DONE_POS 11 /**< INTFL_MST_DONE Position */ - #define MXC_F_SPI_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */ +#define MXC_F_SPI_INTFL_MST_DONE_POS 11 /**< INTFL_MST_DONE Position */ +#define MXC_F_SPI_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */ - #define MXC_F_SPI_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ - #define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ +#define MXC_F_SPI_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ +#define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ - #define MXC_F_SPI_INTFL_TX_UN_POS 13 /**< INTFL_TX_UN Position */ - #define MXC_F_SPI_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */ +#define MXC_F_SPI_INTFL_TX_UN_POS 13 /**< INTFL_TX_UN Position */ +#define MXC_F_SPI_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */ - #define MXC_F_SPI_INTFL_RX_OV_POS 14 /**< INTFL_RX_OV Position */ - #define MXC_F_SPI_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ +#define MXC_F_SPI_INTFL_RX_OV_POS 14 /**< INTFL_RX_OV Position */ +#define MXC_F_SPI_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ - #define MXC_F_SPI_INTFL_RX_UN_POS 15 /**< INTFL_RX_UN Position */ - #define MXC_F_SPI_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */ +#define MXC_F_SPI_INTFL_RX_UN_POS 15 /**< INTFL_RX_UN Position */ +#define MXC_F_SPI_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */ /**@} end of group SPI_INTFL_Register */ @@ -384,44 +384,44 @@ * @brief Register for enabling interrupts. * @{ */ - #define MXC_F_SPI_INTEN_TX_THD_POS 0 /**< INTEN_TX_THD Position */ - #define MXC_F_SPI_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */ +#define MXC_F_SPI_INTEN_TX_THD_POS 0 /**< INTEN_TX_THD Position */ +#define MXC_F_SPI_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */ - #define MXC_F_SPI_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */ - #define MXC_F_SPI_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */ +#define MXC_F_SPI_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */ +#define MXC_F_SPI_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */ - #define MXC_F_SPI_INTEN_RX_THD_POS 2 /**< INTEN_RX_THD Position */ - #define MXC_F_SPI_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ +#define MXC_F_SPI_INTEN_RX_THD_POS 2 /**< INTEN_RX_THD Position */ +#define MXC_F_SPI_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ - #define MXC_F_SPI_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */ - #define MXC_F_SPI_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ +#define MXC_F_SPI_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */ +#define MXC_F_SPI_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ - #define MXC_F_SPI_INTEN_SSA_POS 4 /**< INTEN_SSA Position */ - #define MXC_F_SPI_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS)) /**< INTEN_SSA Mask */ +#define MXC_F_SPI_INTEN_SSA_POS 4 /**< INTEN_SSA Position */ +#define MXC_F_SPI_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS)) /**< INTEN_SSA Mask */ - #define MXC_F_SPI_INTEN_SSD_POS 5 /**< INTEN_SSD Position */ - #define MXC_F_SPI_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS)) /**< INTEN_SSD Mask */ +#define MXC_F_SPI_INTEN_SSD_POS 5 /**< INTEN_SSD Position */ +#define MXC_F_SPI_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS)) /**< INTEN_SSD Mask */ - #define MXC_F_SPI_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */ - #define MXC_F_SPI_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */ +#define MXC_F_SPI_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */ +#define MXC_F_SPI_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */ - #define MXC_F_SPI_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ - #define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ +#define MXC_F_SPI_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ +#define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ - #define MXC_F_SPI_INTEN_MST_DONE_POS 11 /**< INTEN_MST_DONE Position */ - #define MXC_F_SPI_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */ +#define MXC_F_SPI_INTEN_MST_DONE_POS 11 /**< INTEN_MST_DONE Position */ +#define MXC_F_SPI_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */ - #define MXC_F_SPI_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ - #define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ +#define MXC_F_SPI_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ +#define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ - #define MXC_F_SPI_INTEN_TX_UN_POS 13 /**< INTEN_TX_UN Position */ - #define MXC_F_SPI_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */ +#define MXC_F_SPI_INTEN_TX_UN_POS 13 /**< INTEN_TX_UN Position */ +#define MXC_F_SPI_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */ - #define MXC_F_SPI_INTEN_RX_OV_POS 14 /**< INTEN_RX_OV Position */ - #define MXC_F_SPI_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ +#define MXC_F_SPI_INTEN_RX_OV_POS 14 /**< INTEN_RX_OV Position */ +#define MXC_F_SPI_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ - #define MXC_F_SPI_INTEN_RX_UN_POS 15 /**< INTEN_RX_UN Position */ - #define MXC_F_SPI_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */ +#define MXC_F_SPI_INTEN_RX_UN_POS 15 /**< INTEN_RX_UN Position */ +#define MXC_F_SPI_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */ /**@} end of group SPI_INTEN_Register */ @@ -431,17 +431,17 @@ * @brief Register for wake up flags. All bits in this register are write 1 to clear. * @{ */ - #define MXC_F_SPI_WKFL_TX_THD_POS 0 /**< WKFL_TX_THD Position */ - #define MXC_F_SPI_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */ +#define MXC_F_SPI_WKFL_TX_THD_POS 0 /**< WKFL_TX_THD Position */ +#define MXC_F_SPI_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */ - #define MXC_F_SPI_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */ - #define MXC_F_SPI_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */ +#define MXC_F_SPI_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */ +#define MXC_F_SPI_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */ - #define MXC_F_SPI_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ - #define MXC_F_SPI_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ +#define MXC_F_SPI_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ +#define MXC_F_SPI_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ - #define MXC_F_SPI_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */ - #define MXC_F_SPI_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ +#define MXC_F_SPI_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */ +#define MXC_F_SPI_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ /**@} end of group SPI_WKFL_Register */ @@ -451,17 +451,17 @@ * @brief Register for wake up enable. * @{ */ - #define MXC_F_SPI_WKEN_TX_THD_POS 0 /**< WKEN_TX_THD Position */ - #define MXC_F_SPI_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */ +#define MXC_F_SPI_WKEN_TX_THD_POS 0 /**< WKEN_TX_THD Position */ +#define MXC_F_SPI_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */ - #define MXC_F_SPI_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */ - #define MXC_F_SPI_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */ +#define MXC_F_SPI_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */ +#define MXC_F_SPI_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */ - #define MXC_F_SPI_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ - #define MXC_F_SPI_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ +#define MXC_F_SPI_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ +#define MXC_F_SPI_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ - #define MXC_F_SPI_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */ - #define MXC_F_SPI_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ +#define MXC_F_SPI_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */ +#define MXC_F_SPI_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ /**@} end of group SPI_WKEN_Register */ @@ -471,8 +471,8 @@ * @brief SPI Status register. * @{ */ - #define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ - #define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ +#define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ +#define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ /**@} end of group SPI_STAT_Register */ @@ -480,4 +480,4 @@ } #endif -#endif /* _SPI_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SPI_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/system_max32670.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/system_max32670.h index 09684bd..83cc404 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/system_max32670.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/system_max32670.h @@ -1,5 +1,5 @@ -/******************************************************************************* - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,11 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * ******************************************************************************/ -#ifndef _SYSTEM_MAX32670_H_ -#define _SYSTEM_MAX32670_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SYSTEM_MAX32670_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SYSTEM_MAX32670_H_ #ifdef __cplusplus extern "C" { @@ -53,42 +52,42 @@ /* NOTE: EXTCLK needs to be defined by user based on the clock they supply */ #ifndef EXTCLK_FREQ -#define EXTCLK_FREQ 75000000 +#define EXTCLK_FREQ 12500000 #endif /* NOTE: This is the nominal value for INRO. The actual value may vary from chip to chip. Update if use of this oscillator requires precise timing.*/ /* NOTE: INRO was previously named NANORING */ #ifndef INRO_FREQ -#define INRO_FREQ 80000 +#define INRO_FREQ 80000 #endif //NOTE: IPO clock bit is documented as 96MHz, but SR says this will be 100. #ifndef IPO_FREQ -#define IPO_FREQ 100000000 +#define IPO_FREQ 100000000 #endif #ifndef IBRO_FREQ -#define IBRO_FREQ 7372800 +#define IBRO_FREQ 7372800 #endif /* NOTE: ERFO_FREQ (16MHz-32MHz) needs to be defined by user based on the clock they supply */ #ifndef ERFO_FREQ -#define ERFO_FREQ 32000000 +#define ERFO_FREQ 32000000 #endif #ifndef ERTCO_FREQ -#define ERTCO_FREQ 32768 -#endif - -#ifndef HIRC_FREQ -#define HIRC_FREQ IPO_FREQ +#define ERTCO_FREQ 32768 #endif -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +#ifndef HIRC_FREQ +#define HIRC_FREQ IPO_FREQ +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ #ifdef PeripheralClock #warning PeripheralClock define is being overidden. #else -#define PeripheralClock (SystemCoreClock /2) /*!< Peripheral Clock Frequency */ +#define PeripheralClock (SystemCoreClock / 2) /*!< Peripheral Clock Frequency */ #endif /* @@ -111,4 +110,4 @@ } #endif -#endif /* _SYSTEM_MAX32670_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SYSTEM_MAX32670_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h index 3203bee..5b0368f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h @@ -1,10 +1,11 @@ /** * @file tmr_regs.h * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _TMR_REGS_H_ -#define _TMR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TMR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TMR_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup tmr * @defgroup tmr_registers TMR_Registers * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. - * @details Low-Power Configurable Timer + * @details Low-Power Configurable Timer */ /** @@ -97,17 +97,17 @@ /** * @ingroup tmr_registers * @defgroup TMR_Register_Offsets Register Offsets - * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. + * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. * @{ */ - #define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: 0x0000 */ - #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ - #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ - #define MXC_R_TMR_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ - #define MXC_R_TMR_CTRL0 ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ - #define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: 0x0014 */ - #define MXC_R_TMR_CTRL1 ((uint32_t)0x00000018UL) /**< Offset from TMR Base Address: 0x0018 */ - #define MXC_R_TMR_WKFL ((uint32_t)0x0000001CUL) /**< Offset from TMR Base Address: 0x001C */ +#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: 0x0000 */ +#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ +#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ +#define MXC_R_TMR_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ +#define MXC_R_TMR_CTRL0 ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ +#define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: 0x0014 */ +#define MXC_R_TMR_CTRL1 ((uint32_t)0x00000018UL) /**< Offset from TMR Base Address: 0x0018 */ +#define MXC_R_TMR_WKFL ((uint32_t)0x0000001CUL) /**< Offset from TMR Base Address: 0x001C */ /**@} end of group tmr_registers */ /** @@ -116,8 +116,8 @@ * @brief Timer Counter Register. * @{ */ - #define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ - #define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ +#define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ +#define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ /**@} end of group TMR_CNT_Register */ @@ -127,8 +127,8 @@ * @brief Timer Compare Register. * @{ */ - #define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ - #define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ +#define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ +#define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ /**@} end of group TMR_CMP_Register */ @@ -138,8 +138,8 @@ * @brief Timer PWM Register. * @{ */ - #define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ - #define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */ +#define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ +#define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */ /**@} end of group TMR_PWM_Register */ @@ -149,23 +149,23 @@ * @brief Timer Interrupt Status Register. * @{ */ - #define MXC_F_TMR_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */ - #define MXC_F_TMR_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */ +#define MXC_F_TMR_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */ +#define MXC_F_TMR_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */ - #define MXC_F_TMR_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */ - #define MXC_F_TMR_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */ +#define MXC_F_TMR_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */ +#define MXC_F_TMR_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */ - #define MXC_F_TMR_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */ - #define MXC_F_TMR_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */ +#define MXC_F_TMR_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */ +#define MXC_F_TMR_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */ - #define MXC_F_TMR_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */ - #define MXC_F_TMR_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */ +#define MXC_F_TMR_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */ +#define MXC_F_TMR_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */ - #define MXC_F_TMR_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */ - #define MXC_F_TMR_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */ +#define MXC_F_TMR_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */ +#define MXC_F_TMR_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */ - #define MXC_F_TMR_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */ - #define MXC_F_TMR_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */ +#define MXC_F_TMR_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */ +#define MXC_F_TMR_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */ /**@} end of group TMR_INTFL_Register */ @@ -175,157 +175,157 @@ * @brief Timer Control Register. * @{ */ - #define MXC_F_TMR_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */ - #define MXC_F_TMR_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */ - #define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */ - #define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */ - #define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */ - #define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */ - #define MXC_V_TMR_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */ - #define MXC_S_TMR_CTRL0_MODE_A_COUNTER (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */ - #define MXC_V_TMR_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */ - #define MXC_S_TMR_CTRL0_MODE_A_PWM (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */ - #define MXC_V_TMR_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */ - #define MXC_S_TMR_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */ - #define MXC_V_TMR_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */ - #define MXC_S_TMR_CTRL0_MODE_A_COMPARE (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */ - #define MXC_V_TMR_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */ - #define MXC_S_TMR_CTRL0_MODE_A_GATED (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */ - #define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */ - #define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */ - #define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */ - #define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */ - #define MXC_V_TMR_CTRL0_MODE_A_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_A_IGATED Value */ - #define MXC_S_TMR_CTRL0_MODE_A_IGATED (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */ +#define MXC_F_TMR_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */ +#define MXC_F_TMR_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */ +#define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */ +#define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */ +#define MXC_S_TMR_CTRL0_MODE_A_COUNTER (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */ +#define MXC_S_TMR_CTRL0_MODE_A_PWM (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_COMPARE (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */ +#define MXC_S_TMR_CTRL0_MODE_A_GATED (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_A_IGATED Value */ +#define MXC_S_TMR_CTRL0_MODE_A_IGATED (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */ - #define MXC_F_TMR_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */ - #define MXC_F_TMR_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */ +#define MXC_F_TMR_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */ +#define MXC_F_TMR_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */ - #define MXC_F_TMR_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */ - #define MXC_F_TMR_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */ +#define MXC_F_TMR_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */ +#define MXC_F_TMR_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */ - #define MXC_F_TMR_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */ - #define MXC_F_TMR_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */ +#define MXC_F_TMR_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */ +#define MXC_F_TMR_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */ - #define MXC_F_TMR_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */ - #define MXC_F_TMR_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */ +#define MXC_F_TMR_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */ +#define MXC_F_TMR_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */ - #define MXC_F_TMR_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */ - #define MXC_F_TMR_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */ +#define MXC_F_TMR_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */ +#define MXC_F_TMR_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */ - #define MXC_F_TMR_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */ - #define MXC_F_TMR_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */ +#define MXC_F_TMR_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */ +#define MXC_F_TMR_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */ - #define MXC_F_TMR_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */ - #define MXC_F_TMR_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */ +#define MXC_F_TMR_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */ +#define MXC_F_TMR_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */ - #define MXC_F_TMR_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */ - #define MXC_F_TMR_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */ +#define MXC_F_TMR_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */ +#define MXC_F_TMR_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */ - #define MXC_F_TMR_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */ - #define MXC_F_TMR_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */ +#define MXC_F_TMR_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */ +#define MXC_F_TMR_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */ - #define MXC_F_TMR_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */ - #define MXC_F_TMR_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */ - #define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */ - #define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */ - #define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */ - #define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */ - #define MXC_V_TMR_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */ - #define MXC_S_TMR_CTRL0_MODE_B_COUNTER (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */ - #define MXC_V_TMR_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */ - #define MXC_S_TMR_CTRL0_MODE_B_PWM (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */ - #define MXC_V_TMR_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */ - #define MXC_S_TMR_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */ - #define MXC_V_TMR_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */ - #define MXC_S_TMR_CTRL0_MODE_B_COMPARE (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */ - #define MXC_V_TMR_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */ - #define MXC_S_TMR_CTRL0_MODE_B_GATED (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */ - #define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */ - #define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */ - #define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */ - #define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */ - #define MXC_V_TMR_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */ - #define MXC_S_TMR_CTRL0_MODE_B_IGATED (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */ +#define MXC_F_TMR_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */ +#define MXC_F_TMR_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */ +#define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */ +#define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */ +#define MXC_S_TMR_CTRL0_MODE_B_COUNTER (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */ +#define MXC_S_TMR_CTRL0_MODE_B_PWM (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_COMPARE (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */ +#define MXC_S_TMR_CTRL0_MODE_B_GATED (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */ +#define MXC_S_TMR_CTRL0_MODE_B_IGATED (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */ - #define MXC_F_TMR_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */ - #define MXC_F_TMR_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */ - #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */ - #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */ +#define MXC_F_TMR_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */ +#define MXC_F_TMR_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */ - #define MXC_F_TMR_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */ - #define MXC_F_TMR_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */ +#define MXC_F_TMR_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */ +#define MXC_F_TMR_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */ - #define MXC_F_TMR_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */ - #define MXC_F_TMR_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */ +#define MXC_F_TMR_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */ +#define MXC_F_TMR_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */ - #define MXC_F_TMR_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */ - #define MXC_F_TMR_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */ +#define MXC_F_TMR_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */ +#define MXC_F_TMR_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */ - #define MXC_F_TMR_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */ - #define MXC_F_TMR_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */ +#define MXC_F_TMR_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */ +#define MXC_F_TMR_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */ - #define MXC_F_TMR_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */ - #define MXC_F_TMR_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */ +#define MXC_F_TMR_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */ +#define MXC_F_TMR_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */ - #define MXC_F_TMR_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */ - #define MXC_F_TMR_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */ +#define MXC_F_TMR_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */ +#define MXC_F_TMR_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */ - #define MXC_F_TMR_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */ - #define MXC_F_TMR_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */ +#define MXC_F_TMR_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */ +#define MXC_F_TMR_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */ - #define MXC_F_TMR_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */ - #define MXC_F_TMR_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */ +#define MXC_F_TMR_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */ +#define MXC_F_TMR_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */ /**@} end of group TMR_CTRL0_Register */ @@ -335,17 +335,17 @@ * @brief Timer Non-Overlapping Compare Register. * @{ */ - #define MXC_F_TMR_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */ - #define MXC_F_TMR_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */ +#define MXC_F_TMR_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */ +#define MXC_F_TMR_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */ - #define MXC_F_TMR_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */ - #define MXC_F_TMR_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */ +#define MXC_F_TMR_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */ +#define MXC_F_TMR_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */ - #define MXC_F_TMR_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */ - #define MXC_F_TMR_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */ +#define MXC_F_TMR_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */ +#define MXC_F_TMR_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */ - #define MXC_F_TMR_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */ - #define MXC_F_TMR_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */ +#define MXC_F_TMR_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */ +#define MXC_F_TMR_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */ /**@} end of group TMR_NOLCMP_Register */ @@ -355,68 +355,68 @@ * @brief Timer Configuration Register. * @{ */ - #define MXC_F_TMR_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */ - #define MXC_F_TMR_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */ +#define MXC_F_TMR_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */ +#define MXC_F_TMR_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */ - #define MXC_F_TMR_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */ - #define MXC_F_TMR_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */ +#define MXC_F_TMR_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */ +#define MXC_F_TMR_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */ - #define MXC_F_TMR_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */ - #define MXC_F_TMR_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */ +#define MXC_F_TMR_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */ +#define MXC_F_TMR_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */ - #define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */ - #define MXC_F_TMR_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */ +#define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */ +#define MXC_F_TMR_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */ - #define MXC_F_TMR_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */ - #define MXC_F_TMR_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */ +#define MXC_F_TMR_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */ +#define MXC_F_TMR_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */ - #define MXC_F_TMR_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */ - #define MXC_F_TMR_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */ +#define MXC_F_TMR_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */ +#define MXC_F_TMR_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */ - #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */ - #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */ +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */ +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */ - #define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */ - #define MXC_F_TMR_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */ +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */ +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */ - #define MXC_F_TMR_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */ - #define MXC_F_TMR_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */ +#define MXC_F_TMR_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */ +#define MXC_F_TMR_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */ - #define MXC_F_TMR_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */ - #define MXC_F_TMR_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */ +#define MXC_F_TMR_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */ +#define MXC_F_TMR_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */ - #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ - #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ +#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ +#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ - #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ - #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ +#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ +#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ - #define MXC_F_TMR_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */ - #define MXC_F_TMR_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */ +#define MXC_F_TMR_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */ +#define MXC_F_TMR_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */ - #define MXC_F_TMR_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */ - #define MXC_F_TMR_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */ +#define MXC_F_TMR_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */ +#define MXC_F_TMR_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */ - #define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */ - #define MXC_F_TMR_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */ +#define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */ +#define MXC_F_TMR_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */ - #define MXC_F_TMR_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */ - #define MXC_F_TMR_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */ +#define MXC_F_TMR_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */ +#define MXC_F_TMR_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */ - #define MXC_F_TMR_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */ - #define MXC_F_TMR_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */ +#define MXC_F_TMR_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */ +#define MXC_F_TMR_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */ - #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */ - #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */ +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */ +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */ - #define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */ - #define MXC_F_TMR_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */ +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */ +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */ - #define MXC_F_TMR_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */ - #define MXC_F_TMR_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */ +#define MXC_F_TMR_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */ +#define MXC_F_TMR_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */ - #define MXC_F_TMR_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */ - #define MXC_F_TMR_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */ +#define MXC_F_TMR_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */ +#define MXC_F_TMR_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */ /**@} end of group TMR_CTRL1_Register */ @@ -426,11 +426,11 @@ * @brief Timer Wakeup Status Register. * @{ */ - #define MXC_F_TMR_WKFL_A_POS 0 /**< WKFL_A Position */ - #define MXC_F_TMR_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_A_POS)) /**< WKFL_A Mask */ +#define MXC_F_TMR_WKFL_A_POS 0 /**< WKFL_A Position */ +#define MXC_F_TMR_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_A_POS)) /**< WKFL_A Mask */ - #define MXC_F_TMR_WKFL_B_POS 16 /**< WKFL_B Position */ - #define MXC_F_TMR_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_B_POS)) /**< WKFL_B Mask */ +#define MXC_F_TMR_WKFL_B_POS 16 /**< WKFL_B Position */ +#define MXC_F_TMR_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_B_POS)) /**< WKFL_B Mask */ /**@} end of group TMR_WKFL_Register */ @@ -438,4 +438,4 @@ } #endif -#endif /* _TMR_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TMR_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h index 6d5caba..d7aeb41 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h @@ -1,10 +1,11 @@ /** * @file trng_regs.h * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _TRNG_REGS_H_ -#define _TRNG_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TRNG_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TRNG_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup trng * @defgroup trng_registers TRNG_Registers * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. - * @details Random Number Generator. + * @details Random Number Generator. */ /** @@ -84,7 +84,7 @@ */ typedef struct { __IO uint32_t ctrl; /**< \b 0x00: TRNG CTRL Register */ - __I uint32_t status; /**< \b 0x04: TRNG STATUS Register */ + __IO uint32_t status; /**< \b 0x04: TRNG STATUS Register */ __I uint32_t data; /**< \b 0x08: TRNG DATA Register */ } mxc_trng_regs_t; @@ -92,12 +92,12 @@ /** * @ingroup trng_registers * @defgroup TRNG_Register_Offsets Register Offsets - * @brief TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address. + * @brief TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address. * @{ */ - #define MXC_R_TRNG_CTRL ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: 0x0000 */ - #define MXC_R_TRNG_STATUS ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: 0x0004 */ - #define MXC_R_TRNG_DATA ((uint32_t)0x00000008UL) /**< Offset from TRNG Base Address: 0x0008 */ +#define MXC_R_TRNG_CTRL ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: 0x0000 */ +#define MXC_R_TRNG_STATUS ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: 0x0004 */ +#define MXC_R_TRNG_DATA ((uint32_t)0x00000008UL) /**< Offset from TRNG Base Address: 0x0008 */ /**@} end of group trng_registers */ /** @@ -106,14 +106,23 @@ * @brief TRNG Control Register. * @{ */ - #define MXC_F_TRNG_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */ - #define MXC_F_TRNG_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */ +#define MXC_F_TRNG_CTRL_ODHT_POS 0 /**< CTRL_ODHT Position */ +#define MXC_F_TRNG_CTRL_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ODHT_POS)) /**< CTRL_ODHT Mask */ - #define MXC_F_TRNG_CTRL_KEYGEN_POS 3 /**< CTRL_KEYGEN Position */ - #define MXC_F_TRNG_CTRL_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYGEN_POS)) /**< CTRL_KEYGEN Mask */ +#define MXC_F_TRNG_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */ +#define MXC_F_TRNG_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */ - #define MXC_F_TRNG_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */ - #define MXC_F_TRNG_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */ +#define MXC_F_TRNG_CTRL_HEALTH_EN_POS 2 /**< CTRL_HEALTH_EN Position */ +#define MXC_F_TRNG_CTRL_HEALTH_EN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_HEALTH_EN_POS)) /**< CTRL_HEALTH_EN Mask */ + +#define MXC_F_TRNG_CTRL_AESKG_USR_POS 3 /**< CTRL_AESKG_USR Position */ +#define MXC_F_TRNG_CTRL_AESKG_USR ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_USR_POS)) /**< CTRL_AESKG_USR Mask */ + +#define MXC_F_TRNG_CTRL_AESKG_SYS_POS 4 /**< CTRL_AESKG_SYS Position */ +#define MXC_F_TRNG_CTRL_AESKG_SYS ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_SYS_POS)) /**< CTRL_AESKG_SYS Mask */ + +#define MXC_F_TRNG_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */ +#define MXC_F_TRNG_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */ /**@} end of group TRNG_CTRL_Register */ @@ -124,8 +133,23 @@ * disabled, read returns 0x0000 0000. * @{ */ - #define MXC_F_TRNG_STATUS_RDY_POS 0 /**< STATUS_RDY Position */ - #define MXC_F_TRNG_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */ +#define MXC_F_TRNG_STATUS_RDY_POS 0 /**< STATUS_RDY Position */ +#define MXC_F_TRNG_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */ + +#define MXC_F_TRNG_STATUS_ODHT_POS 1 /**< STATUS_ODHT Position */ +#define MXC_F_TRNG_STATUS_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ODHT_POS)) /**< STATUS_ODHT Mask */ + +#define MXC_F_TRNG_STATUS_HT_POS 2 /**< STATUS_HT Position */ +#define MXC_F_TRNG_STATUS_HT ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HT_POS)) /**< STATUS_HT Mask */ + +#define MXC_F_TRNG_STATUS_SRCFAIL_POS 3 /**< STATUS_SRCFAIL Position */ +#define MXC_F_TRNG_STATUS_SRCFAIL ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_SRCFAIL_POS)) /**< STATUS_SRCFAIL Mask */ + +#define MXC_F_TRNG_STATUS_AESKGD_POS 4 /**< STATUS_AESKGD Position */ +#define MXC_F_TRNG_STATUS_AESKGD ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AESKGD_POS)) /**< STATUS_AESKGD Mask */ + +#define MXC_F_TRNG_STATUS_LD_CNT_POS 24 /**< STATUS_LD_CNT Position */ +#define MXC_F_TRNG_STATUS_LD_CNT ((uint32_t)(0xFFUL << MXC_F_TRNG_STATUS_LD_CNT_POS)) /**< STATUS_LD_CNT Mask */ /**@} end of group TRNG_STATUS_Register */ @@ -136,8 +160,8 @@ * disabled, read returns 0x0000 0000. * @{ */ - #define MXC_F_TRNG_DATA_DATA_POS 0 /**< DATA_DATA Position */ - #define MXC_F_TRNG_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_DATA_POS)) /**< DATA_DATA Mask */ +#define MXC_F_TRNG_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_TRNG_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_DATA_POS)) /**< DATA_DATA Mask */ /**@} end of group TRNG_DATA_Register */ @@ -145,4 +169,4 @@ } #endif -#endif /* _TRNG_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TRNG_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h index 3b6c3c3..5a5f534 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h @@ -1,10 +1,11 @@ /** * @file uart_regs.h * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _UART_REGS_H_ -#define _UART_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_UART_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_UART_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup uart * @defgroup uart_registers UART_Registers * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. - * @details UART Low Power Registers + * @details UART Low Power Registers */ /** @@ -102,21 +102,21 @@ /** * @ingroup uart_registers * @defgroup UART_Register_Offsets Register Offsets - * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. + * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. * @{ */ - #define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ - #define MXC_R_UART_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ - #define MXC_R_UART_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ - #define MXC_R_UART_INT_FL ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ - #define MXC_R_UART_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ - #define MXC_R_UART_OSR ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ - #define MXC_R_UART_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ - #define MXC_R_UART_PNR ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: 0x001C */ - #define MXC_R_UART_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: 0x0020 */ - #define MXC_R_UART_DMA ((uint32_t)0x00000030UL) /**< Offset from UART Base Address: 0x0030 */ - #define MXC_R_UART_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART Base Address: 0x0034 */ - #define MXC_R_UART_WKFL ((uint32_t)0x00000038UL) /**< Offset from UART Base Address: 0x0038 */ +#define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ +#define MXC_R_UART_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ +#define MXC_R_UART_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ +#define MXC_R_UART_INT_FL ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ +#define MXC_R_UART_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ +#define MXC_R_UART_OSR ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ +#define MXC_R_UART_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ +#define MXC_R_UART_PNR ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: 0x001C */ +#define MXC_R_UART_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: 0x0020 */ +#define MXC_R_UART_DMA ((uint32_t)0x00000030UL) /**< Offset from UART Base Address: 0x0030 */ +#define MXC_R_UART_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART Base Address: 0x0034 */ +#define MXC_R_UART_WKFL ((uint32_t)0x00000038UL) /**< Offset from UART Base Address: 0x0038 */ /**@} end of group uart_registers */ /** @@ -125,75 +125,75 @@ * @brief Control register * @{ */ - #define MXC_F_UART_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */ - #define MXC_F_UART_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */ +#define MXC_F_UART_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */ +#define MXC_F_UART_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */ - #define MXC_F_UART_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */ - #define MXC_F_UART_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */ +#define MXC_F_UART_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */ +#define MXC_F_UART_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */ - #define MXC_F_UART_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */ - #define MXC_F_UART_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */ +#define MXC_F_UART_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */ +#define MXC_F_UART_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */ - #define MXC_F_UART_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */ - #define MXC_F_UART_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */ +#define MXC_F_UART_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */ +#define MXC_F_UART_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */ - #define MXC_F_UART_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */ - #define MXC_F_UART_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */ +#define MXC_F_UART_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */ +#define MXC_F_UART_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */ - #define MXC_F_UART_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */ - #define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ +#define MXC_F_UART_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */ +#define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ - #define MXC_F_UART_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */ - #define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ +#define MXC_F_UART_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */ +#define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ - #define MXC_F_UART_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */ - #define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ - #define MXC_V_UART_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */ - #define MXC_S_UART_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */ - #define MXC_V_UART_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */ - #define MXC_S_UART_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */ - #define MXC_V_UART_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */ - #define MXC_S_UART_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */ - #define MXC_V_UART_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */ - #define MXC_S_UART_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */ +#define MXC_F_UART_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */ +#define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ +#define MXC_V_UART_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */ +#define MXC_V_UART_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */ +#define MXC_V_UART_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */ +#define MXC_V_UART_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */ - #define MXC_F_UART_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */ - #define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ +#define MXC_F_UART_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */ +#define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ - #define MXC_F_UART_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */ - #define MXC_F_UART_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */ +#define MXC_F_UART_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */ +#define MXC_F_UART_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */ - #define MXC_F_UART_CTRL_RTSDC_POS 14 /**< CTRL_RTSDC Position */ - #define MXC_F_UART_CTRL_RTSDC ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */ +#define MXC_F_UART_CTRL_RTSDC_POS 14 /**< CTRL_RTSDC Position */ +#define MXC_F_UART_CTRL_RTSDC ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */ - #define MXC_F_UART_CTRL_BCLKEN_POS 15 /**< CTRL_BCLKEN Position */ - #define MXC_F_UART_CTRL_BCLKEN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */ +#define MXC_F_UART_CTRL_BCLKEN_POS 15 /**< CTRL_BCLKEN Position */ +#define MXC_F_UART_CTRL_BCLKEN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */ - #define MXC_F_UART_CTRL_BCLKSRC_POS 16 /**< CTRL_BCLKSRC Position */ - #define MXC_F_UART_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */ - #define MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */ - #define MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */ - #define MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Value */ - #define MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Setting */ - #define MXC_V_UART_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */ - #define MXC_S_UART_CTRL_BCLKSRC_CLK2 (MXC_V_UART_CTRL_BCLKSRC_CLK2 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */ - #define MXC_V_UART_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */ - #define MXC_S_UART_CTRL_BCLKSRC_CLK3 (MXC_V_UART_CTRL_BCLKSRC_CLK3 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */ +#define MXC_F_UART_CTRL_BCLKSRC_POS 16 /**< CTRL_BCLKSRC Position */ +#define MXC_F_UART_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */ +#define MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */ +#define MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */ +#define MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Value */ +#define MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Setting */ +#define MXC_V_UART_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */ +#define MXC_S_UART_CTRL_BCLKSRC_CLK2 (MXC_V_UART_CTRL_BCLKSRC_CLK2 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */ +#define MXC_V_UART_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */ +#define MXC_S_UART_CTRL_BCLKSRC_CLK3 (MXC_V_UART_CTRL_BCLKSRC_CLK3 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */ - #define MXC_F_UART_CTRL_DPFE_EN_POS 18 /**< CTRL_DPFE_EN Position */ - #define MXC_F_UART_CTRL_DPFE_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */ +#define MXC_F_UART_CTRL_DPFE_EN_POS 18 /**< CTRL_DPFE_EN Position */ +#define MXC_F_UART_CTRL_DPFE_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */ - #define MXC_F_UART_CTRL_BCLKRDY_POS 19 /**< CTRL_BCLKRDY Position */ - #define MXC_F_UART_CTRL_BCLKRDY ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */ +#define MXC_F_UART_CTRL_BCLKRDY_POS 19 /**< CTRL_BCLKRDY Position */ +#define MXC_F_UART_CTRL_BCLKRDY ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */ - #define MXC_F_UART_CTRL_UCAGM_POS 20 /**< CTRL_UCAGM Position */ - #define MXC_F_UART_CTRL_UCAGM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */ +#define MXC_F_UART_CTRL_UCAGM_POS 20 /**< CTRL_UCAGM Position */ +#define MXC_F_UART_CTRL_UCAGM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */ - #define MXC_F_UART_CTRL_FDM_POS 21 /**< CTRL_FDM Position */ - #define MXC_F_UART_CTRL_FDM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FDM_POS)) /**< CTRL_FDM Mask */ +#define MXC_F_UART_CTRL_FDM_POS 21 /**< CTRL_FDM Position */ +#define MXC_F_UART_CTRL_FDM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FDM_POS)) /**< CTRL_FDM Mask */ - #define MXC_F_UART_CTRL_DESM_POS 22 /**< CTRL_DESM Position */ - #define MXC_F_UART_CTRL_DESM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DESM_POS)) /**< CTRL_DESM Mask */ +#define MXC_F_UART_CTRL_DESM_POS 22 /**< CTRL_DESM Position */ +#define MXC_F_UART_CTRL_DESM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DESM_POS)) /**< CTRL_DESM Mask */ /**@} end of group UART_CTRL_Register */ @@ -203,29 +203,29 @@ * @brief Status register * @{ */ - #define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ - #define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ +#define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ +#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ - #define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ - #define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ +#define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ +#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ - #define MXC_F_UART_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */ - #define MXC_F_UART_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ +#define MXC_F_UART_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */ +#define MXC_F_UART_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ - #define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ - #define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ +#define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ +#define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ - #define MXC_F_UART_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */ - #define MXC_F_UART_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ +#define MXC_F_UART_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */ +#define MXC_F_UART_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ - #define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ - #define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ +#define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ +#define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ - #define MXC_F_UART_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */ - #define MXC_F_UART_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */ +#define MXC_F_UART_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */ +#define MXC_F_UART_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */ - #define MXC_F_UART_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */ - #define MXC_F_UART_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */ +#define MXC_F_UART_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */ +#define MXC_F_UART_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */ /**@} end of group UART_STATUS_Register */ @@ -235,23 +235,23 @@ * @brief Interrupt Enable control register * @{ */ - #define MXC_F_UART_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */ - #define MXC_F_UART_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */ +#define MXC_F_UART_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */ +#define MXC_F_UART_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */ - #define MXC_F_UART_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */ - #define MXC_F_UART_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */ +#define MXC_F_UART_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */ +#define MXC_F_UART_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */ - #define MXC_F_UART_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */ - #define MXC_F_UART_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */ +#define MXC_F_UART_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */ +#define MXC_F_UART_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */ - #define MXC_F_UART_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */ - #define MXC_F_UART_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */ +#define MXC_F_UART_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */ +#define MXC_F_UART_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */ - #define MXC_F_UART_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */ - #define MXC_F_UART_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */ +#define MXC_F_UART_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */ +#define MXC_F_UART_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */ - #define MXC_F_UART_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */ - #define MXC_F_UART_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */ +#define MXC_F_UART_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */ +#define MXC_F_UART_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */ /**@} end of group UART_INT_EN_Register */ @@ -261,23 +261,23 @@ * @brief Interrupt status flags Control register * @{ */ - #define MXC_F_UART_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */ - #define MXC_F_UART_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */ +#define MXC_F_UART_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */ +#define MXC_F_UART_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */ - #define MXC_F_UART_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */ - #define MXC_F_UART_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */ +#define MXC_F_UART_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */ +#define MXC_F_UART_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */ - #define MXC_F_UART_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */ - #define MXC_F_UART_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */ +#define MXC_F_UART_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */ +#define MXC_F_UART_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */ - #define MXC_F_UART_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */ - #define MXC_F_UART_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */ +#define MXC_F_UART_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */ +#define MXC_F_UART_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */ - #define MXC_F_UART_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */ - #define MXC_F_UART_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */ +#define MXC_F_UART_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */ +#define MXC_F_UART_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */ - #define MXC_F_UART_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */ - #define MXC_F_UART_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */ +#define MXC_F_UART_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */ +#define MXC_F_UART_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */ /**@} end of group UART_INT_FL_Register */ @@ -287,8 +287,8 @@ * @brief Clock Divider register * @{ */ - #define MXC_F_UART_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ - #define MXC_F_UART_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ +#define MXC_F_UART_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_UART_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ /**@} end of group UART_CLKDIV_Register */ @@ -298,8 +298,8 @@ * @brief Over Sampling Rate register * @{ */ - #define MXC_F_UART_OSR_OSR_POS 0 /**< OSR_OSR Position */ - #define MXC_F_UART_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_OSR_OSR_POS)) /**< OSR_OSR Mask */ +#define MXC_F_UART_OSR_OSR_POS 0 /**< OSR_OSR Position */ +#define MXC_F_UART_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_OSR_OSR_POS)) /**< OSR_OSR Mask */ /**@} end of group UART_OSR_Register */ @@ -309,8 +309,8 @@ * @brief TX FIFO Output Peek register * @{ */ - #define MXC_F_UART_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */ - #define MXC_F_UART_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */ +#define MXC_F_UART_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */ +#define MXC_F_UART_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */ /**@} end of group UART_TXPEEK_Register */ @@ -320,11 +320,11 @@ * @brief Pin register * @{ */ - #define MXC_F_UART_PNR_CTS_POS 0 /**< PNR_CTS Position */ - #define MXC_F_UART_PNR_CTS ((uint32_t)(0x1UL << MXC_F_UART_PNR_CTS_POS)) /**< PNR_CTS Mask */ +#define MXC_F_UART_PNR_CTS_POS 0 /**< PNR_CTS Position */ +#define MXC_F_UART_PNR_CTS ((uint32_t)(0x1UL << MXC_F_UART_PNR_CTS_POS)) /**< PNR_CTS Mask */ - #define MXC_F_UART_PNR_RTS_POS 1 /**< PNR_RTS Position */ - #define MXC_F_UART_PNR_RTS ((uint32_t)(0x1UL << MXC_F_UART_PNR_RTS_POS)) /**< PNR_RTS Mask */ +#define MXC_F_UART_PNR_RTS_POS 1 /**< PNR_RTS Position */ +#define MXC_F_UART_PNR_RTS ((uint32_t)(0x1UL << MXC_F_UART_PNR_RTS_POS)) /**< PNR_RTS Mask */ /**@} end of group UART_PNR_Register */ @@ -334,11 +334,11 @@ * @brief FIFO Read/Write register * @{ */ - #define MXC_F_UART_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ - #define MXC_F_UART_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ +#define MXC_F_UART_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_UART_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ - #define MXC_F_UART_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */ - #define MXC_F_UART_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */ +#define MXC_F_UART_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */ +#define MXC_F_UART_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */ /**@} end of group UART_FIFO_Register */ @@ -348,17 +348,17 @@ * @brief DMA Configuration register * @{ */ - #define MXC_F_UART_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ - #define MXC_F_UART_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ +#define MXC_F_UART_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ +#define MXC_F_UART_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ - #define MXC_F_UART_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */ - #define MXC_F_UART_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ +#define MXC_F_UART_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */ +#define MXC_F_UART_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ - #define MXC_F_UART_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */ - #define MXC_F_UART_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ +#define MXC_F_UART_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */ +#define MXC_F_UART_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ - #define MXC_F_UART_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */ - #define MXC_F_UART_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ +#define MXC_F_UART_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */ +#define MXC_F_UART_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ /**@} end of group UART_DMA_Register */ @@ -368,14 +368,14 @@ * @brief Wake up enable Control register * @{ */ - #define MXC_F_UART_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */ - #define MXC_F_UART_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */ +#define MXC_F_UART_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */ +#define MXC_F_UART_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */ - #define MXC_F_UART_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */ - #define MXC_F_UART_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ +#define MXC_F_UART_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */ +#define MXC_F_UART_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ - #define MXC_F_UART_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ - #define MXC_F_UART_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ +#define MXC_F_UART_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ +#define MXC_F_UART_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ /**@} end of group UART_WKEN_Register */ @@ -385,14 +385,14 @@ * @brief Wake up Flags register * @{ */ - #define MXC_F_UART_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */ - #define MXC_F_UART_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */ +#define MXC_F_UART_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */ +#define MXC_F_UART_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */ - #define MXC_F_UART_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */ - #define MXC_F_UART_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ +#define MXC_F_UART_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */ +#define MXC_F_UART_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ - #define MXC_F_UART_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ - #define MXC_F_UART_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ +#define MXC_F_UART_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ +#define MXC_F_UART_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ /**@} end of group UART_WKFL_Register */ @@ -400,4 +400,4 @@ } #endif -#endif /* _UART_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_UART_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h index 8c0356f..3a23e1e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h @@ -1,10 +1,11 @@ /** * @file wdt_regs.h * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + * @note This file is @generated. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _WDT_REGS_H_ -#define _WDT_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_WDT_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_WDT_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,7 +75,7 @@ * @ingroup wdt * @defgroup wdt_registers WDT_Registers * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. - * @details Windowed Watchdog Timer + * @details Windowed Watchdog Timer */ /** @@ -93,13 +93,13 @@ /** * @ingroup wdt_registers * @defgroup WDT_Register_Offsets Register Offsets - * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. + * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. * @{ */ - #define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: 0x0000 */ - #define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: 0x0004 */ - #define MXC_R_WDT_CLKSEL ((uint32_t)0x00000008UL) /**< Offset from WDT Base Address: 0x0008 */ - #define MXC_R_WDT_CNT ((uint32_t)0x0000000CUL) /**< Offset from WDT Base Address: 0x000C */ +#define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: 0x0000 */ +#define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: 0x0004 */ +#define MXC_R_WDT_CLKSEL ((uint32_t)0x00000008UL) /**< Offset from WDT Base Address: 0x0008 */ +#define MXC_R_WDT_CNT ((uint32_t)0x0000000CUL) /**< Offset from WDT Base Address: 0x000C */ /**@} end of group wdt_registers */ /** @@ -108,175 +108,175 @@ * @brief Watchdog Timer Control Register. * @{ */ - #define MXC_F_WDT_CTRL_INT_LATE_VAL_POS 0 /**< CTRL_INT_LATE_VAL Position */ - #define MXC_F_WDT_CTRL_INT_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_LATE_VAL_POS)) /**< CTRL_INT_LATE_VAL Mask */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_LATE_VAL_WDT2POW31 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW31 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_LATE_VAL_WDT2POW30 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW30 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_LATE_VAL_WDT2POW29 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW29 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_LATE_VAL_WDT2POW28 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW28 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_LATE_VAL_WDT2POW27 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW27 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_LATE_VAL_WDT2POW26 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW26 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_LATE_VAL_WDT2POW25 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW25 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_LATE_VAL_WDT2POW24 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW24 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_LATE_VAL_WDT2POW23 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW23 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_LATE_VAL_WDT2POW22 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW22 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_LATE_VAL_WDT2POW21 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW21 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_LATE_VAL_WDT2POW20 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW20 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_LATE_VAL_WDT2POW19 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW19 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_LATE_VAL_WDT2POW18 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW18 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_LATE_VAL_WDT2POW17 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW17 Setting */ - #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_LATE_VAL_WDT2POW16 Value */ - #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW16 Setting */ +#define MXC_F_WDT_CTRL_INT_LATE_VAL_POS 0 /**< CTRL_INT_LATE_VAL Position */ +#define MXC_F_WDT_CTRL_INT_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_LATE_VAL_POS)) /**< CTRL_INT_LATE_VAL Mask */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_LATE_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_LATE_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_LATE_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_LATE_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_LATE_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_LATE_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_LATE_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_LATE_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_LATE_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_LATE_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_LATE_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_LATE_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_LATE_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_LATE_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_LATE_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_LATE_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW16 Setting */ - #define MXC_F_WDT_CTRL_RST_LATE_VAL_POS 4 /**< CTRL_RST_LATE_VAL Position */ - #define MXC_F_WDT_CTRL_RST_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_LATE_VAL_POS)) /**< CTRL_RST_LATE_VAL Mask */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_LATE_VAL_WDT2POW31 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW31 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_LATE_VAL_WDT2POW30 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW30 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_LATE_VAL_WDT2POW29 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW29 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_LATE_VAL_WDT2POW28 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW28 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_LATE_VAL_WDT2POW27 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW27 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_LATE_VAL_WDT2POW26 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW26 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_LATE_VAL_WDT2POW25 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW25 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_LATE_VAL_WDT2POW24 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW24 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_LATE_VAL_WDT2POW23 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW23 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_LATE_VAL_WDT2POW22 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW22 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_LATE_VAL_WDT2POW21 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW21 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_LATE_VAL_WDT2POW20 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW20 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_LATE_VAL_WDT2POW19 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW19 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_LATE_VAL_WDT2POW18 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW18 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_LATE_VAL_WDT2POW17 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW17 Setting */ - #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_LATE_VAL_WDT2POW16 Value */ - #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW16 Setting */ +#define MXC_F_WDT_CTRL_RST_LATE_VAL_POS 4 /**< CTRL_RST_LATE_VAL Position */ +#define MXC_F_WDT_CTRL_RST_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_LATE_VAL_POS)) /**< CTRL_RST_LATE_VAL Mask */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_LATE_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_LATE_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_LATE_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_LATE_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_LATE_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_LATE_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_LATE_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_LATE_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_LATE_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_LATE_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_LATE_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_LATE_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_LATE_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_LATE_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_LATE_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_LATE_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW16 Setting */ - #define MXC_F_WDT_CTRL_EN_POS 8 /**< CTRL_EN Position */ - #define MXC_F_WDT_CTRL_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_WDT_CTRL_EN_POS 8 /**< CTRL_EN Position */ +#define MXC_F_WDT_CTRL_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_WDT_CTRL_INT_LATE_POS 9 /**< CTRL_INT_LATE Position */ - #define MXC_F_WDT_CTRL_INT_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_LATE_POS)) /**< CTRL_INT_LATE Mask */ +#define MXC_F_WDT_CTRL_INT_LATE_POS 9 /**< CTRL_INT_LATE Position */ +#define MXC_F_WDT_CTRL_INT_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_LATE_POS)) /**< CTRL_INT_LATE Mask */ - #define MXC_F_WDT_CTRL_WDT_INT_EN_POS 10 /**< CTRL_WDT_INT_EN Position */ - #define MXC_F_WDT_CTRL_WDT_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_INT_EN_POS)) /**< CTRL_WDT_INT_EN Mask */ +#define MXC_F_WDT_CTRL_WDT_INT_EN_POS 10 /**< CTRL_WDT_INT_EN Position */ +#define MXC_F_WDT_CTRL_WDT_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_INT_EN_POS)) /**< CTRL_WDT_INT_EN Mask */ - #define MXC_F_WDT_CTRL_WDT_RST_EN_POS 11 /**< CTRL_WDT_RST_EN Position */ - #define MXC_F_WDT_CTRL_WDT_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_RST_EN_POS)) /**< CTRL_WDT_RST_EN Mask */ +#define MXC_F_WDT_CTRL_WDT_RST_EN_POS 11 /**< CTRL_WDT_RST_EN Position */ +#define MXC_F_WDT_CTRL_WDT_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_RST_EN_POS)) /**< CTRL_WDT_RST_EN Mask */ - #define MXC_F_WDT_CTRL_INT_EARLY_POS 12 /**< CTRL_INT_EARLY Position */ - #define MXC_F_WDT_CTRL_INT_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EARLY_POS)) /**< CTRL_INT_EARLY Mask */ +#define MXC_F_WDT_CTRL_INT_EARLY_POS 12 /**< CTRL_INT_EARLY Position */ +#define MXC_F_WDT_CTRL_INT_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EARLY_POS)) /**< CTRL_INT_EARLY Mask */ - #define MXC_F_WDT_CTRL_INT_EARLY_VAL_POS 16 /**< CTRL_INT_EARLY_VAL Position */ - #define MXC_F_WDT_CTRL_INT_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS)) /**< CTRL_INT_EARLY_VAL Mask */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Setting */ - #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Value */ - #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Setting */ +#define MXC_F_WDT_CTRL_INT_EARLY_VAL_POS 16 /**< CTRL_INT_EARLY_VAL Position */ +#define MXC_F_WDT_CTRL_INT_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS)) /**< CTRL_INT_EARLY_VAL Mask */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Setting */ - #define MXC_F_WDT_CTRL_RST_EARLY_VAL_POS 20 /**< CTRL_RST_EARLY_VAL Position */ - #define MXC_F_WDT_CTRL_RST_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS)) /**< CTRL_RST_EARLY_VAL Mask */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Setting */ - #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Value */ - #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Setting */ +#define MXC_F_WDT_CTRL_RST_EARLY_VAL_POS 20 /**< CTRL_RST_EARLY_VAL Position */ +#define MXC_F_WDT_CTRL_RST_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS)) /**< CTRL_RST_EARLY_VAL Mask */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Setting */ - #define MXC_F_WDT_CTRL_CLKRDY_IE_POS 27 /**< CTRL_CLKRDY_IE Position */ - #define MXC_F_WDT_CTRL_CLKRDY_IE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_IE_POS)) /**< CTRL_CLKRDY_IE Mask */ +#define MXC_F_WDT_CTRL_CLKRDY_IE_POS 27 /**< CTRL_CLKRDY_IE Position */ +#define MXC_F_WDT_CTRL_CLKRDY_IE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_IE_POS)) /**< CTRL_CLKRDY_IE Mask */ - #define MXC_F_WDT_CTRL_CLKRDY_POS 28 /**< CTRL_CLKRDY Position */ - #define MXC_F_WDT_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_POS)) /**< CTRL_CLKRDY Mask */ +#define MXC_F_WDT_CTRL_CLKRDY_POS 28 /**< CTRL_CLKRDY Position */ +#define MXC_F_WDT_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_POS)) /**< CTRL_CLKRDY Mask */ - #define MXC_F_WDT_CTRL_WIN_EN_POS 29 /**< CTRL_WIN_EN Position */ - #define MXC_F_WDT_CTRL_WIN_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WIN_EN_POS)) /**< CTRL_WIN_EN Mask */ +#define MXC_F_WDT_CTRL_WIN_EN_POS 29 /**< CTRL_WIN_EN Position */ +#define MXC_F_WDT_CTRL_WIN_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WIN_EN_POS)) /**< CTRL_WIN_EN Mask */ - #define MXC_F_WDT_CTRL_RST_EARLY_POS 30 /**< CTRL_RST_EARLY Position */ - #define MXC_F_WDT_CTRL_RST_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EARLY_POS)) /**< CTRL_RST_EARLY Mask */ +#define MXC_F_WDT_CTRL_RST_EARLY_POS 30 /**< CTRL_RST_EARLY Position */ +#define MXC_F_WDT_CTRL_RST_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EARLY_POS)) /**< CTRL_RST_EARLY Mask */ - #define MXC_F_WDT_CTRL_RST_LATE_POS 31 /**< CTRL_RST_LATE Position */ - #define MXC_F_WDT_CTRL_RST_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_LATE_POS)) /**< CTRL_RST_LATE Mask */ +#define MXC_F_WDT_CTRL_RST_LATE_POS 31 /**< CTRL_RST_LATE Position */ +#define MXC_F_WDT_CTRL_RST_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_LATE_POS)) /**< CTRL_RST_LATE Mask */ /**@} end of group WDT_CTRL_Register */ @@ -286,12 +286,12 @@ * @brief Windowed Watchdog Timer Reset Register. * @{ */ - #define MXC_F_WDT_RST_RESET_POS 0 /**< RST_RESET Position */ - #define MXC_F_WDT_RST_RESET ((uint32_t)(0xFFUL << MXC_F_WDT_RST_RESET_POS)) /**< RST_RESET Mask */ - #define MXC_V_WDT_RST_RESET_SEQ0 ((uint32_t)0xA5UL) /**< RST_RESET_SEQ0 Value */ - #define MXC_S_WDT_RST_RESET_SEQ0 (MXC_V_WDT_RST_RESET_SEQ0 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ0 Setting */ - #define MXC_V_WDT_RST_RESET_SEQ1 ((uint32_t)0x5AUL) /**< RST_RESET_SEQ1 Value */ - #define MXC_S_WDT_RST_RESET_SEQ1 (MXC_V_WDT_RST_RESET_SEQ1 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ1 Setting */ +#define MXC_F_WDT_RST_RESET_POS 0 /**< RST_RESET Position */ +#define MXC_F_WDT_RST_RESET ((uint32_t)(0xFFUL << MXC_F_WDT_RST_RESET_POS)) /**< RST_RESET Mask */ +#define MXC_V_WDT_RST_RESET_SEQ0 ((uint32_t)0xA5UL) /**< RST_RESET_SEQ0 Value */ +#define MXC_S_WDT_RST_RESET_SEQ0 (MXC_V_WDT_RST_RESET_SEQ0 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ0 Setting */ +#define MXC_V_WDT_RST_RESET_SEQ1 ((uint32_t)0x5AUL) /**< RST_RESET_SEQ1 Value */ +#define MXC_S_WDT_RST_RESET_SEQ1 (MXC_V_WDT_RST_RESET_SEQ1 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ1 Setting */ /**@} end of group WDT_RST_Register */ @@ -301,8 +301,8 @@ * @brief Windowed Watchdog Timer Clock Select Register. * @{ */ - #define MXC_F_WDT_CLKSEL_SOURCE_POS 0 /**< CLKSEL_SOURCE Position */ - #define MXC_F_WDT_CLKSEL_SOURCE ((uint32_t)(0x7UL << MXC_F_WDT_CLKSEL_SOURCE_POS)) /**< CLKSEL_SOURCE Mask */ +#define MXC_F_WDT_CLKSEL_SOURCE_POS 0 /**< CLKSEL_SOURCE Position */ +#define MXC_F_WDT_CLKSEL_SOURCE ((uint32_t)(0x7UL << MXC_F_WDT_CLKSEL_SOURCE_POS)) /**< CLKSEL_SOURCE Mask */ /**@} end of group WDT_CLKSEL_Register */ @@ -312,8 +312,8 @@ * @brief Windowed Watchdog Timer Count Register. * @{ */ - #define MXC_F_WDT_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ - #define MXC_F_WDT_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WDT_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ +#define MXC_F_WDT_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ +#define MXC_F_WDT_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WDT_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ /**@} end of group WDT_CNT_Register */ @@ -321,4 +321,4 @@ } #endif -#endif /* _WDT_REGS_H_ */ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_WDT_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c index d834dfe..ef6abfa 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c @@ -1,5 +1,5 @@ -/******************************************************************************* - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,6 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * ******************************************************************************/ #include @@ -37,9 +36,9 @@ #include #include "max32670.h" #include "gcr_regs.h" +#include "pwrseq_regs.h" #include "mxc_sys.h" - uint32_t SystemCoreClock = HIRC_FREQ; __weak void SystemCoreClockUpdate(void) @@ -48,36 +47,35 @@ // Get the clock source and frequency clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL); - switch (clk_src) - { - case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK: - base_freq = EXTCLK_FREQ; - break; - case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO: - base_freq = ERFO_FREQ; - break; - case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO: - base_freq = INRO_FREQ; - break; - case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO: + switch (clk_src) { + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK: + base_freq = EXTCLK_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO: + base_freq = ERFO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO: + base_freq = INRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO: base_freq = IPO_FREQ; - break; - case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: base_freq = IBRO_FREQ; - break; - case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: - base_freq = ERTCO_FREQ; - break; - default: - // Codes 001 and 111 are reserved. - // This code should never execute, however, initialize to safe value. - base_freq = HIRC_FREQ; - break; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: + base_freq = ERTCO_FREQ; + break; + default: + // Codes 001 and 111 are reserved. + // This code should never execute, however, initialize to safe value. + base_freq = HIRC_FREQ; + break; } // Get the clock divider - if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) - { - base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV)>> MXC_F_GCR_CLKCTRL_IPO_DIV_POS); + if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) { + base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV) >> + MXC_F_GCR_CLKCTRL_IPO_DIV_POS); } div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS; @@ -106,10 +104,9 @@ } /* Override this function for early platform initialization */ -__weak void low_level_init(void) +__weak void low_level_init(void) { /* Do nothing */ - return; } /* This function is called just before control is transferred to main(). @@ -136,8 +133,8 @@ MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); SystemCoreClockUpdate(); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); - + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + low_level_init(); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/crc.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/crc.h index de83cc5..2daae19 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/crc.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/crc.h @@ -3,8 +3,8 @@ * @brief cyclic redundancy check driver. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,11 +33,11 @@ * trademarks, maskwork rights, or any other form of intellectual * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. - * - *************************************************************************** */ + * + ******************************************************************************/ -#ifndef _CRC_H_ -#define _CRC_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_CRC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_CRC_H_ /***** Includes *****/ #include "crc_regs.h" @@ -58,19 +58,16 @@ * */ typedef struct _mxc_crc_req_t { - uint32_t* dataBuffer; ///< Pointer to the data - uint32_t dataLen; ///< Length of the data - uint32_t resultCRC; ///< Calculated CRC value + uint32_t *dataBuffer; ///< Pointer to the data + uint32_t dataLen; ///< Length of the data + uint32_t resultCRC; ///< Calculated CRC value } mxc_crc_req_t; /** * @brief CRC data bit order * */ -typedef enum { - CRC_LSB_FIRST, - CRC_MSB_FIRST -} mxc_crc_bitorder_t; +typedef enum { CRC_LSB_FIRST, CRC_MSB_FIRST } mxc_crc_bitorder_t; /***** Function Prototypes *****/ @@ -84,14 +81,14 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_CRC_Init (void); +int MXC_CRC_Init(void); /** * @brief Disable and reset portions of the CRC * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_CRC_Shutdown (void); +int MXC_CRC_Shutdown(void); /** * @brief This function should be called from the CRC ISR Handler @@ -99,56 +96,56 @@ * @param ch DMA channel * @param error error */ -void MXC_CRC_Handler (int ch, int error); +void MXC_CRC_Handler(int ch, int error); /** * @brief Set the bit-order of CRC calculation * * @param bitOrder The direction to perform CRC calculation in */ -void MXC_CRC_SetDirection (mxc_crc_bitorder_t bitOrder); +void MXC_CRC_SetDirection(mxc_crc_bitorder_t bitOrder); /** * @brief Set the bit-order of CRC calculation * * @return The direction of calculation, 1 for MSB first, 0 for LSB first */ -mxc_crc_bitorder_t MXC_CRC_GetDirection (void); +mxc_crc_bitorder_t MXC_CRC_GetDirection(void); /** * @brief Byte Swap CRC Data Input * * @param bitOrder The direction to perform CRC calculation in */ -void MXC_CRC_SwapDataIn (mxc_crc_bitorder_t bitOrder); +void MXC_CRC_SwapDataIn(mxc_crc_bitorder_t bitOrder); /** * @brief Byte Swap CRC Data output * * @param bitOrder The direction to perform CRC calculation in */ -void MXC_CRC_SwapDataOut (mxc_crc_bitorder_t bitOrder); +void MXC_CRC_SwapDataOut(mxc_crc_bitorder_t bitOrder); /** * @brief Set the Polynomial for CRC calculation * * @param poly The polynomial to use for CRC calculation */ -void MXC_CRC_SetPoly (uint32_t poly); +void MXC_CRC_SetPoly(uint32_t poly); /** * @brief Get the polynomial for CRC calculation * * @return The polynomial used in calculation */ -uint32_t MXC_CRC_GetPoly (void); +uint32_t MXC_CRC_GetPoly(void); /** * @brief Get the result of a CRC calculation * * @return The calculated CRC value */ -uint32_t MXC_CRC_GetResult (void); +uint32_t MXC_CRC_GetResult(void); /*******************************/ /* High Level Functions */ @@ -163,7 +160,7 @@ * * @return see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_CRC_Compute (mxc_crc_req_t* req); +int MXC_CRC_Compute(mxc_crc_req_t *req); /** * @brief Perform a CRC computation using DMA @@ -175,11 +172,11 @@ * * @return see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_CRC_ComputeAsync (mxc_crc_req_t* req); +int MXC_CRC_ComputeAsync(mxc_crc_req_t *req); #ifdef __cplusplus } #endif /**@} end of group crc */ -#endif /* _CRC_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_CRC_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/dma.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/dma.h index 489fa35..59b5d4f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/dma.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/dma.h @@ -3,8 +3,8 @@ * @brief Direct Memory Access (DMA) driver function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,11 +33,11 @@ * trademarks, maskwork rights, or any other form of intellectual * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. - * - *************************************************************************** */ + * + ******************************************************************************/ -#ifndef _DMA_H_ -#define _DMA_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_DMA_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_DMA_H_ /* **** Includes **** */ #include @@ -61,60 +61,69 @@ * */ typedef enum { - MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority */ - MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority */ - MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority */ - MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority */ + MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority */ + MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority */ + MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority */ + MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority */ } mxc_dma_priority_t; /** @brief DMA request select */ typedef enum { - MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection - MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection - MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection - MXC_DMA_REQUEST_SPI2RX = MXC_S_DMA_CTRL_REQUEST_SPI2RX, ///< SPI2 Receive DMA Request Selection - MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection - MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection - MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection - MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection - MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection - MXC_DMA_REQUEST_UART2RX = MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection - MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection - MXC_DMA_REQUEST_UART3RX = MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection - MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection - MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection - MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection - MXC_DMA_REQUEST_SPI2TX = MXC_S_DMA_CTRL_REQUEST_SPI2TX, ///< SPI2 Transmit DMA Request Selection - MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection - MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection - MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection - MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection - MXC_DMA_REQUEST_I2C2TX = MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection - MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection - MXC_DMA_REQUEST_UART2TX = MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection - MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection - MXC_DMA_REQUEST_UART3TX = MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection - MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection + MXC_DMA_REQUEST_MEMTOMEM = + MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection + MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection + MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection + MXC_DMA_REQUEST_SPI2RX = MXC_S_DMA_CTRL_REQUEST_SPI2RX, ///< SPI2 Receive DMA Request Selection + MXC_DMA_REQUEST_UART0RX = + MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection + MXC_DMA_REQUEST_UART1RX = + MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection + MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection + MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection + MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection + MXC_DMA_REQUEST_UART2RX = + MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection + MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection + MXC_DMA_REQUEST_UART3RX = + MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection + MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection + MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection + MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection + MXC_DMA_REQUEST_SPI2TX = MXC_S_DMA_CTRL_REQUEST_SPI2TX, ///< SPI2 Transmit DMA Request Selection + MXC_DMA_REQUEST_UART0TX = + MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection + MXC_DMA_REQUEST_UART1TX = + MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2C2TX = MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection + MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection + MXC_DMA_REQUEST_UART2TX = + MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection + MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection + MXC_DMA_REQUEST_UART3TX = + MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection } mxc_dma_reqsel_t; /** @brief Enumeration for the DMA prescaler */ typedef enum { - MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled - MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256 - MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536 - MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216 + MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled + MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256 + MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536 + MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216 } mxc_dma_prescale_t; /** @brief Enumeration for the DMA timeout value */ typedef enum { - MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks - MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks - MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks - MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks - MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks - MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks - MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks - MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks + MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks + MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks + MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks + MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks + MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks + MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks + MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks + MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks } mxc_dma_timeout_t; /** @brief DMA transfer data width */ @@ -122,9 +131,9 @@ /* Using the '_V_' define instead of the '_S_' since these same values will be used to specify the DSTWD also. The API functions will shift the value the correct amount prior to writing the cfg register. */ - MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes - MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words - MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words + MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes + MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words + MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words } mxc_dma_width_t; /** @@ -133,12 +142,12 @@ * */ typedef struct { - int ch; ///< The channel to load the configuration data into - mxc_dma_reqsel_t reqsel;///< The request select line to be used (mem2mem, peripheral) - mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) - mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) - int srcinc_en; ///< Whether to increment the source address during the transfer - int dstinc_en; ///< Whether to increment the source address during the transfer + int ch; ///< The channel to load the configuration data into + mxc_dma_reqsel_t reqsel; ///< The request select line to be used (mem2mem, peripheral) + mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) + mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) + int srcinc_en; ///< Whether to increment the source address during the transfer + int dstinc_en; ///< Whether to increment the source address during the transfer } mxc_dma_config_t; /** @@ -146,10 +155,10 @@ * */ typedef struct { - int ch; ///< The channel to use for the transfer - void* source; ///< Pointer to the source address, if applicable - void* dest; ///< Pointer to the destination address, if applicable - int len; ///< Number of bytes to transfer + int ch; ///< The channel to use for the transfer + void *source; ///< Pointer to the source address, if applicable + void *dest; ///< Pointer to the destination address, if applicable + int len; ///< Number of bytes to transfer } mxc_dma_srcdst_t; /** @@ -159,12 +168,12 @@ * */ typedef struct { - int ch; ///< The channel to use for the transfer - mxc_dma_priority_t prio; ///< The DMA priority for the channel - unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer - mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout - mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer - unsigned int burst_size; ///< Number of bytes moved in a single burst + int ch; ///< The channel to use for the transfer + mxc_dma_priority_t prio; ///< The DMA priority for the channel + unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer + mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout + mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer + unsigned int burst_size; ///< Number of bytes moved in a single burst } mxc_dma_adv_config_t; /** @@ -172,7 +181,7 @@ * * @param dest Pointer to the destination of the copy */ -typedef void (*mxc_dma_complete_cb_t) (void* dest); +typedef void (*mxc_dma_complete_cb_t)(void *dest); /** * @brief The callback called on completion of a transfer, @@ -185,7 +194,7 @@ * @return Returns the next transfer to be completed, or NULL * if no more transfers will be done */ -typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t) (mxc_dma_srcdst_t dest); +typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); /* **** Function Prototypes **** */ /*************************/ @@ -196,7 +205,7 @@ * @details This initialization is required before using the DMA driver functions. * @return #E_NO_ERROR if successful */ -int MXC_DMA_Init (void); +int MXC_DMA_Init(void); /** * @brief Request DMA channel @@ -207,7 +216,7 @@ * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. * @return #E_BUSY DMA is currently busy (locked), try again later. */ -int MXC_DMA_AcquireChannel (void); +int MXC_DMA_AcquireChannel(void); /** * @brief Release DMA channel @@ -217,7 +226,7 @@ * * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_ReleaseChannel (int ch); +int MXC_DMA_ReleaseChannel(int ch); /** * @brief Configure the DMA channel @@ -228,7 +237,7 @@ * * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_ConfigChannel (mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); +int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); /** * @brief Configure the DMA channel with more advanced parameters @@ -237,7 +246,7 @@ * * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_AdvConfigChannel (mxc_dma_adv_config_t advConfig); +int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); /** * @brief Set channel source, destination, and count for the transfer @@ -248,7 +257,7 @@ * Guide for more information. * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst); +int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst); /** * @brief Get channel source, destination, and count for transfer @@ -257,7 +266,7 @@ * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t* srcdst); +int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst); /** * @brief Set channel reload source, destination, and count for the transfer @@ -268,7 +277,7 @@ * Guide for more information. * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload); +int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload); /** * @brief Get channel reload source, destination, and count for transfer @@ -277,7 +286,7 @@ * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t* srcdstReload); +int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); /** * @brief Set channel interrupt callback @@ -301,7 +310,7 @@ * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR * otherwise */ -int MXC_DMA_SetCallback (int ch, void (*callback) (int, int)); +int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); /** * @brief Set channel interrupt @@ -323,7 +332,7 @@ * @param flags The flags to enable * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_ChannelEnableInt (int ch, int flags); +int MXC_DMA_ChannelEnableInt(int ch, int flags); /** * @brief Disable channel interrupt @@ -331,14 +340,14 @@ * @param flags The flags to disable * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_ChannelDisableInt (int ch, int flags); +int MXC_DMA_ChannelDisableInt(int ch, int flags); /** * @brief Read channel interrupt flags * @param ch channel handle * @return #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise */ -int MXC_DMA_ChannelGetFlags (int ch); +int MXC_DMA_ChannelGetFlags(int ch); /** * @brief Clear channel interrupt flags @@ -346,7 +355,7 @@ * @param flags The flags to clear * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_ChannelClearFlags (int ch, int flags); +int MXC_DMA_ChannelClearFlags(int ch, int flags); /** * @brief Enable channel interrupt @@ -355,14 +364,14 @@ * @param ch channel handle * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_EnableInt (int ch); +int MXC_DMA_EnableInt(int ch); /** * @brief Disable channel interrupt * @param ch channel handle * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_DisableInt (int ch); +int MXC_DMA_DisableInt(int ch); /** * @brief Start transfer @@ -370,14 +379,14 @@ * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_Start (int ch); +int MXC_DMA_Start(int ch); /** * @brief Stop DMA transfer, irrespective of status (complete or in-progress) * @param ch channel handle * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ -int MXC_DMA_Stop (int ch); +int MXC_DMA_Stop(int ch); /** * @brief Get a pointer to the DMA channel registers @@ -386,7 +395,7 @@ * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise */ -mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs (int ch); +mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); /** * @brief Interrupt handler function @@ -411,7 +420,7 @@ * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callback); +int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); /** * @brief Performs a memcpy, using DMA, optionally asynchronous @@ -424,7 +433,8 @@ * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); +int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, + mxc_dma_trans_chain_t callback); /** * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver */ @@ -434,4 +444,4 @@ } #endif -#endif /* _DMA_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_DMA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/flc.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/flc.h index e3e2520..0c16550 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/flc.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/flc.h @@ -4,8 +4,8 @@ * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,10 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _FLC_H_ -#define _FLC_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_FLC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_FLC_H_ /* **** Includes **** */ #include "flc_regs.h" @@ -57,10 +57,10 @@ /***** Definitions *****/ /// Bit mask that can be used to find the starting address of a page in flash -#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) +#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) /// Calculate the address of a page in flash from the page number -#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE)) +#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((uint32_t)page * MXC_FLASH_PAGE_SIZE)) /***** Function Prototypes *****/ @@ -76,14 +76,14 @@ * with an erase or write operation. * @return If non-zero, flash operation is in progress */ -int MXC_FLC_Busy (void); +int MXC_FLC_Busy(void); /** * @brief Erases the entire flash array. * @note This function must be executed from RAM. * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_MassErase (void); +int MXC_FLC_MassErase(void); /** * @brief Erases the page of flash at the specified address. @@ -91,7 +91,7 @@ * @param address Any address within the page to erase. * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_PageErase (uint32_t address); +int MXC_FLC_PageErase(uint32_t address); /** * @brief Read Data out of Flash from an address @@ -101,7 +101,7 @@ * @param[in] len The length of the buffer * */ -void MXC_FLC_Read (int address, void* buffer, int len); +void MXC_FLC_Read(int address, void *buffer, int len); /** * @brief Writes data to flash. @@ -112,7 +112,7 @@ * @return #E_NO_ERROR If function is successful. * @note make sure to disable ICC with ICC_Disable(); before Running this function */ -int MXC_FLC_Write (uint32_t address, uint32_t length, uint32_t *buffer); +int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer); /** * @brief Writes 32 bits of data to flash. @@ -122,7 +122,7 @@ * @return #E_NO_ERROR If function is successful. * @note make sure to disable ICC with ICC_Disable(); before Running this function */ -int MXC_FLC_Write32 (uint32_t address, uint32_t data); +int MXC_FLC_Write32(uint32_t address, uint32_t data); /** * @brief Writes 128 bits of data to flash. @@ -132,27 +132,27 @@ * @return #E_NO_ERROR If function is successful. * @note make sure to disable ICC with ICC_Disable(); before Running this function */ -int MXC_FLC_Write128 (uint32_t address, uint32_t *data); +int MXC_FLC_Write128(uint32_t address, uint32_t *data); /** * @brief Enable flash interrupts * @param flags Interrupts to enable * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_EnableInt (uint32_t flags); +int MXC_FLC_EnableInt(uint32_t flags); /** * @brief Disable flash interrupts * @param flags Interrupts to disable * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_DisableInt (uint32_t flags); +int MXC_FLC_DisableInt(uint32_t flags); /** * @brief Retrieve flash interrupt flags * @return Interrupt flags registers */ -int MXC_FLC_GetFlags (void); +int MXC_FLC_GetFlags(void); /** * @brief Clear flash interrupt flags @@ -160,7 +160,7 @@ * @param flags Flag bit(s) to clear * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_ClearFlags (uint32_t flags); +int MXC_FLC_ClearFlags(uint32_t flags); /** * @brief Unlock info block @@ -169,7 +169,7 @@ * * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_UnlockInfoBlock (uint32_t address); +int MXC_FLC_UnlockInfoBlock(uint32_t address); /** * @brief Lock info block @@ -177,7 +177,27 @@ * @param[in] address The address in the info block that was written to * @return #E_NO_ERROR If function is successful. */ -int MXC_FLC_LockInfoBlock (uint32_t address); +int MXC_FLC_LockInfoBlock(uint32_t address); + +/** + * @brief Blocks write operations to the flash page associated with the 'address' argument + * @note Flash pages cannot be unblocked except for on POR and external resets + * + * @param address Absolute address located anywhere in the flash page to be locked (does not need to be word-aligned) + * + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_BlockPageWrite(uint32_t address); + +/** + * @brief Blocks read operations from the flash page associated with the 'address' argument + * @note Flash pages cannot be unblocked except for on POR and external resets + * + * @param address Absolute address located anywhere in the flash page to be locked (does not need to be word-aligned) + * + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_BlockPageRead(uint32_t address); /**@} end of group flc */ @@ -185,4 +205,4 @@ } #endif -#endif /* _FLC_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_FLC_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/gpio.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/gpio.h index 11c5307..ef9fe57 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/gpio.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/gpio.h @@ -3,8 +3,8 @@ * @brief General-Purpose Input/Output (GPIO) function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _GPIO_H_ -#define _GPIO_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_GPIO_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_GPIO_H_ /* **** Includes **** */ #include "gpio_regs.h" @@ -62,48 +62,48 @@ * @ingroup gpio_port_pin * @{ */ -#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define -#define MXC_GPIO_PORT_1 ((uint32_t)(1UL << 1)) ///< Port 1 Define -#define MXC_GPIO_PORT_2 ((uint32_t)(1UL << 2)) ///< Port 2 Define -#define MXC_GPIO_PORT_3 ((uint32_t)(1UL << 3)) ///< Port 3 Define +#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define +#define MXC_GPIO_PORT_1 ((uint32_t)(1UL << 1)) ///< Port 1 Define +#define MXC_GPIO_PORT_2 ((uint32_t)(1UL << 2)) ///< Port 2 Define +#define MXC_GPIO_PORT_3 ((uint32_t)(1UL << 3)) ///< Port 3 Define /**@} end of gpio_port group*/ /** * @defgroup gpio_pin Pin Definitions * @ingroup gpio_port_pin * @{ */ -#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) ///< Pin 0 Define -#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) ///< Pin 1 Define -#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) ///< Pin 2 Define -#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) ///< Pin 3 Define -#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) ///< Pin 4 Define -#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) ///< Pin 5 Define -#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) ///< Pin 6 Define -#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) ///< Pin 7 Define -#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) ///< Pin 8 Define -#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) ///< Pin 9 Define -#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define -#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define -#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define -#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define -#define MXC_GPIO_PIN_14 ((uint32_t)(1UL << 14)) ///< Pin 14 Define -#define MXC_GPIO_PIN_15 ((uint32_t)(1UL << 15)) ///< Pin 15 Define -#define MXC_GPIO_PIN_16 ((uint32_t)(1UL << 16)) ///< Pin 16 Define -#define MXC_GPIO_PIN_17 ((uint32_t)(1UL << 17)) ///< Pin 17 Define -#define MXC_GPIO_PIN_18 ((uint32_t)(1UL << 18)) ///< Pin 18 Define -#define MXC_GPIO_PIN_19 ((uint32_t)(1UL << 19)) ///< Pin 19 Define -#define MXC_GPIO_PIN_20 ((uint32_t)(1UL << 20)) ///< Pin 20 Define -#define MXC_GPIO_PIN_21 ((uint32_t)(1UL << 21)) ///< Pin 21 Define -#define MXC_GPIO_PIN_22 ((uint32_t)(1UL << 22)) ///< Pin 22 Define -#define MXC_GPIO_PIN_23 ((uint32_t)(1UL << 23)) ///< Pin 23 Define -#define MXC_GPIO_PIN_24 ((uint32_t)(1UL << 24)) ///< Pin 24 Define -#define MXC_GPIO_PIN_25 ((uint32_t)(1UL << 25)) ///< Pin 25 Define -#define MXC_GPIO_PIN_26 ((uint32_t)(1UL << 26)) ///< Pin 26 Define -#define MXC_GPIO_PIN_27 ((uint32_t)(1UL << 27)) ///< Pin 27 Define -#define MXC_GPIO_PIN_28 ((uint32_t)(1UL << 28)) ///< Pin 28 Define -#define MXC_GPIO_PIN_29 ((uint32_t)(1UL << 29)) ///< Pin 29 Define -#define MXC_GPIO_PIN_30 ((uint32_t)(1UL << 30)) ///< Pin 30 Define -#define MXC_GPIO_PIN_31 ((uint32_t)(1UL << 31)) ///< Pin 31 Define +#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) ///< Pin 0 Define +#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) ///< Pin 1 Define +#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) ///< Pin 2 Define +#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) ///< Pin 3 Define +#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) ///< Pin 4 Define +#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) ///< Pin 5 Define +#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) ///< Pin 6 Define +#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) ///< Pin 7 Define +#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) ///< Pin 8 Define +#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) ///< Pin 9 Define +#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define +#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define +#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define +#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define +#define MXC_GPIO_PIN_14 ((uint32_t)(1UL << 14)) ///< Pin 14 Define +#define MXC_GPIO_PIN_15 ((uint32_t)(1UL << 15)) ///< Pin 15 Define +#define MXC_GPIO_PIN_16 ((uint32_t)(1UL << 16)) ///< Pin 16 Define +#define MXC_GPIO_PIN_17 ((uint32_t)(1UL << 17)) ///< Pin 17 Define +#define MXC_GPIO_PIN_18 ((uint32_t)(1UL << 18)) ///< Pin 18 Define +#define MXC_GPIO_PIN_19 ((uint32_t)(1UL << 19)) ///< Pin 19 Define +#define MXC_GPIO_PIN_20 ((uint32_t)(1UL << 20)) ///< Pin 20 Define +#define MXC_GPIO_PIN_21 ((uint32_t)(1UL << 21)) ///< Pin 21 Define +#define MXC_GPIO_PIN_22 ((uint32_t)(1UL << 22)) ///< Pin 22 Define +#define MXC_GPIO_PIN_23 ((uint32_t)(1UL << 23)) ///< Pin 23 Define +#define MXC_GPIO_PIN_24 ((uint32_t)(1UL << 24)) ///< Pin 24 Define +#define MXC_GPIO_PIN_25 ((uint32_t)(1UL << 25)) ///< Pin 25 Define +#define MXC_GPIO_PIN_26 ((uint32_t)(1UL << 26)) ///< Pin 26 Define +#define MXC_GPIO_PIN_27 ((uint32_t)(1UL << 27)) ///< Pin 27 Define +#define MXC_GPIO_PIN_28 ((uint32_t)(1UL << 28)) ///< Pin 28 Define +#define MXC_GPIO_PIN_29 ((uint32_t)(1UL << 29)) ///< Pin 29 Define +#define MXC_GPIO_PIN_30 ((uint32_t)(1UL << 30)) ///< Pin 30 Define +#define MXC_GPIO_PIN_31 ((uint32_t)(1UL << 31)) ///< Pin 31 Define /**@} end of gpio_pin group */ /**@} end of gpio_port_pin group */ @@ -115,65 +115,65 @@ * @param cbdata A void pointer to the data type as registered when * MXC_GPIO_RegisterCallback() was called. */ -typedef void (*mxc_gpio_callback_fn) (void *cbdata); +typedef void (*mxc_gpio_callback_fn)(void *cbdata); /** * @brief Enumeration type for the GPIO Function Type */ typedef enum { - MXC_GPIO_FUNC_IN, ///< GPIO Input - MXC_GPIO_FUNC_OUT, ///< GPIO Output - MXC_GPIO_FUNC_ALT1, ///< Alternate Function Selection - MXC_GPIO_FUNC_ALT2, ///< Alternate Function Selection - MXC_GPIO_FUNC_ALT3, ///< Alternate Function Selection - MXC_GPIO_FUNC_ALT4, ///< Alternate Function Selection + MXC_GPIO_FUNC_IN, ///< GPIO Input + MXC_GPIO_FUNC_OUT, ///< GPIO Output + MXC_GPIO_FUNC_ALT1, ///< Alternate Function Selection + MXC_GPIO_FUNC_ALT2, ///< Alternate Function Selection + MXC_GPIO_FUNC_ALT3, ///< Alternate Function Selection + MXC_GPIO_FUNC_ALT4, ///< Alternate Function Selection } mxc_gpio_func_t; /** * @brief Enumeration type for the voltage level on a given pin. */ typedef enum { - MXC_GPIO_VSSEL_VDDIO, ///< Set pin to VIDDIO voltage - MXC_GPIO_VSSEL_VDDIOH, ///< Set pin to VIDDIOH voltage + MXC_GPIO_VSSEL_VDDIO, ///< Set pin to VIDDIO voltage + MXC_GPIO_VSSEL_VDDIOH, ///< Set pin to VIDDIOH voltage } mxc_gpio_vssel_t; /** * @brief Enumeration type for the type of GPIO pad on a given pin. */ typedef enum { - MXC_GPIO_PAD_NONE, ///< No pull-up or pull-down - MXC_GPIO_PAD_PULL_UP, ///< Set pad to weak pull-up - MXC_GPIO_PAD_PULL_DOWN, ///< Set pad to weak pull-down + MXC_GPIO_PAD_NONE, ///< No pull-up or pull-down + MXC_GPIO_PAD_PULL_UP, ///< Set pad to weak pull-up + MXC_GPIO_PAD_PULL_DOWN, ///< Set pad to weak pull-down } mxc_gpio_pad_t; /** * @brief Structure type for configuring a GPIO port. */ typedef struct { - mxc_gpio_regs_t* port; ///< Pointer to GPIO regs - uint32_t mask; ///< Pin mask (multiple pins may be set) - mxc_gpio_func_t func; ///< Function type - mxc_gpio_pad_t pad; ///< Pad type - mxc_gpio_vssel_t vssel; ///< Voltage select + mxc_gpio_regs_t *port; ///< Pointer to GPIO regs + uint32_t mask; ///< Pin mask (multiple pins may be set) + mxc_gpio_func_t func; ///< Function type + mxc_gpio_pad_t pad; ///< Pad type + mxc_gpio_vssel_t vssel; ///< Voltage select } mxc_gpio_cfg_t; /** * @brief Enumeration type for the interrupt modes. */ typedef enum { - MXC_GPIO_INT_LEVEL, ///< Interrupt is level sensitive - MXC_GPIO_INT_EDGE ///< Interrupt is edge sensitive + MXC_GPIO_INT_LEVEL, ///< Interrupt is level sensitive + MXC_GPIO_INT_EDGE ///< Interrupt is edge sensitive } mxc_gpio_int_mode_t; /** * @brief Enumeration type for the interrupt polarity. */ typedef enum { - MXC_GPIO_INT_FALLING, ///< Interrupt triggers on falling edge - MXC_GPIO_INT_HIGH, ///< Interrupt triggers when level is high - MXC_GPIO_INT_RISING, ///< Interrupt triggers on rising edge - MXC_GPIO_INT_LOW, ///< Interrupt triggers when level is low - MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge + MXC_GPIO_INT_FALLING, ///< Interrupt triggers on falling edge + MXC_GPIO_INT_HIGH, ///< Interrupt triggers when level is high + MXC_GPIO_INT_RISING, ///< Interrupt triggers on rising edge + MXC_GPIO_INT_LOW, ///< Interrupt triggers when level is low + MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; /* **** Function Prototypes **** */ @@ -183,28 +183,28 @@ * @param portMask Mask for the port to be initialized * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_Init (uint32_t portMask); +int MXC_GPIO_Init(uint32_t portMask); /** * @brief Shutdown GPIO. * @param portMask Mask for the port to be initialized * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_Shutdown (uint32_t portMask); +int MXC_GPIO_Shutdown(uint32_t portMask); /** * @brief Reset GPIO. * @param portMask Mask for the port to be initialized * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_Reset (uint32_t portMask); +int MXC_GPIO_Reset(uint32_t portMask); /** * @brief Configure GPIO pin(s). * @param cfg Pointer to configuration structure describing the pin. * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg); +int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg); /** * @brief Gets the pin(s) input state. @@ -212,21 +212,21 @@ * @param mask Mask of the pin to read * @return The requested pin state. */ -uint32_t MXC_GPIO_InGet (mxc_gpio_regs_t* port, uint32_t mask); +uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Sets the pin(s) to a high level output. * @param port Pointer to GPIO port. * @param mask Mask of the pin to set */ -void MXC_GPIO_OutSet (mxc_gpio_regs_t* port, uint32_t mask); +void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Clears the pin(s) to a low level output. * @param port Pointer to GPIO port. * @param mask Mask of the pin to clear */ -void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask); +void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Gets the pin(s) output state. @@ -235,7 +235,7 @@ * @return The state of the requested pin. * */ -uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask); +uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Write the pin(s) to a desired output level. @@ -244,14 +244,14 @@ * @param val Desired output level of the pin(s). This will be masked * with the configuration mask. */ -void MXC_GPIO_OutPut (mxc_gpio_regs_t* port, uint32_t mask, uint32_t val); +void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val); /** * @brief Toggles the the pin(s) output level. * @param port Pointer to GPIO port. * @param mask Mask of the pin to toggle the output */ -void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask); +void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Configure GPIO interrupt(s) @@ -259,7 +259,7 @@ * @param pol Requested interrupt polarity. * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); +int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); /** * @brief Enables the specified GPIO interrupt @@ -267,14 +267,14 @@ * @param mask mask of the pin to enable interrupt * */ -void MXC_GPIO_EnableInt (mxc_gpio_regs_t* port, uint32_t mask); +void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Disables the specified GPIO interrupt. * @param port Pointer to GPIO port. * @param mask mask of the pin to disable interrupt */ -void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask); +void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask); /** * @brief Gets the interrupt(s) status on a GPIO port @@ -283,7 +283,7 @@ * * @return The requested interrupt status. */ -uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port); +uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port); /** * @brief Gets the interrupt(s) status on a GPIO port @@ -291,7 +291,7 @@ * @param port Pointer to GPIO port. * @param flags The flags to clear */ -void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags); +void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags); /** * @brief Registers a callback for the interrupt on a given port and pin. @@ -300,7 +300,8 @@ * @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs. * */ -void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata); +void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, + void *cbdata); /** * @brief GPIO IRQ Handler. @note If a callback is registered for a given @@ -309,7 +310,7 @@ * @param port number of the port that generated the interrupt service routine. * */ -void MXC_GPIO_Handler (unsigned int port); +void MXC_GPIO_Handler(unsigned int port); /** * @brief Set Voltage select for pins to VDDIO or VDDIOH @@ -320,7 +321,7 @@ * * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask); +int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask); /**@} end of group gpio */ @@ -328,4 +329,4 @@ } #endif -#endif /* _GPIO_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_GPIO_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/i2s.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/i2s.h index 9990562..b90e817 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/i2s.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/i2s.h @@ -3,8 +3,8 @@ * @brief I2S (Inter-Integrated Sound) driver function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,10 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _I2S_H_ -#define _I2S_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2S_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2S_H_ /* **** Includes **** */ #include "mxc_sys.h" @@ -58,27 +58,19 @@ /** @brief I2S stereo mode select */ typedef enum { + MXC_I2S_STEREO = 0, MXC_I2S_MONO_LEFT_CH = 2, MXC_I2S_MONO_RIGHT_CH = 3 } mxc_i2s_stereo_t; /** @brief I2S polarity configuration */ -typedef enum { - MXC_I2S_POL_NORMAL, - MXC_I2S_POL_INVERSE -} mxc_i2s_polarity_t; +typedef enum { MXC_I2S_POL_NORMAL, MXC_I2S_POL_INVERSE } mxc_i2s_polarity_t; /** @brief I2S transaction bit order */ -typedef enum { - MXC_I2S_MSB_FIRST, - MXC_I2S_LSB_FIRST -} mxc_i2s_bitorder_t; +typedef enum { MXC_I2S_MSB_FIRST, MXC_I2S_LSB_FIRST } mxc_i2s_bitorder_t; /** @brief I2S transaction justify order */ -typedef enum { - MXC_I2S_MSB_JUSTIFY, - MXC_I2S_LSB_JUSTIFY -} mxc_i2s_justify_t; +typedef enum { MXC_I2S_MSB_JUSTIFY, MXC_I2S_LSB_JUSTIFY } mxc_i2s_justify_t; /** @brief I2S transaction word size */ typedef enum { @@ -106,20 +98,20 @@ /** @brief I2S Configuration Struct */ typedef struct { - mxc_i2s_ch_mode_t channelMode; - mxc_i2s_stereo_t stereoMode; - mxc_i2s_wsize_t wordSize; - mxc_i2s_justify_t justify; - mxc_i2s_bitorder_t bitOrder; - mxc_i2s_polarity_t wsPolarity; - mxc_i2s_samplesize_t sampleSize; - uint16_t clkdiv; - void *rawData; - void *txData; - void *rxData; - uint32_t length; + mxc_i2s_ch_mode_t channelMode; + mxc_i2s_stereo_t stereoMode; + mxc_i2s_wsize_t wordSize; + mxc_i2s_justify_t justify; + mxc_i2s_bitorder_t bitOrder; + mxc_i2s_polarity_t wsPolarity; + mxc_i2s_samplesize_t sampleSize; + uint16_t clkdiv; + void *rawData; + void *txData; + void *rxData; + uint32_t length; } mxc_i2s_req_t; - + /* **** Function Prototypes **** */ /** @@ -134,7 +126,7 @@ * @brief Release I2S, clear configuration and flush FIFOs * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. - */ + */ int MXC_I2S_Shutdown(void); /** @@ -142,7 +134,7 @@ * * @param req see \ref mxc_i2s_req_t I2S Request Struct * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. - */ + */ int MXC_I2S_ConfigData(mxc_i2s_req_t *req); /** @@ -179,15 +171,66 @@ * @param mode Channel mode to select clock * @param clkdiv clock divider to set baudrate * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. - */ + */ int MXC_I2S_SetFrequency(mxc_i2s_ch_mode_t mode, uint16_t clkdiv); +/** + * @brief Sets the clock divider to provide the desired sampling rate. + * + * @param smpl_rate The desired sampling rate. + * @param smpl_sz The size of each sample. + * + * @return If successful, the actual sampling rate. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2S_SetSampleRate(uint32_t smpl_rate, mxc_i2s_wsize_t smpl_sz); + +/** + * @brief Returns the current sampling rate. + * + * @return If successful, sampling rate. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2S_GetSampleRate(void); + +/** + * @brief Calculates the value of the clock divider that should be used in order to get the desired sampling frequency. + * + * @param smpl_rate Desired sampling rate. + * @param smple_sz The size of each I2S word. + * + * @return If successful, the clock divider value. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2S_CalculateClockDiv(uint32_t smpl_rate, mxc_i2s_wsize_t smpl_sz); + /** * @brief Flush I2S FIFO * - */ + */ void MXC_I2S_Flush(void); +/** + * @brief Fill I2S FIFO with data to transmit + * + * @param txData Pointer to base address of the data buffer + * @param wordSize Size of the data samples + * @param len Number of samples in the data buffer + * @param smpl_cnt Number of samples already sent from the data buffer + * + * @returns If successful the number of samples successfuly written to the FIFO. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2S_FillTXFIFO(void *txData, mxc_i2s_wsize_t wordSize, int len, int smpl_cnt); + +/** + * @brief Read audio samples from I2S receive buffer + * + * @param rxData Pointer to data buffer that will store the audio samples + * @param wordSize Size of the samples in the FIFO + * @param len Number of samples to read + * @param smpl_cnt Number of samples already received in the data buffer + * + * @returns If successful, the number of samples actually read from the buffer. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2S_ReadRXFIFO(void *rxData, mxc_i2s_wsize_t wordSize, int len, int smpl_cnt); + /** * @brief Enable Interrupts * @@ -213,34 +256,68 @@ * @brief Clears Interrupt Flags * * @param flags Interrupt flags to be cleared - */ + */ void MXC_I2S_ClearFlags(uint32_t flags); /** + * @brief Performs a blocking I2S transaction. + * + * @param Pointer to transaction request structure + * + * @returns If successful, E_NO_ERROR. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2S_Transaction(mxc_i2s_req_t *i2s_req); + +/** + * @brief Sets up an asynchronous I2S transaction. + * + * @param Pointer to transaction request structure + * + * @returns If successful, E_NO_ERROR. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2S_TransactionAsync(mxc_i2s_req_t *i2s_req); + +/** * @brief Configure TX DMA transaction * * @param src_addr source address of data - * @param len length od the data to be transmitted + * @param len length od the data to be transmitted + * + * @return If successful, the DMA channel number used for the request. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes. */ -void MXC_I2S_TXDMAConfig(void *src_addr, int len); +int MXC_I2S_TXDMAConfig(void *src_addr, int len); /** * @brief Configure RX DMA transaction * * @param dest_addr destination address * @param len length of the data to be received + * + * @return If successful, the DMA channel number used for the request. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes. */ -void MXC_I2S_RXDMAConfig(void *dest_addr, int len); +int MXC_I2S_RXDMAConfig(void *dest_addr, int len); + +/** + * @brief Handler for asynchronous I2S transactions. + */ +void MXC_I2S_Handler(void); /** * @brief Set the callback function pointer for I2S DMA transactions * * @param callback Function pointer to the DMA callback function */ -void MXC_I2S_RegisterDMACallback(void(*callback)(int, int)); +void MXC_I2S_RegisterDMACallback(void (*callback)(int, int)); + +/** + * @brief Sets the callback function for asynchronous I2S transactions + * + * @param callback Function pointer to the asynchronous transaction callback + */ +void MXC_I2S_RegisterAsyncCallback(void (*callback)(int)); #ifdef __cplusplus } #endif -#endif /* _I2S_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2S_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/icc.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/icc.h index b64be6c..c7c9d3d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/icc.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/icc.h @@ -3,8 +3,8 @@ * @brief Instruction Controller Cache(ICC) function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _ICC_H_ -#define _ICC_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_ICC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_ICC_H_ /* **** Includes **** */ #include @@ -58,9 +58,9 @@ * @brief Enumeration type for the Cache ID Register */ typedef enum { - ICC_INFO_RELNUM, ///< Identifies the RTL release version - ICC_INFO_PARTNUM, ///< Specifies the value of C_ID Port Number - ICC_INFO_ID ///< Specifies the value of Cache ID + ICC_INFO_RELNUM, ///< Identifies the RTL release version + ICC_INFO_PARTNUM, ///< Specifies the value of C_ID Port Number + ICC_INFO_ID ///< Specifies the value of Cache ID } mxc_icc_info_t; /** @@ -68,22 +68,22 @@ * @param cid Enumeration type for Cache Id Register. * @retval Returns the contents of Cache Id Register. */ -int MXC_ICC_ID (mxc_icc_info_t cid); +int MXC_ICC_ID(mxc_icc_info_t cid); /** * @brief Enable the instruction cache controller. */ -void MXC_ICC_Enable (void); +void MXC_ICC_Enable(void); /** * @brief Disable the instruction cache controller. */ -void MXC_ICC_Disable (void); +void MXC_ICC_Disable(void); /** * @brief Flush the instruction cache controller. */ -void MXC_ICC_Flush (void); +void MXC_ICC_Flush(void); /**@} end of group icc */ @@ -91,4 +91,4 @@ } #endif -#endif /* _ICC_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_ICC_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h index 2c468d8..e760510 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h @@ -3,8 +3,8 @@ * @brief Low Power(LP) function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _LP_H_ -#define _LP_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_LP_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_LP_H_ /* **** Includes **** */ #include @@ -62,18 +62,14 @@ * @brief Enumeration type for voltage selection * */ -typedef enum { - MXC_LP_V0_9 = 0, - MXC_LP_V1_0, - MXC_LP_V1_1 -} mxc_lp_ovr_t; +typedef enum { MXC_LP_V0_9 = 0, MXC_LP_V1_0, MXC_LP_V1_1 } mxc_lp_ovr_t; /** * @brief Enumeration type for PM Mode * */ typedef enum { - MXC_LP_IPO = MXC_F_GCR_PM_IPO_PD, + MXC_LP_IPO = MXC_F_GCR_PM_IPO_PD, MXC_LP_IBRO = MXC_F_GCR_PM_IBRO_PD, MXC_LP_XRFO = MXC_F_GCR_PM_ERFO_PD } mxc_lp_cfg_ds_pd_t; @@ -81,127 +77,127 @@ /** * @brief Places the device into SLEEP mode. This function returns once an RTC or external interrupt occur. */ -void MXC_LP_EnterSleepMode (void); +void MXC_LP_EnterSleepMode(void); /** * @brief Places the device into DEEPSLEEP mode. This function returns once an RTC or external interrupt occur. */ -void MXC_LP_EnterDeepSleepMode (void); +void MXC_LP_EnterDeepSleepMode(void); /** * @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns. * Instead, the device will restart once an RTC or external interrupt occur. */ -void MXC_LP_EnterBackupMode (void); +void MXC_LP_EnterBackupMode(void); /** * @brief Places the device into Storage mode. CPU state is not maintained in this mode, so this function never returns. * Instead, the device will restart once an RTC or external interrupt occur. */ -void MXC_LP_EnterStorageMode (void); +void MXC_LP_EnterStorageMode(void); /** * @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns. * Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur. */ -void MXC_LP_EnterShutDownMode (void); +void MXC_LP_EnterShutDownMode(void); /** * @brief Set ovr bits to set the voltage the micro will run at. * * @param[in] ovr The ovr options are only 0.9V, 1.0V, and 1.1V use enum mxc_lp_ovr_t */ -void MXC_LP_SetOVR (mxc_lp_ovr_t ovr); +void MXC_LP_SetOVR(mxc_lp_ovr_t ovr); /** * @brief Enable retention regulator */ -void MXC_LP_RetentionRegEnable (void); +void MXC_LP_RetentionRegEnable(void); /** * @brief Disable retention regulator */ -void MXC_LP_RetentionRegDisable (void); +void MXC_LP_RetentionRegDisable(void); /** * @brief Is the retention regulator enabled * * @return 1 = enabled 0 = disabled */ -int MXC_LP_RetentionRegIsEnabled (void); +int MXC_LP_RetentionRegIsEnabled(void); /** * @brief Turn bandgap on */ -void MXC_LP_BandgapOn (void); +void MXC_LP_BandgapOn(void); /** * @brief Turn bandgap off */ -void MXC_LP_BandgapOff (void); +void MXC_LP_BandgapOff(void); /** * @brief Is the bandgap on or off * * @return 1 = bandgap on , 0 = bandgap off */ -int MXC_LP_BandgapIsOn (void); +int MXC_LP_BandgapIsOn(void); /** * @brief Enable Power on Reset VDD Core Monitor */ -void MXC_LP_PORVCOREoreMonitorEnable (void); +void MXC_LP_PORVCOREoreMonitorEnable(void); /** * @brief Disable Power on Reset VDD Core Monitor */ -void MXC_LP_PORVCOREoreMonitorDisable (void); +void MXC_LP_PORVCOREoreMonitorDisable(void); /** * @brief Is Power on Reset VDD Core Monitor enabled * * @return 1 = enabled , 0 = disabled */ -int MXC_LP_PORVCOREoreMonitorIsEnabled (void); +int MXC_LP_PORVCOREoreMonitorIsEnabled(void); /** * @brief Enable LDO */ -void MXC_LP_LDOEnable (void); +void MXC_LP_LDOEnable(void); /** * @brief Disable LDO */ -void MXC_LP_LDODisable (void); +void MXC_LP_LDODisable(void); /** * @brief Is LDO enabled * * @return 1 = enabled , 0 = disabled */ -int MXC_LP_LDOIsEnabled (void); +int MXC_LP_LDOIsEnabled(void); /** * @brief Enable Fast wakeup */ -void MXC_LP_FastWakeupEnable (void); +void MXC_LP_FastWakeupEnable(void); /** * @brief Disable Fast wakeup */ -void MXC_LP_FastWakeupDisable (void); +void MXC_LP_FastWakeupDisable(void); /** * @brief Is Fast wake up is Enabled * * @return 1 = enabled , 0 = disabled */ -int MXC_LP_FastWakeupIsEnabled (void); +int MXC_LP_FastWakeupIsEnabled(void); /** * @brief clear all wake up status */ -void MXC_LP_ClearWakeStatus (void); +void MXC_LP_ClearWakeStatus(void); /** * @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode. @@ -218,60 +214,70 @@ * @param port The port to configure as wakeup sources. * @param mask The pins to configure as wakeup sources. */ -void MXC_LP_DisableGPIOWakeup (unsigned int port, unsigned int mask); +void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask); /** * @brief Enables the RTC alarm to wake up the device from any low power mode. */ -void MXC_LP_EnableRTCAlarmWakeup (void); +void MXC_LP_EnableRTCAlarmWakeup(void); /** * @brief Disables the RTC alarm from waking up the device. */ -void MXC_LP_DisableRTCAlarmWakeup (void); +void MXC_LP_DisableRTCAlarmWakeup(void); /** * @brief Enables Timer to wakeup from any low power mode. * * @param tmr Pointer to timer module. */ -void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t* tmr); +void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t *tmr); /** * @brief Disables Timer from waking up device. * * @param tmr Pointer to timer module. */ -void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t* tmr); +void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t *tmr); + +/** + * @brief Enables LPUART0 to wake up the device from any low power mode. + */ +void MXC_LP_EnableUARTWakeup(void); + +/** + * @brief Disables LPUART0 from waking up the device. + */ +void MXC_LP_DisableUARTWakeup(void); /** * @brief Enables the USB to wake up the device from any low power mode. */ -void MXC_LP_EnableUSBWakeup (void); +void MXC_LP_EnableUSBWakeup(void); /** * @brief Disables the USB from waking up the device. */ -void MXC_LP_DisableUSBWakeup (void); +void MXC_LP_DisableUSBWakeup(void); /** * @brief Enables the HA0 to wake up the device from any low power mode. */ -void MXC_LP_EnableHA0Wakeup (void); +void MXC_LP_EnableHA0Wakeup(void); /** * @brief Disables the HA)0 from waking up the device. */ -void MXC_LP_DisableHA0Wakeup (void); +void MXC_LP_DisableHA0Wakeup(void); /** * @brief Enables the HA1 to wake up the device from any low power mode. */ -void MXC_LP_EnableHA1Wakeup (void); +void MXC_LP_EnableHA1Wakeup(void); /** * @brief Disables the HA1 from waking up the device. */ -void MXC_LP_DisableHA1Wakeup (void); +void MXC_LP_DisableHA1Wakeup(void); /** * @brief Configure which clocks are powered down at deep sleep and which are not affected. @@ -283,254 +289,254 @@ * * @return #E_NO_ERROR or error based on \ref MXC_Error_Codes */ -int MXC_LP_ConfigDeepSleepClocks (uint32_t mask); +int MXC_LP_ConfigDeepSleepClocks(uint32_t mask); /** * @brief Enable NFC Oscilator Bypass */ -void MXC_LP_NFCOscBypassEnable (void); +void MXC_LP_NFCOscBypassEnable(void); /** * @brief Disable NFC Oscilator Bypass */ -void MXC_LP_NFCOscBypassDisable (void); +void MXC_LP_NFCOscBypassDisable(void); /** * @brief Is NFC Oscilator Bypass Enabled * * @return 1 = enabled, 0 = disabled */ -int MXC_LP_NFCOscBypassIsEnabled (void); +int MXC_LP_NFCOscBypassIsEnabled(void); /** * @brief Enable System Ram 0 in light sleep */ -void MXC_LP_SysRam0LightSleepEnable (void); +void MXC_LP_SysRam0LightSleepEnable(void); /** * @brief Enable System Ram 1 in light sleep */ -void MXC_LP_SysRam1LightSleepEnable (void); +void MXC_LP_SysRam1LightSleepEnable(void); /** * @brief Enable System Ram 2 in light sleep */ -void MXC_LP_SysRam2LightSleepEnable (void); +void MXC_LP_SysRam2LightSleepEnable(void); /** * @brief Enable System Ram 3 in light sleep */ -void MXC_LP_SysRam3LightSleepEnable (void); +void MXC_LP_SysRam3LightSleepEnable(void); /** * @brief Enable System Ram 4 in light sleep */ -void MXC_LP_SysRam4LightSleepEnable (void); +void MXC_LP_SysRam4LightSleepEnable(void); /** * @brief Enable System Ram 5 in light sleep */ -void MXC_LP_SysRam5LightSleepEnable (void); +void MXC_LP_SysRam5LightSleepEnable(void); /** * @brief Enable Icache 0 in light sleep */ -void MXC_LP_ICache0LightSleepEnable (void); +void MXC_LP_ICache0LightSleepEnable(void); /** * @brief Enable Icache XIP in light sleep */ -void MXC_LP_ICacheXIPLightSleepEnable (void); +void MXC_LP_ICacheXIPLightSleepEnable(void); /** * @brief Enable System Cache in light sleep */ -void MXC_LP_SRCCLightSleepEnable (void); +void MXC_LP_SRCCLightSleepEnable(void); /** * @brief Enable Crypto in light sleep */ -void MXC_LP_CryptoLightSleepEnable (void); +void MXC_LP_CryptoLightSleepEnable(void); /** * @brief Enable USB in light sleep */ -void MXC_LP_USBFIFOLightSleepEnable (void); +void MXC_LP_USBFIFOLightSleepEnable(void); /** * @brief Enable ROM 0 in light sleep */ -void MXC_LP_ROMLightSleepEnable (void); +void MXC_LP_ROMLightSleepEnable(void); /** * @brief Disable System Ram 0 in light sleep */ -void MXC_LP_SysRam0LightSleepDisable (void); +void MXC_LP_SysRam0LightSleepDisable(void); /** * @brief Disable System Ram 1 in light sleep */ -void MXC_LP_SysRam1LightSleepDisable (void); +void MXC_LP_SysRam1LightSleepDisable(void); /** * @brief Disable System Ram 2 in light sleep */ -void MXC_LP_SysRam2LightSleepDisable (void); +void MXC_LP_SysRam2LightSleepDisable(void); /** * @brief Disable System Ram 3 in light sleep */ -void MXC_LP_SysRam3LightSleepDisable (void); +void MXC_LP_SysRam3LightSleepDisable(void); /** * @brief Disable System Ram 4 in light sleep */ -void MXC_LP_SysRam4LightSleepDisable (void); +void MXC_LP_SysRam4LightSleepDisable(void); /** * @brief Disable System Ram 5 in light sleep */ -void MXC_LP_SysRam5LightSleepDisable (void); +void MXC_LP_SysRam5LightSleepDisable(void); /** * @brief Disable Icache 0 in light sleep */ -void MXC_LP_ICache0LightSleepDisable (void); +void MXC_LP_ICache0LightSleepDisable(void); /** * @brief Disable Icache XIP in light sleep */ -void MXC_LP_ICacheXIPLightSleepDisable (void); +void MXC_LP_ICacheXIPLightSleepDisable(void); /** * @brief Disable System Cache in light sleep */ -void MXC_LP_SRCCLightSleepDisable (void); +void MXC_LP_SRCCLightSleepDisable(void); /** * @brief Disable Crypto in light sleep */ -void MXC_LP_CryptoLightSleepDisable (void); +void MXC_LP_CryptoLightSleepDisable(void); /** * @brief Disable USB in light sleep */ -void MXC_LP_USBFIFOLightSleepDisable (void); +void MXC_LP_USBFIFOLightSleepDisable(void); /** * @brief Disable ROM 0 in light sleep */ -void MXC_LP_ROMLightSleepDisable (void); +void MXC_LP_ROMLightSleepDisable(void); /** * @brief Shutdown System Ram 0 */ -void MXC_LP_SysRam0Shutdown (void); +void MXC_LP_SysRam0Shutdown(void); /** * @brief Wakeup System Ram 0 */ -void MXC_LP_SysRam0PowerUp (void); +void MXC_LP_SysRam0PowerUp(void); /** * @brief Shutdown System Ram 1 */ -void MXC_LP_SysRam1Shutdown (void); +void MXC_LP_SysRam1Shutdown(void); /** * @brief PowerUp System Ram 1 */ -void MXC_LP_SysRam1PowerUp (void); +void MXC_LP_SysRam1PowerUp(void); /** * @brief Shutdown System Ram 2 */ -void MXC_LP_SysRam2Shutdown (void); +void MXC_LP_SysRam2Shutdown(void); /** * @brief PowerUp System Ram 2 */ -void MXC_LP_SysRam2PowerUp (void); +void MXC_LP_SysRam2PowerUp(void); /** * @brief Shutdown System Ram 3 */ -void MXC_LP_SysRam3Shutdown (void); +void MXC_LP_SysRam3Shutdown(void); /** * @brief PowerUp System Ram 3 */ -void MXC_LP_SysRam3PowerUp (void); +void MXC_LP_SysRam3PowerUp(void); /** * @brief Shutdown System Ram 4 */ -void MXC_LP_SysRam4Shutdown (void); +void MXC_LP_SysRam4Shutdown(void); /** * @brief PowerUp System Ram 4 */ -void MXC_LP_SysRam4PowerUp (void); +void MXC_LP_SysRam4PowerUp(void); /** * @brief Shutdown System Ram 5 */ -void MXC_LP_SysRam5Shutdown (void); +void MXC_LP_SysRam5Shutdown(void); /** * @brief PowerUp System Ram 5 */ -void MXC_LP_SysRam5PowerUp (void); +void MXC_LP_SysRam5PowerUp(void); /** * @brief Shutdown Internal Cache */ -void MXC_LP_ICache0Shutdown (void); +void MXC_LP_ICache0Shutdown(void); /** * @brief PowerUp Internal Cache */ -void MXC_LP_ICache0PowerUp (void); +void MXC_LP_ICache0PowerUp(void); /** * @brief Shutdown Internal Cache XIP */ -void MXC_LP_ICacheXIPShutdown (void); +void MXC_LP_ICacheXIPShutdown(void); /** * @brief PowerUp Internal Cache XIP */ -void MXC_LP_ICacheXIPPowerUp (void); +void MXC_LP_ICacheXIPPowerUp(void); /** * @brief Shutdown SRCC */ -void MXC_LP_SRCCShutdown (void); +void MXC_LP_SRCCShutdown(void); /** * @brief PowerUp SRCC */ -void MXC_LP_SRCCPowerUp (void); +void MXC_LP_SRCCPowerUp(void); /** * @brief Shutdown USB FIFO */ -void MXC_LP_USBFIFOShutdown (void); +void MXC_LP_USBFIFOShutdown(void); /** * @brief PowerUp USB FIFO */ -void MXC_LP_USBFIFOPowerUp (void); +void MXC_LP_USBFIFOPowerUp(void); /** * @brief Shutdown ROM */ -void MXC_LP_ROMShutdown (void); +void MXC_LP_ROMShutdown(void); /** * @brief PowerUp ROM */ -void MXC_LP_ROMPowerUp (void); +void MXC_LP_ROMPowerUp(void); /**@} end of group pwrseq */ @@ -538,4 +544,4 @@ } #endif -#endif /* _LP_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_LP_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_aes.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_aes.h index 1f21b909..57a76d7 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_aes.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_aes.h @@ -1,10 +1,10 @@ /** * @file - * @brief Trust Protection Unit driver. + * @brief AES driver. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,14 +34,14 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _MXC_AES_H_ -#define _MXC_AES_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_AES_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_AES_H_ /***** Includes *****/ #include "aes_regs.h" -#include "aes_key_regs.h" +#include "aeskeys_regs.h" #ifdef __cplusplus extern "C" { @@ -56,7 +56,7 @@ /***** Definitions *****/ -typedef void (*mxc_aes_complete_t) (void* req, int result); +typedef void (*mxc_aes_complete_t)(void *req, int result); /* ************************************************************************* */ /* Cipher Definitions */ @@ -67,9 +67,9 @@ * */ typedef enum { - MXC_AES_128BITS = MXC_S_AES_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key - MXC_AES_192BITS = MXC_S_AES_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key - MXC_AES_256BITS = MXC_S_AES_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key + MXC_AES_128BITS = MXC_S_AES_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key + MXC_AES_192BITS = MXC_S_AES_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key + MXC_AES_256BITS = MXC_S_AES_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key } mxc_aes_keys_t; /** @@ -77,9 +77,9 @@ * */ typedef enum { - MXC_AES_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key - MXC_AES_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key - MXC_AES_DECRYPT_INT_KEY = 2 ///< Decryption using internal key + MXC_AES_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key + MXC_AES_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key + MXC_AES_DECRYPT_INT_KEY = 2 ///< Decryption using internal key } mxc_aes_enc_type_t; /** @@ -87,12 +87,12 @@ * */ typedef struct _mxc_aes_cipher_req_t { - uint32_t length; ///< Length of the data - uint32_t *inputData; ///< Pointer to input data - uint32_t *resultData; ///< Pointer to encrypted data - mxc_aes_keys_t keySize; ///< Size of AES key - mxc_aes_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t - mxc_aes_complete_t callback; ///< Callback function + uint32_t length; ///< Length of the data + uint32_t *inputData; ///< Pointer to input data + uint32_t *resultData; ///< Pointer to encrypted data + mxc_aes_keys_t keySize; ///< Size of AES key + mxc_aes_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t + mxc_aes_complete_t callback; ///< Callback function } mxc_aes_req_t; /***** Function Prototypes *****/ @@ -106,92 +106,92 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_Init (void); +int MXC_AES_Init(void); /** * @brief Enable AES Interrupts * * @param interrupt interrupt to enable */ -void MXC_AES_EnableInt (uint32_t interrupt); +void MXC_AES_EnableInt(uint32_t interrupt); /** * @brief Disable AES Interrupts * * @param interrupt interrupt to disable */ -void MXC_AES_DisableInt (uint32_t interrupt); +void MXC_AES_DisableInt(uint32_t interrupt); /** * @brief Checks the global AES Busy Status * * @return E_BUSY if busy and E_NO_ERROR otherwise, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_IsBusy (void); +int MXC_AES_IsBusy(void); /** * @brief Disable and reset portions of the AES * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_Shutdown (void); +int MXC_AES_Shutdown(void); /** * @brief This function should be called from the DMA Handler * when using Async functions */ -void MXC_AES_DMACallback (int ch, int error); +void MXC_AES_DMACallback(int ch, int error); /** * @brief This function should be called before encryption to genrate external key */ -void MXC_AES_GenerateKey (void); +void MXC_AES_GenerateKey(void); /** * @brief Set Key size for encryption or decryption * * @param key Key size, see \ref mxc_aes_keys_t for a list of keys */ -void MXC_AES_SetKeySize (mxc_aes_keys_t key); +void MXC_AES_SetKeySize(mxc_aes_keys_t key); /** * @brief Get the currently set key size * * @return mxc_aes_keys_t see \ref mxc_aes_keys_t */ -mxc_aes_keys_t MXC_AES_GetKeySize (void); +mxc_aes_keys_t MXC_AES_GetKeySize(void); /** * @brief Flush Input Data FIFO * */ -void MXC_AES_FlushInputFIFO (void); +void MXC_AES_FlushInputFIFO(void); /** * @brief Flush Output Data FIFO * */ -void MXC_AES_FlushOutputFIFO (void); +void MXC_AES_FlushOutputFIFO(void); /** * @brief Start AES Calculations * */ -void MXC_AES_Start (void); +void MXC_AES_Start(void); /** * @brief Get Interrupt flags set * * @return return the flags set in intfl register */ -uint32_t MXC_AES_GetFlags (void); +uint32_t MXC_AES_GetFlags(void); /** * @brief Clear the interrupts * * @param flags flags to be cleared */ -void MXC_AES_ClearFlags (uint32_t flags); +void MXC_AES_ClearFlags(uint32_t flags); /** * @brief @@ -201,7 +201,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_Generic (mxc_aes_req_t* req); +int MXC_AES_Generic(mxc_aes_req_t *req); /** * @brief Perform an encryption @@ -211,7 +211,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_Encrypt (mxc_aes_req_t* req); +int MXC_AES_Encrypt(mxc_aes_req_t *req); /** * @brief Perform a decryption @@ -221,7 +221,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_Decrypt (mxc_aes_req_t* req); +int MXC_AES_Decrypt(mxc_aes_req_t *req); /** * @brief Perform AES TX using DMA. Configures DMA request and starts the transmission. @@ -230,7 +230,7 @@ * @param len number of words of data * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_TXDMAConfig (void *src_addr, int len); +int MXC_AES_TXDMAConfig(void *src_addr, int len); /** * @brief Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO. @@ -239,7 +239,7 @@ * @param len number of words of data * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_RXDMAConfig (void *dest_addr, int len); +int MXC_AES_RXDMAConfig(void *dest_addr, int len); /** * @brief Perform encryption or decryption using DMA @@ -249,7 +249,7 @@ * @param enc 0 for encryption and 1 for decryption * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_GenericAsync (mxc_aes_req_t* req, uint8_t enc); +int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc); /** * @brief Perform an encryption using Interrupt @@ -259,7 +259,7 @@ * @param req Structure containing data for the encryption * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_EncryptAsync (mxc_aes_req_t* req); +int MXC_AES_EncryptAsync(mxc_aes_req_t *req); /** * @brief Perform a decryption using Interrupt @@ -269,14 +269,14 @@ * @param req Structure containing data for the decryption * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_DecryptAsync (mxc_aes_req_t* req); +int MXC_AES_DecryptAsync(mxc_aes_req_t *req); /** * @brief Set the external key * @param key Buffer for the key. * @param len Key size. */ -void MXC_AES_SetExtKey(const void* key, mxc_aes_keys_t len); +void MXC_AES_SetExtKey(const void *key, mxc_aes_keys_t len); /** * @brief Set the key that will be loaded into the AES key registers on a POR event. @@ -284,7 +284,7 @@ * @param len Key size. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_SetPORKey(const void* key, mxc_aes_keys_t len); +int MXC_AES_SetPORKey(const void *key, mxc_aes_keys_t len); /** * @brief Clears the key that will be loaded into the AES key registers on a POR event. @@ -309,10 +309,9 @@ */ int MXC_AES_HasPORKey(); - #ifdef __cplusplus } #endif /**@} end of group aes */ -#endif /* _MXC_AES_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_AES_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_assert.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_assert.h index 59f140e..96afe1c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_assert.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_assert.h @@ -3,8 +3,8 @@ * @brief Assertion checks for debugging. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,15 +34,14 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _MXC_ASSERT_H_ -#define _MXC_ASSERT_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ASSERT_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ASSERT_H_ /* **** Includes **** */ - #ifdef __cplusplus extern "C" { #endif @@ -65,11 +64,10 @@ * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be * defined. */ -#define MXC_ASSERT(expr) \ -if (!(expr)) \ -{ \ - mxc_assert(#expr, __FILE__, __LINE__); \ -} +#define MXC_ASSERT(expr) \ + if (!(expr)) { \ + mxc_assert(#expr, __FILE__, __LINE__); \ + } /** * Macro that generates an assertion with the message "FAIL". * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be @@ -98,7 +96,7 @@ * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be * defined. */ -void mxc_assert (const char *expr, const char *file, int line); +void mxc_assert(const char *expr, const char *file, int line); /**@} end of group MXC_Assertions*/ @@ -106,4 +104,4 @@ } #endif -#endif /* _MXC_ASSERT_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ASSERT_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_delay.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_delay.h index e9d387f..5bfc02b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_delay.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_delay.h @@ -3,8 +3,8 @@ * @brief Asynchronous delay routines based on the SysTick Timer. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,17 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _DELAY_H_ -#define _DELAY_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DELAY_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DELAY_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif /** * @ingroup devicelibs @@ -54,21 +60,21 @@ * x = SEC(3) // 3 seconds -> x = 3,000,000 * \endcode */ -#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL) +#define MXC_DELAY_SEC(s) (((uint32_t)s) * 1000000UL) /** * Macro used to specify a microsecond timing parameter in milliseconds. * \code * x = MSEC(3) // 3ms -> x = 3,000 * \endcode */ -#define MXC_DELAY_MSEC(ms) (ms * 1000UL) +#define MXC_DELAY_MSEC(ms) (ms * 1000UL) /** * Macro used to specify a microsecond timing parameter. * \code * x = USEC(3) // 3us -> x = 3 * \endcode */ -#define MXC_DELAY_USEC(us) (us) +#define MXC_DELAY_USEC(us) (us) /** * @brief The callback routine used by MXC_DelayAsync() when the delay is complete @@ -76,7 +82,7 @@ * * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*mxc_delay_complete_t) (int result); +typedef void (*mxc_delay_complete_t)(int result); /***** Function Prototypes *****/ @@ -88,7 +94,7 @@ * @param us microseconds to delay * @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful. */ -int MXC_Delay (unsigned long us); +int MXC_Delay(uint32_t us); /** * @brief Starts a non-blocking delay for the specified number of @@ -103,28 +109,32 @@ * @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another * delay request. */ -int MXC_DelayAsync (unsigned long us, mxc_delay_complete_t callback); +int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback); /** * @brief Returns the status of a non-blocking delay request * @pre Start the asynchronous delay by calling MXC_Delay_start(). * @return #E_BUSY until the requested delay time has expired. */ -int MXC_DelayCheck (void); +int MXC_DelayCheck(void); /** * @brief Stops an asynchronous delay previously started. * @pre Start the asynchronous delay by calling MXC_Delay_start(). */ -void MXC_DelayAbort (void); +void MXC_DelayAbort(void); /** * @brief Processes the delay interrupt. * @details This function must be called from the SysTick IRQ or polled at a * rate greater than the SysTick overflow rate. */ -void MXC_DelayHandler (void); +void MXC_DelayHandler(void); /**@} end of group MXC_delay */ -#endif /* _DELAY_H_ */ +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DELAY_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h index 86c7bbf..4095f4a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h @@ -3,8 +3,8 @@ * @brief Device specific header file. */ -/******************************************************************************* - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -36,16 +36,16 @@ * ******************************************************************************/ -#ifndef _MXC_DEVICE_H_ -#define _MXC_DEVICE_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DEVICE_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DEVICE_H_ #include "max32670.h" #include "mxc_errors.h" #include "mxc_pins.h" -#if defined ( __ICCARM__ ) || (__CC_ARM) +#if defined(__ICCARM__) || (__CC_ARM) #include "RTE_Components.h" -#endif +#endif #ifndef TARGET #error TARGET NOT DEFINED @@ -63,14 +63,14 @@ #error TARGET_REV NOT DEFINED #endif -#if(TARGET_REV == 0x4131) +#if (TARGET_REV == 0x4131) // A1 -#define MXC_TMR_REV 0 -#define MXC_UART_REV 0 +#define MXC_TMR_REV 0 +#define MXC_UART_REV 0 #else #error TARGET_REV NOT SUPPORTED #endif /* if(TARGET_REV == ...) */ -#endif /* _MXC_DEVICE_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DEVICE_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_errors.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_errors.h index 4b0b0bb..fc9a7ce 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_errors.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_errors.h @@ -3,8 +3,8 @@ * @brief List of common error return codes for Maxim Integrated libraries. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _MXC_ERRORS_H_ -#define _MXC_ERRORS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ERRORS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ERRORS_H_ /** * @ingroup syscfg @@ -50,43 +50,45 @@ */ /** No Error */ -#define E_NO_ERROR 0 +#define E_NO_ERROR 0 /** No Error, success */ -#define E_SUCCESS 0 +#define E_SUCCESS 0 /** Pointer is NULL */ -#define E_NULL_PTR -1 +#define E_NULL_PTR -1 /** No such device */ -#define E_NO_DEVICE -2 +#define E_NO_DEVICE -2 /** Parameter not acceptable */ -#define E_BAD_PARAM -3 +#define E_BAD_PARAM -3 /** Value not valid or allowed */ -#define E_INVALID -4 +#define E_INVALID -4 /** Module not initialized */ -#define E_UNINITIALIZED -5 +#define E_UNINITIALIZED -5 /** Busy now, try again later */ -#define E_BUSY -6 +#define E_BUSY -6 /** Operation not allowed in current state */ -#define E_BAD_STATE -7 +#define E_BAD_STATE -7 /** Generic error */ -#define E_UNKNOWN -8 +#define E_UNKNOWN -8 /** General communications error */ -#define E_COMM_ERR -9 +#define E_COMM_ERR -9 /** Operation timed out */ -#define E_TIME_OUT -10 +#define E_TIME_OUT -10 /** Expected response did not occur */ -#define E_NO_RESPONSE -11 +#define E_NO_RESPONSE -11 /** Operations resulted in unexpected overflow */ -#define E_OVERFLOW -12 +#define E_OVERFLOW -12 /** Operations resulted in unexpected underflow */ -#define E_UNDERFLOW -13 +#define E_UNDERFLOW -13 /** Data or resource not available at this time */ -#define E_NONE_AVAIL -14 +#define E_NONE_AVAIL -14 /** Event was shutdown */ -#define E_SHUTDOWN -15 +#define E_SHUTDOWN -15 /** Event was aborted */ -#define E_ABORT -16 +#define E_ABORT -16 /** The requested operation is not supported */ -#define E_NOT_SUPPORTED -17 +#define E_NOT_SUPPORTED -17 +/** The requested operation is failed */ +#define E_FAIL -255 /**@} end of MXC_Error_Codes group */ -#endif /* _MXC_ERRORS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ERRORS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_i2c.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_i2c.h index 04ebc79..569b8a9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_i2c.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_i2c.h @@ -3,8 +3,8 @@ * @brief Inter-integrated circuit (I2C) communications interface driver. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _MXC_I2C_H_ -#define _MXC_I2C_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2C_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2C_H_ #include #include "mxc_sys.h" @@ -69,7 +69,7 @@ * @return 0 if the byte should not be acknowledged (NACK), non-zero to * acknowledge the byte. */ -typedef int (*mxc_i2c_getAck_t) (mxc_i2c_regs_t* i2c, unsigned char byte); +typedef int (*mxc_i2c_getAck_t)(mxc_i2c_regs_t *i2c, unsigned char byte); /** * @brief The callback routine used by the MXC_I2C_MasterTransactionAsync() @@ -80,7 +80,7 @@ * transmitted is not acknowledged, negative if error. * See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*mxc_i2c_complete_cb_t) (mxc_i2c_req_t* req, int result); +typedef void (*mxc_i2c_complete_cb_t)(mxc_i2c_req_t *req, int result); /** * @brief The callback routine used by the I2C Read/Write FIFO DMA @@ -89,7 +89,7 @@ * @param len The length of data actually read/written * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*mxc_i2c_dma_complete_cb_t) (int len, int result); +typedef void (*mxc_i2c_dma_complete_cb_t)(int len, int result); /** * @brief The information required to perform a complete I2C transaction as @@ -100,22 +100,22 @@ * MXC_I2C_MasterTransactionAsync() functions. */ struct _i2c_req_t { - mxc_i2c_regs_t* i2c; ///< Pointer to I2C registers (selects the + mxc_i2c_regs_t *i2c; ///< Pointer to I2C registers (selects the ///< I2C block used.) - unsigned int addr; ///< The 7-bit or 10-bit address of the slave. - unsigned char* tx_buf; ///< The buffer containing the bytes to write. - unsigned int tx_len; ///< The number of bytes to write. On return + unsigned int addr; ///< The 7-bit or 10-bit address of the slave. + unsigned char *tx_buf; ///< The buffer containing the bytes to write. + unsigned int tx_len; ///< The number of bytes to write. On return ///< from the function, this will be set to ///< the number of bytes actually transmitted. - unsigned char* rx_buf; ///< The buffer to read the data into. - unsigned int rx_len; ///< The number of bytes to read. On return + unsigned char *rx_buf; ///< The buffer to read the data into. + unsigned int rx_len; ///< The number of bytes to read. On return ///< from the function, this will be set to ///< the number of bytes actually received. - int restart; ///< Controls whether the transaction is + int restart; ///< Controls whether the transaction is ///< terminated with a stop or repeated start ///< condition. Use 0 for a stop, non-zero ///< for repeated start. - mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the + mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the ///< transaction is complete or an error has ///< occurred. This field may be set to NULL ///< if no indication is necessary. This @@ -134,18 +134,18 @@ * application to handle these events. */ typedef enum { - MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master + MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master ///< requesting a write to the slave. - MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master + MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master ///< requesting a read from the slave. - MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its + MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its ///< threshold level. - MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its + MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its ///< threshold level. MXC_I2C_EVT_TRANS_COMP, ///< The transaction has ended. - MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the + MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the ///< transmit FIFO was empty. - MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive + MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive ///< FIFO was already full. } mxc_i2c_slave_event_t; @@ -165,9 +165,9 @@ * non-zero to not acknowledge. The return value is ignored for all * other event types. */ -typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c, - mxc_i2c_slave_event_t event, void* data); - +typedef int (*mxc_i2c_slave_handler_t)(mxc_i2c_regs_t *i2c, mxc_i2c_slave_event_t event, + void *data); + /***** Function Prototypes *****/ /* ************************************************************************* */ @@ -188,7 +188,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr); +int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr); /** * @brief Initialize and enable I2C peripheral. @@ -202,7 +202,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx); +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx); /** * @brief Disable and shutdown I2C peripheral. @@ -211,7 +211,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c); +int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c); /** * @brief Reset the I2C peripheral. @@ -221,7 +221,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Reset (mxc_i2c_regs_t* i2c); +int MXC_I2C_Reset(mxc_i2c_regs_t *i2c); /** * @brief Set the frequency of the I2C interface. @@ -232,7 +232,7 @@ * @return Negative if error, otherwise actual speed set. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_I2C_SetFrequency (mxc_i2c_regs_t* i2c, unsigned int hz); +int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz); /** * @brief Get the frequency of the I2C interface. @@ -241,7 +241,7 @@ * * @return The I2C bus frequency in Hertz */ -unsigned int MXC_I2C_GetFrequency (mxc_i2c_regs_t* i2c); +unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c); /** * @brief Checks if the given I2C bus can be placed in sleep more. @@ -255,7 +255,7 @@ * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_I2C_ReadyForSleep (mxc_i2c_regs_t* i2c); +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c); /** * @brief Enables or disables clock stretching by the slave. @@ -268,7 +268,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SetClockStretching (mxc_i2c_regs_t* i2c, int enable); +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable); /** * @brief Determines if clock stretching has been enabled. @@ -277,7 +277,7 @@ * * @return Zero if clock stretching is disabled, non-zero otherwise */ -int MXC_I2C_GetClockStretching (mxc_i2c_regs_t* i2c); +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c); /* ************************************************************************* */ /* Low-level functions */ @@ -294,7 +294,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Start (mxc_i2c_regs_t* i2c); +int MXC_I2C_Start(mxc_i2c_regs_t *i2c); /** * @brief Generate a stop condition on the I2C bus. @@ -303,7 +303,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Stop (mxc_i2c_regs_t* i2c); +int MXC_I2C_Stop(mxc_i2c_regs_t *i2c); /** * @brief Write a single byte to the I2C bus. @@ -320,7 +320,7 @@ * @return 0 if byte is acknowledged, 1 if not acknowledged, negative if * error. See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_I2C_WriteByte (mxc_i2c_regs_t* i2c, unsigned char byte); +int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte); /** * @brief Read a single byte from the I2C bus. @@ -336,7 +336,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack); +int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack); /** * @brief Read a single byte from the I2C bus. @@ -360,9 +360,8 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte, - mxc_i2c_getAck_t getAck); - +int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck); + /** * @brief Write multiple bytes to the I2C bus. * @@ -380,7 +379,7 @@ * acknowledged, negative if error. See \ref MXC_Error_Codes for the * list of error return codes. */ -int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len); +int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len); /** * @brief Read multiple bytes from the I2C bus. @@ -399,9 +398,8 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, - int ack); - +int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack); + /** * @brief Unloads bytes from the receive FIFO. * @@ -411,9 +409,8 @@ * * @return The number of bytes actually read. */ -int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, - unsigned int len); - +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len); + /** * @brief Unloads bytes from the receive FIFO using DMA for longer reads. * @@ -426,9 +423,9 @@ * * @return See \ref MXC_Error_Codes for a list of return values. */ -int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes, - unsigned int len, mxc_i2c_dma_complete_cb_t callback); - +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback); + /** * @brief Get the number of bytes currently available in the receive FIFO. * @@ -436,7 +433,7 @@ * * @return The number of bytes available. */ -int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c); +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c); /** * @brief Loads bytes into the transmit FIFO. @@ -447,9 +444,8 @@ * * @return The number of bytes actually written. */ -int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, - unsigned int len); - +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len); + /** * @brief Loads bytes into the transmit FIFO using DMA for longer writes. * @@ -461,9 +457,9 @@ * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes, - unsigned int len, mxc_i2c_dma_complete_cb_t callback); - +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback); + /** * @brief Get the amount of free space available in the transmit FIFO. * @@ -471,21 +467,21 @@ * * @return The number of bytes available. */ -int MXC_I2C_GetTXFIFOAvailable (mxc_i2c_regs_t* i2c); +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c); /** * @brief Removes and discards all bytes currently in the receive FIFO. * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_ClearRXFIFO (mxc_i2c_regs_t* i2c); +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c); /** * @brief Removes and discards all bytes currently in the transmit FIFO. * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c); +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c); /** * @brief Get the presently set interrupt flags. @@ -496,7 +492,7 @@ * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1); +int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1); /** * @brief Clears the Interrupt Flags. @@ -505,7 +501,7 @@ * @param flags0 Flags to be cleared in interrupt register intfl0. * @param flags1 Flags to be cleared in interrupt register intfl1. */ -void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); /** * @brief Enable Interrupts. @@ -514,7 +510,7 @@ * @param flags0 Interrupts to be enabled in int->en0 * @param flags1 Interrupts to be enabled in int->en1 */ -void MXC_I2C_EnableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); /** * @brief Disable Interrupts. @@ -523,7 +519,7 @@ * @param flags0 Interrupts to be disabled in int->en0 * @param flags1 Interrupts to be disabled in int->en1 */ -void MXC_I2C_DisableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); /** * @brief Enables the slave preload mode @@ -533,28 +529,28 @@ * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c); +void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c); /** * @brief Disable the slave preload mode * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c); +void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c); /** * @brief Enables the slave to respond to the general call address * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c); +void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c); /** * @brief Prevents the slave from responding to the general call address * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c); +void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c); /** * @brief Set the I2C Timeout @@ -568,7 +564,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout); +void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout); /** * @brief Get the current I2C timeout @@ -577,7 +573,7 @@ * * @return The current timeout in uS */ -unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c); +unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c); /** * @brief Attempts to recover the I2C bus, ensuring the I2C lines are idle. @@ -603,7 +599,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_Recover (mxc_i2c_regs_t* i2c, unsigned int retries); +int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries); /* ************************************************************************* */ /* Transaction level functions */ @@ -630,7 +626,7 @@ * acknowledged, negative if error. See \ref MXC_Error_Codes for the * list of error return codes. */ -int MXC_I2C_MasterTransaction (mxc_i2c_req_t* req); +int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req); /** * @brief Performs a non-blocking I2C Master transaction. @@ -657,7 +653,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_MasterTransactionAsync (mxc_i2c_req_t* req); +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req); /** * @brief Performs a non-blocking I2C Master transaction using DMA for reduced time @@ -685,7 +681,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_MasterTransactionDMA (mxc_i2c_req_t* req); +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req); /** * @brief Performs a blocking I2C Slave transaction. @@ -725,7 +721,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback); +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback); /** * @brief Performs a non-blocking I2C Slave transaction. @@ -768,7 +764,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SlaveTransactionAsync (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback); +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback); /** * @brief Set the receive threshold level. @@ -791,7 +787,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SetRXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes); +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes); /** * @brief Get the current receive threshold level. @@ -800,7 +796,7 @@ * * @return The receive threshold value (in bytes). */ -unsigned int MXC_I2C_GetRXThreshold (mxc_i2c_regs_t* i2c); +unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c); /** * @brief Set the transmit threshold level. @@ -824,7 +820,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes); +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes); /** * @brief Get the current transmit threshold level. @@ -833,7 +829,7 @@ * * @return The transmit threshold value (in bytes). */ -unsigned int MXC_I2C_GetTXThreshold (mxc_i2c_regs_t* i2c); +unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c); /** * @brief Abort any asynchronous requests in progress. @@ -844,7 +840,7 @@ * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_AbortAsync (mxc_i2c_regs_t* i2c); +void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c); /** * @brief The processing function for asynchronous transactions. @@ -855,7 +851,7 @@ * * @param i2c Pointer to I2C registers (selects the I2C block used.) */ -void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c); +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c); /** * @brief The processing function for DMA transactions. @@ -866,14 +862,12 @@ * @param ch DMA channel * @param error Error status */ -void MXC_I2C_DMACallback (int ch, int error); - +void MXC_I2C_DMACallback(int ch, int error); /**@} end of group i2c */ - #ifdef __cplusplus } #endif -#endif /* _MXC_I2C_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2C_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h index a8567a9..4e000f1 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h @@ -3,8 +3,8 @@ * @brief Exclusive access lock utility functions. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,16 +34,14 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _MXC_LOCK_H_ -#define _MXC_LOCK_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_ // To enable disable this module -#define USE_LOCK_IN_DRIVERS 0 - -#if USE_LOCK_IN_DRIVERS +#define USE_LOCK_IN_DRIVERS 0 /* **** Includes **** */ #include "mxc_device.h" @@ -52,6 +50,8 @@ extern "C" { #endif +#if USE_LOCK_IN_DRIVERS + /** * @ingroup syscfg * @defgroup mxc_lock_utilities Exclusive Access Locks @@ -78,27 +78,26 @@ * * @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken. */ -int MXC_GetLock (uint32_t *lock, uint32_t value); +int MXC_GetLock(uint32_t *lock, uint32_t value); /** * @brief Free the given lock. * @param[in,out] lock Pointer to the variable used for the lock. When the lock * is free, the value pointed to by @p lock is set to zero. */ -void MXC_FreeLock (uint32_t *lock); +void MXC_FreeLock(uint32_t *lock); /**@} end of group mxc_lock_utilities */ +#else // USE_LOCK_IN_DRIVERS + +#define MXC_GetLock(x, y) E_NO_ERROR +#define MXC_FreeLock(x) + +#endif // USE_LOCK_IN_DRIVERS + #ifdef __cplusplus } #endif - -#else // USE_LOCK_IN_DRIVERS - -#define MXC_GetLock(x, y) E_NO_ERROR -#define MXC_FreeLock(x) - -#endif // USE_LOCK_IN_DRIVERS - -#endif /* _MXC_LOCK_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h index af5545a..be402cd 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h @@ -3,8 +3,8 @@ * @brief This file contains constant pin configurations for the peripherals. */ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,30 +34,25 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ - -#ifndef _MXC_PINS_H_ -#define _MXC_PINS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_PINS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_PINS_H_ #include "gpio.h" -typedef enum { - MAP_A, - MAP_B, - MAP_C -} sys_map_t; +typedef enum { MAP_A, MAP_B, MAP_C } sys_map_t; /***** Global Variables *****/ // Predefined GPIO Configurations -extern const mxc_gpio_cfg_t gpio_cfg_extclk; +extern const mxc_gpio_cfg_t gpio_cfg_lpextclk; +extern const mxc_gpio_cfg_t gpio_cfg_hfextclk; extern const mxc_gpio_cfg_t gpio_cfg_i2c0; extern const mxc_gpio_cfg_t gpio_cfg_i2c1; extern const mxc_gpio_cfg_t gpio_cfg_i2c2; extern const mxc_gpio_cfg_t gpio_cfg_i2c2b; extern const mxc_gpio_cfg_t gpio_cfg_i2c2c; - extern const mxc_gpio_cfg_t gpio_cfg_uart0a; extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow_disable; @@ -80,7 +75,6 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable; - extern const mxc_gpio_cfg_t gpio_cfg_spi0; // NOTE: SPI1 definied here with SS1 only, SS0 is on port0 by itself. extern const mxc_gpio_cfg_t gpio_cfg_spi1; @@ -112,5 +106,4 @@ extern const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc2; extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc2; -#endif /* _MXC_PINS_H_ */ - +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_PINS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h index 734f663..b20d52f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h @@ -3,8 +3,8 @@ * @brief Serial Peripheral Interface (SPI) communications driver. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,9 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ -#ifndef _SPI_H_ -#define _SPI_H_ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_SPI_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_SPI_H_ /***** includes *******/ #include "spi_regs.h" @@ -79,10 +80,10 @@ * */ typedef enum { - SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex - SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex - SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex - SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex + SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex + SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex + SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex + SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex } mxc_spi_width_t; /** @@ -97,10 +98,10 @@ * */ typedef enum { - SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 - SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 - SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 - SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 + SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 + SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 + SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 + SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 } mxc_spi_mode_t; typedef struct _mxc_spi_req_t mxc_spi_req_t; @@ -111,7 +112,7 @@ * @param req The details of the transaction. * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*spi_complete_cb_t) (void * req, int result); +typedef void (*spi_complete_cb_t)(void *req, int result); /** * @brief The information required to perform a complete SPI transaction @@ -120,23 +121,23 @@ * @note "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions. */ struct _mxc_spi_req_t { - mxc_spi_regs_t* spi; /// 8 bits, use two bytes per character ///< and pad the MSB of the upper byte with zeros - uint8_t *rxData; ///< Buffer to store received data For character sizes + uint8_t *rxData; ///< Buffer to store received data For character sizes ///< < 8 bits, pad the MSB of each byte with zeros. For ///< character sizes > 8 bits, use two bytes per character ///< and pad the MSB of the upper byte with zeros - uint32_t txLen; ///< Number of bytes to be sent from txData - uint32_t rxLen; ///< Number of bytes to be stored in rxData - uint32_t txCnt; ///< Number of bytes actually transmitted from txData - uint32_t rxCnt; ///< Number of bytes stored in rxData + uint32_t txLen; ///< Number of bytes to be sent from txData + uint32_t rxLen; ///< Number of bytes to be stored in rxData + uint32_t txCnt; ///< Number of bytes actually transmitted from txData + uint32_t rxCnt; ///< Number of bytes stored in rxData - spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete + spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete }; /* ************************************************************************* */ @@ -172,8 +173,8 @@ * @return If successful, the actual clock frequency is returned. Otherwise, see * \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel); +int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel); /** * @brief Disable and shutdown SPI peripheral. @@ -182,7 +183,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_Shutdown (mxc_spi_regs_t* spi); +int MXC_SPI_Shutdown(mxc_spi_regs_t *spi); /** * @brief Checks if the given SPI bus can be placed in sleep mode. @@ -196,7 +197,7 @@ * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi); +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi); /** * @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance. @@ -205,7 +206,7 @@ * * @return Frequency of the clock used as the bit rate generator */ -int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi); +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi); /** * @brief Set the frequency of the SPI interface. @@ -218,7 +219,7 @@ * @return Negative if error, otherwise actual speed set. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SetFrequency (mxc_spi_regs_t* spi, unsigned int hz); +int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz); /** * @brief Get the frequency of the SPI interface. @@ -229,7 +230,7 @@ * * @return The SPI bus frequency in Hertz */ -unsigned int MXC_SPI_GetFrequency (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi); /** * @brief Sets the number of bits per character @@ -239,7 +240,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize); +int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize); /** * @brief Gets the number of bits per character @@ -248,8 +249,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_GetDataSize (mxc_spi_regs_t* spi); - +int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi); /* ************************************************************************* */ /* Low-level functions */ @@ -265,7 +265,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetSlave (mxc_spi_regs_t* spi, int ssIdx); +int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx); /** * @brief Gets the slave select (SS) line used for transmissions @@ -276,7 +276,7 @@ * * @return slave slect */ -int MXC_SPI_GetSlave (mxc_spi_regs_t* spi); +int MXC_SPI_GetSlave(mxc_spi_regs_t *spi); /** * @brief Sets the SPI width used for transmissions @@ -286,7 +286,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetWidth (mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth); +int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth); /** * @brief Gets the SPI width used for transmissions @@ -295,7 +295,7 @@ * * @return Spi Width \ref mxc_spi_width_t */ -mxc_spi_width_t MXC_SPI_GetWidth (mxc_spi_regs_t* spi); +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi); /** * @brief Sets the spi mode using clock polarity and clock phase @@ -305,7 +305,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode); +int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode); /** * @brief Gets the spi mode @@ -314,7 +314,7 @@ * * @return mxc_spi_mode_t \ref mxc_spi_mode_t */ -mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi); +mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi); /** * @brief Starts a SPI Transmission @@ -328,7 +328,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_StartTransmission (mxc_spi_regs_t* spi); +int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi); /** * @brief Checks the SPI Peripheral for an ongoing transmission @@ -339,7 +339,7 @@ * * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_GetActive (mxc_spi_regs_t* spi); +int MXC_SPI_GetActive(mxc_spi_regs_t *spi); /** * @brief Aborts an ongoing SPI Transmission @@ -350,7 +350,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi); +int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi); /** * @brief Unloads bytes from the receive FIFO. @@ -361,8 +361,7 @@ * * @return The number of bytes actually read. */ -unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes, - unsigned int len); +unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); /** * @brief Get the number of bytes currently available in the receive FIFO. @@ -371,7 +370,7 @@ * * @return The number of bytes available. */ -unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi); /** * @brief Loads bytes into the transmit FIFO. @@ -382,8 +381,7 @@ * * @return The number of bytes actually written. */ -unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes, - unsigned int len); +unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); /** * @brief Get the amount of free space available in the transmit FIFO. @@ -392,21 +390,21 @@ * * @return The number of bytes available. */ -unsigned int MXC_SPI_GetTXFIFOAvailable (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi); /** * @brief Removes and discards all bytes currently in the receive FIFO. * * @param spi Pointer to SPI registers (selects the SPI block used.) */ -void MXC_SPI_ClearRXFIFO (mxc_spi_regs_t* spi); +void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi); /** * @brief Removes and discards all bytes currently in the transmit FIFO. * * @param spi Pointer to SPI registers (selects the SPI block used.) */ -void MXC_SPI_ClearTXFIFO (mxc_spi_regs_t* spi); +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); /** * @brief Set the receive threshold level. @@ -425,7 +423,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetRXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes); +int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); /** * @brief Get the current receive threshold level. @@ -434,7 +432,7 @@ * * @return The receive threshold value (in bytes). */ -unsigned int MXC_SPI_GetRXThreshold (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); /** * @brief Set the transmit threshold level. @@ -453,7 +451,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetTXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes); +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); /** * @brief Get the current transmit threshold level. @@ -462,7 +460,7 @@ * * @return The transmit threshold value (in bytes). */ -unsigned int MXC_SPI_GetTXThreshold (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); /** * @brief Gets the interrupt flags that are currently set @@ -474,7 +472,7 @@ * * @return The interrupt flags */ -unsigned int MXC_SPI_GetFlags (mxc_spi_regs_t* spi); +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi); /** * @brief Clears the interrupt flags that are currently set @@ -484,7 +482,7 @@ * * @param spi Pointer to SPI registers (selects the SPI block used.) */ -void MXC_SPI_ClearFlags (mxc_spi_regs_t* spi); +void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi); /** * @brief Enables specific interrupts @@ -495,7 +493,7 @@ * @param spi Pointer to SPI registers (selects the SPI block used.) * @param mask The interrupts to be enabled */ -void MXC_SPI_EnableInt (mxc_spi_regs_t* spi, unsigned int mask); +void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int mask); /** * @brief Disables specific interrupts @@ -506,7 +504,7 @@ * @param spi Pointer to SPI registers (selects the SPI block used.) * @param mask The interrupts to be disabled */ -void MXC_SPI_DisableInt (mxc_spi_regs_t* spi, unsigned int mask); +void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int mask); /* ************************************************************************* */ /* Transaction level functions */ @@ -535,7 +533,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_MasterTransaction (mxc_spi_req_t* req); +int MXC_SPI_MasterTransaction(mxc_spi_req_t *req); /** * @brief Setup an interrupt-driven SPI transaction @@ -547,7 +545,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_MasterTransactionAsync (mxc_spi_req_t* req); +int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req); /** * @brief Setup a DMA driven SPI transaction @@ -564,7 +562,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_MasterTransactionDMA (mxc_spi_req_t* req); +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req); /** * @brief Performs a blocking SPI transaction. @@ -581,7 +579,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SlaveTransaction (mxc_spi_req_t* req); +int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req); /** * @brief Setup an interrupt-driven SPI transaction @@ -593,7 +591,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SlaveTransactionAsync (mxc_spi_req_t* req); +int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req); /** * @brief Setup a DMA driven SPI transaction @@ -610,7 +608,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SlaveTransactionDMA (mxc_spi_req_t* req); +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req); /** * @brief Sets the TX data to transmit as a 'dummy' byte @@ -623,7 +621,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetDefaultTXData (mxc_spi_regs_t* spi, unsigned int defaultTXData); +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData); /** * @brief Abort any asynchronous requests in progress. @@ -634,7 +632,7 @@ * * @param spi Pointer to SPI registers (selects the SPI block used.) */ -void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi); +void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi); /** * @brief The processing function for asynchronous transactions. @@ -645,7 +643,7 @@ * * @param spi Pointer to SPI registers (selects the SPI block used.) */ -void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi); +void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi); /**@} end of group spi */ @@ -653,4 +651,4 @@ } #endif -#endif /* _PT_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_SPI_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h index f5df5da..d26e94e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h @@ -3,8 +3,8 @@ * @brief System level header file. */ -/******************************************************************************* - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -36,8 +36,8 @@ * ******************************************************************************/ -#ifndef _MXC_MXC_SYS_H_ -#define _MXC_MXC_SYS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_SYS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_SYS_H_ #include "mxc_device.h" #include "gcr_regs.h" @@ -49,85 +49,196 @@ /** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */ typedef enum { - MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */ - MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */ - MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ - MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */ - MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TIMER0 */ - MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TIMER1 */ - MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TIMER2 */ - MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TIMER3 */ - MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */ - MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */ - MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */ - MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */ - MXC_SYS_RESET0_SPI2 = MXC_F_GCR_RST0_SPI2_POS, /**< Reset SPI2 */ - MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */ - MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */ - MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */ - MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */ - MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ - MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ - MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */ + MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */ + MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */ + MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ + MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */ + MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TIMER0 */ + MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TIMER1 */ + MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TIMER2 */ + MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TIMER3 */ + MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */ + MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */ + MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */ + MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */ + MXC_SYS_RESET0_SPI2 = MXC_F_GCR_RST0_SPI2_POS, /**< Reset SPI2 */ + MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */ + MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */ + MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */ + MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ + MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ + MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */ /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */ - MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */ - MXC_SYS_RESET1_WDT1 = (MXC_F_GCR_RST1_WDT1_POS + 32), /**< Reset WDT1 */ - MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset WDT1 */ - MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset WDT1 */ - MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset */ - MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset */ + MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */ + MXC_SYS_RESET1_WDT1 = (MXC_F_GCR_RST1_WDT1_POS + 32), /**< Reset WDT1 */ + MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */ + MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */ + MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset I2C2*/ + MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S*/ /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */ - MXC_SYS_RESET_TMR4 = (MXC_F_MCR_RST_LPTMR0_POS + 64), /**< Reset TMR4 */ - MXC_SYS_RESET_TMR5 = (MXC_F_MCR_RST_LPTMR1_POS + 64), /**< Reset TMR5 */ - MXC_SYS_RESET_UART3 = (MXC_F_MCR_RST_LPUART0_POS + 64), /**< Reset UART3 */ + MXC_SYS_RESET_TMR4 = (MXC_F_MCR_RST_LPTMR0_POS + 64), /**< Reset TMR4 */ + MXC_SYS_RESET_TMR5 = (MXC_F_MCR_RST_LPTMR1_POS + 64), /**< Reset TMR5 */ + MXC_SYS_RESET_UART3 = (MXC_F_MCR_RST_LPUART0_POS + 64), /**< Reset UART3 */ + MXC_SYS_RESET_RTC = (MXC_F_MCR_RST_RTC_POS + 64), /**< Reset RTC */ } mxc_sys_reset_t; /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ typedef enum { - MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */ - MXC_SYS_PERIPH_CLOCK_GPIO1 = MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */ - MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */ - MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLKDIS0_SPI0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */ - MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */ - MXC_SYS_PERIPH_CLOCK_SPI2 = MXC_F_GCR_PCLKDIS0_SPI2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI2 clock */ - MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */ - MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */ - MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */ - MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */ - MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */ - MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */ - MXC_SYS_PERIPH_CLOCK_TMR3 = MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */ - MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */ + MXC_SYS_PERIPH_CLOCK_GPIO0 = + MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */ + MXC_SYS_PERIPH_CLOCK_GPIO1 = + MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */ + MXC_SYS_PERIPH_CLOCK_DMA = + MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */ + MXC_SYS_PERIPH_CLOCK_SPI0 = + MXC_F_GCR_PCLKDIS0_SPI0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */ + MXC_SYS_PERIPH_CLOCK_SPI1 = + MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */ + MXC_SYS_PERIPH_CLOCK_SPI2 = + MXC_F_GCR_PCLKDIS0_SPI2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI2 clock */ + MXC_SYS_PERIPH_CLOCK_UART0 = + MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */ + MXC_SYS_PERIPH_CLOCK_UART1 = + MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */ + MXC_SYS_PERIPH_CLOCK_I2C0 = + MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */ + MXC_SYS_PERIPH_CLOCK_TMR0 = + MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */ + MXC_SYS_PERIPH_CLOCK_TMR1 = + MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */ + MXC_SYS_PERIPH_CLOCK_TMR2 = + MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */ + MXC_SYS_PERIPH_CLOCK_TMR3 = + MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */ + MXC_SYS_PERIPH_CLOCK_I2C1 = + MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */ /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ - MXC_SYS_PERIPH_CLOCK_UART2 = (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */ - MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */ - MXC_SYS_PERIPH_CLOCK_WDT0 = (MXC_F_GCR_PCLKDIS1_WWDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */ - MXC_SYS_PERIPH_CLOCK_WDT1 = (MXC_F_GCR_PCLKDIS1_WWDT1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */ - MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLKDIS1_ICC0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_ICACHE clock */ - MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */ - MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */ - MXC_SYS_PERIPH_CLOCK_I2C2 = (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */ - MXC_SYS_PERIPH_CLOCK_I2S = (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */ + MXC_SYS_PERIPH_CLOCK_UART2 = + (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */ + MXC_SYS_PERIPH_CLOCK_TRNG = + (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */ + MXC_SYS_PERIPH_CLOCK_WDT0 = + (MXC_F_GCR_PCLKDIS1_WWDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */ + MXC_SYS_PERIPH_CLOCK_WDT1 = + (MXC_F_GCR_PCLKDIS1_WWDT1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */ + MXC_SYS_PERIPH_CLOCK_ICACHE = + (MXC_F_GCR_PCLKDIS1_ICC0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_ICACHE clock */ + MXC_SYS_PERIPH_CLOCK_CRC = + (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */ + MXC_SYS_PERIPH_CLOCK_AES = + (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */ + MXC_SYS_PERIPH_CLOCK_I2C2 = + (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */ + MXC_SYS_PERIPH_CLOCK_I2S = + (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */ /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */ - MXC_SYS_PERIPH_CLOCK_TMR4 = (MXC_F_MCR_CLKDIS_LPTMR0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */ - MXC_SYS_PERIPH_CLOCK_TMR5 = (MXC_F_MCR_CLKDIS_LPTMR1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */ - MXC_SYS_PERIPH_CLOCK_UART3 = (MXC_F_MCR_CLKDIS_LPUART0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */ + MXC_SYS_PERIPH_CLOCK_TMR4 = + (MXC_F_MCR_CLKDIS_LPTMR0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */ + MXC_SYS_PERIPH_CLOCK_TMR5 = + (MXC_F_MCR_CLKDIS_LPTMR1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */ + MXC_SYS_PERIPH_CLOCK_UART3 = + (MXC_F_MCR_CLKDIS_LPUART0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */ } mxc_sys_periph_clock_t; /** @brief Enumeration to select System Clock source */ typedef enum { - MXC_SYS_CLOCK_IPO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, - MXC_SYS_CLOCK_IBRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO, - MXC_SYS_CLOCK_ERFO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO, - MXC_SYS_CLOCK_INRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, - MXC_SYS_CLOCK_ERTCO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, - MXC_SYS_CLOCK_EXTCLK = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK + MXC_SYS_CLOCK_IPO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, + MXC_SYS_CLOCK_IBRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO, + MXC_SYS_CLOCK_ERFO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO, + MXC_SYS_CLOCK_INRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, + MXC_SYS_CLOCK_ERTCO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, + MXC_SYS_CLOCK_EXTCLK = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK } mxc_sys_system_clock_t; -#define MXC_SYS_USN_CHECKSUM_LEN 16 +#define MXC_SYS_USN_CHECKSUM_LEN 16 /***** Function Prototypes *****/ +typedef struct { + int ie_status; + int in_critical; +} mxc_crit_state_t; + +static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 }; + +static inline void _mxc_crit_get_state() +{ +#ifdef __CORTEX_M + /* + On ARM M the 0th bit of the Priority Mask register indicates + whether interrupts are enabled or not. + + 0 = enabled + 1 = disabled + */ + uint32_t primask = __get_PRIMASK(); + _state.ie_status = (primask == 0); +#endif +#ifdef __riscv + /* + On RISC-V bit position 3 (Machine Interrupt Enable) of the + mstatus register indicates whether interrupts are enabled. + + 0 = disabled + 1 = enabled + */ + uint32_t mstatus = get_mstatus(); + _state.ie_status = ((mstatus & (1 << 3)) != 0); +#endif +} + +/** + * @brief Enter a critical section of code that cannot be interrupted. + */ +static inline void MXC_SYS_Crit_Enter(void) +{ + _mxc_crit_get_state(); + if (_state.ie_status) + __disable_irq(); + _state.in_critical = 1; +} + +/** + * @brief Exit a critical section of code, re-enabling interrupts if they + * were previously. + */ +static inline void MXC_SYS_Crit_Exit(void) +{ + if (_state.ie_status) { + __enable_irq(); + } + _state.in_critical = 0; + _mxc_crit_get_state(); + /* + ^ Reset the state again to prevent edge case + where interrupts get disabled, then Crit_Exit() gets + called, which would inadvertently re-enable interrupts + from old state. + */ +} + +/** + * @brief Polls whether code is currently executing from a critical section. + * @returns 1 if code is currently in a critical section (interrupts are disabled). + * 0 if code is not in a critical section. + */ +static inline int MXC_SYS_In_Crit_Section(void) +{ + return _state.in_critical; +} + +/** + * @brief Macro for wrapping a section of code to make it critical. Note: this macro + * does not support nesting. + */ +// clang-format off +#define MXC_CRITICAL(code) { \ + MXC_SYS_Crit_Enter();\ + code;\ + MXC_SYS_Crit_Exit();\ +} +// clang-format on + /** * @brief Reads the device USN. * @param usn Pointer to store the USN. @@ -141,25 +252,25 @@ * @param clock Enumeration for desired clock. * @returns 0 is the clock is disabled, non 0 if the clock is enabled. */ -int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock); +int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock); /** * @brief Disables the selected peripheral clock. * @param clock Enumeration for desired clock. */ -void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock); +void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock); /** * @brief Enables the selected peripheral clock. * @param clock Enumeration for desired clock. */ -void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock); +void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock); /** * @brief Enables the 32kHz oscillator * @param mxc_sys_cfg Not used, may be NULL. */ -void MXC_SYS_RTCClockEnable (void); +void MXC_SYS_RTCClockEnable(void); /** * @brief Disables the 32kHz oscillator @@ -172,14 +283,14 @@ * @param clock The clock to enable * @return E_NO_ERROR if everything is successful */ -int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock); +int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock); /** * @brief Disable System Clock Source * @param clock The clock to disable * @return E_NO_ERROR if everything is successful */ -int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock); +int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock); /** * @brief Select the system clock. @@ -187,22 +298,22 @@ * @param tmr Optional tmr pointer for timeout. NULL if undesired. * @returns E_NO_ERROR if everything is successful. */ -int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock); +int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock); /** * @brief Wait for a clock to enable with timeout * @param ready The clock to wait for * @return E_NO_ERROR if ready, E_TIME_OUT if timeout */ -int MXC_SYS_Clock_Timeout (uint32_t ready); +int MXC_SYS_Clock_Timeout(uint32_t ready); /** * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register. * @param Enumeration for what to reset. Can reset multiple items at once. */ -void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset); +void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset); #ifdef __cplusplus } #endif -#endif /* _MXC_MXC_SYS_H_*/ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_SYS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/rtc.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/rtc.h index c24dae0..e6a0bc0 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/rtc.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/rtc.h @@ -3,8 +3,8 @@ * @brief Real Time Clock (RTC) functions and prototypes. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,17 +34,19 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _RTC_H_ -#define _RTC_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_RTC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_RTC_H_ /* **** Includes **** */ #include + #include "mxc_device.h" -#include "rtc_regs.h" #include "mxc_sys.h" +#include "rtc_regs.h" +#include "tmr_regs.h" #ifdef __cplusplus extern "C" { @@ -56,33 +58,36 @@ * @{ */ +#define MXC_RTC_MAX_SSEC (MXC_F_RTC_SSEC_SSEC + 1) +#define MXC_RTC_TRIM_TMR_IRQ MXC_F_TMR_INTFL_IRQ_A + /* **** Definitions **** */ /** * @brief Bitmasks for each of the RTC's Frequency. */ typedef enum { - MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ, ///< 1Hz (Compensated) - MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ, ///< 512Hz (Compensated) - MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ, ///< 4Khz - MXC_RTC_F_32KHZ = 32, ///< 32Khz + MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ, ///< 1Hz (Compensated) + MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ, ///< 512Hz (Compensated) + MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ, ///< 4Khz + MXC_RTC_F_32KHZ = 32, ///< 32Khz } mxc_rtc_freq_sel_t; /** * @brief Bitmasks for each of the RTC's interrupt enables. */ typedef enum { - MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_TOD_ALARM_IE, ///< Long-interval alarm interrupt enable - MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM_IE, ///< Short-interval alarm interrupt enable - MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDY_IE, ///< Timer ready interrupt enable + MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_TOD_ALARM_IE, ///< Long-interval alarm interrupt enable + MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM_IE, ///< Short-interval alarm interrupt enable + MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDY_IE, ///< Timer ready interrupt enable } mxc_rtc_int_en_t; /** * @brief Bitmasks for each of the RTC's interrupt flags. */ typedef enum { - MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM, ///< Long-interval alarm interrupt flag - MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM, ///< Short-interval alarm interrupt flag - MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag + MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM, ///< Long-interval alarm interrupt flag + MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM, ///< Short-interval alarm interrupt flag + MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag } mxc_rtc_int_fl_t; /** @@ -90,7 +95,7 @@ * @param ras 20-bit value 0-0xFFFFF * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_SetTimeofdayAlarm (uint32_t ras); +int MXC_RTC_SetTimeofdayAlarm(uint32_t ras); /** * @brief Set Sub-Second alarm value and enable interrupt, @@ -98,46 +103,46 @@ * @param rssa 32-bit value 0-0xFFFFFFFF * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_SetSubsecondAlarm (uint32_t rssa); +int MXC_RTC_SetSubsecondAlarm(uint32_t rssa); /** * @brief Start the Real Time Clock (Blocking function) * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_Start (void); +int MXC_RTC_Start(void); /** * @brief Stop the Real Time Clock (Blocking function) * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_Stop (void); +int MXC_RTC_Stop(void); /** * @brief Initialize the sec and ssec registers and enable RTC (Blocking function) * @param sec set the RTC Sec counter (32-bit) - * @param ssec set the RTC Sub-second counter (8-bit) + * @param ssec set the RTC Sub-second counter (12-bit) * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_Init (uint32_t sec, uint8_t ssec); +int MXC_RTC_Init(uint32_t sec, uint16_t ssec); /** * @brief Allow generation of Square Wave on the SQW pin (Blocking function) * @param fq Frequency output selection * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_SquareWaveStart (mxc_rtc_freq_sel_t fq); - +int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq); + /** * @brief Stop the generation of square wave (Blocking function) * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_SquareWaveStop (void); +int MXC_RTC_SquareWaveStop(void); /** * @brief Set Trim register value (Blocking function) * @param trm set the RTC Trim (8-bit, +/- 127) * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_Trim (int8_t trm); +int MXC_RTC_Trim(int8_t trm); /** * @brief Enable Interurpts (Blocking function) @@ -145,7 +150,7 @@ * See #mxc_rtc_int_en_t for available choices. * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_EnableInt (uint32_t mask); +int MXC_RTC_EnableInt(uint32_t mask); /** * @brief Disable Interurpts (Blocking function) @@ -153,7 +158,7 @@ * See #mxc_rtc_int_en_t for available choices. * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_DisableInt (uint32_t mask); +int MXC_RTC_DisableInt(uint32_t mask); /** * @brief Gets interrupt flags. @@ -161,7 +166,7 @@ * currently set. See \ref mxc_rtc_int_fl_t for the list * of possible flags. */ -int MXC_RTC_GetFlags (void); +int MXC_RTC_GetFlags(void); /** * @brief Clear interrupt flags. @@ -169,19 +174,19 @@ * See #mxc_rtc_int_fl_t for the list of possible flags. * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_ClearFlags (int flags); +int MXC_RTC_ClearFlags(int flags); /** * @brief Get SubSecond * @retval Returns subsecond value or E_BUSY, see /ref MXC_ERROR_CODES */ -int MXC_RTC_GetSubSecond (void); +int MXC_RTC_GetSubSecond(void); /** * @brief Get Second * @retval returns second value or E_BUSY, see /ref MXC_ERROR_CODES */ -int MXC_RTC_GetSecond (void); +int MXC_RTC_GetSecond(void); /** * @brief Get the time using nuclear fusion. Or atomically. Something like that. @@ -189,7 +194,7 @@ * @param subsec pointer to store subseconds value * @retval returns Success or Fail, see \ref MXC_Error_Codes */ -int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec); +int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec); /** * @brief Get RTC busy flag. @@ -197,9 +202,21 @@ */ int MXC_RTC_GetBusyFlag(void); +/** + * @brief Calculate and set the appropriate RTC trim value based on an accurate reference clock + * + * @param tmr Timer available to be used to measure known time periods over which the RTC ticks are counted + * + * @retval returns Success or Fail, see \ref MXC_Error_Codes + * + * @note If RTC running before calling this function and interrupts enabled, accuracy of trimming could be affected + * @note External 32MHz must be installed and calibrated properly for this function to be successful + */ +int MXC_RTC_TrimCrystal(mxc_tmr_regs_t *tmr); + /**@} end of group rtc */ #ifdef __cplusplus } #endif -#endif /* _RTC_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_RTC_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/tmr.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/tmr.h index c720b04..100b1c3 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/tmr.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/tmr.h @@ -3,8 +3,8 @@ * @brief Timer (TMR) function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,19 +34,20 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _TMR_H_ -#define _TMR_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TMR_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TMR_H_ /* **** Includes **** */ +#include +#include #include "mxc_device.h" #include "tmr_regs.h" #include "mxc_sys.h" #include "gcr_regs.h" #include "mcr_regs.h" -#include "stdbool.h" #ifdef __cplusplus extern "C" { @@ -62,33 +63,33 @@ * @brief Timer prescaler values */ typedef enum { - TMR_PRES_1 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1, ///< Divide input clock by 1 - TMR_PRES_2 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2, ///< Divide input clock by 2 - TMR_PRES_4 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4, ///< Divide input clock by 4 - TMR_PRES_8 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8, ///< Divide input clock by 8 - TMR_PRES_16 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16, ///< Divide input clock by 16 - TMR_PRES_32 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32, ///< Divide input clock by 32 - TMR_PRES_64 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64, ///< Divide input clock by 64 - TMR_PRES_128 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128, ///< Divide input clock by 128 - TMR_PRES_256 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256, ///< Divide input clock by 256 - TMR_PRES_512 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512, ///< Divide input clock by 512 - TMR_PRES_1024 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024, ///< Divide input clock by 1024 - TMR_PRES_2048 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048, ///< Divide input clock by 2048 - TMR_PRES_4096 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ///< Divide input clock by 4096 + TMR_PRES_1 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1, ///< Divide input clock by 1 + TMR_PRES_2 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2, ///< Divide input clock by 2 + TMR_PRES_4 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4, ///< Divide input clock by 4 + TMR_PRES_8 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8, ///< Divide input clock by 8 + TMR_PRES_16 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16, ///< Divide input clock by 16 + TMR_PRES_32 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32, ///< Divide input clock by 32 + TMR_PRES_64 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64, ///< Divide input clock by 64 + TMR_PRES_128 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128, ///< Divide input clock by 128 + TMR_PRES_256 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256, ///< Divide input clock by 256 + TMR_PRES_512 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512, ///< Divide input clock by 512 + TMR_PRES_1024 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024, ///< Divide input clock by 1024 + TMR_PRES_2048 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048, ///< Divide input clock by 2048 + TMR_PRES_4096 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ///< Divide input clock by 4096 } mxc_tmr_pres_t; /** * @brief Timer modes */ typedef enum { - TMR_MODE_ONESHOT = MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT, ///< Timer Mode ONESHOT - TMR_MODE_CONTINUOUS = MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS, ///< Timer Mode CONTINUOUS - TMR_MODE_COUNTER = MXC_S_TMR_CTRL0_MODE_A_COUNTER, ///< Timer Mode COUNTER - TMR_MODE_PWM = MXC_S_TMR_CTRL0_MODE_A_PWM, ///< Timer Mode PWM - TMR_MODE_CAPTURE = MXC_S_TMR_CTRL0_MODE_A_CAPTURE, ///< Timer Mode CAPTURE - TMR_MODE_COMPARE = MXC_S_TMR_CTRL0_MODE_A_COMPARE, ///< Timer Mode COMPARE - TMR_MODE_GATED = MXC_S_TMR_CTRL0_MODE_A_GATED, ///< Timer Mode GATED - TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CTRL0_MODE_A_CAPCOMP ///< Timer Mode CAPTURECOMPARE + TMR_MODE_ONESHOT = MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT, ///< Timer Mode ONESHOT + TMR_MODE_CONTINUOUS = MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS, ///< Timer Mode CONTINUOUS + TMR_MODE_COUNTER = MXC_S_TMR_CTRL0_MODE_A_COUNTER, ///< Timer Mode COUNTER + TMR_MODE_PWM = MXC_S_TMR_CTRL0_MODE_A_PWM, ///< Timer Mode PWM + TMR_MODE_CAPTURE = MXC_S_TMR_CTRL0_MODE_A_CAPTURE, ///< Timer Mode CAPTURE + TMR_MODE_COMPARE = MXC_S_TMR_CTRL0_MODE_A_COMPARE, ///< Timer Mode COMPARE + TMR_MODE_GATED = MXC_S_TMR_CTRL0_MODE_A_GATED, ///< Timer Mode GATED + TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CTRL0_MODE_A_CAPCOMP ///< Timer Mode CAPTURECOMPARE } mxc_tmr_mode_t; /** @@ -96,19 +97,19 @@ * */ typedef enum { - TMR_BIT_MODE_32, ///< Timer Mode 32 bit - TMR_BIT_MODE_16A, ///< Timer Mode Lower 16 bit - TMR_BIT_MODE_16B, ///< Timer Mode Upper 16 bit + TMR_BIT_MODE_32, ///< Timer Mode 32 bit + TMR_BIT_MODE_16A, ///< Timer Mode Lower 16 bit + TMR_BIT_MODE_16B, ///< Timer Mode Upper 16 bit } mxc_tmr_bit_mode_t; /** * @brief Timer units of time enumeration */ typedef enum { - TMR_UNIT_NANOSEC, ///< Nanosecond Unit Indicator - TMR_UNIT_MICROSEC, ///< Microsecond Unit Indicator - TMR_UNIT_MILLISEC, ///< Millisecond Unit Indicator - TMR_UNIT_SEC, ///< Second Unit Indicator + TMR_UNIT_NANOSEC, ///< Nanosecond Unit Indicator + TMR_UNIT_MICROSEC, ///< Microsecond Unit Indicator + TMR_UNIT_MILLISEC, ///< Millisecond Unit Indicator + TMR_UNIT_SEC, ///< Second Unit Indicator } mxc_tmr_unit_t; /** @@ -117,28 +118,28 @@ * 32K and 80K clocks can only be used for Timers 4 and 5 */ typedef enum { - MXC_TMR_APB_CLK, ///< PCLK CLock - MXC_TMR_EXT_CLK, ///< External Clock - MXC_TMR_8M_CLK , ///< 8MHz Clock - MXC_TMR_32M_CLK, ///< 32MHz Clock - MXC_TMR_32K_CLK, ///< 32KHz Clock - MXC_TMR_80K_CLK, ///< 80KHz Clock + MXC_TMR_APB_CLK, ///< PCLK CLock + MXC_TMR_EXT_CLK, ///< External Clock + MXC_TMR_8M_CLK, ///< 8MHz Clock + MXC_TMR_32M_CLK, ///< 32MHz Clock + MXC_TMR_32K_CLK, ///< 32KHz Clock + MXC_TMR_80K_CLK, ///< 80KHz Clock } mxc_tmr_clock_t; /** * @brief Timer Configuration */ typedef struct { - mxc_tmr_pres_t pres; ///< Desired timer prescaler - mxc_tmr_mode_t mode; ///< Desired timer mode - mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits - mxc_tmr_clock_t clock; ///< Desired clock source - uint32_t cmp_cnt; ///< Compare register value in timer ticks - unsigned pol; ///< Polarity (0 or 1) + mxc_tmr_pres_t pres; ///< Desired timer prescaler + mxc_tmr_mode_t mode; ///< Desired timer mode + mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits + mxc_tmr_clock_t clock; ///< Desired clock source + uint32_t cmp_cnt; ///< Compare register value in timer ticks + unsigned pol; ///< Polarity (0 or 1) } mxc_tmr_cfg_t; /* **** Definitions **** */ -typedef void (*mxc_tmr_complete_t) (int error); +typedef void (*mxc_tmr_complete_t)(int error); /* **** Function Prototypes **** */ @@ -151,25 +152,25 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TMR_Init (mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg, bool init_pins); +int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins); /** * @brief Shutdown timer module clock. * @param tmr Pointer to timer module to initialize. */ -void MXC_TMR_Shutdown (mxc_tmr_regs_t *tmr); +void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr); /** * @brief Start the timer counting. * @param tmr Pointer to timer module to initialize. */ -void MXC_TMR_Start (mxc_tmr_regs_t* tmr); +void MXC_TMR_Start(mxc_tmr_regs_t *tmr); /** * @brief Stop the timer. * @param tmr Pointer to timer module to initialize. */ -void MXC_TMR_Stop (mxc_tmr_regs_t* tmr); +void MXC_TMR_Stop(mxc_tmr_regs_t *tmr); /** * @brief Set the value of the first transition in PWM mode @@ -178,28 +179,28 @@ * @note Will block until safe to change the period count. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TMR_SetPWM (mxc_tmr_regs_t* tmr, uint32_t pwm); +int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm); /** * @brief Get the timer compare count. * @param tmr Pointer to timer module to initialize. * @return Returns the current compare count. */ -uint32_t MXC_TMR_GetCompare (mxc_tmr_regs_t* tmr); +uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr); /** * @brief Get the timer capture count. * @param tmr Pointer to timer module to initialize. * @return Returns the most recent capture count. */ -uint32_t MXC_TMR_GetCapture (mxc_tmr_regs_t* tmr); +uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr); /** * @brief Get the timer count. * @param tmr Pointer to timer module to initialize. * @return Returns the current count. */ -uint32_t MXC_TMR_GetCount (mxc_tmr_regs_t* tmr); +uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr); /** * @brief Calculate count for required frequency. @@ -209,34 +210,35 @@ * @param frequency required frequency. * @return Returns the period count. */ -uint32_t MXC_TMR_GetPeriod (mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency); +uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar, + uint32_t frequency); /** * @brief Clear the timer interrupt. * @param tmr Pointer to timer module to initialize. */ -void MXC_TMR_ClearFlags (mxc_tmr_regs_t* tmr); +void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr); /** * @brief Get the timer interrupt status. * @param tmr Pointer to timer module to initialize. * @return Returns the interrupt status. 1 if interrupt has occured. */ -uint32_t MXC_TMR_GetFlags (mxc_tmr_regs_t* tmr); +uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr); /** * @brief enable interupt * * @param tmr Pointer to timer module to initialize. */ -void MXC_TMR_EnableInt (mxc_tmr_regs_t* tmr); +void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr); /** * @brief disable interupt * * @param tmr Pointer to timer module to initialize. */ -void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr); +void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr); /** * @brief Enable wakeup from sleep @@ -244,7 +246,7 @@ * @param tmr Pointer to timer module to initialize. * @param cfg System configuration object */ -void MXC_TMR_EnableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg); +void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg); /** * @brief Disable wakeup from sleep @@ -252,7 +254,7 @@ * @param tmr Pointer to timer module to initialize. * @param cfg System configuration object */ -void MXC_TMR_DisableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg); +void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg); /** * @brief Set the timer compare count. @@ -260,14 +262,14 @@ * @param cmp_cnt New compare count. * @note In PWM Mode use this to set the value of the second transition. */ -void MXC_TMR_SetCompare (mxc_tmr_regs_t *tmr, uint32_t cmp_cnt); +void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt); /** * @brief Set the timer count. * @param tmr Pointer to timer module to initialize. * @param cnt New count. */ -void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt); +void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt); /** * @brief Dealay for a set periord of time measured in microseconds @@ -275,7 +277,7 @@ * @param tmr The timer * @param us microseconds to delay for */ -void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us); +void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us); /** * @brief Start a timer that will time out after a certain number of microseconds @@ -284,7 +286,7 @@ * @param tmr The timer * @param us microseconds to time out after */ -void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us); +void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us); /** * @brief Check on time out timer @@ -293,21 +295,21 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TMR_TO_Check (mxc_tmr_regs_t *tmr); +int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr); /** * @brief Stop the Timeout timer * * @param tmr The timer */ -void MXC_TMR_TO_Stop (mxc_tmr_regs_t *tmr); +void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr); /** * @brief Clear timeout timer back to zero * * @param tmr The timer */ -void MXC_TMR_TO_Clear (mxc_tmr_regs_t *tmr); +void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr); /** * @brief Get elapsed time of timeout timer @@ -316,7 +318,7 @@ * * @return Time that has elapsed in timeout timer */ -unsigned int MXC_TMR_TO_Elapsed (mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr); /** * @brief Amount of time remaining until timeour @@ -325,14 +327,14 @@ * * @return Time that is left until timeout */ -unsigned int MXC_TMR_TO_Remaining (mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr); /** * @brief Start stopwatch * * @param tmr The timer */ -void MXC_TMR_SW_Start (mxc_tmr_regs_t *tmr); +void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr); /** * @brief Stopwatch stop @@ -341,7 +343,7 @@ * * @return the time when the stopwatch is stopped. */ -unsigned int MXC_TMR_SW_Stop (mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr); /** * @brief Get time from timer @@ -353,7 +355,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); +int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); /**@} end of group tmr */ @@ -361,4 +363,4 @@ } #endif -#endif /* _TMR_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TMR_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/trng.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/trng.h index a864f41..44b0a3f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/trng.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/trng.h @@ -3,8 +3,8 @@ * @brief Random number generator driver. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,10 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _TRNG_H_ -#define _TRNG_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TRNG_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TRNG_H_ /***** Includes *****/ #include "trng_regs.h" @@ -52,9 +52,8 @@ * @{ */ - /***** Function Prototypes *****/ -typedef void (*mxc_trng_complete_t) (void* req, int result); +typedef void (*mxc_trng_complete_t)(void *req, int result); /* ************************************************************************* */ /* Global Control/Configuration functions */ @@ -65,32 +64,32 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TRNG_Init (void); +int MXC_TRNG_Init(void); /** * @brief Enable TRNG Interrupts * */ -void MXC_TRNG_EnableInt (); +void MXC_TRNG_EnableInt(); /** * @brief Disable TRNG Interrupts * */ -void MXC_TRNG_DisableInt (); +void MXC_TRNG_DisableInt(); /** * @brief Disable and reset portions of the TRNG * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TRNG_Shutdown (void); +int MXC_TRNG_Shutdown(void); /** * @brief This function should be called from the TRNG ISR Handler * when using Async functions */ -void MXC_TRNG_Handler (void); +void MXC_TRNG_Handler(void); /* ************************************************************************* */ /* True Random Number Generator (TRNG) functions */ @@ -101,7 +100,7 @@ * * @return A random 32-bit number */ -int MXC_TRNG_RandomInt (void); +int MXC_TRNG_RandomInt(void); /** * @brief Get a random number of length len @@ -111,7 +110,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_TRNG_Random (uint8_t* data, uint32_t len); +int MXC_TRNG_Random(uint8_t *data, uint32_t len); /** * @brief Get a random number of length len, do not block while generating data @@ -122,16 +121,25 @@ * @param callback Function that will be called when all data has been generated * */ -void MXC_TRNG_RandomAsync (uint8_t* data, uint32_t len, mxc_trng_complete_t callback); +void MXC_TRNG_RandomAsync(uint8_t *data, uint32_t len, mxc_trng_complete_t callback); /** * @brief Generate an AES key and transfer to the AES block */ void MXC_TRNG_GenerateKey(void); +/** + * @brief Perform health test of the TRNG entropy source + * + * @return If test fails the function will return E_BAD_STATE (-7), otherwise it will return E_NO_ERROR. + * + * @warning MAX32670 with Rev. A Silicon does not support health tests. (Check MXC_GCR->revision to see which revision your chip is.) + */ +int MXC_TRNG_HealthTest(void); + #ifdef __cplusplus } #endif /**@} end of group trng */ -#endif /* _TRNG_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TRNG_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h index 69092ca..08a4f25 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h @@ -3,8 +3,8 @@ * @brief Serial Peripheral Interface (UART) communications driver. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,16 +34,18 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ - - /* Define to prevent redundant inclusion */ -#ifndef _MXC_UART_H_ -#define _MXC_UART_H_ + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_UART_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_UART_H_ /***** Definitions *****/ #include "uart_regs.h" #include "mxc_sys.h" +#define UART_EXTCLK_FREQ EXTCLK_FREQ + #ifdef __cplusplus extern "C" { #endif @@ -60,8 +62,8 @@ * */ typedef enum { - MXC_UART_STOP_1, ///< UART Stop 1 clock cycle - MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters) + MXC_UART_STOP_1, ///< UART Stop 1 clock cycle + MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters) } mxc_uart_stop_t; /** @@ -69,11 +71,11 @@ * */ typedef enum { - MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled - MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based - MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based - MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based - MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based + MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled + MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based + MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based + MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based + MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based } mxc_uart_parity_t; /** @@ -81,21 +83,21 @@ * */ typedef enum { - MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled - MXC_UART_FLOW_EN, ///< UART Flow Control Enabled + MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled + MXC_UART_FLOW_EN, ///< UART Flow Control Enabled } mxc_uart_flow_t; /** * @brief Clock settings */ typedef enum { - MXC_UART_APB_CLK = 0, - MXC_UART_EXT_CLK = 1, + MXC_UART_APB_CLK = 0, + MXC_UART_EXT_CLK = 1, /*8M (IBRO) and 32M (EFRO) clocks can be used for UARTs 0,1 and 2*/ - MXC_UART_IBRO_CLK = 2, + MXC_UART_IBRO_CLK = 2, MXC_UART_ERFO_CLK = 3, /*32K (ERTCO) and INRO clocks can only be used for UART3*/ MXC_UART_ERTCO_CLK = 4, - MXC_UART_INRO_CLK = 5, + MXC_UART_INRO_CLK = 5, } mxc_uart_clock_t; /** @@ -104,7 +106,7 @@ * @param req The details of the transaction. * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t* req, int result); +typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t *req, int result); /** * @brief The callback routine used to indicate the transaction has terminated. @@ -113,7 +115,7 @@ * @param num The number of characters actually copied * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t* req, int num, int result); +typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t *req, int num, int result); /** * @brief The information required to perform a complete UART transaction @@ -122,21 +124,21 @@ * @note "callback" only needs to be initialized for interrupt driven (Async) and DMA transactions. */ struct _mxc_uart_req_t { - mxc_uart_regs_t* uart; /// 8 bits, use two bytes per character - ///< and pad the MSB of the upper byte with zeros - uint8_t *rxData; ///< Buffer to store received data For character sizes - ///< < 8 bits, pad the MSB of each byte with zeros. For - ///< character sizes > 8 bits, use two bytes per character - ///< and pad the MSB of the upper byte with zeros - uint32_t txLen; ///< Number of bytes to be sent from txData - uint32_t rxLen; ///< Number of bytes to be stored in rxData - volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData - volatile uint32_t rxCnt; ///< Number of bytes stored in rxData + mxc_uart_regs_t *uart; /// 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint8_t *rxData; ///< Buffer to store received data For character sizes + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint32_t txLen; ///< Number of bytes to be sent from txData + uint32_t rxLen; ///< Number of bytes to be stored in rxData + volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData + volatile uint32_t rxCnt; ///< Number of bytes stored in rxData - mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete + mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete }; /***** Function Prototypes *****/ @@ -164,7 +166,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Init(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clock, sys_map_t map); +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock, sys_map_t map); /** * @brief Disable and shutdown UART peripheral. @@ -173,7 +175,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Shutdown(mxc_uart_regs_t* uart); +int MXC_UART_Shutdown(mxc_uart_regs_t *uart); /** * @brief Checks if the given UART bus can be placed in sleep more. @@ -187,7 +189,7 @@ * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_ReadyForSleep(mxc_uart_regs_t* uart); +int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart); /** * @brief Set the frequency of the UART interface. @@ -199,7 +201,7 @@ * @return Negative if error, otherwise actual speed set. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_SetFrequency(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clock); +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); /** * @brief Get the frequency of the UART interface. @@ -210,7 +212,7 @@ * * @return The UART baud rate */ -int MXC_UART_GetFrequency(mxc_uart_regs_t* uart); +int MXC_UART_GetFrequency(mxc_uart_regs_t *uart); /** * @brief Sets the number of bits per character @@ -220,7 +222,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetDataSize(mxc_uart_regs_t* uart, int dataSize); +int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize); /** * @brief Sets the number of stop bits sent at the end of a character @@ -230,7 +232,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetStopBits(mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits); +int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits); /** * @brief Sets the type of parity generation used @@ -240,7 +242,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetParity(mxc_uart_regs_t* uart, mxc_uart_parity_t parity); +int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity); /** * @brief Sets the flow control used @@ -251,7 +253,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetFlowCtrl(mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold, sys_map_t map); +int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold, sys_map_t map); /** * @brief Sets the clock source for the baud rate generator @@ -262,7 +264,7 @@ * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes * for a list of return codes. */ -int MXC_UART_SetClockSource(mxc_uart_regs_t* uart, mxc_uart_clock_t clock); +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock); /* ************************************************************************* */ /* Low-level functions */ @@ -277,7 +279,7 @@ * * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_GetActive(mxc_uart_regs_t* uart); +int MXC_UART_GetActive(mxc_uart_regs_t *uart); /** * @brief Aborts an ongoing UART Transmission @@ -286,7 +288,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_AbortTransmission(mxc_uart_regs_t* uart); +int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart); /** * @brief Reads the next available character. If no character is available, this function @@ -296,7 +298,7 @@ * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t* uart); +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart); /** * @brief Writes a character on the UART. If the character cannot be written because the @@ -307,7 +309,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character); +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); /** * @brief Reads the next available character @@ -316,7 +318,7 @@ * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_ReadCharacter(mxc_uart_regs_t* uart); +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart); /** * @brief Writes a character on the UART @@ -326,7 +328,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character); +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); /** * @brief Reads the next available character @@ -339,7 +341,7 @@ * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Read(mxc_uart_regs_t* uart, uint8_t* buffer, int* len); +int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len); /** * @brief Writes a byte on the UART @@ -350,7 +352,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Write(mxc_uart_regs_t* uart, const uint8_t* byte, int* len); +int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len); /** * @brief Unloads bytes from the receive FIFO. @@ -361,8 +363,7 @@ * * @return The number of bytes actually read. */ -unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len); +unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len); /** * @brief Unloads bytes from the receive FIFO user DMA for longer reads. @@ -374,8 +375,8 @@ * * @return See \ref MXC_ERROR_CODES for a list of return values */ -int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback); +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback); /** * @brief Get the number of bytes currently available in the receive FIFO. @@ -384,7 +385,7 @@ * * @return The number of bytes available. */ -unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart); /** * @brief Loads bytes into the transmit FIFO. @@ -395,8 +396,8 @@ * * @return The number of bytes actually written. */ -unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t* uart, const unsigned char* bytes, - unsigned int len); +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, + unsigned int len); /** * @brief Loads bytes into the transmit FIFO using DMA for longer writes @@ -408,8 +409,8 @@ * * @return See \ref MXC_ERROR_CODES for a list of return values */ -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t* uart, const unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback); +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback); /** * @brief Get the amount of free space available in the transmit FIFO. @@ -418,7 +419,7 @@ * * @return The number of bytes available. */ -unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart); /** * @brief Removes and discards all bytes currently in the receive FIFO. @@ -427,7 +428,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_ClearRXFIFO(mxc_uart_regs_t* uart); +int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart); /** * @brief Removes and discards all bytes currently in the transmit FIFO. @@ -436,7 +437,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_ClearTXFIFO(mxc_uart_regs_t* uart); +int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart); /** * @brief Set the receive threshold level. @@ -455,7 +456,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetRXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes); +int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); /** * @brief Get the current receive threshold level. @@ -464,7 +465,7 @@ * * @return The receive threshold value (in bytes). */ -unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart); /** * @brief Set the transmit threshold level. @@ -483,7 +484,7 @@ * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetTXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes); +int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); /** * @brief Get the current transmit threshold level. @@ -492,7 +493,7 @@ * * @return The transmit threshold value (in bytes). */ -unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart); /** * @brief Gets the interrupt flags that are currently set @@ -504,7 +505,7 @@ * * @return The interrupt flags */ -unsigned int MXC_UART_GetFlags(mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart); /** * @brief Clears the interrupt flags that are currently set @@ -517,7 +518,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_ClearFlags(mxc_uart_regs_t* uart, unsigned int flags); +int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags); /** * @brief Enables specific interrupts @@ -530,7 +531,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_EnableInt(mxc_uart_regs_t* uart, unsigned int mask); +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask); /** * @brief Disables specific interrupts @@ -543,7 +544,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_DisableInt(mxc_uart_regs_t* uart, unsigned int mask); +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask); /** * @brief Gets the status flags that are currently set @@ -552,7 +553,7 @@ * * @return The status flags */ -unsigned int MXC_UART_GetStatus(mxc_uart_regs_t* uart); +unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart); /* ************************************************************************* */ /* Transaction level functions */ @@ -569,7 +570,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_Transaction(mxc_uart_req_t* req); +int MXC_UART_Transaction(mxc_uart_req_t *req); /** * @brief Setup an interrupt-driven UART transaction @@ -581,7 +582,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_TransactionAsync(mxc_uart_req_t* req); +int MXC_UART_TransactionAsync(mxc_uart_req_t *req); /** * @brief Setup a DMA driven UART transaction @@ -596,7 +597,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_TransactionDMA(mxc_uart_req_t* req); +int MXC_UART_TransactionDMA(mxc_uart_req_t *req); /** * @brief The processing function for DMA transactions. @@ -607,7 +608,7 @@ * @param ch DMA channel * @param error Error status */ -void MXC_UART_DMACallback (int ch, int error); +void MXC_UART_DMACallback(int ch, int error); /** * @brief Async callback @@ -617,7 +618,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal); +int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal); /** * @brief stop any async callbacks @@ -626,7 +627,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_AsyncStop (mxc_uart_regs_t* uart); +int MXC_UART_AsyncStop(mxc_uart_regs_t *uart); /** * @brief Abort any asynchronous requests in progress. @@ -639,7 +640,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_AbortAsync(mxc_uart_regs_t* uart); +int MXC_UART_AbortAsync(mxc_uart_regs_t *uart); /** * @brief The processing function for asynchronous transactions. @@ -652,7 +653,7 @@ * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_AsyncHandler(mxc_uart_regs_t* uart); +int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); /** * @brief Provide TXCount for asynchronous transactions.. @@ -661,7 +662,7 @@ * * @return Returns transmit bytes (in FIFO). */ -uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t* req); +uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req); /** * @brief Provide RXCount for asynchronous transactions.. @@ -670,7 +671,7 @@ * * @return Returns receive bytes (in FIFO). */ -uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t* req); +uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req); /**@} end of group uart */ @@ -678,4 +679,4 @@ } #endif -#endif /* _MXC_UART_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_UART_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/wdt.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/wdt.h index 2047507..183e440 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/wdt.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/wdt.h @@ -3,8 +3,8 @@ * @brief Watchdog timer (WDT) function prototypes and data types. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,15 +34,11 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef _WDT_H_ -#define _WDT_H_ - -#ifdef __CC_ARM -#pragma diag_suppress 66 // enumeration value is out of "int" range -#endif +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_WDT_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_WDT_H_ /* **** Includes **** */ #include @@ -64,22 +60,22 @@ /** @brief Watchdog upper limit period enumeration. Used to configure the period of the watchdog interrupt */ typedef enum { - MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31, ///< Period 2^31 - MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30, ///< Period 2^30 - MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29, ///< Period 2^29 - MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28, ///< Period 2^28 - MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27, ///< Period 2^27 - MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26, ///< Period 2^26 - MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25, ///< Period 2^25 - MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24, ///< Period 2^24 - MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23, ///< Period 2^23 - MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22, ///< Period 2^22 - MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21, ///< Period 2^21 - MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20, ///< Period 2^20 - MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19, ///< Period 2^19 - MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18, ///< Period 2^18 - MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17, ///< Period 2^17 - MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16, ///< Period 2^16 + MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31, ///< Period 2^31 + MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30, ///< Period 2^30 + MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29, ///< Period 2^29 + MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28, ///< Period 2^28 + MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27, ///< Period 2^27 + MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26, ///< Period 2^26 + MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25, ///< Period 2^25 + MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24, ///< Period 2^24 + MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23, ///< Period 2^23 + MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22, ///< Period 2^22 + MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21, ///< Period 2^21 + MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20, ///< Period 2^20 + MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19, ///< Period 2^19 + MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18, ///< Period 2^18 + MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17, ///< Period 2^17 + MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16, ///< Period 2^16 } mxc_wdt_period_t; /** @@ -110,11 +106,11 @@ * @brief Timer Configuration */ typedef struct { - mxc_wdt_mode_t mode; ///< WDT mode - mxc_wdt_period_t upperResetPeriod; ///< Reset upper limit - mxc_wdt_period_t lowerResetPeriod; ///< Reset lower limit - mxc_wdt_period_t upperIntPeriod; ///< Interrupt upper limit - mxc_wdt_period_t lowerIntPeriod; ///< Interrupt lower limit + mxc_wdt_mode_t mode; ///< WDT mode + mxc_wdt_period_t upperResetPeriod; ///< Reset upper limit + mxc_wdt_period_t lowerResetPeriod; ///< Reset lower limit + mxc_wdt_period_t upperIntPeriod; ///< Interrupt upper limit + mxc_wdt_period_t lowerIntPeriod; ///< Interrupt lower limit } mxc_wdt_cfg_t; /* **** Function Prototypes **** */ @@ -124,96 +120,96 @@ * @param cfg watchdog configuration * @return See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_WDT_Init (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg); +int MXC_WDT_Init(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg); /** * @brief Shutdown the Watchdog Timer * @param wdt Pointer to the watchdog registers * @return See \ref MXC_Error_Codes for the list of error codes. */ -int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt); +int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt); /** * @brief Set the period of the watchdog interrupt. * @param wdt Pointer to watchdog registers. * @param cfg watchdog configuration. */ -void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg); +void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg); /** * @brief Set the period of the watchdog reset. * @param wdt Pointer to watchdog registers. * @param cfg watchdog configuration. */ -void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg); +void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg); /** * @brief Enable the watchdog timer. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_Enable (mxc_wdt_regs_t* wdt); +void MXC_WDT_Enable(mxc_wdt_regs_t *wdt); /** * @brief Disable the watchdog timer. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_Disable (mxc_wdt_regs_t* wdt); +void MXC_WDT_Disable(mxc_wdt_regs_t *wdt); /** * @brief Enable the watchdog interrupt. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt); +void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt); /** * @brief Disable the watchdog interrupt. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt); +void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt); /** * @brief Enable the watchdog reset. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt); +void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt); /** * @brief Disable the watchdog reset. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt); +void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt); /** * @brief Reset the watchdog timer. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_ResetTimer (mxc_wdt_regs_t* wdt); +void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt); /** * @brief Get the status of the reset flag. * @param wdt Pointer to watchdog registers. * @returns 1 if the previous reset was caused by the watchdog, 0 otherwise. */ -int MXC_WDT_GetResetFlag (mxc_wdt_regs_t* wdt); +int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt); /** * @brief Clears the reset flag. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_ClearResetFlag (mxc_wdt_regs_t* wdt); +void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt); /** * @brief Get the status of the interrupt flag. * @param wdt Pointer to watchdog registers. * @returns 1 if the interrupt is pending, 0 otherwise. */ -int MXC_WDT_GetIntFlag (mxc_wdt_regs_t* wdt); +int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt); /** * @brief Clears the interrupt flag. * @param wdt Pointer to watchdog registers. */ -void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt); +void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt); /**@} end of group wdt */ @@ -221,4 +217,4 @@ } #endif -#endif /* _WDT_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_WDT_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_key_revb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_key_revb_regs.h deleted file mode 100644 index 9819af8..0000000 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_key_revb_regs.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file aes_key_revb_regs.h - * @brief Registers, Bit Masks and Bit Positions for the AES_KEY_REVB Peripheral Module. - */ - -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - * - * - *************************************************************************** */ - -#ifndef _AES_KEY_REVB_REGS_H_ -#define _AES_KEY_REVB_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup aes_key_revb - * @defgroup aes_key_revb_registers AES_KEY_REVB_Registers - * @brief Registers, Bit Masks and Bit Positions for the AES_KEY_REVB Peripheral Module. - * @details AES Key Registers. - */ - -/** - * @ingroup aes_key_revb_registers - * Structure type to access the AES_KEY_REVB Registers. - */ -typedef struct { - __IO uint32_t aes_key0; /**< \b 0x00: AES_KEY_REVB AES_KEY0 Register */ - __IO uint32_t aes_key1; /**< \b 0x04: AES_KEY_REVB AES_KEY1 Register */ - __IO uint32_t aes_key2; /**< \b 0x08: AES_KEY_REVB AES_KEY2 Register */ - __IO uint32_t aes_key3; /**< \b 0x0C: AES_KEY_REVB AES_KEY3 Register */ - __IO uint32_t aes_key4; /**< \b 0x10: AES_KEY_REVB AES_KEY4 Register */ - __IO uint32_t aes_key5; /**< \b 0x14: AES_KEY_REVB AES_KEY5 Register */ - __IO uint32_t aes_key6; /**< \b 0x18: AES_KEY_REVB AES_KEY6 Register */ - __IO uint32_t aes_key7; /**< \b 0x1C: AES_KEY_REVB AES_KEY7 Register */ -} mxc_aes_key_revb_regs_t; - -/* Register offsets for module AES_KEY_REVB */ -/** - * @ingroup aes_key_revb_registers - * @defgroup AES_KEY_REVB_Register_Offsets Register Offsets - * @brief AES_KEY_REVB Peripheral Register Offsets from the AES_KEY_REVB Base Peripheral Address. - * @{ - */ - #define MXC_R_AES_KEY_REVB_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY_REVB Base Address: 0x0000 */ - #define MXC_R_AES_KEY_REVB_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY_REVB Base Address: 0x0004 */ - #define MXC_R_AES_KEY_REVB_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY_REVB Base Address: 0x0008 */ - #define MXC_R_AES_KEY_REVB_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY_REVB Base Address: 0x000C */ - #define MXC_R_AES_KEY_REVB_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY_REVB Base Address: 0x0010 */ - #define MXC_R_AES_KEY_REVB_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY_REVB Base Address: 0x0014 */ - #define MXC_R_AES_KEY_REVB_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY_REVB Base Address: 0x0018 */ - #define MXC_R_AES_KEY_REVB_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY_REVB Base Address: 0x001C */ -/**@} end of group aes_key_revb_registers */ - -#ifdef __cplusplus -} -#endif - -#endif /* _AES_KEY_REVB_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_me15.c index d1569f0..0fa0f79 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_me15.c @@ -3,8 +3,8 @@ * @brief Trust Protection Unit driver. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,7 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include "mxc_device.h" #include "mxc_errors.h" @@ -47,15 +47,14 @@ #define KEY_ADDR 0x10802008 #define FMV_ADDR 0x10802000 -static const uint32_t fmv[2] = {0x2B86D479, 0x2B86D479}; +static const uint32_t fmv[2] = { 0x2B86D479, 0x2B86D479 }; -static void reverse_key(const void* key, uint8_t* keyr, int len) +static void reverse_key(const void *key, uint8_t *keyr, int len) { int i; uint8_t tmp; - uint8_t* k = (uint8_t*)key; - for(i = 0; i < len; i++) - { + uint8_t *k = (uint8_t *)key; + for (i = 0; i < len; i++) { tmp = k[i]; k[i] = keyr[len - i - 1]; keyr[len - i - 1] = tmp; @@ -70,37 +69,37 @@ { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_AES); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); - + MXC_AES->ctrl = 0x00; // Start with a randomly generated key. MXC_AES_GenerateKey(); - MXC_AES_RevB_Init((mxc_aes_revb_regs_t*) MXC_AES); - + MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + return E_NO_ERROR; } -void MXC_AES_EnableInt (uint32_t interrupt) +void MXC_AES_EnableInt(uint32_t interrupt) { - MXC_AES_RevB_EnableInt((mxc_aes_revb_regs_t*) MXC_AES, interrupt); + MXC_AES_RevB_EnableInt((mxc_aes_revb_regs_t *)MXC_AES, interrupt); } -void MXC_AES_DisableInt (uint32_t interrupt) +void MXC_AES_DisableInt(uint32_t interrupt) { - MXC_AES_RevB_DisableInt((mxc_aes_revb_regs_t*) MXC_AES, interrupt); + MXC_AES_RevB_DisableInt((mxc_aes_revb_regs_t *)MXC_AES, interrupt); } int MXC_AES_IsBusy(void) { - return MXC_AES_RevB_IsBusy((mxc_aes_revb_regs_t*) MXC_AES); + return MXC_AES_RevB_IsBusy((mxc_aes_revb_regs_t *)MXC_AES); } -int MXC_AES_Shutdown (void) +int MXC_AES_Shutdown(void) { - int error = MXC_AES_RevB_Shutdown ((mxc_aes_revb_regs_t*) MXC_AES); - + int error = MXC_AES_RevB_Shutdown((mxc_aes_revb_regs_t *)MXC_AES); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_AES); - + return error; } @@ -117,85 +116,86 @@ void MXC_AES_SetKeySize(mxc_aes_keys_t key) { - MXC_AES_RevB_SetKeySize((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_keys_t) key); + MXC_AES_RevB_SetKeySize((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_keys_t)key); } mxc_aes_keys_t MXC_AES_GetKeySize(void) { - return MXC_AES_RevB_GetKeySize((mxc_aes_revb_regs_t*) MXC_AES); + return MXC_AES_RevB_GetKeySize((mxc_aes_revb_regs_t *)MXC_AES); } void MXC_AES_FlushInputFIFO(void) { - MXC_AES_RevB_FlushInputFIFO((mxc_aes_revb_regs_t*) MXC_AES); + MXC_AES_RevB_FlushInputFIFO((mxc_aes_revb_regs_t *)MXC_AES); } void MXC_AES_FlushOutputFIFO(void) { - MXC_AES_RevB_FlushOutputFIFO((mxc_aes_revb_regs_t*) MXC_AES); + MXC_AES_RevB_FlushOutputFIFO((mxc_aes_revb_regs_t *)MXC_AES); } void MXC_AES_Start(void) { - MXC_AES_RevB_Start((mxc_aes_revb_regs_t*) MXC_AES); + MXC_AES_RevB_Start((mxc_aes_revb_regs_t *)MXC_AES); } uint32_t MXC_AES_GetFlags(void) { - return MXC_AES_RevB_GetFlags((mxc_aes_revb_regs_t*) MXC_AES); + return MXC_AES_RevB_GetFlags((mxc_aes_revb_regs_t *)MXC_AES); } void MXC_AES_ClearFlags(uint32_t flags) { - MXC_AES_RevB_ClearFlags((mxc_aes_revb_regs_t*) MXC_AES, flags); + MXC_AES_RevB_ClearFlags((mxc_aes_revb_regs_t *)MXC_AES, flags); } -int MXC_AES_Generic(mxc_aes_req_t* req) +int MXC_AES_Generic(mxc_aes_req_t *req) { - return MXC_AES_RevB_Generic((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req); + return MXC_AES_RevB_Generic((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); } -int MXC_AES_Encrypt(mxc_aes_req_t* req) +int MXC_AES_Encrypt(mxc_aes_req_t *req) { - return MXC_AES_RevB_Encrypt((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req); + return MXC_AES_RevB_Encrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); } -int MXC_AES_Decrypt(mxc_aes_req_t* req) +int MXC_AES_Decrypt(mxc_aes_req_t *req) { - return MXC_AES_RevB_Decrypt((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req); + return MXC_AES_RevB_Decrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); } -int MXC_AES_TXDMAConfig(void* src_addr, int len) +int MXC_AES_TXDMAConfig(void *src_addr, int len) { return MXC_AES_RevB_TXDMAConfig(src_addr, len); } -int MXC_AES_RXDMAConfig(void* dest_addr, int len) +int MXC_AES_RXDMAConfig(void *dest_addr, int len) { return MXC_AES_RevB_RXDMAConfig(dest_addr, len); } -int MXC_AES_GenericAsync(mxc_aes_req_t* req, uint8_t enc) +int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) { - return MXC_AES_RevB_GenericAsync((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req, enc); + return MXC_AES_RevB_GenericAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req, + enc); } -int MXC_AES_EncryptAsync(mxc_aes_req_t* req) +int MXC_AES_EncryptAsync(mxc_aes_req_t *req) { - return MXC_AES_RevB_EncryptAsync((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req); + return MXC_AES_RevB_EncryptAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); } -int MXC_AES_DecryptAsync(mxc_aes_req_t* req) +int MXC_AES_DecryptAsync(mxc_aes_req_t *req) { - return MXC_AES_RevB_DecryptAsync((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req); + return MXC_AES_RevB_DecryptAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); } -void MXC_AES_SetExtKey(const void* key, mxc_aes_keys_t len) +void MXC_AES_SetExtKey(const void *key, mxc_aes_keys_t len) { - MXC_AES_RevB_SetExtKey((mxc_aes_key_revb_regs_t*) MXC_AESKEY, key, len); + MXC_AES_RevB_SetExtKey((mxc_aeskeys_revb_regs_t *)MXC_AESKEYS, key, len); } -int MXC_AES_SetPORKey(const void* key, mxc_aes_keys_t len) +int MXC_AES_SetPORKey(const void *key, mxc_aes_keys_t len) { int err = E_BAD_PARAM; uint8_t keyr[32]; @@ -204,23 +204,22 @@ MXC_FLC_UnlockInfoBlock(KEY_ADDR); // Write the key - switch(len) - { - case MXC_AES_128BITS: - reverse_key(key, keyr, 16); - err = MXC_FLC_Write(KEY_ADDR, 16, (uint32_t*)keyr); - break; - case MXC_AES_192BITS: - reverse_key(key, keyr, 24); - err = MXC_FLC_Write(KEY_ADDR, 24, (uint32_t*)keyr); - break; - case MXC_AES_256BITS: - reverse_key(key, keyr, 32); - err = MXC_FLC_Write(KEY_ADDR, 32, (uint32_t*)keyr); - break; + switch (len) { + case MXC_AES_128BITS: + reverse_key(key, keyr, 16); + err = MXC_FLC_Write(KEY_ADDR, 16, (uint32_t *)keyr); + break; + case MXC_AES_192BITS: + reverse_key(key, keyr, 24); + err = MXC_FLC_Write(KEY_ADDR, 24, (uint32_t *)keyr); + break; + case MXC_AES_256BITS: + reverse_key(key, keyr, 32); + err = MXC_FLC_Write(KEY_ADDR, 32, (uint32_t *)keyr); + break; } - - if(err == E_NO_ERROR) { + + if (err == E_NO_ERROR) { // Write the magic value to activate the key err = MXC_FLC_Write(FMV_ADDR, sizeof(fmv), (uint32_t *)fmv); @@ -246,10 +245,10 @@ MXC_FLC_UnlockInfoBlock(FMV_ADDR); // Copy the current memory contents - memcpy(page, (uint8_t*)FMV_ADDR + 40, MXC_FLASH_PAGE_SIZE - 40); - + memcpy(page, (uint8_t *)FMV_ADDR + 40, MXC_FLASH_PAGE_SIZE - 40); + err = MXC_FLC_PageErase(FMV_ADDR); - if(err != E_NO_ERROR) { + if (err != E_NO_ERROR) { // Couldn't erase the memory. Abort. // Lock the key region from reads/writes MXC_FLC_LockInfoBlock(FMV_ADDR); @@ -257,7 +256,7 @@ } // Write the old contents (minus the fmv and key) back to the part - err = MXC_FLC_Write(FMV_ADDR + 40, MXC_FLASH_PAGE_SIZE - 40, (uint32_t*)page); + err = MXC_FLC_Write(FMV_ADDR + 40, MXC_FLASH_PAGE_SIZE - 40, (uint32_t *)page); // Lock the key region from reads/writes MXC_FLC_LockInfoBlock(FMV_ADDR); @@ -271,17 +270,16 @@ MXC_FLC_UnlockInfoBlock(KEY_ADDR); // Copy the values to the key register - switch(len) - { - case MXC_AES_128BITS: - memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 16); - break; - case MXC_AES_192BITS: - memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 24); - break; - case MXC_AES_256BITS: - memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 32); - break; + switch (len) { + case MXC_AES_128BITS: + memcpy(MXC_AESKEYS, (uint8_t *)KEY_ADDR, 16); + break; + case MXC_AES_192BITS: + memcpy(MXC_AESKEYS, (uint8_t *)KEY_ADDR, 24); + break; + case MXC_AES_256BITS: + memcpy(MXC_AESKEYS, (uint8_t *)KEY_ADDR, 32); + break; } // Lock the key region from reads/writes @@ -291,12 +289,12 @@ int MXC_AES_HasPORKey() { int res; - + // Make the key location readable/writable MXC_FLC_UnlockInfoBlock(FMV_ADDR); - + // Look for the magic value. - res = memcmp((uint8_t*)FMV_ADDR, (uint8_t*)fmv, 8); + res = memcmp((uint8_t *)FMV_ADDR, (uint8_t *)fmv, 8); // Lock the key region from reads/writes MXC_FLC_LockInfoBlock(FMV_ADDR); diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.c index 561fe8d..af1551f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,10 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ -#ifdef __CC_ARM // Keil - #pragma diag_suppress 188 // enumerated type mixed with another type -#endif + ******************************************************************************/ #include #include @@ -44,7 +41,7 @@ #include "dma.h" #include "aes_regs.h" -#include "aes_key_regs.h" +#include "aeskeys_regs.h" #include "aes_revb.h" #include "trng_revb.h" @@ -53,204 +50,206 @@ uint8_t enc; uint8_t channelRX; uint8_t channelTX; - uint32_t remain; - uint32_t* inputText; - uint32_t* outputText; + uint32_t remain; + uint32_t *inputText; + uint32_t *outputText; } mxc_aes_revb_dma_req_t; static mxc_aes_revb_dma_req_t dma_state; -#define SWAP_BYTES(x) ((((x) >> 24) & 0x000000FF) | (((x) >> 8) & 0x0000FF00) | (((x) << 8) & 0x00FF0000) | (((x) << 24) & 0xFF000000)) +#define SWAP_BYTES(x) \ + ((((x) >> 24) & 0x000000FF) | (((x) >> 8) & 0x0000FF00) | (((x) << 8) & 0x00FF0000) | \ + (((x) << 24) & 0xFF000000)) -static void memcpy32r(uint32_t * dst, const uint32_t * src, unsigned int len) +/* Prevent GCC from optimimzing this function to memcpy */ +static void __attribute__((optimize("no-tree-loop-distribute-patterns"))) +memcpy32r(uint32_t *dst, const uint32_t *src, unsigned int len) { - uint32_t * dstr = dst + (len/4) - 1; - while (len) { - *dstr = SWAP_BYTES(*src); - dstr--; - src++; - len -= 4; - } + uint32_t *dstr = dst + (len / 4) - 1; + while (len) { + *dstr = SWAP_BYTES(*src); + dstr--; + src++; + len -= 4; + } } -int MXC_AES_RevB_Init(mxc_aes_revb_regs_t* aes) +int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes) { - aes->ctrl = 0x00; - - while (MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR); - - aes->ctrl |= MXC_F_AES_REVB_CTRL_EN; - - return E_NO_ERROR; -} - -int MXC_AES_RevB_Shutdown (mxc_aes_revb_regs_t* aes) -{ - MXC_AES_RevB_FlushInputFIFO(aes); - MXC_AES_RevB_FlushOutputFIFO(aes); - - while(MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR) ; - aes->ctrl = 0x00; - return E_NO_ERROR; + while (MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR) {} + + aes->ctrl |= MXC_F_AES_REVB_CTRL_EN; + + return E_NO_ERROR; } -int MXC_AES_RevB_IsBusy (mxc_aes_revb_regs_t* aes) +int MXC_AES_RevB_Shutdown(mxc_aes_revb_regs_t *aes) { - if(aes->status & MXC_F_AES_REVB_STATUS_BUSY) - { + MXC_AES_RevB_FlushInputFIFO(aes); + MXC_AES_RevB_FlushOutputFIFO(aes); + + while (MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR) {} + + aes->ctrl = 0x00; + + return E_NO_ERROR; +} + +int MXC_AES_RevB_IsBusy(mxc_aes_revb_regs_t *aes) +{ + if (aes->status & MXC_F_AES_REVB_STATUS_BUSY) { return E_BUSY; } - return E_NO_ERROR; + return E_NO_ERROR; } -void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t* aes, mxc_aes_revb_keys_t key) +void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t *aes, mxc_aes_revb_keys_t key) { - while(MXC_AES_IsBusy() != E_NO_ERROR); + while (MXC_AES_IsBusy() != E_NO_ERROR) {} aes->ctrl |= key; } -mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t* aes) +mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t *aes) { return (aes->ctrl & MXC_F_AES_REVB_CTRL_KEY_SIZE); } -void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t* aes) +void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t *aes) { - while(MXC_AES_IsBusy() != E_NO_ERROR); + while (MXC_AES_IsBusy() != E_NO_ERROR) {} aes->ctrl |= MXC_F_AES_REVB_CTRL_INPUT_FLUSH; } -void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t* aes) +void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t *aes) { - while(MXC_AES_IsBusy() != E_NO_ERROR); + while (MXC_AES_IsBusy() != E_NO_ERROR) {} aes->ctrl |= MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH; } -void MXC_AES_RevB_Start(mxc_aes_revb_regs_t* aes) +void MXC_AES_RevB_Start(mxc_aes_revb_regs_t *aes) { - while(MXC_AES_IsBusy() != E_NO_ERROR); - aes->ctrl |= MXC_F_AES_REVB_CTRL_START; + while (MXC_AES_IsBusy() != E_NO_ERROR) {} + aes->ctrl |= MXC_F_AES_REVB_CTRL_START; } -void MXC_AES_RevB_EnableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt) +void MXC_AES_RevB_EnableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt) { - aes->inten |= (interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE | \ - MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV)); + aes->inten |= (interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE | + MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV)); } -void MXC_AES_RevB_DisableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt) +void MXC_AES_RevB_DisableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt) { - aes->inten &= ~(interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE | \ - MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV)); + aes->inten &= ~(interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE | + MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV)); } -uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t* aes) +uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t *aes) { return aes->intfl; } -void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t* aes, uint32_t flags) +void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t *aes, uint32_t flags) { - aes->intfl = (flags & (MXC_F_AES_REVB_INTFL_DONE | MXC_F_AES_REVB_INTFL_KEY_CHANGE | \ - MXC_F_AES_REVB_INTFL_KEY_ZERO | MXC_F_AES_REVB_INTFL_OV)); + aes->intfl = (flags & (MXC_F_AES_REVB_INTFL_DONE | MXC_F_AES_REVB_INTFL_KEY_CHANGE | + MXC_F_AES_REVB_INTFL_KEY_ZERO | MXC_F_AES_REVB_INTFL_OV)); } -int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req) +int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req) { int i; int remain; - if(req == NULL) { + if (req == NULL) { return E_NULL_PTR; } - if(req->inputData == NULL || req->resultData == NULL) { + if (req->inputData == NULL || req->resultData == NULL) { return E_NULL_PTR; } - if(req->length == 0) { + if (req->length == 0) { return E_BAD_PARAM; } remain = req->length; - + MXC_AES_RevB_FlushInputFIFO(aes); - MXC_AES_RevB_FlushOutputFIFO(aes); + MXC_AES_RevB_FlushOutputFIFO(aes); MXC_AES_RevB_SetKeySize(aes, req->keySize); - while(MXC_AES_IsBusy() != E_NO_ERROR); - - MXC_SETFIELD (aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS); + while (MXC_AES_IsBusy() != E_NO_ERROR) {} - while(remain/4) - { - for(i = 0; i < 4; i++) { - aes->fifo = SWAP_BYTES(req->inputData[3-i]); + MXC_SETFIELD(aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, + req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS); + + while (remain / 4) { + for (i = 0; i < 4; i++) { + aes->fifo = SWAP_BYTES(req->inputData[3 - i]); } req->inputData += 4; - while(!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE)); + while (!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE)) {} aes->intfl |= MXC_F_AES_REVB_INTFL_DONE; - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { uint32_t tmp = aes->fifo; - req->resultData[3-i] = SWAP_BYTES(tmp); - } + req->resultData[3 - i] = SWAP_BYTES(tmp); + } req->resultData += 4; remain -= 4; } - if(remain%4) - { - for(i = 0; i < remain; i++) { - aes->fifo = SWAP_BYTES(req->inputData[remain-1-i]); + if (remain % 4) { + for (i = 0; i < remain; i++) { + aes->fifo = SWAP_BYTES(req->inputData[remain - 1 - i]); } req->inputData += remain; // Pad last block with 0's - for(i = remain; i < 4; i++) { + for (i = remain; i < 4; i++) { aes->fifo = 0; } - while(!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE)); + while (!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE)) {} aes->intfl |= MXC_F_AES_REVB_INTFL_DONE; - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { uint32_t tmp = aes->fifo; - req->resultData[3-i] = SWAP_BYTES(tmp); - } + req->resultData[3 - i] = SWAP_BYTES(tmp); + } req->resultData += 4; } return E_NO_ERROR; } -int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req) +int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req) { return MXC_AES_RevB_Generic(aes, req); } -int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req) +int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req) { return MXC_AES_RevB_Generic(aes, req); } -int MXC_AES_RevB_TXDMAConfig(void* src_addr, int len) +int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) { uint8_t channel; mxc_dma_config_t config; mxc_dma_srcdst_t srcdst; if (src_addr == NULL) { - return E_NULL_PTR; + return E_NULL_PTR; } if (len == 0) { - return E_BAD_PARAM; + return E_BAD_PARAM; } MXC_DMA_Init(); @@ -259,47 +258,45 @@ dma_state.channelTX = channel; config.reqsel = MXC_DMA_REQUEST_AESTX; - + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_WORD; config.dstwd = MXC_DMA_WIDTH_WORD; - + config.srcinc_en = 1; config.dstinc_en = 0; - + srcdst.ch = channel; srcdst.source = src_addr; - - if(dma_state.enc == 1) { + + if (dma_state.enc == 1) { srcdst.len = 4; - } - else if(len > 4) { + } else if (len > 4) { srcdst.len = 4; - } - else{ + } else { srcdst.len = len; } - MXC_DMA_ConfigChannel (config, srcdst); - MXC_DMA_SetCallback (channel, MXC_AES_RevB_DMACallback); - - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback); + + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); return E_NO_ERROR; } -int MXC_AES_RevB_RXDMAConfig(void* dest_addr, int len) +int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) { if (dest_addr == NULL) { - return E_NULL_PTR; + return E_NULL_PTR; } if (len == 0) { - return E_BAD_PARAM; + return E_BAD_PARAM; } uint8_t channel; @@ -312,125 +309,121 @@ dma_state.channelRX = channel; config.reqsel = MXC_DMA_REQUEST_AESRX; - + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_WORD; config.dstwd = MXC_DMA_WIDTH_WORD; - + config.srcinc_en = 0; config.dstinc_en = 1; - + srcdst.ch = channel; srcdst.dest = dest_addr; - if(dma_state.enc == 0) { + if (dma_state.enc == 0) { srcdst.len = 4; - } - else if(len > 4) { + } else if (len > 4) { srcdst.len = 4; - } - else{ + } else { srcdst.len = len; } - - MXC_DMA_ConfigChannel (config, srcdst); - MXC_DMA_SetCallback (channel, MXC_AES_RevB_DMACallback); - - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback); + + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); return E_NO_ERROR; } -int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req, uint8_t enc) +int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, uint8_t enc) { - if(req == NULL) { + if (req == NULL) { return E_NULL_PTR; } - if(req->inputData == NULL || req->resultData == NULL) { + if (req->inputData == NULL || req->resultData == NULL) { return E_NULL_PTR; } - if(req->length == 0) { + if (req->length == 0) { return E_BAD_PARAM; } MXC_AES_RevB_FlushInputFIFO(aes); - MXC_AES_RevB_FlushOutputFIFO(aes); + MXC_AES_RevB_FlushOutputFIFO(aes); MXC_AES_RevB_SetKeySize(aes, req->keySize); MXC_AES_IsBusy(); - MXC_SETFIELD (aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS); + MXC_SETFIELD(aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, + req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS); dma_state.enc = enc; dma_state.remain = req->length; dma_state.inputText = req->inputData; dma_state.outputText = req->resultData; - aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_RX_EN; //Enable AES DMA - aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_TX_EN; //Enable AES DMA + aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_RX_EN; //Enable AES DMA + aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_TX_EN; //Enable AES DMA - if(MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain) != E_NO_ERROR) { + if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain) != E_NO_ERROR) { return E_BAD_PARAM; } return E_NO_ERROR; } - -int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req) + +int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req) { return MXC_AES_RevB_GenericAsync(aes, req, 0); } -int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req) +int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req) { return MXC_AES_RevB_GenericAsync(aes, req, 1); } void MXC_AES_RevB_DMACallback(int ch, int error) { - if(error != E_NO_ERROR) { - - } - else { - if (dma_state.channelTX == ch) { - MXC_DMA_ReleaseChannel(dma_state.channelTX); - if (dma_state.remain < 4) { - MXC_AES_Start(); + if (error != E_NO_ERROR) { + } else { + if (dma_state.channelTX == ch) { + MXC_DMA_ReleaseChannel(dma_state.channelTX); + if (dma_state.remain < 4) { + MXC_AES_Start(); + } + MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain); + } else if (dma_state.channelRX == ch) { + if (dma_state.remain > 4) { + dma_state.remain -= 4; + } else if (dma_state.remain > 0) { + dma_state.remain = 0; + } + MXC_DMA_ReleaseChannel(dma_state.channelRX); + if (dma_state.remain > 0) { + MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain); + } } - MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain); - } - else if (dma_state.channelRX == ch) { - if (dma_state.remain > 4) { - dma_state.remain -= 4; - } else if (dma_state.remain > 0) { - dma_state.remain = 0; - } - MXC_DMA_ReleaseChannel(dma_state.channelRX); - if (dma_state.remain > 0) { - MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain); - } - } } } -void MXC_AES_RevB_SetExtKey(mxc_aes_key_revb_regs_t* aeskey, const void* key, mxc_aes_keys_t len) +void MXC_AES_RevB_SetExtKey(mxc_aeskeys_revb_regs_t *aeskeys, const void *key, mxc_aes_keys_t len) { - int numBytes; + int numBytes; - if(len == MXC_AES_128BITS) { - numBytes = 16; - } else if (len == MXC_AES_192BITS) { - numBytes = 24; - } else { - numBytes = 32; - } + if (len == MXC_AES_128BITS) { + numBytes = 16; + } else if (len == MXC_AES_192BITS) { + numBytes = 24; + } else { + numBytes = 32; + } - /* TODO: Figure out if this is the correct byte ordering */ - memcpy32r((void*)&(aeskey->aes_key0), key, numBytes); + /* TODO: Figure out if this is the correct byte ordering */ + memcpy32r((void *)&(aeskeys->key0), key, numBytes); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h index cf1f1e6..7d4cbf3 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,12 +29,15 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_AES_AES_REVB_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_AES_AES_REVB_H_ #include #include "mxc_aes.h" #include "aes_revb_regs.h" -#include "aes_key_revb_regs.h" +#include "aeskeys_revb_regs.h" #include "trng_revb_regs.h" /** @@ -42,9 +45,9 @@ * */ typedef enum { - MXC_AES_REVB_128BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key - MXC_AES_REVB_192BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key - MXC_AES_REVB_256BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key + MXC_AES_REVB_128BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key + MXC_AES_REVB_192BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key + MXC_AES_REVB_256BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key } mxc_aes_revb_keys_t; /** @@ -52,9 +55,9 @@ * */ typedef enum { - MXC_AES_REVB_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key - MXC_AES_REVB_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key - MXC_AES_REVB_DECRYPT_INT_KEY = 2 ///< Decryption using internal key + MXC_AES_REVB_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key + MXC_AES_REVB_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key + MXC_AES_REVB_DECRYPT_INT_KEY = 2 ///< Decryption using internal key } mxc_aes_revb_enc_type_t; /** @@ -62,35 +65,36 @@ * */ typedef struct _mxc_aes_revb_cipher_req_t { - uint32_t length; ///< Length of the data - uint32_t *inputData; ///< Pointer to input data - uint32_t *resultData; ///< Pointer to encrypted data - mxc_aes_revb_keys_t keySize; ///< Size of AES key - mxc_aes_revb_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t - mxc_aes_complete_t callback; ///< Callback function + uint32_t length; ///< Length of the data + uint32_t *inputData; ///< Pointer to input data + uint32_t *resultData; ///< Pointer to encrypted data + mxc_aes_revb_keys_t keySize; ///< Size of AES key + mxc_aes_revb_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t + mxc_aes_complete_t callback; ///< Callback function } mxc_aes_revb_req_t; - -int MXC_AES_RevB_Init (mxc_aes_revb_regs_t* aes); -void MXC_AES_RevB_EnableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt); -void MXC_AES_RevB_DisableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt); -int MXC_AES_RevB_IsBusy (mxc_aes_revb_regs_t* aes); -int MXC_AES_RevB_Shutdown (mxc_aes_revb_regs_t* aes); -void MXC_AES_RevB_GenerateKey(mxc_trng_revb_regs_t* trng); -void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t* aes, mxc_aes_revb_keys_t key); -mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t* aes); -void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t* aes); -void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t* aes); -void MXC_AES_RevB_Start(mxc_aes_revb_regs_t* aes); -uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t* aes); -void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t* aes, uint32_t flags); -int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req); -int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req); -int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req); +int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes); +void MXC_AES_RevB_EnableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt); +void MXC_AES_RevB_DisableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt); +int MXC_AES_RevB_IsBusy(mxc_aes_revb_regs_t *aes); +int MXC_AES_RevB_Shutdown(mxc_aes_revb_regs_t *aes); +void MXC_AES_RevB_GenerateKey(mxc_trng_revb_regs_t *trng); +void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t *aes, mxc_aes_revb_keys_t key); +mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t *aes); +void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t *aes); +void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t *aes); +void MXC_AES_RevB_Start(mxc_aes_revb_regs_t *aes); +uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t *aes); +void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t *aes, uint32_t flags); +int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); +int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); +int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len); int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len); -int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req, uint8_t enc); -int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req); -int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req); -void MXC_AES_RevB_DMACallback (int ch, int error); -void MXC_AES_RevB_SetExtKey(mxc_aes_key_revb_regs_t* aeskey, const void* key, mxc_aes_keys_t len); +int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, uint8_t enc); +int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); +int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); +void MXC_AES_RevB_DMACallback(int ch, int error); +void MXC_AES_RevB_SetExtKey(mxc_aeskeys_revb_regs_t *aeskey, const void *key, mxc_aes_keys_t len); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_AES_AES_REVB_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h index 54013c6..192aacb 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the AES_REVB Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _AES_REVB_REGS_H_ #define _AES_REVB_REGS_H_ @@ -67,9 +66,6 @@ #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aeskeys_revb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aeskeys_revb_regs.h new file mode 100644 index 0000000..e536e40 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aeskeys_revb_regs.h @@ -0,0 +1,117 @@ +/** + * @file aeskeys_revb_regs.h + * @brief Registers, Bit Masks and Bit Positions for the AESKEYS_REVB Peripheral Module. + * @note This file is @generated. + */ + +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_AESKEYS_AESKEYS_REVB_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_AESKEYS_AESKEYS_REVB_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup aeskeys_revb + * @defgroup aeskeys_revb_registers AESKEYS_REVB_Registers + * @brief Registers, Bit Masks and Bit Positions for the AESKEYS_REVB Peripheral Module. + * @details AES Key Registers. + */ + +/** + * @ingroup aeskeys_revb_registers + * Structure type to access the AESKEYS_REVB Registers. + */ +typedef struct { + __IO uint32_t key0; /**< \b 0x00: AESKEYS_REVB KEY0 Register */ + __IO uint32_t key1; /**< \b 0x04: AESKEYS_REVB KEY1 Register */ + __IO uint32_t key2; /**< \b 0x08: AESKEYS_REVB KEY2 Register */ + __IO uint32_t key3; /**< \b 0x0C: AESKEYS_REVB KEY3 Register */ + __IO uint32_t key4; /**< \b 0x10: AESKEYS_REVB KEY4 Register */ + __IO uint32_t key5; /**< \b 0x14: AESKEYS_REVB KEY5 Register */ + __IO uint32_t key6; /**< \b 0x18: AESKEYS_REVB KEY6 Register */ + __IO uint32_t key7; /**< \b 0x1C: AESKEYS_REVB KEY7 Register */ +} mxc_aeskeys_revb_regs_t; + +/* Register offsets for module AESKEYS_REVB */ +/** + * @ingroup aeskeys_revb_registers + * @defgroup AESKEYS_REVB_Register_Offsets Register Offsets + * @brief AESKEYS_REVB Peripheral Register Offsets from the AESKEYS_REVB Base Peripheral Address. + * @{ + */ +#define MXC_R_AESKEYS_REVB_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AESKEYS_REVB Base Address: 0x0000 */ +#define MXC_R_AESKEYS_REVB_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AESKEYS_REVB Base Address: 0x0004 */ +#define MXC_R_AESKEYS_REVB_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AESKEYS_REVB Base Address: 0x0008 */ +#define MXC_R_AESKEYS_REVB_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AESKEYS_REVB Base Address: 0x000C */ +#define MXC_R_AESKEYS_REVB_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AESKEYS_REVB Base Address: 0x0010 */ +#define MXC_R_AESKEYS_REVB_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AESKEYS_REVB Base Address: 0x0014 */ +#define MXC_R_AESKEYS_REVB_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AESKEYS_REVB Base Address: 0x0018 */ +#define MXC_R_AESKEYS_REVB_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AESKEYS_REVB Base Address: 0x001C */ +/**@} end of group aeskeys_revb_registers */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_AESKEYS_AESKEYS_REVB_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_me15.c index 2b64c14..e0bdb81 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_me15.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include "mxc_device.h" #include "mxc_errors.h" @@ -39,7 +39,6 @@ #include "crc.h" #include "crc_reva.h" - /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ @@ -48,66 +47,66 @@ { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t*) MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); return E_NO_ERROR; } int MXC_CRC_Shutdown(void) { - int error = MXC_CRC_RevA_Shutdown((mxc_crc_reva_regs_t*) MXC_CRC); - + int error = MXC_CRC_RevA_Shutdown((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_CRC); - + return error; } -void MXC_CRC_Handler (int ch, int error) +void MXC_CRC_Handler(int ch, int error) { MXC_CRC_RevA_Handler(ch, error); } void MXC_CRC_SetDirection(mxc_crc_bitorder_t bitOrder) { - MXC_CRC_RevA_SetDirection((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_bitorder_t) bitOrder); + MXC_CRC_RevA_SetDirection((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder); } mxc_crc_bitorder_t MXC_CRC_GetDirection(void) { - return MXC_CRC_RevA_GetDirection((mxc_crc_reva_regs_t*) MXC_CRC); + return MXC_CRC_RevA_GetDirection((mxc_crc_reva_regs_t *)MXC_CRC); } void MXC_CRC_SwapDataIn(mxc_crc_bitorder_t bitOrder) { - MXC_CRC_RevA_SwapDataIn((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_bitorder_t) bitOrder); + MXC_CRC_RevA_SwapDataIn((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder); } void MXC_CRC_SwapDataOut(mxc_crc_bitorder_t bitOrder) { - MXC_CRC_RevA_SwapDataOut((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_bitorder_t) bitOrder); + MXC_CRC_RevA_SwapDataOut((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder); } void MXC_CRC_SetPoly(uint32_t poly) { - MXC_CRC_RevA_SetPoly((mxc_crc_reva_regs_t*) MXC_CRC, poly); + MXC_CRC_RevA_SetPoly((mxc_crc_reva_regs_t *)MXC_CRC, poly); } uint32_t MXC_CRC_GetPoly(void) { - return MXC_CRC_RevA_GetPoly((mxc_crc_reva_regs_t*) MXC_CRC); + return MXC_CRC_RevA_GetPoly((mxc_crc_reva_regs_t *)MXC_CRC); } uint32_t MXC_CRC_GetResult(void) { - return MXC_CRC_RevA_GetResult((mxc_crc_reva_regs_t*) MXC_CRC); + return MXC_CRC_RevA_GetResult((mxc_crc_reva_regs_t *)MXC_CRC); } -int MXC_CRC_Compute(mxc_crc_req_t* req) +int MXC_CRC_Compute(mxc_crc_req_t *req) { - return MXC_CRC_RevA_Compute((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_req_t*) req); + return MXC_CRC_RevA_Compute((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_req_t *)req); } -int MXC_CRC_ComputeAsync(mxc_crc_req_t* req) +int MXC_CRC_ComputeAsync(mxc_crc_req_t *req) { - return MXC_CRC_RevA_ComputeAsync((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_req_t*) req); + return MXC_CRC_RevA_ComputeAsync((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_req_t *)req); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.c index a1535e0..9969f52 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.c @@ -1,8 +1,8 @@ -/* **************************************************************************** - * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,11 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ - -#ifdef __CC_ARM -#pragma diag_suppress 188 -#endif + ******************************************************************************/ #include #include @@ -48,7 +44,6 @@ #include "crc_regs.h" #include "crc_reva.h" - /***** Global Variables *****/ static mxc_crc_reva_req_t *CRCreq; @@ -56,14 +51,14 @@ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t* crc) +int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc) { crc->ctrl = 0x00; - crc->val = 0xFFFFFFFF; + crc->val = 0xFFFFFFFF; return E_NO_ERROR; } -int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t* crc) +int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t *crc) { crc->ctrl &= ~MXC_F_CRC_REVA_CTRL_EN; return E_NO_ERROR; @@ -71,7 +66,7 @@ int MXC_CRC_RevA_Handler(int ch, int error) { - if(error == E_NO_ERROR) { + if (error == E_NO_ERROR) { CRCreq->resultCRC = MXC_CRC_GetResult(); } return error; @@ -85,37 +80,39 @@ /* Low Level Functions */ /*******************************/ -void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder) +void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder) { MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_MSB, bitOrder << MXC_F_CRC_REVA_CTRL_MSB_POS); } -mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t* crc) +mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t *crc) { return !!(crc->ctrl & MXC_F_CRC_REVA_CTRL_MSB); } -void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder) +void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder) { - MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN, bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN_POS); + MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN, + bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN_POS); } -void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder) +void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder) { - MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT, bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT_POS); + MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT, + bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT_POS); } -void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t* crc, uint32_t poly) +void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t *crc, uint32_t poly) { crc->poly = poly; } -uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t* crc) +uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t *crc) { return crc->poly; } -uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t* crc) +uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t *crc) { return crc->val; } @@ -124,86 +121,85 @@ /* High Level Functions */ /*******************************/ -int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req) +int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req) { int i = 0; volatile int length; - if(req == NULL) { + if (req == NULL) { return E_NULL_PTR; } - if(req->dataBuffer == NULL) { + if (req->dataBuffer == NULL) { return E_NULL_PTR; } - if(req->dataLen == 0) { + if (req->dataLen == 0) { return E_INVALID; } crc->ctrl |= MXC_F_CRC_REVA_CTRL_EN; length = req->dataLen; - - while(length--) - { + + while (length--) { crc->datain32 = req->dataBuffer[i++]; - while(crc->ctrl & MXC_F_CRC_REVA_CTRL_BUSY); + while (crc->ctrl & MXC_F_CRC_REVA_CTRL_BUSY) {} } - + // Store the crc value req->resultCRC = MXC_CRC_GetResult(); - + return E_NO_ERROR; } -int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req) +int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req) { uint8_t channel; mxc_dma_config_t config; mxc_dma_srcdst_t srcdst; - if(req == NULL) { + if (req == NULL) { return E_NULL_PTR; } - if(req->dataBuffer == NULL) { + if (req->dataBuffer == NULL) { return E_NULL_PTR; } - if(req->dataLen == 0) { + if (req->dataLen == 0) { return E_INVALID; } - + CRCreq = req; - + MXC_DMA_Init(); - + channel = MXC_DMA_AcquireChannel(); - + config.reqsel = MXC_DMA_REQUEST_CRCTX; - + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 1; config.dstinc_en = 0; - + srcdst.ch = channel; - srcdst.source = (uint8_t*) req->dataBuffer; //transfering bytes - srcdst.len = req->dataLen * 4; //number of bytes - + srcdst.source = (uint8_t *)req->dataBuffer; //transfering bytes + srcdst.len = req->dataLen * 4; //number of bytes + MXC_CRC->ctrl |= MXC_F_CRC_CTRL_DMA_EN; MXC_CRC->ctrl |= MXC_F_CRC_CTRL_EN; - MXC_DMA_ConfigChannel(config,srcdst); - MXC_DMA_SetCallback(channel,(void *) MXC_CRC_Handler); + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_SetCallback(channel, MXC_CRC_Handler); MXC_DMA_EnableInt(channel); MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); - + return E_NO_ERROR; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.h index c0da254..283240d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.h @@ -1,8 +1,8 @@ -/* **************************************************************************** - * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,42 +29,42 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_CRC_CRC_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_CRC_CRC_REVA_H_ #include "crc.h" #include "crc_reva_regs.h" - /***** CRC Definitions *****/ /** * @brief Structure used to set up CRC request * */ typedef struct _mxc_crc_reva_req_t { - uint32_t* dataBuffer; ///< Pointer to the data - uint32_t dataLen; ///< Length of the data - uint32_t resultCRC; ///< Calculated CRC value + uint32_t *dataBuffer; ///< Pointer to the data + uint32_t dataLen; ///< Length of the data + uint32_t resultCRC; ///< Calculated CRC value } mxc_crc_reva_req_t; /** * @brief CRC data bit order * */ -typedef enum { - CRC_REVA_LSB_FIRST, - CRC_REVA_MSB_FIRST -} mxc_crc_reva_bitorder_t; +typedef enum { CRC_REVA_LSB_FIRST, CRC_REVA_MSB_FIRST } mxc_crc_reva_bitorder_t; - -int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t* crc); -int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t* crc); +int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc); +int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t *crc); int MXC_CRC_RevA_Handler(int ch, int error); -void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder); -mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t* crc); -void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder); -void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder); -void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t* crc, uint32_t poly); -uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t* crc); -uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t* crc); -int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req); -int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req); +void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder); +mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t *crc); +void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder); +void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder); +void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t *crc, uint32_t poly); +uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t *crc); +uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t *crc); +int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req); +int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_CRC_CRC_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva_regs.h index d7c2bb9..74835dc 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the CRC_REVA Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _CRC_REVA_REGS_H_ #define _CRC_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_me15.c index 2472c50..fcd6526 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_me15.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ /****** Includes *******/ #include @@ -45,17 +45,17 @@ int MXC_DMA_Init(void) { - if(!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); - } + if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); + } - return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t*) MXC_DMA); + return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA); } int MXC_DMA_AcquireChannel(void) { - return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t*) MXC_DMA); + return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)MXC_DMA); } int MXC_DMA_ReleaseChannel(int ch) @@ -78,7 +78,7 @@ return MXC_DMA_RevA_SetSrcDst(srcdst); } -int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t* srcdst) +int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst) { return MXC_DMA_RevA_GetSrcDst(srcdst); } @@ -100,7 +100,7 @@ int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz) { - return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz); + return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz); } int MXC_DMA_ChannelEnableInt(int ch, int flags) @@ -125,12 +125,12 @@ int MXC_DMA_EnableInt(int ch) { - return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch); + return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); } int MXC_DMA_DisableInt(int ch) { - return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch); + return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); } int MXC_DMA_Start(int ch) @@ -143,22 +143,23 @@ return MXC_DMA_RevA_Stop(ch); } -mxc_dma_ch_regs_t* MXC_DMA_GetCHRegs(int ch) +mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch) { return MXC_DMA_RevA_GetCHRegs(ch); } void MXC_DMA_Handler(void) { - MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t*) MXC_DMA); + MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)MXC_DMA); } -int MXC_DMA_MemCpy(void* dest, void* src, int len, mxc_dma_complete_cb_t callback) +int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback) { - return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t*) MXC_DMA, dest, src, len, callback); + return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback); } -int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) +int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, + mxc_dma_trans_chain_t callback) { - return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t*) MXC_DMA, config, firstSrcDst, callback); + return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.c index b48b285..2bd9e99 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.c @@ -1,8 +1,8 @@ -/* **************************************************************************** - * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,10 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ -#ifdef __CC_ARM // Keil -#pragma diag_suppress 68 // integer conversion resulted in a change of sign -#endif + ******************************************************************************/ /****** Includes *******/ #include @@ -46,28 +43,26 @@ #include "dma_reva_regs.h" /***** Definitions *****/ -#define CHECK_HANDLE(x)((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid)) +#define CHECK_HANDLE(x) ((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid)) typedef struct { - void* userCallback; // user given callback - void* dest; // memcpy destination + void *userCallback; // user given callback + void *dest; // memcpy destination } mxc_dma_highlevel_t; typedef struct { - unsigned int valid; // Flag to invalidate this resource - unsigned int instance; // Hardware instance of this DMA controller - unsigned int id; // Channel ID, which matches the index into the underlying hardware - mxc_dma_reva_ch_regs_t *regs; // Pointer to the registers for this channel - void(*cb)(int, int); // Pointer to a callback function type + unsigned int valid; // Flag to invalidate this resource + unsigned int instance; // Hardware instance of this DMA controller + unsigned int id; // Channel ID, which matches the index into the underlying hardware + mxc_dma_reva_ch_regs_t *regs; // Pointer to the registers for this channel + void (*cb)(int, int); // Pointer to a callback function type } mxc_dma_channel_t; /******* Globals *******/ -static unsigned int dma_initialized[MXC_DMA_INSTANCES] = {0}; +static unsigned int dma_initialized[MXC_DMA_INSTANCES] = { 0 }; static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS]; static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS]; -#if USE_LOCK_IN_DRIVERS - static uint32_t dma_lock; -#endif +static uint32_t dma_lock; /****** Functions ******/ static void memcpy_callback(int ch, int error); @@ -78,59 +73,59 @@ int i, numCh, offset; #if TARGET_NUM == 32665 numCh = MXC_DMA_CH_OFFSET; - offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); + offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma); #else numCh = MXC_DMA_CHANNELS; offset = 0; #endif - - if(dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) { + + if (dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]) { return E_BAD_STATE; } - + #ifndef __riscv - /* Initialize mutex */ - MXC_FreeLock(&dma_lock); - - if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { - return E_BUSY; - } + /* Initialize mutex */ + MXC_FreeLock(&dma_lock); + + if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } #endif - + /* Ensure all channels are disabled at start, clear flags, init handles */ dma->inten = 0; - - for(i = offset; i < (offset + numCh); i++) { + + for (i = offset; i < (offset + numCh); i++) { dma_resource[i].valid = 0; dma_resource[i].instance = 0; dma_resource[i].id = i; - dma_resource[i].regs = (mxc_dma_reva_ch_regs_t*) &(dma->ch[(i % numCh)]); + dma_resource[i].regs = (mxc_dma_reva_ch_regs_t *)&(dma->ch[(i % numCh)]); dma_resource[i].regs->ctrl = 0; dma_resource[i].regs->status = dma_resource[i].regs->status; - + dma_resource[i].cb = NULL; } - - dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]++; + + dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]++; #ifndef __riscv - MXC_FreeLock(&dma_lock); + MXC_FreeLock(&dma_lock); #endif - + return E_NO_ERROR; } -int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma) +int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t *dma) { int i, channel, numCh, offset; - + /* Check for initialization */ - if(!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) { + if (!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]) { return E_BAD_STATE; } - + #if TARGET_NUM == 32665 numCh = MXC_DMA_CH_OFFSET; - offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); + offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma); #else numCh = MXC_DMA_CHANNELS; offset = 0; @@ -138,15 +133,15 @@ #ifndef __riscv /* If DMA is locked return busy */ - if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { + if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { return E_BUSY; } #endif /* Default is no channel available */ channel = E_NONE_AVAIL; - - for(i = offset; i < (offset + numCh); i++) { - if(!dma_resource[i].valid) { + + for (i = offset; i < (offset + numCh); i++) { + if (!dma_resource[i].valid) { /* Found one */ channel = i; dma_resource[i].valid = 1; @@ -164,159 +159,142 @@ int MXC_DMA_RevA_ReleaseChannel(int ch) { - if(CHECK_HANDLE(ch)) { - if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { + if (CHECK_HANDLE(ch)) { + if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { return E_BUSY; } - + dma_resource[ch].valid = 0; dma_resource[ch].regs->ctrl = 0; dma_resource[ch].regs->status = dma_resource[ch].regs->status; MXC_FreeLock(&dma_lock); - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst) { - if(CHECK_HANDLE(config.ch)) { + if (CHECK_HANDLE(config.ch)) { /* Designed to be safe, not speedy. Should not be called often */ dma_resource[config.ch].regs->ctrl = - ((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) | - (config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) | - config.reqsel | - (config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) | - (config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS)); - } - else { + ((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) | + (config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) | config.reqsel | + (config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) | + (config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS)); + } else { return E_BAD_PARAM; } - + return MXC_DMA_RevA_SetSrcDst(srcdst); } - int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) { - if(CHECK_HANDLE(advConfig.ch) &&(advConfig.burst_size > 0)) { + if (CHECK_HANDLE(advConfig.ch) && (advConfig.burst_size > 0)) { dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here /* Designed to be safe, not speedy. Should not be called often */ dma_resource[advConfig.ch].regs->ctrl |= - ((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | - advConfig.prio | advConfig.tosel | advConfig.pssel | - (((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & MXC_F_DMA_REVA_CTRL_BURST_SIZE)); - } - else { + ((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | advConfig.prio | + advConfig.tosel | advConfig.pssel | + (((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & + MXC_F_DMA_REVA_CTRL_BURST_SIZE)); + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } - int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst) { - if(CHECK_HANDLE(srcdst.ch)) { - dma_resource[srcdst.ch].regs->src = (unsigned int) srcdst.source; - dma_resource[srcdst.ch].regs->dst = (unsigned int) srcdst.dest; + if (CHECK_HANDLE(srcdst.ch)) { + dma_resource[srcdst.ch].regs->src = (unsigned int)srcdst.source; + dma_resource[srcdst.ch].regs->dst = (unsigned int)srcdst.dest; dma_resource[srcdst.ch].regs->cnt = srcdst.len; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } - -int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t* srcdst) +int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst) { if (CHECK_HANDLE(srcdst->ch)) { - srcdst->source = (void*) dma_resource[srcdst->ch].regs->src; - srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dst; + srcdst->source = (void *)dma_resource[srcdst->ch].regs->src; + srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dst; srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_REVA_CNTRLD_EN; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } - int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst) { - if(CHECK_HANDLE(srcdst.ch)) { - dma_resource[srcdst.ch].regs->srcrld = (unsigned int) srcdst.source; - dma_resource[srcdst.ch].regs->dstrld = (unsigned int) srcdst.dest; - - if(dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) { + if (CHECK_HANDLE(srcdst.ch)) { + dma_resource[srcdst.ch].regs->srcrld = (unsigned int)srcdst.source; + dma_resource[srcdst.ch].regs->dstrld = (unsigned int)srcdst.dest; + + if (dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) { /* If channel is already running, set RLDEN to enable next reload */ dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_REVA_CNTRLD_EN | srcdst.len; - } - else { + } else { /* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */ dma_resource[srcdst.ch].regs->cntrld = srcdst.len; } - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } - -int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t* srcdst) +int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst) { if (CHECK_HANDLE(srcdst->ch)) { - srcdst->source = (void*) dma_resource[srcdst->ch].regs->srcrld; - srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dstrld; + srcdst->source = (void *)dma_resource[srcdst->ch].regs->srcrld; + srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dstrld; srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_REVA_CNTRLD_EN; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } - -int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int)) +int MXC_DMA_RevA_SetCallback(int ch, void (*callback)(int, int)) { - if(CHECK_HANDLE(ch)) { + if (CHECK_HANDLE(ch)) { /* Callback for interrupt handler, no checking is done, as NULL is valid for(none) */ dma_resource[ch].cb = callback; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz) { - if(CHECK_HANDLE(ch)) { - if(chdis){ - dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE); - } - if(ctz){ - dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE); - } - } - else { + if (CHECK_HANDLE(ch)) { + if (chdis) { + dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE); + } + if (ctz) { + dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE); + } + } else { return E_BAD_PARAM; } return E_NO_ERROR; } - int MXC_DMA_RevA_GetChannelInterruptEn(int ch) { return E_NOT_SUPPORTED; @@ -324,119 +302,111 @@ int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags) { - if(CHECK_HANDLE(ch)) { - dma_resource[ch].regs->ctrl |= (flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE)); - } - else { + if (CHECK_HANDLE(ch)) { + dma_resource[ch].regs->ctrl |= + (flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE)); + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags) { - if(CHECK_HANDLE(ch)) { - dma_resource[ch].regs->ctrl &= ~(flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE)); - } - else { + if (CHECK_HANDLE(ch)) { + dma_resource[ch].regs->ctrl &= + ~(flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE)); + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch) { - if(CHECK_HANDLE(ch)) { - #if TARGET_NUM == 32665 + if (CHECK_HANDLE(ch)) { +#if TARGET_NUM == 32665 ch %= MXC_DMA_CH_OFFSET; - #endif - dma->inten |= (1 << ch); - } - else { +#endif + dma->inten |= (1 << ch); + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch) { - if(CHECK_HANDLE(ch)) { - #if TARGET_NUM == 32665 + if (CHECK_HANDLE(ch)) { +#if TARGET_NUM == 32665 ch %= MXC_DMA_CH_OFFSET; - #endif - dma->inten &= ~(1 << ch); - } - else { +#endif + dma->inten &= ~(1 << ch); + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_ChannelGetFlags(int ch) { - if(CHECK_HANDLE(ch)) { + if (CHECK_HANDLE(ch)) { return dma_resource[ch].regs->status; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags) { - if(CHECK_HANDLE(ch)) { - dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags - } - else { + if (CHECK_HANDLE(ch)) { + dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_Start(int ch) { - if(CHECK_HANDLE(ch)) { + if (CHECK_HANDLE(ch)) { MXC_DMA_ChannelClearFlags(ch, MXC_DMA_RevA_ChannelGetFlags(ch)); - - if(dma_resource[ch].regs->cntrld) { + + if (dma_resource[ch].regs->cntrld) { dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_EN | MXC_F_DMA_REVA_CTRL_RLDEN); - } - else { + } else { dma_resource[ch].regs->ctrl |= MXC_F_DMA_REVA_CTRL_EN; } - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } int MXC_DMA_RevA_Stop(int ch) { - if(CHECK_HANDLE(ch)) { + if (CHECK_HANDLE(ch)) { dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_REVA_CTRL_EN; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } -mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch) +mxc_dma_ch_regs_t *MXC_DMA_RevA_GetCHRegs(int ch) { - if(CHECK_HANDLE(ch)) { - return(mxc_dma_ch_regs_t*) dma_resource[ch].regs; - } - else { + if (CHECK_HANDLE(ch)) { + return (mxc_dma_ch_regs_t *)dma_resource[ch].regs; + } else { return NULL; } } @@ -444,17 +414,21 @@ void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma) { int numCh = MXC_DMA_CHANNELS / MXC_DMA_INSTANCES; - int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); + int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma); /* Do callback, if enabled */ - for(int i = offset; i < (offset + numCh); i++) { - if(CHECK_HANDLE(i)) { - if(dma->intfl &(0x1 << (i % numCh))) { - if(dma_resource[i].cb != NULL) { + for (int i = offset; i < (offset + numCh); i++) { + if (CHECK_HANDLE(i)) { + if (dma->intfl & (0x1 << (i % numCh))) { + if (dma_resource[i].cb != NULL) { dma_resource[i].cb(i, E_NO_ERROR); } - + MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevA_ChannelGetFlags(i)); - break; + + // No need to check rest of the channels if no interrupt flags set. + if (dma->intfl == 0) { + break; + } } } } @@ -463,72 +437,76 @@ void memcpy_callback(int ch, int error) { mxc_dma_complete_cb_t callback; - callback = (mxc_dma_complete_cb_t) memcpy_resource[ch].userCallback; - - if(error != E_NO_ERROR) { + callback = (mxc_dma_complete_cb_t)memcpy_resource[ch].userCallback; + + if (error != E_NO_ERROR) { callback(NULL); } - + callback(memcpy_resource[ch].dest); - + + // Release global objects and local resources callback = NULL; + memcpy_resource[ch].userCallback = NULL; + memcpy_resource[ch].dest = NULL; MXC_DMA_ReleaseChannel(ch); } -int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback) +int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback) { int retval; mxc_dma_config_t config; mxc_dma_srcdst_t transfer; int channel; - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma); - #else +#if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); +#else channel = MXC_DMA_AcquireChannel(); - #endif - - if(memcpy_resource[channel].userCallback != NULL) { +#endif + + if (memcpy_resource[channel].userCallback != NULL) { // We acquired a channel we haven't cleared yet MXC_DMA_ReleaseChannel(channel); return E_UNKNOWN; } - + transfer.ch = channel; transfer.source = src; transfer.dest = dest; transfer.len = len; - + config.ch = channel; config.reqsel = MXC_DMA_REQUEST_MEMTOMEM; config.srcwd = MXC_DMA_WIDTH_WORD; config.dstwd = MXC_DMA_WIDTH_WORD; config.srcinc_en = 1; config.dstinc_en = 1; - + retval = MXC_DMA_ConfigChannel(config, transfer); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + retval = MXC_DMA_EnableInt(channel); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + MXC_DMA_SetCallback(channel, memcpy_callback); - - memcpy_resource[channel].userCallback = (void*) callback; + + memcpy_resource[channel].userCallback = (void *)callback; memcpy_resource[channel].dest = dest; - + return MXC_DMA_Start(channel); } @@ -539,46 +517,47 @@ // Call user callback for next transfer // determine whether to load into the transfer slot or reload slot // continue on or stop - while(1); + while (1) {} } -int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) +int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, + mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) { int retval, channel; - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma); - #else +#if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); +#else channel = MXC_DMA_AcquireChannel(); - #endif - - if(memcpy_resource[channel].userCallback != NULL) { +#endif + + if (memcpy_resource[channel].userCallback != NULL) { // We acquired a channel we haven't cleared yet MXC_DMA_ReleaseChannel(channel); return E_UNKNOWN; } - + retval = MXC_DMA_ConfigChannel(config, firstSrcDst); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + retval = MXC_DMA_EnableInt(channel); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE); - - if(retval != E_NO_ERROR) { + + if (retval != E_NO_ERROR) { return retval; } - + MXC_DMA_SetCallback(channel, transfer_callback); - - memcpy_resource[channel].userCallback = (void*) callback; - + + memcpy_resource[channel].userCallback = (void *)callback; + return MXC_DMA_Start(channel); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.h index c46e8c5..bb254a2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.h @@ -1,8 +1,8 @@ -/* **************************************************************************** - * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_ /****** Includes *******/ #include "dma_reva_regs.h" @@ -41,7 +44,7 @@ /****** Functions ******/ int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma); -int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma); +int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t *dma); int MXC_DMA_RevA_ReleaseChannel(int ch); int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); @@ -49,7 +52,7 @@ int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst); int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst); int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst); -int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int)); +int MXC_DMA_RevA_SetCallback(int ch, void (*callback)(int, int)); int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags); int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags); @@ -59,7 +62,11 @@ int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch); int MXC_DMA_RevA_Start(int ch); int MXC_DMA_RevA_Stop(int ch); -mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch); +mxc_dma_ch_regs_t *MXC_DMA_RevA_GetCHRegs(int ch); void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma); -int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback); -int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); +int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback); +int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, + mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h index 2f65f7d..0cb0b1c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _DMA_REVA_REGS_H_ #define _DMA_REVA_REGS_H_ @@ -86,14 +85,14 @@ * Structure type to access the DMA Registers. */ typedef struct { - __IO uint32_t ctrl; /**< \b 0x100: DMA CTRL Register */ - __IO uint32_t status; /**< \b 0x104: DMA STATUS Register */ - __IO uint32_t src; /**< \b 0x108: DMA SRC Register */ - __IO uint32_t dst; /**< \b 0x10C: DMA DST Register */ - __IO uint32_t cnt; /**< \b 0x110: DMA CNT Register */ - __IO uint32_t srcrld; /**< \b 0x114: DMA SRCRLD Register */ - __IO uint32_t dstrld; /**< \b 0x118: DMA DSTRLD Register */ - __IO uint32_t cntrld; /**< \b 0x11C: DMA CNTRLD Register */ + __IO uint32_t ctrl; /**< \b 0x000: DMA CTRL Register */ + __IO uint32_t status; /**< \b 0x004: DMA STATUS Register */ + __IO uint32_t src; /**< \b 0x008: DMA SRC Register */ + __IO uint32_t dst; /**< \b 0x00C: DMA DST Register */ + __IO uint32_t cnt; /**< \b 0x010: DMA CNT Register */ + __IO uint32_t srcrld; /**< \b 0x014: DMA SRCRLD Register */ + __IO uint32_t dstrld; /**< \b 0x018: DMA DSTRLD Register */ + __IO uint32_t cntrld; /**< \b 0x01C: DMA CNTRLD Register */ } mxc_dma_reva_ch_regs_t; typedef struct { @@ -110,14 +109,14 @@ * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. * @{ */ - #define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ - #define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: 0x0104 */ - #define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: 0x0108 */ - #define MXC_R_DMA_REVA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: 0x010C */ - #define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: 0x0110 */ - #define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: 0x0114 */ - #define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: 0x0118 */ - #define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: 0x011C */ + #define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0100 */ + #define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0104 */ + #define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: 0x0108 */ + #define MXC_R_DMA_REVA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: 0x010C */ + #define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: 0x0110 */ + #define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: 0x0114 */ + #define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: 0x0118 */ + #define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: 0x011C */ #define MXC_R_DMA_REVA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ #define MXC_R_DMA_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ #define MXC_R_DMA_REVA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.c index 9703d68..7675569 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.c @@ -1,10 +1,10 @@ /** - * @file flc.h - * @brief Flash Controler driver. + * @file flc_common.c + * @brief Common functions for the flash controller drivers. * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -43,79 +42,78 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "flc.h" +#include "flc_common.h" #include "stdlib.h" //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif // Length is number of 32-bit words -int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t* data) +int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t *data) { - volatile uint32_t* ptr; - - - for (ptr = (uint32_t*) address; ptr < (((uint32_t*)(address)) + length); ptr++, data++) { + volatile uint32_t *ptr; + + for (ptr = (uint32_t *)address; ptr < (((uint32_t *)(address)) + length); ptr++, data++) { if (*ptr != *data) { return E_BAD_STATE; } } - + return E_NO_ERROR; } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif // make sure to disable ICC with ICC_Disable(); before Running this function -int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer) +int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t *buffer) { int err; uint32_t bytes_written; uint32_t current_data_32; - uint8_t* current_data = (uint8_t*) ¤t_data_32; - uint8_t* buffer8 = (uint8_t*)buffer; + uint8_t *current_data = (uint8_t *)¤t_data_32; + uint8_t *buffer8 = (uint8_t *)buffer; // Align the address to a word boundary and read/write if we have to if (address & 0x3) { - // Figure out how many bytes we have to write to round up the address bytes_written = 4 - (address & 0x3); - + // Save the data currently in the flash - memcpy(current_data, (void*)(address & (~0x3)), 4); - + memcpy(current_data, (void *)(address & (~0x3)), 4); + // Modify current_data to insert the data from buffer memcpy(¤t_data[4 - bytes_written], buffer8, bytes_written); - + // Write the modified data if ((err = MXC_FLC_Write32(address - (address % 4), current_data_32)) != E_NO_ERROR) { return err; } - + address += bytes_written; length -= bytes_written; buffer8 += bytes_written; } - + // Align the address to a 4-word (128bit) boundary while ((length >= 4) && ((address & 0xF) != 0)) { memcpy(current_data, buffer8, 4); if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) { return err; } - + address += 4; length -= 4; buffer8 += 4; } - + if (length >= 16) { uint32_t buff128[4]; while (length >= 16) { @@ -123,48 +121,46 @@ if ((err = MXC_FLC_Write128(address, buff128)) != E_NO_ERROR) { return err; } - + address += 16; length -= 16; buffer8 += 16; } - } - + while (length >= 4) { memcpy(current_data, buffer8, 4); if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) { return err; } - + address += 4; length -= 4; buffer8 += 4; } - + if (length > 0) { // Save the data currently in the flash - memcpy(current_data, (void*)(address), 4); - + memcpy(current_data, (void *)(address), 4); + // Modify current_data to insert the data from buffer memcpy(current_data, buffer8, length); - + if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) { return err; } } - + return E_NO_ERROR; } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -void MXC_FLC_Com_Read(int address, void* buffer, int len) +void MXC_FLC_Com_Read(int address, void *buffer, int len) { - memcpy(buffer, (void*) address, len); + memcpy(buffer, (void *)address, len); } - diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.h index 5b4d673..16d5759 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.h @@ -1,11 +1,11 @@ /** - * @file flc.h - * @brief Flash Controller driver. + * @file flc_common.h + * @brief Common functions for the flash controller driver. * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,9 +35,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_ /* **** Includes **** */ #include "mxc_sys.h" @@ -54,19 +55,22 @@ /***** Definitions *****/ - - /***** Function Prototypes *****/ -int MXC_FLC_Com_VerifyData (uint32_t address, uint32_t length, uint32_t * data); +int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t *data); -int MXC_FLC_Com_Write (uint32_t address, uint32_t length, uint32_t *buffer); +int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t *buffer); -void MXC_FLC_Com_Read (int address, void* buffer, int len); +void MXC_FLC_Com_Read(int address, void *buffer, int len); + +volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num); + +volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num); /**@} end of group flc */ - #ifdef __cplusplus } #endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_me15.c index 9aef444..63e1c89 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_me15.c @@ -1,10 +1,10 @@ /** - * @file flc.h + * @file flc_me15.c * @brief Flash Controler driver. * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -43,7 +42,7 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "flc.h" -#include "flc_revb.h" +#include "flc_reva.h" #include "flc_common.h" #include "ecc_regs.h" // For ECCEN registers. #include "mcr_regs.h" // For ECCEN registers. @@ -53,74 +52,69 @@ { /* Flush all instruction caches */ MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC0_FLUSH; - + /* Wait for flush to complete */ - while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) { - } + while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) {} } //****************************************************************************** -int MXC_FLC_ME15_GetByAddress(mxc_flc_regs_t** flc, uint32_t addr) +int MXC_FLC_ME15_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr) { - if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { - *flc = MXC_FLC0; - } - else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { *flc = MXC_FLC0; - } - else { + } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + *flc = MXC_FLC0; + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } //****************************************************************************** -int MXC_FLC_ME15_GetPhysicalAddress (uint32_t addr, uint32_t *result) +int MXC_FLC_ME15_GetPhysicalAddress(uint32_t addr, uint32_t *result) { if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { *result = addr - MXC_FLASH_MEM_BASE; - } - else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { /* For ME15, the info block base was located at the next power of 2 address beyond the main flash. The ME15 ends at 0x5FFFF, so the info block starts at 0x80000. */ *result = (addr & (MXC_INFO_MEM_SIZE - 1)) + 0x80000; - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } //****************************************************************************** - int MXC_FLC_Init() { return E_NO_ERROR; } +//****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif int MXC_FLC_Busy(void) { - return MXC_FLC_RevB_Busy(); + return MXC_FLC_RevA_Busy(); } +//****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -int MXC_FLC_ME15_PageErase(uint32_t address) +int MXC_FLC_PageErase(uint32_t address) { int err; uint32_t addr; - mxc_flc_regs_t* flc = NULL; + mxc_flc_regs_t *flc = NULL; // Get FLC Instance if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) { @@ -131,184 +125,224 @@ return err; } - err = MXC_FLC_RevB_PageErase ((mxc_flc_revb_regs_t*) flc, addr); + err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)flc, addr); // Flush the cache MXC_FLC_ME15_Flash_Operation(); - + return err; } +//****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif // make sure to disable ICC with ICC_Disable(); before Running this function -int MXC_FLC_ME15_Write128(uint32_t address, uint32_t* data) +int MXC_FLC_Write128(uint32_t address, uint32_t *data) { int err; - mxc_flc_regs_t* flc = NULL; + mxc_flc_regs_t *flc = NULL; uint32_t addr; - + // Address checked if it is 128-bit aligned if (address & 0xF) { return E_BAD_PARAM; } - + // Get FLC Instance if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) { return err; } - + if ((err = MXC_FLC_ME15_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { return err; } - - if((err= MXC_FLC_RevB_Write128 ((mxc_flc_revb_regs_t*) flc, addr, data)) != E_NO_ERROR) { + + if ((err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)flc, addr, data)) != E_NO_ERROR) { return err; } - + // Flush the cache MXC_FLC_ME15_Flash_Operation(); - + if ((err = MXC_FLC_Com_VerifyData(address, 4, data)) != E_NO_ERROR) { return err; } - + return E_NO_ERROR; } //****************************************************************************** -int MXC_FLC_ME15_Write32(uint32_t address, uint32_t data) +int MXC_FLC_Write32(uint32_t address, uint32_t data) { uint32_t addr, aligned; int err; - mxc_flc_regs_t* flc = NULL; - + mxc_flc_regs_t *flc = NULL; + // Address checked if it is byte addressable if (address & 0x3) { return E_BAD_PARAM; } - + // Align address to 128-bit word aligned = address & 0xfffffff0; - + // Get FLC Instance if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) { return err; } - + if ((err = MXC_FLC_ME15_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { return err; } - + if (MXC_ECC->en & MXC_F_ECC_EN_FLASH) { - return E_BAD_STATE; } - - return MXC_FLC_RevB_Write32 ((mxc_flc_revb_regs_t*) flc, address, data, addr); - + + return MXC_FLC_RevA_Write32Using128((mxc_flc_reva_regs_t *)flc, address, data, addr); } -int MXC_FLC_ME15_MassErase(void) +//****************************************************************************** +int MXC_FLC_MassErase(void) { int err, i; - mxc_flc_regs_t* flc; - - for (i=0; i (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return E_INVALID; + } + + return MXC_FLC_RevA_BlockPageWrite(address, MXC_FLASH_MEM_BASE); } -int MXC_FLC_LockInfoBlock(uint32_t address) +//****************************************************************************** +int MXC_FLC_BlockPageRead(uint32_t address) { - return MXC_FLC_ME15_LockInfoBlock(address); + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return E_INVALID; + } + + return MXC_FLC_RevA_BlockPageRead(address, MXC_FLASH_MEM_BASE); +} + +//****************************************************************************** +volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num) +{ + uint32_t reg_num; + reg_num = page_num >> + 5; // Divide by 32 to get WELR register number containing the page lock bit + + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return NULL; + } + + switch (reg_num) { + case 0: + return &(MXC_FLC0->welr0); + case 1: + return &(MXC_FLC0->welr1); + } + + return NULL; +} + +//****************************************************************************** +volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num) +{ + uint32_t reg_num; + reg_num = page_num >> 5; // Divide by 32 to get RLR register number containing the page lock bit + + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return NULL; + } + + switch (reg_num) { + case 0: + return &(MXC_FLC0->rlr0); + case 1: + return &(MXC_FLC0->rlr1); + } + + return NULL; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.c index d1b21f6..befba39 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.c @@ -3,8 +3,8 @@ * @brief Flash Controler driver. * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -54,54 +53,55 @@ /* **** Globals **** */ #ifdef MXC_FLC0 -static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t*) MXC_FLC0; +static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t *)MXC_FLC0; #else -static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t*) MXC_FLC; +static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t *)MXC_FLC; #endif /* **** Functions **** */ //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -static int MXC_busy_flc(mxc_flc_reva_regs_t* flc) +static int MXC_busy_flc(mxc_flc_reva_regs_t *flc) { - return (flc->ctrl & (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE)); + return (flc->ctrl & + (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE)); } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -static int MXC_prepare_flc(mxc_flc_reva_regs_t* flc) +static int MXC_prepare_flc(mxc_flc_reva_regs_t *flc) { /* Check if the flash controller is busy */ if (MXC_busy_flc(flc)) { return E_BUSY; } - + // Set flash clock divider to generate a 1MHz clock from the APB clock flc->clkdiv = SystemCoreClock / 1000000; - + /* Clear stale errors */ if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; } - + /* Unlock flash */ flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_UNLOCK) | MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED; - + return E_NO_ERROR; } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif @@ -110,60 +110,61 @@ uint32_t flc_cn = 0; int i; mxc_flc_reva_regs_t *flc; - + for (i = 0; i < MXC_FLC_INSTANCES; i++) { - flc = (mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC (i); - flc_cn = MXC_busy_flc (flc); - + flc = (mxc_flc_reva_regs_t *)MXC_FLC_GET_FLC(i); + flc_cn = MXC_busy_flc(flc); + if (flc_cn != 0) { break; } } - + return flc_cn; } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc) +int MXC_FLC_RevA_MassErase(mxc_flc_reva_regs_t *flc) { int err; - + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { return err; } - + /* Write mass erase code */ - flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL; - + flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | + MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL; + /* Issue mass erase command */ flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME; - + /* Wait until flash operation is complete */ - while (MXC_busy_flc(flc)); - + while (MXC_busy_flc(flc)) {} + /* Lock flash */ flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; - + /* Check access violations */ if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; return E_BAD_STATE; } - + return E_NO_ERROR; } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif -int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr) +int MXC_FLC_RevA_PageErase(mxc_flc_reva_regs_t *flc, uint32_t addr) { int err; @@ -172,108 +173,158 @@ } /* Write page erase code */ - flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE; + flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | + MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE; /* Issue page erase command */ flc->addr = addr; flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE; - + /* Wait until flash operation is complete */ - while (MXC_FLC_Busy()); - + while (MXC_busy_flc(flc)) {} + /* Lock flash */ flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; - + /* Check access violations */ if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; return E_BAD_STATE; } - + return E_NO_ERROR; } - - //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif // make sure to disable ICC with ICC_Disable(); before Running this function -int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr) +int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data, + uint32_t physicalAddr) { - int err, i = 0; - uint32_t byte; - volatile uint32_t* ptr; - uint32_t current_data[4] = {0, 0, 0, 0}; - + int err; + // Address checked if it is byte addressable if (logicAddr & 0x3) { return E_BAD_PARAM; } - + // Check if the location trying to be written has 1's in to be written to 0's - if ((* (uint32_t*) logicAddr & data) != data) { + if ((*(uint32_t *)logicAddr & data) != data) { return E_BAD_STATE; } - + + // Align address to 32-bit word + logicAddr = logicAddr & 0xfffffffc; + + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { + return err; + } + + // write 32-bits + flc->ctrl |= MXC_F_FLC_REVA_CTRL_WDTH; + + // write the data + flc->addr = logicAddr; + flc->data[0] = data; + flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR; + + /* Wait until flash operation is complete */ + while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND) != 0) {} + while (MXC_busy_flc(flc)) {} + + /* Lock flash */ + flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; + + /* Check access violations */ + if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { + flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; + return E_BAD_STATE; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +// make sure to disable ICC with ICC_Disable(); before Running this function +int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data, + uint32_t physicalAddr) +{ + int err, i = 0; + uint32_t byte; + volatile uint32_t *ptr; + uint32_t current_data[4] = { 0, 0, 0, 0 }; + + // Address checked if it is byte addressable + if (logicAddr & 0x3) { + return E_BAD_PARAM; + } + + // Check if the location trying to be written has 1's in to be written to 0's + if ((*(uint32_t *)logicAddr & data) != data) { + return E_BAD_STATE; + } + // Get byte idx within 128-bit word byte = (logicAddr & 0xf); // Align address to 128-bit word logicAddr = logicAddr & 0xfffffff0; - + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { return err; } - + // Get current data stored in flash - for (ptr = (uint32_t*) logicAddr; ptr < (uint32_t*)(logicAddr + 16); ptr++, i++) { + for (ptr = (uint32_t *)logicAddr; ptr < (uint32_t *)(logicAddr + 16); ptr++, i++) { current_data[i] = *ptr; } - + // write the data flc->addr = physicalAddr; - + if (byte < 4) { current_data[0] = data; - } - else if (byte < 8) { + } else if (byte < 8) { current_data[1] = data; - } - else if (byte < 12) { + } else if (byte < 12) { current_data[2] = data; - } - else { + } else { current_data[3] = data; } - + return MXC_FLC_Write128(logicAddr, current_data); } //****************************************************************************** #if IAR_PRAGMAS -#pragma section=".flashprog" +#pragma section = ".flashprog" #else __attribute__((section(".flashprog"))) #endif // make sure to disable ICC with ICC_Disable(); before Running this function -int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data) +int MXC_FLC_RevA_Write128(mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data) { int err; - + // Address checked if it is 128-bit aligned if (addr & 0xF) { return E_BAD_PARAM; } - + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { return err; } - + // write 128-bits flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_WDTH; - + // write the data flc->addr = addr; flc->data[0] = data[0]; @@ -283,18 +334,18 @@ flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR; /* Wait until flash operation is complete */ - while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND)!=0){} - while (MXC_busy_flc (flc)){} - + while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND) != 0) {} + while (MXC_busy_flc(flc)) {} + /* Lock flash */ flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; - + /* Check access violations */ if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; return E_BAD_STATE; } - + return E_NO_ERROR; } @@ -305,7 +356,7 @@ } //****************************************************************************** -mxc_flc_reva_regs_t* MXC_FLC_RevA_GetFLCInt(void) +mxc_flc_reva_regs_t *MXC_FLC_RevA_GetFLCInt(void) { return flc_int; } @@ -313,32 +364,32 @@ //****************************************************************************** int MXC_FLC_RevA_EnableInt(uint32_t mask) { - mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); - + mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); + if (!mask) { /* No bits set? Wasn't something we can enable. */ return E_BAD_PARAM; } - + /* Apply enables and write back, preserving the flags */ flc_int->intr |= mask; - + return E_NO_ERROR; } //****************************************************************************** int MXC_FLC_RevA_DisableInt(uint32_t mask) { - mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); - + mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); + if (!mask) { /* No bits set? Wasn't something we can disable. */ return E_BAD_PARAM; } - + /* Apply disables and write back, preserving the flags */ flc_int->intr &= ~mask; - + return E_NO_ERROR; } @@ -352,44 +403,83 @@ int MXC_FLC_RevA_ClearFlags(uint32_t mask) { mask &= (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF); - + if (!mask) { /* No bits set? Wasn't something we can clear. */ return E_BAD_PARAM; } - + /* Both flags are write zero clear */ flc_int->intr ^= mask; - + return E_NO_ERROR; } //****************************************************************************** -int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address) +int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address) { - if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { + if ((address < MXC_INFO_MEM_BASE) || + (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { return E_BAD_PARAM; } /* Make sure the info block is locked */ flc->actrl = 0x1234; - + /* Write the unlock sequence */ flc->actrl = 0x3a7f5ca3; flc->actrl = 0xa1e34f20; flc->actrl = 0x9608b2c1; - + return E_NO_ERROR; } //****************************************************************************** -int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address) +int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address) { - if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { + if ((address < MXC_INFO_MEM_BASE) || + (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { return E_BAD_PARAM; } - + flc->actrl = 0xDEADBEEF; return E_NO_ERROR; } + +//****************************************************************************** +int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base) +{ + uint32_t page_num; + page_num = address - bank_base; // Get page number in flash bank + page_num /= MXC_FLASH_PAGE_SIZE; + + volatile uint32_t *welr = MXC_FLC_GetWELR( + address, page_num); // Get pointer to WELR register containing corresponding page bit + + while (page_num > 31) { // Set corresponding bit in WELR register + page_num -= 32; + } + *welr = (1 << page_num); + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base) +{ + uint32_t page_num; + page_num = address - bank_base; // Get page number in flash bank + page_num /= MXC_FLASH_PAGE_SIZE; + + volatile uint32_t *rlr = MXC_FLC_GetRLR( + address, page_num); // Get pointer to RLR register containing corresponding page bit + + while (page_num > 31) { // Set corresponding bit in WELR register + page_num -= 32; + } + *rlr = (1 << page_num); + + return E_NO_ERROR; +} + /**@} end of group flc */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.h index 4f5173e..6188287 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.h @@ -1,10 +1,10 @@ /** - * @file flc.h - * @brief Flash Controler driver. + * @file flc_reva.h + * @brief Flash RevA Controller driver. * @details This driver can be used to operate on the embedded flash memory. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_ /* **** Includes **** */ #include @@ -43,6 +45,7 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "flc.h" +#include "flc_common.h" #include "flc_reva_regs.h" /** @@ -56,34 +59,44 @@ /* **** Functions **** */ -int MXC_FLC_RevA_Busy (void); +int MXC_FLC_RevA_Busy(void); -int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc); +int MXC_FLC_RevA_MassErase(mxc_flc_reva_regs_t *flc); -int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc,uint32_t addr); +int MXC_FLC_RevA_PageErase(mxc_flc_reva_regs_t *flc, uint32_t addr); -int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr); +int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, + uint32_t physicalAddr); -int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data); +int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, + uint32_t physicalAddr); -void MXC_FLC_RevA_SetFLCInt (mxc_flc_reva_regs_t *flc); +int MXC_FLC_RevA_Write128(mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data); -mxc_flc_reva_regs_t* MXC_FLC_RevA_GetFLCInt (void); +void MXC_FLC_RevA_SetFLCInt(mxc_flc_reva_regs_t *flc); -int MXC_FLC_RevA_EnableInt (uint32_t mask); +mxc_flc_reva_regs_t *MXC_FLC_RevA_GetFLCInt(void); -int MXC_FLC_RevA_DisableInt (uint32_t mask); +int MXC_FLC_RevA_EnableInt(uint32_t mask); -int MXC_FLC_RevA_GetFlags (void); +int MXC_FLC_RevA_DisableInt(uint32_t mask); -int MXC_FLC_RevA_ClearFlags (uint32_t mask); +int MXC_FLC_RevA_GetFlags(void); -int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address); +int MXC_FLC_RevA_ClearFlags(uint32_t mask); -int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address); +int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address); + +int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address); + +int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base); + +int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base); + /**@} end of group flc */ - #ifdef __cplusplus } #endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h index d6fb3cd..bf6419f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _FLC_REVA_REGS_H_ -#define _FLC_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,13 +45,13 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) - #pragma system_include +#pragma system_include #endif - + #if defined (__CC_ARM) - #pragma anon_unions +#pragma anon_unions #endif /// @cond /* @@ -104,13 +103,13 @@ * @brief FLC_REVA Peripheral Register Offsets from the FLC_REVA Base Peripheral Address. * @{ */ - #define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: 0x0000 */ - #define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: 0x0004 */ - #define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: 0x0008 */ - #define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: 0x0024 */ - #define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: 0x0028 */ - #define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: 0x0030 */ - #define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: 0x0040 */ +#define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: 0x0000 */ +#define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: 0x0004 */ +#define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: 0x0008 */ +#define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: 0x0024 */ +#define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: 0x0028 */ +#define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: 0x0030 */ +#define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: 0x0040 */ /**@} end of group flc_reva_registers */ /** @@ -119,8 +118,8 @@ * @brief Flash Write Address. * @{ */ - #define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ - #define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ +#define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ +#define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ /**@} end of group FLC_REVA_ADDR_Register */ @@ -131,8 +130,8 @@ * MHz clock for Flash controller. * @{ */ - #define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ - #define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ +#define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ /**@} end of group FLC_REVA_CLKDIV_Register */ @@ -142,39 +141,39 @@ * @brief Flash Control Register. * @{ */ - #define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */ - #define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */ +#define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */ +#define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */ - #define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */ - #define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */ +#define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */ +#define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */ - #define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ - #define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ +#define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ +#define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ - #define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */ - #define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */ +#define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */ +#define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */ - #define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ - #define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ - #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ - #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ - #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ - #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ - #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ - #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ +#define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ +#define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ +#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ +#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ +#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ +#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ +#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ +#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ - #define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ - #define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ +#define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ +#define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ - #define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ - #define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ +#define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ +#define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ - #define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ - #define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ - #define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ - #define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ - #define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ - #define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ +#define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ +#define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ +#define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ +#define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ +#define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ +#define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ /**@} end of group FLC_REVA_CTRL_Register */ @@ -184,17 +183,17 @@ * @brief Flash Interrupt Register. * @{ */ - #define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */ - #define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */ +#define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */ +#define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */ - #define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */ - #define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */ +#define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */ +#define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */ - #define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ - #define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ +#define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ +#define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ - #define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ - #define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ +#define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ +#define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ /**@} end of group FLC_REVA_INTR_Register */ @@ -204,11 +203,11 @@ * @brief ECC Data Register. * @{ */ - #define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ - #define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ +#define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ +#define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ - #define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ - #define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ +#define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ +#define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ /**@} end of group FLC_REVA_ECCDATA_Register */ @@ -218,8 +217,8 @@ * @brief Flash Write Data. * @{ */ - #define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */ - #define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */ +#define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */ /**@} end of group FLC_REVA_DATA_Register */ @@ -234,8 +233,8 @@ * this register is always zero. * @{ */ - #define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ - #define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ +#define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ +#define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ /**@} end of group FLC_REVA_ACTRL_Register */ @@ -243,4 +242,4 @@ } #endif -#endif /* _FLC_REVA_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.c deleted file mode 100644 index dbc411c..0000000 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.c +++ /dev/null @@ -1,154 +0,0 @@ -/** - * @file flc.h - * @brief Flash Controler driver. - * @details This driver can be used to operate on the embedded flash memory. - */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - * - * - *************************************************************************** */ - -/* **** Includes **** */ -#include -#include "mxc_device.h" -#include "mxc_assert.h" -#include "mxc_sys.h" -#include "flc.h" -#include "flc_revb.h" -#include "flc_reva.h" - -/** - * @ingroup flc - * @{ - */ - -/* **** Definitions **** */ - -/* **** Globals **** */ - -/* **** Functions **** */ - - -//****************************************************************************** -#if IAR_PRAGMAS -#pragma section=".flashprog" -#else -__attribute__((section(".flashprog"))) -#endif -int MXC_FLC_RevB_Busy(void) -{ - return MXC_FLC_RevA_Busy(); -} -//****************************************************************************** -#if IAR_PRAGMAS -#pragma section=".flashprog" -#else -__attribute__((section(".flashprog"))) -#endif -int MXC_FLC_RevB_MassErase(mxc_flc_revb_regs_t* flc) -{ - return MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t*)flc); -} - -//****************************************************************************** -#if IAR_PRAGMAS -#pragma section=".flashprog" -#else -__attribute__((section(".flashprog"))) -#endif -int MXC_FLC_RevB_PageErase(mxc_flc_revb_regs_t* flc, uint32_t addr) -{ - return MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t*)flc,addr); -} - - - -//****************************************************************************** -#if IAR_PRAGMAS -#pragma section=".flashprog" -#else -__attribute__((section(".flashprog"))) -#endif -// make sure to disable ICC with ICC_Disable(); before Running this function -int MXC_FLC_RevB_Write32(mxc_flc_revb_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr) -{ - return MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t*)flc, logicAddr, data, physicalAddr); -} - -//****************************************************************************** -#if IAR_PRAGMAS -#pragma section=".flashprog" -#else -__attribute__((section(".flashprog"))) -#endif -// make sure to disable ICC with ICC_Disable(); before Running this function -int MXC_FLC_RevB_Write128(mxc_flc_revb_regs_t* flc, uint32_t addr, uint32_t* data) -{ - return MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t*)flc, addr, data); -} - -//****************************************************************************** -int MXC_FLC_RevB_EnableInt(uint32_t mask) -{ - return MXC_FLC_RevA_EnableInt(mask); -} - -//****************************************************************************** -int MXC_FLC_RevB_DisableInt(uint32_t mask) -{ - return MXC_FLC_RevA_DisableInt(mask); -} - -//****************************************************************************** -int MXC_FLC_RevB_GetFlags(void) -{ - return MXC_FLC_RevA_GetFlags(); -} - -//****************************************************************************** -int MXC_FLC_RevB_ClearFlags(uint32_t mask) -{ - return MXC_FLC_RevA_ClearFlags(mask); -} - -//****************************************************************************** -int MXC_FLC_RevB_UnlockInfoBlock(mxc_flc_revb_regs_t* flc, uint32_t address) -{ - return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t*)flc, address); -} - -//****************************************************************************** -int MXC_FLC_RevB_LockInfoBlock(mxc_flc_revb_regs_t* flc, uint32_t address) -{ - return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t*)flc, address); -} -/**@} end of group flc */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.h deleted file mode 100644 index 77dd797..0000000 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * @file flc.h - * @brief Flash Controler driver. - * @details This driver can be used to operate on the embedded flash memory. - */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - * - * - *************************************************************************** */ - -/* **** Includes **** */ -#include -#include "mxc_device.h" -#include "mxc_assert.h" -#include "mxc_sys.h" -#include "flc_revb_regs.h" -#include "mcr_regs.h" // For ECCEN registers. - -/** - * @ingroup flc - * @{ - */ - -/* **** Definitions **** */ - -/* **** Globals **** */ - -/* **** Functions **** */ - -int MXC_FLC_RevB_Busy (void); - -int MXC_FLC_RevB_MassErase (mxc_flc_revb_regs_t *flc); - -int MXC_FLC_RevB_PageErase (mxc_flc_revb_regs_t *flc,uint32_t addr); - -int MXC_FLC_RevB_Write32 (mxc_flc_revb_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr); - -int MXC_FLC_RevB_Write128 (mxc_flc_revb_regs_t *flc, uint32_t addr, uint32_t *data); - -int MXC_FLC_RevB_EnableInt (uint32_t mask); - -int MXC_FLC_RevB_DisableInt (uint32_t mask); - -int MXC_FLC_RevB_GetFlags (void); - -int MXC_FLC_RevB_ClearFlags (uint32_t mask); - -int MXC_FLC_RevB_UnlockInfoBlock (mxc_flc_revb_regs_t *flc, uint32_t address); - -int MXC_FLC_RevB_LockInfoBlock (mxc_flc_revb_regs_t *flc, uint32_t address); -/**@} end of group flc */ - - -#ifdef __cplusplus -} -#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb_regs.h deleted file mode 100644 index 66b8788..0000000 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb_regs.h +++ /dev/null @@ -1,301 +0,0 @@ -/** - * @file flc_revb_regs.h - * @brief Registers, Bit Masks and Bit Positions for the FLC_REVB Peripheral Module. - */ - -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - * - * - *************************************************************************** */ - -#ifndef _FLC_REVB_REGS_H_ -#define _FLC_REVB_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup flc_revb - * @defgroup flc_revb_registers FLC_REVB_Registers - * @brief Registers, Bit Masks and Bit Positions for the FLC_REVB Peripheral Module. - * @details Flash Memory Control. - */ - -/** - * @ingroup flc_revb_registers - * Structure type to access the FLC_REVB Registers. - */ -typedef struct { - __IO uint32_t addr; /**< \b 0x00: FLC_REVB ADDR Register */ - __IO uint32_t clkdiv; /**< \b 0x04: FLC_REVB CLKDIV Register */ - __IO uint32_t ctrl; /**< \b 0x08: FLC_REVB CTRL Register */ - __R uint32_t rsv_0xc_0x23[6]; - __IO uint32_t intr; /**< \b 0x024: FLC_REVB INTR Register */ - __IO uint32_t eccdata; /**< \b 0x028: FLC_REVB ECCDATA Register */ - __R uint32_t rsv_0x2c; - __IO uint32_t data[4]; /**< \b 0x30: FLC_REVB DATA Register */ - __O uint32_t actrl; /**< \b 0x40: FLC_REVB ACTRL Register */ - __R uint32_t rsv_0x44_0x7f[15]; - __IO uint32_t welr0; /**< \b 0x80: FLC_REVB WELR0 Register */ - __R uint32_t rsv_0x84; - __IO uint32_t welr1; /**< \b 0x88: FLC_REVB WELR1 Register */ - __R uint32_t rsv_0x8c; - __IO uint32_t rlr0; /**< \b 0x90: FLC_REVB RLR0 Register */ - __R uint32_t rsv_0x94; - __IO uint32_t rlr1; /**< \b 0x98: FLC_REVB RLR1 Register */ -} mxc_flc_revb_regs_t; - -/* Register offsets for module FLC_REVB */ -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_Register_Offsets Register Offsets - * @brief FLC_REVB Peripheral Register Offsets from the FLC_REVB Base Peripheral Address. - * @{ - */ - #define MXC_R_FLC_REVB_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVB Base Address: 0x0000 */ - #define MXC_R_FLC_REVB_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVB Base Address: 0x0004 */ - #define MXC_R_FLC_REVB_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVB Base Address: 0x0008 */ - #define MXC_R_FLC_REVB_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVB Base Address: 0x0024 */ - #define MXC_R_FLC_REVB_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVB Base Address: 0x0028 */ - #define MXC_R_FLC_REVB_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVB Base Address: 0x0030 */ - #define MXC_R_FLC_REVB_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVB Base Address: 0x0040 */ - #define MXC_R_FLC_REVB_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC_REVB Base Address: 0x0080 */ - #define MXC_R_FLC_REVB_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC_REVB Base Address: 0x0088 */ - #define MXC_R_FLC_REVB_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC_REVB Base Address: 0x0090 */ - #define MXC_R_FLC_REVB_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC_REVB Base Address: 0x0098 */ -/**@} end of group flc_revb_registers */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_ADDR FLC_REVB_ADDR - * @brief Flash Write Address. - * @{ - */ - #define MXC_F_FLC_REVB_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ - #define MXC_F_FLC_REVB_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ - -/**@} end of group FLC_REVB_ADDR_Register */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_CLKDIV FLC_REVB_CLKDIV - * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 - * MHz clock for Flash controller. - * @{ - */ - #define MXC_F_FLC_REVB_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ - #define MXC_F_FLC_REVB_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVB_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ - -/**@} end of group FLC_REVB_CLKDIV_Register */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_CTRL FLC_REVB_CTRL - * @brief Flash Control Register. - * @{ - */ - #define MXC_F_FLC_REVB_CTRL_WR_POS 0 /**< CTRL_WR Position */ - #define MXC_F_FLC_REVB_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_WR_POS)) /**< CTRL_WR Mask */ - - #define MXC_F_FLC_REVB_CTRL_ME_POS 1 /**< CTRL_ME Position */ - #define MXC_F_FLC_REVB_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_ME_POS)) /**< CTRL_ME Mask */ - - #define MXC_F_FLC_REVB_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ - #define MXC_F_FLC_REVB_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ - - #define MXC_F_FLC_REVB_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */ - #define MXC_F_FLC_REVB_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */ - - #define MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ - #define MXC_F_FLC_REVB_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ - #define MXC_V_FLC_REVB_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ - #define MXC_S_FLC_REVB_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVB_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ - #define MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ - #define MXC_S_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ - #define MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ - #define MXC_S_FLC_REVB_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ - - #define MXC_F_FLC_REVB_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ - #define MXC_F_FLC_REVB_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ - - #define MXC_F_FLC_REVB_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ - #define MXC_F_FLC_REVB_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ - - #define MXC_F_FLC_REVB_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ - #define MXC_F_FLC_REVB_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVB_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ - #define MXC_V_FLC_REVB_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ - #define MXC_S_FLC_REVB_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVB_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVB_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ - #define MXC_V_FLC_REVB_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ - #define MXC_S_FLC_REVB_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVB_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVB_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ - -/**@} end of group FLC_REVB_CTRL_Register */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_INTR FLC_REVB_INTR - * @brief Flash Interrupt Register. - * @{ - */ - #define MXC_F_FLC_REVB_INTR_DONE_POS 0 /**< INTR_DONE Position */ - #define MXC_F_FLC_REVB_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_DONE_POS)) /**< INTR_DONE Mask */ - - #define MXC_F_FLC_REVB_INTR_AF_POS 1 /**< INTR_AF Position */ - #define MXC_F_FLC_REVB_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_AF_POS)) /**< INTR_AF Mask */ - - #define MXC_F_FLC_REVB_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ - #define MXC_F_FLC_REVB_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ - - #define MXC_F_FLC_REVB_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ - #define MXC_F_FLC_REVB_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ - -/**@} end of group FLC_REVB_INTR_Register */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_ECCDATA FLC_REVB_ECCDATA - * @brief ECC Data Register. - * @{ - */ - #define MXC_F_FLC_REVB_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ - #define MXC_F_FLC_REVB_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVB_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ - - #define MXC_F_FLC_REVB_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ - #define MXC_F_FLC_REVB_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVB_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ - -/**@} end of group FLC_REVB_ECCDATA_Register */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_DATA FLC_REVB_DATA - * @brief Flash Write Data. - * @{ - */ - #define MXC_F_FLC_REVB_DATA_DATA_POS 0 /**< DATA_DATA Position */ - #define MXC_F_FLC_REVB_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_DATA_DATA_POS)) /**< DATA_DATA Mask */ - -/**@} end of group FLC_REVB_DATA_Register */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_ACTRL FLC_REVB_ACTRL - * @brief Access Control Register. Writing the ACTRL register with the following values in - * the order shown, allows read and write access to the system and user Information - * block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl - * = 0x9608b2c1. When unlocked, a write of any word will disable access to system - * and user information block. Readback of this register is always zero. - * @{ - */ - #define MXC_F_FLC_REVB_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ - #define MXC_F_FLC_REVB_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ - -/**@} end of group FLC_REVB_ACTRL_Register */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_WELR0 FLC_REVB_WELR0 - * @brief WELR0 - * @{ - */ - #define MXC_F_FLC_REVB_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */ - #define MXC_F_FLC_REVB_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */ - -/**@} end of group FLC_REVB_WELR0_Register */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_WELR1 FLC_REVB_WELR1 - * @brief WELR1 - * @{ - */ - #define MXC_F_FLC_REVB_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */ - #define MXC_F_FLC_REVB_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */ - -/**@} end of group FLC_REVB_WELR1_Register */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_RLR0 FLC_REVB_RLR0 - * @brief RLR0 - * @{ - */ - #define MXC_F_FLC_REVB_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */ - #define MXC_F_FLC_REVB_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */ - -/**@} end of group FLC_REVB_RLR0_Register */ - -/** - * @ingroup flc_revb_registers - * @defgroup FLC_REVB_RLR1 FLC_REVB_RLR1 - * @brief RLR1 - * @{ - */ - #define MXC_F_FLC_REVB_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */ - #define MXC_F_FLC_REVB_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */ - -/**@} end of group FLC_REVB_RLR1_Register */ - -#ifdef __cplusplus -} -#endif - -#endif /* _FLC_REVB_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c index c02c255..ba58087 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,17 +29,18 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ +#include +#include "gpio_common.h" #include "mxc_device.h" #include "mxc_assert.h" #include "gpio.h" -#include /* **** Globals **** */ -static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void*); -static void* cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT]; +static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void *); +static void *cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT]; static uint8_t initialized = 0; /* **** Functions **** */ @@ -47,34 +48,35 @@ { if (!initialized) { int i, j; - + for (i = 0; i < MXC_CFG_GPIO_INSTANCES; i++) { // Initialize call back arrays for (j = 0; j < MXC_CFG_GPIO_PINS_PORT; j++) { callback[i][j] = NULL; } } - + initialized = 1; } - + return E_NO_ERROR; } -void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t* cfg, mxc_gpio_callback_fn func, void* cbdata) +void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, + void *cbdata) { uint32_t mask; unsigned int pin; - + mask = cfg->mask; pin = 0; - + while (mask) { if (mask & 1) { callback[MXC_GPIO_GET_IDX(cfg->port)][pin] = func; cbparam[MXC_GPIO_GET_IDX(cfg->port)][pin] = cbdata; } - + pin++; mask >>= 1; } @@ -84,23 +86,23 @@ { uint32_t stat; unsigned int pin; - + MXC_ASSERT(port < MXC_CFG_GPIO_INSTANCES); - - mxc_gpio_regs_t* gpio = MXC_GPIO_GET_GPIO(port); - + + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); + stat = MXC_GPIO_GetFlags(gpio); MXC_GPIO_ClearFlags(gpio, stat); - + pin = 0; - + while (stat) { if (stat & 1) { if (callback[port][pin]) { callback[port][pin](cbparam[port][pin]); } } - + pin++; stat >>= 1; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h index 9199ae1..6c02acd 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,10 +29,14 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_ /* **** Includes **** */ #include "gpio_regs.h" +#include "gpio.h" #ifdef __cplusplus extern "C" { @@ -40,9 +44,10 @@ /* **** Function Prototypes **** */ -int MXC_GPIO_Common_Init (uint32_t portmask); -void MXC_GPIO_Common_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata); -void MXC_GPIO_Common_Handler (unsigned int port); +int MXC_GPIO_Common_Init(uint32_t portmask); +void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, + void *cbdata); +void MXC_GPIO_Common_Handler(unsigned int port); /**@} end of group gpio */ @@ -50,3 +55,4 @@ } #endif +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c index df466fe..b8bace0 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,15 +29,15 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ +#include #include "mxc_device.h" #include "mxc_assert.h" #include "gpio.h" #include "gpio_reva.h" #include "gpio_common.h" -#include #include "mxc_sys.h" /* **** Functions **** */ @@ -47,11 +47,11 @@ if (portmask & MXC_GPIO_PORT_0) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); } - + if (portmask & MXC_GPIO_PORT_1) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); } - + return MXC_GPIO_Common_Init(portmask); } @@ -60,11 +60,11 @@ if (portmask & MXC_GPIO_PORT_0) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0); } - + if (portmask & MXC_GPIO_PORT_1) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO1); } - + return E_NO_ERROR; } @@ -73,95 +73,95 @@ if (portmask & MXC_GPIO_PORT_0) { MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0); } - + if (portmask & MXC_GPIO_PORT_1) { MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO1); } - + return E_NO_ERROR; } -int MXC_GPIO_Config(const mxc_gpio_cfg_t* cfg) +int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) { int error; mxc_gpio_regs_t *gpio = cfg->port; // Configure alternate function - error = MXC_GPIO_RevA_SetAF ((mxc_gpio_reva_regs_t*)gpio, cfg->func, cfg->mask); - - if(error != E_NO_ERROR) { + error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); + + if (error != E_NO_ERROR) { return error; } // Configure the pad switch (cfg->pad) { case MXC_GPIO_PAD_NONE: - gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl0 &= ~cfg->mask; break; - + case MXC_GPIO_PAD_PULL_UP: - gpio->padctrl0 |= cfg->mask; - gpio->ps |= cfg->mask; + gpio->padctrl0 |= cfg->mask; + gpio->ps |= cfg->mask; break; - + case MXC_GPIO_PAD_PULL_DOWN: - gpio->padctrl0 |= cfg->mask; + gpio->padctrl0 |= cfg->mask; gpio->ps &= ~cfg->mask; break; - + default: return E_BAD_PARAM; } - + return E_NO_ERROR; } -uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t* port, uint32_t mask) +uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask) { - return MXC_GPIO_RevA_InGet ((mxc_gpio_reva_regs_t*) port, mask); + return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t *)port, mask); } -void MXC_GPIO_OutSet(mxc_gpio_regs_t* port, uint32_t mask) +void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask) { - MXC_GPIO_RevA_OutSet ((mxc_gpio_reva_regs_t*) port, mask); + MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t *)port, mask); } -void MXC_GPIO_OutClr(mxc_gpio_regs_t* port, uint32_t mask) +void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask) { - MXC_GPIO_RevA_OutClr ((mxc_gpio_reva_regs_t*) port, mask); + MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t *)port, mask); } -uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t* port, uint32_t mask) +uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask) { - return MXC_GPIO_RevA_OutGet ((mxc_gpio_reva_regs_t*) port, mask); + return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t *)port, mask); } -void MXC_GPIO_OutPut(mxc_gpio_regs_t* port, uint32_t mask, uint32_t val) +void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val) { - MXC_GPIO_RevA_OutPut ((mxc_gpio_reva_regs_t*) port, mask, val); + MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t *)port, mask, val); } -void MXC_GPIO_OutToggle(mxc_gpio_regs_t* port, uint32_t mask) +void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask) { - MXC_GPIO_RevA_OutToggle ((mxc_gpio_reva_regs_t*) port, mask); + MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t *)port, mask); } -int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t* cfg, mxc_gpio_int_pol_t pol) +int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol) { return MXC_GPIO_RevA_IntConfig(cfg, pol); } -void MXC_GPIO_EnableInt(mxc_gpio_regs_t* port, uint32_t mask) +void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask) { - MXC_GPIO_RevA_EnableInt ((mxc_gpio_reva_regs_t*) port, mask); + MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t *)port, mask); } -void MXC_GPIO_DisableInt(mxc_gpio_regs_t* port, uint32_t mask) +void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask) { - MXC_GPIO_RevA_DisableInt ((mxc_gpio_reva_regs_t*) port, mask); + MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t *)port, mask); } -void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t* cfg, mxc_gpio_callback_fn func, void* cbdata) +void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, void *cbdata) { MXC_GPIO_Common_RegisterCallback(cfg, func, cbdata); } @@ -171,17 +171,17 @@ MXC_GPIO_Common_Handler(port); } -void MXC_GPIO_ClearFlags(mxc_gpio_regs_t* port, uint32_t flags) +void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags) { - MXC_GPIO_RevA_ClearFlags ((mxc_gpio_reva_regs_t*) port, flags); + MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t *)port, flags); } -uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t* port) +uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port) { - return MXC_GPIO_RevA_GetFlags ((mxc_gpio_reva_regs_t*) port); + return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t *)port); } -int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask) +int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { return E_NOT_SUPPORTED; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c index 815606a..ea09bce 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,176 +29,191 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ +#include #include "mxc_device.h" #include "mxc_assert.h" #include "mxc_errors.h" #include "gpio.h" #include "gpio_reva.h" #include "gpio_common.h" -#include /* **** Functions **** */ -uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask) +uint32_t MXC_GPIO_RevA_InGet(mxc_gpio_reva_regs_t *port, uint32_t mask) { return (port->in & mask); } -void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask) +void MXC_GPIO_RevA_OutSet(mxc_gpio_reva_regs_t *port, uint32_t mask) { port->out_set = mask; } -void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask) +void MXC_GPIO_RevA_OutClr(mxc_gpio_reva_regs_t *port, uint32_t mask) { port->out_clr = mask; } -uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask) +uint32_t MXC_GPIO_RevA_OutGet(mxc_gpio_reva_regs_t *port, uint32_t mask) { return (port->out & mask); } -void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val) +void MXC_GPIO_RevA_OutPut(mxc_gpio_reva_regs_t *port, uint32_t mask, uint32_t val) { port->out = (port->out & ~mask) | (val & mask); } -void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask) +void MXC_GPIO_RevA_OutToggle(mxc_gpio_reva_regs_t *port, uint32_t mask) { port->out ^= mask; } -int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t* cfg, mxc_gpio_int_pol_t pol) +int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol) { - mxc_gpio_reva_regs_t *gpio = (mxc_gpio_reva_regs_t*) cfg->port; - + mxc_gpio_reva_regs_t *gpio = (mxc_gpio_reva_regs_t *)cfg->port; + switch (pol) { case MXC_GPIO_INT_HIGH: - gpio->intpol &= ~cfg->mask; + gpio->intpol &= ~cfg->mask; gpio->dualedge &= ~cfg->mask; - gpio->intmode &= ~cfg->mask; + gpio->intmode &= ~cfg->mask; break; - - case MXC_GPIO_INT_FALLING: /* MXC_GPIO_INT_HIGH */ - gpio->intpol &= ~cfg->mask; - gpio->dualedge &= ~cfg->mask; - gpio->intmode |= cfg->mask; - break; - - case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */ - gpio->intpol |= cfg->mask; - gpio->dualedge &= ~cfg->mask; - gpio->intmode &= ~cfg->mask; - break; - - case MXC_GPIO_INT_RISING: /* MXC_GPIO_INT_LOW */ - gpio->intpol |= cfg->mask; + + case MXC_GPIO_INT_FALLING: /* MXC_GPIO_INT_HIGH */ + gpio->intpol &= ~cfg->mask; gpio->dualedge &= ~cfg->mask; - gpio->intmode |= cfg->mask; + gpio->intmode |= cfg->mask; break; - + + case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */ + gpio->intpol |= cfg->mask; + gpio->dualedge &= ~cfg->mask; + gpio->intmode &= ~cfg->mask; + break; + + case MXC_GPIO_INT_RISING: /* MXC_GPIO_INT_LOW */ + gpio->intpol |= cfg->mask; + gpio->dualedge &= ~cfg->mask; + gpio->intmode |= cfg->mask; + break; + case MXC_GPIO_INT_BOTH: - gpio->dualedge |= cfg->mask; - gpio->intmode |= cfg->mask; + gpio->dualedge |= cfg->mask; + gpio->intmode |= cfg->mask; break; - + default: return E_BAD_PARAM; } - + return E_NO_ERROR; } -void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask) +void MXC_GPIO_RevA_EnableInt(mxc_gpio_reva_regs_t *port, uint32_t mask) { port->inten_set = mask; } -void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask) +void MXC_GPIO_RevA_DisableInt(mxc_gpio_reva_regs_t *port, uint32_t mask) { port->inten_clr = mask; } -void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags) +void MXC_GPIO_RevA_ClearFlags(mxc_gpio_reva_regs_t *port, uint32_t flags) { - port->intfl_clr = flags; + port->intfl_clr = flags; } -uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port) +uint32_t MXC_GPIO_RevA_GetFlags(mxc_gpio_reva_regs_t *port) { return port->intfl; } -int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask) +int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { // Configure the vssel switch (vssel) { case MXC_GPIO_VSSEL_VDDIO: port->vssel &= ~mask; break; - + case MXC_GPIO_VSSEL_VDDIOH: port->vssel |= mask; break; - + default: return E_BAD_PARAM; } - + return E_NO_ERROR; } -int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask) +int MXC_GPIO_RevA_SetAF(mxc_gpio_reva_regs_t *port, mxc_gpio_func_t func, uint32_t mask) { - //This is required for new devices going forward. - port->inen |= mask; - + //This is required for new devices going forward. + port->inen |= mask; + switch (func) { case MXC_GPIO_FUNC_IN: - port->outen_clr = mask; - port->en0_set = mask; - port->en1_clr = mask; - port->en2_clr = mask; - break; - - case MXC_GPIO_FUNC_OUT: - port->outen_set = mask; - port->en0_set = mask; - port->en1_clr = mask; - port->en2_clr = mask; - break; - - case MXC_GPIO_FUNC_ALT1: - port->en2_clr = mask; - port->en1_clr = mask; - port->en0_clr = mask; - break; - - case MXC_GPIO_FUNC_ALT2: - port->en2_clr = mask; - port->en1_set = mask; - port->en0_clr = mask; + port->outen_clr = mask; + port->en0_set = mask; + port->en1_clr = mask; + port->en2_clr = mask; + port->en3_clr = mask; break; - #if TARGET_NUM != 32650 + case MXC_GPIO_FUNC_OUT: + port->outen_set = mask; + port->en0_set = mask; + port->en1_clr = mask; + port->en2_clr = mask; + port->en3_clr = mask; + break; + + case MXC_GPIO_FUNC_ALT1: + port->en2_clr = mask; + port->en1_clr = mask; + port->en0_clr = mask; + port->en3_clr = mask; + break; + + case MXC_GPIO_FUNC_ALT2: + port->en2_clr = mask; + port->en1_set = mask; + port->en0_clr = mask; + port->en3_clr = mask; + break; + +#if TARGET_NUM != 32650 case MXC_GPIO_FUNC_ALT3: - port->en2_set = mask; - port->en1_clr = mask; - port->en0_clr = mask; + port->en2_set = mask; + port->en1_clr = mask; + port->en0_clr = mask; + port->en3_clr = mask; break; - + case MXC_GPIO_FUNC_ALT4: - port->en2_set = mask; - port->en1_set = mask; - port->en0_clr = mask; + port->en2_set = mask; + port->en1_set = mask; + port->en0_clr = mask; + port->en3_clr = mask; break; - #endif + +#if TARGET_NUM == 32662 + case MXC_GPIO_FUNC_ALT5: + port->en0_clr = mask; + port->en1_clr = mask; + port->en2_clr = mask; + port->en3_set = mask; + break; +#endif +#endif default: return E_BAD_PARAM; } - return E_NO_ERROR; + return E_NO_ERROR; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h index f893624..6e7ca95 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_ /* **** Includes **** */ #include "gpio_reva_regs.h" @@ -38,34 +41,34 @@ extern "C" { #endif - - /** * @brief Enumeration type for the pullup strength on a given pin. */ typedef enum { - MXC_GPIO_PS_NONE, /**< No pull-up or pull-down strength required*/ - MXC_GPIO_PS_PULL_SELECT, /**< Selct pull-up or pull-down strength*/ + MXC_GPIO_PS_NONE, /**< No pull-up or pull-down strength required*/ + MXC_GPIO_PS_PULL_SELECT, /**< Selct pull-up or pull-down strength*/ } mxc_gpio_ps_t; /* **** Function Prototypes **** */ -uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask); -void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask); -void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask); -uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask); -void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val); -void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask); -int MXC_GPIO_RevA_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); -void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask); -void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask); -void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags); -uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port); -int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask); -int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask); +uint32_t MXC_GPIO_RevA_InGet(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_OutSet(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_OutClr(mxc_gpio_reva_regs_t *port, uint32_t mask); +uint32_t MXC_GPIO_RevA_OutGet(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_OutPut(mxc_gpio_reva_regs_t *port, uint32_t mask, uint32_t val); +void MXC_GPIO_RevA_OutToggle(mxc_gpio_reva_regs_t *port, uint32_t mask); +int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); +void MXC_GPIO_RevA_EnableInt(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_DisableInt(mxc_gpio_reva_regs_t *port, uint32_t mask); +void MXC_GPIO_RevA_ClearFlags(mxc_gpio_reva_regs_t *port, uint32_t flags); +uint32_t MXC_GPIO_RevA_GetFlags(mxc_gpio_reva_regs_t *port); +int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask); +int MXC_GPIO_RevA_SetAF(mxc_gpio_reva_regs_t *port, mxc_gpio_func_t func, uint32_t mask); /**@} end of group gpio */ #ifdef __cplusplus } #endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h index 3b995fa..1433971 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h @@ -1,10 +1,10 @@ /** - * @file gpio_regs.h - * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @file gpio_reva_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GPIO_REVA Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _GPIO_REVA_REGS_H_ -#define _GPIO_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +45,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -75,616 +74,665 @@ /* **** Definitions **** */ /** - * @ingroup gpio - * @defgroup gpio_registers GPIO_Registers - * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @ingroup gpio_reva + * @defgroup gpio_reva_registers GPIO_REVA_Registers + * @brief Registers, Bit Masks and Bit Positions for the GPIO_REVA Peripheral Module. * @details Individual I/O for each GPIO */ /** - * @ingroup gpio_registers - * Structure type to access the GPIO Registers. + * @ingroup gpio_reva_registers + * Structure type to access the GPIO_REVA Registers. */ typedef struct { - __IO uint32_t en0; /**< \b 0x00: GPIO EN0 Register */ - __IO uint32_t en0_set; /**< \b 0x04: GPIO EN0_SET Register */ - __IO uint32_t en0_clr; /**< \b 0x08: GPIO EN0_CLR Register */ - __IO uint32_t outen; /**< \b 0x0C: GPIO OUTEN Register */ - __IO uint32_t outen_set; /**< \b 0x10: GPIO OUTEN_SET Register */ - __IO uint32_t outen_clr; /**< \b 0x14: GPIO OUTEN_CLR Register */ - __IO uint32_t out; /**< \b 0x18: GPIO OUT Register */ - __O uint32_t out_set; /**< \b 0x1C: GPIO OUT_SET Register */ - __O uint32_t out_clr; /**< \b 0x20: GPIO OUT_CLR Register */ - __I uint32_t in; /**< \b 0x24: GPIO IN Register */ - __IO uint32_t intmode; /**< \b 0x28: GPIO INTMODE Register */ - __IO uint32_t intpol; /**< \b 0x2C: GPIO INTPOL Register */ - __IO uint32_t inen; /**< \b 0x30: GPIO INEN Register */ - __IO uint32_t inten; /**< \b 0x34: GPIO INTEN Register */ - __IO uint32_t inten_set; /**< \b 0x38: GPIO INTEN_SET Register */ - __IO uint32_t inten_clr; /**< \b 0x3C: GPIO INTEN_CLR Register */ - __I uint32_t intfl; /**< \b 0x40: GPIO INTFL Register */ + __IO uint32_t en0; /**< \b 0x00: GPIO_REVA EN0 Register */ + __IO uint32_t en0_set; /**< \b 0x04: GPIO_REVA EN0_SET Register */ + __IO uint32_t en0_clr; /**< \b 0x08: GPIO_REVA EN0_CLR Register */ + __IO uint32_t outen; /**< \b 0x0C: GPIO_REVA OUTEN Register */ + __IO uint32_t outen_set; /**< \b 0x10: GPIO_REVA OUTEN_SET Register */ + __IO uint32_t outen_clr; /**< \b 0x14: GPIO_REVA OUTEN_CLR Register */ + __IO uint32_t out; /**< \b 0x18: GPIO_REVA OUT Register */ + __O uint32_t out_set; /**< \b 0x1C: GPIO_REVA OUT_SET Register */ + __O uint32_t out_clr; /**< \b 0x20: GPIO_REVA OUT_CLR Register */ + __I uint32_t in; /**< \b 0x24: GPIO_REVA IN Register */ + __IO uint32_t intmode; /**< \b 0x28: GPIO_REVA INTMODE Register */ + __IO uint32_t intpol; /**< \b 0x2C: GPIO_REVA INTPOL Register */ + __IO uint32_t inen; /**< \b 0x30: GPIO_REVA INEN Register */ + __IO uint32_t inten; /**< \b 0x34: GPIO_REVA INTEN Register */ + __IO uint32_t inten_set; /**< \b 0x38: GPIO_REVA INTEN_SET Register */ + __IO uint32_t inten_clr; /**< \b 0x3C: GPIO_REVA INTEN_CLR Register */ + __I uint32_t intfl; /**< \b 0x40: GPIO_REVA INTFL Register */ __R uint32_t rsv_0x44; - __IO uint32_t intfl_clr; /**< \b 0x48: GPIO INTFL_CLR Register */ - __IO uint32_t wken; /**< \b 0x4C: GPIO WKEN Register */ - __IO uint32_t wken_set; /**< \b 0x50: GPIO WKEN_SET Register */ - __IO uint32_t wken_clr; /**< \b 0x54: GPIO WKEN_CLR Register */ + __IO uint32_t intfl_clr; /**< \b 0x48: GPIO_REVA INTFL_CLR Register */ + __IO uint32_t wken; /**< \b 0x4C: GPIO_REVA WKEN Register */ + __IO uint32_t wken_set; /**< \b 0x50: GPIO_REVA WKEN_SET Register */ + __IO uint32_t wken_clr; /**< \b 0x54: GPIO_REVA WKEN_CLR Register */ __R uint32_t rsv_0x58; - __IO uint32_t dualedge; /**< \b 0x5C: GPIO DUALEDGE Register */ - __IO uint32_t padctrl0; /**< \b 0x60: GPIO PADCTRL0 Register */ - __IO uint32_t padctrl1; /**< \b 0x64: GPIO PADCTRL1 Register */ - __IO uint32_t en1; /**< \b 0x68: GPIO EN1 Register */ - __IO uint32_t en1_set; /**< \b 0x6C: GPIO EN1_SET Register */ - __IO uint32_t en1_clr; /**< \b 0x70: GPIO EN1_CLR Register */ - __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ - __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ - __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ - __R uint32_t rsv_0x80_0xa7[10]; - __IO uint32_t hysen; /**< \b 0xA8: GPIO HYSEN Register */ - __IO uint32_t srsel; /**< \b 0xAC: GPIO SRSEL Register */ - __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ - __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ - __IO uint32_t ps; /**< \b 0xB8: GPIO PS Register */ + __IO uint32_t dualedge; /**< \b 0x5C: GPIO_REVA DUALEDGE Register */ + __IO uint32_t padctrl0; /**< \b 0x60: GPIO_REVA PADCTRL0 Register */ + __IO uint32_t padctrl1; /**< \b 0x64: GPIO_REVA PADCTRL1 Register */ + __IO uint32_t en1; /**< \b 0x68: GPIO_REVA EN1 Register */ + __IO uint32_t en1_set; /**< \b 0x6C: GPIO_REVA EN1_SET Register */ + __IO uint32_t en1_clr; /**< \b 0x70: GPIO_REVA EN1_CLR Register */ + __IO uint32_t en2; /**< \b 0x74: GPIO_REVA EN2 Register */ + __IO uint32_t en2_set; /**< \b 0x78: GPIO_REVA EN2_SET Register */ + __IO uint32_t en2_clr; /**< \b 0x7C: GPIO_REVA EN2_CLR Register */ + __IO uint32_t en3; /**< \b 0x80: GPIO_REVA EN3 Register */ + __IO uint32_t en3_set; /**< \b 0x84: GPIO_REVA EN3_SET Register */ + __IO uint32_t en3_clr; /**< \b 0x88: GPIO_REVA EN3_CLR Register */ + __R uint32_t rsv_0x8c_0xa7[7]; + __IO uint32_t hysen; /**< \b 0xA8: GPIO_REVA HYSEN Register */ + __IO uint32_t srsel; /**< \b 0xAC: GPIO_REVA SRSEL Register */ + __IO uint32_t ds0; /**< \b 0xB0: GPIO_REVA DS0 Register */ + __IO uint32_t ds1; /**< \b 0xB4: GPIO_REVA DS1 Register */ + __IO uint32_t ps; /**< \b 0xB8: GPIO_REVA PS Register */ __R uint32_t rsv_0xbc; - __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ + __IO uint32_t vssel; /**< \b 0xC0: GPIO_REVA VSSEL Register */ } mxc_gpio_reva_regs_t; -/* Register offsets for module GPIO */ +/* Register offsets for module GPIO_REVA */ /** - * @ingroup gpio_registers - * @defgroup GPIO_Register_Offsets Register Offsets - * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_Register_Offsets Register Offsets + * @brief GPIO_REVA Peripheral Register Offsets from the GPIO_REVA Base Peripheral Address. * @{ */ - #define MXC_R_GPIO_REVA_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ - #define MXC_R_GPIO_REVA_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ - #define MXC_R_GPIO_REVA_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ - #define MXC_R_GPIO_REVA_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ - #define MXC_R_GPIO_REVA_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ - #define MXC_R_GPIO_REVA_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ - #define MXC_R_GPIO_REVA_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ - #define MXC_R_GPIO_REVA_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ - #define MXC_R_GPIO_REVA_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ - #define MXC_R_GPIO_REVA_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ - #define MXC_R_GPIO_REVA_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ - #define MXC_R_GPIO_REVA_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ - #define MXC_R_GPIO_REVA_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ - #define MXC_R_GPIO_REVA_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ - #define MXC_R_GPIO_REVA_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ - #define MXC_R_GPIO_REVA_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ - #define MXC_R_GPIO_REVA_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ - #define MXC_R_GPIO_REVA_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ - #define MXC_R_GPIO_REVA_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ - #define MXC_R_GPIO_REVA_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ - #define MXC_R_GPIO_REVA_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ - #define MXC_R_GPIO_REVA_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ - #define MXC_R_GPIO_REVA_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ - #define MXC_R_GPIO_REVA_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ - #define MXC_R_GPIO_REVA_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ - #define MXC_R_GPIO_REVA_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ - #define MXC_R_GPIO_REVA_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ - #define MXC_R_GPIO_REVA_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ - #define MXC_R_GPIO_REVA_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ - #define MXC_R_GPIO_REVA_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ - #define MXC_R_GPIO_REVA_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ - #define MXC_R_GPIO_REVA_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ - #define MXC_R_GPIO_REVA_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ - #define MXC_R_GPIO_REVA_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ - #define MXC_R_GPIO_REVA_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ - #define MXC_R_GPIO_REVA_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ -/**@} end of group gpio_registers */ +#define MXC_R_GPIO_REVA_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO_REVA Base Address: 0x0000 */ +#define MXC_R_GPIO_REVA_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO_REVA Base Address: 0x0004 */ +#define MXC_R_GPIO_REVA_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO_REVA Base Address: 0x0008 */ +#define MXC_R_GPIO_REVA_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO_REVA Base Address: 0x000C */ +#define MXC_R_GPIO_REVA_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO_REVA Base Address: 0x0010 */ +#define MXC_R_GPIO_REVA_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO_REVA Base Address: 0x0014 */ +#define MXC_R_GPIO_REVA_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO_REVA Base Address: 0x0018 */ +#define MXC_R_GPIO_REVA_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO_REVA Base Address: 0x001C */ +#define MXC_R_GPIO_REVA_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO_REVA Base Address: 0x0020 */ +#define MXC_R_GPIO_REVA_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO_REVA Base Address: 0x0024 */ +#define MXC_R_GPIO_REVA_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO_REVA Base Address: 0x0028 */ +#define MXC_R_GPIO_REVA_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO_REVA Base Address: 0x002C */ +#define MXC_R_GPIO_REVA_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO_REVA Base Address: 0x0030 */ +#define MXC_R_GPIO_REVA_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO_REVA Base Address: 0x0034 */ +#define MXC_R_GPIO_REVA_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO_REVA Base Address: 0x0038 */ +#define MXC_R_GPIO_REVA_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO_REVA Base Address: 0x003C */ +#define MXC_R_GPIO_REVA_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO_REVA Base Address: 0x0040 */ +#define MXC_R_GPIO_REVA_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO_REVA Base Address: 0x0048 */ +#define MXC_R_GPIO_REVA_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO_REVA Base Address: 0x004C */ +#define MXC_R_GPIO_REVA_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO_REVA Base Address: 0x0050 */ +#define MXC_R_GPIO_REVA_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO_REVA Base Address: 0x0054 */ +#define MXC_R_GPIO_REVA_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO_REVA Base Address: 0x005C */ +#define MXC_R_GPIO_REVA_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO_REVA Base Address: 0x0060 */ +#define MXC_R_GPIO_REVA_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO_REVA Base Address: 0x0064 */ +#define MXC_R_GPIO_REVA_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO_REVA Base Address: 0x0068 */ +#define MXC_R_GPIO_REVA_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO_REVA Base Address: 0x006C */ +#define MXC_R_GPIO_REVA_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO_REVA Base Address: 0x0070 */ +#define MXC_R_GPIO_REVA_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO_REVA Base Address: 0x0074 */ +#define MXC_R_GPIO_REVA_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO_REVA Base Address: 0x0078 */ +#define MXC_R_GPIO_REVA_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO_REVA Base Address: 0x007C */ +#define MXC_R_GPIO_REVA_EN3 ((uint32_t)0x00000080UL) /**< Offset from GPIO_REVA Base Address: 0x0080 */ +#define MXC_R_GPIO_REVA_EN3_SET ((uint32_t)0x00000084UL) /**< Offset from GPIO_REVA Base Address: 0x0084 */ +#define MXC_R_GPIO_REVA_EN3_CLR ((uint32_t)0x00000088UL) /**< Offset from GPIO_REVA Base Address: 0x0088 */ +#define MXC_R_GPIO_REVA_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO_REVA Base Address: 0x00A8 */ +#define MXC_R_GPIO_REVA_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO_REVA Base Address: 0x00AC */ +#define MXC_R_GPIO_REVA_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO_REVA Base Address: 0x00B0 */ +#define MXC_R_GPIO_REVA_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO_REVA Base Address: 0x00B4 */ +#define MXC_R_GPIO_REVA_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO_REVA Base Address: 0x00B8 */ +#define MXC_R_GPIO_REVA_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO_REVA Base Address: 0x00C0 */ +/**@} end of group gpio_reva_registers */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN0 GPIO_EN0 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN0 GPIO_REVA_EN0 * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one * GPIO pin on the associated port. * @{ */ - #define MXC_F_GPIO_REVA_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_REVA_EN Position */ - #define MXC_F_GPIO_REVA_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ - #define MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ - #define MXC_S_GPIO_REVA_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ - #define MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ - #define MXC_S_GPIO_REVA_EN0_GPIO_EN_GPIO (MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ +#define MXC_F_GPIO_REVA_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ +#define MXC_F_GPIO_REVA_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ +#define MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ +#define MXC_S_GPIO_REVA_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ +#define MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ +#define MXC_S_GPIO_REVA_EN0_GPIO_EN_GPIO (MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ -/**@} end of group GPIO_EN0_Register */ +/**@} end of group GPIO_REVA_EN0_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN0_SET GPIO_EN0_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN0_SET GPIO_REVA_EN0_SET * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this * register sets the bits in the same positions in GPIO_EN to 1, without affecting * other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ - #define MXC_F_GPIO_REVA_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ +#define MXC_F_GPIO_REVA_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ +#define MXC_F_GPIO_REVA_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ -/**@} end of group GPIO_EN0_SET_Register */ +/**@} end of group GPIO_REVA_EN0_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN0_CLR GPIO_REVA_EN0_CLR * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this * register clears the bits in the same positions in GPIO_EN to 0, without * affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ -/**@} end of group GPIO_EN0_CLR_Register */ +/**@} end of group GPIO_REVA_EN0_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUTEN GPIO_OUTEN + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUTEN GPIO_REVA_OUTEN * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one * GPIO pin in the associated port. * @{ */ - #define MXC_F_GPIO_REVA_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ - #define MXC_F_GPIO_REVA_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ - #define MXC_V_GPIO_REVA_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ - #define MXC_S_GPIO_REVA_OUTEN_EN_DIS (MXC_V_GPIO_REVA_OUTEN_EN_DIS << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ - #define MXC_V_GPIO_REVA_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ - #define MXC_S_GPIO_REVA_OUTEN_EN_EN (MXC_V_GPIO_REVA_OUTEN_EN_EN << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ +#define MXC_F_GPIO_REVA_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ +#define MXC_F_GPIO_REVA_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ +#define MXC_V_GPIO_REVA_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ +#define MXC_S_GPIO_REVA_OUTEN_EN_DIS (MXC_V_GPIO_REVA_OUTEN_EN_DIS << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ +#define MXC_V_GPIO_REVA_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ +#define MXC_S_GPIO_REVA_OUTEN_EN_EN (MXC_V_GPIO_REVA_OUTEN_EN_EN << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ -/**@} end of group GPIO_OUTEN_Register */ +/**@} end of group GPIO_REVA_OUTEN_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUTEN_SET GPIO_REVA_OUTEN_SET * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, * without affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ - #define MXC_F_GPIO_REVA_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ +#define MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ +#define MXC_F_GPIO_REVA_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ -/**@} end of group GPIO_OUTEN_SET_Register */ +/**@} end of group GPIO_REVA_OUTEN_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUTEN_CLR GPIO_REVA_OUTEN_CLR * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, * without affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ -/**@} end of group GPIO_OUTEN_CLR_Register */ +/**@} end of group GPIO_REVA_OUTEN_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUT GPIO_OUT + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUT GPIO_REVA_OUT * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the * associated port. This register can be written either directly, or by using the * GPIO_OUT_SET and GPIO_OUT_CLR registers. * @{ */ - #define MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ - #define MXC_F_GPIO_REVA_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ - #define MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ - #define MXC_S_GPIO_REVA_OUT_GPIO_OUT_LOW (MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ - #define MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ - #define MXC_S_GPIO_REVA_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ +#define MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ +#define MXC_F_GPIO_REVA_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ +#define MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ +#define MXC_S_GPIO_REVA_OUT_GPIO_OUT_LOW (MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ +#define MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ +#define MXC_S_GPIO_REVA_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ -/**@} end of group GPIO_OUT_Register */ +/**@} end of group GPIO_REVA_OUT_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUT_SET GPIO_OUT_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUT_SET GPIO_REVA_OUT_SET * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits * in the same positions in GPIO_OUT to 1, without affecting other bits in that * register. * @{ */ - #define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ - #define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ - #define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ - #define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ - #define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ - #define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ +#define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ +#define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ +#define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ +#define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ +#define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ +#define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ -/**@} end of group GPIO_OUT_SET_Register */ +/**@} end of group GPIO_REVA_OUT_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_OUT_CLR GPIO_REVA_OUT_CLR * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the * bits in the same positions in GPIO_OUT to 0, without affecting other bits in * that register. * @{ */ - #define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ - #define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ +#define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ +#define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ -/**@} end of group GPIO_OUT_CLR_Register */ +/**@} end of group GPIO_REVA_OUT_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_IN GPIO_IN + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_IN GPIO_REVA_IN * @brief GPIO Input Register. Read-only register to read from the logic states of the * GPIO pins on this port. * @{ */ - #define MXC_F_GPIO_REVA_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ - #define MXC_F_GPIO_REVA_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ +#define MXC_F_GPIO_REVA_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ +#define MXC_F_GPIO_REVA_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ -/**@} end of group GPIO_IN_Register */ +/**@} end of group GPIO_REVA_IN_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTMODE GPIO_INTMODE + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTMODE GPIO_REVA_INTMODE * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt * mode setting for the associated GPIO pin on this port. * @{ */ - #define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ - #define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ - #define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ - #define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ - #define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ - #define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ +#define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ +#define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ +#define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ +#define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ +#define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ +#define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ -/**@} end of group GPIO_INTMODE_Register */ +/**@} end of group GPIO_REVA_INTMODE_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTPOL GPIO_INTPOL + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTPOL GPIO_REVA_INTPOL * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the * interrupt polarity setting for one GPIO pin in the associated port. * @{ */ - #define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ - #define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ - #define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ - #define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ - #define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ - #define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ +#define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ +#define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ +#define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ +#define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ +#define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ +#define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ -/**@} end of group GPIO_INTPOL_Register */ +/**@} end of group GPIO_REVA_INTPOL_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTEN GPIO_INTEN + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTEN GPIO_REVA_INTEN * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO * interrupt enable for the associated pin on the GPIO port. * @{ */ - #define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_REVA_INTEN Position */ - #define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ - #define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ - #define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ - #define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ - #define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ +#define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */ +#define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ +#define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ +#define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ +#define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ +#define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ -/**@} end of group GPIO_INTEN_Register */ +/**@} end of group GPIO_REVA_INTEN_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTEN_SET GPIO_INTEN_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTEN_SET GPIO_REVA_INTEN_SET * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits * in that register. * @{ */ - #define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ - #define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ - #define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ - #define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ - #define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ - #define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ +#define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ +#define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ +#define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ +#define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ +#define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ +#define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ -/**@} end of group GPIO_INTEN_SET_Register */ +/**@} end of group GPIO_REVA_INTEN_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTEN_CLR GPIO_REVA_INTEN_CLR * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting * other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ - #define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ - #define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ - #define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ - #define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ - #define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ +#define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ +#define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ +#define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ +#define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ +#define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ +#define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ -/**@} end of group GPIO_INTEN_CLR_Register */ +/**@} end of group GPIO_REVA_INTEN_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTFL GPIO_INTFL + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTFL GPIO_REVA_INTFL * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending * interrupt status for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ - #define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ - #define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ - #define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ - #define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ - #define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ +#define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ +#define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ +#define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ +#define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ +#define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ +#define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ -/**@} end of group GPIO_INTFL_Register */ +/**@} end of group GPIO_REVA_INTFL_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_INTFL_CLR GPIO_REVA_INTFL_CLR * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits * in that register. * @{ */ - #define MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ -/**@} end of group GPIO_INTFL_CLR_Register */ +/**@} end of group GPIO_REVA_INTFL_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_WKEN GPIO_WKEN + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_WKEN GPIO_REVA_WKEN * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup * enable for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ - #define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ - #define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_REVA_WKEN_DIS Value */ - #define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_REVA_GPIO_WKEN_DIS << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ - #define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ - #define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ +#define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ +#define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ +#define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */ +#define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ +#define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ +#define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ -/**@} end of group GPIO_WKEN_Register */ +/**@} end of group GPIO_REVA_WKEN_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_WKEN_SET GPIO_WKEN_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_WKEN_SET GPIO_REVA_WKEN_SET * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in * that register. * @{ */ - #define MXC_F_GPIO_REVA_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ - #define MXC_F_GPIO_REVA_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ +#define MXC_F_GPIO_REVA_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ +#define MXC_F_GPIO_REVA_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ -/**@} end of group GPIO_WKEN_SET_Register */ +/**@} end of group GPIO_REVA_WKEN_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_WKEN_CLR GPIO_REVA_WKEN_CLR * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other * bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ -/**@} end of group GPIO_WKEN_CLR_Register */ +/**@} end of group GPIO_REVA_WKEN_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_DUALEDGE GPIO_DUALEDGE + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_DUALEDGE GPIO_REVA_DUALEDGE * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual * edge mode for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ - #define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ - #define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ - #define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ - #define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ - #define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ +#define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ +#define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ +#define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ +#define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ +#define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ +#define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ -/**@} end of group GPIO_DUALEDGE_Register */ +/**@} end of group GPIO_REVA_DUALEDGE_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_PADCTRL0 GPIO_REVA_PADCTRL0 * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for * the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ - #define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ - #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ - #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ - #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ - #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ - #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ - #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ +#define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ +#define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ +#define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ +#define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ +#define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ +#define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ +#define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ +#define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ -/**@} end of group GPIO_PADCTRL0_Register */ +/**@} end of group GPIO_REVA_PADCTRL0_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_PADCTRL1 GPIO_REVA_PADCTRL1 * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for * the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ - #define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ - #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ - #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ - #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ - #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ - #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ - #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ +#define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ +#define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ +#define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ +#define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ +#define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ +#define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ +#define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ +#define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ -/**@} end of group GPIO_PADCTRL1_Register */ +/**@} end of group GPIO_REVA_PADCTRL1_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN1 GPIO_EN1 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN1 GPIO_REVA_EN1 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ - #define MXC_F_GPIO_REVA_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ - #define MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ - #define MXC_S_GPIO_REVA_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ - #define MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ - #define MXC_S_GPIO_REVA_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ +#define MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ +#define MXC_F_GPIO_REVA_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ +#define MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ +#define MXC_S_GPIO_REVA_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ +#define MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ +#define MXC_S_GPIO_REVA_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ -/**@} end of group GPIO_EN1_Register */ +/**@} end of group GPIO_REVA_EN1_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN1_SET GPIO_EN1_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN1_SET GPIO_REVA_EN1_SET * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other * bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ - #define MXC_F_GPIO_REVA_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ +#define MXC_F_GPIO_REVA_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ +#define MXC_F_GPIO_REVA_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ -/**@} end of group GPIO_EN1_SET_Register */ +/**@} end of group GPIO_REVA_EN1_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN1_CLR GPIO_REVA_EN1_CLR * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other * bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ -/**@} end of group GPIO_EN1_CLR_Register */ +/**@} end of group GPIO_REVA_EN1_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN2 GPIO_EN2 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN2 GPIO_REVA_EN2 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ - #define MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ - #define MXC_F_GPIO_REVA_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ - #define MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ - #define MXC_S_GPIO_REVA_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ - #define MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ - #define MXC_S_GPIO_REVA_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ +#define MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ +#define MXC_F_GPIO_REVA_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ +#define MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ +#define MXC_S_GPIO_REVA_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ +#define MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ +#define MXC_S_GPIO_REVA_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ -/**@} end of group GPIO_EN2_Register */ +/**@} end of group GPIO_REVA_EN2_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN2_SET GPIO_EN2_SET + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN2_SET GPIO_REVA_EN2_SET * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other * bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ - #define MXC_F_GPIO_REVA_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ +#define MXC_F_GPIO_REVA_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ +#define MXC_F_GPIO_REVA_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ -/**@} end of group GPIO_EN2_SET_Register */ +/**@} end of group GPIO_REVA_EN2_SET_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN2_CLR GPIO_REVA_EN2_CLR * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this * register clears the bits in the same positions in GPIO_EN2 to 0, without * affecting other bits in that register. * @{ */ - #define MXC_F_GPIO_REVA_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ - #define MXC_F_GPIO_REVA_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ +#define MXC_F_GPIO_REVA_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ -/**@} end of group GPIO_EN2_CLR_Register */ +/**@} end of group GPIO_REVA_EN2_CLR_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_HYSEN GPIO_HYSEN + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN3 GPIO_REVA_EN3 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS 0 /**< EN3_GPIO_EN3 Position */ +#define MXC_F_GPIO_REVA_EN3_GPIO_EN3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS)) /**< EN3_GPIO_EN3 Mask */ +#define MXC_V_GPIO_REVA_EN3_GPIO_EN3_PRIMARY ((uint32_t)0x0UL) /**< EN3_GPIO_EN3_PRIMARY Value */ +#define MXC_S_GPIO_REVA_EN3_GPIO_EN3_PRIMARY (MXC_V_GPIO_REVA_EN3_GPIO_EN3_PRIMARY << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS) /**< EN3_GPIO_EN3_PRIMARY Setting */ +#define MXC_V_GPIO_REVA_EN3_GPIO_EN3_SECONDARY ((uint32_t)0x1UL) /**< EN3_GPIO_EN3_SECONDARY Value */ +#define MXC_S_GPIO_REVA_EN3_GPIO_EN3_SECONDARY (MXC_V_GPIO_REVA_EN3_GPIO_EN3_SECONDARY << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS) /**< EN3_GPIO_EN3_SECONDARY Setting */ + +/**@} end of group GPIO_REVA_EN3_Register */ + +/** + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN3_SET GPIO_REVA_EN3_SET + * @brief GPIO Alternate Function 3 Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN3 to 1, without affecting other + * bits in that register. + * @{ + */ +#define MXC_F_GPIO_REVA_EN3_SET_ALL_POS 0 /**< EN3_SET_ALL Position */ +#define MXC_F_GPIO_REVA_EN3_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_SET_ALL_POS)) /**< EN3_SET_ALL Mask */ + +/**@} end of group GPIO_REVA_EN3_SET_Register */ + +/** + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_EN3_CLR GPIO_REVA_EN3_CLR + * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN3 to 0, without + * affecting other bits in that register. + * @{ + */ +#define MXC_F_GPIO_REVA_EN3_CLR_ALL_POS 0 /**< EN3_CLR_ALL Position */ +#define MXC_F_GPIO_REVA_EN3_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_CLR_ALL_POS)) /**< EN3_CLR_ALL Mask */ + +/**@} end of group GPIO_REVA_EN3_CLR_Register */ + +/** + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_HYSEN GPIO_REVA_HYSEN * @brief GPIO Input Hysteresis Enable. * @{ */ - #define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ - #define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ +#define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ +#define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ -/**@} end of group GPIO_HYSEN_Register */ +/**@} end of group GPIO_REVA_HYSEN_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_SRSEL GPIO_SRSEL + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_SRSEL GPIO_REVA_SRSEL * @brief GPIO Slew Rate Enable Register. * @{ */ - #define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ - #define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ - #define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ - #define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ - #define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ - #define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ +#define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ +#define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ +#define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ +#define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ +#define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ +#define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ -/**@} end of group GPIO_SRSEL_Register */ +/**@} end of group GPIO_REVA_SRSEL_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_DS0 GPIO_DS0 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_DS0 GPIO_REVA_DS0 * @brief GPIO Drive Strength Register. Each bit in this register selects the drive * strength for the associated GPIO pin in this port. Refer to the Datasheet for * sink/source current of GPIO pins in each mode. * @{ */ - #define MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ - #define MXC_F_GPIO_REVA_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ - #define MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ - #define MXC_S_GPIO_REVA_DS0_GPIO_DS0_LD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ - #define MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ - #define MXC_S_GPIO_REVA_DS0_GPIO_DS0_HD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ +#define MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ +#define MXC_F_GPIO_REVA_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ +#define MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ +#define MXC_S_GPIO_REVA_DS0_GPIO_DS0_LD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ +#define MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ +#define MXC_S_GPIO_REVA_DS0_GPIO_DS0_HD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ -/**@} end of group GPIO_DS0_Register */ +/**@} end of group GPIO_REVA_DS0_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_DS1 GPIO_DS1 + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_DS1 GPIO_REVA_DS1 * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive * strength for the associated GPIO pin in this port. Refer to the Datasheet for * sink/source current of GPIO pins in each mode. * @{ */ - #define MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ - #define MXC_F_GPIO_REVA_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ +#define MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ +#define MXC_F_GPIO_REVA_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ -/**@} end of group GPIO_DS1_Register */ +/**@} end of group GPIO_REVA_DS1_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_PS GPIO_PS + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_PS GPIO_REVA_PS * @brief GPIO Pull Select Mode. * @{ */ - #define MXC_F_GPIO_REVA_PS_ALL_POS 0 /**< PS_ALL Position */ - #define MXC_F_GPIO_REVA_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PS_ALL_POS)) /**< PS_ALL Mask */ +#define MXC_F_GPIO_REVA_PS_ALL_POS 0 /**< PS_ALL Position */ +#define MXC_F_GPIO_REVA_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PS_ALL_POS)) /**< PS_ALL Mask */ -/**@} end of group GPIO_PS_Register */ +/**@} end of group GPIO_REVA_PS_Register */ /** - * @ingroup gpio_registers - * @defgroup GPIO_VSSEL GPIO_VSSEL + * @ingroup gpio_reva_registers + * @defgroup GPIO_REVA_VSSEL GPIO_REVA_VSSEL * @brief GPIO Voltage Select. * @{ */ - #define MXC_F_GPIO_REVA_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ - #define MXC_F_GPIO_REVA_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ +#define MXC_F_GPIO_REVA_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ +#define MXC_F_GPIO_REVA_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ -/**@} end of group GPIO_VSSEL_Register */ +/**@} end of group GPIO_REVA_VSSEL_Register */ #ifdef __cplusplus } #endif -#endif /* _GPIO_REVA_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c index 8d6fd6a..9393683 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include #include diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c index 572ca6f..eff2011 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include #include @@ -66,9 +66,8 @@ void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, - mxc_i2c_reva_slave_handler_t callback, - unsigned int interruptEnables, int *retVal); +void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t *int_en, int *retVal); /* ************************************************************************* */ /* Control/Configuration functions */ @@ -805,7 +804,7 @@ i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; - + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)) {} // Wait for Transaction to finish } @@ -1017,9 +1016,12 @@ int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) { - unsigned int interruptEnables = interruptCheck; int retVal = E_NO_ERROR; + uint32_t int_en[2]; + int_en[0] = interruptCheck; + int_en[1] = 0; + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } @@ -1050,8 +1052,8 @@ // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - while (interruptEnables > 0) { - interruptEnables = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, interruptEnables, &retVal); + while (int_en[0] > 0 || int_en[1] > 0) { + MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, int_en, &retVal); } return retVal; @@ -1270,9 +1272,8 @@ } } -unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, - mxc_i2c_reva_slave_handler_t callback, - unsigned int interruptEnables, int *retVal) +void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t *int_en, int *retVal) { uint32_t tFlags = i2c->intfl0; *retVal = E_NO_ERROR; @@ -1294,9 +1295,8 @@ // I2C_EVT_TRANS_COMP // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - if (!(interruptEnables & - (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH | - MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { + if (!(int_en[0] & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH | + MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { // The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed // (fires anytime a stop/start is detected out of sequence). if (tFlags & MXC_I2C_REVA_ERROR) { @@ -1310,11 +1310,12 @@ MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); - interruptEnables = 0; + int_en[0] = 0; + int_en[1] = 0; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) { + if (int_en[0] & MXC_F_I2C_REVA_INTFL0_RX_THD || int_en[1] & MXC_F_I2C_REVA_INTFL1_RX_OV) { if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) { if (callback != NULL) { callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); @@ -1332,8 +1333,8 @@ } } - if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | - MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { + if (int_en[0] & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) || + int_en[1] & MXC_F_I2C_REVA_INTFL1_TX_UN) { if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) { if (callback != NULL) { callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); @@ -1358,7 +1359,8 @@ } i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; - interruptEnables = 0; + int_en[0] = 0; + int_en[1] = 0; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } @@ -1371,7 +1373,8 @@ } i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP; - interruptEnables = 0; + int_en[0] = 0; + int_en[1] = 0; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } @@ -1383,8 +1386,10 @@ i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | - MXC_I2C_REVA_ERROR; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; + + int_en[0] = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE | MXC_I2C_REVA_ERROR; + int_en[1] = MXC_F_I2C_REVA_INTFL1_RX_OV; } if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { @@ -1394,8 +1399,9 @@ i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | - MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + int_en[0] = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | + MXC_I2C_REVA_ERROR; + int_en[1] = MXC_F_I2C_REVA_INTFL1_TX_UN; } if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) { @@ -1404,19 +1410,23 @@ callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | - MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; + + int_en[0] = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | + MXC_I2C_REVA_ERROR; + int_en[1] = MXC_F_I2C_REVA_INTFL1_TX_UN; } else { if (callback != NULL) { callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | - MXC_I2C_REVA_ERROR; + int_en[0] = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE | + MXC_I2C_REVA_ERROR; + int_en[1] = MXC_F_I2C_REVA_INTFL1_RX_OV; } } else if (tFlags & MXC_I2C_REVA_ERROR) { *retVal = E_COMM_ERR; @@ -1429,17 +1439,17 @@ MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts MXC_I2C_RevA_ClearTXFIFO(i2c); MXC_I2C_RevA_ClearRXFIFO(i2c); - interruptEnables = 0; + int_en[0] = 0; + int_en[1] = 0; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - - return interruptEnables; } void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck) { int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); int slaveRetVal; + uint32_t int_en[2]; if (i2cNum < 0) { return; @@ -1449,6 +1459,13 @@ MXC_I2C_RevA_MasterAsyncHandler(i2cNum); } else { mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum]; - i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal); + + int_en[0] = i2c->inten0; + int_en[1] = i2c->inten1; + + MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, int_en, &slaveRetVal); + + i2c->inten0 = int_en[0]; + i2c->inten1 = int_en[1]; } } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h index aa41e2c..9bcbd06 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ #define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ @@ -163,9 +163,8 @@ void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, - mxc_i2c_reva_slave_handler_t callback, - unsigned int interruptEnables, int *retVal); +void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t *int_en, int *retVal); void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck); void MXC_I2C_RevA_DMACallback(int ch, int error); diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h index 49a4341..17e75c8 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ #define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_me15.c index 0228f77..e9016bc 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_me15.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include #include @@ -44,97 +44,145 @@ #include "i2s_reva.h" #include "i2s_regs.h" -int MXC_I2S_Init(mxc_i2s_req_t* req) +int MXC_I2S_Init(mxc_i2s_req_t *req) { MXC_I2S_Shutdown(); - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERFO); - MXC_SYS_ClockEnable (MXC_SYS_PERIPH_CLOCK_I2S); - MXC_GPIO_Config (&gpio_cfg_i2s0); + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERFO); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2S); + MXC_GPIO_Config(&gpio_cfg_i2s0); - return MXC_I2S_RevA_Init ((mxc_i2s_reva_regs_t*) MXC_I2S, req); + return MXC_I2S_RevA_Init((mxc_i2s_reva_regs_t *)MXC_I2S, req); } - -int MXC_I2S_Shutdown(void) { - MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t*) MXC_I2S); - MXC_SYS_ClockDisable (MXC_SYS_PERIPH_CLOCK_I2S); +int MXC_I2S_Shutdown(void) +{ + MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t *)MXC_I2S); + + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2S); MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2S); - + return E_NO_ERROR; } -int MXC_I2S_ConfigData(mxc_i2s_req_t *req) +int MXC_I2S_ConfigData(mxc_i2s_req_t *req) { - return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t*) MXC_I2S, req); + return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t *)MXC_I2S, req); } -void MXC_I2S_TXEnable(void) +void MXC_I2S_TXEnable(void) { - MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t*) MXC_I2S); + MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); } -void MXC_I2S_TXDisable(void) +void MXC_I2S_TXDisable(void) { - MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t*) MXC_I2S); + MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); } -void MXC_I2S_RXEnable(void) +void MXC_I2S_RXEnable(void) { - MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t*) MXC_I2S); + MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t *)MXC_I2S); } -void MXC_I2S_RXDisable(void) +void MXC_I2S_RXDisable(void) { - MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t*) MXC_I2S); + MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t *)MXC_I2S); } int MXC_I2S_SetRXThreshold(uint8_t threshold) { - return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t*) MXC_I2S, threshold); + return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t *)MXC_I2S, threshold); } -int MXC_I2S_SetFrequency(mxc_i2s_ch_mode_t mode, uint16_t clkdiv) +int MXC_I2S_SetFrequency(mxc_i2s_ch_mode_t mode, uint16_t clkdiv) { - return MXC_I2S_RevA_SetFrequency((mxc_i2s_reva_regs_t*) MXC_I2S, mode, clkdiv); + return MXC_I2S_RevA_SetFrequency((mxc_i2s_reva_regs_t *)MXC_I2S, mode, clkdiv); } -void MXC_I2S_Flush(void) +int MXC_I2S_SetSampleRate(uint32_t smpl_rate, mxc_i2s_wsize_t smpl_sz) { - MXC_I2S_RevA_Flush((mxc_i2s_reva_regs_t*) MXC_I2S); + return MXC_I2S_RevA_SetSampleRate((mxc_i2s_reva_regs_t *)MXC_I2S, smpl_rate, smpl_sz, + ERFO_FREQ); +} + +int MXC_I2S_GetSampleRate(void) +{ + return MXC_I2S_RevA_GetSampleRate((mxc_i2s_reva_regs_t *)MXC_I2S, ERFO_FREQ); +} + +int MXC_I2S_CalculateClockDiv(uint32_t smpl_rate, mxc_i2s_wsize_t smpl_sz) +{ + return MXC_I2S_RevA_CalculateClockDiv((mxc_i2s_reva_regs_t *)MXC_I2S, smpl_rate, smpl_sz, + ERFO_FREQ); +} + +void MXC_I2S_Flush(void) +{ + MXC_I2S_RevA_Flush((mxc_i2s_reva_regs_t *)MXC_I2S); +} + +int MXC_I2S_FillTXFIFO(void *txData, mxc_i2s_wsize_t wordSize, int len, int smpl_cnt) +{ + return MXC_I2S_RevA_FillTXFIFO((mxc_i2s_reva_regs_t *)MXC_I2S, txData, wordSize, len, smpl_cnt); +} + +int MXC_I2S_ReadRXFIFO(void *rxData, mxc_i2s_wsize_t wordSize, int len, int smpl_cnt) +{ + return MXC_I2S_RevA_ReadRXFIFO((mxc_i2s_reva_regs_t *)MXC_I2S, rxData, wordSize, len, smpl_cnt); } void MXC_I2S_EnableInt(uint32_t flags) { - MXC_I2S_RevA_EnableInt((mxc_i2s_reva_regs_t*) MXC_I2S, flags); + MXC_I2S_RevA_EnableInt((mxc_i2s_reva_regs_t *)MXC_I2S, flags); } void MXC_I2S_DisableInt(uint32_t flags) { - MXC_I2S_RevA_DisableInt((mxc_i2s_reva_regs_t*) MXC_I2S, flags); + MXC_I2S_RevA_DisableInt((mxc_i2s_reva_regs_t *)MXC_I2S, flags); } int MXC_I2S_GetFlags(void) { - return MXC_I2S_RevA_GetFlags((mxc_i2s_reva_regs_t*) MXC_I2S); + return MXC_I2S_RevA_GetFlags((mxc_i2s_reva_regs_t *)MXC_I2S); } -void MXC_I2S_ClearFlags(uint32_t flags) +void MXC_I2S_ClearFlags(uint32_t flags) { - MXC_I2S_RevA_ClearFlags((mxc_i2s_reva_regs_t*) MXC_I2S, flags); + MXC_I2S_RevA_ClearFlags((mxc_i2s_reva_regs_t *)MXC_I2S, flags); } -void MXC_I2S_TXDMAConfig(void *src_addr, int len) +int MXC_I2S_Transaction(mxc_i2s_req_t *i2s_req) { - MXC_I2S_RevA_TXDMAConfig((mxc_i2s_reva_regs_t*) MXC_I2S, src_addr, len); + return MXC_I2S_RevA_Transaction((mxc_i2s_reva_regs_t *)MXC_I2S, i2s_req); } -void MXC_I2S_RXDMAConfig(void *dest_addr, int len) +int MXC_I2S_TransactionAsync(mxc_i2s_req_t *i2s_req) { - MXC_I2S_RevA_RXDMAConfig((mxc_i2s_reva_regs_t*) MXC_I2S, dest_addr, len); + return MXC_I2S_RevA_TransactionAsync((mxc_i2s_reva_regs_t *)MXC_I2S, i2s_req); } -void MXC_I2S_RegisterDMACallback(void(*callback)(int, int)) +int MXC_I2S_TXDMAConfig(void *src_addr, int len) +{ + return MXC_I2S_RevA_TXDMAConfig((mxc_i2s_reva_regs_t *)MXC_I2S, src_addr, len); +} + +int MXC_I2S_RXDMAConfig(void *dest_addr, int len) +{ + return MXC_I2S_RevA_RXDMAConfig((mxc_i2s_reva_regs_t *)MXC_I2S, dest_addr, len); +} + +void MXC_I2S_Handler(void) +{ + MXC_I2S_RevA_Handler((mxc_i2s_reva_regs_t *)MXC_I2S); +} + +void MXC_I2S_RegisterDMACallback(void (*callback)(int, int)) { MXC_I2S_RevA_RegisterDMACallback(callback); -} \ No newline at end of file +} + +void MXC_I2S_RegisterAsyncCallback(void (*callback)(int)) +{ + MXC_I2S_RevA_RegisterAsyncCallback(callback); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva.c index f876e0a..6035bd9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,8 +29,9 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ +#include #include #include #include @@ -44,236 +45,256 @@ #include "i2s.h" /* ***** Definitions ***** */ -#define DATALENGTH_EIGHT (8 - 1) -#define DATALENGTH_SIXTEEN (16 - 1) -#define DATALENGTH_TWENTY (20 - 1) -#define DATALENGTH_TWENTYFOUR (24 - 1) -#define DATALENGTH_THIRTYTWO (32 - 1) +#define DATALENGTH_EIGHT (8 - 1) +#define DATALENGTH_SIXTEEN (16 - 1) +#define DATALENGTH_TWENTY (20 - 1) +#define DATALENGTH_TWENTYFOUR (24 - 1) +#define DATALENGTH_THIRTYTWO (32 - 1) + +// #define USE_LEGACY_I2S_DMA_CFG + +typedef struct { + int rxCnt; + int txCnt; + bool async; +} mxc_i2s_reva_txn_t; /* ****** Globals ****** */ -static mxc_i2s_req_t* request; -static void* dma_cb = NULL; +static mxc_i2s_req_t *request; +static void (*dma_cb)(int, int) = NULL; +static void (*async_cb)(int) = NULL; + +static mxc_i2s_req_t txn_req; +static mxc_i2s_reva_txn_t txn_state; +static uint32_t txn_lock = 0; /* ****** Functions ****** */ -int MXC_I2S_RevA_Init(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t* req) +int MXC_I2S_RevA_Init(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *req) { if (((req->txData == NULL) || (req->rawData == NULL)) && (req->rxData == NULL)) { return E_NULL_PTR; } - + if (req->length == 0) { return E_BAD_PARAM; } request = req; - + if (req->stereoMode) { i2s->ctrl0ch0 |= (req->stereoMode << MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS); } - + //Set RX Threshold 2 (default) i2s->ctrl0ch0 |= (2 << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS); - + //Set justify - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_ALIGN, (req->justify) << MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS); - - if (MXC_I2S_ConfigData((mxc_i2s_req_t*) req) != E_NO_ERROR) { + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_ALIGN, + (req->justify) << MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS); + + if (MXC_I2S_ConfigData((mxc_i2s_req_t *)req) != E_NO_ERROR) { return E_BAD_PARAM; } - + MXC_I2S_SetFrequency(req->channelMode, req->clkdiv); - + return E_NO_ERROR; } int MXC_I2S_RevA_Shutdown(mxc_i2s_reva_regs_t *i2s) { MXC_I2S_DisableInt(0xFF); - + //Disable I2S TX and RX channel MXC_I2S_TXDisable(); MXC_I2S_RXDisable(); - + MXC_I2S_Flush(); - + //Clear all the registers. Not cleared on reset i2s->ctrl0ch0 = 0x00; - i2s->dmach0 = 0x00; + i2s->dmach0 = 0x00; i2s->ctrl1ch0 = 0x00; - - i2s->ctrl0ch0 |= MXC_F_I2S_REVA_CTRL0CH0_RST; //Reset channel - + + i2s->ctrl0ch0 |= MXC_F_I2S_REVA_CTRL0CH0_RST; //Reset channel + return E_NO_ERROR; } -int MXC_I2S_RevA_ConfigData(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t* req) +int MXC_I2S_RevA_ConfigData(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *req) { uint32_t dataMask; - - //Data pointers - uint8_t *txdata_8 = (uint8_t*) req->txData; - uint16_t *txdata_16 = (uint16_t*) req->txData; - uint32_t *txdata_32 = (uint32_t*) req->txData; - uint8_t *rawdata_8 = (uint8_t*) req->rawData; - uint16_t *rawdata_16 = (uint16_t*) req->rawData; - uint32_t *rawdata_32 = (uint32_t*) req->rawData; - if ((req->txData == NULL) & (req->rxData == NULL)) { + //Data pointers + uint8_t *txdata_8 = (uint8_t *)req->txData; + uint16_t *txdata_16 = (uint16_t *)req->txData; + uint32_t *txdata_32 = (uint32_t *)req->txData; + uint8_t *rawdata_8 = (uint8_t *)req->rawData; + uint16_t *rawdata_16 = (uint16_t *)req->rawData; + uint32_t *rawdata_32 = (uint32_t *)req->rawData; + + if ((req->txData == NULL) && (req->rxData == NULL)) { return E_NULL_PTR; } - + if (req->length == 0) { return E_BAD_PARAM; } - + // Clear configuration bits i2s->ctrl0ch0 &= ~MXC_F_I2S_REVA_CTRL0CH0_WSIZE; i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD; i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE; - + switch (req->sampleSize) { case MXC_I2S_SAMPLESIZE_EIGHT: if (req->wordSize == MXC_I2S_DATASIZE_WORD) { //Set word length i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS); - } - else if (req->wordSize == MXC_I2S_DATASIZE_HALFWORD) { + } else if (req->wordSize == MXC_I2S_DATASIZE_HALFWORD) { //Set word length i2s->ctrl1ch0 |= (DATALENGTH_SIXTEEN << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS); - } - else { + } else { //Set word length i2s->ctrl1ch0 |= (DATALENGTH_EIGHT << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS); } - + //Set sample length i2s->ctrl1ch0 |= (DATALENGTH_EIGHT << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS); - + //Set datasize to load in FIFO - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, (MXC_I2S_DATASIZE_BYTE) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS); - - dataMask = 0x000000ff; - + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, + (MXC_I2S_DATASIZE_BYTE) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS); + + dataMask = 0x000000ff; + if ((req->rawData != NULL) && (req->txData != NULL)) { - for (uint32_t i = 0; i < req->length ; i++) { + for (uint32_t i = 0; i < req->length; i++) { *txdata_8++ = *rawdata_8++ & dataMask; } } - + break; - + case MXC_I2S_SAMPLESIZE_SIXTEEN: if (req->wordSize == MXC_I2S_DATASIZE_WORD) { //Set word length i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS); - } - else { + } else { //Set word length i2s->ctrl1ch0 |= (DATALENGTH_SIXTEEN << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS); } - + //Set sample length i2s->ctrl1ch0 |= (DATALENGTH_SIXTEEN << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS); - + //Set datasize - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, (MXC_I2S_DATASIZE_HALFWORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS); - + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, + (MXC_I2S_DATASIZE_HALFWORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS); + dataMask = 0x0000ffff; - + if ((req->rawData != NULL) && (req->txData != NULL)) { - for (uint32_t i = 0; i < req->length ; i++) { + for (uint32_t i = 0; i < req->length; i++) { *txdata_16++ = *rawdata_16++ & dataMask; } } - + break; - + case MXC_I2S_SAMPLESIZE_TWENTY: //Set word length i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS); - + //Set sample length i2s->ctrl1ch0 |= (DATALENGTH_TWENTY << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS); - + //Set datasize - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, (MXC_I2S_DATASIZE_WORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS); - + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, + (MXC_I2S_DATASIZE_WORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS); + dataMask = 0x00fffff; - + if ((req->rawData != NULL) && (req->txData != NULL)) { - for (uint32_t i = 0; i < req->length ; i++) { + for (uint32_t i = 0; i < req->length; i++) { *txdata_32++ = (*rawdata_32++ & dataMask) << 12; } } - + break; - + case MXC_I2S_SAMPLESIZE_TWENTYFOUR: //Set word length i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS); - + //Set sample length i2s->ctrl1ch0 |= (DATALENGTH_TWENTYFOUR << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS); - + //Set datasize - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, (MXC_I2S_DATASIZE_WORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS); - + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, + (MXC_I2S_DATASIZE_WORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS); + dataMask = 0x00ffffff; - + if ((req->rawData != NULL) && (req->txData != NULL)) { - for (uint32_t i = 0; i < req->length ; i++) { + for (uint32_t i = 0; i < req->length; i++) { *txdata_32++ = (*rawdata_32++ & dataMask) << 8; } } - + break; - + case MXC_I2S_SAMPLESIZE_THIRTYTWO: //Set word length i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS); - + //Set sample length i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS); - + //Set datasize - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, (MXC_I2S_DATASIZE_WORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS); - + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, + (MXC_I2S_DATASIZE_WORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS); + dataMask = 0xffffffff; - + if ((req->rawData != NULL) && (req->txData != NULL)) { - for (uint32_t i = 0; i < req->length ; i++) { + for (uint32_t i = 0; i < req->length; i++) { *txdata_32++ = *rawdata_32++ & dataMask; } } - + break; - + default: return E_BAD_PARAM; break; } - + return E_NO_ERROR; } void MXC_I2S_RevA_TXEnable(mxc_i2s_reva_regs_t *i2s) { - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_TX_EN, 1 << MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS); + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_TX_EN, + 1 << MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS); } void MXC_I2S_RevA_TXDisable(mxc_i2s_reva_regs_t *i2s) { - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_TX_EN, 0 << MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS); + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_TX_EN, + 0 << MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS); } void MXC_I2S_RevA_RXEnable(mxc_i2s_reva_regs_t *i2s) { - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_EN, 1 << MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS); + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_EN, + 1 << MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS); } void MXC_I2S_RevA_RXDisable(mxc_i2s_reva_regs_t *i2s) { - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_EN, 0 << MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS); + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_EN, + 0 << MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS); } int MXC_I2S_RevA_SetRXThreshold(mxc_i2s_reva_regs_t *i2s, uint8_t threshold) @@ -281,30 +302,204 @@ if ((threshold == 0) || (threshold > 8)) { return E_NOT_SUPPORTED; } - + i2s->ctrl0ch0 |= (threshold << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS); - + return E_NO_ERROR; } int MXC_I2S_RevA_SetFrequency(mxc_i2s_reva_regs_t *i2s, mxc_i2s_ch_mode_t mode, uint16_t clkdiv) { i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_EN; - - MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_CH_MODE, (mode) << MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS); - - i2s->ctrl1ch0 |= ((uint32_t) clkdiv) << MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS; - + + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_CH_MODE, + (mode) << MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS); + + i2s->ctrl1ch0 |= ((uint32_t)clkdiv) << MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS; + i2s->ctrl1ch0 |= MXC_F_I2S_REVA_CTRL1CH0_EN; - + return E_NO_ERROR; } +int MXC_I2S_RevA_SetSampleRate(mxc_i2s_reva_regs_t *i2s, uint32_t smpl_rate, + mxc_i2s_wsize_t smpl_sz, uint32_t src_clk) +{ + int clk_div; + + clk_div = MXC_I2S_RevA_CalculateClockDiv(i2s, smpl_rate, smpl_sz, src_clk); + if (clk_div < 0) { + return clk_div; + } + + i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_EN; + i2s->ctrl1ch0 |= ((uint32_t)clk_div) << MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS; + i2s->ctrl1ch0 |= MXC_F_I2S_REVA_CTRL1CH0_EN; + + return MXC_I2S_RevA_GetSampleRate(i2s, src_clk); +} + +int MXC_I2S_RevA_GetSampleRate(mxc_i2s_reva_regs_t *i2s, uint32_t src_clk) +{ + uint16_t word_sz, clk_div; + uint32_t bclk; + + word_sz = (i2s->ctrl0ch0 & MXC_F_I2S_REVA_CTRL0CH0_WSIZE) >> MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS; + clk_div = (i2s->ctrl1ch0 & MXC_F_I2S_REVA_CTRL1CH0_CLKDIV) >> + MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS; // Get clock divider value + + switch (word_sz) { // Get word size + case MXC_I2S_DATASIZE_BYTE: + word_sz = 8; + break; + case MXC_I2S_DATASIZE_HALFWORD: + word_sz = 16; + break; + case MXC_I2S_DATASIZE_WORD: + default: + word_sz = 32; + break; + } + + bclk = (src_clk / (clk_div + 1)) >> + 1; // bclk_frequency = src_clk_frequency / (clk_divider + 1) / 2 + return (bclk / word_sz) >> + 1; // return sample rate (sample_rate = bclk_frequency / word_size / 2) +} + +int MXC_I2S_RevA_CalculateClockDiv(mxc_i2s_reva_regs_t *i2s, uint32_t smpl_rate, + mxc_i2s_wsize_t smpl_sz, uint32_t src_clk) +{ + uint32_t bclk; + + switch (smpl_sz) { // Get word size + case MXC_I2S_DATASIZE_BYTE: + bclk = 8; + break; + case MXC_I2S_DATASIZE_HALFWORD: + bclk = 16; + break; + case MXC_I2S_DATASIZE_WORD: + bclk = 32; + break; + default: + return E_BAD_PARAM; + } + + bclk *= smpl_rate * 4; // bclk_frequency = sample_rate * word_size * 2 + + if (bclk > src_clk) { + return E_INVALID; + } + + return (src_clk / bclk) - 1; // clk_divider = src_clk_frequency / (bclk_frequency * 2) - 1 +} + void MXC_I2S_RevA_Flush(mxc_i2s_reva_regs_t *i2s) { i2s->ctrl0ch0 |= MXC_F_I2S_REVA_CTRL0CH0_FLUSH; - - while (i2s->ctrl0ch0 & MXC_F_I2S_REVA_CTRL0CH0_FLUSH); + + while (i2s->ctrl0ch0 & MXC_F_I2S_REVA_CTRL0CH0_FLUSH) {} +} + +static uint32_t write_tx_fifo(void *tx, mxc_i2s_wsize_t wordSize, int smpl_cnt) +{ + uint32_t write_val = 0; + + if (wordSize == MXC_I2S_DATASIZE_BYTE) { + uint8_t *tx8 = (uint8_t *)tx; + for (int i = 0; i < 4; i++) { + write_val |= (tx8[smpl_cnt++] << (i * 8)); + } + } else if (wordSize == MXC_I2S_DATASIZE_HALFWORD) { + uint16_t *tx16 = (uint16_t *)tx; + for (int i = 0; i < 2; i++) { + write_val |= (tx16[smpl_cnt++] << (i * 16)); + } + } else if (wordSize == MXC_I2S_DATASIZE_WORD) { + uint32_t *tx32 = (uint32_t *)tx; + write_val = tx32[smpl_cnt]; + } + + return write_val; +} + +int MXC_I2S_RevA_FillTXFIFO(mxc_i2s_reva_regs_t *i2s, void *txData, mxc_i2s_wsize_t wordSize, + int len, int smpl_cnt) +{ + int num_smpl = 0x4 >> wordSize; // Number of samples per FIFO write + int sent = 0; // Total number of samples transmitted + uint32_t fifo_write, fifo_avail; // Value to write to I2S TX FIFO + + if (txData == NULL) { // Check for bad parameters + return E_NULL_PTR; + } else if (wordSize < MXC_I2S_DATASIZE_BYTE || wordSize > MXC_I2S_DATASIZE_WORD) { + return E_BAD_PARAM; + } else if (len == 0) { + return E_NO_ERROR; + } + + len -= len % num_smpl; // TEST + fifo_avail = + 8 - ((i2s->dmach0 & MXC_F_I2S_REVA_DMACH0_TX_LVL) >> MXC_F_I2S_REVA_DMACH0_TX_LVL_POS); + fifo_avail *= num_smpl; + while (sent < len && sent < fifo_avail) { + fifo_write = write_tx_fifo(txData, wordSize, sent + smpl_cnt); + sent += num_smpl; + + i2s->fifoch0 = fifo_write; + } + + return sent; +} + +static void read_rx_fifo(mxc_i2s_reva_regs_t *i2s, void *rxData, mxc_i2s_wsize_t wordSize, int cnt) +{ + uint32_t fifo_val = i2s->fifoch0; + + if (wordSize == MXC_I2S_DATASIZE_BYTE) { + uint8_t *rx8 = (uint8_t *)rxData; + for (int i = 0; i < 4; i++) { + rx8[cnt++] = fifo_val & 0xFF; + fifo_val = fifo_val >> 8; + } + } else if (wordSize == MXC_I2S_DATASIZE_HALFWORD) { + uint16_t *rx16 = (uint16_t *)rxData; + for (int i = 0; i < 2; i++) { + rx16[cnt++] = fifo_val & 0xFFFF; + fifo_val = fifo_val >> 16; + } + } else if (wordSize == MXC_I2S_DATASIZE_WORD) { + uint32_t *rx32 = (uint32_t *)rxData; + rx32[cnt] = fifo_val; + } +} + +int MXC_I2S_RevA_ReadRXFIFO(mxc_i2s_reva_regs_t *i2s, void *rxData, mxc_i2s_wsize_t wordSize, + int len, int smpl_cnt) +{ + int received = 0; + int num_smpl = 0x4 >> wordSize; + uint32_t fifo_avail; + + if (rxData == NULL) { // Check for bad parameters + return E_NULL_PTR; + } else if (wordSize < MXC_I2S_DATASIZE_BYTE || wordSize > MXC_I2S_DATASIZE_WORD) { + return E_BAD_PARAM; + } else if (len == 0) { + return E_NO_ERROR; + } + + len -= len % num_smpl; + fifo_avail = (i2s->dmach0 & MXC_F_I2S_REVA_DMACH0_RX_LVL) >> MXC_F_I2S_REVA_DMACH0_RX_LVL_POS; + while (received < len && fifo_avail) { + read_rx_fifo(i2s, rxData, wordSize, received + smpl_cnt); + received += num_smpl; + fifo_avail = (i2s->dmach0 & MXC_F_I2S_REVA_DMACH0_RX_LVL) >> + MXC_F_I2S_REVA_DMACH0_RX_LVL_POS; + } + + return received; } void MXC_I2S_RevA_EnableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags) @@ -327,24 +522,153 @@ i2s->intfl |= flags; } -void MXC_I2S_RevA_TXDMAConfig(mxc_i2s_reva_regs_t *i2s, void* src_addr, int len) +int MXC_I2S_RevA_Transaction(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *i2s_req) { - uint8_t channel; + int err; + + if (i2s_req->rawData != NULL && i2s_req->txData == NULL) { + return E_INVALID; + } else if (i2s_req->length == 0) { + return E_INVALID; + } else if (MXC_GetLock(&txn_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } + + i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_EN; // Disable I2S while it's being configured + + txn_req = *i2s_req; // Initialize transaction request state variables + txn_state.rxCnt = txn_req.length; + txn_state.txCnt = txn_req.length; + txn_state.async = false; + + MXC_I2S_Flush(); + + if (txn_req.rawData != NULL && + txn_req.txData != NULL) { // Set up transmit if transmit parameters valid + txn_state.txCnt = 0; + + err = MXC_I2S_ConfigData(&txn_req); + if (err) { + MXC_FreeLock(&txn_lock); + return err; + } + + err = MXC_I2S_FillTXFIFO(txn_req.txData, txn_req.wordSize, txn_req.length, + txn_state.txCnt); // Initialize TX FIFO + if (err < E_NO_ERROR) { + MXC_FreeLock(&txn_lock); + return err; + } + txn_state.txCnt = err; + + MXC_I2S_TXEnable(); // Enable I2S transmit (Do this before Fill FIFO?) + } + + if (txn_req.rxData != NULL) { // Setup I2S receive if receive parameters valid + txn_state.rxCnt = 0; + + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL, + (6 << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS)); // Set RX threshold + + MXC_I2S_RXEnable(); // Enable I2S Receive + } + + i2s->ctrl1ch0 |= MXC_F_I2S_REVA_CTRL1CH0_EN; // Enable I2S RX/TX + + while (MXC_GetLock(&txn_lock, 1) != E_NO_ERROR) { + MXC_I2S_RevA_Handler(i2s); + } + + MXC_FreeLock(&txn_lock); + + return E_NO_ERROR; +} + +int MXC_I2S_RevA_TransactionAsync(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *i2s_req) +{ + int err; + uint32_t int_en = 0; + + if (i2s_req->rawData != NULL && i2s_req->txData == NULL) { + return E_INVALID; + } else if (i2s_req->length == 0) { + return E_INVALID; + } else if (MXC_GetLock(&txn_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } + + i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_EN; // Disable I2S while it's being configured + + txn_req = *i2s_req; // Initialize transacion request state variables + txn_state.rxCnt = txn_req.length; + txn_state.txCnt = txn_req.length; + txn_state.async = true; + + MXC_I2S_Flush(); + + if (txn_req.rawData != NULL && + txn_req.txData != NULL) { // Set up transmit if transmit parameters valid + txn_state.txCnt = 0; + + err = MXC_I2S_ConfigData(&txn_req); + if (err) { + MXC_FreeLock(&txn_lock); + return err; + } + + int_en |= MXC_F_I2S_REVA_INTFL_TX_OB_CH0; // Enable TX one entry remaining interrupt + + err = MXC_I2S_FillTXFIFO(txn_req.txData, txn_req.wordSize, txn_req.length, + txn_state.txCnt); // Initialize TX FIFO + if (err < E_NO_ERROR) { + MXC_FreeLock(&txn_lock); + return err; + } + txn_state.txCnt = err; + + MXC_I2S_TXEnable(); // Enable I2S transmit (Do this before Fill FIFO?) + } + + if (txn_req.rxData != NULL) { // Setup I2S receive if receive parameters valid + txn_state.rxCnt = 0; + + int_en |= MXC_F_I2S_REVA_INTEN_RX_THD_CH0; // Enable RX threshold interrupt + MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL, + (6 << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS)); // Set RX threshold + + MXC_I2S_RXEnable(); // Enable I2S Receive + } + + MXC_I2S_DisableInt(0xF); // Configure interrupts + MXC_I2S_ClearFlags(0xF); + MXC_I2S_EnableInt(int_en); + + i2s->ctrl1ch0 |= MXC_F_I2S_REVA_CTRL1CH0_EN; // Enable I2S RX/TX + + return E_NO_ERROR; +} + +int MXC_I2S_RevA_TXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *src_addr, int len) +{ + int channel; mxc_dma_config_t config; mxc_dma_adv_config_t advConfig; mxc_dma_srcdst_t srcdst; - + MXC_DMA_Init(); - - i2s->dmach0 |= (2 << MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS); //TX DMA Threshold - + + i2s->dmach0 |= (2 << MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS); //TX DMA Threshold + channel = MXC_DMA_AcquireChannel(); - + if (channel < E_NO_ERROR) { + return channel; + } + config.reqsel = MXC_DMA_REQUEST_I2STX; - + config.ch = channel; - - switch(request->wordSize) { + + switch (request->wordSize) { case MXC_I2S_DATASIZE_WORD: config.srcwd = MXC_DMA_WIDTH_WORD; config.dstwd = MXC_DMA_WIDTH_WORD; @@ -353,26 +677,30 @@ case MXC_I2S_DATASIZE_HALFWORD: config.srcwd = MXC_DMA_WIDTH_HALFWORD; - config.dstwd = MXC_DMA_WIDTH_HALFWORD; + config.dstwd = MXC_DMA_WIDTH_WORD; advConfig.burst_size = 2; break; case MXC_I2S_DATASIZE_BYTE: config.srcwd = MXC_DMA_WIDTH_BYTE; - config.dstwd = MXC_DMA_WIDTH_BYTE; + config.dstwd = MXC_DMA_WIDTH_WORD; advConfig.burst_size = 1; break; default: config.srcwd = MXC_DMA_WIDTH_BYTE; - config.dstwd = MXC_DMA_WIDTH_BYTE; + config.dstwd = MXC_DMA_WIDTH_WORD; advConfig.burst_size = 1; break; } - + +#ifndef USE_LEGACY_I2S_DMA_CFG + advConfig.burst_size = 4; +#endif + config.srcinc_en = 1; config.dstinc_en = 0; - + advConfig.ch = channel; advConfig.prio = 0; advConfig.reqwait_en = 0; @@ -382,37 +710,42 @@ srcdst.ch = channel; srcdst.source = src_addr; srcdst.len = len; - + MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_AdvConfigChannel(advConfig); MXC_DMA_SetCallback(channel, dma_cb); - - MXC_I2S_TXEnable(); //Enable I2S TX - i2s->dmach0 |= MXC_F_I2S_REVA_DMACH0_DMA_TX_EN; //Enable I2S DMA - + + MXC_I2S_TXEnable(); //Enable I2S TX + i2s->dmach0 |= MXC_F_I2S_REVA_DMACH0_DMA_TX_EN; //Enable I2S DMA + MXC_DMA_EnableInt(channel); MXC_DMA_Start(channel); MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; + + return channel; } -void MXC_I2S_RevA_RXDMAConfig(mxc_i2s_reva_regs_t *i2s, void* dest_addr, int len) +int MXC_I2S_RevA_RXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *dest_addr, int len) { - uint8_t channel; + int channel; mxc_dma_config_t config; mxc_dma_adv_config_t advConfig; mxc_dma_srcdst_t srcdst; - + MXC_DMA_Init(); - - i2s->dmach0 |= (6 << MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS); //RX DMA Threshold - + + i2s->dmach0 |= (6 << MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS); //RX DMA Threshold + channel = MXC_DMA_AcquireChannel(); - + if (channel < E_NO_ERROR) { + return channel; + } + config.reqsel = MXC_DMA_REQUEST_I2SRX; - + config.ch = channel; - - switch(request->wordSize) { + + switch (request->wordSize) { case MXC_I2S_DATASIZE_WORD: config.srcwd = MXC_DMA_WIDTH_WORD; config.dstwd = MXC_DMA_WIDTH_WORD; @@ -420,24 +753,28 @@ break; case MXC_I2S_DATASIZE_HALFWORD: - config.srcwd = MXC_DMA_WIDTH_HALFWORD; + config.srcwd = MXC_DMA_WIDTH_WORD; config.dstwd = MXC_DMA_WIDTH_HALFWORD; advConfig.burst_size = 2; break; case MXC_I2S_DATASIZE_BYTE: - config.srcwd = MXC_DMA_WIDTH_BYTE; + config.srcwd = MXC_DMA_WIDTH_WORD; config.dstwd = MXC_DMA_WIDTH_BYTE; advConfig.burst_size = 1; break; default: - config.srcwd = MXC_DMA_WIDTH_BYTE; + config.srcwd = MXC_DMA_WIDTH_WORD; config.dstwd = MXC_DMA_WIDTH_BYTE; advConfig.burst_size = 1; break; } - + +#ifndef USE_LEGACY_I2S_DMA_CFG + advConfig.burst_size = 4; +#endif + config.srcinc_en = 0; config.dstinc_en = 1; @@ -446,24 +783,68 @@ advConfig.reqwait_en = 0; advConfig.tosel = 0; advConfig.pssel = 0; - + srcdst.ch = channel; srcdst.dest = dest_addr; srcdst.len = len; - + MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_AdvConfigChannel(advConfig); MXC_DMA_SetCallback(channel, dma_cb); - - MXC_I2S_RXEnable(); //Enable I2S RX - i2s->dmach0 |= MXC_F_I2S_REVA_DMACH0_DMA_RX_EN; //Enable I2S DMA - + + MXC_I2S_RXEnable(); //Enable I2S RX + i2s->dmach0 |= MXC_F_I2S_REVA_DMACH0_DMA_RX_EN; //Enable I2S DMA + MXC_DMA_EnableInt(channel); MXC_DMA_Start(channel); MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; + + return channel; } -void MXC_I2S_RevA_RegisterDMACallback(void(*callback)(int, int)) +void MXC_I2S_RevA_Handler(mxc_i2s_reva_regs_t *i2s) +{ + uint32_t flags = MXC_I2S_GetFlags(); + + if (txn_state.txCnt == txn_req.length && txn_state.rxCnt == txn_req.length) { + MXC_I2S_DisableInt(MXC_F_I2S_REVA_INTEN_TX_OB_CH0 | MXC_F_I2S_REVA_INTEN_RX_THD_CH0); + MXC_I2S_ClearFlags(MXC_F_I2S_REVA_INTFL_TX_OB_CH0 | MXC_F_I2S_REVA_INTFL_RX_THD_CH0); + + while (i2s->dmach0 & MXC_F_I2S_REVA_DMACH0_TX_LVL) {} + + MXC_I2S_TXDisable(); + MXC_I2S_RXDisable(); + + if (async_cb != NULL && txn_state.async) { + async_cb(E_NO_ERROR); + } + + MXC_FreeLock(&txn_lock); + } else if (txn_req.txData != NULL && (flags & MXC_F_I2S_REVA_INTFL_TX_OB_CH0)) { + MXC_I2S_ClearFlags(MXC_F_I2S_REVA_INTFL_TX_OB_CH0); + + if (txn_state.txCnt < txn_req.length) { + txn_state.txCnt += MXC_I2S_FillTXFIFO(txn_req.txData, txn_req.wordSize, + (txn_req.length - txn_state.txCnt), + txn_state.txCnt); + } + } else if (txn_req.rxData != NULL && (flags & MXC_F_I2S_REVA_INTFL_RX_THD_CH0)) { + MXC_I2S_ClearFlags(MXC_F_I2S_REVA_INTFL_RX_THD_CH0); + + if (txn_state.rxCnt < txn_req.length) { + txn_state.rxCnt += MXC_I2S_ReadRXFIFO(txn_req.rxData, txn_req.wordSize, + (txn_req.length - txn_state.rxCnt), + txn_state.rxCnt); + } + } +} + +void MXC_I2S_RevA_RegisterDMACallback(void (*callback)(int, int)) { dma_cb = callback; -} \ No newline at end of file +} + +void MXC_I2S_RevA_RegisterAsyncCallback(void (*callback)(int)) +{ + async_cb = callback; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva.h index 3660922..92c3ef1 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,25 +29,19 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2S_I2S_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2S_I2S_REVA_H_ /* **** Includes **** */ -#include -#include #include -#include "mxc_device.h" -#include "mxc_assert.h" -#include "mxc_lock.h" -#include "mxc_sys.h" -#include "mxc_delay.h" -#include "dma.h" -#include "i2s_regs.h" #include "i2s.h" #include "i2s_reva_regs.h" +/****** Definitions *****/ /* **** Functions **** */ - int MXC_I2S_RevA_Init(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *req); int MXC_I2S_RevA_Shutdown(mxc_i2s_reva_regs_t *i2s); @@ -66,8 +60,22 @@ int MXC_I2S_RevA_SetFrequency(mxc_i2s_reva_regs_t *i2s, mxc_i2s_ch_mode_t mode, uint16_t clkdiv); +int MXC_I2S_RevA_SetSampleRate(mxc_i2s_reva_regs_t *i2s, uint32_t smpl_rate, + mxc_i2s_wsize_t smpl_sz, uint32_t src_clk); + +int MXC_I2S_RevA_GetSampleRate(mxc_i2s_reva_regs_t *i2s, uint32_t src_clk); + +int MXC_I2S_RevA_CalculateClockDiv(mxc_i2s_reva_regs_t *i2s, uint32_t smpl_rate, + mxc_i2s_wsize_t smpl_sz, uint32_t src_clk); + void MXC_I2S_RevA_Flush(mxc_i2s_reva_regs_t *i2s); +int MXC_I2S_RevA_FillTXFIFO(mxc_i2s_reva_regs_t *i2s, void *txData, mxc_i2s_wsize_t wordSize, + int len, int smpl_cnt); + +int MXC_I2S_RevA_ReadRXFIFO(mxc_i2s_reva_regs_t *i2s, void *rxData, mxc_i2s_wsize_t wordSize, + int len, int smpl_cnt); + void MXC_I2S_RevA_EnableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags); void MXC_I2S_RevA_DisableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags); @@ -76,8 +84,18 @@ void MXC_I2S_RevA_ClearFlags(mxc_i2s_reva_regs_t *i2s, uint32_t flags); -void MXC_I2S_RevA_TXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *src_addr, int len); +int MXC_I2S_RevA_Transaction(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *i2s_req); -void MXC_I2S_RevA_RXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *dest_addr, int len); +int MXC_I2S_RevA_TransactionAsync(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *i2s_req); -void MXC_I2S_RevA_RegisterDMACallback(void(*callback)(int, int)); \ No newline at end of file +int MXC_I2S_RevA_TXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *src_addr, int len); + +int MXC_I2S_RevA_RXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *dest_addr, int len); + +void MXC_I2S_RevA_Handler(mxc_i2s_reva_regs_t *i2s); + +void MXC_I2S_RevA_RegisterDMACallback(void (*callback)(int, int)); + +void MXC_I2S_RevA_RegisterAsyncCallback(void (*callback)(int)); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2S_I2S_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva_regs.h index 92fa247..fb7a545 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the I2S_REVA Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _I2S_REVA_REGS_H_ -#define _I2S_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2S_I2S_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2S_I2S_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +45,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -106,13 +105,13 @@ * @brief I2S_REVA Peripheral Register Offsets from the I2S_REVA Base Peripheral Address. * @{ */ - #define MXC_R_I2S_REVA_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S_REVA Base Address: 0x0000 */ - #define MXC_R_I2S_REVA_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S_REVA Base Address: 0x0010 */ - #define MXC_R_I2S_REVA_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S_REVA Base Address: 0x0030 */ - #define MXC_R_I2S_REVA_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S_REVA Base Address: 0x0040 */ - #define MXC_R_I2S_REVA_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S_REVA Base Address: 0x0050 */ - #define MXC_R_I2S_REVA_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S_REVA Base Address: 0x0054 */ - #define MXC_R_I2S_REVA_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S_REVA Base Address: 0x0058 */ +#define MXC_R_I2S_REVA_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S_REVA Base Address: 0x0000 */ +#define MXC_R_I2S_REVA_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S_REVA Base Address: 0x0010 */ +#define MXC_R_I2S_REVA_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S_REVA Base Address: 0x0030 */ +#define MXC_R_I2S_REVA_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S_REVA Base Address: 0x0040 */ +#define MXC_R_I2S_REVA_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S_REVA Base Address: 0x0050 */ +#define MXC_R_I2S_REVA_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S_REVA Base Address: 0x0054 */ +#define MXC_R_I2S_REVA_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S_REVA Base Address: 0x0058 */ /**@} end of group i2s_reva_registers */ /** @@ -121,47 +120,47 @@ * @brief Global mode channel. * @{ */ - #define MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB_POS 19 /**< CTRL0CH0_FIFO_LSB Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB_POS 19 /**< CTRL0CH0_FIFO_LSB Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */ - #define MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */ - #define MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */ +#define MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */ +#define MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */ /**@} end of group I2S_REVA_CTRL0CH0_Register */ @@ -171,20 +170,20 @@ * @brief Local channel Setup. * @{ */ - #define MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */ - #define MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */ +#define MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */ +#define MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */ - #define MXC_F_I2S_REVA_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */ - #define MXC_F_I2S_REVA_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */ +#define MXC_F_I2S_REVA_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */ +#define MXC_F_I2S_REVA_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */ - #define MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */ - #define MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */ +#define MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */ +#define MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */ - #define MXC_F_I2S_REVA_CTRL1CH0_ADJUST_POS 15 /**< CTRL1CH0_ADJUST Position */ - #define MXC_F_I2S_REVA_CTRL1CH0_ADJUST ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL1CH0_ADJUST_POS)) /**< CTRL1CH0_ADJUST Mask */ +#define MXC_F_I2S_REVA_CTRL1CH0_ADJUST_POS 15 /**< CTRL1CH0_ADJUST Position */ +#define MXC_F_I2S_REVA_CTRL1CH0_ADJUST ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL1CH0_ADJUST_POS)) /**< CTRL1CH0_ADJUST Mask */ - #define MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */ - #define MXC_F_I2S_REVA_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */ +#define MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */ +#define MXC_F_I2S_REVA_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */ /**@} end of group I2S_REVA_CTRL1CH0_Register */ @@ -194,23 +193,23 @@ * @brief DMA Control. * @{ */ - #define MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */ - #define MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */ +#define MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */ +#define MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */ - #define MXC_F_I2S_REVA_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */ - #define MXC_F_I2S_REVA_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */ +#define MXC_F_I2S_REVA_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */ +#define MXC_F_I2S_REVA_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */ - #define MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */ - #define MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */ +#define MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */ +#define MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */ - #define MXC_F_I2S_REVA_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */ - #define MXC_F_I2S_REVA_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */ +#define MXC_F_I2S_REVA_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */ +#define MXC_F_I2S_REVA_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */ - #define MXC_F_I2S_REVA_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */ - #define MXC_F_I2S_REVA_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */ +#define MXC_F_I2S_REVA_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */ +#define MXC_F_I2S_REVA_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */ - #define MXC_F_I2S_REVA_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */ - #define MXC_F_I2S_REVA_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */ +#define MXC_F_I2S_REVA_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */ +#define MXC_F_I2S_REVA_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */ /**@} end of group I2S_REVA_DMACH0_Register */ @@ -220,8 +219,8 @@ * @brief I2S Fifo. * @{ */ - #define MXC_F_I2S_REVA_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */ - #define MXC_F_I2S_REVA_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_REVA_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */ +#define MXC_F_I2S_REVA_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */ +#define MXC_F_I2S_REVA_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_REVA_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */ /**@} end of group I2S_REVA_FIFOCH0_Register */ @@ -231,17 +230,17 @@ * @brief ISR Status. * @{ */ - #define MXC_F_I2S_REVA_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */ - #define MXC_F_I2S_REVA_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */ +#define MXC_F_I2S_REVA_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */ +#define MXC_F_I2S_REVA_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */ - #define MXC_F_I2S_REVA_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */ - #define MXC_F_I2S_REVA_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */ +#define MXC_F_I2S_REVA_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */ +#define MXC_F_I2S_REVA_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */ - #define MXC_F_I2S_REVA_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */ - #define MXC_F_I2S_REVA_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */ +#define MXC_F_I2S_REVA_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */ +#define MXC_F_I2S_REVA_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */ - #define MXC_F_I2S_REVA_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */ - #define MXC_F_I2S_REVA_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */ +#define MXC_F_I2S_REVA_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */ +#define MXC_F_I2S_REVA_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */ /**@} end of group I2S_REVA_INTFL_Register */ @@ -251,17 +250,17 @@ * @brief Interrupt Enable. * @{ */ - #define MXC_F_I2S_REVA_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */ - #define MXC_F_I2S_REVA_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */ +#define MXC_F_I2S_REVA_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */ +#define MXC_F_I2S_REVA_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */ - #define MXC_F_I2S_REVA_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */ - #define MXC_F_I2S_REVA_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */ +#define MXC_F_I2S_REVA_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */ +#define MXC_F_I2S_REVA_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */ - #define MXC_F_I2S_REVA_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */ - #define MXC_F_I2S_REVA_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */ +#define MXC_F_I2S_REVA_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */ +#define MXC_F_I2S_REVA_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */ - #define MXC_F_I2S_REVA_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */ - #define MXC_F_I2S_REVA_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */ +#define MXC_F_I2S_REVA_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */ +#define MXC_F_I2S_REVA_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */ /**@} end of group I2S_REVA_INTEN_Register */ @@ -271,8 +270,8 @@ * @brief Ext Control. * @{ */ - #define MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */ - #define MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */ +#define MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */ +#define MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */ /**@} end of group I2S_REVA_EXTSETUP_Register */ @@ -280,4 +279,5 @@ } #endif -#endif /* _I2S_REVA_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2S_I2S_REVA_REGS_H_ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_common.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_common.c index 8c3df8b..7764fa9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_common.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" @@ -38,6 +38,7 @@ #include "mxc_sys.h" #include "icc.h" #include "icc_reva.h" +#include "icc_common.h" void MXC_ICC_Com_Flush(void) { diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_common.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_common.h index fa20af8..e6b1b75 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_common.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_common.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_ /* **** Includes **** */ #include "mxc_sys.h" @@ -48,3 +51,5 @@ #ifdef __cplusplus } #endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_me15.c index 18b009b..aa60013 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_me15.c @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" @@ -44,17 +44,17 @@ int MXC_ICC_ID(mxc_icc_info_t cid) { - return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t*) MXC_ICC, cid); + return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t *)MXC_ICC, cid); } void MXC_ICC_Enable(void) { - MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t*) MXC_ICC); + MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t *)MXC_ICC); } void MXC_ICC_Disable(void) { - MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t*) MXC_ICC); + MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t *)MXC_ICC); } void MXC_ICC_Flush(void) diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva.c index 0ed9fdd..2984a8f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva.c @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -38,6 +38,7 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "icc.h" +#include "icc_reva.h" #include "icc_reva_regs.h" /* **** Definitions **** */ @@ -45,27 +46,27 @@ /* **** Globals **** */ /* **** Functions **** */ -static int MXC_ICC_Ready(mxc_icc_reva_regs_t* icc) +static int MXC_ICC_Ready(mxc_icc_reva_regs_t *icc) { return (icc->ctrl & MXC_F_ICC_REVA_CTRL_RDY); } -int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid) +int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t *icc, mxc_icc_info_t cid) { - if(icc == NULL) { + if (icc == NULL) { return E_NULL_PTR; } - switch(cid) { + switch (cid) { case ICC_INFO_RELNUM: return ((icc->info & MXC_F_ICC_REVA_INFO_RELNUM) >> MXC_F_ICC_REVA_INFO_RELNUM_POS); - + case ICC_INFO_PARTNUM: return ((icc->info & MXC_F_ICC_REVA_INFO_PARTNUM) >> MXC_F_ICC_REVA_INFO_PARTNUM_POS); - + case ICC_INFO_ID: return ((icc->info & MXC_F_ICC_REVA_INFO_ID) >> MXC_F_ICC_REVA_INFO_ID_POS); - + default: return E_BAD_PARAM; } @@ -76,15 +77,15 @@ // Invalidate cache and wait until ready icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN; icc->invalidate = 1; - - while(!(MXC_ICC_Ready(icc))); - + + while (!(MXC_ICC_Ready(icc))) {} + // Enable Cache icc->ctrl |= MXC_F_ICC_REVA_CTRL_EN; - while(!(MXC_ICC_Ready(icc))); + while (!(MXC_ICC_Ready(icc))) {} } -void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t* icc) +void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t *icc) { // Disable Cache icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva.h index 178e14c..bc3aeee 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva.h @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright (C); 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software");, + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_ /* **** Includes **** */ #include "mxc_device.h" @@ -45,6 +48,8 @@ /* **** Functions **** */ -int MXC_ICC_RevA_ID (mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid); -void MXC_ICC_RevA_Enable (mxc_icc_reva_regs_t* icc); -void MXC_ICC_RevA_Disable (mxc_icc_reva_regs_t* icc); +int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t *icc, mxc_icc_info_t cid); +void MXC_ICC_RevA_Enable(mxc_icc_reva_regs_t *icc); +void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t *icc); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h index 885047d..ac77603 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,11 +34,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ -#ifndef _ICC_REVA_REGS_H_ -#define _ICC_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +45,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -101,10 +100,10 @@ * @brief ICC_REVA Peripheral Register Offsets from the ICC_REVA Base Peripheral Address. * @{ */ - #define MXC_R_ICC_REVA_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC_REVA Base Address: 0x0000 */ - #define MXC_R_ICC_REVA_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC_REVA Base Address: 0x0004 */ - #define MXC_R_ICC_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC_REVA Base Address: 0x0100 */ - #define MXC_R_ICC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC_REVA Base Address: 0x0700 */ +#define MXC_R_ICC_REVA_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC_REVA Base Address: 0x0000 */ +#define MXC_R_ICC_REVA_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC_REVA Base Address: 0x0004 */ +#define MXC_R_ICC_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC_REVA Base Address: 0x0100 */ +#define MXC_R_ICC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC_REVA Base Address: 0x0700 */ /**@} end of group icc_reva_registers */ /** @@ -113,14 +112,14 @@ * @brief Cache ID Register. * @{ */ - #define MXC_F_ICC_REVA_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ - #define MXC_F_ICC_REVA_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ +#define MXC_F_ICC_REVA_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ +#define MXC_F_ICC_REVA_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ - #define MXC_F_ICC_REVA_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ - #define MXC_F_ICC_REVA_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ +#define MXC_F_ICC_REVA_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ +#define MXC_F_ICC_REVA_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ - #define MXC_F_ICC_REVA_INFO_ID_POS 10 /**< INFO_ID Position */ - #define MXC_F_ICC_REVA_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */ +#define MXC_F_ICC_REVA_INFO_ID_POS 10 /**< INFO_ID Position */ +#define MXC_F_ICC_REVA_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */ /**@} end of group ICC_REVA_INFO_Register */ @@ -130,11 +129,11 @@ * @brief Memory Configuration Register. * @{ */ - #define MXC_F_ICC_REVA_SZ_CCH_POS 0 /**< SZ_CCH Position */ - #define MXC_F_ICC_REVA_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */ +#define MXC_F_ICC_REVA_SZ_CCH_POS 0 /**< SZ_CCH Position */ +#define MXC_F_ICC_REVA_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */ - #define MXC_F_ICC_REVA_SZ_MEM_POS 16 /**< SZ_MEM Position */ - #define MXC_F_ICC_REVA_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */ +#define MXC_F_ICC_REVA_SZ_MEM_POS 16 /**< SZ_MEM Position */ +#define MXC_F_ICC_REVA_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */ /**@} end of group ICC_REVA_SZ_Register */ @@ -144,11 +143,11 @@ * @brief Cache Control and Status Register. * @{ */ - #define MXC_F_ICC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_ICC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_ICC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_ICC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_ICC_REVA_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ - #define MXC_F_ICC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ +#define MXC_F_ICC_REVA_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ +#define MXC_F_ICC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ /**@} end of group ICC_REVA_CTRL_Register */ @@ -156,4 +155,5 @@ } #endif -#endif /* _ICC_REVA_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/LP/lp_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/LP/lp_me15.c index 0684f7b..74b3023 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/LP/lp_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/LP/lp_me15.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include "mxc_device.h" #include "mxc_assert.h" @@ -40,13 +40,13 @@ void MXC_LP_EnterSleepMode(void) { MXC_LP_ClearWakeStatus(); - + // set block detect bit MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS; - + // Clear SLEEPDEEP bit SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - + // Go into Sleep mode and wait for an interrupt to wake the processor __WFI(); } @@ -54,13 +54,13 @@ void MXC_LP_EnterDeepSleepMode(void) { MXC_LP_ClearWakeStatus(); - + // set block detect bit MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS; - + // Set SLEEPDEEP bit SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - + // Go into Deepsleep mode and wait for an interrupt to wake the processor __WFI(); } @@ -68,14 +68,15 @@ void MXC_LP_EnterBackupMode(void) { MXC_LP_ClearWakeStatus(); - + // set block detect bit MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS; - + MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP; - - while (1); // Should never reach this line - device will jump to backup vector on exit from background mode. + + while (1) {} + // Should never reach this line - device will jump to backup vector on exit from background mode. } void MXC_LP_EnterStorageMode(void) @@ -83,20 +84,22 @@ MXC_LP_ClearWakeStatus(); /*set block detect bit */ MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS; - + MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_STORAGE_EN; MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP; - - while (1); // Should never reach this line - device will jump to backup vector on exit from background mode. + + while (1) {} + // Should never reach this line - device will jump to backup vector on exit from background mode. } void MXC_LP_EnterShutDownMode(void) { MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN; - - while (1); // Should never reach this line - device will reset on exit from shutdown mode. + + while (1) {} + // Should never reach this line - device will reset on exit from shutdown mode. } void MXC_LP_SetOVR(mxc_lp_ovr_t ovr) @@ -114,7 +117,7 @@ MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_RETREG_EN; } -int MXC_LP_RetentionRegIsEnabled(void) +int MXC_LP_RetentionRegIsEnabled(void) { return (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_RETREG_EN); } @@ -159,7 +162,7 @@ MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_LDO_DIS; } -int MXC_LP_LDOIsEnabled(void) +int MXC_LP_LDOIsEnabled(void) { return (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_LDO_DIS); } @@ -174,7 +177,7 @@ MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_FASTWK_EN; } -int MXC_LP_FastWakeupIsEnabled(void) +int MXC_LP_FastWakeupIsEnabled(void) { return (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_FASTWK_EN); } @@ -184,21 +187,20 @@ // Write 1 to clear MXC_PWRSEQ->lpwkst0 = 0xFFFFFFFF; MXC_PWRSEQ->lpwkst1 = 0xFFFFFFFF; - MXC_PWRSEQ->lppwkst = 0xFFFFFFFF; + MXC_PWRSEQ->lppwkst = 0xFFFFFFFF; } void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask) { MXC_GCR->pm |= MXC_F_GCR_PM_GPIO_WE; - + switch (1 << port) { case MXC_GPIO_PORT_0: MXC_PWRSEQ->lpwken0 |= mask; break; - + case MXC_GPIO_PORT_1: MXC_PWRSEQ->lpwken1 |= mask; - break; } } @@ -208,12 +210,11 @@ case MXC_GPIO_PORT_0: MXC_PWRSEQ->lpwken0 &= ~mask; break; - + case MXC_GPIO_PORT_1: MXC_PWRSEQ->lpwken1 &= ~mask; - break; } - + if (MXC_PWRSEQ->lpwken1 == 0 && MXC_PWRSEQ->lpwken0 == 0) { MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIO_WE; } @@ -229,37 +230,50 @@ MXC_GCR->pm &= ~MXC_F_GCR_PM_RTC_WE; } -void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t* tmr) +void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t *tmr) { MXC_ASSERT(MXC_TMR_GET_IDX(tmr) > 3); - if(tmr == MXC_TMR4) { - MXC_PWRSEQ->lppwken |= MXC_F_PWRSEQ_LPPWKEN_LPTMR0; - } - else { - MXC_PWRSEQ->lppwken |= MXC_F_PWRSEQ_LPPWKEN_LPTMR1; + if (tmr == MXC_TMR4) { + MXC_GCR->pm |= MXC_F_GCR_PM_LPTMR0_WE; + MXC_PWRSEQ->lppwken |= MXC_F_PWRSEQ_LPPWKEN_LPTMR0; + } else { + MXC_GCR->pm |= MXC_F_GCR_PM_LPTMR1_WE; + MXC_PWRSEQ->lppwken |= MXC_F_PWRSEQ_LPPWKEN_LPTMR1; } } -void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t* tmr) +void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t *tmr) { MXC_ASSERT(MXC_TMR_GET_IDX(tmr) > 3); - if(tmr == MXC_TMR4) { - MXC_PWRSEQ->lppwken &= ~MXC_F_PWRSEQ_LPPWKEN_LPTMR0; + if (tmr == MXC_TMR4) { + MXC_GCR->pm &= ~MXC_F_GCR_PM_LPTMR0_WE; + MXC_PWRSEQ->lppwken &= ~MXC_F_PWRSEQ_LPPWKEN_LPTMR0; + } else { + MXC_GCR->pm &= ~MXC_F_GCR_PM_LPTMR1_WE; + MXC_PWRSEQ->lppwken &= ~MXC_F_PWRSEQ_LPPWKEN_LPTMR1; } - else { - MXC_PWRSEQ->lppwken &= ~MXC_F_PWRSEQ_LPPWKEN_LPTMR1; - } +} + +void MXC_LP_EnableUARTWakeup(void) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_LPUART0_WE; + MXC_PWRSEQ->lppwken |= MXC_F_PWRSEQ_LPPWKEN_LPUART0; +} + +void MXC_LP_DisableUARTWakeup(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_LPUART0_WE; + MXC_PWRSEQ->lppwken &= ~MXC_F_PWRSEQ_LPPWKEN_LPUART0; } int MXC_LP_ConfigDeepSleepClocks(uint32_t mask) { - if (!(mask & (MXC_F_GCR_PM_IBRO_PD | MXC_F_GCR_PM_IPO_PD - | MXC_F_GCR_PM_ERFO_PD))) { + if (!(mask & (MXC_F_GCR_PM_IBRO_PD | MXC_F_GCR_PM_IPO_PD | MXC_F_GCR_PM_ERFO_PD))) { return E_BAD_PARAM; } - + MXC_GCR->pm |= mask; return E_NO_ERROR; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_me15.c index ddbb3f1..e16edbd 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_me15.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,120 +29,142 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ -#include "mxc_device.h" -#include "rtc_regs.h" -#include "rtc.h" -#include "mxc_sys.h" -#include "mxc_delay.h" #include "gpio_regs.h" -#include "mxc_errors.h" #include "mcr_regs.h" +#include "mxc_delay.h" +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_sys.h" +#include "rtc.h" +#include "rtc_regs.h" #include "rtc_reva.h" +#include "tmr.h" /* ***** Functions ***** */ int MXC_RTC_EnableInt(uint32_t mask) { - return MXC_RTC_RevA_EnableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask); + return MXC_RTC_RevA_EnableInt((mxc_rtc_reva_regs_t *)MXC_RTC, mask); } int MXC_RTC_DisableInt(uint32_t mask) { - return MXC_RTC_RevA_DisableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask); + return MXC_RTC_RevA_DisableInt((mxc_rtc_reva_regs_t *)MXC_RTC, mask); } int MXC_RTC_SetTimeofdayAlarm(uint32_t ras) { - return MXC_RTC_RevA_SetTimeofdayAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, ras); + return MXC_RTC_RevA_SetTimeofdayAlarm((mxc_rtc_reva_regs_t *)MXC_RTC, ras); } int MXC_RTC_SetSubsecondAlarm(uint32_t rssa) { - return MXC_RTC_RevA_SetSubsecondAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, rssa); + return MXC_RTC_RevA_SetSubsecondAlarm((mxc_rtc_reva_regs_t *)MXC_RTC, rssa); } int MXC_RTC_Start(void) { - return MXC_RTC_RevA_Start ((mxc_rtc_reva_regs_t*) MXC_RTC); + return MXC_RTC_RevA_Start((mxc_rtc_reva_regs_t *)MXC_RTC); } int MXC_RTC_Stop(void) { - return MXC_RTC_RevA_Stop ((mxc_rtc_reva_regs_t*) MXC_RTC); + return MXC_RTC_RevA_Stop((mxc_rtc_reva_regs_t *)MXC_RTC); } -int MXC_RTC_Init(uint32_t sec, uint8_t ssec) +int MXC_RTC_Init(uint32_t sec, uint16_t ssec) { // Enable clock - MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; - - return MXC_RTC_RevA_Init ((mxc_rtc_reva_regs_t*) MXC_RTC, sec, ssec); + MXC_SYS_RTCClockEnable(); + + return MXC_RTC_RevA_Init((mxc_rtc_reva_regs_t *)MXC_RTC, sec, (ssec & MXC_F_RTC_SSEC_SSEC)); } -int MXC_RTC_SquareWave (mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft) +int MXC_RTC_SquareWave(mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft) { - #if TARGET_NUM != 32675 +#if TARGET_NUM != 32675 MXC_GPIO_Config(&gpio_cfg_rtcsqw); - - return MXC_RTC_RevA_SquareWave ((mxc_rtc_reva_regs_t*) MXC_RTC, sqe, ft); - #else + + return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, sqe, ft); +#else return E_NOT_SUPPORTED; - #endif +#endif } -int MXC_RTC_SquareWaveStart (mxc_rtc_freq_sel_t fq) +int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq) { - #if TARGET_NUM != 32675 +#if TARGET_NUM != 32675 MXC_GPIO_Config(&gpio_cfg_rtcsqw); - return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t*) MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_ENABLED, fq); - #else + return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_ENABLED, + fq); +#else return E_NOT_SUPPORTED; - #endif +#endif } -int MXC_RTC_SquareWaveStop (void) +int MXC_RTC_SquareWaveStop(void) { - #if TARGET_NUM != 32675 - return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t*) MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_DISABLED, 0); - #else +#if TARGET_NUM != 32675 + return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, + MXC_RTC_REVA_SQUARE_WAVE_DISABLED, 0); +#else return E_NOT_SUPPORTED; - #endif +#endif } - int MXC_RTC_Trim(int8_t trm) { - return MXC_RTC_RevA_Trim ((mxc_rtc_reva_regs_t*) MXC_RTC, trm); + return MXC_RTC_RevA_Trim((mxc_rtc_reva_regs_t *)MXC_RTC, trm); } int MXC_RTC_GetFlags(void) { - return MXC_RTC_RevA_GetFlags(); + return MXC_RTC_RevA_GetFlags((mxc_rtc_reva_regs_t *)MXC_RTC); } int MXC_RTC_ClearFlags(int flags) { - return MXC_RTC_RevA_ClearFlags(flags); + return MXC_RTC_RevA_ClearFlags((mxc_rtc_reva_regs_t *)MXC_RTC, flags); } int MXC_RTC_GetSubSecond(void) { - return MXC_RTC_RevA_GetSubSecond(); + return MXC_RTC_RevA_GetSubSecond((mxc_rtc_reva_regs_t *)MXC_RTC); } int MXC_RTC_GetSecond(void) { - return MXC_RTC_RevA_GetSecond(); + return MXC_RTC_RevA_GetSecond((mxc_rtc_reva_regs_t *)MXC_RTC); } -int MXC_RTC_GetTime(uint32_t* sec, uint32_t* subsec) +int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec) { - return MXC_RTC_RevA_GetTime(sec, subsec); + return MXC_RTC_RevA_GetTime((mxc_rtc_reva_regs_t *)MXC_RTC, sec, subsec); } int MXC_RTC_GetBusyFlag(void) { - return MXC_RTC_RevA_GetBusyFlag(); + return MXC_RTC_RevA_GetBusyFlag((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_TrimCrystal(mxc_tmr_regs_t *tmr) +{ + if (MXC_TMR_GET_IDX(tmr) < 0 || + MXC_TMR_GET_IDX(tmr) > 4) { // Timer must support ERFO as clock source + return E_BAD_PARAM; + } + + mxc_tmr_cfg_t + tmr_cfg; // Configure timer to trigger each interrupt NUM_PERIOD number of times within a second + tmr_cfg.pres = TMR_PRES_1; + tmr_cfg.mode = TMR_MODE_CONTINUOUS; + tmr_cfg.bitMode = TMR_BIT_MODE_32; + tmr_cfg.clock = MXC_TMR_32M_CLK; + tmr_cfg.cmp_cnt = ERFO_FREQ / MXC_RTC_REVA_TRIM_PERIODS; + tmr_cfg.pol = 0; + MXC_TMR_Init(tmr, &tmr_cfg, false); + + return MXC_RTC_RevA_TrimCrystal((mxc_rtc_reva_regs_t *)MXC_RTC, tmr); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c index 8967e93..6059419 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,29 +29,30 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ +#include #include -#include "mxc_device.h" -#include "rtc.h" -#include "mxc_sys.h" -#include "mxc_delay.h" + #include "gpio_regs.h" +#include "mxc_delay.h" +#include "mxc_device.h" #include "mxc_errors.h" +#include "mxc_sys.h" +#include "rtc.h" #include "rtc_reva.h" +#include "tmr.h" #if TARGET_NUM == 32650 - #include "pwrseq_regs.h" +#include "pwrseq_regs.h" #endif void MXC_RTC_Wait_BusyToClear(void) { - while (MXC_RTC_REVA_IS_BUSY) { - - } + while (MXC_RTC_REVA_IS_BUSY) {} } -int MXC_RTC_RevA_GetBusyFlag (void) +int MXC_RTC_RevA_GetBusyFlag(mxc_rtc_reva_regs_t *rtc) { if (MXC_RTC_REVA_IS_BUSY) { return E_BUSY; @@ -59,295 +60,364 @@ return E_SUCCESS; } -int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask) +int MXC_RTC_RevA_EnableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask) { - mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY); - + mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY); + if (!mask) { /* No bits set? Wasn't something we can enable. */ return E_BAD_PARAM; } - + MXC_RTC_Wait_BusyToClear(); - + rtc->ctrl |= mask; - - /* If TOD and SSEC interrupt enable, check busy after CTRL register write*/ + + /* If TOD and SSEC interrupt enable, check busy after CTRL register write*/ mask &= ~MXC_RTC_INT_EN_READY; if (mask) { MXC_RTC_Wait_BusyToClear(); - } + } return E_SUCCESS; } -int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask) +int MXC_RTC_RevA_DisableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask) { - mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY); - + mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY); + if (!mask) { /* No bits set? Wasn't something we can enable. */ return E_BAD_PARAM; } - + MXC_RTC_Wait_BusyToClear(); - + rtc->ctrl &= ~mask; - - /* If TOD and SSEC interrupt enable, check busy after CTRL register write*/ + + /* If TOD and SSEC interrupt enable, check busy after CTRL register write*/ mask &= ~MXC_RTC_INT_EN_READY; if (mask) { MXC_RTC_Wait_BusyToClear(); - } + } return E_SUCCESS; } -int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras) +int MXC_RTC_RevA_SetTimeofdayAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t ras) { // ras can only be written if BUSY = 0 & (RTCE = 0 or ADE = 0); - if (MXC_RTC_RevA_GetBusyFlag()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - + rtc->toda = (ras << MXC_F_RTC_REVA_TODA_TOD_ALARM_POS) & MXC_F_RTC_REVA_TODA_TOD_ALARM; - + return E_SUCCESS; } -int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa) +int MXC_RTC_RevA_SetSubsecondAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t rssa) { // ras can only be written if BUSY = 0 & (RTCE = 0 or ASE = 0); - if (MXC_RTC_RevA_GetBusyFlag()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - + rtc->sseca = (rssa << MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS) & MXC_F_RTC_REVA_SSECA_SSEC_ALARM; - + return E_SUCCESS; } -int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc) +int MXC_RTC_RevA_Start(mxc_rtc_reva_regs_t *rtc) { - if (MXC_RTC_RevA_GetBusyFlag()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers - + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers + MXC_RTC_Wait_BusyToClear(); - + // Can only write if WE=1 and BUSY=0 - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 1 - + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 1 + MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... - + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... + return E_SUCCESS; } -int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc) +int MXC_RTC_RevA_Stop(mxc_rtc_reva_regs_t *rtc) { - if (MXC_RTC_RevA_GetBusyFlag()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers - + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers + MXC_RTC_Wait_BusyToClear(); - + // Can only write if WE=1 and BUSY=0 - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 0 - + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 0 + MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... - + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... + return E_SUCCESS; } -int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec) +int MXC_RTC_RevA_Init(mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint32_t ssec) { - if (MXC_RTC_RevA_GetBusyFlag()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - - rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN; // Allow Writes - + + rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN; // Allow Writes + MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT; // Start with a Clean Register - + + rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT; // Start with a Clean Register + MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Set Write Enable, allow writing to reg. - + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Set Write Enable, allow writing to reg. + MXC_RTC_Wait_BusyToClear(); - + rtc->ssec = ssec; - + MXC_RTC_Wait_BusyToClear(); - + rtc->sec = sec; - + MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... - + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... + return E_SUCCESS; } -int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft) +int MXC_RTC_RevA_SquareWave(mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, + mxc_rtc_freq_sel_t ft) { - if (MXC_RTC_RevA_GetBusyFlag()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers - + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers + MXC_RTC_Wait_BusyToClear(); - + if (sqe == MXC_RTC_REVA_SQUARE_WAVE_ENABLED) { - if (ft == MXC_RTC_F_32KHZ) { // if 32KHz output is selected... - rtc->oscctrl |= MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Enable 32KHz wave - + if (ft == MXC_RTC_F_32KHZ) { // if 32KHz output is selected... + rtc->oscctrl |= MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Enable 32KHz wave + MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_SQW_EN; // Enable output on the pin + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_SQW_EN; // Enable output on the pin + } else { // if 1Hz, 512Hz, 4KHz output is selected + rtc->oscctrl &= + ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_SEL; + + MXC_RTC_Wait_BusyToClear(); + + rtc->ctrl |= (MXC_F_RTC_REVA_CTRL_SQW_EN | ft); // Enable Sq. wave, } - else { // if 1Hz, 512Hz, 4KHz output is selected - - rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled - - MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl &= ~ MXC_F_RTC_REVA_CTRL_SQW_SEL; - - MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl |= (MXC_F_RTC_REVA_CTRL_SQW_EN | ft); // Enable Sq. wave, - } - + MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // Enable Real Time Clock - } - else { // Turn off the square wave output on the pin - - rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled - + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // Enable Real Time Clock + } else { // Turn off the square wave output on the pin + rtc->oscctrl &= + ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled + MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_EN; // No sq. wave output + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_EN; // No sq. wave output } - + MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register - + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register + return E_SUCCESS; } -int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trim) +int MXC_RTC_RevA_Trim(mxc_rtc_reva_regs_t *rtc, int8_t trim) { - if (MXC_RTC_RevA_GetBusyFlag()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; - + MXC_RTC_Wait_BusyToClear(); - - MXC_SETFIELD (rtc->trim, MXC_F_RTC_REVA_TRIM_TRIM, trim << MXC_F_RTC_REVA_TRIM_TRIM_POS); - + + MXC_SETFIELD(rtc->trim, MXC_F_RTC_REVA_TRIM_TRIM, trim << MXC_F_RTC_REVA_TRIM_TRIM_POS); + MXC_RTC_Wait_BusyToClear(); - - rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register - + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register + return E_SUCCESS; } -int MXC_RTC_RevA_GetFlags(void) +int MXC_RTC_RevA_GetFlags(mxc_rtc_reva_regs_t *rtc) { - return MXC_RTC->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY); + return rtc->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY); } -int MXC_RTC_RevA_ClearFlags(int flags) -{ - MXC_RTC->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY)); - +int MXC_RTC_RevA_ClearFlags(mxc_rtc_reva_regs_t *rtc, int flags) +{ + rtc->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY)); + return E_SUCCESS; } -int MXC_RTC_RevA_GetSubSecond(void) +int MXC_RTC_RevA_GetSubSecond(mxc_rtc_reva_regs_t *rtc) { - if (MXC_RTC_RevA_GetBusyFlag()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } #if TARGET_NUM == 32650 int ssec; - if(ChipRevision > 0xA1){ - ssec = ((MXC_PWRSEQ->ctrl >> 12)& 0xF00) | (MXC_RTC->ssec & 0xFF); - }else{ - ssec = MXC_RTC->ssec; + if (ChipRevision > 0xA1) { + ssec = ((MXC_PWRSEQ->ctrl >> 12) & 0xF00) | (rtc->ssec & 0xFF); + } else { + ssec = rtc->ssec; } - return ssec; + return ssec; #else - return MXC_RTC->ssec; + return rtc->ssec; #endif } -int MXC_RTC_RevA_GetSecond(void) +int MXC_RTC_RevA_GetSecond(mxc_rtc_reva_regs_t *rtc) { - if (MXC_RTC_RevA_GetBusyFlag()) { + if (MXC_RTC_RevA_GetBusyFlag(rtc)) { return E_BUSY; } - - return MXC_RTC->sec; + + return rtc->sec; } -int MXC_RTC_RevA_GetTime(uint32_t* sec, uint32_t* subsec) +int MXC_RTC_RevA_GetTime(mxc_rtc_reva_regs_t *rtc, uint32_t *sec, uint32_t *subsec) { uint32_t temp_sec = 0; - + if (sec == NULL || subsec == NULL) { return E_NULL_PTR; } - + do { // Check if an update is about to happen. - if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { + if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { return E_BUSY; } - - // Read the seconds count. - temp_sec = MXC_RTC_RevA_GetSecond(); - if ((int)temp_sec == E_BUSY) { - return E_BUSY; - } - - // Check if an update is about to happen. - if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { - return E_BUSY; - } - - // Read the sub-seconds count. - *subsec = MXC_RTC_RevA_GetSubSecond(); - - // Check if an update is about to happen. - if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { - return E_BUSY; - } - // Read the seconds count. - *sec = MXC_RTC_RevA_GetSecond(); - + temp_sec = MXC_RTC_RevA_GetSecond(rtc); + + if (temp_sec == E_BUSY) { + return E_BUSY; + } + + // Check if an update is about to happen. + if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { + return E_BUSY; + } + + // Read the sub-seconds count. + *subsec = MXC_RTC_RevA_GetSubSecond(rtc); + + // Check if an update is about to happen. + if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { + return E_BUSY; + } + + // Read the seconds count. + *sec = MXC_RTC_RevA_GetSecond(rtc); + // Repeat until a steady state is reached. - } - while (temp_sec != *sec); - + } while (temp_sec != *sec); + return E_NO_ERROR; } + +int MXC_RTC_RevA_TrimCrystal(mxc_rtc_reva_regs_t *rtc, mxc_tmr_regs_t *tmr) +{ + int err, ppm = 0; + uint32_t sec = 0, ssec = 0, ctrl = 0; + uint32_t sec_sample[MXC_RTC_REVA_TRIM_PERIODS + 1] = { 0 }; + uint32_t ssec_sample[MXC_RTC_REVA_TRIM_PERIODS + 1] = { 0 }; + bool rtc_en = true; + + if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_EN)) { // If RTC not enable, initialize it + rtc_en = false; + while ((sec = MXC_RTC_RevA_GetSecond(rtc)) < 0) {} + // Save state + while ((ssec = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {} + while (rtc->ctrl & MXC_F_RTC_CTRL_BUSY) {} + ctrl = rtc->ctrl; + + if ((err = MXC_RTC_Init(0, 0)) != E_NO_ERROR) { + return err; + } + MXC_RTC_Start(); + } + + MXC_TMR_ClearFlags(tmr); + MXC_TMR_Start(tmr); // Sample the RTC ticks in MXC_RTC_REVA_TRIM_PERIODS number of periods + while ((sec_sample[0] = MXC_RTC_RevA_GetSecond(rtc)) < 0) {} + while ((ssec_sample[0] = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {} + + for (int i = 1; i < (MXC_RTC_REVA_TRIM_PERIODS + 1); i++) { + while (!(MXC_TMR_GetFlags(tmr) & MXC_RTC_TRIM_TMR_IRQ)) {} + // Wait for time trim period to elapse + + while ((sec_sample[i] = MXC_RTC_RevA_GetSecond(rtc)) < 0) {} + // Take time sample + while ((ssec_sample[i] = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {} + + MXC_TMR_ClearFlags(tmr); + } + + MXC_TMR_Stop(tmr); // Shutdown timer + MXC_TMR_Shutdown(tmr); + + if (!rtc_en) { // If RTC wasn't enabled entering the function, restore state + MXC_RTC_Stop(); + + while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {} + MXC_SETFIELD(rtc->ssec, MXC_F_RTC_REVA_SSEC_SSEC, (ssec << MXC_F_RTC_REVA_SSEC_SSEC_POS)); + while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {} + MXC_SETFIELD(rtc->sec, MXC_F_RTC_REVA_SEC_SEC, (sec << MXC_F_RTC_REVA_SEC_SEC_POS)); + while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {} + rtc->ctrl = ctrl; + } + + for (int i = 0; i < MXC_RTC_REVA_TRIM_PERIODS; + i++) { // Get total error in RTC ticks over MXC_RTC_REVA_TRIM_PERIODS number of sample periods + if (sec_sample[i] < sec_sample[i + 1]) { + ppm += MXC_RTC_REVA_TICKS_PER_PERIOD - + ((MXC_RTC_MAX_SSEC - ssec_sample[i]) + ssec_sample[i + 1]); + } else { + ppm += MXC_RTC_REVA_TICKS_PER_PERIOD - (ssec_sample[i + 1] - ssec_sample[i]); + } + } + + ppm /= MXC_RTC_REVA_TRIM_PERIODS; + ppm = PPM(ppm); // Convert total error to PPM and set trim + if (ppm < -128 || ppm > 127) { + return E_OVERFLOW; + } + + return MXC_RTC_RevA_Trim(rtc, (int8_t)ppm); // Set Trim +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h index ea68a71..b6f9325 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,39 +29,51 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_ + +#include "gpio.h" +#include "mxc_delay.h" #include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_sys.h" #include "rtc_reva_regs.h" #include "rtc.h" -#include "mxc_sys.h" -#include "mxc_delay.h" -#include "gpio.h" -#include "mxc_errors.h" +#include "tmr.h" typedef enum { MXC_RTC_REVA_SQUARE_WAVE_DISABLED, ///< Sq. wave output disabled - MXC_RTC_REVA_SQUARE_WAVE_ENABLED, ///< Sq. wave output enabled + MXC_RTC_REVA_SQUARE_WAVE_ENABLED, ///< Sq. wave output enabled } mxc_rtc_reva_sqwave_en_t; #define MXC_RTC_REVA_CTRL_RESET_DEFAULT (0x0000UL) -#define MXC_RTC_REVA_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) -#define MXC_RTC_REVA_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RTCE) +#define MXC_RTC_REVA_IS_BUSY (MXC_F_RTC_REVA_CTRL_BUSY & MXC_RTC->ctrl) +#define MXC_RTC_REVA_IS_ENABLED (MXC_F_RTC_REVA_CTRL_RTCE & MXC_RTC->ctrl) -#define MXC_BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit +#define MXC_RTC_REVA_TRIM_PERIODS 5 +#define MXC_RTC_REVA_TICKS_PER_PERIOD (MXC_RTC_MAX_SSEC / MXC_RTC_REVA_TRIM_PERIODS) +#define PPM(ppm) ((ppm * 1000000) / 4096) -int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec); -int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask); -int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask); -int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras); -int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa); -int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc); -int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc); -int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft); -int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trm); -int MXC_RTC_RevA_GetFlags (void); -int MXC_RTC_RevA_ClearFlags (int flags); -int MXC_RTC_RevA_GetSubSecond (void); -int MXC_RTC_RevA_GetSecond (void); -int MXC_RTC_RevA_GetTime (uint32_t* sec, uint32_t* subsec); -int MXC_RTC_RevA_GetBusyFlag (void); +#define MXC_BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit + +int MXC_RTC_RevA_Init(mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint32_t ssec); +int MXC_RTC_RevA_EnableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask); +int MXC_RTC_RevA_DisableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask); +int MXC_RTC_RevA_SetTimeofdayAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t ras); +int MXC_RTC_RevA_SetSubsecondAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t rssa); +int MXC_RTC_RevA_Start(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_Stop(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_SquareWave(mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, + mxc_rtc_freq_sel_t ft); +int MXC_RTC_RevA_Trim(mxc_rtc_reva_regs_t *rtc, int8_t trm); +int MXC_RTC_RevA_GetFlags(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_ClearFlags(mxc_rtc_reva_regs_t *rtc, int flags); +int MXC_RTC_RevA_GetSubSecond(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_GetSecond(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_GetTime(mxc_rtc_reva_regs_t *rtc, uint32_t *sec, uint32_t *subsec); +int MXC_RTC_RevA_GetBusyFlag(mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_TrimCrystal(mxc_rtc_reva_regs_t *rtc, mxc_tmr_regs_t *tmr); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h index f6f752f..f71a8c5 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _RTC_REVA_REGS_H_ #define _RTC_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c index c2e0a1e..b0909b2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,10 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ -#ifdef __CC_ARM //Keil -#pragma diag_suppress 550 // variable xxx was set but never used. -#endif + ******************************************************************************/ #include #include @@ -45,352 +42,352 @@ #include "spi_reva.h" #include "dma.h" - /* **** Functions **** */ -int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, +int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel) { + int spi_num; + + spi_num = MXC_SPI_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); if (numSlaves > MXC_SPI_SS_INSTANCES) { return E_BAD_PARAM; } - + // Check if frequency is too high if (hz > PeripheralClock) { return E_BAD_PARAM; } - + // Configure GPIO for spi if (spi == MXC_SPI0) { - #if TARGET_NUM != 32675 +#if TARGET_NUM != 32675 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI0); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI0); MXC_GPIO_Config(&gpio_cfg_spi0); - #endif - } - else if (spi == MXC_SPI1) { +#endif + } else if (spi == MXC_SPI1) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI1); MXC_GPIO_Config(&gpio_cfg_spi1); - } - else if (spi == MXC_SPI2) { + } else if (spi == MXC_SPI2) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI2); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI2); MXC_GPIO_Config(&gpio_cfg_spi2); - } - else { + } else { return E_NO_DEVICE; } - - return MXC_SPI_RevA_Init ((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz, drv_ssel); + + return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t *)spi, masterMode, quadModeUsed, numSlaves, + ssPolarity, hz, drv_ssel); } -int MXC_SPI_Shutdown(mxc_spi_regs_t* spi) -{ - MXC_SPI_RevA_Shutdown ((mxc_spi_reva_regs_t*) spi); - +int MXC_SPI_Shutdown(mxc_spi_regs_t *spi) +{ + int spi_num; + spi_num = MXC_SPI_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); + + MXC_SPI_RevA_Shutdown((mxc_spi_reva_regs_t *)spi); + if (spi == MXC_SPI0) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI0); - } - else if (spi == MXC_SPI1) { + } else if (spi == MXC_SPI1) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); - } - else if (spi == MXC_SPI2) { + } else if (spi == MXC_SPI2) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI2); - } - else { + } else { return E_INVALID; } - + return E_NO_ERROR; } -int MXC_SPI_ReadyForSleep(mxc_spi_regs_t* spi) +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_ReadyForSleep ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_ReadyForSleep((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi) +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi) { - if(MXC_SPI_GET_IDX(spi) != -1) { + if (MXC_SPI_GET_IDX(spi) != -1) { return PeripheralClock; - } - else { + } else { return E_BAD_PARAM; } return E_NO_ERROR; } -int MXC_SPI_SetFrequency(mxc_spi_regs_t* spi, unsigned int hz) +int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz) { - return MXC_SPI_RevA_SetFrequency ((mxc_spi_reva_regs_t*) spi, hz); + return MXC_SPI_RevA_SetFrequency((mxc_spi_reva_regs_t *)spi, hz); } -unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetFrequency ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetFrequency((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetDataSize(mxc_spi_regs_t* spi, int dataSize) +int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize) { - return MXC_SPI_RevA_SetDataSize ((mxc_spi_reva_regs_t*) spi, dataSize); + return MXC_SPI_RevA_SetDataSize((mxc_spi_reva_regs_t *)spi, dataSize); } -int MXC_SPI_GetDataSize(mxc_spi_regs_t* spi) +int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetDataSize ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetDataSize((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetSlave(mxc_spi_regs_t* spi, int ssIdx) +int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx) { - return MXC_SPI_RevA_SetSlave ((mxc_spi_reva_regs_t*) spi, ssIdx); + return MXC_SPI_RevA_SetSlave((mxc_spi_reva_regs_t *)spi, ssIdx); } -int MXC_SPI_GetSlave(mxc_spi_regs_t* spi) +int MXC_SPI_GetSlave(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetSlave ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetSlave((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetWidth(mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth) +int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth) { - return MXC_SPI_RevA_SetWidth ((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_width_t) spiWidth); + return MXC_SPI_RevA_SetWidth((mxc_spi_reva_regs_t *)spi, (mxc_spi_reva_width_t)spiWidth); } -mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t* spi) +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi) { - return ((mxc_spi_width_t) MXC_SPI_RevA_GetWidth ((mxc_spi_reva_regs_t*) spi)); + return ((mxc_spi_width_t)MXC_SPI_RevA_GetWidth((mxc_spi_reva_regs_t *)spi)); } -int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode) +int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode) { - return MXC_SPI_RevA_SetMode ((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_mode_t) spiMode); + return MXC_SPI_RevA_SetMode((mxc_spi_reva_regs_t *)spi, (mxc_spi_reva_mode_t)spiMode); } -mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi) +mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi) { - return ((mxc_spi_mode_t) MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t*) spi)); + return ((mxc_spi_mode_t)MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t *)spi)); } -int MXC_SPI_StartTransmission(mxc_spi_regs_t* spi) +int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_StartTransmission ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_StartTransmission((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_GetActive(mxc_spi_regs_t* spi) +int MXC_SPI_GetActive(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetActive ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetActive((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_AbortTransmission(mxc_spi_regs_t* spi) +int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_AbortTransmission ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_AbortTransmission((mxc_spi_reva_regs_t *)spi); } -unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes, - unsigned int len) +unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len) { - return MXC_SPI_RevA_ReadRXFIFO ((mxc_spi_reva_regs_t*) spi, bytes, len); + return MXC_SPI_RevA_ReadRXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len); } -unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetRXFIFOAvailable ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetRXFIFOAvailable((mxc_spi_reva_regs_t *)spi); } -unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes, - unsigned int len) +unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len) { - return MXC_SPI_RevA_WriteTXFIFO ((mxc_spi_reva_regs_t*) spi, bytes, len); + return MXC_SPI_RevA_WriteTXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len); } -unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetTXFIFOAvailable ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetTXFIFOAvailable((mxc_spi_reva_regs_t *)spi); } -void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t* spi) +void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi) { - MXC_SPI_RevA_ClearRXFIFO ((mxc_spi_reva_regs_t*) spi); + MXC_SPI_RevA_ClearRXFIFO((mxc_spi_reva_regs_t *)spi); } -void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t* spi) +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi) { - MXC_SPI_RevA_ClearTXFIFO ((mxc_spi_reva_regs_t*) spi); + MXC_SPI_RevA_ClearTXFIFO((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetRXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes) +int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes) { - return MXC_SPI_RevA_SetRXThreshold ((mxc_spi_reva_regs_t*) spi, numBytes); + return MXC_SPI_RevA_SetRXThreshold((mxc_spi_reva_regs_t *)spi, numBytes); } -unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetRXThreshold ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetRXThreshold((mxc_spi_reva_regs_t *)spi); } -int MXC_SPI_SetTXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes) +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes) { - return MXC_SPI_RevA_SetTXThreshold ((mxc_spi_reva_regs_t*) spi, numBytes); + return MXC_SPI_RevA_SetTXThreshold((mxc_spi_reva_regs_t *)spi, numBytes); } -unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetTXThreshold ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetTXThreshold((mxc_spi_reva_regs_t *)spi); } -unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t* spi) +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi) { - return MXC_SPI_RevA_GetFlags ((mxc_spi_reva_regs_t*) spi); + return MXC_SPI_RevA_GetFlags((mxc_spi_reva_regs_t *)spi); } -void MXC_SPI_ClearFlags(mxc_spi_regs_t* spi) +void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi) { - MXC_SPI_RevA_ClearFlags ((mxc_spi_reva_regs_t*) spi); + MXC_SPI_RevA_ClearFlags((mxc_spi_reva_regs_t *)spi); } -void MXC_SPI_EnableInt(mxc_spi_regs_t* spi, unsigned int mask) +void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int mask) { - MXC_SPI_RevA_EnableInt ((mxc_spi_reva_regs_t*) spi, mask); + MXC_SPI_RevA_EnableInt((mxc_spi_reva_regs_t *)spi, mask); } -void MXC_SPI_DisableInt(mxc_spi_regs_t* spi, unsigned int mask) +void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int mask) { - MXC_SPI_RevA_DisableInt ((mxc_spi_reva_regs_t*) spi, mask); + MXC_SPI_RevA_DisableInt((mxc_spi_reva_regs_t *)spi, mask); } -int MXC_SPI_MasterTransaction(mxc_spi_req_t* req) +int MXC_SPI_MasterTransaction(mxc_spi_req_t *req) { - return MXC_SPI_RevA_MasterTransaction ((mxc_spi_reva_req_t*) req); + return MXC_SPI_RevA_MasterTransaction((mxc_spi_reva_req_t *)req); } -int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t* req) +int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req) { - return MXC_SPI_RevA_MasterTransactionAsync ((mxc_spi_reva_req_t*) req); + return MXC_SPI_RevA_MasterTransactionAsync((mxc_spi_reva_req_t *)req); } -int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req) +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) { int reqselTx = -1; int reqselRx = -1; - + int spi_num; - + spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - + if (req->txData != NULL) { switch (spi_num) { case 0: reqselTx = MXC_DMA_REQUEST_SPI0TX; break; - + case 1: reqselTx = MXC_DMA_REQUEST_SPI1TX; break; - + case 2: reqselTx = MXC_DMA_REQUEST_SPI2TX; break; - + default: return E_BAD_PARAM; } } - + if (req->rxData != NULL) { switch (spi_num) { case 0: reqselRx = MXC_DMA_REQUEST_SPI0RX; break; - + case 1: reqselRx = MXC_DMA_REQUEST_SPI1RX; break; - + case 2: reqselRx = MXC_DMA_REQUEST_SPI2RX; break; - + default: return E_BAD_PARAM; } } - return MXC_SPI_RevA_MasterTransactionDMA ((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA); + return MXC_SPI_RevA_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, + MXC_DMA); } -int MXC_SPI_SlaveTransaction(mxc_spi_req_t* req) +int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req) { - return MXC_SPI_RevA_SlaveTransaction ((mxc_spi_reva_req_t*) req); + return MXC_SPI_RevA_SlaveTransaction((mxc_spi_reva_req_t *)req); } -int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t* req) +int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req) { - return MXC_SPI_RevA_SlaveTransactionAsync ((mxc_spi_reva_req_t*) req); + return MXC_SPI_RevA_SlaveTransactionAsync((mxc_spi_reva_req_t *)req); } -int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req) +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) { int reqselTx = -1; int reqselRx = -1; - + int spi_num; - + spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - + if (req->txData != NULL) { switch (spi_num) { case 0: reqselTx = MXC_DMA_REQUEST_SPI0TX; break; - + case 1: reqselTx = MXC_DMA_REQUEST_SPI1TX; break; - + case 2: reqselTx = MXC_DMA_REQUEST_SPI2TX; break; - + default: return E_BAD_PARAM; } } - + if (req->rxData != NULL) { switch (spi_num) { case 0: reqselRx = MXC_DMA_REQUEST_SPI0RX; break; - + case 1: reqselRx = MXC_DMA_REQUEST_SPI1RX; break; - + case 2: reqselRx = MXC_DMA_REQUEST_SPI2RX; break; - + default: return E_BAD_PARAM; } } - return MXC_SPI_RevA_SlaveTransactionDMA ((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA); + return MXC_SPI_RevA_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, MXC_DMA); } -int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t* spi, unsigned int defaultTXData) +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData) { - return MXC_SPI_RevA_SetDefaultTXData ((mxc_spi_reva_regs_t*) spi, defaultTXData); + return MXC_SPI_RevA_SetDefaultTXData((mxc_spi_reva_regs_t *)spi, defaultTXData); } -void MXC_SPI_AbortAsync(mxc_spi_regs_t* spi) +void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi) { - MXC_SPI_RevA_AbortAsync ((mxc_spi_reva_regs_t*) spi); + MXC_SPI_RevA_AbortAsync((mxc_spi_reva_regs_t *)spi); } -void MXC_SPI_AsyncHandler(mxc_spi_regs_t* spi) +void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi) { - MXC_SPI_RevA_AsyncHandler ((mxc_spi_reva_regs_t*) spi); + MXC_SPI_RevA_AsyncHandler((mxc_spi_reva_regs_t *)spi); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c index 174817d..2726ede 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,13 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ -#ifdef __CC_ARM //Keil -#pragma diag_suppress 188 // enumerated type mixed with another type -#pragma diag_suppress 68 // integer conversion resulted in a change of sign -#endif - - + ******************************************************************************/ #include #include @@ -59,334 +53,397 @@ unsigned defaultTXData; int channelTx; int channelRx; + int mtMode; + int mtFirstTrans; bool txrx_req; uint8_t req_done; + uint8_t async; unsigned drv_ssel; } spi_req_reva_state_t; -/* states whether to use call back or not */ -uint8_t async; - static spi_req_reva_state_t states[MXC_SPI_INSTANCES]; -static uint32_t MXC_SPI_RevA_MasterTransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req); -static uint32_t MXC_SPI_RevA_TransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req); -static uint32_t MXC_SPI_RevA_SlaveTransHandler (mxc_spi_reva_req_t *req); -static void MXC_SPI_RevA_SwapByte (uint8_t * arr, size_t length); -static int MXC_SPI_RevA_TransSetup (mxc_spi_reva_req_t * req); +static uint32_t MXC_SPI_RevA_MasterTransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req); +static uint32_t MXC_SPI_RevA_TransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req); +static uint32_t MXC_SPI_RevA_SlaveTransHandler(mxc_spi_reva_req_t *req); +static void MXC_SPI_RevA_SwapByte(uint8_t *arr, size_t length); +static int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req); - -int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz, unsigned drv_ssel) +int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel) { int spi_num; - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); + states[spi_num].req = NULL; states[spi_num].last_size = 0; states[spi_num].ssDeassert = 1; states[spi_num].defaultTXData = 0; + states[spi_num].mtMode = 0; + states[spi_num].mtFirstTrans = 0; + states[spi_num].channelTx = E_NO_DEVICE; + states[spi_num].channelRx = E_NO_DEVICE; states[spi_num].drv_ssel = drv_ssel; - + spi->ctrl0 = (MXC_F_SPI_REVA_CTRL0_EN); - spi->sstime = ( (0x1 << MXC_F_SPI_REVA_SSTIME_PRE_POS) | - (0x1 << MXC_F_SPI_REVA_SSTIME_POST_POS) | - (0x1 << MXC_F_SPI_REVA_SSTIME_INACT_POS)); - + spi->sstime = + ((0x1 << MXC_F_SPI_REVA_SSTIME_PRE_POS) | (0x1 << MXC_F_SPI_REVA_SSTIME_POST_POS) | + (0x1 << MXC_F_SPI_REVA_SSTIME_INACT_POS)); + //set master if (masterMode) { spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_MST_MODE; + } else { + spi->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_MST_MODE); } - else { - spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_MST_MODE); + + MXC_SPI_SetFrequency((mxc_spi_regs_t *)spi, hz); + + if (ssPolarity > (MXC_F_SPI_REVA_CTRL2_SS_POL >> MXC_F_SPI_REVA_CTRL2_SS_POL_POS)) { + return E_BAD_PARAM; } - - MXC_SPI_SetFrequency ((mxc_spi_regs_t*) spi, hz); - + //set slave select polarity - spi->ctrl2 |= ( (!!ssPolarity) << MXC_F_SPI_REVA_CTRL2_SS_POL_POS); - + spi->ctrl2 |= (ssPolarity << MXC_F_SPI_REVA_CTRL2_SS_POL_POS); + // Clear the interrupts spi->intfl = spi->intfl; - + // Driver will drive SS pin? if (states[spi_num].drv_ssel) { - if (numSlaves == 1) { - spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0; + if (numSlaves == 1) { + spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0; } - - else if (numSlaves == 2) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1); - } - - else if (numSlaves == 3) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2); - } - - else if (numSlaves == 4) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3); - } + + else if (numSlaves == 2) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1); + } + + else if (numSlaves == 3) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | + MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2); + } + + else if (numSlaves == 4) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | + MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3); + } } //set quad mode if (quadModeUsed) { spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD; } - + return E_NO_ERROR; } -int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_Shutdown(mxc_spi_reva_regs_t *spi) { int spi_num; - mxc_spi_reva_req_t * temp_req; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); - + mxc_spi_reva_req_t *temp_req; + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); + //disable and clear interrupts spi->inten = 0; spi->intfl = spi->intfl; - + // Disable SPI and FIFOS - spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); - spi->dma &= ~ (MXC_F_SPI_REVA_DMA_TX_FIFO_EN | MXC_F_SPI_REVA_DMA_RX_FIFO_EN); - + spi->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); + spi->dma &= ~(MXC_F_SPI_REVA_DMA_TX_FIFO_EN | MXC_F_SPI_REVA_DMA_RX_FIFO_EN); + //call all of the pending callbacks for this spi - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + if (states[spi_num].req != NULL) { //save the request temp_req = states[spi_num].req; - MXC_FreeLock((uint32_t*)(uint32_t*) &states[spi_num].req); - + MXC_FreeLock((uint32_t *)(uint32_t *)&states[spi_num].req); + // Callback if not NULL if (states[spi_num].req->completeCB != NULL) { states[spi_num].req->completeCB(temp_req, E_SHUTDOWN); } - } - + // Clear registers spi->ctrl0 = 0; spi->ctrl1 = 0; spi->ctrl2 = 0; spi->sstime = 0; - + + // release any acquired DMA channels + if (states[spi_num].channelTx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelTx); + states[spi_num].channelTx = E_NO_DEVICE; + } + if (states[spi_num].channelRx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelRx); + states[spi_num].channelRx = E_NO_DEVICE; + } + return E_NO_ERROR; } -int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_ReadyForSleep(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - - if (spi->stat & MXC_F_SPI_REVA_STAT_BUSY || (spi->dma & MXC_F_SPI_REVA_DMA_TX_LVL) || (spi->dma & MXC_F_SPI_REVA_DMA_RX_LVL)) { + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + + if (spi->stat & MXC_F_SPI_REVA_STAT_BUSY || (spi->dma & MXC_F_SPI_REVA_DMA_TX_LVL) || + (spi->dma & MXC_F_SPI_REVA_DMA_RX_LVL)) { return E_BUSY; - } - else { + } else { return E_NO_ERROR; } } -int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz) +int MXC_SPI_RevA_SetFrequency(mxc_spi_reva_regs_t *spi, unsigned int hz) { int hi_clk, lo_clk, scale; uint32_t freq_div; - + // Check if frequency is too high if (hz > PeripheralClock) { return E_BAD_PARAM; } - + // Set the clock high and low - freq_div = MXC_SPI_GetPeripheralClock((mxc_spi_regs_t*) spi); + freq_div = MXC_SPI_GetPeripheralClock((mxc_spi_regs_t *)spi); freq_div = (freq_div / hz); hi_clk = freq_div / 2; lo_clk = freq_div / 2; scale = 0; - + if (freq_div % 2) { hi_clk += 1; } - + while (hi_clk >= 16 && scale < 8) { hi_clk /= 2; lo_clk /= 2; - scale ++; + scale++; } - + if (scale == 8) { lo_clk = 15; hi_clk = 15; } - - MXC_SETFIELD (spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_LO, (lo_clk << MXC_F_SPI_REVA_CLKCTRL_LO_POS)); - MXC_SETFIELD (spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_HI, (hi_clk << MXC_F_SPI_REVA_CLKCTRL_HI_POS)); - MXC_SETFIELD (spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_CLKDIV, (scale << MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS)); - + + MXC_SETFIELD(spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_LO, + (lo_clk << MXC_F_SPI_REVA_CLKCTRL_LO_POS)); + MXC_SETFIELD(spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_HI, + (hi_clk << MXC_F_SPI_REVA_CLKCTRL_HI_POS)); + MXC_SETFIELD(spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_CLKDIV, + (scale << MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS)); + return E_NO_ERROR; } -unsigned int MXC_SPI_RevA_GetFrequency (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetFrequency(mxc_spi_reva_regs_t *spi) { - if (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) < 0) { + if (MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) < 0) { return E_BAD_PARAM; } - + unsigned scale, lo_clk, hi_clk; - + scale = (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_CLKDIV) >> MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS; - hi_clk= (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_HI) >> MXC_F_SPI_REVA_CLKCTRL_HI_POS; - lo_clk= (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_LO) >> MXC_F_SPI_REVA_CLKCTRL_LO_POS; - + hi_clk = (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_HI) >> MXC_F_SPI_REVA_CLKCTRL_HI_POS; + lo_clk = (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_LO) >> MXC_F_SPI_REVA_CLKCTRL_LO_POS; + return (PeripheralClock / (1 << scale)) / (lo_clk + hi_clk); } -int MXC_SPI_RevA_SetDataSize (mxc_spi_reva_regs_t* spi, int dataSize) +int MXC_SPI_RevA_SetDataSize(mxc_spi_reva_regs_t *spi, int dataSize) { int spi_num; - + // HW has problem with these two character sizes if (dataSize == 1 || dataSize > 16) { return E_BAD_PARAM; } - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); + // Setup the character size - if (! (spi->stat & MXC_F_SPI_REVA_STAT_BUSY) && states[spi_num].ssDeassert == 1) { + if (!(spi->stat & MXC_F_SPI_REVA_STAT_BUSY) && states[spi_num].ssDeassert == 1) { //disable spi to change transfer size - spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); + spi->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); // set bit size states[spi_num].last_size = dataSize; - + if (dataSize < 16) { - MXC_SETFIELD (spi->ctrl2, MXC_F_SPI_REVA_CTRL2_NUMBITS, dataSize << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS); + MXC_SETFIELD(spi->ctrl2, MXC_F_SPI_REVA_CTRL2_NUMBITS, + dataSize << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS); + } else { + MXC_SETFIELD(spi->ctrl2, MXC_F_SPI_REVA_CTRL2_NUMBITS, + 0 << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS); //may not be neccessary } - - else { - MXC_SETFIELD (spi->ctrl2, MXC_F_SPI_REVA_CTRL2_NUMBITS, 0 << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS); //may not be neccessary - } - + //enable spi to change transfer size spi->ctrl0 |= (MXC_F_SPI_REVA_CTRL0_EN); - } - else { + } else { return E_BAD_STATE; } - + return E_NO_ERROR; } -int MXC_SPI_RevA_GetDataSize (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_GetDataSize(mxc_spi_reva_regs_t *spi) { int spi_num; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - + if (!(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_NUMBITS)) { return 16; } - + return (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_NUMBITS) >> MXC_F_SPI_REVA_CTRL2_NUMBITS_POS; } -int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx) +int MXC_SPI_RevA_SetMTMode(mxc_spi_reva_regs_t *spi, int mtMode) { int spi_num; - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); + + if ((mtMode != 0) && (mtMode != 1)) { + return E_BAD_PARAM; + } + + if (states[spi_num].mtMode == 1) { + if (mtMode == 0) { + // exiting MT Mode: release any acquired DMA channels + if (states[spi_num].channelTx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelTx); + states[spi_num].channelTx = E_NO_DEVICE; + } + if (states[spi_num].channelRx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelRx); + states[spi_num].channelRx = E_NO_DEVICE; + } + } + } else if (mtMode == 1) { + // entering MT Mode: set first transaction + states[spi_num].mtFirstTrans = 1; + } + + states[spi_num].mtMode = mtMode; + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_GetMTMode(mxc_spi_reva_regs_t *spi) +{ + int spi_num; + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); + + return states[spi_num].mtMode; +} + +int MXC_SPI_RevA_SetSlave(mxc_spi_reva_regs_t *spi, int ssIdx) +{ + int spi_num; + // HW has problem with these two character sizes if (ssIdx >= MXC_SPI_SS_INSTANCES) { return E_BAD_PARAM; } - + //check if in master mode - if (! (spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE)) { + if (!(spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE)) { return E_BAD_STATE; } - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - + if (states[spi_num].drv_ssel) { // Setup the slave select // Activate chosen SS pin - spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; + spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; // Deactivate all unchosen pins - spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS); + spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | + ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS); } return E_NO_ERROR; } -int MXC_SPI_RevA_GetSlave (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_GetSlave(mxc_spi_reva_regs_t *spi) { - int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + int spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - - return ( (spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_SS_ACTIVE) >> MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) >> 1; + + return ((spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_SS_ACTIVE) >> MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) >> + 1; } -int MXC_SPI_RevA_SetWidth (mxc_spi_reva_regs_t* spi, mxc_spi_reva_width_t spiWidth) +int MXC_SPI_RevA_SetWidth(mxc_spi_reva_regs_t *spi, mxc_spi_reva_width_t spiWidth) { int spi_num; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - - spi->ctrl2 &= ~ (MXC_F_SPI_REVA_CTRL2_THREE_WIRE | MXC_F_SPI_REVA_CTRL2_DATA_WIDTH); - + + spi->ctrl2 &= ~(MXC_F_SPI_REVA_CTRL2_THREE_WIRE | MXC_F_SPI_REVA_CTRL2_DATA_WIDTH); + switch (spiWidth) { - case SPI_REVA_WIDTH_3WIRE: spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_THREE_WIRE; break; - + case SPI_REVA_WIDTH_STANDARD: spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_MONO; break; - + case SPI_REVA_WIDTH_DUAL: spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_DUAL; break; - + case SPI_REVA_WIDTH_QUAD: spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD; break; } - + return E_NO_ERROR; } -mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth (mxc_spi_reva_regs_t* spi) +mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth(mxc_spi_reva_regs_t *spi) { if (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_THREE_WIRE) { return SPI_REVA_WIDTH_3WIRE; } - + if (spi->ctrl2 & MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_DUAL) { return SPI_REVA_WIDTH_DUAL; } - + if (spi->ctrl2 & MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD) { return SPI_REVA_WIDTH_QUAD; } - + return SPI_REVA_WIDTH_STANDARD; } -int MXC_SPI_RevA_SetMode (mxc_spi_reva_regs_t* spi, mxc_spi_reva_mode_t spiMode) +int MXC_SPI_RevA_SetMode(mxc_spi_reva_regs_t *spi, mxc_spi_reva_mode_t spiMode) { - int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + int spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - switch(spiMode) { + switch (spiMode) { case SPI_REVA_MODE_0: spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPHA; spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPOL; @@ -394,42 +451,40 @@ case SPI_REVA_MODE_1: spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPHA; - spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPOL; + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPOL; break; case SPI_REVA_MODE_2: - spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPHA; + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPHA; spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPOL; break; case SPI_REVA_MODE_3: - spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPHA; - spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPOL; + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPHA; + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPOL; break; default: - break; + break; } return E_NO_ERROR; } -mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode (mxc_spi_reva_regs_t* spi) +mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode(mxc_spi_reva_regs_t *spi) { - int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + int spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - if(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPHA) { - if(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPOL) { + if (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPHA) { + if (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPOL) { return SPI_REVA_MODE_3; - } - else { + } else { return SPI_REVA_MODE_2; } - } - else { - if(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPOL) { + } else { + if (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPOL) { return SPI_REVA_MODE_1; } } @@ -437,584 +492,595 @@ return SPI_REVA_MODE_0; } -int MXC_SPI_RevA_StartTransmission (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_StartTransmission(mxc_spi_reva_regs_t *spi) { - int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + int spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); (void)spi_num; - - if (MXC_SPI_GetActive ((mxc_spi_regs_t*) spi) == E_BUSY) { + + if (MXC_SPI_GetActive((mxc_spi_regs_t *)spi) == E_BUSY) { return E_BUSY; } - + spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_START; - + return E_NO_ERROR; } -int MXC_SPI_RevA_GetActive (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_GetActive(mxc_spi_reva_regs_t *spi) { if (spi->stat & MXC_F_SPI_REVA_STAT_BUSY) { return E_BUSY; } - + return E_NO_ERROR; } -int MXC_SPI_RevA_AbortTransmission (mxc_spi_reva_regs_t* spi) +int MXC_SPI_RevA_AbortTransmission(mxc_spi_reva_regs_t *spi) { int spi_num; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); // Disable interrupts, clear the flags spi->inten = 0; spi->intfl = spi->intfl; - + // Reset the SPI17Y to cancel the on ongoing transaction - spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); + spi->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); spi->ctrl0 |= (MXC_F_SPI_REVA_CTRL0_EN); - + // Unlock this SPI - mxc_spi_reva_req_t * temp = states[spi_num].req; - MXC_FreeLock ((uint32_t*) &states[spi_num].req); - + mxc_spi_reva_req_t *temp = states[spi_num].req; + MXC_FreeLock((uint32_t *)&states[spi_num].req); + // Callback if not NULL if (temp->completeCB != NULL) { temp->completeCB(states[spi_num].req, E_ABORT); } - + + // release any acquired DMA channels + if (states[spi_num].channelTx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelTx); + states[spi_num].channelTx = E_NO_DEVICE; + } + if (states[spi_num].channelRx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[spi_num].channelRx); + states[spi_num].channelRx = E_NO_DEVICE; + } + if (states[spi_num].mtMode == 1) { + states[spi_num].mtFirstTrans = 1; + } + return E_NO_ERROR; } -unsigned int MXC_SPI_RevA_ReadRXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, - unsigned int len) +unsigned int MXC_SPI_RevA_ReadRXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes, + unsigned int len) { - unsigned rx_avail,bits; - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - + unsigned rx_avail, bits; + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + if (!bytes || !len) { return 0; } - - rx_avail = MXC_SPI_GetRXFIFOAvailable ((mxc_spi_regs_t*) spi); - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) spi); - + + rx_avail = MXC_SPI_GetRXFIFOAvailable((mxc_spi_regs_t *)spi); + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)spi); + if (len > rx_avail) { len = rx_avail; } - + if (bits > 8) { - len &= ~(unsigned) 0x1; + len &= ~(unsigned)0x1; } - + unsigned cnt = 0; - + if (bits <= 8 || len >= 2) { // Read from the FIFO while (len) { if (len > 3) { - memcpy(& ((uint8_t*) bytes) [cnt], (void*) &spi->fifo32, 4); + memcpy((uint8_t *)(&bytes[cnt]), (void *)(&spi->fifo32), 4); len -= 4; cnt += 4; - } - else if (len > 1) { - memcpy(& ((uint8_t*) bytes) [cnt], (void*) &spi->fifo16[0], 2); + } else if (len > 1) { + memcpy((uint8_t *)(&bytes[cnt]), (void *)(&spi->fifo16[0]), 2); len -= 2; cnt += 2; - - } - else { - ((uint8_t*) bytes) [cnt++] = spi->fifo8[0]; + + } else { + ((uint8_t *)bytes)[cnt++] = spi->fifo8[0]; len -= 1; } - + // Don't read less than 2 bytes if we are using greater than 8 bit characters if (len == 1 && bits > 8) { break; } } } - + return cnt; } -unsigned int MXC_SPI_RevA_GetRXFIFOAvailable (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetRXFIFOAvailable(mxc_spi_reva_regs_t *spi) { return (spi->dma & MXC_F_SPI_REVA_DMA_RX_LVL) >> MXC_F_SPI_REVA_DMA_RX_LVL_POS; } -unsigned int MXC_SPI_RevA_WriteTXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, - unsigned int len) +unsigned int MXC_SPI_RevA_WriteTXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes, + unsigned int len) { - unsigned tx_avail,bits; - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - + unsigned tx_avail, bits; + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + if (!bytes || !len) { return 0; } - - tx_avail = MXC_SPI_GetTXFIFOAvailable ((mxc_spi_regs_t*) spi); - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) spi); - + + tx_avail = MXC_SPI_GetTXFIFOAvailable((mxc_spi_regs_t *)spi); + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)spi); + if (len > tx_avail) { len = tx_avail; } - + if (bits > 8) { - len &= ~(unsigned) 0x1; + len &= ~(unsigned)0x1; } - + unsigned cnt = 0; - + while (len) { if (len > 3) { - memcpy((void*) &spi->fifo32, & ((uint8_t*) bytes) [cnt], 4); - + memcpy((void *)(&spi->fifo32), (uint8_t *)(&bytes[cnt]), 4); + len -= 4; cnt += 4; - - } - else if (len > 1) { - memcpy((void*) &spi->fifo16[0], & ((uint8_t*) bytes) [cnt], 2); - + + } else if (len > 1) { + memcpy((void *)(&spi->fifo16[0]), (uint8_t *)(&bytes[cnt]), 2); + len -= 2; cnt += 2; - - } - else if (bits <= 8) { - spi->fifo8[0] = ((uint8_t*) bytes) [cnt++]; + + } else if (bits <= 8) { + spi->fifo8[0] = ((uint8_t *)bytes)[cnt++]; len--; } - } - + return cnt; } -unsigned int MXC_SPI_RevA_GetTXFIFOAvailable (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetTXFIFOAvailable(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - return MXC_SPI_FIFO_DEPTH - ((spi->dma & MXC_F_SPI_REVA_DMA_TX_LVL) >> MXC_F_SPI_REVA_DMA_TX_LVL_POS); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + return MXC_SPI_FIFO_DEPTH - + ((spi->dma & MXC_F_SPI_REVA_DMA_TX_LVL) >> MXC_F_SPI_REVA_DMA_TX_LVL_POS); } -void MXC_SPI_RevA_ClearRXFIFO (mxc_spi_reva_regs_t* spi) +void MXC_SPI_RevA_ClearRXFIFO(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); spi->dma |= MXC_F_SPI_REVA_DMA_RX_FLUSH; } -void MXC_SPI_RevA_ClearTXFIFO (mxc_spi_reva_regs_t* spi) +void MXC_SPI_RevA_ClearTXFIFO(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); spi->dma |= MXC_F_SPI_REVA_DMA_TX_FLUSH; } -int MXC_SPI_RevA_SetRXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes) +int MXC_SPI_RevA_SetRXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + if (numBytes > 32) { return E_BAD_PARAM; } - - MXC_SETFIELD (spi->dma, MXC_F_SPI_REVA_DMA_RX_THD_VAL, numBytes << MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS); - + + MXC_SETFIELD(spi->dma, MXC_F_SPI_REVA_DMA_RX_THD_VAL, + numBytes << MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS); + return E_NO_ERROR; } -unsigned int MXC_SPI_RevA_GetRXThreshold (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetRXThreshold(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); return (spi->dma & MXC_F_SPI_REVA_DMA_RX_THD_VAL) >> MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS; } -int MXC_SPI_RevA_SetTXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes) +int MXC_SPI_RevA_SetTXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + if (numBytes > 32) { return E_BAD_PARAM; } - - MXC_SETFIELD (spi->dma, MXC_F_SPI_REVA_DMA_TX_THD_VAL, numBytes << MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS); - + + MXC_SETFIELD(spi->dma, MXC_F_SPI_REVA_DMA_TX_THD_VAL, + numBytes << MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS); + return E_NO_ERROR; } -unsigned int MXC_SPI_RevA_GetTXThreshold (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetTXThreshold(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); return (spi->dma & MXC_F_SPI_REVA_DMA_TX_THD_VAL) >> MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS; } -unsigned int MXC_SPI_RevA_GetFlags (mxc_spi_reva_regs_t* spi) +unsigned int MXC_SPI_RevA_GetFlags(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); return spi->intfl; } -void MXC_SPI_RevA_ClearFlags (mxc_spi_reva_regs_t* spi) +void MXC_SPI_RevA_ClearFlags(mxc_spi_reva_regs_t *spi) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); spi->intfl = spi->intfl; } -void MXC_SPI_RevA_EnableInt (mxc_spi_reva_regs_t* spi, unsigned int intEn) +void MXC_SPI_RevA_EnableInt(mxc_spi_reva_regs_t *spi, unsigned int intEn) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); spi->inten |= intEn; } -void MXC_SPI_RevA_DisableInt (mxc_spi_reva_regs_t* spi, unsigned int intDis) +void MXC_SPI_RevA_DisableInt(mxc_spi_reva_regs_t *spi, unsigned int intDis) { - MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); - spi->inten &= ~ (intDis); + MXC_ASSERT(MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi) >= 0); + spi->inten &= ~(intDis); } -int MXC_SPI_RevA_TransSetup (mxc_spi_reva_req_t * req) +int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req) { int spi_num; uint8_t bits; - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)(req->spi)); + MXC_ASSERT(spi_num >= 0); + MXC_ASSERT(req->ssIdx < MXC_SPI_SS_INSTANCES); + if ((!req) || ((req->txData == NULL) && (req->rxData == NULL))) { return E_BAD_PARAM; } - + // Setup the number of characters to transact if (req->txLen > (MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR >> MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS)) { return E_BAD_PARAM; } - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*)(req->spi)); - MXC_ASSERT (spi_num >= 0); - MXC_ASSERT (req->ssIdx < MXC_SPI_SS_INSTANCES); - - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); + + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); req->txCnt = 0; req->rxCnt = 0; - + states[spi_num].req = req; states[spi_num].started = 0; states[spi_num].req_done = 0; - // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive). if (states[spi_num].ssDeassert == 1) { - (req->spi)->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); + (req->spi)->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN); } - - //if master + + //if master if ((req->spi)->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE) { // Setup the slave select - MXC_SPI_SetSlave ((mxc_spi_regs_t*) req->spi, req->ssIdx); - + MXC_SPI_SetSlave((mxc_spi_regs_t *)req->spi, req->ssIdx); } - + if (req->rxData != NULL && req->rxLen > 0) { - MXC_SETFIELD ( (req->spi)->ctrl1, MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR, - req->rxLen << MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS); + MXC_SETFIELD((req->spi)->ctrl1, MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR, + req->rxLen << MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS); (req->spi)->dma |= MXC_F_SPI_REVA_DMA_RX_FIFO_EN; + } else { + (req->spi)->ctrl1 &= ~(MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR); + (req->spi)->dma &= ~(MXC_F_SPI_REVA_DMA_RX_FIFO_EN); } - else { - (req->spi)->ctrl1 &= ~ (MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR); - (req->spi)->dma &= ~ (MXC_F_SPI_REVA_DMA_RX_FIFO_EN); - } - - // Must use TXFIFO and NUM in full duplex//start editing here - if ((mxc_spi_reva_width_t) MXC_SPI_GetWidth ((mxc_spi_regs_t*) req->spi) == SPI_REVA_WIDTH_STANDARD - && ! ( ( (req->spi)->ctrl2 & MXC_F_SPI_REVA_CTRL2_THREE_WIRE) >> MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS)) { + + // Must use TXFIFO and NUM in full duplex//start editing here + if ((mxc_spi_reva_width_t)MXC_SPI_GetWidth((mxc_spi_regs_t *)req->spi) == + SPI_REVA_WIDTH_STANDARD && + !(((req->spi)->ctrl2 & MXC_F_SPI_REVA_CTRL2_THREE_WIRE) >> + MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS)) { if (req->txData == NULL) { // Must have something to send, so we'll use the rx_data buffer initialized to 0. //SPI_SetDefaultTXData(spi, 0); - memset(req->rxData, states[spi_num].defaultTXData, (bits > 8 ? req->rxLen << 1 : req->rxLen)); + memset(req->rxData, states[spi_num].defaultTXData, + (bits > 8 ? req->rxLen << 1 : req->rxLen)); req->txData = req->rxData; req->txLen = req->rxLen; } } - - if(req->txData != NULL && req->txLen > 0) { - MXC_SETFIELD ( (req->spi)->ctrl1, MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR, - req->txLen << MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS); + + if (req->txData != NULL && req->txLen > 0) { + MXC_SETFIELD((req->spi)->ctrl1, MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR, + req->txLen << MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS); (req->spi)->dma |= MXC_F_SPI_REVA_DMA_TX_FIFO_EN; - } - else { + } else { (req->spi)->ctrl1 &= ~(MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR); (req->spi)->dma &= ~(MXC_F_SPI_REVA_DMA_TX_FIFO_EN); } - if((req->txData != NULL && req->txLen) && (req->rxData != NULL && req->rxLen)) { + if ((req->txData != NULL && req->txLen) && (req->rxData != NULL && req->rxLen)) { states[spi_num].txrx_req = true; - } - else { + } else { states[spi_num].txrx_req = false; } - (req->spi)->dma |= (MXC_F_SPI_REVA_DMA_TX_FLUSH | MXC_F_SPI_REVA_DMA_RX_FLUSH); (req->spi)->ctrl0 |= (MXC_F_SPI_REVA_CTRL0_EN); - + states[spi_num].ssDeassert = req->ssDeassert; // Clear master done flag (req->spi)->intfl = MXC_F_SPI_REVA_INTFL_MST_DONE; - - + return E_NO_ERROR; } -uint32_t MXC_SPI_RevA_MasterTransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req) +uint32_t MXC_SPI_RevA_MasterTransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req) { uint32_t retval; int spi_num; - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + // Leave slave select asserted at the end of the transaction if (states[spi_num].drv_ssel) { - if (!req->ssDeassert) { + if (!req->ssDeassert) { spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; - } + } } retval = MXC_SPI_RevA_TransHandler(spi, req); - + if (!states[spi_num].started) { - MXC_SPI_StartTransmission ((mxc_spi_regs_t*) spi); + MXC_SPI_StartTransmission((mxc_spi_regs_t *)spi); states[spi_num].started = 1; } - + // Deassert slave select at the end of the transaction if (states[spi_num].drv_ssel) { if (req->ssDeassert) { spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; - } + } } return retval; } -uint32_t MXC_SPI_RevA_SlaveTransHandler (mxc_spi_reva_req_t *req) +uint32_t MXC_SPI_RevA_SlaveTransHandler(mxc_spi_reva_req_t *req) { return MXC_SPI_RevA_TransHandler(req->spi, req); } -uint32_t MXC_SPI_RevA_TransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req) +uint32_t MXC_SPI_RevA_TransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req) { int remain, spi_num; uint32_t int_en = 0; uint32_t tx_length = 0, rx_length = 0; uint8_t bits; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - if (spi_num == -1) { - return E_BAD_PARAM; - } + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); - + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); + //MXC_F_SPI_REVA_CTRL2_NUMBITS data bits // Read/write 2x number of bytes if larger character size if (bits > 8) { tx_length = req->txLen * 2; rx_length = req->rxLen * 2; - } - else { + } else { tx_length = req->txLen; rx_length = req->rxLen; } - + if (req->txData != NULL) { - - req->txCnt += MXC_SPI_WriteTXFIFO ((mxc_spi_regs_t*) spi, & (req->txData[req->txCnt]),tx_length - req->txCnt); + req->txCnt += MXC_SPI_WriteTXFIFO((mxc_spi_regs_t *)spi, &(req->txData[req->txCnt]), + tx_length - req->txCnt); } - + remain = tx_length - req->txCnt; - + // Set the TX interrupts // Write the FIFO //starting here if (remain) { if (remain > MXC_SPI_FIFO_DEPTH) { - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) spi,MXC_SPI_FIFO_DEPTH); + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)spi, MXC_SPI_FIFO_DEPTH); + } else { + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)spi, remain); } - else { - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) spi,remain); - } - + int_en |= MXC_F_SPI_REVA_INTEN_TX_THD; - } // Break out if we've transmitted all the bytes and not receiving if ((req->rxData == NULL) && (req->txCnt == tx_length)) { spi->inten = 0; int_en = 0; - MXC_FreeLock((uint32_t*) &states[spi_num].req); - + MXC_FreeLock((uint32_t *)&states[spi_num].req); + // Callback if not NULL - if (async && req->completeCB != NULL) { + if (states[spi_num].async && req->completeCB != NULL) { req->completeCB(req, E_NO_ERROR); } } // Read the RX FIFO if (req->rxData != NULL) { - - req->rxCnt += MXC_SPI_ReadRXFIFO ((mxc_spi_regs_t*) spi,& (req->rxData[req->rxCnt]),rx_length - req->rxCnt); - - + req->rxCnt += MXC_SPI_ReadRXFIFO((mxc_spi_regs_t *)spi, &(req->rxData[req->rxCnt]), + rx_length - req->rxCnt); + remain = rx_length - req->rxCnt; - + if (remain) { if (remain > MXC_SPI_FIFO_DEPTH) { - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) spi, 2); + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)spi, 2); + } else { + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)spi, remain - 1); } - else { - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) spi, remain - 1); - } - + int_en |= MXC_F_SPI_REVA_INTEN_RX_THD; } - + // Break out if we've received all the bytes and we're not transmitting if ((req->txData == NULL) && (req->rxCnt == rx_length)) { spi->inten = 0; int_en = 0; - MXC_FreeLock((uint32_t*) &states[spi_num].req); - + MXC_FreeLock((uint32_t *)&states[spi_num].req); + // Callback if not NULL - if (async && req->completeCB != NULL) { + if (states[spi_num].async && req->completeCB != NULL) { req->completeCB(req, E_NO_ERROR); } } } // Break out once we've transmitted and received all of the data - if ((req->rxCnt == rx_length) && (req->txCnt == tx_length)) { + if ((req->rxCnt == rx_length) && (req->txCnt == tx_length)) { spi->inten = 0; int_en = 0; - MXC_FreeLock((uint32_t*) &states[spi_num].req); - + MXC_FreeLock((uint32_t *)&states[spi_num].req); + // Callback if not NULL - if (async && req->completeCB != NULL) { + if (states[spi_num].async && req->completeCB != NULL) { req->completeCB(req, E_NO_ERROR); } } - + return int_en; } -int MXC_SPI_RevA_MasterTransaction (mxc_spi_reva_req_t* req) +int MXC_SPI_RevA_MasterTransaction(mxc_spi_reva_req_t *req) { int error; - + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - - async = 0; - + + states[MXC_SPI_GET_IDX((mxc_spi_regs_t *)req->spi)].async = 0; + //call master transHandler - while (MXC_SPI_RevA_MasterTransHandler(req->spi, req) != 0); - - while (!((req->spi)->intfl & MXC_F_SPI_REVA_INTFL_MST_DONE)); - + while (MXC_SPI_RevA_MasterTransHandler(req->spi, req) != 0) {} + + while (!((req->spi)->intfl & MXC_F_SPI_REVA_INTFL_MST_DONE)) {} + return E_NO_ERROR; } -int MXC_SPI_RevA_MasterTransactionAsync (mxc_spi_reva_req_t* req) +int MXC_SPI_RevA_MasterTransactionAsync(mxc_spi_reva_req_t *req) { int error; - + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - - async = 1; - - MXC_SPI_EnableInt ((mxc_spi_regs_t*) req->spi, MXC_SPI_RevA_MasterTransHandler (req->spi,req)); - + + states[MXC_SPI_GET_IDX((mxc_spi_regs_t *)req->spi)].async = 1; + + MXC_SPI_EnableInt((mxc_spi_regs_t *)req->spi, MXC_SPI_RevA_MasterTransHandler(req->spi, req)); + return E_NO_ERROR; } -int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma) +int MXC_SPI_RevA_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx, + mxc_dma_regs_t *dma) { int spi_num; - uint8_t channel,error,bits; + uint8_t error, bits; mxc_dma_config_t config; mxc_dma_srcdst_t srcdst; - mxc_dma_adv_config_t advConfig = {0, 0, 0, 0, 0, 0}; + mxc_dma_adv_config_t advConfig = { 0, 0, 0, 0, 0, 0 }; - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*)(req->spi)); - MXC_ASSERT (spi_num >= 0); + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)(req->spi)); + MXC_ASSERT(spi_num >= 0); if (req->txData == NULL && req->rxData == NULL) { return E_BAD_PARAM; } - if ((error = MXC_SPI_RevA_TransSetup (req)) != E_NO_ERROR) { + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - // Leave slave select asserted at the end of the transaction - if (!req->ssDeassert) { - req->spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + // for non-MT mode do this setup every time, for MT mode only first time + if ((states[spi_num].mtMode == 0) || + ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { +#if TARGET_NUM == 32665 + MXC_DMA_Init(dma); + states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); + states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); +#else + MXC_DMA_Init(); + states[spi_num].channelTx = MXC_DMA_AcquireChannel(); + states[spi_num].channelRx = MXC_DMA_AcquireChannel(); +#endif + + if ((states[spi_num].channelTx < 0) || (states[spi_num].channelRx < 0)) { + states[spi_num].channelTx = E_NO_DEVICE; + states[spi_num].channelRx = E_NO_DEVICE; + return E_NO_DEVICE; + } + + states[spi_num].mtFirstTrans = 0; + + MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA_DMACallback); + MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA_DMACallback); + MXC_DMA_EnableInt(states[spi_num].channelTx); + MXC_DMA_EnableInt(states[spi_num].channelRx); + + // Configure SS for per-transaction or always on + if (req->ssDeassert) { + req->spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } else { + req->spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } } - - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); - + + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); + MXC_SPI_RevA_TransHandler(req->spi, req); - + if (bits <= 8) { - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 1); //set threshold to 1 byte - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); //set threshold to 0 bytes + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)req->spi, 1); //set threshold to 1 byte + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)req->spi, 0); //set threshold to 0 bytes + } else { + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)req->spi, 2); + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)req->spi, 0); } - else { - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 2); - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); - } - - #if TARGET_NUM == 32665 - MXC_DMA_Init(dma); - #else - MXC_DMA_Init(); - #endif - + //tx if (req->txData != NULL) { - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel(dma); - #else - channel = MXC_DMA_AcquireChannel(); - #endif - config.reqsel = reqselTx; - config.ch = channel; - advConfig.ch = channel; + config.ch = states[spi_num].channelTx; + advConfig.ch = states[spi_num].channelTx; advConfig.burst_size = 2; - + if (bits <= 8) { config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - } - else { + } else { config.srcwd = MXC_DMA_WIDTH_HALFWORD; config.dstwd = MXC_DMA_WIDTH_HALFWORD; } - + config.srcinc_en = 1; config.dstinc_en = 0; - - srcdst.ch = channel; - srcdst.source = & (req->txData[req->txCnt]); - + + srcdst.ch = states[spi_num].channelTx; + srcdst.source = &(req->txData[req->txCnt]); + if (bits > 8) { srcdst.len = (req->txLen * 2) - req->txCnt; - } - else { + } else { srcdst.len = (req->txLen) - req->txCnt; } - - states[spi_num].channelTx = channel; - MXC_DMA_ConfigChannel (config,srcdst); - MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); - MXC_DMA_SetChannelInterruptEn(channel, false, true); + + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_Start(states[spi_num].channelTx); + MXC_DMA_SetChannelInterruptEn(states[spi_num].channelTx, false, true); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; if (bits > 8) { @@ -1022,334 +1088,313 @@ //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 1 << MXC_F_DMA_CTRL_BURST_SIZE_POS); } } - - if (req->rxData != NULL) { - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel(dma); - #else - channel = MXC_DMA_AcquireChannel(); - #endif + if (req->rxData != NULL) { config.reqsel = reqselRx; - config.ch = channel; + config.ch = states[spi_num].channelRx; config.srcinc_en = 0; config.dstinc_en = 1; - advConfig.ch = channel; + advConfig.ch = states[spi_num].channelRx; advConfig.burst_size = 1; - + if (bits <= 8) { config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - } - else { + } else { config.srcwd = MXC_DMA_WIDTH_HALFWORD; config.dstwd = MXC_DMA_WIDTH_HALFWORD; } - - - srcdst.ch = channel; + + srcdst.ch = states[spi_num].channelRx; srcdst.dest = req->rxData; - + if (bits <= 8) { srcdst.len = req->rxLen; - } - else { + } else { srcdst.len = req->rxLen * 2; } - - states[spi_num].channelRx = channel; - - MXC_DMA_ConfigChannel (config,srcdst); - MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); - MXC_DMA_SetChannelInterruptEn(channel, false, true); + + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_Start(states[spi_num].channelRx); + MXC_DMA_SetChannelInterruptEn(states[spi_num].channelRx, false, true); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; if (bits > 8) { MXC_DMA_AdvConfigChannel(advConfig); //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 0 << MXC_F_DMA_CTRL_BURST_SIZE_POS); } - } - + (req->spi)->dma |= (MXC_F_SPI_REVA_DMA_DMA_TX_EN | MXC_F_SPI_REVA_DMA_DMA_RX_EN); - - + if (!states[spi_num].started) { - MXC_SPI_StartTransmission ((mxc_spi_regs_t*) req->spi); + MXC_SPI_StartTransmission((mxc_spi_regs_t *)req->spi); states[spi_num].started = 1; } - - // Deassert slave select at the end of the transaction - if (req->ssDeassert) { - req->spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; - } - + return E_NO_ERROR; } -int MXC_SPI_RevA_SlaveTransaction (mxc_spi_reva_req_t* req) +int MXC_SPI_RevA_SlaveTransaction(mxc_spi_reva_req_t *req) { int error; - + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - - - async = 0; - - while (MXC_SPI_RevA_SlaveTransHandler(req) != 0); - + + states[MXC_SPI_GET_IDX((mxc_spi_regs_t *)req->spi)].async = 0; + + while (MXC_SPI_RevA_SlaveTransHandler(req) != 0) {} + return E_NO_ERROR; } -int MXC_SPI_RevA_SlaveTransactionAsync (mxc_spi_reva_req_t* req) +int MXC_SPI_RevA_SlaveTransactionAsync(mxc_spi_reva_req_t *req) { int error; - + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - - async = 1; - - MXC_SPI_EnableInt ((mxc_spi_regs_t*) req->spi,MXC_SPI_RevA_SlaveTransHandler (req)); - + + states[MXC_SPI_GET_IDX((mxc_spi_regs_t *)req->spi)].async = 1; + + MXC_SPI_EnableInt((mxc_spi_regs_t *)req->spi, MXC_SPI_RevA_SlaveTransHandler(req)); + return E_NO_ERROR; } -int MXC_SPI_RevA_SlaveTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma) +int MXC_SPI_RevA_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx, + mxc_dma_regs_t *dma) { int spi_num; - uint8_t channel, error, bits; + uint8_t error, bits; mxc_dma_config_t config; mxc_dma_srcdst_t srcdst; - mxc_dma_adv_config_t advConfig = {0, 0, 0, 0, 0, 0}; - + mxc_dma_adv_config_t advConfig = { 0, 0, 0, 0, 0, 0 }; + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)(req->spi)); + MXC_ASSERT(spi_num >= 0); + if (req->txData == NULL && req->rxData == NULL) { return E_BAD_PARAM; } - + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { return error; } - - bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); - + + // for non-MT mode do this setup every time, for MT mode only first time + if ((states[spi_num].mtMode == 0) || + ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { +#if TARGET_NUM == 32665 + MXC_DMA_Init(dma); + states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); + states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); +#else + MXC_DMA_Init(); + states[spi_num].channelTx = MXC_DMA_AcquireChannel(); + states[spi_num].channelRx = MXC_DMA_AcquireChannel(); +#endif + + if ((states[spi_num].channelTx < 0) || (states[spi_num].channelRx < 0)) { + states[spi_num].channelTx = E_NO_DEVICE; + states[spi_num].channelRx = E_NO_DEVICE; + return E_NO_DEVICE; + } + + states[spi_num].mtFirstTrans = 0; + + MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA_DMACallback); + MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA_DMACallback); + MXC_DMA_EnableInt(states[spi_num].channelTx); + MXC_DMA_EnableInt(states[spi_num].channelRx); + } + + bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); + MXC_SPI_RevA_TransHandler(req->spi, req); - + if (bits <= 8) { - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 1); - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)req->spi, 1); + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)req->spi, 0); + } else { + MXC_SPI_SetTXThreshold((mxc_spi_regs_t *)req->spi, 2); + MXC_SPI_SetRXThreshold((mxc_spi_regs_t *)req->spi, 0); } - else { - - MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 2); - MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); - } - - #if TARGET_NUM == 32665 - MXC_DMA_Init(dma); - #else - MXC_DMA_Init(); - #endif - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*)(req->spi)); - MXC_ASSERT (spi_num >= 0); - + //tx if (req->txData != NULL) { - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel(dma); - #else - channel = MXC_DMA_AcquireChannel(); - #endif - config.reqsel = reqselTx; - config.ch = channel; - advConfig.ch = channel; + config.ch = states[spi_num].channelTx; + advConfig.ch = states[spi_num].channelTx; advConfig.burst_size = 2; - + if (bits <= 8) { config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - } - else { + } else { config.srcwd = MXC_DMA_WIDTH_HALFWORD; config.dstwd = MXC_DMA_WIDTH_HALFWORD; } - + config.srcinc_en = 1; config.dstinc_en = 0; - - srcdst.ch = channel; - srcdst.source = & (req->txData[req->txCnt]); - + + srcdst.ch = states[spi_num].channelTx; + srcdst.source = &(req->txData[req->txCnt]); + if (bits > 8) { srcdst.len = (req->txLen * 2) - req->txCnt; - } - else { + } else { srcdst.len = (req->txLen) - req->txCnt; } - - states[spi_num].channelTx = channel; - - MXC_DMA_ConfigChannel (config,srcdst); - MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); - MXC_DMA_SetChannelInterruptEn(channel, false, true); + + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_Start(states[spi_num].channelTx); + MXC_DMA_SetChannelInterruptEn(states[spi_num].channelTx, false, true); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; - + if (bits > 8) { MXC_DMA_AdvConfigChannel(advConfig); //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 1 << MXC_F_DMA_CTRL_BURST_SIZE_POS); } } - - if (req->rxData != NULL) { - #if TARGET_NUM == 32665 - channel = MXC_DMA_AcquireChannel(dma); - #else - channel = MXC_DMA_AcquireChannel(); - #endif + if (req->rxData != NULL) { config.reqsel = reqselRx; - config.ch = channel; + config.ch = states[spi_num].channelRx; config.srcinc_en = 0; config.dstinc_en = 1; - advConfig.ch = channel; + advConfig.ch = states[spi_num].channelRx; advConfig.burst_size = 1; - + if (bits <= 8) { config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - } - else { + } else { config.srcwd = MXC_DMA_WIDTH_HALFWORD; config.dstwd = MXC_DMA_WIDTH_HALFWORD; } - - - srcdst.ch = channel; + + srcdst.ch = states[spi_num].channelRx; srcdst.dest = req->rxData; - + if (bits <= 8) { srcdst.len = req->rxLen; - } - else { + } else { srcdst.len = req->rxLen * 2; } - - states[spi_num].channelRx = channel; - - MXC_DMA_ConfigChannel (config,srcdst); - MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); - MXC_DMA_SetChannelInterruptEn(channel, false, true); + + MXC_DMA_ConfigChannel(config, srcdst); + MXC_DMA_Start(states[spi_num].channelRx); + MXC_DMA_SetChannelInterruptEn(states[spi_num].channelRx, false, true); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; - + if (bits > 8) { MXC_DMA_AdvConfigChannel(advConfig); //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 0 << MXC_F_DMA_CTRL_BURST_SIZE_POS); } } - + (req->spi)->dma |= (MXC_F_SPI_REVA_DMA_DMA_TX_EN | MXC_F_SPI_REVA_DMA_DMA_RX_EN); - + return E_NO_ERROR; } void MXC_SPI_RevA_DMACallback(int ch, int error) { - mxc_spi_reva_req_t * temp_req; - - for (int i = 0; i < MXC_SPI_INSTANCES; i ++) { - if(states[i].req != NULL) { - if (states[i].channelTx == ch) { - states[i].req_done++; - } + mxc_spi_reva_req_t *temp_req; - else if (states[i].channelRx == ch) { + for (int i = 0; i < MXC_SPI_INSTANCES; i++) { + if (states[i].req != NULL) { + if (states[i].channelTx == ch) { states[i].req_done++; - //save the request - temp_req = states[i].req; - - if (MXC_SPI_GetDataSize ((mxc_spi_regs_t*) temp_req->spi) > 8) { - MXC_SPI_RevA_SwapByte (temp_req->rxData, temp_req->rxLen); - } - } - - if(!states[i].txrx_req || (states[i].txrx_req && states[i].req_done == 2)) { + } else if (states[i].channelRx == ch) { + states[i].req_done++; //save the request temp_req = states[i].req; - MXC_FreeLock((uint32_t*) &states[i].req); + + if (MXC_SPI_GetDataSize((mxc_spi_regs_t *)temp_req->spi) > 8) { + MXC_SPI_RevA_SwapByte(temp_req->rxData, temp_req->rxLen); + } + } + + if (!states[i].txrx_req || (states[i].txrx_req && states[i].req_done == 2)) { + //save the request + temp_req = states[i].req; + MXC_FreeLock((uint32_t *)&states[i].req); // Callback if not NULL if (temp_req->completeCB != NULL) { temp_req->completeCB(temp_req, E_NO_ERROR); } + if (states[i].mtMode == 0) { + // release any acquired DMA channels + if (states[i].channelTx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[i].channelTx); + states[i].channelTx = E_NO_DEVICE; + } + if (states[i].channelRx >= 0) { + MXC_DMA_RevA_ReleaseChannel(states[i].channelRx); + states[i].channelRx = E_NO_DEVICE; + } + } break; } - } + } } } -int MXC_SPI_RevA_SetDefaultTXData (mxc_spi_reva_regs_t* spi, unsigned int defaultTXData) +int MXC_SPI_RevA_SetDefaultTXData(mxc_spi_reva_regs_t *spi, unsigned int defaultTXData) { - int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - MXC_ASSERT (spi_num >= 0); + int spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + MXC_ASSERT(spi_num >= 0); states[spi_num].defaultTXData = defaultTXData; return E_NO_ERROR; } -void MXC_SPI_RevA_AbortAsync (mxc_spi_reva_regs_t* spi) +void MXC_SPI_RevA_AbortAsync(mxc_spi_reva_regs_t *spi) { - MXC_SPI_AbortTransmission ((mxc_spi_regs_t*) spi); + MXC_SPI_AbortTransmission((mxc_spi_regs_t *)spi); } -void MXC_SPI_RevA_AsyncHandler (mxc_spi_reva_regs_t* spi) +void MXC_SPI_RevA_AsyncHandler(mxc_spi_reva_regs_t *spi) { int spi_num; unsigned rx_avail; uint32_t flags; - + // Clear the interrupt flags spi->inten = 0; flags = spi->intfl; spi->intfl = flags; - - spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); - + + spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); + // Figure out if this SPI has an active request - if ( (states[spi_num].req != NULL) && (flags)) { - if ( (spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE) >> MXC_F_SPI_REVA_CTRL0_MST_MODE_POS) { + if ((states[spi_num].req != NULL) && (flags)) { + if ((spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE) >> MXC_F_SPI_REVA_CTRL0_MST_MODE_POS) { do { - spi->inten = MXC_SPI_RevA_MasterTransHandler(spi, states[spi_num].req); + spi->inten = MXC_SPI_RevA_MasterTransHandler(spi, states[spi_num].req); rx_avail = MXC_SPI_RevA_GetRXFIFOAvailable(spi); - } - while (rx_avail > MXC_SPI_RevA_GetRXThreshold(spi)); - - } - else { + } while (rx_avail > MXC_SPI_RevA_GetRXThreshold(spi)); + + } else { do { spi->inten = MXC_SPI_RevA_SlaveTransHandler(states[spi_num].req); rx_avail = MXC_SPI_RevA_GetRXFIFOAvailable(spi); - } - while (rx_avail > MXC_SPI_RevA_GetRXThreshold(spi)); - + } while (rx_avail > MXC_SPI_RevA_GetRXThreshold(spi)); } } } //call in DMA IRQHANDLER with rxData for transmissions with bits > 8 -void MXC_SPI_RevA_SwapByte(uint8_t* arr, size_t length) +void MXC_SPI_RevA_SwapByte(uint8_t *arr, size_t length) { MXC_ASSERT(arr != NULL); - - for (size_t i = 0 ; i < (length * 2); i+=2) { + + for (size_t i = 0; i < (length * 2); i += 2) { uint8_t tmp = arr[i]; arr[i] = arr[i + 1]; arr[i + 1] = tmp; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h index f2003ea..6f46c85 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_ #include #include @@ -44,6 +47,10 @@ #include "mxc_spi.h" #include "dma.h" +#ifdef __cplusplus +extern "C" { +#endif + typedef enum { SPI_REVA_WIDTH_3WIRE, SPI_REVA_WIDTH_STANDARD, @@ -52,7 +59,7 @@ } mxc_spi_reva_width_t; typedef enum { - SPI_REVA_MODE_0, + SPI_REVA_MODE_0, SPI_REVA_MODE_1, SPI_REVA_MODE_2, SPI_REVA_MODE_3, @@ -61,58 +68,68 @@ typedef struct _mxc_spi_reva_req_t mxc_spi_reva_req_t; struct _mxc_spi_reva_req_t { - mxc_spi_reva_regs_t* spi; - int ssIdx; - int ssDeassert; - uint8_t *txData; - uint8_t *rxData; - uint32_t txLen; - uint32_t rxLen; - uint32_t txCnt; - uint32_t rxCnt; - spi_complete_cb_t completeCB; + mxc_spi_reva_regs_t *spi; + int ssIdx; + int ssDeassert; + uint8_t *txData; + uint8_t *rxData; + uint32_t txLen; + uint32_t rxLen; + uint32_t txCnt; + uint32_t rxCnt; + spi_complete_cb_t completeCB; }; -int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz, unsigned drv_ssel); -int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz); -unsigned int MXC_SPI_RevA_GetFrequency (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetDataSize (mxc_spi_reva_regs_t* spi, int dataSize); -int MXC_SPI_RevA_GetDataSize (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx); -int MXC_SPI_RevA_GetSlave (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetWidth (mxc_spi_reva_regs_t* spi, mxc_spi_reva_width_t spiWidth); -mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetMode (mxc_spi_reva_regs_t* spi, mxc_spi_reva_mode_t spiMode); -mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_StartTransmission (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_GetActive (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_AbortTransmission (mxc_spi_reva_regs_t* spi); -unsigned int MXC_SPI_RevA_ReadRXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, +int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel); +int MXC_SPI_RevA_Shutdown(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_ReadyForSleep(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetFrequency(mxc_spi_reva_regs_t *spi, unsigned int hz); +unsigned int MXC_SPI_RevA_GetFrequency(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetDataSize(mxc_spi_reva_regs_t *spi, int dataSize); +int MXC_SPI_RevA_GetDataSize(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetMTMode(mxc_spi_reva_regs_t *spi, int mtMode); +int MXC_SPI_RevA_GetMTMode(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetSlave(mxc_spi_reva_regs_t *spi, int ssIdx); +int MXC_SPI_RevA_GetSlave(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetWidth(mxc_spi_reva_regs_t *spi, mxc_spi_reva_width_t spiWidth); +mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetMode(mxc_spi_reva_regs_t *spi, mxc_spi_reva_mode_t spiMode); +mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_StartTransmission(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_GetActive(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_AbortTransmission(mxc_spi_reva_regs_t *spi); +unsigned int MXC_SPI_RevA_ReadRXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes, + unsigned int len); +unsigned int MXC_SPI_RevA_WriteTXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes, unsigned int len); -unsigned int MXC_SPI_RevA_WriteTXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, - unsigned int len); -unsigned int MXC_SPI_RevA_GetTXFIFOAvailable (mxc_spi_reva_regs_t* spi); -unsigned int MXC_SPI_RevA_GetRXFIFOAvailable (mxc_spi_reva_regs_t* spi); -void MXC_SPI_RevA_ClearRXFIFO (mxc_spi_reva_regs_t* spi); -void MXC_SPI_RevA_ClearTXFIFO (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetRXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes); -unsigned int MXC_SPI_RevA_GetRXThreshold (mxc_spi_reva_regs_t* spi); -int MXC_SPI_RevA_SetTXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes); -unsigned int MXC_SPI_RevA_GetTXThreshold (mxc_spi_reva_regs_t* spi); -unsigned int MXC_SPI_RevA_GetFlags (mxc_spi_reva_regs_t* spi); -void MXC_SPI_RevA_ClearFlags (mxc_spi_reva_regs_t* spi); -void MXC_SPI_RevA_EnableInt (mxc_spi_reva_regs_t* spi, unsigned int mask); -void MXC_SPI_RevA_DisableInt (mxc_spi_reva_regs_t* spi, unsigned int mask); -int MXC_SPI_RevA_MasterTransaction (mxc_spi_reva_req_t* req); -int MXC_SPI_RevA_MasterTransactionAsync (mxc_spi_reva_req_t* req); -int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma); -int MXC_SPI_RevA_SlaveTransaction (mxc_spi_reva_req_t* req); -int MXC_SPI_RevA_SlaveTransactionAsync (mxc_spi_reva_req_t* req); -int MXC_SPI_RevA_SlaveTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma); -void MXC_SPI_RevA_DMACallback (int ch, int error); -int MXC_SPI_RevA_SetDefaultTXData (mxc_spi_reva_regs_t* spi, unsigned int defaultTXData); -void MXC_SPI_RevA_AbortAsync (mxc_spi_reva_regs_t* spi); -void MXC_SPI_RevA_AsyncHandler (mxc_spi_reva_regs_t* spi); +unsigned int MXC_SPI_RevA_GetTXFIFOAvailable(mxc_spi_reva_regs_t *spi); +unsigned int MXC_SPI_RevA_GetRXFIFOAvailable(mxc_spi_reva_regs_t *spi); +void MXC_SPI_RevA_ClearRXFIFO(mxc_spi_reva_regs_t *spi); +void MXC_SPI_RevA_ClearTXFIFO(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetRXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes); +unsigned int MXC_SPI_RevA_GetRXThreshold(mxc_spi_reva_regs_t *spi); +int MXC_SPI_RevA_SetTXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes); +unsigned int MXC_SPI_RevA_GetTXThreshold(mxc_spi_reva_regs_t *spi); +unsigned int MXC_SPI_RevA_GetFlags(mxc_spi_reva_regs_t *spi); +void MXC_SPI_RevA_ClearFlags(mxc_spi_reva_regs_t *spi); +void MXC_SPI_RevA_EnableInt(mxc_spi_reva_regs_t *spi, unsigned int mask); +void MXC_SPI_RevA_DisableInt(mxc_spi_reva_regs_t *spi, unsigned int mask); +int MXC_SPI_RevA_MasterTransaction(mxc_spi_reva_req_t *req); +int MXC_SPI_RevA_MasterTransactionAsync(mxc_spi_reva_req_t *req); +int MXC_SPI_RevA_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx, + mxc_dma_regs_t *dma); +int MXC_SPI_RevA_SlaveTransaction(mxc_spi_reva_req_t *req); +int MXC_SPI_RevA_SlaveTransactionAsync(mxc_spi_reva_req_t *req); +int MXC_SPI_RevA_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx, + mxc_dma_regs_t *dma); +void MXC_SPI_RevA_DMACallback(int ch, int error); +int MXC_SPI_RevA_SetDefaultTXData(mxc_spi_reva_regs_t *spi, unsigned int defaultTXData); +void MXC_SPI_RevA_AbortAsync(mxc_spi_reva_regs_t *spi); +void MXC_SPI_RevA_AsyncHandler(mxc_spi_reva_regs_t *spi); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h index 8c4da3f..0601b8c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _SPI_REVA_REGS_H_ #define _SPI_REVA_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c index 79ced96..f356cc6 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,8 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" @@ -42,7 +41,7 @@ /* **** Functions **** */ /* ************************************************************************** */ -__weak void mxc_assert(const char* expr, const char* file, int line) +__weak void mxc_assert(const char *expr, const char *file, int line) { while (1) {} } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c index 299e2d1..df60f7e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,8 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -41,7 +40,7 @@ #ifdef __riscv -int MXC_Delay(unsigned long us) +int MXC_Delay(uint32_t us) { // Check if there is nothing to do if (us == 0) { @@ -51,18 +50,18 @@ // Calculate number of cycles needed. uint32_t ticks = (MXC_SYS_RiscVClockRate() / 1000000) * us; - CSR_SetPCMR(0); // Turn off counter - CSR_SetPCCR(0); // Clear counter register - CSR_SetPCER(1); // Enable counting of cycles - CSR_SetPCMR(3); // Turn on counter + CSR_SetPCMR(0); // Turn off counter + CSR_SetPCCR(0); // Clear counter register + CSR_SetPCER(1); // Enable counting of cycles + CSR_SetPCMR(3); // Turn on counter - while(CSR_GetPCCR() < ticks) { + while (CSR_GetPCCR() < ticks) { // Wait for counter to reach the tick count. } return E_NO_ERROR; } -int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback) +int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback) { return E_NOT_SUPPORTED; } @@ -72,9 +71,7 @@ return E_NOT_SUPPORTED; } -void MXC_DelayAbort(void) -{ -} +void MXC_DelayAbort(void) {} #else @@ -84,7 +81,7 @@ static uint32_t ctrl_save; static mxc_delay_complete_t cbFunc; -static void MXC_DelayInit(unsigned long us); +static void MXC_DelayInit(uint32_t us); extern void SysTick_Handler(void); /* ************************************************************************** */ @@ -101,10 +98,9 @@ // Decrement overflow flag if delay is still ongoing if (overflows > 0) { overflows--; - } - else { + } else { MXC_DelayAbort(); - + if (cbFunc != NULL) { cbFunc(E_NO_ERROR); cbFunc = NULL; @@ -114,16 +110,16 @@ } /* ************************************************************************** */ -static void MXC_DelayInit(unsigned long us) +static void MXC_DelayInit(uint32_t us) { uint32_t starttick, reload, ticks, lastticks; - + // Record the current tick value and clear the overflow flag starttick = SysTick->VAL; - + // Save the state of control register (and clear the overflow flag) ctrl_save = SysTick->CTRL & ~SysTick_CTRL_COUNTFLAG_Msk; - + // If the SysTick is not running, configure and start it if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { SysTick->LOAD = SysTick_LOAD_RELOAD_Msk; @@ -131,53 +127,51 @@ SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; starttick = SysTick_VAL_CURRENT_Msk; reload = SysTick_LOAD_RELOAD_Msk + 1; - } - else { + } else { reload = SysTick->LOAD + 1; // get the current reload value } - + // Calculate the total number of ticks to delay - ticks = (uint32_t)(((uint64_t) us * (uint64_t) SystemCoreClock) / 1000000); - + ticks = (uint32_t)(((uint64_t)us * (uint64_t)SystemCoreClock) / 1000000); + // How many overflows of the SysTick will occur overflows = ticks / reload; - + // How many remaining ticks after the last overflow lastticks = ticks % reload; - + // Check if there will be another overflow due to the current value of the SysTick if (lastticks >= starttick) { overflows++; endtick = reload - (lastticks - starttick); - } - else { + } else { endtick = starttick - lastticks; } } /* ************************************************************************** */ -int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback) +int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback) { cbFunc = callback; - + // Check if timeout currently ongoing if (overflows > 0) { return E_BUSY; } - + // Check if there is nothing to do if (us == 0) { return E_NO_ERROR; } - + // Calculate the necessary delay and start the timer MXC_DelayInit(us); - + // Enable SysTick interrupt if necessary if (overflows > 0) { SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; } - + return E_NO_ERROR; } @@ -190,22 +184,22 @@ cbFunc(E_NO_ERROR); cbFunc = NULL; } - + return E_NO_ERROR; } - + // Check the global values if ((overflows == 0) && (SysTick->VAL <= endtick)) { MXC_DelayAbort(); - + if (cbFunc != NULL) { cbFunc(E_NO_ERROR); cbFunc = NULL; } - + return E_NO_ERROR; } - + return E_BUSY; } @@ -216,27 +210,27 @@ cbFunc(E_ABORT); cbFunc = NULL; } - + SysTick->CTRL = ctrl_save; overflows = -1; } /* ************************************************************************** */ -int MXC_Delay(unsigned long us) +int MXC_Delay(uint32_t us) { // Check if timeout currently ongoing if (overflows > 0) { return E_BUSY; } - + // Check if there is nothing to do if (us == 0) { return E_NO_ERROR; } - + // Calculate the necessary delay and start the timer MXC_DelayInit(us); - + // Wait for the number of overflows while (overflows > 0) { // If SysTick interrupts are enabled, COUNTFLAG will never be set here and @@ -246,12 +240,12 @@ overflows--; } } - + // Wait for the counter value - while (SysTick->VAL > endtick); - + while (SysTick->VAL > endtick) {} + MXC_DelayAbort(); return E_NO_ERROR; } -#endif // __riscv \ No newline at end of file +#endif // __riscv diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c index 51c73bc..a28121d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,8 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" @@ -40,27 +39,25 @@ #ifndef __riscv /* ************************************************************************** */ -int MXC_GetLock(uint32_t* lock, uint32_t value) +int MXC_GetLock(uint32_t *lock, uint32_t value) { do { - // Return if the lock is taken by a different thread - if (__LDREXW((volatile unsigned long*) lock) != 0) { + if (__LDREXW((volatile uint32_t *)lock) != 0) { return E_BUSY; } - + // Attempt to take the lock - } - while (__STREXW(value, (volatile unsigned long*) lock) != 0); - + } while (__STREXW(value, (volatile uint32_t *)lock) != 0); + // Do not start any other memory access until memory barrier is complete __DMB(); - + return E_NO_ERROR; } /* ************************************************************************** */ -void MXC_FreeLock(uint32_t* lock) +void MXC_FreeLock(uint32_t *lock) { // Ensure memory operations complete before releasing lock __DMB(); @@ -68,16 +65,16 @@ } #else // __riscv /* ************************************************************************** */ -int MXC_GetLock(uint32_t* lock, uint32_t value) -{ - #warning "Unimplemented for RISCV" +int MXC_GetLock(uint32_t *lock, uint32_t value) +{ +#warning "Unimplemented for RISCV" return E_NO_ERROR; } /* ************************************************************************** */ -void MXC_FreeLock(uint32_t* lock) +void MXC_FreeLock(uint32_t *lock) { - #warning "Unimplemented for RISCV" +#warning "Unimplemented for RISCV" } #endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/pins_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/pins_me15.c index 97cec01..e2d09f3 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/pins_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/pins_me15.c @@ -3,8 +3,8 @@ * @brief This file contains constant pin configurations for the peripherals. */ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - **************************************************************************** */ + ******************************************************************************/ #include "gpio.h" #include "mxc_device.h" @@ -43,11 +42,20 @@ /***** Definitions *****/ /***** Global Variables *****/ -const mxc_gpio_cfg_t gpio_cfg_extclk = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_lpextclk = { MXC_GPIO0, (MXC_GPIO_PIN_12), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_hfextclk = { MXC_GPIO0, (MXC_GPIO_PIN_12), MXC_GPIO_FUNC_ALT4, + MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO}; -const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO}; -const mxc_gpio_cfg_t gpio_cfg_i2c2 = { MXC_GPIO0, (MXC_GPIO_PIN_18 | MXC_GPIO_PIN_19), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO}; +const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_VSSEL_VDDIO }; +const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_VSSEL_VDDIO }; +const mxc_gpio_cfg_t gpio_cfg_i2c2 = { MXC_GPIO0, (MXC_GPIO_PIN_18 | MXC_GPIO_PIN_19), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_VSSEL_VDDIO }; const mxc_gpio_cfg_t gpio_cfg_uart0a = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; const mxc_gpio_cfg_t gpio_cfg_uart0a_flow = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; @@ -72,35 +80,70 @@ const mxc_gpio_cfg_t gpio_cfg_uart3_flow = { MXC_GPIO0, (MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_i2s0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9 | MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_i2s0 = { + MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9 | MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE +}; -const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, (MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi0 = { + MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE +}; +const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, MXC_GPIO_PIN_5, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; + // NOTE: SPI1 definied here with SS0 only -const mxc_gpio_cfg_t gpio_cfg_spi1 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_spi1_ss = { MXC_GPIO0, (MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi1 = { + MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE +}; +const mxc_gpio_cfg_t gpio_cfg_spi1_ss = { MXC_GPIO0, MXC_GPIO_PIN_17, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; + // NOTE: SPI2 defined here with SS0 only, and NOT SS1 and SS2 -const mxc_gpio_cfg_t gpio_cfg_spi2 = { MXC_GPIO1, (MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_spi2_ss = { MXC_GPIO1, (MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi2 = { + MXC_GPIO1, (MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE +}; +const mxc_gpio_cfg_t gpio_cfg_spi2_ss = { MXC_GPIO1, MXC_GPIO_PIN_4, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; // Timers are only defined once, depending on package, each timer could be mapped to other pins -const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO}; -const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO}; -const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO}; -const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO}; -const mxc_gpio_cfg_t gpio_cfg_tmr4 = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO}; -const mxc_gpio_cfg_t gpio_cfg_tmr5 = { MXC_GPIO0, (MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO}; +const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), + MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, + MXC_GPIO_VSSEL_VDDIO }; +const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), + MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, + MXC_GPIO_VSSEL_VDDIO }; +const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), + MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, + MXC_GPIO_VSSEL_VDDIO }; +const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), + MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, + MXC_GPIO_VSSEL_VDDIO }; +const mxc_gpio_cfg_t gpio_cfg_tmr4 = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, + MXC_GPIO_VSSEL_VDDIO }; +const mxc_gpio_cfg_t gpio_cfg_tmr5 = { MXC_GPIO0, (MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, + MXC_GPIO_VSSEL_VDDIO }; -const mxc_gpio_cfg_t gpio_cfg_rtcsqw = { MXC_GPIO0, MXC_GPIO_PIN_8, MXC_GPIO_FUNC_ALT4, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_rtcsqwb = { MXC_GPIO1, MXC_GPIO_PIN_11, MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_rtcsqw = { MXC_GPIO0, MXC_GPIO_PIN_8, MXC_GPIO_FUNC_ALT4, + MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_rtcsqwb = { MXC_GPIO1, MXC_GPIO_PIN_11, MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_lc1 = { MXC_GPIO1, MXC_GPIO_PIN_9, MXC_GPIO_FUNC_ALT4, + MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_mon_lc1 = { MXC_GPIO1, MXC_GPIO_PIN_10, MXC_GPIO_FUNC_ALT4, + MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc1 = { MXC_GPIO1, MXC_GPIO_PIN_11, MXC_GPIO_FUNC_ALT4, + MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_chrg_lc1 = { MXC_GPIO1, MXC_GPIO_PIN_12, MXC_GPIO_FUNC_ALT4, + MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_lc1 = { MXC_GPIO1, MXC_GPIO_PIN_9, MXC_GPIO_FUNC_ALT4, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_mon_lc1 = { MXC_GPIO1, MXC_GPIO_PIN_10, MXC_GPIO_FUNC_ALT4, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc1 = { MXC_GPIO1, MXC_GPIO_PIN_11, MXC_GPIO_FUNC_ALT4, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_chrg_lc1 = { MXC_GPIO1, MXC_GPIO_PIN_12, MXC_GPIO_FUNC_ALT4, MXC_GPIO_PAD_NONE }; - -const mxc_gpio_cfg_t gpio_cfg_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_31, MXC_GPIO_FUNC_ALT4, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_mon_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_19, MXC_GPIO_FUNC_ALT4, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_18, MXC_GPIO_FUNC_ALT4, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_chrg_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_17, MXC_GPIO_FUNC_ALT4, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_31, MXC_GPIO_FUNC_ALT4, + MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_mon_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_19, MXC_GPIO_FUNC_ALT4, + MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_18, MXC_GPIO_FUNC_ALT4, + MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_chrg_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_17, MXC_GPIO_FUNC_ALT4, + MXC_GPIO_PAD_NONE }; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/sys_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/sys_me15.c index c224062..71a4586 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/sys_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/sys_me15.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,8 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ /** * @file mxc_sys.c @@ -45,11 +44,12 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "mxc_delay.h" -#include "mxc_aes.h" +#include "aes.h" #include "flc.h" #include "gcr_regs.h" #include "fcr_regs.h" #include "mcr_regs.h" +#include "pwrseq_regs.h" /** * @ingroup mxc_sys @@ -57,8 +57,13 @@ */ /* **** Definitions **** */ -#define MXC_SYS_CLOCK_TIMEOUT MSEC(1) -#define MXC_SYS_ERFO_TIMEOUT MSEC(100) +#define MXC_SYS_CLOCK_TIMEOUT MSEC(1) +#define MXC_SYS_ERFO_TIMEOUT MSEC(100) + +// MAX32670 RevB updates may conflict with other parts dependent on RevA version (e.g. MAX32675) +#if TARGET_NUM != 32670 +#define MXC_SYS_RESET_RTC MXC_SYS_RESET0_RTC +#endif /* **** Globals **** */ @@ -67,61 +72,31 @@ /* ************************************************************************** */ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) { - uint32_t *infoblock = (uint32_t*)MXC_INFO0_MEM_BASE; + uint32_t *infoblock = (uint32_t *)MXC_INFO0_MEM_BASE; /* Read the USN from the info block */ MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); - usn[0] = (infoblock[0] & 0x007F8000) >> 15; - usn[1] = (infoblock[0] & 0x7F800000) >> 23; - usn[2] = (infoblock[1] & 0x0000007F) << 1; + usn[0] = (infoblock[0] & 0x007F8000) >> 15; + usn[1] = (infoblock[0] & 0x7F800000) >> 23; + usn[2] = (infoblock[1] & 0x0000007F) << 1; usn[2] |= (infoblock[0] & 0x80000000) >> 31; - usn[3] = (infoblock[1] & 0x00007F80) >> 7; - usn[4] = (infoblock[1] & 0x007F8000) >> 15; - usn[5] = (infoblock[1] & 0x7F800000) >> 23; - usn[6] = (infoblock[2] & 0x007F8000) >> 15; - usn[7] = (infoblock[2] & 0x7F800000) >> 23; - usn[8] = (infoblock[3] & 0x0000007F) << 1; + usn[3] = (infoblock[1] & 0x00007F80) >> 7; + usn[4] = (infoblock[1] & 0x007F8000) >> 15; + usn[5] = (infoblock[1] & 0x7F800000) >> 23; + usn[6] = (infoblock[2] & 0x007F8000) >> 15; + usn[7] = (infoblock[2] & 0x7F800000) >> 23; + usn[8] = (infoblock[3] & 0x0000007F) << 1; usn[8] |= (infoblock[2] & 0x80000000) >> 31; - usn[9] = (infoblock[3] & 0x00007F80) >> 7; + usn[9] = (infoblock[3] & 0x00007F80) >> 7; usn[10] = (infoblock[3] & 0x007F8000) >> 15; - // Compute the checksum - if(checksum != NULL) { - uint8_t info_checksum[2]; - uint8_t key[MXC_SYS_USN_CHECKSUM_LEN]; - - /* Initialize the remainder of the USN and key */ - memset(key, 0, MXC_SYS_USN_CHECKSUM_LEN); - memset(checksum, 0, MXC_SYS_USN_CHECKSUM_LEN); - - /* Read the checksum from the info block */ - info_checksum[0] = ((infoblock[3] & 0x7F800000) >> 23); - info_checksum[1] = ((infoblock[4] & 0x007F8000) >> 15); - - /* Setup the encryption parameters */ - MXC_AES_Init(); - - mxc_aes_req_t aesReq; - aesReq.length = MXC_SYS_USN_CHECKSUM_LEN/4; - aesReq.inputData = (uint32_t*)usn; - aesReq.resultData = (uint32_t*)checksum; - aesReq.keySize = MXC_AES_128BITS; - aesReq.encryption = MXC_AES_ENCRYPT_EXT_KEY; - - MXC_AES_SetExtKey(key, MXC_AES_128BITS); - MXC_AES_Encrypt(&aesReq); - MXC_AES_Shutdown(); - - /* Verify the checksum */ - if((checksum[1] != info_checksum[0]) || - (checksum[0] != info_checksum[1])) { - - MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); - return E_UNKNOWN; - } + /* If requested, return the checksum */ + if (checksum != NULL) { + checksum[0] = ((infoblock[3] & 0x7F800000) >> 23); + checksum[1] = ((infoblock[4] & 0x007F8000) >> 15); } /* Add the info block checksum to the USN */ @@ -140,12 +115,10 @@ if (clock > 63) { clock -= 64; return !(MXC_MCR->clkdis & (0x1 << clock)); - } - else if (clock > 31) { + } else if (clock > 31) { clock -= 32; return !(MXC_GCR->pclkdis1 & (0x1 << clock)); - } - else { + } else { return !(MXC_GCR->pclkdis0 & (0x1 << clock)); } } @@ -157,12 +130,10 @@ if (clock > 63) { clock -= 64; MXC_MCR->clkdis |= (0x1 << clock); - } - else if (clock > 31) { + } else if (clock > 31) { clock -= 32; MXC_GCR->pclkdis1 |= (0x1 << clock); - } - else { + } else { MXC_GCR->pclkdis0 |= (0x1 << clock); } } @@ -174,19 +145,18 @@ if (clock > 63) { clock -= 64; MXC_MCR->clkdis &= ~(0x1 << clock); - } - else if (clock > 31) { + } else if (clock > 31) { clock -= 32; MXC_GCR->pclkdis1 &= ~(0x1 << clock); - } - else { + } else { MXC_GCR->pclkdis0 &= ~(0x1 << clock); } } /* ************************************************************************** */ void MXC_SYS_RTCClockEnable() { - MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; + MXC_PWRSEQ->lpcn &= ~(MXC_F_PWRSEQ_LPCN_ERTCO_PD); // For Rev B parts + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; // For Rev A parts } /* ************************************************************************** */ @@ -195,9 +165,9 @@ /* Check that the RTC is not the system clock source */ if ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) != MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO) { MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_ERTCO_EN; + MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_ERTCO_PD; return E_NO_ERROR; - } - else { + } else { return E_BAD_STATE; } } @@ -210,33 +180,33 @@ MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IPO_EN; return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IPO_RDY); break; - + case MXC_SYS_CLOCK_IBRO: MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IBRO_EN; return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IBRO_RDY); break; - + case MXC_SYS_CLOCK_EXTCLK: // MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_EXTCLK_EN; // return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY); return E_NOT_SUPPORTED; break; - + case MXC_SYS_CLOCK_INRO: - // The 80k clock is always enabled + MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_INRO_EN; return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_INRO_RDY); break; - + case MXC_SYS_CLOCK_ERFO: MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERFO_RDY); break; - + case MXC_SYS_CLOCK_ERTCO: - MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; + MXC_SYS_RTCClockEnable(); return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERTCO_RDY); break; - + default: return E_BAD_PARAM; break; @@ -247,43 +217,42 @@ int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock) { uint32_t current_clock; - + current_clock = MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL; - + // Don't turn off the clock we're running on if (clock == current_clock) { return E_BAD_PARAM; } - + switch (clock) { case MXC_SYS_CLOCK_IPO: MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_IPO_EN; break; - + case MXC_SYS_CLOCK_IBRO: MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_IBRO_EN; break; - + case MXC_SYS_CLOCK_EXTCLK: // MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_EXTCLK_EN; break; - + case MXC_SYS_CLOCK_INRO: - // The 80k clock is always enabled + // The 80k clock can't be disabled through software. break; - + case MXC_SYS_CLOCK_ERFO: MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_ERFO_EN; break; - + case MXC_SYS_CLOCK_ERTCO: - MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_ERTCO_EN; - break; - + return MXC_SYS_RTCClockDisable(); + default: return E_BAD_PARAM; } - + return E_NO_ERROR; } @@ -291,7 +260,7 @@ int MXC_SYS_Clock_Timeout(uint32_t ready) { // Start timeout, wait for ready - if(ready == MXC_F_GCR_CLKCTRL_ERFO_RDY) { + if (ready == MXC_F_GCR_CLKCTRL_ERFO_RDY) { MXC_DelayAsync(MXC_SYS_ERFO_TIMEOUT, NULL); } else { MXC_DelayAsync(MXC_SYS_CLOCK_TIMEOUT, NULL); @@ -302,9 +271,8 @@ MXC_DelayAbort(); return E_NO_ERROR; } - } - while (MXC_DelayCheck() == E_BUSY); - + } while (MXC_DelayCheck() == E_BUSY); + return E_TIME_OUT; } @@ -312,139 +280,147 @@ int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock) { uint32_t current_clock; - + // Save the current system clock current_clock = MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL; - + switch (clock) { case MXC_SYS_CLOCK_IPO: - + // Enable IPO clock if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_EN)) { - MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IPO_EN; - + // Check if IPO clock is ready if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IPO_RDY) != E_NO_ERROR) { return E_TIME_OUT; } } - + // Set IPO clock as System Clock - MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO); - + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO); + break; - + case MXC_SYS_CLOCK_IBRO: - + // Enable IBRO clock if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IBRO_EN)) { MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IBRO_EN; - + // Check if IBRO clock is ready if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IBRO_RDY) != E_NO_ERROR) { return E_TIME_OUT; } } - + // Set IBRO clock as System Clock - MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO); - + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO); + break; - + case MXC_SYS_CLOCK_EXTCLK: // Enable HIRC clock // if(!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_EXTCLK_EN)) { // MXC_GCR->clkctrl |=MXC_F_GCR_CLKCTRL_EXTCLK_EN; - + // // Check if HIRC clock is ready // if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY) != E_NO_ERROR) { // return E_TIME_OUT; // } // } - + // Set HIRC clock as System Clock // MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); - + break; - + case MXC_SYS_CLOCK_ERFO: - + // Enable ERFO clock if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERFO_EN)) { MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; - + // Check if ERFO clock is ready if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERFO_RDY) != E_NO_ERROR) { return E_TIME_OUT; } } - + // Set ERFO clock as System Clock - MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO); - + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO); + break; - + case MXC_SYS_CLOCK_INRO: // Set INRO clock as System Clock - MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO); - + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO); + break; - + case MXC_SYS_CLOCK_ERTCO: - + // Enable ERTCO clock if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERTCO_EN)) { MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; - + // Check if ERTCO clock is ready if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERTCO_RDY) != E_NO_ERROR) { return E_TIME_OUT; } } - + // Set ERTCO clock as System Clock - MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO); - + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO); + break; - + default: return E_BAD_PARAM; } - + // Wait for system clock to be ready if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_SYSCLK_RDY) != E_NO_ERROR) { - // Restore the old system clock if timeout MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, current_clock); - + return E_TIME_OUT; } - + // Update the system core clock SystemCoreClockUpdate(); - + return E_NO_ERROR; } /* ************************************************************************** */ void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset) { + // RTC reset bit is different for RevA and RevB + if (reset == MXC_SYS_RESET_RTC) { + // If RevA, switch to reset bit in RST0 + if ((MXC_GCR->revision & 0x00F0) == 0xA0) { + reset = MXC_F_GCR_RST0_RTC_POS; + } + } + /* The mxc_sys_reset_t enum uses enum values that are the offset by 32 and 64 for the rst register. */ if (reset > 63) { reset -= 64; MXC_MCR->rst = (0x1 << reset); - while (MXC_MCR->rst & (0x1 << reset)); - } - else if (reset > 31) { + while (MXC_MCR->rst & (0x1 << reset)) {} + } else if (reset > 31) { reset -= 32; MXC_GCR->rst1 = (0x1 << reset); - while (MXC_GCR->rst1 & (0x1 << reset)); - } - else { + while (MXC_GCR->rst1 & (0x1 << reset)) {} + } else { MXC_GCR->rst0 = (0x1 << reset); - while (MXC_GCR->rst0 & (0x1 << reset)); + while (MXC_GCR->rst0 & (0x1 << reset)) {} } } /**@} end of mxc_sys */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_common.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_common.c index e18d1ca..e886118 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_common.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -39,92 +39,92 @@ /* **** Functions **** */ -void MXC_TMR_Common_Delay(mxc_tmr_regs_t* tmr, unsigned long us) +void MXC_TMR_Common_Delay(mxc_tmr_regs_t *tmr, uint32_t us) { // Return immediately if delay is 0 if (!us) { return; } - + MXC_TMR_TO_Start(tmr, us); - + while (MXC_TMR_TO_Check(tmr) != E_TIME_OUT) {} } -int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t* tmr) +int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t *tmr) { if (MXC_TMR_GetFlags(tmr)) { return E_TIME_OUT; } - + return E_NO_ERROR; } -void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t* tmr) +void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t *tmr) { MXC_TMR_Stop(tmr); MXC_TMR_SetCount(tmr, 0x0); } -void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t* tmr) +void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t *tmr) { MXC_TMR_ClearFlags(tmr); MXC_TMR_SetCount(tmr, 0x0); } -unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t* tmr) +unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t *tmr) { uint32_t remaining_ticks, remaining_time; mxc_tmr_unit_t units; - + remaining_ticks = MXC_TMR_GetCompare(tmr) - MXC_TMR_GetCount(tmr); MXC_TMR_GetTime(tmr, remaining_ticks, &remaining_time, &units); - + switch (units) { case TMR_UNIT_NANOSEC: default: return (remaining_time / 1000); - + case TMR_UNIT_MICROSEC: return (remaining_time); - + case TMR_UNIT_MILLISEC: return (remaining_time * 1000); - + case TMR_UNIT_SEC: return (remaining_time * 1000000); } } -void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t* tmr) +void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t *tmr) { MXC_TMR_TO_Start(tmr, 0xFFFFFFFF); } -unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t* tmr) +unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t *tmr) { unsigned int elapsed = MXC_TMR_TO_Elapsed(tmr); MXC_TMR_TO_Stop(tmr); return elapsed; } -unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t* tmr) +unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t *tmr) { uint32_t elapsed; mxc_tmr_unit_t units; - MXC_TMR_GetTime (tmr, tmr->cnt, &elapsed, &units); - + MXC_TMR_GetTime(tmr, tmr->cnt, &elapsed, &units); + switch (units) { case TMR_UNIT_NANOSEC: default: return (elapsed / 1000); - + case TMR_UNIT_MICROSEC: return (elapsed); - + case TMR_UNIT_MILLISEC: return (elapsed * 1000); - + case TMR_UNIT_SEC: return (elapsed * 1000000); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_common.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_common.h index 46e08fa..517e1e2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_common.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_common.h @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_ /* **** Includes **** */ #include @@ -37,12 +40,14 @@ #include "tmr.h" /* **** Functions **** */ -void MXC_TMR_Common_Delay (mxc_tmr_regs_t *tmr, unsigned long us); -void MXC_TMR_Common_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us); -int MXC_TMR_Common_TO_Check (mxc_tmr_regs_t *tmr); -void MXC_TMR_Common_TO_Stop (mxc_tmr_regs_t *tmr); -void MXC_TMR_Common_TO_Clear (mxc_tmr_regs_t *tmr); -unsigned int MXC_TMR_Common_TO_Elapsed (mxc_tmr_regs_t *tmr); -unsigned int MXC_TMR_Common_TO_Remaining (mxc_tmr_regs_t *tmr); -void MXC_TMR_Common_SW_Start (mxc_tmr_regs_t *tmr); -unsigned int MXC_TMR_Common_SW_Stop (mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_Delay(mxc_tmr_regs_t *tmr, uint32_t us); +void MXC_TMR_Common_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us); +int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t *tmr); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_me15.c index 8eb3ebd..9e3a6c9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_me15.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,354 +29,369 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ -#ifdef __CC_ARM // Keil -#pragma diag_suppress 188 // enumerated type mixed with another type -#endif + ******************************************************************************/ - +#include #include "tmr.h" #include "tmr_revb.h" #include "tmr_common.h" -#include "stdbool.h" +#include "mcr_regs.h" -int MXC_TMR_Init(mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg, bool init_pins) +int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) { int tmr_id = MXC_TMR_GET_IDX(tmr); uint8_t clockSource = MXC_TMR_CLK0; - if(cfg == NULL) { + if (cfg == NULL) { return E_NULL_PTR; } - + MXC_ASSERT(tmr_id >= 0); - + switch (cfg->clock) { case MXC_TMR_EXT_CLK: clockSource = MXC_TMR_CLK1; - MXC_GPIO_Config(&gpio_cfg_extclk); +#if TARGET_NUM != 32675 + if (tmr_id < 4) { + MXC_GPIO_Config(&gpio_cfg_hfextclk); + } else { + MXC_GPIO_Config(&gpio_cfg_lpextclk); + } +#else + MXC_GPIO_Config(&gpio_cfg_extclk); +#endif break; - + case MXC_TMR_32K_CLK: - if(tmr_id < 5) { + if (tmr_id < 4) { return E_NOT_SUPPORTED; } clockSource = MXC_TMR_CLK2; - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); break; - + case MXC_TMR_80K_CLK: - if(tmr_id < 5) { + if (tmr_id < 4) { return E_NOT_SUPPORTED; } clockSource = MXC_TMR_CLK3; - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO); + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO); break; - + case MXC_TMR_8M_CLK: - if(tmr_id > 4) { + if (tmr_id > 3) { return E_NOT_SUPPORTED; } clockSource = MXC_TMR_CLK2; - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); break; - + case MXC_TMR_32M_CLK: - if(tmr_id > 4) { + if (tmr_id > 3) { return E_NOT_SUPPORTED; } clockSource = MXC_TMR_CLK3; - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERFO); - break; + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERFO); + break; default: break; } - + //enable peripheral clock and configure gpio pins switch (tmr_id) { case 0: MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0); - + if (init_pins) { if (cfg->bitMode != TMR_BIT_MODE_16B) { MXC_GPIO_Config(&gpio_cfg_tmr0); } } - + break; - + case 1: MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR1); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1); - + if (init_pins) { if (cfg->bitMode != TMR_BIT_MODE_16B) { MXC_GPIO_Config(&gpio_cfg_tmr1); } } - + break; - + case 2: MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR2); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2); - + if (init_pins) { if (cfg->bitMode != TMR_BIT_MODE_16B) { MXC_GPIO_Config(&gpio_cfg_tmr2); } } - + break; - + case 3: MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR3); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR3); - + if (init_pins) { if (cfg->bitMode != TMR_BIT_MODE_16B) { MXC_GPIO_Config(&gpio_cfg_tmr3); } } - + break; - + case 4: MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR4); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR4); - + if (init_pins) { if (cfg->bitMode != TMR_BIT_MODE_16B) { MXC_GPIO_Config(&gpio_cfg_tmr4); - } - else { +#if TARGET_NUM == 32670 + MXC_MCR->lppioctrl |= MXC_F_MCR_LPPIOCTRL_LPTMR0_I | MXC_F_MCR_LPPIOCTRL_LPTMR0_O; +#endif + } else { return E_NOT_SUPPORTED; } } - + break; - + case 5: MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR5); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR5); - + if (init_pins) { if (cfg->bitMode != TMR_BIT_MODE_16B) { MXC_GPIO_Config(&gpio_cfg_tmr5); - } - else { +#if TARGET_NUM == 32670 + MXC_MCR->lppioctrl |= MXC_F_MCR_LPPIOCTRL_LPTMR1_I | MXC_F_MCR_LPPIOCTRL_LPTMR1_O; +#endif + } else { return E_NOT_SUPPORTED; } } - + break; } - - return MXC_TMR_RevB_Init ((mxc_tmr_revb_regs_t*) tmr, cfg, clockSource); + + return MXC_TMR_RevB_Init((mxc_tmr_revb_regs_t *)tmr, cfg, clockSource); } -void MXC_TMR_Shutdown(mxc_tmr_regs_t* tmr) +void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr) { int tmr_id = MXC_TMR_GET_IDX(tmr); - + MXC_ASSERT(tmr_id >= 0); - - MXC_TMR_RevB_Shutdown ((mxc_tmr_revb_regs_t*) tmr); - + + MXC_TMR_RevB_Shutdown((mxc_tmr_revb_regs_t *)tmr); + // System settigns //diasble peripheral clock switch (tmr_id) { case 0: MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0); break; - + case 1: MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1); break; - + case 2: MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2); break; - + case 3: MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR3); break; - + case 4: MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR4); +#if TARGET_NUM == 32670 + MXC_MCR->lppioctrl &= ~(MXC_F_MCR_LPPIOCTRL_LPTMR0_I | MXC_F_MCR_LPPIOCTRL_LPTMR0_O); +#endif break; - + case 5: MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR5); +#if TARGET_NUM == 32670 + MXC_MCR->lppioctrl &= ~(MXC_F_MCR_LPPIOCTRL_LPTMR1_I | MXC_F_MCR_LPPIOCTRL_LPTMR1_O); +#endif break; } } -void MXC_TMR_Start(mxc_tmr_regs_t* tmr) +void MXC_TMR_Start(mxc_tmr_regs_t *tmr) { - MXC_TMR_RevB_Start ((mxc_tmr_revb_regs_t*) tmr); + MXC_TMR_RevB_Start((mxc_tmr_revb_regs_t *)tmr); } -void MXC_TMR_Stop(mxc_tmr_regs_t* tmr) +void MXC_TMR_Stop(mxc_tmr_regs_t *tmr) { - MXC_TMR_RevB_Stop ((mxc_tmr_revb_regs_t*) tmr); + MXC_TMR_RevB_Stop((mxc_tmr_revb_regs_t *)tmr); } -int MXC_TMR_SetPWM(mxc_tmr_regs_t* tmr, uint32_t pwm) +int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm) { - return MXC_TMR_RevB_SetPWM((mxc_tmr_revb_regs_t*) tmr, pwm); + return MXC_TMR_RevB_SetPWM((mxc_tmr_revb_regs_t *)tmr, pwm); } -uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t* tmr) +uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr) { - return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t*)tmr); + return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t *)tmr); } -uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t* tmr) +uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr) { - return MXC_TMR_RevB_GetCompare ((mxc_tmr_revb_regs_t*) tmr); + return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t *)tmr); } -uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency) +uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar, + uint32_t frequency) { uint32_t clockFrequency = PeripheralClock; int tmr_id = MXC_TMR_GET_IDX(tmr); - + MXC_ASSERT(tmr_id >= 0); - + if (tmr_id > 3) { switch (clock) { case MXC_TMR_APB_CLK: clockFrequency = (PeripheralClock / 4); break; - + case MXC_TMR_32K_CLK: clockFrequency = ERTCO_FREQ; break; - + case MXC_TMR_80K_CLK: clockFrequency = INRO_FREQ; break; - + default: break; } - } - else { + } else { switch (clock) { case MXC_TMR_APB_CLK: clockFrequency = PeripheralClock; break; - + case MXC_TMR_8M_CLK: clockFrequency = IBRO_FREQ; break; - + case MXC_TMR_32M_CLK: - clockFrequency = 16000000; // Clock Frequency 16 MHz + clockFrequency = ERFO_FREQ; break; - + default: break; } } - - return MXC_TMR_RevB_GetPeriod((mxc_tmr_revb_regs_t*)tmr, clockFrequency, prescalar, frequency); + + return MXC_TMR_RevB_GetPeriod((mxc_tmr_revb_regs_t *)tmr, clockFrequency, prescalar, frequency); } -uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t* tmr) +uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr) { - return MXC_TMR_RevB_GetCount((mxc_tmr_revb_regs_t*)tmr); + return MXC_TMR_RevB_GetCount((mxc_tmr_revb_regs_t *)tmr); } -void MXC_TMR_ClearFlags(mxc_tmr_regs_t* tmr) +void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr) { - MXC_TMR_RevB_ClearFlags((mxc_tmr_revb_regs_t*)tmr); + MXC_TMR_RevB_ClearFlags((mxc_tmr_revb_regs_t *)tmr); } -uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t* tmr) +uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr) { - return MXC_TMR_RevB_GetFlags((mxc_tmr_revb_regs_t*)tmr); + return MXC_TMR_RevB_GetFlags((mxc_tmr_revb_regs_t *)tmr); } -void MXC_TMR_EnableInt(mxc_tmr_regs_t* tmr) +void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr) { - MXC_TMR_RevB_EnableInt((mxc_tmr_revb_regs_t*)tmr); + MXC_TMR_RevB_EnableInt((mxc_tmr_revb_regs_t *)tmr); } -void MXC_TMR_DisableInt(mxc_tmr_regs_t* tmr) +void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr) { - MXC_TMR_RevB_DisableInt((mxc_tmr_revb_regs_t*)tmr); + MXC_TMR_RevB_DisableInt((mxc_tmr_revb_regs_t *)tmr); } -void MXC_TMR_EnableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg) +void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg) { - MXC_TMR_RevB_EnableWakeup ((mxc_tmr_revb_regs_t*)tmr, cfg); + MXC_TMR_RevB_EnableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg); } -void MXC_TMR_DisableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg) +void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg) { - MXC_TMR_RevB_DisableWakeup ((mxc_tmr_revb_regs_t*)tmr, cfg); + MXC_TMR_RevB_DisableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg); } -void MXC_TMR_SetCompare(mxc_tmr_regs_t* tmr, uint32_t cmp_cnt) +void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt) { - MXC_TMR_RevB_SetCompare((mxc_tmr_revb_regs_t*)tmr, cmp_cnt); + MXC_TMR_RevB_SetCompare((mxc_tmr_revb_regs_t *)tmr, cmp_cnt); } -void MXC_TMR_SetCount(mxc_tmr_regs_t* tmr, uint32_t cnt) +void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt) { - MXC_TMR_RevB_SetCount((mxc_tmr_revb_regs_t*)tmr, cnt); + MXC_TMR_RevB_SetCount((mxc_tmr_revb_regs_t *)tmr, cnt); } -void MXC_TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us) +void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us) { MXC_TMR_Common_Delay(tmr, us); } -void MXC_TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us) +void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us) { - MXC_TMR_RevB_TO_Start((mxc_tmr_revb_regs_t*)tmr, us); + MXC_TMR_RevB_TO_Start((mxc_tmr_revb_regs_t *)tmr, us); } -int MXC_TMR_TO_Check(mxc_tmr_regs_t* tmr) +int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr) { return MXC_TMR_Common_TO_Check(tmr); } -void MXC_TMR_TO_Stop(mxc_tmr_regs_t* tmr) +void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr) { MXC_TMR_Common_TO_Stop(tmr); } -void MXC_TMR_TO_Clear(mxc_tmr_regs_t* tmr) +void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr) { MXC_TMR_Common_TO_Clear(tmr); } -unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t* tmr) +unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr) { return MXC_TMR_Common_TO_Elapsed(tmr); } -unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t* tmr) +unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr) { return MXC_TMR_Common_TO_Remaining(tmr); } -void MXC_TMR_SW_Start(mxc_tmr_regs_t* tmr) +void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr) { MXC_TMR_Common_SW_Start(tmr); } -unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t* tmr) +unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr) { return MXC_TMR_Common_SW_Stop(tmr); } -int MXC_TMR_GetTime(mxc_tmr_regs_t* tmr, uint32_t ticks, uint32_t* time, mxc_tmr_unit_t* units) +int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units) { - return MXC_TMR_RevB_GetTime((mxc_tmr_revb_regs_t*)tmr, ticks, time, units); + return MXC_TMR_RevB_GetTime((mxc_tmr_revb_regs_t *)tmr, ticks, time, units); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c index 25596a5..c51784f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c @@ -1,10 +1,10 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * @@ -15,7 +15,7 @@ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * @@ -24,15 +24,12 @@ * Products, Inc. Branding Policy. * * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, + * of trade secrets, proprietary technology, copyrights, patents, * trademarks, maskwork rights, or any other form of intellectual * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ -#ifdef __CC_ARM // Keil -#pragma diag_suppress 188 // enumerated type mixed with another type -#endif + ******************************************************************************/ /* **** Includes **** */ #include @@ -44,220 +41,218 @@ #include "mxc_lock.h" /* **** Definitions **** */ -#define TIMER_16A_OFFSET 0 -#define TIMER_16B_OFFSET 16 - +#define TIMER_16A_OFFSET 0 +#define TIMER_16B_OFFSET 16 /* **** Functions **** */ -int MXC_TMR_RevB_Init(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t* cfg, uint8_t clk_src) +int MXC_TMR_RevB_Init(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg, uint8_t clk_src) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); - if(cfg == NULL){ + if (cfg == NULL) { return E_NULL_PTR; } - + uint32_t timerOffset; - + if (cfg->bitMode == TMR_BIT_MODE_16B) { timerOffset = TIMER_16B_OFFSET; - } - else { + } else { timerOffset = TIMER_16A_OFFSET; } - + // Default 32 bit timer - if(cfg->bitMode & (TMR_BIT_MODE_16A | TMR_BIT_MODE_16B)){ + if (cfg->bitMode & (TMR_BIT_MODE_16A | TMR_BIT_MODE_16B)) { tmr->ctrl1 &= ~MXC_F_TMR_REVB_CTRL1_CASCADE; - }else{ + } else { tmr->ctrl1 |= MXC_F_TMR_REVB_CTRL1_CASCADE; } - + // Clear interrupt flag tmr->intfl |= (MXC_F_TMR_REVB_INTFL_IRQ_A | MXC_F_TMR_REVB_INTFL_IRQ_B); - + // Set the prescale tmr->ctrl0 |= (cfg->pres << timerOffset); - + // Select clock Source tmr->ctrl1 |= ((clk_src << MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS) << timerOffset); - + //TIMER_16B only supports compare, oneshot and continuous modes. - switch(cfg->mode) { + switch (cfg->mode) { case TMR_MODE_ONESHOT: - MXC_TMR_RevB_ConfigGeneric((mxc_tmr_revb_regs_t*) tmr, cfg); + MXC_TMR_RevB_ConfigGeneric((mxc_tmr_revb_regs_t *)tmr, cfg); break; - + case TMR_MODE_CONTINUOUS: - MXC_TMR_RevB_ConfigGeneric((mxc_tmr_revb_regs_t*) tmr, cfg); + MXC_TMR_RevB_ConfigGeneric((mxc_tmr_revb_regs_t *)tmr, cfg); break; - + case TMR_MODE_COUNTER: if (cfg->bitMode == TMR_BIT_MODE_16B) { return E_NOT_SUPPORTED; } - + MXC_TMR_RevB_ConfigGeneric(tmr, cfg); break; - + case TMR_MODE_CAPTURE: if (cfg->bitMode == TMR_BIT_MODE_16B) { return E_NOT_SUPPORTED; } - + MXC_TMR_RevB_ConfigGeneric(tmr, cfg); break; - + case TMR_MODE_COMPARE: - MXC_TMR_RevB_ConfigGeneric((mxc_tmr_revb_regs_t*) tmr, cfg); + MXC_TMR_RevB_ConfigGeneric((mxc_tmr_revb_regs_t *)tmr, cfg); break; - + case TMR_MODE_GATED: if (cfg->bitMode == TMR_BIT_MODE_16B) { return E_NOT_SUPPORTED; } - + MXC_TMR_RevB_ConfigGeneric(tmr, cfg); break; - + case TMR_MODE_CAPTURE_COMPARE: if (cfg->bitMode == TMR_BIT_MODE_16B) { return E_NOT_SUPPORTED; } - + MXC_TMR_RevB_ConfigGeneric(tmr, cfg); break; - + case TMR_MODE_PWM: if (cfg->bitMode == TMR_BIT_MODE_16B) { return E_NOT_SUPPORTED; } - MXC_TMR_RevB_ConfigGeneric((mxc_tmr_revb_regs_t*) tmr, cfg); + MXC_TMR_RevB_ConfigGeneric((mxc_tmr_revb_regs_t *)tmr, cfg); break; } - + return E_NO_ERROR; } -void MXC_TMR_RevB_ConfigGeneric(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t* cfg) +void MXC_TMR_RevB_ConfigGeneric(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg) { uint32_t timerOffset; - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); - if(cfg == NULL){ + if (cfg == NULL) { return; } - - if(cfg->bitMode == TMR_BIT_MODE_16B) { + + if (cfg->bitMode == TMR_BIT_MODE_16B) { timerOffset = TIMER_16B_OFFSET; - } - else { + } else { timerOffset = TIMER_16A_OFFSET; } tmr->ctrl0 |= (MXC_F_TMR_REVB_CTRL0_CLKEN_A << timerOffset); - while(!(tmr->ctrl1 & (MXC_F_TMR_REVB_CTRL1_CLKRDY_A << timerOffset))); + while (!(tmr->ctrl1 & (MXC_F_TMR_REVB_CTRL1_CLKRDY_A << timerOffset))) {} tmr->ctrl0 |= (cfg->mode << timerOffset); tmr->ctrl0 |= ((cfg->pol << MXC_F_TMR_REVB_CTRL0_POL_A_POS) << timerOffset); //enable timer interrupt if needed tmr->cnt = (0x1 << timerOffset); - while(!(tmr->intfl & (MXC_F_TMR_REVB_INTFL_WRDONE_A << timerOffset))); + while (!(tmr->intfl & (MXC_F_TMR_REVB_INTFL_WRDONE_A << timerOffset))) {} tmr->cmp = (cfg->cmp_cnt << timerOffset); #if TARGET_NUM == 32655 || TARGET_NUM == 78000 || TARGET_NUM == 32690 || TARGET_NUM == 78002 tmr->ctrl1 &= ~(MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); #else - tmr->ctrl1 |= (MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); + // on default disable timer gpio out + //tmr->ctrl1 |= (MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); #endif // If configured as TIMER_16B then enable the interrupt and start the timer - if(cfg->bitMode == TMR_BIT_MODE_16B){ + if (cfg->bitMode == TMR_BIT_MODE_16B) { tmr->ctrl1 |= MXC_F_TMR_REVB_CTRL1_IE_B; tmr->ctrl0 |= MXC_F_TMR_REVB_CTRL0_EN_B; - while(!(tmr->ctrl1 & MXC_F_TMR_REVB_CTRL1_CLKEN_B)); + while (!(tmr->ctrl1 & MXC_F_TMR_REVB_CTRL1_CLKEN_B)) {} } } void MXC_TMR_RevB_Shutdown(mxc_tmr_revb_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); - + // Disable timer and clear settings tmr->ctrl0 = 0; - while(tmr->ctrl1 & MXC_F_TMR_REVB_CTRL1_CLKRDY_A); + while (tmr->ctrl1 & MXC_F_TMR_REVB_CTRL1_CLKRDY_A) {} } -void MXC_TMR_RevB_Start(mxc_tmr_revb_regs_t* tmr) +void MXC_TMR_RevB_Start(mxc_tmr_revb_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); tmr->ctrl0 |= MXC_F_TMR_REVB_CTRL0_EN_A; - while(!(tmr->ctrl1 & MXC_F_TMR_REVB_CTRL1_CLKEN_A)); + while (!(tmr->ctrl1 & MXC_F_TMR_REVB_CTRL1_CLKEN_A)) {} } -void MXC_TMR_RevB_Stop(mxc_tmr_revb_regs_t* tmr) +void MXC_TMR_RevB_Stop(mxc_tmr_revb_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); tmr->ctrl0 &= ~MXC_F_TMR_REVB_CTRL0_EN_A; } -int MXC_TMR_RevB_SetPWM(mxc_tmr_revb_regs_t* tmr, uint32_t pwm) +int MXC_TMR_RevB_SetPWM(mxc_tmr_revb_regs_t *tmr, uint32_t pwm) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); - - if(pwm >(tmr->cmp)) { + + if (pwm > (tmr->cmp)) { return E_BAD_PARAM; } - - while(tmr->cnt >= pwm); - + + while (tmr->cnt >= pwm) {} + tmr->pwm = pwm; - while(!(tmr->intfl & MXC_F_TMR_REVB_INTFL_WRDONE_A)); - + while (!(tmr->intfl & MXC_F_TMR_REVB_INTFL_WRDONE_A)) {} + return E_NO_ERROR; } -uint32_t MXC_TMR_RevB_GetCompare(mxc_tmr_revb_regs_t* tmr) +uint32_t MXC_TMR_RevB_GetCompare(mxc_tmr_revb_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); return tmr->cmp; } -uint32_t MXC_TMR_RevB_GetCapture(mxc_tmr_revb_regs_t* tmr) +uint32_t MXC_TMR_RevB_GetCapture(mxc_tmr_revb_regs_t *tmr) { uint32_t pwm; - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); // read pwm register twice pwm = tmr->pwm; pwm = tmr->pwm; - return pwm; + return pwm; } -uint32_t MXC_TMR_RevB_GetCount(mxc_tmr_revb_regs_t* tmr) +uint32_t MXC_TMR_RevB_GetCount(mxc_tmr_revb_regs_t *tmr) { uint32_t cnt; - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); @@ -267,91 +262,86 @@ return cnt; } -uint32_t MXC_TMR_RevB_GetPeriod(mxc_tmr_revb_regs_t* tmr, uint32_t clk_frequency, uint32_t prescalar, uint32_t frequency) +uint32_t MXC_TMR_RevB_GetPeriod(mxc_tmr_revb_regs_t *tmr, uint32_t clk_frequency, + uint32_t prescalar, uint32_t frequency) { uint32_t periodTicks; - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); - periodTicks = clk_frequency /(frequency * prescalar); - + periodTicks = clk_frequency / (frequency * prescalar); + return periodTicks; } -void MXC_TMR_RevB_ClearFlags(mxc_tmr_revb_regs_t* tmr) +void MXC_TMR_RevB_ClearFlags(mxc_tmr_revb_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); tmr->intfl |= (MXC_F_TMR_REVB_INTFL_IRQ_A | MXC_F_TMR_REVB_INTFL_IRQ_B); } -uint32_t MXC_TMR_RevB_GetFlags(mxc_tmr_revb_regs_t* tmr) +uint32_t MXC_TMR_RevB_GetFlags(mxc_tmr_revb_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); - return(tmr->intfl & (MXC_F_TMR_REVB_INTFL_IRQ_A | MXC_F_TMR_REVB_INTFL_IRQ_B)); + return (tmr->intfl & (MXC_F_TMR_REVB_INTFL_IRQ_A | MXC_F_TMR_REVB_INTFL_IRQ_B)); } -void MXC_TMR_RevB_EnableInt(mxc_tmr_revb_regs_t* tmr) +void MXC_TMR_RevB_EnableInt(mxc_tmr_revb_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); tmr->ctrl1 |= MXC_F_TMR_REVB_CTRL1_IE_A | MXC_F_TMR_REVB_CTRL1_IE_B; } -void MXC_TMR_RevB_DisableInt(mxc_tmr_revb_regs_t* tmr) +void MXC_TMR_RevB_DisableInt(mxc_tmr_revb_regs_t *tmr) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); tmr->ctrl1 &= ~(MXC_F_TMR_REVB_CTRL1_IE_A | MXC_F_TMR_REVB_CTRL1_IE_B); } -void MXC_TMR_RevB_EnableWakeup(mxc_tmr_revb_regs_t* tmr, mxc_tmr_cfg_t* cfg) +void MXC_TMR_RevB_EnableWakeup(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); // Enable Timer wake-up source - if(cfg->bitMode == TMR_BIT_MODE_16B) - { - tmr->ctrl1 |= MXC_F_TMR_REVB_CTRL1_WE_B; - } - else - { - tmr->ctrl1 |= MXC_F_TMR_REVB_CTRL1_WE_A; + if (cfg->bitMode == TMR_BIT_MODE_16B) { + tmr->ctrl1 |= MXC_F_TMR_REVB_CTRL1_WE_B; + } else { + tmr->ctrl1 |= MXC_F_TMR_REVB_CTRL1_WE_A; } } -void MXC_TMR_RevB_DisableWakeup(mxc_tmr_revb_regs_t* tmr, mxc_tmr_cfg_t* cfg) +void MXC_TMR_RevB_DisableWakeup(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); // Disable Timer wake-up source - if(cfg->bitMode == TMR_BIT_MODE_16B) - { - tmr->ctrl1 &= ~MXC_F_TMR_REVB_CTRL1_WE_B; - } - else - { - tmr->ctrl1 &= ~MXC_F_TMR_REVB_CTRL1_WE_A; + if (cfg->bitMode == TMR_BIT_MODE_16B) { + tmr->ctrl1 &= ~MXC_F_TMR_REVB_CTRL1_WE_B; + } else { + tmr->ctrl1 &= ~MXC_F_TMR_REVB_CTRL1_WE_A; } } void MXC_TMR_RevB_SetCompare(mxc_tmr_revb_regs_t *tmr, uint32_t cmp_cnt) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); @@ -360,37 +350,37 @@ void MXC_TMR_RevB_SetCount(mxc_tmr_revb_regs_t *tmr, uint32_t cnt) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); tmr->cnt = cnt; - while(!(tmr->intfl & MXC_F_TMR_REVB_INTFL_WRDONE_A)); + while (!(tmr->intfl & MXC_F_TMR_REVB_INTFL_WRDONE_A)) {} } -void MXC_TMR_RevB_TO_Start(mxc_tmr_revb_regs_t *tmr, unsigned long us) +void MXC_TMR_RevB_TO_Start(mxc_tmr_revb_regs_t *tmr, uint32_t us) { uint64_t ticks; int clk_shift = 0; - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); - if(us == 0){ + if (us == 0) { return; - } + } - ticks = (uint64_t) us *(uint64_t) PeripheralClock /(uint64_t) 1000000; - - while(ticks > 0xFFFFFFFFUL) { + ticks = (uint64_t)us * (uint64_t)PeripheralClock / (uint64_t)1000000; + + while (ticks > 0xFFFFFFFFUL) { ticks >>= 1; ++clk_shift; } - - mxc_tmr_pres_t prescale = (mxc_tmr_pres_t) clk_shift << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS; + + mxc_tmr_pres_t prescale = (mxc_tmr_pres_t)clk_shift << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS; mxc_tmr_cfg_t cfg; - + // Initialize the timer in one-shot mode cfg.pres = prescale; cfg.mode = TMR_MODE_ONESHOT; @@ -398,98 +388,105 @@ cfg.clock = MXC_TMR_APB_CLK; cfg.cmp_cnt = ticks; cfg.pol = 0; - - MXC_TMR_Stop((mxc_tmr_regs_t*) tmr); - MXC_TMR_Init((mxc_tmr_regs_t*) tmr, &cfg, false); + + MXC_TMR_Stop((mxc_tmr_regs_t *)tmr); +#if TARGET_NUM == 32662 + MXC_TMR_Init((mxc_tmr_regs_t *)tmr, &cfg, false, MAP_A); +#else + MXC_TMR_Init((mxc_tmr_regs_t *)tmr, &cfg, false); +#endif tmr->ctrl1 |= MXC_F_TMR_REVB_CTRL1_CASCADE; - MXC_TMR_ClearFlags((mxc_tmr_regs_t*) tmr); - MXC_TMR_Start((mxc_tmr_regs_t*) tmr); + MXC_TMR_ClearFlags((mxc_tmr_regs_t *)tmr); + MXC_TMR_Start((mxc_tmr_regs_t *)tmr); } -int MXC_TMR_RevB_GetTime(mxc_tmr_revb_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units) +int MXC_TMR_RevB_GetTime(mxc_tmr_revb_regs_t *tmr, uint32_t ticks, uint32_t *time, + mxc_tmr_unit_t *units) { - int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr); (void)tmr_id; MXC_ASSERT(tmr_id >= 0); uint64_t temp_time = 0; uint32_t timerClock = PeripheralClock; - uint32_t prescale = (tmr->ctrl0 & MXC_F_TMR_REVB_CTRL0_CLKDIV_A) >> MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS; - - temp_time = (uint64_t) ticks * 1000 *(1 <<(prescale & 0xF)) /(timerClock / 1000000); - - if(!(temp_time & 0xffffffff00000000)) { + uint32_t prescale = (tmr->ctrl0 & MXC_F_TMR_REVB_CTRL0_CLKDIV_A) >> + MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS; + + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000000); + + if (!(temp_time & 0xffffffff00000000)) { *time = temp_time; *units = TMR_UNIT_NANOSEC; return E_NO_ERROR; } - - temp_time = (uint64_t) ticks * 1000 *(1 <<(prescale & 0xF)) /(timerClock / 1000); - - if(!(temp_time & 0xffffffff00000000)) { + + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000); + + if (!(temp_time & 0xffffffff00000000)) { *time = temp_time; *units = TMR_UNIT_MICROSEC; return E_NO_ERROR; } - - temp_time = (uint64_t) ticks * 1000 *(1 <<(prescale & 0xF)) / timerClock; - - if(!(temp_time & 0xffffffff00000000)) { + + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / timerClock; + + if (!(temp_time & 0xffffffff00000000)) { *time = temp_time; *units = TMR_UNIT_MILLISEC; return E_NO_ERROR; } - - temp_time = (uint64_t) ticks *(1 <<(prescale & 0xF)) / timerClock; - - if(!(temp_time & 0xffffffff00000000)) { + + temp_time = (uint64_t)ticks * (1 << (prescale & 0xF)) / timerClock; + + if (!(temp_time & 0xffffffff00000000)) { *time = temp_time; *units = TMR_UNIT_SEC; return E_NO_ERROR; } - + return E_INVALID; } -int MXC_TMR_RevB_GetTicks(mxc_tmr_revb_regs_t *tmr, uint32_t time, mxc_tmr_unit_t units, uint32_t *ticks) +int MXC_TMR_RevB_GetTicks(mxc_tmr_revb_regs_t *tmr, uint32_t time, mxc_tmr_unit_t units, + uint32_t *ticks) { uint32_t unit_div0, unit_div1; uint32_t timerClock; uint32_t prescale; uint64_t temp_ticks; - + timerClock = PeripheralClock; - prescale = ((tmr->ctrl0 & MXC_F_TMR_CTRL0_CLKDIV_A) >> MXC_F_TMR_CTRL0_CLKDIV_A_POS); - + prescale = ((tmr->ctrl0 & MXC_F_TMR_CTRL0_CLKDIV_A) >> MXC_F_TMR_CTRL0_CLKDIV_A_POS); + switch (units) { - case TMR_UNIT_NANOSEC: - unit_div0 = 1000000; - unit_div1 = 1000; - break; - case TMR_UNIT_MICROSEC: - unit_div0 = 1000; - unit_div1 = 1000; - break; - case TMR_UNIT_MILLISEC: - unit_div0 = 1; - unit_div1 = 1000; - break; - case TMR_UNIT_SEC: - unit_div0 = 1; - unit_div1 = 1; - break; - default: - return E_BAD_PARAM; + case TMR_UNIT_NANOSEC: + unit_div0 = 1000000; + unit_div1 = 1000; + break; + case TMR_UNIT_MICROSEC: + unit_div0 = 1000; + unit_div1 = 1000; + break; + case TMR_UNIT_MILLISEC: + unit_div0 = 1; + unit_div1 = 1000; + break; + case TMR_UNIT_SEC: + unit_div0 = 1; + unit_div1 = 1; + break; + default: + return E_BAD_PARAM; } - + temp_ticks = (uint64_t)time * (timerClock / unit_div0) / (unit_div1 * (1 << (prescale & 0xF))); - + //make sure ticks is within a 32 bit value - if (!(temp_ticks & 0xffffffff00000000) && (temp_ticks & 0xffffffff)) { + if (!(temp_ticks & 0xffffffff00000000) && (temp_ticks & 0xffffffff)) { *ticks = temp_ticks; return E_NO_ERROR; } - + return E_INVALID; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.h index 1353246..a5251c4 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.h @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVB_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVB_H_ /* **** Includes **** */ #include @@ -40,33 +43,37 @@ #include "mxc_lock.h" #include "tmr_revb_regs.h" - typedef enum { MXC_TMR_CLK0, MXC_TMR_CLK1, MXC_TMR_CLK2, - MXC_TMR_CLK3, + MXC_TMR_CLK3, } mxc_tmr_clksel_t; /* **** Functions **** */ -int MXC_TMR_RevB_Init (mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t* cfg, uint8_t clk_src); -void MXC_TMR_RevB_ConfigGeneric(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t* cfg); -void MXC_TMR_RevB_Shutdown (mxc_tmr_revb_regs_t *tmr); -void MXC_TMR_RevB_Start (mxc_tmr_revb_regs_t* tmr); -void MXC_TMR_RevB_Stop (mxc_tmr_revb_regs_t* tmr); -int MXC_TMR_RevB_SetPWM (mxc_tmr_revb_regs_t* tmr, uint32_t pwm); -uint32_t MXC_TMR_RevB_GetCompare (mxc_tmr_revb_regs_t* tmr); -uint32_t MXC_TMR_RevB_GetCapture (mxc_tmr_revb_regs_t* tmr); -uint32_t MXC_TMR_RevB_GetCount (mxc_tmr_revb_regs_t* tmr); -uint32_t MXC_TMR_RevB_GetPeriod (mxc_tmr_revb_regs_t* tmr, uint32_t clk_frequency, uint32_t prescalar, uint32_t frequency); -void MXC_TMR_RevB_ClearFlags (mxc_tmr_revb_regs_t* tmr); -uint32_t MXC_TMR_RevB_GetFlags (mxc_tmr_revb_regs_t* tmr); -void MXC_TMR_RevB_EnableInt (mxc_tmr_revb_regs_t* tmr); -void MXC_TMR_RevB_DisableInt (mxc_tmr_revb_regs_t* tmr); -void MXC_TMR_RevB_EnableWakeup (mxc_tmr_revb_regs_t* tmr, mxc_tmr_cfg_t* cfg); -void MXC_TMR_RevB_DisableWakeup (mxc_tmr_revb_regs_t* tmr, mxc_tmr_cfg_t* cfg); -void MXC_TMR_RevB_SetCompare (mxc_tmr_revb_regs_t *tmr, uint32_t cmp_cnt); -void MXC_TMR_RevB_SetCount (mxc_tmr_revb_regs_t *tmr, uint32_t cnt); -void MXC_TMR_RevB_TO_Start (mxc_tmr_revb_regs_t *tmr, unsigned long us); -int MXC_TMR_RevB_GetTime (mxc_tmr_revb_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); -int MXC_TMR_RevB_GetTicks(mxc_tmr_revb_regs_t *tmr, uint32_t time, mxc_tmr_unit_t units, uint32_t *ticks); +int MXC_TMR_RevB_Init(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg, uint8_t clk_src); +void MXC_TMR_RevB_ConfigGeneric(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg); +void MXC_TMR_RevB_Shutdown(mxc_tmr_revb_regs_t *tmr); +void MXC_TMR_RevB_Start(mxc_tmr_revb_regs_t *tmr); +void MXC_TMR_RevB_Stop(mxc_tmr_revb_regs_t *tmr); +int MXC_TMR_RevB_SetPWM(mxc_tmr_revb_regs_t *tmr, uint32_t pwm); +uint32_t MXC_TMR_RevB_GetCompare(mxc_tmr_revb_regs_t *tmr); +uint32_t MXC_TMR_RevB_GetCapture(mxc_tmr_revb_regs_t *tmr); +uint32_t MXC_TMR_RevB_GetCount(mxc_tmr_revb_regs_t *tmr); +uint32_t MXC_TMR_RevB_GetPeriod(mxc_tmr_revb_regs_t *tmr, uint32_t clk_frequency, + uint32_t prescalar, uint32_t frequency); +void MXC_TMR_RevB_ClearFlags(mxc_tmr_revb_regs_t *tmr); +uint32_t MXC_TMR_RevB_GetFlags(mxc_tmr_revb_regs_t *tmr); +void MXC_TMR_RevB_EnableInt(mxc_tmr_revb_regs_t *tmr); +void MXC_TMR_RevB_DisableInt(mxc_tmr_revb_regs_t *tmr); +void MXC_TMR_RevB_EnableWakeup(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg); +void MXC_TMR_RevB_DisableWakeup(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg); +void MXC_TMR_RevB_SetCompare(mxc_tmr_revb_regs_t *tmr, uint32_t cmp_cnt); +void MXC_TMR_RevB_SetCount(mxc_tmr_revb_regs_t *tmr, uint32_t cnt); +void MXC_TMR_RevB_TO_Start(mxc_tmr_revb_regs_t *tmr, uint32_t us); +int MXC_TMR_RevB_GetTime(mxc_tmr_revb_regs_t *tmr, uint32_t ticks, uint32_t *time, + mxc_tmr_unit_t *units); +int MXC_TMR_RevB_GetTicks(mxc_tmr_revb_regs_t *tmr, uint32_t time, mxc_tmr_unit_t units, + uint32_t *ticks); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVB_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h index 0c3467c..4a10849 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the TMR_REVB Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _TMR_REVB_REGS_H_ #define _TMR_REVB_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_me15.c index fef61bf..a56907a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_me15.c @@ -1,8 +1,8 @@ -/* **************************************************************************** - * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include "mxc_device.h" #include "mxc_errors.h" @@ -38,7 +38,6 @@ #include "trng_revb.h" #include "trng.h" - /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ @@ -56,26 +55,26 @@ void MXC_TRNG_EnableInt(void) { - MXC_TRNG_RevB_EnableInt((mxc_trng_revb_regs_t*) MXC_TRNG); + MXC_TRNG_RevB_EnableInt((mxc_trng_revb_regs_t *)MXC_TRNG); } void MXC_TRNG_DisableInt(void) { - MXC_TRNG_RevB_DisableInt((mxc_trng_revb_regs_t*) MXC_TRNG); + MXC_TRNG_RevB_DisableInt((mxc_trng_revb_regs_t *)MXC_TRNG); } int MXC_TRNG_Shutdown(void) { int error = MXC_TRNG_RevB_Shutdown(); - + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TRNG); - + return error; } void MXC_TRNG_Handler(void) { - MXC_TRNG_RevB_Handler((mxc_trng_revb_regs_t*) MXC_TRNG); + MXC_TRNG_RevB_Handler((mxc_trng_revb_regs_t *)MXC_TRNG); } /* ************************************************************************* */ @@ -84,20 +83,29 @@ int MXC_TRNG_RandomInt(void) { - return MXC_TRNG_RevB_RandomInt((mxc_trng_revb_regs_t*) MXC_TRNG); + return MXC_TRNG_RevB_RandomInt((mxc_trng_revb_regs_t *)MXC_TRNG); } -int MXC_TRNG_Random(uint8_t* data, uint32_t len) +int MXC_TRNG_Random(uint8_t *data, uint32_t len) { return MXC_TRNG_RevB_Random(data, len); } -void MXC_TRNG_RandomAsync(uint8_t* data, uint32_t len, mxc_trng_complete_t callback) +void MXC_TRNG_RandomAsync(uint8_t *data, uint32_t len, mxc_trng_complete_t callback) { - MXC_TRNG_RevB_RandomAsync((mxc_trng_revb_regs_t*) MXC_TRNG, data, len, callback); + MXC_TRNG_RevB_RandomAsync((mxc_trng_revb_regs_t *)MXC_TRNG, data, len, callback); } void MXC_TRNG_GenerateKey(void) { - MXC_TRNG_RevB_GenerateKey((mxc_trng_revb_regs_t*) MXC_TRNG); + MXC_TRNG_RevB_GenerateKey((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +int MXC_TRNG_HealthTest(void) +{ + if ((MXC_GCR->revision & 0xF0) == 0xA0) { // ME15 Rev. A does not support health tests. + return E_NOT_SUPPORTED; + } + + return MXC_TRNG_RevB_HealthTest((mxc_trng_revb_regs_t *)MXC_TRNG); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb.c index b739fe4..0ba09f3 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb.c @@ -1,8 +1,8 @@ -/* **************************************************************************** - * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include #include @@ -49,7 +49,7 @@ static mxc_trng_complete_t MXC_TRNG_Callback; static uint32_t TRNG_count, TRNG_maxLength; -static uint8_t* TRNG_data; +static uint8_t *TRNG_data; /* ************************************************************************* */ /* Global Control/Configuration functions */ @@ -60,12 +60,12 @@ return E_NO_ERROR; } -void MXC_TRNG_RevB_EnableInt(mxc_trng_revb_regs_t* trng) +void MXC_TRNG_RevB_EnableInt(mxc_trng_revb_regs_t *trng) { trng->ctrl |= MXC_F_TRNG_REVB_CTRL_RND_IE; } -void MXC_TRNG_RevB_DisableInt(mxc_trng_revb_regs_t* trng) +void MXC_TRNG_RevB_DisableInt(mxc_trng_revb_regs_t *trng) { trng->ctrl &= ~MXC_F_TRNG_REVB_CTRL_RND_IE; } @@ -79,24 +79,23 @@ { uint32_t temp; mxc_trng_complete_t cb; - + // if this is last block, disable interrupt before reading trng->data - if(TRNG_maxLength <= TRNG_count + 4) { + if (TRNG_maxLength <= TRNG_count + 4) { trng->ctrl &= ~MXC_F_TRNG_REVB_CTRL_RND_IE; } - + temp = trng->data; - - if((TRNG_count + 3) < TRNG_maxLength) { - memcpy(&(TRNG_data[TRNG_count]), (uint8_t*)(&temp), 4); + + if ((TRNG_count + 3) < TRNG_maxLength) { + memcpy(&(TRNG_data[TRNG_count]), (uint8_t *)(&temp), 4); TRNG_count += 4; - } - else { - memcpy(&(TRNG_data[TRNG_count]), (uint8_t*)(&temp), TRNG_maxLength & 0x03); + } else { + memcpy(&(TRNG_data[TRNG_count]), (uint8_t *)(&temp), TRNG_maxLength & 0x03); TRNG_count += (TRNG_maxLength & 0x03); } - - if(TRNG_maxLength == TRNG_count) { + + if (TRNG_maxLength == TRNG_count) { cb = MXC_TRNG_Callback; cb(0, 0); } @@ -106,55 +105,78 @@ /* True Random Number Generator(TRNG) functions */ /* ************************************************************************* */ -int MXC_TRNG_RevB_RandomInt(mxc_trng_revb_regs_t* trng) +int MXC_TRNG_RevB_RandomInt(mxc_trng_revb_regs_t *trng) { - while(!(trng->status & MXC_F_TRNG_REVB_STATUS_RDY)); - - return (int) trng->data; + while (!(trng->status & MXC_F_TRNG_REVB_STATUS_RDY)) {} + + return (int)trng->data; } -int MXC_TRNG_RevB_Random(uint8_t* data, uint32_t len) +int MXC_TRNG_RevB_Random(uint8_t *data, uint32_t len) { unsigned int i, temp; - - if(data == NULL) { + + if (data == NULL) { return E_NULL_PTR; } - - for(i = 0; (i + 3) < len; i+=4) { + + for (i = 0; (i + 3) < len; i += 4) { temp = MXC_TRNG_RandomInt(); - memcpy(&(data[i]), (uint8_t*)(&temp), 4); + memcpy(&(data[i]), (uint8_t *)(&temp), 4); } - - if(len & 0x03) { + + if (len & 0x03) { temp = MXC_TRNG_RandomInt(); - memcpy(&(data[i]), (uint8_t*)(&temp), len & 0x03); + memcpy(&(data[i]), (uint8_t *)(&temp), len & 0x03); } - + return E_NO_ERROR; } -void MXC_TRNG_RevB_RandomAsync(mxc_trng_revb_regs_t* trng, uint8_t* data, uint32_t len, mxc_trng_complete_t callback) +void MXC_TRNG_RevB_RandomAsync(mxc_trng_revb_regs_t *trng, uint8_t *data, uint32_t len, + mxc_trng_complete_t callback) { MXC_ASSERT(data && callback); - - if(len == 0) { + + if (len == 0) { return; } - + TRNG_data = data; TRNG_count = 0; TRNG_maxLength = len; MXC_TRNG_Callback = callback; - + // Enable interrupts trng->ctrl |= MXC_F_TRNG_REVB_CTRL_RND_IE; } -void MXC_TRNG_RevB_GenerateKey(mxc_trng_revb_regs_t* trng) +void MXC_TRNG_RevB_GenerateKey(mxc_trng_revb_regs_t *trng) { - /*Generate AES Key */ - trng->ctrl |= MXC_F_TRNG_REVB_CTRL_KEYGEN; + // Generate AES Key + trng->ctrl |= MXC_F_TRNG_REVB_CTRL_AESKG_USR; - while(trng->ctrl & MXC_F_TRNG_REVB_CTRL_KEYGEN); -} \ No newline at end of file + // Wait for key transfer to complete + while (trng->status & MXC_F_TRNG_REVB_STATUS_AESKGD) {}; +} + +int MXC_TRNG_RevB_HealthTest(mxc_trng_revb_regs_t *trng) +{ + /* Clear on-going test if necessary */ + if (trng->ctrl & MXC_F_TRNG_REVB_CTRL_ODHT) { + trng->ctrl &= ~MXC_F_TRNG_REVB_CTRL_ODHT; + while (trng->status & MXC_F_TRNG_REVB_STATUS_ODHT) {} + } + + /* Start on-demand health test */ + trng->ctrl |= MXC_F_TRNG_REVB_CTRL_ODHT; + + /* Wait for test to finish */ + while (trng->status & MXC_F_TRNG_REVB_STATUS_ODHT) {} + + /* Check results of test */ + if (trng->status & MXC_F_TRNG_REVB_STATUS_HT) { + return E_BAD_STATE; + } + return E_NO_ERROR; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb.h index 0d8d11b..9ccad3e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TRNG_TRNG_REVB_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_TRNG_TRNG_REVB_H_ #include "trng.h" #include "trng_revb_regs.h" @@ -39,11 +42,15 @@ /* ************************************************************************* */ int MXC_TRNG_RevB_Init(void); -void MXC_TRNG_RevB_EnableInt(mxc_trng_revb_regs_t* trng); -void MXC_TRNG_RevB_DisableInt(mxc_trng_revb_regs_t* trng); +void MXC_TRNG_RevB_EnableInt(mxc_trng_revb_regs_t *trng); +void MXC_TRNG_RevB_DisableInt(mxc_trng_revb_regs_t *trng); int MXC_TRNG_RevB_Shutdown(void); -void MXC_TRNG_RevB_Handler(mxc_trng_revb_regs_t* trng); -int MXC_TRNG_RevB_RandomInt(mxc_trng_revb_regs_t* trng); -int MXC_TRNG_RevB_Random(uint8_t* data, uint32_t len); -void MXC_TRNG_RevB_RandomAsync(mxc_trng_revb_regs_t* trng, uint8_t* data, uint32_t len, mxc_trng_complete_t callback); -void MXC_TRNG_RevB_GenerateKey(mxc_trng_revb_regs_t* trng); +void MXC_TRNG_RevB_Handler(mxc_trng_revb_regs_t *trng); +int MXC_TRNG_RevB_RandomInt(mxc_trng_revb_regs_t *trng); +int MXC_TRNG_RevB_Random(uint8_t *data, uint32_t len); +void MXC_TRNG_RevB_RandomAsync(mxc_trng_revb_regs_t *trng, uint8_t *data, uint32_t len, + mxc_trng_complete_t callback); +void MXC_TRNG_RevB_GenerateKey(mxc_trng_revb_regs_t *trng); +int MXC_TRNG_RevB_HealthTest(mxc_trng_revb_regs_t *trng); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TRNG_TRNG_REVB_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb_regs.h index ac30824..86d238b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TRNG/trng_revb_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the TRNG_REVB Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _TRNG_REVB_REGS_H_ #define _TRNG_REVB_REGS_H_ @@ -46,11 +45,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -87,7 +86,7 @@ */ typedef struct { __IO uint32_t ctrl; /**< \b 0x00: TRNG_REVB CTRL Register */ - __I uint32_t status; /**< \b 0x04: TRNG_REVB STATUS Register */ + __IO uint32_t status; /**< \b 0x04: TRNG_REVB STATUS Register */ __I uint32_t data; /**< \b 0x08: TRNG_REVB DATA Register */ } mxc_trng_revb_regs_t; @@ -95,7 +94,7 @@ /** * @ingroup trng_revb_registers * @defgroup TRNG_REVB_Register_Offsets Register Offsets - * @brief TRNG_REVB Peripheral Register Offsets from the TRNG_REVB Base Peripheral Address. + * @brief TRNG_REVB Peripheral Register Offsets from the TRNG_REVB Base Peripheral Address. * @{ */ #define MXC_R_TRNG_REVB_CTRL ((uint32_t)0x00000000UL) /**< Offset from TRNG_REVB Base Address: 0x0000 */ @@ -109,11 +108,20 @@ * @brief TRNG Control Register. * @{ */ + #define MXC_F_TRNG_REVB_CTRL_ODHT_POS 0 /**< CTRL_ODHT Position */ + #define MXC_F_TRNG_REVB_CTRL_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_ODHT_POS)) /**< CTRL_ODHT Mask */ + #define MXC_F_TRNG_REVB_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */ #define MXC_F_TRNG_REVB_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */ - #define MXC_F_TRNG_REVB_CTRL_KEYGEN_POS 3 /**< CTRL_KEYGEN Position */ - #define MXC_F_TRNG_REVB_CTRL_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_KEYGEN_POS)) /**< CTRL_KEYGEN Mask */ + #define MXC_F_TRNG_REVB_CTRL_HEALTH_EN_POS 2 /**< CTRL_HEALTH_EN Position */ + #define MXC_F_TRNG_REVB_CTRL_HEALTH_EN ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_HEALTH_EN_POS)) /**< CTRL_HEALTH_EN Mask */ + + #define MXC_F_TRNG_REVB_CTRL_AESKG_USR_POS 3 /**< CTRL_AESKG_USR Position */ + #define MXC_F_TRNG_REVB_CTRL_AESKG_USR ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_AESKG_USR_POS)) /**< CTRL_AESKG_USR Mask */ + + #define MXC_F_TRNG_REVB_CTRL_AESKG_SYS_POS 4 /**< CTRL_AESKG_SYS Position */ + #define MXC_F_TRNG_REVB_CTRL_AESKG_SYS ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_AESKG_SYS_POS)) /**< CTRL_AESKG_SYS Mask */ #define MXC_F_TRNG_REVB_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */ #define MXC_F_TRNG_REVB_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */ @@ -130,6 +138,21 @@ #define MXC_F_TRNG_REVB_STATUS_RDY_POS 0 /**< STATUS_RDY Position */ #define MXC_F_TRNG_REVB_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_STATUS_RDY_POS)) /**< STATUS_RDY Mask */ + #define MXC_F_TRNG_REVB_STATUS_ODHT_POS 1 /**< STATUS_ODHT Position */ + #define MXC_F_TRNG_REVB_STATUS_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_STATUS_ODHT_POS)) /**< STATUS_ODHT Mask */ + + #define MXC_F_TRNG_REVB_STATUS_HT_POS 2 /**< STATUS_HT Position */ + #define MXC_F_TRNG_REVB_STATUS_HT ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_STATUS_HT_POS)) /**< STATUS_HT Mask */ + + #define MXC_F_TRNG_REVB_STATUS_SRCFAIL_POS 3 /**< STATUS_SRCFAIL Position */ + #define MXC_F_TRNG_REVB_STATUS_SRCFAIL ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_STATUS_SRCFAIL_POS)) /**< STATUS_SRCFAIL Mask */ + + #define MXC_F_TRNG_REVB_STATUS_AESKGD_POS 4 /**< STATUS_AESKGD Position */ + #define MXC_F_TRNG_REVB_STATUS_AESKGD ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_STATUS_AESKGD_POS)) /**< STATUS_AESKGD Mask */ + + #define MXC_F_TRNG_REVB_STATUS_LD_CNT_POS 24 /**< STATUS_LD_CNT Position */ + #define MXC_F_TRNG_REVB_STATUS_LD_CNT ((uint32_t)(0xFFUL << MXC_F_TRNG_REVB_STATUS_LD_CNT_POS)) /**< STATUS_LD_CNT Mask */ + /**@} end of group TRNG_REVB_STATUS_Register */ /** diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_common.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_common.c index 94916d1..692126b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_common.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,25 +29,25 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include "uart_common.h" #include "uart.h" -int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t* uart) +int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t *uart) { // Wait until FIFO has a character ready. - while (MXC_UART_GetRXFIFOAvailable(uart) < 1); - + while (MXC_UART_GetRXFIFOAvailable(uart) < 1) {} + // Read the character using the non-blocking function. return MXC_UART_ReadCharacterRaw(uart); } -int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character) +int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character) { // Wait until FIFO has space for the character. - while (MXC_UART_GetTXFIFOAvailable(uart) < 1); - + while (MXC_UART_GetTXFIFOAvailable(uart) < 1) {} + // Write the character using the non-blocking function. return MXC_UART_WriteCharacterRaw(uart, character); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_common.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_common.h index 8918a6a..d1e95ec 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_common.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_common.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,10 +29,14 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_ #include "uart_regs.h" -int MXC_UART_Common_ReadCharacter (mxc_uart_regs_t* uart); -int MXC_UART_Common_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character); +int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t *uart); +int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_me15.c index 691ed1f..85ef30d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_me15.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,10 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ -#ifdef __CC_ARM // Keil -#pragma diag_suppress 68 // integer conversion resulted in a change of sign -#endif + ******************************************************************************/ #include "uart.h" #include "mxc_device.h" @@ -43,56 +40,60 @@ #include "mcr_regs.h" #include "dma.h" -void MXC_UART_DMACallback (int ch, int error) +void MXC_UART_DMACallback(int ch, int error) { - MXC_UART_RevB_DMACallback (ch, error); + MXC_UART_RevB_DMACallback(ch, error); } -int MXC_UART_AsyncCallback(mxc_uart_regs_t* uart, int retVal) +int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal) { - return MXC_UART_RevB_AsyncCallback ((mxc_uart_revb_regs_t*) uart, retVal); + return MXC_UART_RevB_AsyncCallback((mxc_uart_revb_regs_t *)uart, retVal); } -int MXC_UART_AsyncStop(mxc_uart_regs_t* uart) +int MXC_UART_AsyncStop(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AsyncStop ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_AsyncStop((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_Init(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clock, sys_map_t map) +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock, sys_map_t map) { int retval; - + retval = MXC_UART_Shutdown(uart); - + if (retval) { return retval; } - + switch (clock) { case MXC_UART_EXT_CLK: - MXC_GPIO_Config(&gpio_cfg_extclk); + if (uart == MXC_UART3) { + MXC_GPIO_Config(&gpio_cfg_lpextclk); + } else { + MXC_GPIO_Config(&gpio_cfg_hfextclk); + } break; - + case MXC_UART_ERTCO_CLK: MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); break; - + case MXC_UART_IBRO_CLK: MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); break; - + case MXC_UART_ERFO_CLK: MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERFO); break; case MXC_UART_INRO_CLK: - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO); - break; + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO); + break; default: break; } - + switch (MXC_UART_GET_IDX(uart)) { case 0: if (map == MAP_B) { @@ -102,7 +103,7 @@ } MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART0); break; - + case 1: if (map == MAP_B) { MXC_GPIO_Config(&gpio_cfg_uart1b); @@ -116,245 +117,185 @@ MXC_GPIO_Config(&gpio_cfg_uart2b); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART2); break; - + case 3: MXC_GPIO_Config(&gpio_cfg_uart3); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART3); + MXC_MCR->lppioctrl |= MXC_F_MCR_LPPIOCTRL_LPUART0_RX | MXC_F_MCR_LPPIOCTRL_LPUART0_TX | + MXC_F_MCR_LPPIOCTRL_LPUART0_RTS | MXC_F_MCR_LPPIOCTRL_LPUART0_CTS; break; default: return E_NOT_SUPPORTED; } - - return MXC_UART_RevB_Init ((mxc_uart_revb_regs_t*) uart, baud, (mxc_uart_revb_clock_t)clock); + + return MXC_UART_RevB_Init((mxc_uart_revb_regs_t *)uart, baud, clock); } -int MXC_UART_Shutdown(mxc_uart_regs_t* uart) +int MXC_UART_Shutdown(mxc_uart_regs_t *uart) { switch (MXC_UART_GET_IDX(uart)) { case 0: MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART0); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART0); break; - + case 1: MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART1); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART1); break; - - case 2: + + case 2: MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART2); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART2); break; - + case 3: MXC_SYS_Reset_Periph(MXC_SYS_RESET_UART3); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART3); + MXC_MCR->lppioctrl |= ~(MXC_F_MCR_LPPIOCTRL_LPUART0_RX | MXC_F_MCR_LPPIOCTRL_LPUART0_TX | + MXC_F_MCR_LPPIOCTRL_LPUART0_RTS | MXC_F_MCR_LPPIOCTRL_LPUART0_CTS); break; default: return E_NOT_SUPPORTED; } - + return E_NO_ERROR; } -int MXC_UART_ReadyForSleep(mxc_uart_regs_t* uart) +int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ReadyForSleep ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_ReadyForSleep((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_SetFrequency(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clock) +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) { int freq; - unsigned int mod = 0; - unsigned int clkdiv = 0; + int mod = 0; + int clkdiv = 0; int div = 8; - if (MXC_UART_GET_IDX (uart) < 0) { + if (MXC_UART_GET_IDX(uart) < 0) { return E_BAD_PARAM; } // check if the uart is LPUART - if(uart == MXC_UART3) { + if (uart == MXC_UART3) { // OSR default value uart->osr = 5; - + switch (clock) { - case MXC_UART_APB_CLK: - uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK; - div = (1 << (MXC_GCR->pclkdiv & MXC_F_GCR_PCLKDIV_AON_CLKDIV)) * 8; - clkdiv = ((SystemCoreClock / div) / baud); - mod = ((SystemCoreClock / div) % baud); - break; + case MXC_UART_APB_CLK: + uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK; + div = (1 << (MXC_GCR->pclkdiv & MXC_F_GCR_PCLKDIV_AON_CLKDIV)) * 8; + clkdiv = ((SystemCoreClock / div) / baud); + mod = ((SystemCoreClock / div) % baud); + break; - case MXC_UART_EXT_CLK: - uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK; - break; + case MXC_UART_EXT_CLK: + uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK; + clkdiv = EXTCLK_FREQ / baud; + mod = EXTCLK_FREQ % baud; + break; - case MXC_UART_ERTCO_CLK: - uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_CLK2; - uart->ctrl |= MXC_F_UART_CTRL_FDM; - clkdiv = ((ERTCO_FREQ * 2) / baud); - mod = ((ERTCO_FREQ * 2) % baud); + case MXC_UART_ERTCO_CLK: + uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_CLK2; + uart->ctrl |= MXC_F_UART_CTRL_FDM; + clkdiv = ((ERTCO_FREQ * 2) / baud); + mod = ((ERTCO_FREQ * 2) % baud); - if (baud > 2400) { - uart->osr = 0; - } else { - uart->osr = 1; - } - break; + if (baud > 2400) { + uart->osr = 0; + } else { + uart->osr = 1; + } + break; - case MXC_UART_INRO_CLK: - uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_CLK3; - uart->ctrl |= MXC_F_UART_CTRL_FDM; - clkdiv = ((INRO_FREQ * 2) / baud); - mod = ((INRO_FREQ * 2) % baud); + case MXC_UART_INRO_CLK: + uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_CLK3; + uart->ctrl |= MXC_F_UART_CTRL_FDM; + clkdiv = ((INRO_FREQ * 2) / baud); + mod = ((INRO_FREQ * 2) % baud); - if (baud > 2400) { - uart->osr = 0; - } else { - uart->osr = 1; - } - break; + if (baud > 2400) { + uart->osr = 0; + } else { + uart->osr = 1; + } + break; - default: - return E_BAD_PARAM; + default: + return E_BAD_PARAM; } - if(!clkdiv || mod > (baud / 2)) { + if (!clkdiv || mod > (baud / 2)) { clkdiv++; } uart->clkdiv = clkdiv; - freq = MXC_UART_GetFrequency (uart); - } - else { - unsigned int clkDiv = 0, mod = 0; - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { - return E_BAD_PARAM; - } - - // OSR default value - uart->osr = 5; + freq = MXC_UART_GetFrequency(uart); + } else { + freq = MXC_UART_RevB_SetFrequency((mxc_uart_revb_regs_t *)uart, baud, clock); + } - switch (clock) { - case MXC_UART_REVB_APB_CLK: - clkDiv = (PeripheralClock / baud); - mod = (PeripheralClock % baud); - break; - - case MXC_UART_REVB_EXT_CLK: - uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK; - break; - - //case MXC_UART_IBRO_CLK: - case MXC_UART_REVB_CLK2: - clkDiv = (IBRO_FREQ / baud); - mod = (IBRO_FREQ % baud); - uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2; - break; - - //case MXC_UART_ERFO: - case MXC_UART_REVB_CLK3: - clkDiv = (ERFO_FREQ / baud); - mod = (ERFO_FREQ % baud); - uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3; - break; - - default: - return E_BAD_PARAM; - } - - if(!clkDiv || mod > (baud / 2)) { - clkDiv++; - } - uart->clkdiv = clkDiv; - freq = MXC_UART_GetFrequency ((mxc_uart_regs_t*) uart); - } - if(freq > 0) { + if (freq > 0) { // Enable baud clock and wait for it to become ready. uart->ctrl |= MXC_F_UART_CTRL_BCLKEN; - while(((uart->ctrl & MXC_F_UART_CTRL_BCLKRDY) >> MXC_F_UART_CTRL_BCLKRDY_POS) == 0); - } + while (((uart->ctrl & MXC_F_UART_CTRL_BCLKRDY) >> MXC_F_UART_CTRL_BCLKRDY_POS) == 0) {} + } return freq; } -int MXC_UART_GetFrequency(mxc_uart_regs_t* uart) +int MXC_UART_GetFrequency(mxc_uart_regs_t *uart) { int periphClock = 0; int div = 8; - - if (MXC_UART_GET_IDX (uart) < 0) { + + if (MXC_UART_GET_IDX(uart) < 0) { return E_BAD_PARAM; } // check if UARt is LP UART - if(uart == MXC_UART3) { + if (uart == MXC_UART3) { if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK) { - return E_NOT_SUPPORTED; - } - else if((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK) { + return EXTCLK_FREQ; + } else if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == + MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK) { div = (1 << (MXC_GCR->pclkdiv & MXC_F_GCR_PCLKDIV_AON_CLKDIV)) * 8; periphClock = SystemCoreClock / div; - } - else if((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_CTRL_BCLKSRC_CLK2) { + } else if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_CTRL_BCLKSRC_CLK2) { periphClock = ERTCO_FREQ * 2; - } - else if((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_CTRL_BCLKSRC_CLK3) { + } else if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_CTRL_BCLKSRC_CLK3) { periphClock = INRO_FREQ * 2; - } - else { + } else { return E_BAD_PARAM; } return (periphClock / uart->clkdiv); + } else { + return MXC_UART_RevB_GetFrequency((mxc_uart_revb_regs_t *)uart); } - else { - //return MXC_UART_RevB_GetFrequency ((mxc_uart_revb_regs_t*) uart); - - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { - return E_BAD_PARAM; - } - - if ((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK) { - return E_NOT_SUPPORTED; - } - else if((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK) { - periphClock = PeripheralClock; - } - else if((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2) { - periphClock = IBRO_FREQ; - } - else if((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3) { - periphClock = ERFO_FREQ; - } - else { - return E_BAD_PARAM; - } - - return (periphClock / uart->clkdiv); - } } -int MXC_UART_SetDataSize(mxc_uart_regs_t* uart, int dataSize) +int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize) { - return MXC_UART_RevB_SetDataSize ((mxc_uart_revb_regs_t*) uart, dataSize); + return MXC_UART_RevB_SetDataSize((mxc_uart_revb_regs_t *)uart, dataSize); } -int MXC_UART_SetStopBits(mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits) +int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits) { - return MXC_UART_RevB_SetStopBits ((mxc_uart_revb_regs_t*) uart, stopBits); + return MXC_UART_RevB_SetStopBits((mxc_uart_revb_regs_t *)uart, stopBits); } -int MXC_UART_SetParity(mxc_uart_regs_t* uart, mxc_uart_parity_t parity) +int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity) { - return MXC_UART_RevB_SetParity ((mxc_uart_revb_regs_t*) uart, parity); + return MXC_UART_RevB_SetParity((mxc_uart_revb_regs_t *)uart, parity); } -int MXC_UART_SetFlowCtrl(mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold, sys_map_t map) +int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold, sys_map_t map) { - if(flowCtrl == MXC_UART_FLOW_EN) { + if (flowCtrl == MXC_UART_FLOW_EN) { switch (MXC_UART_GET_IDX(uart)) { case 0: if (map == MAP_B) { @@ -383,8 +324,7 @@ default: return E_BAD_PARAM; } - } - else { + } else { switch (MXC_UART_GET_IDX(uart)) { case 0: if (map == MAP_B) { @@ -412,115 +352,113 @@ default: return E_BAD_PARAM; - } + } } - - return MXC_UART_RevB_SetFlowCtrl ((mxc_uart_revb_regs_t*) uart, flowCtrl, rtsThreshold); + + return MXC_UART_RevB_SetFlowCtrl((mxc_uart_revb_regs_t *)uart, flowCtrl, rtsThreshold); } -int MXC_UART_SetClockSource(mxc_uart_regs_t* uart, mxc_uart_clock_t clock) +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock) { - return MXC_UART_RevB_SetClockSource ((mxc_uart_revb_regs_t*) uart, (mxc_uart_revb_clock_t)clock); + return MXC_UART_RevB_SetClockSource((mxc_uart_revb_regs_t *)uart, clock); } -int MXC_UART_GetActive(mxc_uart_regs_t* uart) +int MXC_UART_GetActive(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetActive ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_GetActive((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_AbortTransmission(mxc_uart_regs_t* uart) +int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AbortTransmission ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_AbortTransmission((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t* uart) +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ReadCharacterRaw ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_ReadCharacterRaw((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t* uart, uint8_t character) +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character) { - return MXC_UART_RevB_WriteCharacterRaw ((mxc_uart_revb_regs_t*) uart, character); + return MXC_UART_RevB_WriteCharacterRaw((mxc_uart_revb_regs_t *)uart, character); } -int MXC_UART_ReadCharacter(mxc_uart_regs_t* uart) +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart) { - return MXC_UART_Common_ReadCharacter (uart); + return MXC_UART_Common_ReadCharacter(uart); } -int MXC_UART_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character) +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character) { - return MXC_UART_Common_WriteCharacter (uart, character); + return MXC_UART_Common_WriteCharacter(uart, character); } -int MXC_UART_Read(mxc_uart_regs_t* uart, uint8_t* buffer, int* len) +int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len) { - return MXC_UART_RevB_Read ((mxc_uart_revb_regs_t*) uart, buffer, len); + return MXC_UART_RevB_Read((mxc_uart_revb_regs_t *)uart, buffer, len); } -int MXC_UART_Write(mxc_uart_regs_t* uart, const uint8_t* byte, int* len) +int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len) { - return MXC_UART_RevB_Write ((mxc_uart_revb_regs_t*) uart, byte, len); + return MXC_UART_RevB_Write((mxc_uart_revb_regs_t *)uart, byte, len); } -unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len) +unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) { - return MXC_UART_RevB_ReadRXFIFO ((mxc_uart_revb_regs_t*) uart, bytes, len); - + return MXC_UART_RevB_ReadRXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); } -int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t* uart, unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback) +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; - + int uart_num = MXC_UART_GET_IDX(uart); - + switch (uart_num) { case 0: config.reqsel = MXC_DMA_REQUEST_UART0RX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_UART1RX; break; - + case 2: config.reqsel = MXC_DMA_REQUEST_UART2RX; break; - + default: return E_BAD_PARAM; break; } - return MXC_UART_RevB_ReadRXFIFODMA ((mxc_uart_revb_regs_t*) uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); } -unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t* uart) +unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetRXFIFOAvailable ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_GetRXFIFOAvailable((mxc_uart_revb_regs_t *)uart); } -unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t* uart, const unsigned char* bytes, +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len) { - return MXC_UART_RevB_WriteTXFIFO ((mxc_uart_revb_regs_t*) uart, bytes, len); + return MXC_UART_RevB_WriteTXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); } -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t* uart, const unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback) +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; - + int uart_num = MXC_UART_GET_IDX(uart); - + switch (uart_num) { case 0: config.reqsel = MXC_DMA_REQUEST_UART0TX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_UART1TX; break; @@ -528,108 +466,108 @@ case 2: config.reqsel = MXC_DMA_REQUEST_UART2TX; break; - + default: return E_BAD_PARAM; break; } - return MXC_UART_RevB_WriteTXFIFODMA ((mxc_uart_revb_regs_t*) uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); } -unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t* uart) +unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetTXFIFOAvailable ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_GetTXFIFOAvailable((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_ClearRXFIFO(mxc_uart_regs_t* uart) +int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ClearRXFIFO ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_ClearRXFIFO((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_ClearTXFIFO(mxc_uart_regs_t* uart) +int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ClearTXFIFO ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_ClearTXFIFO((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_SetRXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes) +int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) { - return MXC_UART_RevB_SetRXThreshold ((mxc_uart_revb_regs_t*) uart, numBytes); + return MXC_UART_RevB_SetRXThreshold((mxc_uart_revb_regs_t *)uart, numBytes); } -unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t* uart) +unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetRXThreshold ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_GetRXThreshold((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_SetTXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes) +int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) { // TX threshold is fixed at half the length of FIFO return E_NOT_SUPPORTED; } -unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t* uart) +unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart) { // TX threshold is fixed at half the length of FIFO return E_NOT_SUPPORTED; } -unsigned int MXC_UART_GetFlags(mxc_uart_regs_t* uart) +unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetFlags ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_GetFlags((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_ClearFlags(mxc_uart_regs_t* uart, unsigned int flags) +int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags) { - return MXC_UART_RevB_ClearFlags ((mxc_uart_revb_regs_t*) uart, flags); + return MXC_UART_RevB_ClearFlags((mxc_uart_revb_regs_t *)uart, flags); } -int MXC_UART_EnableInt(mxc_uart_regs_t* uart, unsigned int mask) +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask) { - return MXC_UART_RevB_EnableInt ((mxc_uart_revb_regs_t*) uart, mask); + return MXC_UART_RevB_EnableInt((mxc_uart_revb_regs_t *)uart, mask); } -int MXC_UART_DisableInt(mxc_uart_regs_t* uart, unsigned int mask) +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask) { - return MXC_UART_RevB_DisableInt ((mxc_uart_revb_regs_t*) uart, mask); + return MXC_UART_RevB_DisableInt((mxc_uart_revb_regs_t *)uart, mask); } -unsigned int MXC_UART_GetStatus(mxc_uart_regs_t* uart) +unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetStatus ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_GetStatus((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_Transaction(mxc_uart_req_t* req) +int MXC_UART_Transaction(mxc_uart_req_t *req) { - return MXC_UART_RevB_Transaction ((mxc_uart_revb_req_t*) req); + return MXC_UART_RevB_Transaction((mxc_uart_revb_req_t *)req); } -int MXC_UART_TransactionAsync(mxc_uart_req_t* req) +int MXC_UART_TransactionAsync(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionAsync ((mxc_uart_revb_req_t*) req); + return MXC_UART_RevB_TransactionAsync((mxc_uart_revb_req_t *)req); } -int MXC_UART_TransactionDMA(mxc_uart_req_t* req) +int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA ((mxc_uart_revb_req_t*) req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); } -int MXC_UART_AbortAsync(mxc_uart_regs_t* uart) +int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AbortAsync ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_AbortAsync((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_AsyncHandler(mxc_uart_regs_t* uart) +int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AsyncHandler ((mxc_uart_revb_regs_t*) uart); + return MXC_UART_RevB_AsyncHandler((mxc_uart_revb_regs_t *)uart); } -uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t* req) +uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req) { - return req->txCnt; + return req->txCnt; } -uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t* req) +uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req) { - return req->rxCnt; + return req->rxCnt; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb.c index e60f693..3efa096 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ #include #include "mxc_device.h" @@ -39,17 +39,15 @@ #include "dma.h" /* **** Definitions **** */ -#define MXC_UART_REVB_ERRINT_EN (MXC_F_UART_REVB_INT_EN_RX_FERR | \ - MXC_F_UART_REVB_INT_EN_RX_PAR | \ - MXC_F_UART_REVB_INT_EN_RX_OV) +#define MXC_UART_REVB_ERRINT_EN \ + (MXC_F_UART_REVB_INT_EN_RX_FERR | MXC_F_UART_REVB_INT_EN_RX_PAR | MXC_F_UART_REVB_INT_EN_RX_OV) -#define MXC_UART_REVB_ERRINT_FL (MXC_F_UART_REVB_INT_FL_RX_FERR | \ - MXC_F_UART_REVB_INT_FL_RX_PAR | \ - MXC_F_UART_REVB_INT_FL_RX_OV) +#define MXC_UART_REVB_ERRINT_FL \ + (MXC_F_UART_REVB_INT_FL_RX_FERR | MXC_F_UART_REVB_INT_FL_RX_PAR | MXC_F_UART_REVB_INT_FL_RX_OV) /* **** Variable Declaration **** */ -static void* AsyncTxRequests[MXC_UART_INSTANCES]; -static void* AsyncRxRequests[MXC_UART_INSTANCES]; +static void *AsyncTxRequests[MXC_UART_INSTANCES]; +static void *AsyncRxRequests[MXC_UART_INSTANCES]; typedef struct { mxc_uart_revb_req_t *req; @@ -64,167 +62,174 @@ /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_UART_RevB_Init (mxc_uart_revb_regs_t* uart, unsigned int baud, mxc_uart_revb_clock_t clock) +int MXC_UART_RevB_Init(mxc_uart_revb_regs_t *uart, unsigned int baud, mxc_uart_revb_clock_t clock) { - int err; + int err; - if(MXC_UART_GET_IDX((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } // Initialize UART - if((err = MXC_UART_SetRXThreshold ((mxc_uart_regs_t*) uart, 1)) != E_NO_ERROR) { // Set RX threshold to 1 byte - return err; - } - - if((err = MXC_UART_SetDataSize ((mxc_uart_regs_t*) uart, 8)) != E_NO_ERROR) { // Set Datasize to 8 bits + if ((err = MXC_UART_SetRXThreshold((mxc_uart_regs_t *)uart, 1)) != + E_NO_ERROR) { // Set RX threshold to 1 byte return err; } - if((err = MXC_UART_SetParity ((mxc_uart_regs_t*) uart, MXC_UART_PARITY_DISABLE)) != E_NO_ERROR) { - return err; - } - - if((err = MXC_UART_SetStopBits ((mxc_uart_regs_t*) uart, MXC_UART_STOP_1)) != E_NO_ERROR) { + if ((err = MXC_UART_SetDataSize((mxc_uart_regs_t *)uart, 8)) != + E_NO_ERROR) { // Set Datasize to 8 bits return err; } - if((err = MXC_UART_SetFrequency ((mxc_uart_regs_t*) uart, baud, (mxc_uart_clock_t) clock)) < E_NO_ERROR) { - return err; + if ((err = MXC_UART_SetParity((mxc_uart_regs_t *)uart, MXC_UART_PARITY_DISABLE)) != + E_NO_ERROR) { + return err; + } + + if ((err = MXC_UART_SetStopBits((mxc_uart_regs_t *)uart, MXC_UART_STOP_1)) != E_NO_ERROR) { + return err; + } + + if ((err = MXC_UART_SetFrequency((mxc_uart_regs_t *)uart, baud, (mxc_uart_clock_t)clock)) < + E_NO_ERROR) { + return err; } return E_NO_ERROR; } -int MXC_UART_RevB_ReadyForSleep (mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_ReadyForSleep(mxc_uart_revb_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - - if (AsyncTxRequests[MXC_UART_GET_IDX((mxc_uart_regs_t*) uart)] != NULL) { + + if (AsyncTxRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)] != NULL) { return E_BUSY; } - if (AsyncRxRequests[MXC_UART_GET_IDX((mxc_uart_regs_t*) uart)] != NULL) { + if (AsyncRxRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)] != NULL) { return E_BUSY; } - return MXC_UART_GetActive ((mxc_uart_regs_t*) uart); + return MXC_UART_GetActive((mxc_uart_regs_t *)uart); } -int MXC_UART_RevB_SetFrequency (mxc_uart_revb_regs_t* uart, unsigned int baud, mxc_uart_revb_clock_t clock) -{ - unsigned int clkDiv = 0, mod = 0; - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { +int MXC_UART_RevB_SetFrequency(mxc_uart_revb_regs_t *uart, unsigned int baud, + mxc_uart_revb_clock_t clock) +{ + unsigned clkDiv = 0, mod = 0; + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + // OSR default value uart->osr = 5; switch (clock) { - case MXC_UART_REVB_APB_CLK: - clkDiv = (PeripheralClock / baud); - mod = (PeripheralClock % baud); - break; + case MXC_UART_REVB_APB_CLK: + clkDiv = (PeripheralClock / baud); + mod = (PeripheralClock % baud); + break; - case MXC_UART_REVB_EXT_CLK: - uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK; - break; + case MXC_UART_REVB_EXT_CLK: + uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK; + clkDiv = UART_EXTCLK_FREQ / baud; + mod = UART_EXTCLK_FREQ % baud; + break; - //case MXC_UART_IBRO_CLK: - case MXC_UART_REVB_CLK2: - clkDiv = (IBRO_FREQ / baud); - mod = (IBRO_FREQ % baud); + //case MXC_UART_IBRO_CLK: + case MXC_UART_REVB_CLK2: + clkDiv = (IBRO_FREQ / baud); + mod = (IBRO_FREQ % baud); - uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2; - break; + uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2; + break; - //case MXC_UART_ERFO: - case MXC_UART_REVB_CLK3: - #if (TARGET_NUM == 78000 || TARGET_NUM == 78002) - return E_BAD_PARAM; - #else - clkDiv = (ERFO_FREQ / baud); - mod = (ERFO_FREQ % baud); - #endif + //case MXC_UART_ERFO: + case MXC_UART_REVB_CLK3: +#if (TARGET_NUM == 78000 || TARGET_NUM == 78002) + return E_BAD_PARAM; +#else + clkDiv = (ERFO_FREQ / baud); + mod = (ERFO_FREQ % baud); +#endif - uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3; - break; + uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3; + break; - default: - return E_BAD_PARAM; + default: + return E_BAD_PARAM; } - - if(!clkDiv || mod > (baud / 2)) { + + if (!clkDiv || mod > (baud / 2)) { clkDiv++; } uart->clkdiv = clkDiv; - return MXC_UART_GetFrequency ((mxc_uart_regs_t*) uart); + return MXC_UART_GetFrequency((mxc_uart_regs_t *)uart); } -int MXC_UART_RevB_GetFrequency (mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_GetFrequency(mxc_uart_revb_regs_t *uart) { int periphClock = 0; - - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - if ((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK) { - return E_NOT_SUPPORTED; - } - else if((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK) { + if ((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == + MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK) { + periphClock = UART_EXTCLK_FREQ; + } else if ((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == + MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK) { periphClock = PeripheralClock; - } - else if((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2) { - periphClock = 7372800; - } - else if((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3) { - #if (TARGET_NUM == 78000 || TARGET_NUM == 78002) + } else if ((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2) { + periphClock = IBRO_FREQ; + } else if ((uart->ctrl & MXC_F_UART_REVB_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3) { +#if (TARGET_NUM == 78000 || TARGET_NUM == 78002) return E_BAD_PARAM; - #else +#else periphClock = ERFO_FREQ; - #endif - } - else { +#endif + } else { return E_BAD_PARAM; } return (periphClock / uart->clkdiv); } -int MXC_UART_RevB_SetDataSize (mxc_uart_revb_regs_t* uart, int dataSize) +int MXC_UART_RevB_SetDataSize(mxc_uart_revb_regs_t *uart, int dataSize) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } if (dataSize < 5 || dataSize > 8) { return E_BAD_PARAM; } - - dataSize = (dataSize-5) << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS; - - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_CHAR_SIZE, dataSize); - + + dataSize = (dataSize - 5) << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS; + + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_CHAR_SIZE, dataSize); + return E_NO_ERROR; } -int MXC_UART_RevB_SetStopBits (mxc_uart_revb_regs_t* uart, mxc_uart_stop_t stopBits) +int MXC_UART_RevB_SetStopBits(mxc_uart_revb_regs_t *uart, mxc_uart_stop_t stopBits) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } switch (stopBits) { case MXC_UART_STOP_1: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_STOPBITS, 0 << MXC_F_UART_REVB_CTRL_STOPBITS_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_STOPBITS, + 0 << MXC_F_UART_REVB_CTRL_STOPBITS_POS); break; - + case MXC_UART_STOP_2: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_STOPBITS, 1 << MXC_F_UART_REVB_CTRL_STOPBITS_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_STOPBITS, + 1 << MXC_F_UART_REVB_CTRL_STOPBITS_POS); break; default: @@ -235,39 +240,39 @@ return E_NO_ERROR; } -int MXC_UART_RevB_SetParity (mxc_uart_revb_regs_t* uart, mxc_uart_parity_t parity) +int MXC_UART_RevB_SetParity(mxc_uart_revb_regs_t *uart, mxc_uart_parity_t parity) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } switch (parity) { case MXC_UART_PARITY_DISABLE: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EN, 0 << MXC_F_UART_REVB_CTRL_PAR_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EN, 0 << MXC_F_UART_REVB_CTRL_PAR_EN_POS); break; case MXC_UART_PARITY_EVEN_0: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EN, 1 << MXC_F_UART_REVB_CTRL_PAR_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EO, 0 << MXC_F_UART_REVB_CTRL_PAR_EO_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_MD, 0 << MXC_F_UART_REVB_CTRL_PAR_MD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EN, 1 << MXC_F_UART_REVB_CTRL_PAR_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EO, 0 << MXC_F_UART_REVB_CTRL_PAR_EO_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_MD, 0 << MXC_F_UART_REVB_CTRL_PAR_MD_POS); break; - + case MXC_UART_PARITY_EVEN_1: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EN, 1 << MXC_F_UART_REVB_CTRL_PAR_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EO, 0 << MXC_F_UART_REVB_CTRL_PAR_EO_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_MD, 1 << MXC_F_UART_REVB_CTRL_PAR_MD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EN, 1 << MXC_F_UART_REVB_CTRL_PAR_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EO, 0 << MXC_F_UART_REVB_CTRL_PAR_EO_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_MD, 1 << MXC_F_UART_REVB_CTRL_PAR_MD_POS); break; - + case MXC_UART_PARITY_ODD_0: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EN, 1 << MXC_F_UART_REVB_CTRL_PAR_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EO, 1 << MXC_F_UART_REVB_CTRL_PAR_EO_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_MD, 0 << MXC_F_UART_REVB_CTRL_PAR_MD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EN, 1 << MXC_F_UART_REVB_CTRL_PAR_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EO, 1 << MXC_F_UART_REVB_CTRL_PAR_EO_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_MD, 0 << MXC_F_UART_REVB_CTRL_PAR_MD_POS); break; - + case MXC_UART_PARITY_ODD_1: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EN, 1 << MXC_F_UART_REVB_CTRL_PAR_EN_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EO, 1 << MXC_F_UART_REVB_CTRL_PAR_EO_POS); - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_MD, 1 << MXC_F_UART_REVB_CTRL_PAR_MD_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EN, 1 << MXC_F_UART_REVB_CTRL_PAR_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_EO, 1 << MXC_F_UART_REVB_CTRL_PAR_EO_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_PAR_MD, 1 << MXC_F_UART_REVB_CTRL_PAR_MD_POS); break; default: @@ -278,19 +283,20 @@ return E_NO_ERROR; } -int MXC_UART_RevB_SetFlowCtrl (mxc_uart_revb_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) +int MXC_UART_RevB_SetFlowCtrl(mxc_uart_revb_regs_t *uart, mxc_uart_flow_t flowCtrl, + int rtsThreshold) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } switch (flowCtrl) { case MXC_UART_FLOW_DIS: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_HFC_EN, 0 << MXC_F_UART_REVB_CTRL_HFC_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_HFC_EN, 0 << MXC_F_UART_REVB_CTRL_HFC_EN_POS); break; - + case MXC_UART_FLOW_EN: - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_HFC_EN, 1 << MXC_F_UART_REVB_CTRL_HFC_EN_POS); + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_HFC_EN, 1 << MXC_F_UART_REVB_CTRL_HFC_EN_POS); break; default: @@ -299,45 +305,45 @@ } //FIXME: Fix missing code for CTS threshhold. - + return E_NO_ERROR; } -int MXC_UART_RevB_SetClockSource (mxc_uart_revb_regs_t* uart, mxc_uart_revb_clock_t clock) +int MXC_UART_RevB_SetClockSource(mxc_uart_revb_regs_t *uart, mxc_uart_revb_clock_t clock) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + switch (clock) { - case MXC_UART_REVB_APB_CLK: + case MXC_UART_REVB_APB_CLK: break; - case MXC_UART_REVB_EXT_CLK: + case MXC_UART_REVB_EXT_CLK: uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK; break; - case MXC_UART_REVB_CLK2: + case MXC_UART_REVB_CLK2: uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2; break; - case MXC_UART_REVB_CLK3: + case MXC_UART_REVB_CLK3: uart->ctrl |= MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3; break; - default: + default: return E_BAD_PARAM; } return E_NO_ERROR; } -int MXC_UART_RevB_GetActive (mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_GetActive(mxc_uart_revb_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + if (uart->status & (MXC_F_UART_REVB_STATUS_TX_BUSY | MXC_F_UART_REVB_STATUS_RX_BUSY)) { return E_BUSY; } @@ -345,15 +351,15 @@ return E_NO_ERROR; } -int MXC_UART_RevB_AbortTransmission (mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_AbortTransmission(mxc_uart_revb_regs_t *uart) { - MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*) uart); + MXC_UART_ClearTXFIFO((mxc_uart_regs_t *)uart); return E_NO_ERROR; } -int MXC_UART_RevB_ReadCharacterRaw(mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_ReadCharacterRaw(mxc_uart_revb_regs_t *uart) { - if (MXC_UART_GET_IDX((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } @@ -364,9 +370,9 @@ return uart->fifo; } -int MXC_UART_RevB_WriteCharacterRaw(mxc_uart_revb_regs_t* uart, uint8_t character) +int MXC_UART_RevB_WriteCharacterRaw(mxc_uart_revb_regs_t *uart, uint8_t character) { - if (MXC_UART_GET_IDX((mxc_uart_regs_t*)uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } @@ -381,12 +387,12 @@ return E_NO_ERROR; } -int MXC_UART_RevB_ReadCharacter (mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_ReadCharacter(mxc_uart_revb_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - + if (uart->status & MXC_F_UART_REVB_STATUS_RX_EM) { return E_UNDERFLOW; } @@ -394,9 +400,9 @@ return uart->fifo; } -int MXC_UART_RevB_WriteCharacter (mxc_uart_revb_regs_t* uart, uint8_t character) +int MXC_UART_RevB_WriteCharacter(mxc_uart_revb_regs_t *uart, uint8_t character) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } @@ -411,12 +417,12 @@ return E_NO_ERROR; } -int MXC_UART_RevB_Read (mxc_uart_revb_regs_t* uart, uint8_t* buffer, int* len) +int MXC_UART_RevB_Read(mxc_uart_revb_regs_t *uart, uint8_t *buffer, int *len) { int read = 0; int retVal; - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } @@ -429,13 +435,12 @@ } for (; read < *len; read++) { - retVal = MXC_UART_ReadCharacter ((mxc_uart_regs_t*) uart); - + retVal = MXC_UART_ReadCharacter((mxc_uart_regs_t *)uart); + if (retVal < 0) { *len = read; return retVal; - } - else { + } else { buffer[read] = retVal; } } @@ -444,12 +449,12 @@ return E_NO_ERROR; } -int MXC_UART_RevB_Write (mxc_uart_revb_regs_t* uart, const uint8_t* byte, int* len) +int MXC_UART_RevB_Write(mxc_uart_revb_regs_t *uart, const uint8_t *byte, int *len) { int written = 0; int retVal; - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } @@ -462,8 +467,8 @@ } for (; written < *len; written++) { - retVal = MXC_UART_WriteCharacter ((mxc_uart_regs_t*) uart, byte[written]); - + retVal = MXC_UART_WriteCharacterRaw((mxc_uart_regs_t *)uart, byte[written]); + if (retVal != E_NO_ERROR) { *len = written; return retVal; @@ -474,7 +479,8 @@ return E_NO_ERROR; } -unsigned int MXC_UART_RevB_ReadRXFIFO (mxc_uart_revb_regs_t* uart, unsigned char* bytes, unsigned int len) +unsigned int MXC_UART_RevB_ReadRXFIFO(mxc_uart_revb_regs_t *uart, unsigned char *bytes, + unsigned int len) { unsigned read = 0; @@ -489,12 +495,13 @@ return read; } -unsigned int MXC_UART_RevB_GetRXFIFOAvailable (mxc_uart_revb_regs_t* uart) +unsigned int MXC_UART_RevB_GetRXFIFOAvailable(mxc_uart_revb_regs_t *uart) { return (uart->status & MXC_F_UART_REVB_STATUS_RX_LVL) >> MXC_F_UART_REVB_STATUS_RX_LVL_POS; } -unsigned int MXC_UART_RevB_WriteTXFIFO (mxc_uart_revb_regs_t* uart, const unsigned char* bytes, unsigned int len) +unsigned int MXC_UART_RevB_WriteTXFIFO(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, + unsigned int len) { unsigned written = 0; @@ -509,65 +516,65 @@ return written; } -unsigned int MXC_UART_RevB_GetTXFIFOAvailable (mxc_uart_revb_regs_t* uart) +unsigned int MXC_UART_RevB_GetTXFIFOAvailable(mxc_uart_revb_regs_t *uart) { int txCnt = (uart->status & MXC_F_UART_REVB_STATUS_TX_LVL) >> MXC_F_UART_REVB_STATUS_TX_LVL_POS; return MXC_UART_FIFO_DEPTH - txCnt; } -int MXC_UART_RevB_ClearRXFIFO (mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_ClearRXFIFO(mxc_uart_revb_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } uart->ctrl |= MXC_F_UART_REVB_CTRL_RX_FLUSH; - while (!(uart->status & MXC_F_UART_REVB_STATUS_RX_EM)); + while (!(uart->status & MXC_F_UART_REVB_STATUS_RX_EM)) {} return E_NO_ERROR; } -int MXC_UART_RevB_ClearTXFIFO (mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_ClearTXFIFO(mxc_uart_revb_regs_t *uart) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } uart->ctrl |= MXC_F_UART_REVB_CTRL_TX_FLUSH; - while (uart->ctrl & MXC_F_UART_REVB_CTRL_TX_FLUSH); + while (uart->ctrl & MXC_F_UART_REVB_CTRL_TX_FLUSH) {} return E_NO_ERROR; } -int MXC_UART_RevB_SetRXThreshold (mxc_uart_revb_regs_t* uart, unsigned int numBytes) +int MXC_UART_RevB_SetRXThreshold(mxc_uart_revb_regs_t *uart, unsigned int numBytes) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } if (numBytes < 1 || numBytes > MXC_UART_FIFO_DEPTH) { return E_BAD_PARAM; } - + numBytes <<= MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS; - MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVB_CTRL_RX_THD_VAL, numBytes); - + MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVB_CTRL_RX_THD_VAL, numBytes); + return E_NO_ERROR; } -unsigned int MXC_UART_RevB_GetRXThreshold (mxc_uart_revb_regs_t* uart) +unsigned int MXC_UART_RevB_GetRXThreshold(mxc_uart_revb_regs_t *uart) { return ((uart->ctrl & MXC_F_UART_REVB_CTRL_RX_THD_VAL) >> MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS); } -unsigned int MXC_UART_RevB_GetFlags (mxc_uart_revb_regs_t* uart) +unsigned int MXC_UART_RevB_GetFlags(mxc_uart_revb_regs_t *uart) { return uart->int_fl; } -int MXC_UART_RevB_ClearFlags (mxc_uart_revb_regs_t* uart, unsigned int flags) +int MXC_UART_RevB_ClearFlags(mxc_uart_revb_regs_t *uart, unsigned int flags) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } @@ -576,9 +583,9 @@ return E_NO_ERROR; } -int MXC_UART_RevB_EnableInt (mxc_uart_revb_regs_t* uart, unsigned int intEn) +int MXC_UART_RevB_EnableInt(mxc_uart_revb_regs_t *uart, unsigned int intEn) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } @@ -587,9 +594,9 @@ return E_NO_ERROR; } -int MXC_UART_RevB_DisableInt (mxc_uart_revb_regs_t* uart, unsigned int intDis) +int MXC_UART_RevB_DisableInt(mxc_uart_revb_regs_t *uart, unsigned int intDis) { - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } @@ -598,22 +605,22 @@ return E_NO_ERROR; } -unsigned int MXC_UART_RevB_GetStatus (mxc_uart_revb_regs_t* uart) +unsigned int MXC_UART_RevB_GetStatus(mxc_uart_revb_regs_t *uart) { return uart->status; } -int MXC_UART_RevB_Transaction (mxc_uart_revb_req_t* req) +int MXC_UART_RevB_Transaction(mxc_uart_revb_req_t *req) { uint32_t numToWrite, numToRead; - if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) (req->uart)) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)) < 0) { return E_BAD_PARAM; } - - MXC_UART_DisableInt ((mxc_uart_regs_t*) (req->uart), 0xFFFFFFFF); - MXC_UART_ClearFlags ((mxc_uart_regs_t*) (req->uart), 0xFFFFFFFF); - + + MXC_UART_DisableInt((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); + req->txCnt = 0; req->rxCnt = 0; @@ -627,52 +634,60 @@ if (req->txData == NULL) { return E_BAD_PARAM; } - - numToWrite = MXC_UART_GetTXFIFOAvailable ((mxc_uart_regs_t*) (req->uart)); - numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite; - req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*) (req->uart), &req->txData[req->txCnt], numToWrite); - + + numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite; + req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt], + numToWrite); + while (req->txCnt < req->txLen) { - while (! (MXC_UART_GetFlags ((mxc_uart_regs_t*) (req->uart)) & MXC_F_UART_REVB_INT_FL_TX_HE)); - - numToWrite = MXC_UART_GetTXFIFOAvailable ((mxc_uart_regs_t*) (req->uart)); - numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite; - req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*) (req->uart), &req->txData[req->txCnt], numToWrite); - MXC_UART_ClearFlags ((mxc_uart_regs_t*) (req->uart), MXC_F_UART_REVB_INT_FL_TX_HE); + while (!(MXC_UART_GetFlags((mxc_uart_regs_t *)(req->uart)) & + MXC_F_UART_REVB_INT_FL_TX_HE) && + !(req->uart->status & MXC_F_UART_REVB_STATUS_TX_EM)) {} + + numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : + numToWrite; + req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), + &req->txData[req->txCnt], numToWrite); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVB_INT_FL_TX_HE); } } if (req->rxLen) { - numToRead = MXC_UART_GetRXFIFOAvailable ((mxc_uart_regs_t*) (req->uart)); - numToRead = numToRead > (req->rxLen-req->rxCnt) ? req->rxLen-req->rxCnt : numToRead; - req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*) (req->uart), &req->rxData[req->rxCnt], numToRead); - + numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead; + req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), &req->rxData[req->rxCnt], + numToRead); + while (req->rxCnt < req->rxLen) { - while (! (MXC_UART_GetFlags ((mxc_uart_regs_t*) (req->uart)) & MXC_F_UART_REVB_INT_FL_RX_THD)); - - numToRead = MXC_UART_GetRXFIFOAvailable ((mxc_uart_regs_t*) (req->uart)); - numToRead = numToRead > (req->rxLen-req->rxCnt) ? req->rxLen-req->rxCnt : numToRead; - req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*) (req->uart), &req->rxData[req->rxCnt], numToRead); - MXC_UART_ClearFlags ((mxc_uart_regs_t*) (req->uart), MXC_F_UART_REVB_INT_FL_RX_THD); + while (!(MXC_UART_GetFlags((mxc_uart_regs_t *)(req->uart)) & + MXC_F_UART_REVB_INT_FL_RX_THD)) {} + + numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); + numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead; + req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), + &req->rxData[req->rxCnt], numToRead); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVB_INT_FL_RX_THD); } } return E_NO_ERROR; } -int MXC_UART_RevB_TransactionAsync(mxc_uart_revb_req_t* req) +int MXC_UART_RevB_TransactionAsync(mxc_uart_revb_req_t *req) { uint32_t numToWrite, numToRead; - int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t*)(req->uart)); + int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)); if (uartNum < 0) { return E_INVALID; } - if(!AsyncTxRequests[uartNum] && !AsyncRxRequests[uartNum]) { + if (!AsyncTxRequests[uartNum] && !AsyncRxRequests[uartNum]) { /* No requests pending, clear the interrupt state */ - MXC_UART_DisableInt((mxc_uart_regs_t*) (req->uart), 0xFFFFFFFF); - MXC_UART_ClearFlags((mxc_uart_regs_t*) (req->uart), 0xFFFFFFFF); + MXC_UART_DisableInt((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); } else if (AsyncRxRequests[uartNum] && req->rxLen) { /* RX request pending */ @@ -690,50 +705,53 @@ return E_BAD_PARAM; } - MXC_UART_EnableInt((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVB_INT_EN_TX_HE); - numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t*) (req->uart)); + MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVB_INT_EN_TX_HE); + numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite; - req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t*) (req->uart), &req->txData[req->txCnt], numToWrite); + req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt], + numToWrite); /* If we're finished writing to the TX FIFO and it's less than half+1 full, pend the interrupt */ - if((MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t*) (req->uart)) >= (MXC_UART_FIFO_DEPTH/2)) - && (req->txCnt == req->txLen)) { + if ((MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)) >= + (MXC_UART_FIFO_DEPTH / 2)) && + (req->txCnt == req->txLen)) { NVIC_SetPendingIRQ(MXC_UART_GET_IRQ(uartNum)); } - AsyncTxRequests[MXC_UART_GET_IDX((mxc_uart_regs_t*) (req->uart))] = (void*) req; + AsyncTxRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart))] = (void *)req; } if (req->rxLen) { // All error interrupts are related to RX - MXC_UART_EnableInt((mxc_uart_regs_t*) (req->uart), MXC_UART_REVB_ERRINT_EN); + MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_UART_REVB_ERRINT_EN); if (req->rxData == NULL) { - MXC_UART_DisableInt((mxc_uart_regs_t*) (req->uart), 0xFFFFFFFF); - MXC_UART_ClearTXFIFO((mxc_uart_regs_t*) (req->uart)); + MXC_UART_DisableInt((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); + MXC_UART_ClearTXFIFO((mxc_uart_regs_t *)(req->uart)); return E_BAD_PARAM; } - MXC_UART_EnableInt((mxc_uart_regs_t*) (req->uart), MXC_F_UART_REVB_INT_EN_RX_THD); - numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t*) (req->uart)); + MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVB_INT_EN_RX_THD); + numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead; - req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t*) (req->uart), &req->rxData[req->rxCnt], numToRead); - MXC_UART_ClearFlags((mxc_uart_regs_t*) (req->uart), MXC_F_UART_REVB_INT_FL_RX_THD); + req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), &req->rxData[req->rxCnt], + numToRead); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVB_INT_FL_RX_THD); - AsyncRxRequests[MXC_UART_GET_IDX((mxc_uart_regs_t*) (req->uart))] = (void*) req; + AsyncRxRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart))] = (void *)req; } return E_NO_ERROR; } -int MXC_UART_RevB_AsyncTxCallback(mxc_uart_revb_regs_t* uart, int retVal) +int MXC_UART_RevB_AsyncTxCallback(mxc_uart_revb_regs_t *uart, int retVal) { - int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t*)uart); + int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); if (uartNum < 0) { return E_BAD_PARAM; } - mxc_uart_req_t* req = (mxc_uart_req_t*) AsyncTxRequests[uartNum]; + mxc_uart_req_t *req = (mxc_uart_req_t *)AsyncTxRequests[uartNum]; if ((req != NULL) && (req->callback != NULL)) { AsyncTxRequests[uartNum] = NULL; req->callback(req, retVal); @@ -742,14 +760,14 @@ return E_NO_ERROR; } -int MXC_UART_RevB_AsyncRxCallback(mxc_uart_revb_regs_t* uart, int retVal) +int MXC_UART_RevB_AsyncRxCallback(mxc_uart_revb_regs_t *uart, int retVal) { - int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t*)uart); + int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); if (uartNum < 0) { return E_BAD_PARAM; } - mxc_uart_req_t* req = (mxc_uart_req_t*) AsyncRxRequests[uartNum]; + mxc_uart_req_t *req = (mxc_uart_req_t *)AsyncRxRequests[uartNum]; if ((req != NULL) && (req->callback != NULL)) { AsyncRxRequests[uartNum] = NULL; req->callback(req, retVal); @@ -758,9 +776,9 @@ return E_NO_ERROR; } -int MXC_UART_RevB_AsyncCallback(mxc_uart_revb_regs_t* uart, int retVal) +int MXC_UART_RevB_AsyncCallback(mxc_uart_revb_regs_t *uart, int retVal) { - int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t*)uart); + int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); if (uartNum < 0) { return E_BAD_PARAM; } @@ -768,121 +786,123 @@ MXC_UART_RevB_AsyncTxCallback(uart, retVal); /* Only call the callback once if it's for the same request */ - if(AsyncRxRequests[uartNum] != AsyncTxRequests[uartNum]) { + if (AsyncRxRequests[uartNum] != AsyncTxRequests[uartNum]) { MXC_UART_RevB_AsyncRxCallback(uart, retVal); } return E_NO_ERROR; } -int MXC_UART_RevB_AsyncStopTx(mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_AsyncStopTx(mxc_uart_revb_regs_t *uart) { - if (MXC_UART_GET_IDX((mxc_uart_regs_t*)uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - MXC_UART_DisableInt((mxc_uart_regs_t*)uart, MXC_F_UART_REVB_INT_EN_TX_HE); + MXC_UART_DisableInt((mxc_uart_regs_t *)uart, MXC_F_UART_REVB_INT_EN_TX_HE); return E_NO_ERROR; } -int MXC_UART_RevB_AsyncStopRx(mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_AsyncStopRx(mxc_uart_revb_regs_t *uart) { - if (MXC_UART_GET_IDX((mxc_uart_regs_t*)uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - MXC_UART_DisableInt((mxc_uart_regs_t*)uart, MXC_UART_REVB_ERRINT_EN); + MXC_UART_DisableInt((mxc_uart_regs_t *)uart, MXC_UART_REVB_ERRINT_EN); return E_NO_ERROR; } -int MXC_UART_RevB_AsyncStop(mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_AsyncStop(mxc_uart_revb_regs_t *uart) { - if (MXC_UART_GET_IDX((mxc_uart_regs_t*)uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - MXC_UART_DisableInt((mxc_uart_regs_t*)uart, 0xFFFFFFFF); + MXC_UART_DisableInt((mxc_uart_regs_t *)uart, 0xFFFFFFFF); return E_NO_ERROR; } -int MXC_UART_RevB_AbortAsync(mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_AbortAsync(mxc_uart_revb_regs_t *uart) { - if (MXC_UART_GET_IDX((mxc_uart_regs_t*)uart) < 0) { + if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) { return E_BAD_PARAM; } - MXC_UART_AsyncStop((mxc_uart_regs_t*)uart); - MXC_UART_AsyncCallback((mxc_uart_regs_t*)uart, E_ABORT); + MXC_UART_AsyncStop((mxc_uart_regs_t *)uart); + MXC_UART_AsyncCallback((mxc_uart_regs_t *)uart, E_ABORT); return E_NO_ERROR; } -int MXC_UART_RevB_AsyncHandler(mxc_uart_revb_regs_t* uart) +int MXC_UART_RevB_AsyncHandler(mxc_uart_revb_regs_t *uart) { uint32_t numToWrite, numToRead, flags; - mxc_uart_req_t* req; + mxc_uart_req_t *req; - int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t*)uart); + int uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); if (uartNum < 0) { return E_INVALID; } - flags = MXC_UART_GetFlags((mxc_uart_regs_t*)uart); + flags = MXC_UART_GetFlags((mxc_uart_regs_t *)uart); /* Unexpected interrupt */ if (!AsyncTxRequests[uartNum] && !AsyncRxRequests[uartNum]) { - MXC_UART_ClearFlags((mxc_uart_regs_t*)uart, uart->int_fl); + MXC_UART_ClearFlags((mxc_uart_regs_t *)uart, uart->int_fl); return E_INVALID; } if (flags & MXC_UART_REVB_ERRINT_FL & uart->int_en) { - MXC_UART_AsyncStop((mxc_uart_regs_t*)uart); - MXC_UART_AsyncCallback((mxc_uart_regs_t*)uart, E_COMM_ERR); + MXC_UART_AsyncStop((mxc_uart_regs_t *)uart); + MXC_UART_AsyncCallback((mxc_uart_regs_t *)uart, E_COMM_ERR); return E_INVALID; } - req = (mxc_uart_req_t*) AsyncTxRequests[uartNum]; + req = (mxc_uart_req_t *)AsyncTxRequests[uartNum]; if ((req != NULL) && (req->txLen)) { - numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t*)(req->uart)); + numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite; - req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite); + req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt], + numToWrite); MXC_UART_ClearFlags(req->uart, MXC_F_UART_REVB_INT_FL_TX_HE); } - req = (mxc_uart_req_t*) AsyncRxRequests[uartNum]; + req = (mxc_uart_req_t *)AsyncRxRequests[uartNum]; if ((req != NULL) && (flags & MXC_F_UART_REVB_INT_FL_RX_THD) && (req->rxLen)) { - numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t*)(req->uart)); + numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead; - req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead); + req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), &req->rxData[req->rxCnt], + numToRead); - if ((req->rxLen - req->rxCnt) < MXC_UART_GetRXThreshold((mxc_uart_regs_t*)(req->uart))) { - MXC_UART_SetRXThreshold((mxc_uart_regs_t*)(req->uart), req->rxLen - req->rxCnt); + if ((req->rxLen - req->rxCnt) < MXC_UART_GetRXThreshold((mxc_uart_regs_t *)(req->uart))) { + MXC_UART_SetRXThreshold((mxc_uart_regs_t *)(req->uart), req->rxLen - req->rxCnt); } - MXC_UART_ClearFlags((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVB_INT_FL_RX_THD); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVB_INT_FL_RX_THD); } - if(AsyncRxRequests[uartNum] == AsyncTxRequests[uartNum]) { + if (AsyncRxRequests[uartNum] == AsyncTxRequests[uartNum]) { if ((req != NULL) && (req->rxCnt == req->rxLen) && (req->txCnt == req->txLen)) { - MXC_UART_AsyncStop((mxc_uart_regs_t*)uart); - MXC_UART_AsyncCallback((mxc_uart_regs_t*)uart, E_NO_ERROR); + MXC_UART_AsyncStop((mxc_uart_regs_t *)uart); + MXC_UART_AsyncCallback((mxc_uart_regs_t *)uart, E_NO_ERROR); } return E_NO_ERROR; } - req = (mxc_uart_req_t*) AsyncRxRequests[uartNum]; + req = (mxc_uart_req_t *)AsyncRxRequests[uartNum]; if ((req != NULL) && (req->rxCnt == req->rxLen)) { MXC_UART_RevB_AsyncStopRx(uart); MXC_UART_RevB_AsyncRxCallback(uart, E_NO_ERROR); return E_NO_ERROR; } - req = (mxc_uart_req_t*) AsyncTxRequests[uartNum]; - if((req != NULL) && (req->txCnt == req->txLen)) { + req = (mxc_uart_req_t *)AsyncTxRequests[uartNum]; + if ((req != NULL) && (req->txCnt == req->txLen)) { MXC_UART_RevB_AsyncStopTx(uart); MXC_UART_RevB_AsyncTxCallback(uart, E_NO_ERROR); return E_NO_ERROR; @@ -891,13 +911,13 @@ return E_NO_ERROR; } -int MXC_UART_RevB_ReadRXFIFODMA (mxc_uart_revb_regs_t* uart, unsigned char* bytes, unsigned int len, - mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) +int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) { uint8_t channel; mxc_dma_srcdst_t srcdst; - - int uart_num = MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart); + + int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); if (uart_num < 0) { return E_INVALID; @@ -921,7 +941,6 @@ srcdst.dest = bytes; srcdst.len = len; - states[uart_num].channelRx = channel; MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); @@ -930,17 +949,18 @@ //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); uart->dma |= MXC_F_UART_REVB_DMA_RX_EN; - + return E_NO_ERROR; } -int MXC_UART_RevB_WriteTXFIFODMA (mxc_uart_revb_regs_t* uart, const unsigned char* bytes, unsigned int len, - mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) +int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback, + mxc_dma_config_t config) { uint8_t channel; mxc_dma_srcdst_t srcdst; - - int uart_num = MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart); + + int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); if (uart_num < 0) { return E_INVALID; @@ -961,10 +981,9 @@ config.dstinc_en = 0; srcdst.ch = channel; - srcdst.source = (void*)bytes; + srcdst.source = (void *)bytes; srcdst.len = len; - states[uart_num].channelTx = channel; MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); @@ -973,14 +992,14 @@ //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); uart->dma |= MXC_F_UART_REVB_DMA_TX_EN; - + return E_NO_ERROR; } -int MXC_UART_RevB_TransactionDMA (mxc_uart_revb_req_t* req) +int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req) { - int uart_num = MXC_UART_GET_IDX ((mxc_uart_regs_t*) (req->uart)); - + int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)); + if (uart_num < 0) { return E_BAD_PARAM; } @@ -996,41 +1015,49 @@ return E_BAD_PARAM; } } - - MXC_UART_DisableInt ((mxc_uart_regs_t*) (req->uart), 0xFFFFFFFF); - MXC_UART_ClearFlags ((mxc_uart_regs_t*) (req->uart), 0xFFFFFFFF); - MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*) (req->uart)); - MXC_UART_ClearRXFIFO ((mxc_uart_regs_t*) (req->uart)); - + MXC_UART_DisableInt((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); + MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF); + + MXC_UART_ClearTXFIFO((mxc_uart_regs_t *)(req->uart)); + MXC_UART_ClearRXFIFO((mxc_uart_regs_t *)(req->uart)); + //Set DMA FIFO threshold (req->uart)->dma |= (1 << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS); (req->uart)->dma |= (2 << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS); - + MXC_DMA_Init(); //tx - if ( (req->txData != NULL) && (req->txLen)) { - if (MXC_UART_WriteTXFIFODMA ((mxc_uart_regs_t*) (req->uart), req->txData, req->txLen, NULL) != E_NO_ERROR) { + if ((req->txData != NULL) && (req->txLen)) { + if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), req->txData, req->txLen, + NULL) != E_NO_ERROR) { return E_BAD_PARAM; } + + // Save state for UART DMACallback function. + states[uart_num].req = req; } //rx - if ( (req->rxData != NULL) && (req->rxLen)) { - if (MXC_UART_ReadRXFIFODMA ((mxc_uart_regs_t*) (req->uart), req->rxData, req->rxLen, NULL) != E_NO_ERROR) { + if ((req->rxData != NULL) && (req->rxLen)) { + if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), req->rxData, req->rxLen, NULL) != + E_NO_ERROR) { return E_BAD_PARAM; } + + // Save state for UART DMACallback function. + states[uart_num].req = req; } return E_NO_ERROR; } -void MXC_UART_RevB_DMACallback (int ch, int error) +void MXC_UART_RevB_DMACallback(int ch, int error) { - mxc_uart_revb_req_t * temp_req; - - for (int i = 0; i < MXC_UART_INSTANCES; i ++) { + mxc_uart_revb_req_t *temp_req; + + for (int i = 0; i < MXC_UART_INSTANCES; i++) { if (states[i].channelTx == ch) { //save the request temp_req = states[i].req; @@ -1039,12 +1066,10 @@ // Callback if not NULL if (temp_req->callback != NULL) { - temp_req->callback((mxc_uart_req_t*)temp_req, E_NO_ERROR); - } + temp_req->callback((mxc_uart_req_t *)temp_req, E_NO_ERROR); + } break; - } - - else if (states[i].channelRx == ch) { + } else if (states[i].channelRx == ch) { //save the request temp_req = states[i].req; @@ -1052,8 +1077,8 @@ // Callback if not NULL if (temp_req->callback != NULL) { - temp_req->callback((mxc_uart_req_t*)temp_req, E_NO_ERROR); - } + temp_req->callback((mxc_uart_req_t *)temp_req, E_NO_ERROR); + } break; } } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb.h index 60faf4b..0ec4280 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb.h @@ -1,5 +1,5 @@ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,10 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - *************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVB_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVB_H_ #include "mxc_device.h" #include "mxc_assert.h" @@ -42,70 +45,76 @@ /** * @brief Clock settings */ typedef enum { - MXC_UART_REVB_APB_CLK = 0, // PCLK - MXC_UART_REVB_EXT_CLK = 1, - MXC_UART_REVB_CLK2 = 2, - MXC_UART_REVB_CLK3 = 3, - // For UART3, ERTCO and INRO clocks - MXC_UART_REVB_LPCLK2 = 4, - MXC_UART_REVB_LPCLK3 = 5 + MXC_UART_REVB_APB_CLK = 0, // PCLK + MXC_UART_REVB_EXT_CLK = 1, + MXC_UART_REVB_CLK2 = 2, + MXC_UART_REVB_CLK3 = 3, + // For UART3, ERTCO and INRO clocks + MXC_UART_REVB_LPCLK2 = 4, + MXC_UART_REVB_LPCLK3 = 5 } mxc_uart_revb_clock_t; struct _mxc_uart_revb_req_t { - mxc_uart_revb_regs_t* uart; - uint8_t *txData; - uint8_t *rxData; - uint32_t txLen; - uint32_t rxLen; - uint32_t txCnt; - uint32_t rxCnt; + mxc_uart_revb_regs_t *uart; + uint8_t *txData; + uint8_t *rxData; + uint32_t txLen; + uint32_t rxLen; + uint32_t txCnt; + uint32_t rxCnt; mxc_uart_complete_cb_t callback; }; -int MXC_UART_RevB_Init (mxc_uart_revb_regs_t* uart, unsigned int baud, mxc_uart_revb_clock_t clock); -int MXC_UART_RevB_Shutdown (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_ReadyForSleep (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_SetFrequency (mxc_uart_revb_regs_t* uart, unsigned int baud, mxc_uart_revb_clock_t clock); -int MXC_UART_RevB_GetFrequency (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_SetDataSize (mxc_uart_revb_regs_t* uart, int dataSize); -int MXC_UART_RevB_SetStopBits (mxc_uart_revb_regs_t* uart, mxc_uart_stop_t stopBits); -int MXC_UART_RevB_SetParity (mxc_uart_revb_regs_t* uart, mxc_uart_parity_t parity); -int MXC_UART_RevB_SetFlowCtrl (mxc_uart_revb_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold); -int MXC_UART_RevB_SetClockSource (mxc_uart_revb_regs_t* uart, mxc_uart_revb_clock_t clock); -int MXC_UART_RevB_GetActive (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_AbortTransmission (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_ReadCharacterRaw (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_WriteCharacterRaw (mxc_uart_revb_regs_t* uart, uint8_t character); -int MXC_UART_RevB_ReadCharacter (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_WriteCharacter (mxc_uart_revb_regs_t* uart, uint8_t character); -int MXC_UART_RevB_Read (mxc_uart_revb_regs_t* uart, uint8_t* buffer, int* len); -int MXC_UART_RevB_Write (mxc_uart_revb_regs_t* uart, const uint8_t* byte, int* len); -unsigned int MXC_UART_RevB_ReadRXFIFO (mxc_uart_revb_regs_t* uart, unsigned char* bytes, +int MXC_UART_RevB_Init(mxc_uart_revb_regs_t *uart, unsigned int baud, mxc_uart_revb_clock_t clock); +int MXC_UART_RevB_Shutdown(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_ReadyForSleep(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_SetFrequency(mxc_uart_revb_regs_t *uart, unsigned int baud, + mxc_uart_revb_clock_t clock); +int MXC_UART_RevB_GetFrequency(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_SetDataSize(mxc_uart_revb_regs_t *uart, int dataSize); +int MXC_UART_RevB_SetStopBits(mxc_uart_revb_regs_t *uart, mxc_uart_stop_t stopBits); +int MXC_UART_RevB_SetParity(mxc_uart_revb_regs_t *uart, mxc_uart_parity_t parity); +int MXC_UART_RevB_SetFlowCtrl(mxc_uart_revb_regs_t *uart, mxc_uart_flow_t flowCtrl, + int rtsThreshold); +int MXC_UART_RevB_SetClockSource(mxc_uart_revb_regs_t *uart, mxc_uart_revb_clock_t clock); +int MXC_UART_RevB_GetActive(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_AbortTransmission(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_ReadCharacterRaw(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_WriteCharacterRaw(mxc_uart_revb_regs_t *uart, uint8_t character); +int MXC_UART_RevB_ReadCharacter(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_WriteCharacter(mxc_uart_revb_regs_t *uart, uint8_t character); +int MXC_UART_RevB_Read(mxc_uart_revb_regs_t *uart, uint8_t *buffer, int *len); +int MXC_UART_RevB_Write(mxc_uart_revb_regs_t *uart, const uint8_t *byte, int *len); +unsigned int MXC_UART_RevB_ReadRXFIFO(mxc_uart_revb_regs_t *uart, unsigned char *bytes, + unsigned int len); +int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); +unsigned int MXC_UART_RevB_GetRXFIFOAvailable(mxc_uart_revb_regs_t *uart); +unsigned int MXC_UART_RevB_WriteTXFIFO(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, unsigned int len); -int MXC_UART_RevB_ReadRXFIFODMA (mxc_uart_revb_regs_t* uart, unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); -unsigned int MXC_UART_RevB_GetRXFIFOAvailable (mxc_uart_revb_regs_t* uart); -unsigned int MXC_UART_RevB_WriteTXFIFO (mxc_uart_revb_regs_t* uart, const unsigned char* bytes, - unsigned int len); -int MXC_UART_RevB_WriteTXFIFODMA (mxc_uart_revb_regs_t* uart, const unsigned char* bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); -unsigned int MXC_UART_RevB_GetTXFIFOAvailable (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_ClearRXFIFO (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_ClearTXFIFO (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_SetRXThreshold (mxc_uart_revb_regs_t* uart, unsigned int numBytes); -unsigned int MXC_UART_RevB_GetRXThreshold (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_SetTXThreshold (mxc_uart_revb_regs_t* uart, unsigned int numBytes); -unsigned int MXC_UART_RevB_GetTXThreshold (mxc_uart_revb_regs_t* uart); -unsigned int MXC_UART_RevB_GetFlags (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_ClearFlags (mxc_uart_revb_regs_t* uart, unsigned int flags); -int MXC_UART_RevB_EnableInt (mxc_uart_revb_regs_t* uart, unsigned int mask); -int MXC_UART_RevB_DisableInt (mxc_uart_revb_regs_t* uart, unsigned int mask); -unsigned int MXC_UART_RevB_GetStatus (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_Transaction (mxc_uart_revb_req_t* req); -int MXC_UART_RevB_TransactionAsync (mxc_uart_revb_req_t* req); -int MXC_UART_RevB_TransactionDMA (mxc_uart_revb_req_t* req); -int MXC_UART_RevB_AbortAsync (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_AsyncHandler (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_AsyncStop (mxc_uart_revb_regs_t* uart); -int MXC_UART_RevB_AsyncCallback (mxc_uart_revb_regs_t* uart, int retVal); -void MXC_UART_RevB_DMACallback (int ch, int error); +int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback, + mxc_dma_config_t config); +unsigned int MXC_UART_RevB_GetTXFIFOAvailable(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_ClearRXFIFO(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_ClearTXFIFO(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_SetRXThreshold(mxc_uart_revb_regs_t *uart, unsigned int numBytes); +unsigned int MXC_UART_RevB_GetRXThreshold(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_SetTXThreshold(mxc_uart_revb_regs_t *uart, unsigned int numBytes); +unsigned int MXC_UART_RevB_GetTXThreshold(mxc_uart_revb_regs_t *uart); +unsigned int MXC_UART_RevB_GetFlags(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_ClearFlags(mxc_uart_revb_regs_t *uart, unsigned int flags); +int MXC_UART_RevB_EnableInt(mxc_uart_revb_regs_t *uart, unsigned int mask); +int MXC_UART_RevB_DisableInt(mxc_uart_revb_regs_t *uart, unsigned int mask); +unsigned int MXC_UART_RevB_GetStatus(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_Busy(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_Transaction(mxc_uart_revb_req_t *req); +int MXC_UART_RevB_TransactionAsync(mxc_uart_revb_req_t *req); +int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req); +int MXC_UART_RevB_AbortAsync(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_AsyncHandler(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_AsyncStop(mxc_uart_revb_regs_t *uart); +int MXC_UART_RevB_AsyncCallback(mxc_uart_revb_regs_t *uart, int retVal); +void MXC_UART_RevB_DMACallback(int ch, int error); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVB_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h index 9283e4f..eab6759 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the UART_REVB Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _UART_REVB_REGS_H_ #define _UART_REVB_REGS_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_common.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_common.c index e6d4f63..982fbbd 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_common.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_common.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_me15.c index e71f017..7f76120 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_me15.c @@ -1,5 +1,5 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include "mxc_device.h" @@ -41,99 +41,95 @@ /* **** Functions **** */ -int MXC_WDT_Init(mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t* cfg) +int MXC_WDT_Init(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) { if (wdt == MXC_WDT0) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT0); - } - else if (wdt == MXC_WDT1) { + } else if (wdt == MXC_WDT1) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT1); - } - else { + } else { return E_BAD_PARAM; } - - MXC_WDT_RevB_Init((mxc_wdt_revb_regs_t*) wdt, (mxc_wdt_revb_cfg_t*) cfg); - + + MXC_WDT_RevB_Init((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); + return E_NO_ERROR; } -int MXC_WDT_Shutdown(mxc_wdt_regs_t* wdt) +int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt) { if (wdt == MXC_WDT0) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT0); - } - else if (wdt == MXC_WDT1) { + } else if (wdt == MXC_WDT1) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT1); - } - else { + } else { return E_BAD_PARAM; } - + return E_NO_ERROR; } -void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t* cfg) +void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) { - MXC_WDT_RevB_SetIntPeriod ((mxc_wdt_revb_regs_t*) wdt, (mxc_wdt_revb_cfg_t*) cfg); + MXC_WDT_RevB_SetIntPeriod((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); } -void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t* cfg) +void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) { - MXC_WDT_RevB_SetResetPeriod ((mxc_wdt_revb_regs_t*) wdt, (mxc_wdt_revb_cfg_t*) cfg); + MXC_WDT_RevB_SetResetPeriod((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); } -void MXC_WDT_Enable(mxc_wdt_regs_t* wdt) +void MXC_WDT_Enable(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevB_Enable ((mxc_wdt_revb_regs_t*) wdt); + MXC_WDT_RevB_Enable((mxc_wdt_revb_regs_t *)wdt); } -void MXC_WDT_Disable(mxc_wdt_regs_t* wdt) +void MXC_WDT_Disable(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevB_Disable ((mxc_wdt_revb_regs_t*) wdt); + MXC_WDT_RevB_Disable((mxc_wdt_revb_regs_t *)wdt); } -void MXC_WDT_EnableInt(mxc_wdt_regs_t* wdt) +void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevB_EnableInt ((mxc_wdt_revb_regs_t*) wdt, MXC_WDT_REVB_ENABLE); + MXC_WDT_RevB_EnableInt((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_ENABLE); } -void MXC_WDT_DisableInt(mxc_wdt_regs_t* wdt) +void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevB_EnableInt ((mxc_wdt_revb_regs_t*) wdt, MXC_WDT_REVB_DISABLE); + MXC_WDT_RevB_EnableInt((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_DISABLE); } -void MXC_WDT_EnableReset(mxc_wdt_regs_t* wdt) +void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevB_EnableReset ((mxc_wdt_revb_regs_t*) wdt, MXC_WDT_REVB_ENABLE); + MXC_WDT_RevB_EnableReset((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_ENABLE); } -void MXC_WDT_DisableReset(mxc_wdt_regs_t* wdt) +void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevB_EnableReset ((mxc_wdt_revb_regs_t*) wdt, MXC_WDT_REVB_DISABLE); + MXC_WDT_RevB_EnableReset((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_DISABLE); } -void MXC_WDT_ResetTimer(mxc_wdt_regs_t* wdt) +void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevB_ResetTimer ((mxc_wdt_revb_regs_t*) wdt); + MXC_WDT_RevB_ResetTimer((mxc_wdt_revb_regs_t *)wdt); } -int MXC_WDT_GetResetFlag(mxc_wdt_regs_t* wdt) +int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt) { - return MXC_WDT_RevB_GetResetFlag ((mxc_wdt_revb_regs_t*) wdt); + return MXC_WDT_RevB_GetResetFlag((mxc_wdt_revb_regs_t *)wdt); } -void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t* wdt) +void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevB_ClearResetFlag ((mxc_wdt_revb_regs_t*) wdt); + MXC_WDT_RevB_ClearResetFlag((mxc_wdt_revb_regs_t *)wdt); } -int MXC_WDT_GetIntFlag(mxc_wdt_regs_t* wdt) +int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt) { - return MXC_WDT_RevB_GetIntFlag ((mxc_wdt_revb_regs_t*) wdt); + return MXC_WDT_RevB_GetIntFlag((mxc_wdt_revb_regs_t *)wdt); } -void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t* wdt) +void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt) { - MXC_WDT_RevB_ClearIntFlag ((mxc_wdt_revb_regs_t*) wdt); + MXC_WDT_RevB_ClearIntFlag((mxc_wdt_revb_regs_t *)wdt); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb.c index bad36e9..b938350 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb.c @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files(the "Software"), + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,7 +29,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ /* **** Includes **** */ #include @@ -43,95 +43,96 @@ /* **** Functions **** */ -int MXC_WDT_RevB_Init(mxc_wdt_revb_regs_t* wdt, mxc_wdt_revb_cfg_t *cfg) +int MXC_WDT_RevB_Init(mxc_wdt_revb_regs_t *wdt, mxc_wdt_revb_cfg_t *cfg) { if (wdt == NULL || cfg == NULL) { return E_NULL_PTR; } - if(cfg->mode & MXC_WDT_REVB_WINDOWED){ + if (cfg->mode & MXC_WDT_REVB_WINDOWED) { wdt->ctrl |= MXC_F_WDT_REVB_CTRL_WIN_EN; - } - else{ + } else { wdt->ctrl &= ~(MXC_F_WDT_REVB_CTRL_WIN_EN); } - + return E_NO_ERROR; } -void MXC_WDT_RevB_SetIntPeriod(mxc_wdt_revb_regs_t* wdt, mxc_wdt_revb_cfg_t *cfg) +void MXC_WDT_RevB_SetIntPeriod(mxc_wdt_revb_regs_t *wdt, mxc_wdt_revb_cfg_t *cfg) { MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_INT_LATE_VAL, cfg->upperIntPeriod); - if(cfg->mode & MXC_WDT_REVB_WINDOWED){ - MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_INT_EARLY_VAL, \ - (cfg->lowerIntPeriod<mode & MXC_WDT_REVB_WINDOWED) { + MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_INT_EARLY_VAL, + (cfg->lowerIntPeriod << MXC_F_WDT_REVB_CTRL_INT_EARLY_VAL_POS)); } } -void MXC_WDT_RevB_SetResetPeriod(mxc_wdt_revb_regs_t* wdt, mxc_wdt_revb_cfg_t *cfg) +void MXC_WDT_RevB_SetResetPeriod(mxc_wdt_revb_regs_t *wdt, mxc_wdt_revb_cfg_t *cfg) { - MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_RST_LATE_VAL, \ - (cfg->upperResetPeriod << MXC_F_WDT_REVB_CTRL_RST_LATE_VAL_POS)); + MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_RST_LATE_VAL, + (cfg->upperResetPeriod << MXC_F_WDT_REVB_CTRL_RST_LATE_VAL_POS)); - if(cfg->mode & MXC_WDT_REVB_WINDOWED){ - MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_RST_EARLY_VAL, \ - (cfg->lowerResetPeriod << MXC_F_WDT_REVB_CTRL_RST_EARLY_VAL_POS)); + if (cfg->mode & MXC_WDT_REVB_WINDOWED) { + MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_RST_EARLY_VAL, + (cfg->lowerResetPeriod << MXC_F_WDT_REVB_CTRL_RST_EARLY_VAL_POS)); } } -void MXC_WDT_RevB_Enable(mxc_wdt_revb_regs_t* wdt) +void MXC_WDT_RevB_Enable(mxc_wdt_revb_regs_t *wdt) { - wdt->ctrl |= MXC_F_WDT_REVB_CTRL_EN; + wdt->rst = 0xFE; // Feed seuqence chips + wdt->rst = 0xED; + wdt->ctrl |= MXC_F_WDT_REVB_CTRL_EN; // Direct write chips } -void MXC_WDT_RevB_Disable(mxc_wdt_revb_regs_t* wdt) +void MXC_WDT_RevB_Disable(mxc_wdt_revb_regs_t *wdt) { - wdt->ctrl &= ~(MXC_F_WDT_REVB_CTRL_EN); + wdt->rst = 0xDE; // Feed sequence chips + wdt->rst = 0xAD; + wdt->ctrl &= ~(MXC_F_WDT_REVB_CTRL_EN); // Direct write chips } -void MXC_WDT_RevB_EnableInt(mxc_wdt_revb_regs_t* wdt, mxc_wdt_revb_en_t enable) +void MXC_WDT_RevB_EnableInt(mxc_wdt_revb_regs_t *wdt, mxc_wdt_revb_en_t enable) { - if(enable) { + if (enable) { wdt->ctrl |= MXC_F_WDT_REVB_CTRL_WDT_INT_EN; - } - else { + } else { wdt->ctrl &= ~(MXC_F_WDT_REVB_CTRL_WDT_INT_EN); } } -void MXC_WDT_RevB_EnableReset(mxc_wdt_revb_regs_t* wdt, mxc_wdt_revb_en_t enable) +void MXC_WDT_RevB_EnableReset(mxc_wdt_revb_regs_t *wdt, mxc_wdt_revb_en_t enable) { - if(enable) { + if (enable) { wdt->ctrl |= MXC_F_WDT_REVB_CTRL_WDT_RST_EN; - } - else { + } else { wdt->ctrl &= ~(MXC_F_WDT_REVB_CTRL_WDT_RST_EN); } } -void MXC_WDT_RevB_ResetTimer(mxc_wdt_revb_regs_t* wdt) +void MXC_WDT_RevB_ResetTimer(mxc_wdt_revb_regs_t *wdt) { wdt->rst = 0x00A5; wdt->rst = 0x005A; } -int MXC_WDT_RevB_GetResetFlag(mxc_wdt_revb_regs_t* wdt) +int MXC_WDT_RevB_GetResetFlag(mxc_wdt_revb_regs_t *wdt) { - return (wdt->ctrl &(MXC_F_WDT_REVB_CTRL_RST_LATE | MXC_F_WDT_REVB_CTRL_RST_EARLY)); + return (wdt->ctrl & (MXC_F_WDT_REVB_CTRL_RST_LATE | MXC_F_WDT_REVB_CTRL_RST_EARLY)); } -void MXC_WDT_RevB_ClearResetFlag(mxc_wdt_revb_regs_t* wdt) +void MXC_WDT_RevB_ClearResetFlag(mxc_wdt_revb_regs_t *wdt) { wdt->ctrl &= ~(MXC_F_WDT_REVB_CTRL_RST_LATE | MXC_F_WDT_REVB_CTRL_RST_EARLY); } -int MXC_WDT_RevB_GetIntFlag(mxc_wdt_revb_regs_t* wdt) +int MXC_WDT_RevB_GetIntFlag(mxc_wdt_revb_regs_t *wdt) { - return !!(wdt->ctrl &(MXC_F_WDT_REVB_CTRL_INT_LATE | MXC_F_WDT_REVB_CTRL_INT_EARLY)); + return !!(wdt->ctrl & (MXC_F_WDT_REVB_CTRL_INT_LATE | MXC_F_WDT_REVB_CTRL_INT_EARLY)); } -void MXC_WDT_RevB_ClearIntFlag(mxc_wdt_revb_regs_t* wdt) +void MXC_WDT_RevB_ClearIntFlag(mxc_wdt_revb_regs_t *wdt) { wdt->ctrl &= ~(MXC_F_WDT_REVB_CTRL_INT_LATE | MXC_F_WDT_REVB_CTRL_INT_EARLY); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb.h index e620f75..b84aa19 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb.h @@ -1,8 +1,8 @@ -/* ***************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software");, + * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the @@ -29,14 +29,16 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - **************************************************************************** */ + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_WDT_WDT_REVB_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_WDT_WDT_REVB_H_ /* **** Includes **** */ #include "mxc_device.h" #include "mxc_errors.h" #include "mxc_assert.h" #include "mxc_sys.h" -//#include "wdt.h" #include "wdt_revb_regs.h" /* **** Definitions **** */ @@ -70,23 +72,25 @@ } mxc_wdt_revb_en_t; typedef struct { - mxc_wdt_revb_mode_t mode; ///< WDT mode - mxc_wdt_revb_period_t upperResetPeriod; ///< Reset upper limit - mxc_wdt_revb_period_t lowerResetPeriod; ///< Reset lower limit - mxc_wdt_revb_period_t upperIntPeriod; ///< Interrupt upper limit - mxc_wdt_revb_period_t lowerIntPeriod; ///< Interrupt lower limit + mxc_wdt_revb_mode_t mode; ///< WDT mode + mxc_wdt_revb_period_t upperResetPeriod; ///< Reset upper limit + mxc_wdt_revb_period_t lowerResetPeriod; ///< Reset lower limit + mxc_wdt_revb_period_t upperIntPeriod; ///< Interrupt upper limit + mxc_wdt_revb_period_t lowerIntPeriod; ///< Interrupt lower limit } mxc_wdt_revb_cfg_t; /* **** Functions **** */ -int MXC_WDT_RevB_Init (mxc_wdt_revb_regs_t* wdt, mxc_wdt_revb_cfg_t *cfg); -void MXC_WDT_RevB_SetIntPeriod (mxc_wdt_revb_regs_t* wdt, mxc_wdt_revb_cfg_t *cfg); -void MXC_WDT_RevB_SetResetPeriod (mxc_wdt_revb_regs_t* wdt, mxc_wdt_revb_cfg_t *cfg); -void MXC_WDT_RevB_Enable (mxc_wdt_revb_regs_t* wdt); -void MXC_WDT_RevB_Disable (mxc_wdt_revb_regs_t* wdt); -void MXC_WDT_RevB_EnableInt (mxc_wdt_revb_regs_t* wdt, mxc_wdt_revb_en_t enable); -void MXC_WDT_RevB_EnableReset (mxc_wdt_revb_regs_t* wdt, mxc_wdt_revb_en_t enable); -void MXC_WDT_RevB_ResetTimer (mxc_wdt_revb_regs_t* wdt); -int MXC_WDT_RevB_GetResetFlag (mxc_wdt_revb_regs_t* wdt); -void MXC_WDT_RevB_ClearResetFlag (mxc_wdt_revb_regs_t* wdt); -int MXC_WDT_RevB_GetIntFlag (mxc_wdt_revb_regs_t* wdt); -void MXC_WDT_RevB_ClearIntFlag (mxc_wdt_revb_regs_t* wdt); +int MXC_WDT_RevB_Init(mxc_wdt_revb_regs_t *wdt, mxc_wdt_revb_cfg_t *cfg); +void MXC_WDT_RevB_SetIntPeriod(mxc_wdt_revb_regs_t *wdt, mxc_wdt_revb_cfg_t *cfg); +void MXC_WDT_RevB_SetResetPeriod(mxc_wdt_revb_regs_t *wdt, mxc_wdt_revb_cfg_t *cfg); +void MXC_WDT_RevB_Enable(mxc_wdt_revb_regs_t *wdt); +void MXC_WDT_RevB_Disable(mxc_wdt_revb_regs_t *wdt); +void MXC_WDT_RevB_EnableInt(mxc_wdt_revb_regs_t *wdt, mxc_wdt_revb_en_t enable); +void MXC_WDT_RevB_EnableReset(mxc_wdt_revb_regs_t *wdt, mxc_wdt_revb_en_t enable); +void MXC_WDT_RevB_ResetTimer(mxc_wdt_revb_regs_t *wdt); +int MXC_WDT_RevB_GetResetFlag(mxc_wdt_revb_regs_t *wdt); +void MXC_WDT_RevB_ClearResetFlag(mxc_wdt_revb_regs_t *wdt); +int MXC_WDT_RevB_GetIntFlag(mxc_wdt_revb_regs_t *wdt); +void MXC_WDT_RevB_ClearIntFlag(mxc_wdt_revb_regs_t *wdt); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_WDT_WDT_REVB_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb_regs.h index d864a60..ee9e390 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/WDT/wdt_revb_regs.h @@ -3,8 +3,8 @@ * @brief Registers, Bit Masks and Bit Positions for the WDT_REVB Peripheral Module. */ -/* **************************************************************************** - * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. +/****************************************************************************** + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,7 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * - *************************************************************************** */ + ******************************************************************************/ #ifndef _WDT_REVB_REGS_H_ #define _WDT_REVB_REGS_H_ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/analogin_api.c index 6b380a6..7d4bcf3 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M2354/analogin_api.c @@ -25,6 +25,7 @@ #include "PeripheralPins.h" #include "gpio_api.h" #include "nu_modutil.h" +#include "hal/PinNameAliases.h" static uint32_t eadc_modinit_mask = 0; @@ -47,6 +48,18 @@ {ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, }; +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) +/* Structure for extending sampling time on per-pin basis */ +struct nu_eadc_extsmpt { + PinName pin; + uint32_t value; +}; + +static struct nu_eadc_extsmpt eadc_extsmpt_arr[] = { + MBED_CONF_TARGET_EADC_EXTSMPT_LIST +}; +#endif + void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); @@ -92,6 +105,18 @@ // Configure the sample module Nmod for analog input channel Nch and software trigger source EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn); +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) + // Extend sampling time in EADC clocks on per-pin basis + struct nu_eadc_extsmpt *eadc_extsmpt_pos = eadc_extsmpt_arr; + struct nu_eadc_extsmpt *eadc_extsmpt_end = eadc_extsmpt_arr + sizeof (eadc_extsmpt_arr) / sizeof (eadc_extsmpt_arr[0]); + for (; eadc_extsmpt_pos != eadc_extsmpt_end; eadc_extsmpt_pos ++) { + if (eadc_extsmpt_pos->pin == pin) { + EADC_SetExtendSampleTime(eadc_base, chn, eadc_extsmpt_pos->value); + break; + } + } +#endif + eadc_modinit_mask |= 1 << chn; } diff --git a/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c index 5009ffa..3ffc27b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c @@ -24,6 +24,7 @@ #include "pinmap.h" #include "PeripheralPins.h" #include "nu_modutil.h" +#include "hal/PinNameAliases.h" static uint32_t eadc_modinit_mask = 0; @@ -46,6 +47,18 @@ {ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, }; +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) +/* Structure for extending sampling time on per-pin basis */ +struct nu_eadc_extsmpt { + PinName pin; + uint32_t value; +}; + +static struct nu_eadc_extsmpt eadc_extsmpt_arr[] = { + MBED_CONF_TARGET_EADC_EXTSMPT_LIST +}; +#endif + void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); @@ -90,6 +103,18 @@ */ EADC_SetExtendSampleTime(eadc_base, chn, 10); +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) + // Extend sampling time in EADC clocks on per-pin basis + struct nu_eadc_extsmpt *eadc_extsmpt_pos = eadc_extsmpt_arr; + struct nu_eadc_extsmpt *eadc_extsmpt_end = eadc_extsmpt_arr + sizeof (eadc_extsmpt_arr) / sizeof (eadc_extsmpt_arr[0]); + for (; eadc_extsmpt_pos != eadc_extsmpt_end; eadc_extsmpt_pos ++) { + if (eadc_extsmpt_pos->pin == pin) { + EADC_SetExtendSampleTime(eadc_base, chn, eadc_extsmpt_pos->value); + break; + } + } +#endif + eadc_modinit_mask |= 1 << chn; } diff --git a/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c index 48b94b6..36cea1f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c @@ -23,6 +23,7 @@ #include "pinmap.h" #include "PeripheralPins.h" #include "nu_modutil.h" +#include "hal/PinNameAliases.h" static uint32_t eadc_modinit_mask = 0; @@ -45,6 +46,18 @@ {ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, }; +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) +/* Structure for extending sampling time on per-pin basis */ +struct nu_eadc_extsmpt { + PinName pin; + uint32_t value; +}; + +static struct nu_eadc_extsmpt eadc_extsmpt_arr[] = { + MBED_CONF_TARGET_EADC_EXTSMPT_LIST +}; +#endif + void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); @@ -81,6 +94,18 @@ // Configure the sample module Nmod for analog input channel Nch and software trigger source EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn); +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) + // Extend sampling time in EADC clocks on per-pin basis + struct nu_eadc_extsmpt *eadc_extsmpt_pos = eadc_extsmpt_arr; + struct nu_eadc_extsmpt *eadc_extsmpt_end = eadc_extsmpt_arr + sizeof (eadc_extsmpt_arr) / sizeof (eadc_extsmpt_arr[0]); + for (; eadc_extsmpt_pos != eadc_extsmpt_end; eadc_extsmpt_pos ++) { + if (eadc_extsmpt_pos->pin == pin) { + EADC_SetExtendSampleTime(eadc_base, chn, eadc_extsmpt_pos->value); + break; + } + } +#endif + eadc_modinit_mask |= 1 << chn; } diff --git a/targets/TARGET_NUVOTON/TARGET_M451/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M451/analogin_api.c index 7eebaf3..b559d77 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/analogin_api.c @@ -22,6 +22,7 @@ #include "pinmap.h" #include "PeripheralPins.h" #include "nu_modutil.h" +#include "hal/PinNameAliases.h" static uint32_t eadc_modinit_mask = 0; @@ -44,6 +45,18 @@ {ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL}, }; +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) +/* Structure for extending sampling time on per-pin basis */ +struct nu_eadc_extsmpt { + PinName pin; + uint32_t value; +}; + +static struct nu_eadc_extsmpt eadc_extsmpt_arr[] = { + MBED_CONF_TARGET_EADC_EXTSMPT_LIST +}; +#endif + void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); @@ -80,7 +93,19 @@ // Configure the sample module Nmod for analog input channel Nch and software trigger source EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn); - + + #if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) + // Extend sampling time in EADC clocks on per-pin basis + struct nu_eadc_extsmpt *eadc_extsmpt_pos = eadc_extsmpt_arr; + struct nu_eadc_extsmpt *eadc_extsmpt_end = eadc_extsmpt_arr + sizeof (eadc_extsmpt_arr) / sizeof (eadc_extsmpt_arr[0]); + for (; eadc_extsmpt_pos != eadc_extsmpt_end; eadc_extsmpt_pos ++) { + if (eadc_extsmpt_pos->pin == pin) { + EADC_SetExtendSampleTime(eadc_base, chn, eadc_extsmpt_pos->value); + break; + } + } +#endif + eadc_modinit_mask |= 1 << chn; } diff --git a/targets/TARGET_NUVOTON/TARGET_M460/CMakeLists.txt b/targets/TARGET_NUVOTON/TARGET_M460/CMakeLists.txt index 2714ef9..82518cc 100644 --- a/targets/TARGET_NUVOTON/TARGET_M460/CMakeLists.txt +++ b/targets/TARGET_NUVOTON/TARGET_M460/CMakeLists.txt @@ -13,6 +13,7 @@ INTERFACE analogin_api.c analogout_api.c + can_api.c crypto/crypto-misc.cpp diff --git a/targets/TARGET_NUVOTON/TARGET_M460/README.md b/targets/TARGET_NUVOTON/TARGET_M460/README.md index f4086d0..e332dde 100644 --- a/targets/TARGET_NUVOTON/TARGET_M460/README.md +++ b/targets/TARGET_NUVOTON/TARGET_M460/README.md @@ -1,5 +1,14 @@ # Nuvoton M460 series +## CAN + +Current CAN HAL implementation has the following characteristics: + +1. By default, filter handle 0 is configured to accept all messages as requested. +1. Support only single filter handle semantics, that is, filter handle 0. + The `handle` argument passed to `can_filter()` or `can_read()` is ignored. + All filter related operations are done on filter handle 0. + ## HyperRAM HyperRAM, via Hyper Bus Interface Controller (HBI), is mapped to two regions: `0x0A00_0000`–`0x0BFF_FFFF` and `0x8000_0000`–`0x81FF_FFFF`, through which CPU can direct access. diff --git a/targets/TARGET_NUVOTON/TARGET_M460/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M460/analogin_api.c index bf6aeca..d0d01c4 100644 --- a/targets/TARGET_NUVOTON/TARGET_M460/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M460/analogin_api.c @@ -25,6 +25,7 @@ #include "PeripheralPins.h" #include "gpio_api.h" #include "nu_modutil.h" +#include "hal/PinNameAliases.h" static uint32_t eadc_modinit_mask = 0; @@ -84,6 +85,18 @@ {ADC_2_15, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, }; +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) +/* Structure for extending sampling time on per-pin basis */ +struct nu_eadc_extsmpt { + PinName pin; + uint32_t value; +}; + +static struct nu_eadc_extsmpt eadc_extsmpt_arr[] = { + MBED_CONF_TARGET_EADC_EXTSMPT_LIST +}; +#endif + void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); @@ -126,6 +139,18 @@ // Configure the sample module Nmod for analog input channel Nch and software trigger source EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn); +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) + // Extend sampling time in EADC clocks on per-pin basis + struct nu_eadc_extsmpt *eadc_extsmpt_pos = eadc_extsmpt_arr; + struct nu_eadc_extsmpt *eadc_extsmpt_end = eadc_extsmpt_arr + sizeof (eadc_extsmpt_arr) / sizeof (eadc_extsmpt_arr[0]); + for (; eadc_extsmpt_pos != eadc_extsmpt_end; eadc_extsmpt_pos ++) { + if (eadc_extsmpt_pos->pin == pin) { + EADC_SetExtendSampleTime(eadc_base, chn, eadc_extsmpt_pos->value); + break; + } + } +#endif + eadc_modinit_mask |= 1 << chn; } diff --git a/targets/TARGET_NUVOTON/TARGET_M460/can_api.c b/targets/TARGET_NUVOTON/TARGET_M460/can_api.c new file mode 100644 index 0000000..88a63e3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/can_api.c @@ -0,0 +1,1024 @@ +/* + * Copyright (c) 2023, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "can_api.h" + +#if DEVICE_CAN + +#include "cmsis.h" +#include "mbed_error.h" +#include "mbed_assert.h" +#include "mbed_toolchain.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include +#include +#include + +/* Notes of implementation + * + * 1. Each CANFD instance supports two IRQ lines. Use only line 0. Line 1 is not used. + * 2. For Rx disabling multiple filter handles, + * (1) Map all filter handles to filter handle 0 + * (2) Use Rx FIFO 0 for filter handle 0 + * (3) Support mask + * 3. For Rx enabling multiple filter handles, + * (1) Map filter handles to SID/XID filter elements directly: 0 to 0/0, 1 to 1/1, etc. + * (2) Use Rx FIFO 0 for filter handle 0 + * (3) Use Rx FIFO 1 for filter handle through first invoking can_filter() + * (4) Use dedicated Rx Buffer for other filter handles + * The front half for SID filter element and back half for XID filter element + * (5) Support mask only for filter handle 0 and the one through first invoking can_filter() + * H/W supports mask on Rx FIFO 0/1 but not on dedicated Rx Buffer. + * 4. Continuing above, the thread below discusses on CAN filter more precisely: + * https://os.mbed.com/questions/85183/How-to-use-CAN-filter-function/ + * It has some points to note: + * (1) No message will get accepted without filter configured. + * (2) Received message is compared following filter handle 0, 1, 2, 3. + * If no match, the message is discarded. + * On match, the message can be fetched through can_read() with the match filter. + * (3) It is required filter handle 0 be configured in the constructor and accept any message by default. + * If not reconfigured, no message will reach filter handle other than 0. + * 5. For Tx, use only dedicated Tx Buffer. BSP CANFD driver doesn't support Tx FIFO/Queue. + * 6. Support no CAN FD. + * 7. CAN HAL doesn't define modes clearly. Following other chip porting, map them to H/W as below: + * MODE_NORMAL --> Normal operation + * MODE_SILENT --> Bus Monitor mode + * MODE_TEST_GLOBAL/LOCAL --> Test/External Loop Back mode + * MODE_TEST_SILENT --> Test/Internal Loop Back mode + */ + +/* Enable or not multiple filter handles + * + * Reasons for disabling the feature: + * (1) Per-handle implementation doesn't support mask on all filter handles. + * SID/XID filter elements directing to Rx FIFO 0/1 can support mask. + * SID/XID filter elements directing to dedicated Rx Buffer cannot support mask. + * (2) Mbed OS CAN HAL API allows ignoring 'handle' parameter. + * (3) The default filter handle 0 will accept all messages, + * so by default, all messages cannot reach other user defined ones, + * unless filter handle 0 reconfigured. + * However, most samples are unaware of this. + */ +#define NU_CAN_EN_MULT_HNDL 0 + +/* Max number of message ID filter handle */ +#define NU_CAN_MAXNUM_HNDL 8 + +/* Max number of Standard message ID filter elements configured */ +#define NU_CAN_MAXNUM_SIDFLTR NU_CAN_MAXNUM_HNDL + +/* Max number of Extended message ID filter elements configured */ +#define NU_CAN_MAXNUM_XIDFLTR NU_CAN_MAXNUM_HNDL + +/* Max number of dedicated Rx Buffer elements configured */ +#define NU_CAN_MAXNUM_RXBUF (NU_CAN_MAXNUM_SIDFLTR + NU_CAN_MAXNUM_XIDFLTR) + +/* Configured number of SID filter elements must be less than H/W limit */ +static_assert(NU_CAN_MAXNUM_SIDFLTR <= CANFD_MAX_11_BIT_FTR_ELEMS, + "Configured number of SID filter elements must be less than H/W limit"); + +/* Configured number of SID filter elements must be equal to filter handles */ +static_assert(NU_CAN_MAXNUM_SIDFLTR == NU_CAN_MAXNUM_HNDL, + "Configured number of SID filter elements must be equal to filter handles"); + +/* Configured number of XID filter elements must be less than H/W limit */ +static_assert(NU_CAN_MAXNUM_XIDFLTR <= CANFD_MAX_29_BIT_FTR_ELEMS, + "Configured number of XID filter elements must be less than H/W limit"); + +/* Configured number of XID filter elements must be equal to filter handles */ +static_assert(NU_CAN_MAXNUM_XIDFLTR == NU_CAN_MAXNUM_HNDL, + "Configured number of XID filter elements must be equal to filter handles"); + +/* Configured number of dedicated Rx Buffer elements must be less than H/W limit */ +static_assert(NU_CAN_MAXNUM_RXBUF <= CANFD_MAX_RX_BUF_ELEMS, + "Configured number of dedicated Rx Buffer elements must be less than H/W limit"); + +/* Convert to string literal */ +#define NU_STR_(X) #X +#define NU_STR(X) NU_STR_(X) + +/* Rx buffer type for filter */ +enum { + NU_CAN_RXBUF_TYPE_NONE = 0, + NU_CAN_RXBUF_TYPE_FIFO_0, + NU_CAN_RXBUF_TYPE_FIFO_1, + NU_CAN_RXBUF_TYPE_DEDICATED, +}; + +struct nu_can_filter { + uint32_t id; + uint32_t mask; + CANFormat format; + int32_t handle; + uint32_t rxbuf_type; +}; + +struct nu_can_var { + CANFD_FD_T canfd_config; + bool rx_fifo_0_used; + bool rx_fifo_1_used; + struct nu_can_filter filters[NU_CAN_MAXNUM_HNDL]; + CANFD_FD_MSG_T msg_staging; + can_irq_handler irq_handler; + uintptr_t irq_context; + + /* Mark the following area is reserved for not being cleared */ + uint32_t reserved; + + /* Following fields are static-initialized */ + void (*vec)(void); + IRQn_Type irq_line1; +}; + +/* IRQ handler for CAN IRQ line 0. CAN IRQ line 1 is not used. */ +void CANFD00_IRQHandler(void); +void CANFD10_IRQHandler(void); +void CANFD20_IRQHandler(void); +void CANFD30_IRQHandler(void); + +static void can_reconfig(can_t *obj, CANFD_FD_T *canfd_config); +static void can_irq(CANName can); +static void can_filters_reconfig(can_t *obj); +static int can_filter_bind_rxbuf_type(can_t *obj, struct nu_can_filter *filter); +static int can_filter_config(can_t *obj, const struct nu_can_filter *filter); + +/* Get SID/XID filter element index by filter handle + * + * One filter handle maps to one SID filter and one XID filter. + * These three are numbered the same. + */ +static inline uint32_t can_filter_sidfltr_index(const struct nu_can_filter *filter) +{ + return ((uint32_t) filter->handle); +} +static inline uint32_t can_filter_xidfltr_index(const struct nu_can_filter *filter) +{ + return ((uint32_t) filter->handle); +} + +/* Get dedicated Rx Buffer element index for SID/XID filter element by filter handle + * + * Front half of dedicated Rx Buffer elements for SID filter, back half for XID filter. + */ +static inline uint32_t can_filter_sidfltr_rxbuf_index(const struct nu_can_filter *filter) +{ + return ((uint32_t) filter->handle); +} +static inline uint32_t can_filter_xidfltr_rxbuf_index(const struct nu_can_filter *filter) +{ + return (((uint32_t) filter->handle) + NU_CAN_MAXNUM_SIDFLTR); +} + +/* Is message matched? */ +static inline bool can_filter_message_matched(const struct nu_can_filter *filter, const CANFD_FD_MSG_T *msg_staging) +{ + if (filter->format == CANStandard && msg_staging->eIdType != eCANFD_SID) { + return false; + } + + if (filter->format == CANExtended && msg_staging->eIdType != eCANFD_XID) { + return false; + } + + if ((filter->id & filter->mask) != (msg_staging->u32Id & filter->mask)) { + return false; + } + + return true; +} + +static struct nu_can_var can0_var = { + .vec = CANFD00_IRQHandler, + .irq_line1 = CANFD01_IRQn, +}; +static struct nu_can_var can1_var = { + .vec = CANFD10_IRQHandler, + .irq_line1 = CANFD11_IRQn, +}; +static struct nu_can_var can2_var = { + .vec = CANFD20_IRQHandler, + .irq_line1 = CANFD21_IRQn, +}; +static struct nu_can_var can3_var = { + .vec = CANFD30_IRQHandler, + .irq_line1 = CANFD31_IRQn, +}; + +static const struct nu_modinit_s can_modinit_tab[] = { + {CAN_0, CANFD0_MODULE, CLK_CLKSEL0_CANFD0SEL_HCLK, CLK_CLKDIV5_CANFD0(1), CANFD0_RST, CANFD00_IRQn, &can0_var}, + {CAN_1, CANFD1_MODULE, CLK_CLKSEL0_CANFD1SEL_HCLK, CLK_CLKDIV5_CANFD1(1), CANFD1_RST, CANFD10_IRQn, &can1_var}, + {CAN_2, CANFD2_MODULE, CLK_CLKSEL0_CANFD2SEL_HCLK, CLK_CLKDIV5_CANFD2(1), CANFD2_RST, CANFD20_IRQn, &can2_var}, + {CAN_3, CANFD3_MODULE, CLK_CLKSEL0_CANFD3SEL_HCLK, CLK_CLKDIV5_CANFD3(1), CANFD3_RST, CANFD30_IRQn, &can3_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) +{ + uint32_t can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD); + uint32_t can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD); + obj->can = (CANName)pinmap_merge(can_rd, can_td); + MBED_ASSERT((int)obj->can != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + + /* Clear var to zero except reserved area */ + memset(var, 0x00, offsetof(struct nu_can_var, reserved)); + + obj->pin_rd = rd; + obj->pin_td = td; + + pinmap_pinout(rd, PinMap_CAN_RD); + pinmap_pinout(td, PinMap_CAN_TD); + + // Enable IP clock + CLK_EnableModuleClock(modinit->clkidx); + + // Reset IP + SYS_ResetModule(modinit->rsetidx); + + CANFD_FD_T *canfd_config = &var->canfd_config; + + /* Based on BSP CAN driver default configuration, no CAN FD */ + CANFD_GetDefaultConfig(canfd_config, CANFD_OP_CAN_MODE); + + /* Change default configuration here */ + { + /* Change normal bit rate to specified. CAN FD is not supported, + * so data bit rate will be the same as above. */ + if (hz > 0) { + canfd_config->sBtConfig.sNormBitRate.u32BitRate = hz; + } + + /* Change max number of SID filter elements */ + canfd_config->sElemSize.u32SIDFC = NU_CAN_MAXNUM_SIDFLTR; + + /* Change max number of SID filter elements */ + canfd_config->sElemSize.u32XIDFC = NU_CAN_MAXNUM_XIDFLTR; + + /* Change max number of dedicated Rx Buffer elements */ + canfd_config->sElemSize.u32RxBuf = NU_CAN_MAXNUM_RXBUF; + + can_reconfig(obj, canfd_config); + } + + /* As required, filter handle 0 defaults to accept-any */ + struct nu_can_filter *filter_0 = &var->filters[0]; + filter_0->id = 0; + filter_0->mask = 0; + filter_0->format = CANAny; + filter_0->handle = 0; + + /* Bind filter handle 0 to Rx Buffer type */ + can_filter_bind_rxbuf_type(obj, filter_0); + MBED_ASSERT(filter_0->rxbuf_type != NU_CAN_RXBUF_TYPE_NONE); + + /* Configure filter handle 0 */ + can_filter_config(obj, filter_0); +} + +void can_init(can_t *obj, PinName rd, PinName td) +{ + can_init_freq(obj, rd, td, -1); +} + +void can_free(can_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(obj->can); + + CANFD_Close(can_base); + + // Reset this module + SYS_ResetModule(modinit->rsetidx); + + // Disable interrupts + CANFD_DisableInt(can_base, + 0xFFFFFFFF, // interrupt line 0 + 0, // interrupt line 1 unused + 0xFFFFFFFF, // Tx Buffer Transmission 0-31 Interrupts + 0xFFFFFFFF); // Tx Buffer Cancellation Finished 0-31 Interrupts + NVIC_DisableIRQ(modinit->irq_n); + + // Disable IP clock + CLK_DisableModuleClock(modinit->clkidx); + + /* Free up pins */ + gpio_set(obj->pin_rd); + gpio_set(obj->pin_td); + obj->pin_rd = NC; + obj->pin_td = NC; +} + +int can_frequency(can_t *obj, int hz) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + + /* Based on previous configuration */ + CANFD_FD_T *canfd_config = &var->canfd_config; + + canfd_config->sBtConfig.sNormBitRate.u32BitRate = hz; + + can_reconfig(obj, canfd_config); + + /* With BSP CAN FD driver, all filters configured before will get cleared by above call. + * Reconfigure them back. */ + can_filters_reconfig(obj); + + /* 1 on success, or 0 on failure */ + return 1; +} + +void CANFD00_IRQHandler(void) +{ + can_irq(CAN_0); +} + +void CANFD10_IRQHandler(void) +{ + can_irq(CAN_1); +} + +void CANFD20_IRQHandler(void) +{ + can_irq(CAN_2); +} + +void CANFD30_IRQHandler(void) +{ + can_irq(CAN_3); +} + +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + + var->irq_handler = handler; + var->irq_context = context; +} + +void can_irq_free(can_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + + var->irq_handler = NULL; + var->irq_context = 0; +} + +void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable) +{ + if (enable) { + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + + NVIC_SetVector(modinit->irq_n, (uint32_t) var->vec); + NVIC_EnableIRQ(modinit->irq_n); + } + + /* We use only interrupt line 0. */ + uint32_t line0_interrupts = 0; + uint32_t line1_interrupts = 0; + + /* Interrupt mapping from HAL CAN to MCU CANFD */ + switch (irq) { + case IRQ_RX: + line0_interrupts = CANFD_IE_RF0NE_Msk | CANFD_IE_RF1NE_Msk | CANFD_IE_DRXE_Msk; + break; + + case IRQ_TX: + line0_interrupts = CANFD_IE_TCE_Msk; + break; + + case IRQ_ERROR: + line0_interrupts = CANFD_IE_EWE_Msk; + break; + + case IRQ_OVERRUN: + break; + + case IRQ_WAKEUP: + break; + + case IRQ_PASSIVE: + line0_interrupts = CANFD_IE_EPE_Msk; + break; + + case IRQ_ARB: + break; + + case IRQ_BUS: + line0_interrupts = CANFD_IE_BOE_Msk; + break; + + case IRQ_READY: + break; + + default: + break; + } + + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(obj->can); + + uint32_t ie = CANFD_ReadReg(&can_base->IE); + + /* Tx Buffer Transmission/Cancellation Finished Interrupt Enable + * + * Each Tx Buffer has its own Transmission/Cancellation Finished Interrupt Enable bit. + * Dependent on their overall switch IE.TCE/IE.TCFE, these bits are set altogether or not. + */ + uint32_t txbtie = (CANFD_IE_TCE_Msk & (ie | line0_interrupts)) ? 0xFFFFFFFF : 0; + uint32_t txbcie = (CANFD_IE_TCFE_Msk & (ie | line0_interrupts)) ? 0xFFFFFFFF : 0; + + if (enable) { + CANFD_EnableInt(can_base, line0_interrupts, line1_interrupts, txbtie, txbcie); + } else { + CANFD_DisableInt(can_base, line0_interrupts, line1_interrupts, txbtie, txbcie); + } +} + +int can_write(can_t *obj, CAN_Message msg, int cc) +{ + /* Unused */ + (void) cc; + + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(obj->can); + + /* Populate the message */ + CANFD_FD_MSG_T *msg_staging = &var->msg_staging; + memset(msg_staging, 0x00, sizeof(CANFD_FD_MSG_T)); + + /* Message ID */ + msg_staging->u32Id = msg.id; + /* CANFD_FD_MSG_T.u32DLC, not suitable naming, is data length in bytes, not data length code. */ + msg_staging->u32DLC = (msg.len <= CANFD_MAX_MESSAGE_BYTES) ? msg.len : CANFD_MAX_MESSAGE_BYTES; + memcpy(msg_staging->au8Data, msg.data, msg_staging->u32DLC); + /* Standard/extended message */ + msg_staging->eIdType = (msg.format == CANStandard) ? eCANFD_SID : eCANFD_XID; + /* Data/remote message */ + msg_staging->eFrmType = (msg.type == CANData) ? eCANFD_DATA_FRM : eCANFD_REMOTE_FRM; + /* No FD format */ + msg_staging->bFDFormat = 0; + /* No bit rate switch */ + msg_staging->bBitRateSwitch = 0; + + int success; + + /* BSP CAN driver supports Tx Dedicated Buffer */ + uint32_t i; + for (i = 0; i < var->canfd_config.sElemSize.u32TxBuf; i ++) { + success = CANFD_TransmitTxMsg(can_base, i, msg_staging); + if (success) { + return 1; + } + } + + /* BSP CAN driver supports no Tx FIFO/Queue */ + + return 0; +} + +int can_read(can_t *obj, CAN_Message *msg, int handle) +{ +#if NU_CAN_EN_MULT_HNDL + /* Check validity of filter handle */ + if (handle < 0 || handle >= NU_CAN_MAXNUM_HNDL) { + error("Support max " NU_STR(NU_CAN_MAXNUM_HNDL) " CAN filters"); + return 0; + } +#else + /* Single filter handle 0 */ + int32_t handle_orig = handle; + (void) handle_orig; + handle = 0; +#endif + + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + const struct nu_can_filter *filter = &var->filters[handle]; + CANFD_FD_MSG_T *msg_staging = &var->msg_staging; + + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(obj->can); + + if (filter->rxbuf_type == NU_CAN_RXBUF_TYPE_FIFO_0 || + filter->rxbuf_type == NU_CAN_RXBUF_TYPE_FIFO_1) { + uint32_t fifo_idx = (filter->rxbuf_type == NU_CAN_RXBUF_TYPE_FIFO_0) ? 0: 1; + while (1) { + if (!CANFD_ReadRxFifoMsg(can_base, fifo_idx, msg_staging)) { + /* Rx FIFO 0/1 empty */ + goto message_no_accepted; + } + + if (!can_filter_message_matched(filter, msg_staging)) { + /* Not matched, go next one */ + continue; + } + + /* Find one matched */ + goto message_matched; + } + } else { + /* Get dedicated Rx Buffer element index for SID/XID filter element by filter handle */ + uint32_t sidfltr_rxdbf_idx = can_filter_sidfltr_rxbuf_index(filter); + uint32_t xidfltr_rxdbf_idx = can_filter_xidfltr_rxbuf_index(filter); + + /* Receive from dedicated Rx Buffer for SID filter element */ + if (filter->format == CANStandard || filter->format == CANAny) { + if (!CANFD_ReadRxBufMsg(can_base, sidfltr_rxdbf_idx, msg_staging)) { + /* Dedicated Rx Buffer empty */ + goto check_xid_filter; + } + + if (!can_filter_message_matched(filter, msg_staging)) { + /* Not matched */ + goto check_xid_filter; + } + + /* Find one matched */ + goto message_matched; + } + +check_xid_filter: + + /* Receive from dedicated Rx Buffer for XID filter element */ + if (filter->format == CANExtended || filter->format == CANAny) { + if (!CANFD_ReadRxBufMsg(can_base, xidfltr_rxdbf_idx, msg_staging)) { + /* Dedicated Rx Buffer empty */ + goto message_no_accepted; + } + + if (!can_filter_message_matched(filter, msg_staging)) { + /* Not matched */ + goto message_no_matched; + } + + /* Find one matched */ + goto message_matched; + } + } + +message_no_accepted: +message_no_matched: + + return 0; + +message_matched: + + /* ID match, populate the message */ + memset(msg, 0x00, sizeof(CAN_Message)); + + /* Message ID */ + msg->id = msg_staging->u32Id; + /* CANFD_FD_MSG_T.u32DLC, not suitable naming, is data length in bytes, not data length code. */ + msg->len = (msg_staging->u32DLC <= sizeof(msg->data)) ? msg_staging->u32DLC : sizeof(msg->data); + memcpy(&msg->data[0], &msg_staging->au8Data[0], msg->len); + /* Standard/Extended message */ + msg->format = (msg_staging->eIdType == eCANFD_SID) ? CANStandard : CANExtended; + /* Data/Remote message */ + msg->type = (msg_staging->eFrmType == eCANFD_DATA_FRM) ? CANData : CANRemote; + + return 1; +} + +int can_mode(can_t *obj, CanMode mode) +{ + bool monitor_enabled; + bool test_enabled; + bool loopback_enabled; + + switch (mode) { + case MODE_RESET: + MBED_FALLTHROUGH; + case MODE_NORMAL: + monitor_enabled = false; + test_enabled = false; + loopback_enabled = false; + break; + + case MODE_SILENT: + monitor_enabled = true; + test_enabled = false; + loopback_enabled = false; + break; + + case MODE_TEST_GLOBAL: + MBED_FALLTHROUGH; + case MODE_TEST_LOCAL: + monitor_enabled = false; + test_enabled = true; + loopback_enabled = true; + break; + + case MODE_TEST_SILENT: + monitor_enabled = true; + test_enabled = true; + loopback_enabled = true; + break; + + default: + /* 1 if success, or 0 if failure */ + return 0; + } + + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(obj->can); + + /* Enter INIT mode for configuration */ + CANFD_RunToNormal(can_base, false); + + /* Enable write-protect configuration change */ + can_base->CCCR = CANFD_ReadReg(&can_base->CCCR) | CANFD_CCCR_CCE_Msk; + + /* Enable monitor or not */ + if (monitor_enabled) { + can_base->CCCR = CANFD_ReadReg(&can_base->CCCR) | CANFD_CCCR_MON_Msk; + } else { + can_base->CCCR = CANFD_ReadReg(&can_base->CCCR) & ~CANFD_CCCR_MON_Msk; + } + + /* Enable Test mode or not */ + if (test_enabled) { + can_base->CCCR = CANFD_ReadReg(&can_base->CCCR) | CANFD_CCCR_TEST_Msk; + } else { + can_base->CCCR = CANFD_ReadReg(&can_base->CCCR) & ~CANFD_CCCR_TEST_Msk; + } + + /* Enable loopback or not */ + if (loopback_enabled) { + can_base->TEST = CANFD_ReadReg(&can_base->TEST) | CANFD_TEST_LBCK_Msk; + } else { + can_base->TEST = CANFD_ReadReg(&can_base->TEST) & ~CANFD_TEST_LBCK_Msk; + } + + /* Leave INIT mode for normal operation */ + CANFD_RunToNormal(can_base, true); + + /* 1 if success, or 0 if failure */ + return 1; +} + +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) +{ +#if NU_CAN_EN_MULT_HNDL + /* Check validity of filter handle */ + if (handle < 0 || handle >= NU_CAN_MAXNUM_HNDL) { + error("Support max " NU_STR(NU_CAN_MAXNUM_HNDL) " CAN filters"); + return 0; + } +#else + /* Single filter handle 0 */ + int32_t handle_orig = handle; + (void) handle_orig; + handle = 0; +#endif + + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + struct nu_can_filter *filter = &var->filters[handle]; + + /* Keep user-defined filter configuration */ + filter->id = id; + filter->mask = mask; + filter->format = format; + filter->handle = handle; + + /* Bind filter to Rx Buffer type */ + can_filter_bind_rxbuf_type(obj, filter); + MBED_ASSERT(filter->rxbuf_type != NU_CAN_RXBUF_TYPE_NONE); + + if (can_filter_config(obj, filter)) { +#if NU_CAN_EN_MULT_HNDL + return handle; +#else + /* NOTE: 0 is ambiguous, error or filter handle 0. */ + return handle_orig; +#endif + } else { + return 0; + } +} + +void can_reset(can_t *obj) +{ + can_mode(obj, MODE_RESET); +} + +unsigned char can_rderror(can_t *obj) +{ + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(obj->can); + + uint32_t ecr = CANFD_ReadReg(&can_base->ECR); + return (uint8_t) ((ecr >> CANFD_ECR_REC_Pos) & CANFD_ECR_REC_Msk); +} + +unsigned char can_tderror(can_t *obj) +{ + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(obj->can); + + uint32_t ecr = CANFD_ReadReg(&can_base->ECR); + return (uint8_t) ((ecr >> CANFD_ECR_TEC_Pos) & CANFD_ECR_TEC_Msk); +} + +void can_monitor(can_t *obj, int silent) +{ + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(obj->can); + + bool test_enabled = CANFD_ReadReg(&can_base->CCCR) & CANFD_CCCR_TEST_Msk; + + CanMode mode; + + if (silent) { + if (test_enabled) { + mode = MODE_TEST_SILENT; + } else { + mode = MODE_SILENT; + } + } else { + if (test_enabled) { + mode = MODE_TEST_GLOBAL; + } else { + mode = MODE_NORMAL; + } + } + + can_mode(obj, mode); +} + +const PinMap *can_rd_pinmap() +{ + return PinMap_CAN_TD; +} + +const PinMap *can_td_pinmap() +{ + return PinMap_CAN_RD; +} + +void can_reconfig(can_t *obj, CANFD_FD_T *canfd_config) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(obj->can); + + /* Enter INIT mode for configuration */ + CANFD_RunToNormal(can_base, false); + + /* Enable write-protect configuration change */ + can_base->CCCR = CANFD_ReadReg(&can_base->CCCR) | CANFD_CCCR_CCE_Msk; + + /* Keep IRQ enabled or not */ + bool irq_enabled = NVIC_GetEnableIRQ(modinit->irq_n); + + CANFD_Open(can_base, canfd_config); + + /* Cover side effect of CANFD_Open() */ + if (!irq_enabled) { + NVIC_DisableIRQ(modinit->irq_n); // Disable IRQ line 0 + NVIC_DisableIRQ(var->irq_line1); // Disable IRQ line 1 + } + + /* Leave INIT mode for normal operation */ + CANFD_RunToNormal(can_base, true); +} + +/** + * \brief Reconfigure filters configured before + */ +static void can_filters_reconfig(can_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + + struct nu_can_filter *filter = var->filters; + struct nu_can_filter *filter_end = var->filters + sizeof(var->filters) / sizeof(var->filters[0]); + + for (; filter != filter_end; filter ++) { + /* A filter not binding to Rx Buffer type is not configured before. */ + if (filter->rxbuf_type == NU_CAN_RXBUF_TYPE_NONE) { + continue; + } + + can_filter_config(obj, filter); + } +} + +/** + * \brief BInd filter to Rx Buffer type + * + * \return 0 if failure, or 1 if success + */ +static int can_filter_bind_rxbuf_type(can_t *obj, struct nu_can_filter *filter) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + + /* Bind to Rx FIFO 0/1 first if free, or dedicated Rx Buffer */ + if (filter->rxbuf_type == NU_CAN_RXBUF_TYPE_NONE) { + if (!var->rx_fifo_0_used) { + var->rx_fifo_0_used = true; + filter->rxbuf_type = NU_CAN_RXBUF_TYPE_FIFO_0; + } else if (!var->rx_fifo_1_used) { + var->rx_fifo_1_used = true; + filter->rxbuf_type = NU_CAN_RXBUF_TYPE_FIFO_1; + } else { + /* H/W doesn't support mask on directing to dedicated Rx Buffer. */ + if (filter->mask != 0xFFFFFFFF) { + error("CAN HAL supports mask only on first two configured filters (including handle 0). Try disabling mask by setting mask to 0xFFFFFFFF."); + return 0; + } + + filter->rxbuf_type = NU_CAN_RXBUF_TYPE_DEDICATED; + } + } + + return 1; +} + +/** + * \brief Set up message ID filter + * + * \return 0 if failure, or 1 if success + */ +static int can_filter_config(can_t *obj, const struct nu_can_filter *filter) +{ + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(obj->can); + + /* Enter INIT mode for configuration */ + CANFD_RunToNormal(can_base, false); + + /* Enable write-protect configuration change */ + can_base->CCCR = CANFD_ReadReg(&can_base->CCCR) | CANFD_CCCR_CCE_Msk; + + /* Global filter configuration + * + * 1. Reject unmatched standard/extended message ID + * 2. Accept remote message + */ + CANFD_SetGFC(CANFD0, eCANFD_REJ_NON_MATCH_FRM, eCANFD_REJ_NON_MATCH_FRM, 0, 0); + + /* Get SID/XID filter element index by filter handle */ + uint32_t sidfltr_idx = can_filter_sidfltr_index(filter); + uint32_t xidfltr_idx = can_filter_xidfltr_index(filter); + + /* Get dedicated Rx Buffer element index for SID/XID filter element by filter handle */ + uint32_t sidfltr_rxdbf_idx = can_filter_sidfltr_rxbuf_index(filter); + uint32_t xidfltr_rxdbf_idx = can_filter_xidfltr_rxbuf_index(filter); + + /* Configure filter for Standard message ID + * + * Direct accepted message to Rx FIFO 0, Rx FIFO 1, or dedicated Rx Buffer + * + * NOTE: H/W doesn't support mask on directing to dedicated Rx Buffer. + */ + if (filter->format == CANStandard || filter->format == CANAny) { + switch (filter->rxbuf_type) { + case NU_CAN_RXBUF_TYPE_FIFO_0: + CANFD_SetSIDFltr(can_base, sidfltr_idx, CANFD_RX_FIFO0_STD_MASK(filter->id, filter->mask)); + break; + + case NU_CAN_RXBUF_TYPE_FIFO_1: + CANFD_SetSIDFltr(can_base, sidfltr_idx, CANFD_RX_FIFO1_STD_MASK(filter->id, filter->mask)); + break; + + default: + CANFD_SetSIDFltr(can_base, sidfltr_idx, CANFD_RX_BUFFER_STD(filter->id, sidfltr_rxdbf_idx)); + } + } + + /* Configure filter for Extended message ID + * + * Direct accepted message to Rx FIFO 0, Rx FIFO 1, or dedicated Rx Buffer + * + * NOTE: H/W doesn't support mask on directing to dedicated Rx Buffer. + * NOTE: CANFD.XIDAM applies to all XID filters and is unsuitable for the + * per-XID filter requirement. + */ + if (filter->format == CANExtended || filter->format == CANAny) { + switch (filter->rxbuf_type) { + case NU_CAN_RXBUF_TYPE_FIFO_0: + CANFD_SetXIDFltr(can_base, xidfltr_idx, CANFD_RX_FIFO0_EXT_MASK_LOW(filter->id), CANFD_RX_FIFO0_EXT_MASK_HIGH(filter->mask)); + break; + + case NU_CAN_RXBUF_TYPE_FIFO_1: + CANFD_SetXIDFltr(can_base, xidfltr_idx, CANFD_RX_FIFO1_EXT_MASK_LOW(filter->id), CANFD_RX_FIFO1_EXT_MASK_HIGH(filter->mask)); + break; + + default: + CANFD_SetXIDFltr(can_base, xidfltr_idx, CANFD_RX_BUFFER_EXT_LOW(filter->id, xidfltr_rxdbf_idx), CANFD_RX_BUFFER_EXT_HIGH(filter->id, xidfltr_rxdbf_idx)); + } + } + + /* Leave INIT mode for normal operation */ + CANFD_RunToNormal(can_base, true); + + return 1; +} + +static void can_irq(CANName can) +{ + const struct nu_modinit_s *modinit = get_modinit(can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) can); + + struct nu_can_var *var = (struct nu_can_var *) modinit->var; + + CANFD_T *can_base = (CANFD_T *) NU_MODBASE(can); + + uint32_t ir = CANFD_ReadReg(&can_base->IR); + uint32_t ie = CANFD_ReadReg(&can_base->IE); + + /* Clear all interrupt status flags */ + CANFD_ClearStatusFlag(can_base, ir); + + if (ir & CANFD_IR_TC_Msk) { + if (var->irq_handler && (ie & CANFD_IE_TCE_Msk)) { + var->irq_handler(var->irq_context, IRQ_TX); + } + } + + if (ir & (CANFD_IR_RF0N_Msk | CANFD_IR_RF1N_Msk | CANFD_IR_DRX_Msk)) { + if (var->irq_handler && (ie & (CANFD_IE_RF0NE_Msk | CANFD_IE_RF1NE_Msk | CANFD_IE_DRXE_Msk))) { + var->irq_handler(var->irq_context, IRQ_RX); + } + } + + if (ir & CANFD_IR_EW_Msk) { + if (var->irq_handler && (ie & CANFD_IE_EWE_Msk)) { + var->irq_handler(var->irq_context, IRQ_ERROR); + } + } + + if (ir & CANFD_IR_EP_Msk) { + if (var->irq_handler && (ie & CANFD_IE_EPE_Msk)) { + var->irq_handler(var->irq_context, IRQ_PASSIVE); + } + } + + if (ir & CANFD_IR_BO_Msk) { + if (var->irq_handler && (ie & CANFD_IE_BOE_Msk)) { + var->irq_handler(var->irq_context, IRQ_BUS); + } + } +} + +#endif // DEVICE_CAN diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_canfd.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_canfd.h index 941c3c9..51424ec 100644 --- a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_canfd.h +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_canfd.h @@ -11,7 +11,7 @@ #define __CANFD_H__ #if defined ( __CC_ARM ) -#pragma anon_unions + #pragma anon_unions #endif #include "NuMicro.h" @@ -37,7 +37,7 @@ #define CANFD_OP_CAN_FD_MODE 1 /* Reserved number of elements in Message RAM - used for calculation of start addresses within RAM Configuration - some element_numbers set to less than max, to stay altogether below 256 words of MessageRAM requirement*/ + some element_numbers set to less than max, to stay altogether below 256 words of Message RAM requirement*/ #define CANFD_MAX_11_BIT_FTR_ELEMS 128ul /*!< maximum is 128 11-bit Filter */ #define CANFD_MAX_29_BIT_FTR_ELEMS 64ul /*!< maximum is 64 29-bit Filter */ #define CANFD_MAX_RX_FIFO0_ELEMS 64ul /*!< maximum is 64 Rx FIFO 0 elements */ @@ -48,12 +48,10 @@ /* CAN FD sram size */ #define CANFD_SRAM_SIZE 0x1800ul +#define CANFD_SRAM_OFFSET 0x200ul /* CAN FD sram address */ -#define CANFD0_SRAM_BASE_ADDR CANFD0_BASE + 0x200ul -#define CANFD1_SRAM_BASE_ADDR CANFD1_BASE + 0x200ul -#define CANFD2_SRAM_BASE_ADDR CANFD2_BASE + 0x200ul -#define CANFD3_SRAM_BASE_ADDR CANFD3_BASE + 0x200ul +#define CANFD_SRAM_BASE_ADDR(psCanfd) ((uint32_t)psCanfd + CANFD_SRAM_OFFSET) /* CAN FD Mask all interrupt */ #define CANFD_INT_ALL_SIGNALS 0x3FFFFFFFul @@ -62,34 +60,49 @@ #define CANFD_MAX_MESSAGE_BYTES 64 /* Maximum size of a CAN FD frame. Must be a valid CAN FD value */ -#define CANFD_MAX_MESSAGE_WORDS CANFD_MAX_MESSAGE_BYTES/4 +#define CANFD_MAX_MESSAGE_WORDS (CANFD_MAX_MESSAGE_BYTES/4) /* Receive message buffer helper macro */ -#define CANFD_RX_BUFFER_STD(id, mbIdx) (7UL << 27) | ((id & 0x7FF) << 16) | (mbIdx & 0x3F) +#define CANFD_RX_BUFFER_STD(id, mbIdx) ((7UL << 27) | ((id & 0x7FF) << 16) | (mbIdx & 0x3F)) /* Receive message buffer extended helper macro - low */ -#define CANFD_RX_BUFFER_EXT_LOW(id, mbIdx) (7UL << 29) | (id & 0x1FFFFFFFUL) +#define CANFD_RX_BUFFER_EXT_LOW(id, mbIdx) ((7UL << 29) | (id & 0x1FFFFFFFUL)) /* Receive message buffer extended helper macro - high */ #define CANFD_RX_BUFFER_EXT_HIGH(id, mbIdx) (mbIdx & 0x3FUL) /* CAN FD Rx FIFO 0 Mask helper macro. */ -#define CANFD_RX_FIFO0_STD_MASK(match, mask) (2UL << 30) | (1UL << 27) | ((match & 0x7FF) << 16) | (mask & 0x7FF) +#define CANFD_RX_FIFO0_STD_MASK(match, mask) ((2UL << 30) | (1UL << 27) | ((match & 0x7FF) << 16) | (mask & 0x7FF)) /* CAN FD Rx FIFO 0 extended Mask helper macro - low. */ -#define CANFD_RX_FIFO0_EXT_MASK_LOW(match) (1UL << 29) | ((match & 0x1FFFFFFF)) +#define CANFD_RX_FIFO0_EXT_MASK_LOW(match) ((1UL << 29) | (match & 0x1FFFFFFF)) /* CAN FD Rx FIFO 0 extended Mask helper macro - high. */ -#define CANFD_RX_FIFO0_EXT_MASK_HIGH(mask) (2UL << 30) | ((mask & 0x1FFFFFFF)) +#define CANFD_RX_FIFO0_EXT_MASK_HIGH(mask) ((2UL << 30) | (mask & 0x1FFFFFFF)) /* CAN FD Rx FIFO 1 Mask helper macro. */ -#define CANFD_RX_FIFO1_STD_MASK(match, mask) (2UL << 30) | (2UL << 27) | ((match & 0x7FF) << 16) | (mask & 0x7FF) +#define CANFD_RX_FIFO1_STD_MASK(match, mask) ((2UL << 30) | (2UL << 27) | ((match & 0x7FF) << 16) | (mask & 0x7FF)) /* CANFD Rx FIFO 1 extended Mask helper macro - low. */ -#define CANFD_RX_FIFO1_EXT_MASK_LOW(match) (2UL << 29) | ((match & 0x1FFFFFFF)) +#define CANFD_RX_FIFO1_EXT_MASK_LOW(match) ((2UL << 29) | (match & 0x1FFFFFFF)) /* CANFD Rx FIFO 1 extended Mask helper macro - high. */ -#define CANFD_RX_FIFO1_EXT_MASK_HIGH(mask) (2UL << 30) | ((mask & 0x1FFFFFFF)) +#define CANFD_RX_FIFO1_EXT_MASK_HIGH(mask) ((2UL << 30) | (mask & 0x1FFFFFFF)) + +/** + * @brief Get the CAN Communication State Flag + * + * @param[in] canfd The pointer of the specified CANFD module + * + * @retval 0 Synchronizing - node is synchronizing on CANFD communication. + * @retval 1 Idle - node is neither receiver nor transmitter. + * @retval 2 Receiver - node is operating as receiver. + * @retval 3 Transmitter - node is operating as transmitter. + * + * @details This macro gets the CANFD communication state. + * \hideinitializer + */ +#define CANFD_GET_COMMUNICATION_STATE(canfd) (((canfd)->PSR & CANFD_PSR_ACT_Msk) >> CANFD_PSR_ACT_Pos) /* CAN FD frame data field size. */ @@ -218,6 +231,15 @@ eCANFD_RX_DBUF = 2 } E_CANFD_RX_BUF_TYPE; +/* CAN FD communication state.*/ +typedef enum +{ + eCANFD_SYNC = 0, + eCANFD_IDLE = 1, + eCANFD_RECEIVER = 2, + eCANFD_TRANSMITTER = 3 +} E_CANFD_COMMUNICATION_STATE; + /* CAN FD Message receive Information: via which RX Buffers, etc. */ typedef struct { @@ -318,7 +340,7 @@ /* Standard ID Filter Element Type */ typedef enum { - eCANFD_SID_FLTR_TYPE_RANGE = 0x0, /*!< Range filter from SFID1 to SFID2 (SFID2 ??SFID1). */ + eCANFD_SID_FLTR_TYPE_RANGE = 0x0, /*!< Range filter from SFID1 to SFID2. */ eCANFD_SID_FLTR_TYPE_DUAL = 0x1, /*!< Dual ID filter for SFID1 or SFID2. */ eCANFD_SID_FLTR_TYPE_CLASSIC = 0x2, /*!< Classic filter: SFID1 = filter, SFID2 = mask. */ eCANFD_SID_FLTR_TYPE_DIS = 0x3 /*!< Filter element disabled */ @@ -327,7 +349,7 @@ /* Extended ID Filter Element Type */ typedef enum { - eCANFD_XID_FLTR_TYPE_RANGE = 0x0, /*!< Range filter from EFID1 to EFID2 (EFID2 ??EFID1). */ + eCANFD_XID_FLTR_TYPE_RANGE = 0x0, /*!< Range filter from EFID1 to EFID2. */ eCANFD_XID_FLTR_TYPE_DUAL = 0x1, /*!< Dual ID filter for EFID1 or EFID2. */ eCANFD_XID_FLTR_TYPE_CLASSIC = 0x2, /*!< Classic filter: EFID1=filter, EFID2=mask */ eCANFD_XID_FLTR_TYPE_RANGE_XIDAM_NOT_APP = 0x3 /*!< XID range filter from EFID1 to EFID2(EFID2 > EFID1), XIDAM not applied */ @@ -361,9 +383,11 @@ } CANFD_TX_EVNT_ELEM_T; -#define CANFD_TIMEOUT SystemCoreClock /* 1 second time-out */ -#define CANFD_TIMEOUT_ERR (-1L) /*!< CANFD operation abort due to timeout error \hideinitializer */ -extern int32_t g_CANFD_i32ErrCode; +#define CANFD_TIMEOUT SystemCoreClock /*!< CANFD time-out counter (1 second time-out) */ +#define CANFD_OK ( 0L) /*!< CANFD operation OK */ +#define CANFD_ERR_FAIL (-1L) /*!< CANFD operation failed */ +#define CANFD_ERR_TIMEOUT (-2L) /*!< CANFD operation abort due to timeout error */ +#define CANFD_READ_REG_TIMEOUT (48UL) /*!< CANFD read register time-out count */ void CANFD_Open(CANFD_T *canfd, CANFD_FD_T *psCanfdStr); void CANFD_Close(CANFD_T *canfd); @@ -372,12 +396,6 @@ uint32_t CANFD_TransmitTxMsg(CANFD_T *canfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg); uint32_t CANFD_TransmitDMsg(CANFD_T *canfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg); void CANFD_SetGFC(CANFD_T *canfd, E_CANFD_ACC_NON_MATCH_FRM eNMStdFrm, E_CANFD_ACC_NON_MATCH_FRM eEMExtFrm, uint32_t u32RejRmtStdFrm, uint32_t u32RejRmtExtFrm); -void CANFD_InitRxFifo(CANFD_T *canfd, uint32_t u32RxFifoNum, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWM, E_CANFD_DATA_FIELD_SIZE eFifoSize); -void CANFD_InitRxDBuf(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eRxBufSize); -void CANFD_InitTxDBuf(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eTxBufSize); -void CANFD_InitTxEvntFifo(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWaterLvl); -void CANFD_ConfigSIDFC(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize); -void CANFD_ConfigXIDFC(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize); void CANFD_SetSIDFltr(CANFD_T *canfd, uint32_t u32FltrIdx, uint32_t u32Filter); void CANFD_SetXIDFltr(CANFD_T *canfd, uint32_t u32FltrIdx, uint32_t u32FilterLow, uint32_t u32FilterHigh); uint32_t CANFD_ReadRxBufMsg(CANFD_T *canfd, uint8_t u8MbIdx, CANFD_FD_MSG_T *psMsgBuf); @@ -391,10 +409,11 @@ uint32_t CANFD_GetTxEvntFifoWaterLvl(CANFD_T *canfd); void CANFD_CopyTxEvntFifoToUsrBuf(CANFD_T *canfd, uint32_t u32TxEvntNum, CANFD_TX_EVNT_ELEM_T *psTxEvntElem); void CANFD_GetBusErrCount(CANFD_T *canfd, uint8_t *pu8TxErrBuf, uint8_t *pu8RxErrBuf); -void CANFD_RunToNormal(CANFD_T *canfd, uint8_t u8Enable); +int32_t CANFD_RunToNormal(CANFD_T *canfd, uint8_t u8Enable); void CANFD_GetDefaultConfig(CANFD_FD_T *psConfig, uint8_t u8OpMode); void CANFD_ClearStatusFlag(CANFD_T *canfd, uint32_t u32InterruptFlag); uint32_t CANFD_GetStatusFlag(CANFD_T *canfd, uint32_t u32IntTypeFlag); +uint32_t CANFD_ReadReg(__I uint32_t* pu32RegAddr); /*@}*/ /* end of group CANFD_EXPORTED_FUNCTIONS */ @@ -406,4 +425,8 @@ } #endif +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + #endif /* __CANFD_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_canfd.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_canfd.c index 5e78726..a4f5aae 100644 --- a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_canfd.c +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_canfd.c @@ -170,24 +170,34 @@ @{ */ -int32_t g_CANFD_i32ErrCode = 0; /*!< CANFD global error code */ - /** @addtogroup CANFD_EXPORTED_FUNCTIONS CAN_FD Exported Functions @{ */ -static uint32_t _GetCanfdSramBaseAddr(CANFD_T * psCanfd) +static void CANFD_InitRxFifo(CANFD_T *canfd, uint32_t u32RxFifoNum, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWM, E_CANFD_DATA_FIELD_SIZE eFifoSize); +static void CANFD_InitRxDBuf(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eRxBufSize); +static void CANFD_InitTxDBuf(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eTxBufSize); +static void CANFD_InitTxEvntFifo(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWaterLvl); +static void CANFD_ConfigSIDFC(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize); +static void CANFD_ConfigXIDFC(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize); + +uint32_t CANFD_ReadReg(__I uint32_t* pu32RegAddr) { - if (psCanfd == CANFD0) - return (CANFD0_SRAM_BASE_ADDR); - else if (psCanfd == CANFD1) - return (CANFD1_SRAM_BASE_ADDR); - else if (psCanfd == CANFD2) - return (CANFD2_SRAM_BASE_ADDR); - else if (psCanfd == CANFD3) - return (CANFD3_SRAM_BASE_ADDR); - - return 0; + uint32_t u32ReadReg; + uint32_t u32TimeOutCnt = CANFD_READ_REG_TIMEOUT; + u32ReadReg = 0UL; + + do + { + u32ReadReg = inpw(pu32RegAddr); + if (--u32TimeOutCnt == 0UL) + { + break; + } + } + while (u32ReadReg == 0UL); + + return u32ReadReg; } /** @@ -211,27 +221,13 @@ u32RamAddrOffset += psConfigSize->u32SIDFC * sizeof(CANFD_STD_FILTER_T); } - /* Get the Standard Message ID Filter element address */ + /* Get the Extended Message ID Filter element address */ if (psConfigSize->u32XIDFC > 0) { psConfigAddr->u32XIDFC_FLESA = u32RamAddrOffset; u32RamAddrOffset += psConfigSize->u32XIDFC * sizeof(CANFD_EXT_FILTER_T); } - /* Get the Tx Buffer element address */ - if (psConfigSize->u32TxBuf > 0) - { - psConfigAddr->u32TXBC_TBSA = u32RamAddrOffset; - u32RamAddrOffset += psConfigSize->u32TxBuf * sizeof(CANFD_BUF_T); - } - - /* Get the Rx Buffer element address */ - if (psConfigSize->u32RxBuf > 0) - { - psConfigAddr->u32RXBC_RBSA = u32RamAddrOffset; - u32RamAddrOffset += psConfigSize->u32RxBuf * sizeof(CANFD_BUF_T); - } - /* Get the Rx FIFO0 element address */ if (psConfigSize->u32RxFifo0 > 0) { @@ -246,14 +242,27 @@ u32RamAddrOffset += psConfigSize->u32RxFifo1 * sizeof(CANFD_BUF_T); } - /* Get the Rx FIFO1 element address */ + /* Get the Rx Buffer element address */ + if (psConfigSize->u32RxBuf > 0) + { + psConfigAddr->u32RXBC_RBSA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32RxBuf * sizeof(CANFD_BUF_T); + } + + /* Get the TX Event FIFO element address */ if (psConfigSize->u32TxEventFifo > 0) { psConfigAddr->u32TXEFC_EFSA = u32RamAddrOffset; u32RamAddrOffset += psConfigSize->u32TxEventFifo * sizeof(CANFD_EXT_FILTER_T); } -} + /* Get the Tx Buffer element address */ + if (psConfigSize->u32TxBuf > 0) + { + psConfigAddr->u32TXBC_TBSA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32TxBuf * sizeof(CANFD_BUF_T); + } +} /** * @brief Get the default configuration structure. @@ -271,13 +280,6 @@ * bEnableLoopBack = FALSE; * bBitRateSwitch = FALSE(CAN Mode) or TRUE(CAN FD Mode); * bFDEn = FALSE(CAN Mode) or TRUE(CAN FD Mode); - * CAN FD Standard ID elements = 12 - * CAN FD Extended ID elements = 10 - * CAN FD TX Buffer elements = 3 - * CAN FD RX Buffer elements = 3 - * CAN FD RX FIFO0 elements = 3 - * CAN FD RX FIFO1 elements = 3 - * CAN FD TX Event FOFI elements = 3 */ void CANFD_GetDefaultConfig(CANFD_FD_T *psConfig, uint8_t u8OpMode) { @@ -303,20 +305,20 @@ /*Get the CAN FD memory address*/ psConfig->u32MRamSize = CANFD_SRAM_SIZE; - /* CAN FD Standard message ID elements as 12 elements */ - psConfig->sElemSize.u32SIDFC = 12; - /* CAN FD Extended message ID elements as 10 elements */ - psConfig->sElemSize.u32XIDFC = 10; - /* CAN FD TX Buffer elements as 3 elements */ - psConfig->sElemSize.u32TxBuf = 3; - /* CAN FD RX Buffer elements as 3 elements */ - psConfig->sElemSize.u32RxBuf = 3; - /* CAN FD RX FIFO0 elements as 3 elements */ - psConfig->sElemSize.u32RxFifo0 = 3; - /* CAN FD RX FIFO1 elements as 3 elements */ - psConfig->sElemSize.u32RxFifo1 = 3; - /* CAN FD TX Event FOFI elements as 3 elements */ - psConfig->sElemSize.u32TxEventFifo = 3; + /* CAN FD Standard message ID elements as 64 elements */ + psConfig->sElemSize.u32SIDFC = 64; + /* CAN FD Extended message ID elements as 64 elements */ + psConfig->sElemSize.u32XIDFC = 64; + /* CAN FD TX Buffer elements as 8 elements */ + psConfig->sElemSize.u32TxBuf = 8; + /* CAN FD RX Buffer elements as 8 elements */ + psConfig->sElemSize.u32RxBuf = 8; + /* CAN FD RX FIFO0 elements as 48 elements */ + psConfig->sElemSize.u32RxFifo0 = 48; + /* CAN FD RX FIFO1 elements as 8 elements */ + psConfig->sElemSize.u32RxFifo1 = 8; + /* CAN FD TX Event FOFI elements as 8 elements */ + psConfig->sElemSize.u32TxEventFifo = 8; /*Calculates the CAN FD RAM buffer address*/ CANFD_CalculateRamAddress(&psConfig->sMRamStartAddr, &psConfig->sElemSize); } @@ -381,17 +383,34 @@ */ static void CANFD_SetTimingConfig(CANFD_T *psCanfd, const CANFD_TIMEING_CONFIG_T *psConfig) { - uint32_t *pu32DBTP; + if (psCanfd == (CANFD_T *)CANFD0) + { + /* Set CANFD0 clock divider number */ + CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD0DIV_Msk) | CLK_CLKDIV5_CANFD0(psConfig->u8PreDivider) ; + } + else if (psCanfd == (CANFD_T *)CANFD1) + { + /* Set CANFD1 clock divider number */ + CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD1DIV_Msk) | CLK_CLKDIV5_CANFD1(psConfig->u8PreDivider) ; + } + else if (psCanfd == (CANFD_T *)CANFD2) + { + /* Set CANFD2 clock divider number */ + CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD2DIV_Msk) | CLK_CLKDIV5_CANFD2(psConfig->u8PreDivider) ; + } + else if (psCanfd == (CANFD_T *)CANFD3) + { + /* Set CANFD3 clock divider number */ + CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD3DIV_Msk) | CLK_CLKDIV5_CANFD3(psConfig->u8PreDivider) ; + } + else + { + return; + } /* configuration change enable */ psCanfd->CCCR |= CANFD_CCCR_CCE_Msk; - if (psCanfd == (CANFD_T *)CANFD0) - { - /* Get CANF D0 clock divider number */ - CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD0DIV_Msk) | CLK_CLKDIV5_CANFD0(psConfig->u8PreDivider) ; - } - /* nominal bit rate */ psCanfd->NBTP = (((psConfig->u8NominalRJumpwidth & 0x7F) - 1) << 25) + (((psConfig->u16NominalPrescaler & 0x1FF) - 1) << 16) + @@ -402,11 +421,10 @@ /* canfd->DBTP */ if (psCanfd->CCCR & CANFD_CCCR_FDOE_Msk) { - pu32DBTP = (((uint32_t *)psCanfd) + 0x03); - *pu32DBTP = (((psConfig->u8DataPrescaler & 0x1F) - 1) << 16) + - ((((psConfig->u8DataPhaseSeg1 + psConfig->u8DataPropSeg) & 0x1F) - 1) << 8) + - (((psConfig->u8DataPhaseSeg2 & 0xF) - 1) << 4) + - (((psConfig->u8DataRJumpwidth & 0xF) - 1) << 0); + psCanfd->DBTP = (((psConfig->u8DataPrescaler & 0x1F) - 1) << 16) + + ((((psConfig->u8DataPhaseSeg1 + psConfig->u8DataPropSeg) & 0x1F) - 1) << 8) + + (((psConfig->u8DataPhaseSeg2 & 0xF) - 1) << 4) + + (((psConfig->u8DataRJumpwidth & 0xF) - 1) << 0); } } @@ -485,7 +503,7 @@ * * @details Calculates the CAN controller timing values for specific baudrates. */ -static uint32_t CANFD_CalculateTimingValues(uint32_t u32NominalBaudRate, uint32_t u32DataBaudRate, uint32_t u32SourceClock_Hz, CANFD_TIMEING_CONFIG_T *psConfig) +static uint32_t CANFD_CalculateTimingValues(CANFD_T *psCanfd, uint32_t u32NominalBaudRate, uint32_t u32DataBaudRate, uint32_t u32SourceClock_Hz, CANFD_TIMEING_CONFIG_T *psConfig) { int i32Nclk; int i32Nclk2; @@ -505,49 +523,46 @@ { i32Nclk2 = i32Nclk * psConfig->u16NominalPrescaler; - if (((u32SourceClock_Hz / i32Nclk2) <= 5) && ((float)(u32SourceClock_Hz) / i32Nclk2) == (u32SourceClock_Hz / i32Nclk2)) + if (((u32SourceClock_Hz / i32Nclk2) <= 5) && ((u32SourceClock_Hz % i32Nclk2) == 0)) { psConfig->u8PreDivider = u32SourceClock_Hz / i32Nclk2; - - /* if not using baudrate switch then we are done */ - if (!u32DataBaudRate) + /* FD Operation? */ + if ( psCanfd->CCCR & CANFD_CCCR_FDOE_Msk ) { - i32Dtq = 0; - psConfig->u8DataPrescaler = 0; - CANFD_GetSegments(u32NominalBaudRate, u32DataBaudRate, i32Ntq, i32Dtq, psConfig); - return TRUE; - } + /* Exception case: Let u32DataBaudRate is same with u32NominalBaudRate. */ + if (u32DataBaudRate == 0) + u32DataBaudRate = u32NominalBaudRate; - /* if baudrates are the same and the solution for nominal will work for - data, then use the nominal settings for both */ - if ((u32DataBaudRate == u32NominalBaudRate) && psConfig->u16NominalPrescaler <= 0x20) - { - i32Dtq = i32Ntq; - psConfig->u8DataPrescaler = (uint8_t)psConfig->u16NominalPrescaler; - CANFD_GetSegments(u32NominalBaudRate, u32DataBaudRate, i32Ntq, i32Dtq, psConfig); - return TRUE; - } - - /* calculate data settings */ - for (i32Dtq = MAX_TIME_QUANTA; i32Dtq >= MIN_TIME_QUANTA; i32Dtq--) - { - i32Dclk = u32DataBaudRate * i32Dtq; - - for (psConfig->u8DataPrescaler = 0x01; psConfig->u8DataPrescaler <= 0x20; (psConfig->u8DataPrescaler)++) + /* if baudrates are the same and the solution for nominal will work for + data, then use the nominal settings for both */ + if ((u32DataBaudRate == u32NominalBaudRate) && (psConfig->u16NominalPrescaler <= 0x20)) { - i32Dclk2 = i32Dclk * psConfig->u8DataPrescaler; + i32Dtq = i32Ntq; + psConfig->u8DataPrescaler = (uint8_t)psConfig->u16NominalPrescaler; + CANFD_GetSegments(u32NominalBaudRate, u32DataBaudRate, i32Ntq, i32Dtq, psConfig); + return TRUE; + } - if ((float)(u32SourceClock_Hz) / i32Dclk2 == psConfig->u8PreDivider) + /* calculate data settings */ + for (i32Dtq = MAX_TIME_QUANTA; i32Dtq >= MIN_TIME_QUANTA; i32Dtq--) + { + i32Dclk = u32DataBaudRate * i32Dtq; + + for (psConfig->u8DataPrescaler = 0x01; psConfig->u8DataPrescaler <= 0x20; (psConfig->u8DataPrescaler)++) { - CANFD_GetSegments(u32NominalBaudRate, u32DataBaudRate, i32Ntq, i32Dtq, psConfig); - return TRUE; + i32Dclk2 = i32Dclk * psConfig->u8DataPrescaler; + if (u32SourceClock_Hz == ((uint32_t)i32Dclk2 * psConfig->u8PreDivider)) + { + CANFD_GetSegments(u32NominalBaudRate, u32DataBaudRate, i32Ntq, i32Dtq, psConfig); + return TRUE; + } } } } - - if (u32DataBaudRate == 0) + else { + psConfig->u8DataPrescaler = 0; CANFD_GetSegments(u32NominalBaudRate, 0, i32Ntq, 0, psConfig); return TRUE; } @@ -556,7 +571,7 @@ } /* failed to find solution */ - return 0; + return FALSE; } @@ -572,39 +587,38 @@ */ void CANFD_Open(CANFD_T *psCanfd, CANFD_FD_T *psCanfdStr) { + uint32_t u32RegLockLevel = SYS_IsRegLocked(); + + if (u32RegLockLevel) + SYS_UnlockReg(); + if (psCanfd == (CANFD_T *)CANFD0) { - //CLK_EnableModuleClock(CANFD0_MODULE); - CLK->AHBCLK1 |= BIT0; - //SYS_ResetModule(CANFD0_RST); - NVIC_EnableIRQ(CANFD00_IRQn); - NVIC_EnableIRQ(CANFD01_IRQn); + CLK_EnableModuleClock(CANFD0_MODULE); + SYS_ResetModule(CANFD0_RST); } - else if (psCanfd == (CANFD_T *)CANFD1) + else if (psCanfd == (CANFD_T *)CANFD1) { - //CLK_EnableModuleClock(CANFD1_MODULE); - CLK->AHBCLK1 |= BIT1; - //SYS_ResetModule(CANFD1_RST); - NVIC_EnableIRQ(CANFD10_IRQn); - NVIC_EnableIRQ(CANFD11_IRQn); + CLK_EnableModuleClock(CANFD1_MODULE); + SYS_ResetModule(CANFD1_RST); } - else if (psCanfd == (CANFD_T *)CANFD2) + else if (psCanfd == (CANFD_T *)CANFD2) { - //CLK_EnableModuleClock(CANFD2_MODULE); - CLK->AHBCLK1 |= BIT2; - //SYS_ResetModule(CANFD2_RST); - NVIC_EnableIRQ(CANFD20_IRQn); - NVIC_EnableIRQ(CANFD21_IRQn); + CLK_EnableModuleClock(CANFD2_MODULE); + SYS_ResetModule(CANFD2_RST); } - else if (psCanfd == (CANFD_T *)CANFD3) + else if (psCanfd == (CANFD_T *)CANFD3) { - //CLK_EnableModuleClock(CANFD3_MODULE); - CLK->AHBCLK1 |= BIT3; - //SYS_ResetModule(CANFD3_RST); - NVIC_EnableIRQ(CANFD30_IRQn); - NVIC_EnableIRQ(CANFD31_IRQn); + CLK_EnableModuleClock(CANFD3_MODULE); + SYS_ResetModule(CANFD3_RST); } + else + { + if (u32RegLockLevel) + SYS_LockReg(); + return; + } /* configuration change enable */ psCanfd->CCCR |= CANFD_CCCR_CCE_Msk; @@ -627,12 +641,15 @@ psCanfd->RXF1C = 0; /* calculate and apply timing */ - if (CANFD_CalculateTimingValues(psCanfdStr->sBtConfig.sNormBitRate.u32BitRate, psCanfdStr->sBtConfig.sDataBitRate.u32BitRate, + if (CANFD_CalculateTimingValues(psCanfd, psCanfdStr->sBtConfig.sNormBitRate.u32BitRate, psCanfdStr->sBtConfig.sDataBitRate.u32BitRate, SystemCoreClock, &psCanfdStr->sBtConfig.sConfigBitTing)) { CANFD_SetTimingConfig(psCanfd, &psCanfdStr->sBtConfig.sConfigBitTing); } + if (u32RegLockLevel) + SYS_LockReg(); + /* Configures the Standard ID Filter element */ if (psCanfdStr->sElemSize.u32SIDFC != 0) CANFD_ConfigSIDFC(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize); @@ -685,31 +702,19 @@ { if (psCanfd == (CANFD_T *)CANFD0) { - //CLK_DisableModuleClock(CANFD0_MODULE); - CLK->AHBCLK1 |= BIT20; - NVIC_DisableIRQ(CANFD00_IRQn); - NVIC_DisableIRQ(CANFD01_IRQn); + CLK_DisableModuleClock(CANFD0_MODULE); } - else if (psCanfd == (CANFD_T *)CANFD1) + else if (psCanfd == (CANFD_T *)CANFD1) { - //CLK_DisableModuleClock(CANFD1_MODULE); - CLK->AHBCLK1 |= BIT21; - NVIC_DisableIRQ(CANFD10_IRQn); - NVIC_DisableIRQ(CANFD11_IRQn); + CLK_DisableModuleClock(CANFD1_MODULE); } - else if (psCanfd == (CANFD_T *)CANFD2) + else if (psCanfd == (CANFD_T *)CANFD2) { - //CLK_DisableModuleClock(CANFD2_MODULE); - CLK->AHBCLK1 |= BIT22; - NVIC_DisableIRQ(CANFD20_IRQn); - NVIC_DisableIRQ(CANFD21_IRQn); + CLK_DisableModuleClock(CANFD2_MODULE); } - else if (psCanfd == (CANFD_T *)CANFD3) + else if (psCanfd == (CANFD_T *)CANFD3) { - //CLK_DisableModuleClock(CANFD3_MODULE); - CLK->AHBCLK1 |= BIT23; - NVIC_DisableIRQ(CANFD30_IRQn); - NVIC_DisableIRQ(CANFD31_IRQn); + CLK_DisableModuleClock(CANFD3_MODULE); } } @@ -727,7 +732,7 @@ static uint32_t CANFD_GetTxBufferElementAddress(CANFD_T *psCanfd, uint32_t u32Idx) { uint32_t u32Size = 0; - u32Size = (psCanfd->TXESC & CANFD_TXESC_TBDS_Msk) >> CANFD_TXESC_TBDS_Pos; + u32Size = (CANFD_ReadReg(&psCanfd->TXESC) & CANFD_TXESC_TBDS_Msk) >> CANFD_TXESC_TBDS_Pos; if (u32Size < 5U) { @@ -738,7 +743,7 @@ u32Size = u32Size * 4U - 10U; } - return (psCanfd->TXBC & CANFD_TXBC_TBSA_Msk) + u32Idx * u32Size * 4U; + return (CANFD_ReadReg(&psCanfd->TXBC) & CANFD_TXBC_TBSA_Msk) + u32Idx * u32Size * 4U; } @@ -791,24 +796,24 @@ if (u32IntLine0 != 0) { /*Setting the CANFD0_IRQ0 Interrupt*/ - psCanfd->IE |= u32IntLine0; + psCanfd->IE = CANFD_ReadReg(&psCanfd->IE) | u32IntLine0; /* Enable CAN FD specified interrupt */ - psCanfd->ILE |= ((uint32_t)1U << 0); + psCanfd->ILE = CANFD_ReadReg(&psCanfd->ILE) | CANFD_ILE_ENT0_Msk; } if (u32IntLine1 != 0) { /*Setting the CANFD0_IRQ1 Interrupt*/ - psCanfd->ILS |= u32IntLine1; + psCanfd->ILS = CANFD_ReadReg(&psCanfd->ILS) | u32IntLine1; /* Enable CAN FD specified interrupt */ - psCanfd->ILE |= ((uint32_t)1U << 1); + psCanfd->ILE = CANFD_ReadReg(&psCanfd->ILE) | CANFD_ILE_ENT1_Msk; } /*Setting the Tx Buffer Transmission Interrupt Enable*/ - psCanfd->TXBTIE |= u32TXBTIE; + psCanfd->TXBTIE = CANFD_ReadReg(&psCanfd->TXBTIE) | u32TXBTIE; /*Tx Buffer Cancellation Finished Interrupt Enable*/ - psCanfd->TXBCIE |= u32TXBCIE; + psCanfd->TXBCIE = CANFD_ReadReg(&psCanfd->TXBCIE) | u32TXBCIE; } @@ -860,24 +865,24 @@ if (u32IntLine0 != 0) { /*Clear the CANFD0_IRQ0 Interrupt*/ - psCanfd->IE &= ~u32IntLine0; + psCanfd->IE = CANFD_ReadReg(&psCanfd->IE) & ~u32IntLine0; /* Disable CAN FD specified interrupt */ - psCanfd->ILE &= ~((uint32_t)1U << 0); + psCanfd->ILE = CANFD_ReadReg(&psCanfd->ILE) & ~CANFD_ILE_ENT0_Msk; } if (u32IntLine1 != 0) { /*Clear the CANFD0_IRQ1 Interrupt*/ - psCanfd->ILS &= ~u32IntLine1; + psCanfd->ILS = CANFD_ReadReg(&psCanfd->ILS) & ~u32IntLine1; /* Disable CAN FD specified interrupt */ - psCanfd->ILE &= ~((uint32_t)1U << 1); + psCanfd->ILE = CANFD_ReadReg(&psCanfd->ILE) & ~CANFD_ILE_ENT1_Msk; } /*Setting the Tx Buffer Transmission Interrupt Disable*/ - psCanfd->TXBTIE &= ~u32TXBTIE; + psCanfd->TXBTIE = CANFD_ReadReg(&psCanfd->TXBTIE) & ~u32TXBTIE; /*Tx Buffer Cancellation Finished Interrupt Disable*/ - psCanfd->TXBCIE &= ~u32TXBCIE; + psCanfd->TXBCIE = CANFD_ReadReg(&psCanfd->TXBCIE) & ~u32TXBCIE; } @@ -896,7 +901,7 @@ uint32_t CANFD_TransmitTxMsg(CANFD_T *psCanfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg) { uint32_t u32Success = 0; - uint32_t u32TimeOutCount = CANFD_TIMEOUT; + uint32_t u32TimeOutCnt = CANFD_TIMEOUT; /* write the message to the message buffer */ u32Success = CANFD_TransmitDMsg(psCanfd, u32TxBufIdx, psTxMsg); @@ -906,7 +911,7 @@ /* wait for completion */ while (!(psCanfd->TXBRP & (1UL << u32TxBufIdx))) { - if(u32TimeOutCount-- == 0) + if (--u32TimeOutCnt == 0) { u32Success = 0; break; @@ -937,16 +942,15 @@ { CANFD_BUF_T *psTxBuffer; uint32_t u32Idx = 0, u32Success = 1; - uint32_t u32SramBaseAddr; + uint32_t u32TimeOutCnt = CANFD_TIMEOUT; if (u32TxBufIdx >= CANFD_MAX_TX_BUF_ELEMS) return 0; /* transmission is pending in this message buffer */ - if (psCanfd->TXBRP & (1UL << u32TxBufIdx)) return 0; + if (CANFD_ReadReg(&(psCanfd->TXBRP)) & (1UL << u32TxBufIdx)) return 0; - //psTxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR + (psCanfd->TXBC & 0xFFFF) + (u32TxBufIdx * sizeof(CANFD_BUF_T))); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - psTxBuffer = (CANFD_BUF_T *)(u32SramBaseAddr + (psCanfd->TXBC & 0xFFFF) + (u32TxBufIdx * sizeof(CANFD_BUF_T))); + /*Get the TX Buffer Start Address in the RAM*/ + psTxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR(psCanfd) + (CANFD_ReadReg(&psCanfd->TXBC) & 0xFFFF) + (u32TxBufIdx * sizeof(CANFD_BUF_T))); if (psTxMsg->eIdType == eCANFD_XID) { @@ -971,6 +975,11 @@ psTxBuffer->au32Data[u32Idx] = psTxMsg->au32Data[u32Idx]; } + while (CANFD_GET_COMMUNICATION_STATE(psCanfd) != eCANFD_IDLE) + { + if (--u32TimeOutCnt == 0) return 0; + } + psCanfd->TXBAR = (1 << u32TxBufIdx); return u32Success; @@ -1013,11 +1022,10 @@ * * @details Rx FIFO Configuration for RX_FIFO_0 and RX_FIFO_1. */ -void CANFD_InitRxFifo(CANFD_T *psCanfd, uint32_t u32RxFifoNum, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWM, E_CANFD_DATA_FIELD_SIZE eFifoSize) +static void CANFD_InitRxFifo(CANFD_T *psCanfd, uint32_t u32RxFifoNum, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWM, E_CANFD_DATA_FIELD_SIZE eFifoSize) { uint32_t u32Address; uint32_t u32Size; - uint32_t u32SramBaseAddr; /* ignore if index is too high */ if (u32RxFifoNum > CANFD_NUM_RX_FIFOS)return; @@ -1030,71 +1038,68 @@ switch (u32RxFifoNum) { - case 0: - if (psElemSize-> u32RxFifo0) + case 0: + if (psElemSize-> u32RxFifo0) + { + /* set size of Rx FIFO 0, set offset, blocking mode */ + psCanfd->RXF0C = (psRamConfig->u32RXF0C_F0SA) | (psElemSize->u32RxFifo0 << CANFD_RXF0C_F0S_Pos) + | (u32FifoWM << CANFD_RXF0C_F0WM_Pos); + psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_F0DS_Msk)) | (eFifoSize << CANFD_RXESC_F0DS_Pos); + + /*Get the RX FIFO 0 Start Address in the RAM*/ + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32RXF0C_F0SA & CANFD_RXF0C_F0SA_Msk); + u32Size = eFifoSize; + + if (u32Size < 5U) { - /* set size of Rx FIFO 0, set offset, blocking mode */ - psCanfd->RXF0C = (psRamConfig->u32RXF0C_F0SA) | (psElemSize->u32RxFifo0 << CANFD_RXF0C_F0S_Pos) - | (u32FifoWM << CANFD_RXF0C_F0WM_Pos); - psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_F0DS_Msk)) | (eFifoSize << CANFD_RXESC_F0DS_Pos); - /*Get the RX FIFO 0 Start Address in the RAM*/ - //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32RXF0C_F0SA & CANFD_RXF0C_F0SA_Msk); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - u32Address = u32SramBaseAddr + (psRamConfig->u32RXF0C_F0SA & CANFD_RXF0C_F0SA_Msk); - u32Size = eFifoSize; - - if (u32Size < 5U) - { - u32Size += 4U; - } - else - { - u32Size = u32Size * 4U - 10U; - } - - /*Clear the RX FIFO 0 Memory*/ - memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32RxFifo0)); + u32Size += 4U; } else { - psCanfd->RXF0C = 0; + u32Size = u32Size * 4U - 10U; } - break; + /*Clear the RX FIFO 0 Memory*/ + memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32RxFifo0)); + } + else + { + psCanfd->RXF0C = 0; + } - case 1: - if (psElemSize-> u32RxFifo1) + break; + + case 1: + if (psElemSize-> u32RxFifo1) + { + /* set size of Rx FIFO 1, set offset, blocking mode */ + psCanfd->RXF1C = (psRamConfig->u32RXF1C_F1SA) | (psElemSize->u32RxFifo1 << CANFD_RXF1C_F1S_Pos) + | (u32FifoWM << CANFD_RXF1C_F1WM_Pos); + psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_F1DS_Msk)) | (eFifoSize << CANFD_RXESC_F1DS_Pos); + + /*Get the RX FIFO 1 Start Address in the RAM*/ + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32RXF1C_F1SA & CANFD_RXF1C_F1SA_Msk); + + u32Size = eFifoSize; + + if (u32Size < 5U) { - - /* set size of Rx FIFO 1, set offset, blocking mode */ - psCanfd->RXF1C = (psRamConfig->u32RXF1C_F1SA) | (psElemSize->u32RxFifo1 << CANFD_RXF1C_F1S_Pos) - | (u32FifoWM << CANFD_RXF1C_F1WM_Pos); - psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_F1DS_Msk)) | (eFifoSize << CANFD_RXESC_F1DS_Pos); - /*Get the RX FIFO 1 Start Address in the RAM*/ - //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32RXF1C_F1SA & CANFD_RXF1C_F1SA_Msk); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - u32Address = u32SramBaseAddr + (psRamConfig->u32RXF1C_F1SA & CANFD_RXF1C_F1SA_Msk); - - u32Size = eFifoSize; - - if (u32Size < 5U) - { - u32Size += 4U; - } - else - { - u32Size = u32Size * 4U - 10U; - } - - /*Clear the RX FIFO 0 Memory*/ - memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32RxFifo1)); + u32Size += 4U; } else { - psCanfd->RXF1C = 0; + u32Size = u32Size * 4U - 10U; } - break; + /*Clear the RX FIFO 0 Memory*/ + memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32RxFifo1)); + } + else + { + psCanfd->RXF1C = 0; + } + + break; } } @@ -1112,19 +1117,20 @@ * * @details Function configures the data structures used by a dedicated Rx Buffer. */ -void CANFD_InitTxDBuf(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eTxBufSize) +static void CANFD_InitTxDBuf(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eTxBufSize) { uint32_t u32Address; uint32_t u32Size; - uint32_t u32SramBaseAddr; + /*Setting the Tx Buffer Start Address*/ psCanfd->TXBC = ((psElemSize->u32TxBuf & 0x3F) << CANFD_TXBC_NDTB_Pos) | (psRamConfig->u32TXBC_TBSA & CANFD_TXBC_TBSA_Msk); + /*Get the TX Buffer Start Address in the RAM*/ - //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32TXBC_TBSA & CANFD_TXBC_TBSA_Msk); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - u32Address = u32SramBaseAddr + (psRamConfig->u32TXBC_TBSA & CANFD_TXBC_TBSA_Msk); + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32TXBC_TBSA & CANFD_TXBC_TBSA_Msk); + /*Setting the Tx Buffer Data Field Size*/ psCanfd->TXESC = (psCanfd->TXESC & (~CANFD_TXESC_TBDS_Msk)) | (eTxBufSize << CANFD_TXESC_TBDS_Pos); + /*Get the Buffer Data Field Size*/ u32Size = eTxBufSize; @@ -1155,17 +1161,17 @@ * * @details Function configures the data structures used by a dedicated Rx Buffer. */ -void CANFD_InitRxDBuf(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eRxBufSize) +static void CANFD_InitRxDBuf(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eRxBufSize) { uint32_t u32Address; uint32_t u32Size; - uint32_t u32SramBaseAddr; + /*Setting the Rx Buffer Start Address*/ psCanfd->RXBC = (psRamConfig->u32RXBC_RBSA & CANFD_RXBC_RBSA_Msk); + /*Get the RX Buffer Start Address in the RAM*/ - //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32RXBC_RBSA & CANFD_RXBC_RBSA_Msk); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - u32Address = u32SramBaseAddr + (psRamConfig->u32RXBC_RBSA & CANFD_RXBC_RBSA_Msk); + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32RXBC_RBSA & CANFD_RXBC_RBSA_Msk); + /*Setting the Rx Buffer Data Field Size*/ psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_RBDS_Msk)) | (eRxBufSize << CANFD_RXESC_RBDS_Pos); /*Get the Buffer Data Field Size*/ @@ -1196,18 +1202,18 @@ * * @details Function configures the data structures used by a dedicated Rx Buffer. */ -void CANFD_ConfigSIDFC(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize) +static void CANFD_ConfigSIDFC(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize) { uint32_t u32Address; - uint32_t u32SramBaseAddr; + /*Setting the Filter List Standard Start Address and List Size */ psCanfd->SIDFC = ((psElemSize->u32SIDFC & 0xFF) << CANFD_SIDFC_LSS_Pos) | (psRamConfig->u32SIDFC_FLSSA & CANFD_SIDFC_FLSSA_Msk); + /*Get the Filter List Standard Start Address in the RAM*/ - //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32SIDFC_FLSSA & CANFD_SIDFC_FLSSA_Msk); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - u32Address = u32SramBaseAddr + (psRamConfig->u32SIDFC_FLSSA & CANFD_SIDFC_FLSSA_Msk); + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32SIDFC_FLSSA & CANFD_SIDFC_FLSSA_Msk); + /*Clear the Filter List Memory*/ - memset((uint32_t *)(u32Address), 0x00, (psElemSize->u32SIDFC * 4)); + memset((uint32_t *)(u32Address), 0x00, (psElemSize->u32SIDFC * sizeof(CANFD_STD_FILTER_T))); } @@ -1222,18 +1228,18 @@ * * @details Configures the register XIDFC for the 29-bit Extended Message ID Filter elements. */ -void CANFD_ConfigXIDFC(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize) +static void CANFD_ConfigXIDFC(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize) { uint32_t u32Address; - uint32_t u32SramBaseAddr; + /*Setting the Filter List Extended Start Address and List Size */ psCanfd->XIDFC = ((psElemSize->u32XIDFC & 0xFF) << CANFD_XIDFC_LSE_Pos) | (psRamConfig->u32XIDFC_FLESA & CANFD_XIDFC_FLESA_Msk); + /*Get the Filter List Standard Start Address in the RAM*/ - //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32XIDFC_FLESA & CANFD_XIDFC_FLESA_Msk); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - u32Address = u32SramBaseAddr + (psRamConfig->u32XIDFC_FLESA & CANFD_XIDFC_FLESA_Msk); + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32XIDFC_FLESA & CANFD_XIDFC_FLESA_Msk); + /*Clear the Filter List Memory*/ - memset((uint32_t *)(u32Address), 0x00, (psElemSize->u32XIDFC * 8)); + memset((uint32_t *)(u32Address), 0x00, (psElemSize->u32XIDFC * sizeof(CANFD_EXT_FILTER_T))); } @@ -1251,15 +1257,13 @@ void CANFD_SetSIDFltr(CANFD_T *psCanfd, uint32_t u32FltrIdx, uint32_t u32Filter) { CANFD_STD_FILTER_T *psFilter; - uint32_t u32SramBaseAddr; /* ignore if index is too high */ if (u32FltrIdx >= CANFD_MAX_11_BIT_FTR_ELEMS) return; /*Get the Filter List Configuration Address in the RAM*/ - //psFilter = (CANFD_STD_FILTER_T *)(CANFD_SRAM_BASE_ADDR + (psCanfd->SIDFC & CANFD_SIDFC_FLSSA_Msk) + (u32FltrIdx * sizeof(CANFD_STD_FILTER_T))); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - psFilter = (CANFD_STD_FILTER_T *)(u32SramBaseAddr + (psCanfd->SIDFC & CANFD_SIDFC_FLSSA_Msk) + (u32FltrIdx * sizeof(CANFD_STD_FILTER_T))); + psFilter = (CANFD_STD_FILTER_T *)(CANFD_SRAM_BASE_ADDR(psCanfd) + (psCanfd->SIDFC & CANFD_SIDFC_FLSSA_Msk) + (u32FltrIdx * sizeof(CANFD_STD_FILTER_T))); + /*Wirted the Standard ID filter element to RAM */ psFilter->VALUE = u32Filter; } @@ -1281,15 +1285,13 @@ void CANFD_SetXIDFltr(CANFD_T *psCanfd, uint32_t u32FltrIdx, uint32_t u32FilterLow, uint32_t u32FilterHigh) { CANFD_EXT_FILTER_T *psFilter; - uint32_t u32SramBaseAddr; /* ignore if index is too high */ if (u32FltrIdx >= CANFD_MAX_29_BIT_FTR_ELEMS) return; /*Get the Filter List Configuration Address on RAM*/ - //psFilter = (CANFD_EXT_FILTER_T *)(CANFD_SRAM_BASE_ADDR + (psCanfd->XIDFC & CANFD_XIDFC_FLESA_Msk) + (u32FltrIdx * sizeof(CANFD_EXT_FILTER_T))); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - psFilter = (CANFD_EXT_FILTER_T *)(u32SramBaseAddr + (psCanfd->XIDFC & CANFD_XIDFC_FLESA_Msk) + (u32FltrIdx * sizeof(CANFD_EXT_FILTER_T))); + psFilter = (CANFD_EXT_FILTER_T *)(CANFD_SRAM_BASE_ADDR(psCanfd) + (psCanfd->XIDFC & CANFD_XIDFC_FLESA_Msk) + (u32FltrIdx * sizeof(CANFD_EXT_FILTER_T))); + /*Wirted the Extended ID filter element to RAM */ psFilter->LOWVALUE = u32FilterLow; psFilter->HIGHVALUE = u32FilterHigh; @@ -1315,31 +1317,28 @@ CANFD_BUF_T *psRxBuffer; uint32_t u32Success = 0; uint32_t newData = 0; - uint32_t u32SramBaseAddr; if (u8MbIdx < CANFD_MAX_RX_BUF_ELEMS) { if (u8MbIdx < 32) - newData = (psCanfd->NDAT1 >> u8MbIdx) & 1; + newData = (CANFD_ReadReg(&psCanfd->NDAT1) >> u8MbIdx) & 1; else - newData = (psCanfd->NDAT2 >> (u8MbIdx - 32)) & 1; + newData = (CANFD_ReadReg(&psCanfd->NDAT2) >> (u8MbIdx - 32)) & 1; /* new message is waiting to be read */ if (newData) { /* get memory location of rx buffer */ - //psRxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR + (psCanfd->RXBC & 0xFFFF) + (u8MbIdx * sizeof(CANFD_BUF_T))); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - psRxBuffer = (CANFD_BUF_T *)(u32SramBaseAddr + (psCanfd->RXBC & 0xFFFF) + (u8MbIdx * sizeof(CANFD_BUF_T))); + psRxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR(psCanfd) + (CANFD_ReadReg(&psCanfd->RXBC) & 0xFFFF) + (u8MbIdx * sizeof(CANFD_BUF_T))); /* read the message */ CANFD_CopyDBufToMsgBuf(psRxBuffer, psMsgBuf); /* clear 'new data' flag */ if (u8MbIdx < 32) - psCanfd->NDAT1 |= (1UL << u8MbIdx); + psCanfd->NDAT1 = CANFD_ReadReg(&psCanfd->NDAT1) | (1UL << u8MbIdx); else - psCanfd->NDAT2 |= (1UL << (u8MbIdx - 32)); + psCanfd->NDAT2 = CANFD_ReadReg(&psCanfd->NDAT2) | (1UL << (u8MbIdx - 32)); u32Success = 1; } @@ -1370,7 +1369,6 @@ __I uint32_t *pRXFS; __IO uint32_t *pRXFC, *pRXFA; uint8_t msgLostBit; - uint32_t u32SramBaseAddr; /* check for valid FIFO number */ if (u8FifoIdx < CANFD_NUM_RX_FIFOS) @@ -1391,19 +1389,18 @@ } /* if FIFO is not empty */ - if ((*pRXFS & 0x7F) > 0) + if ((CANFD_ReadReg(pRXFS) & 0x7F) > 0) { - GetIndex = (uint8_t)((*pRXFS >> 8) & 0x3F); - //pRxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR + (*pRXFC & 0xFFFF) + (GetIndex * sizeof(CANFD_BUF_T))); - u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); - pRxBuffer = (CANFD_BUF_T *)(u32SramBaseAddr + (*pRXFC & 0xFFFF) + (GetIndex * sizeof(CANFD_BUF_T))); + GetIndex = (uint8_t)((CANFD_ReadReg(pRXFS) >> 8) & 0x3F); + pRxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR(psCanfd) + (CANFD_ReadReg(pRXFC) & 0xFFFF) + (GetIndex * sizeof(CANFD_BUF_T))); CANFD_CopyRxFifoToMsgBuf(pRxBuffer, psMsgBuf); + /* we got the message */ *pRXFA = GetIndex; /* check for overflow */ - if (*pRXFS & CANFD_RXFS_RFL) + if (CANFD_ReadReg(pRXFS) & CANFD_RXFS_RFL) { /* clear overflow flag */ psCanfd->IR = (1UL << msgLostBit); @@ -1492,9 +1489,9 @@ uint32_t u32WaterLevel = 0; if (u32RxFifoNum == 0) - u32WaterLevel = ((psCanfd->RXF0C & CANFD_RXF0C_F0WM_Msk) >> CANFD_RXF0C_F0WM_Pos); + u32WaterLevel = ((CANFD_ReadReg(&psCanfd->RXF0C) & CANFD_RXF0C_F0WM_Msk) >> CANFD_RXF0C_F0WM_Pos); else - u32WaterLevel = ((psCanfd->RXF1C & CANFD_RXF1C_F1WM_Msk) >> CANFD_RXF1C_F1WM_Pos); + u32WaterLevel = ((CANFD_ReadReg(&psCanfd->RXF1C) & CANFD_RXF1C_F1WM_Msk) >> CANFD_RXF1C_F1WM_Pos); return u32WaterLevel; } @@ -1529,7 +1526,7 @@ */ void CANFD_TxBufCancelReq(CANFD_T *psCanfd, uint32_t u32TxBufIdx) { - psCanfd->TXBCR |= (0x1ul << u32TxBufIdx); + psCanfd->TXBCR = CANFD_ReadReg(&psCanfd->TXBCR) | (0x1ul << u32TxBufIdx); } @@ -1547,7 +1544,7 @@ uint32_t CANFD_IsTxBufCancelFin(CANFD_T *psCanfd, uint32_t u32TxBufIdx) { /* wait for completion */ - return ((psCanfd->TXBCR & (0x1ul << u32TxBufIdx)) >> u32TxBufIdx); + return ((CANFD_ReadReg(&psCanfd->TXBCR) & (0x1ul << u32TxBufIdx)) >> u32TxBufIdx); } @@ -1564,7 +1561,7 @@ */ uint32_t CANFD_IsTxBufTransmitOccur(CANFD_T *psCanfd, uint32_t u32TxBufIdx) { - return ((psCanfd->TXBTO & (0x1ul << u32TxBufIdx)) >> u32TxBufIdx); + return ((CANFD_ReadReg(&psCanfd->TXBTO) & (0x1ul << u32TxBufIdx)) >> u32TxBufIdx); } @@ -1580,7 +1577,7 @@ * * @details Init Tx event fifo. */ -void CANFD_InitTxEvntFifo(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWaterLvl) +static void CANFD_InitTxEvntFifo(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWaterLvl) { /* Set TX Event FIFO element size,watermark,start address. */ psCanfd->TXEFC = (u32FifoWaterLvl << CANFD_TXEFC_EFWN_Pos) | (psElemSize->u32TxEventFifo << CANFD_TXEFC_EFS_Pos) @@ -1599,7 +1596,7 @@ */ uint32_t CANFD_GetTxEvntFifoWaterLvl(CANFD_T *psCanfd) { - return ((psCanfd->TXEFC & CANFD_TXEFC_EFWN_Msk) >> CANFD_TXEFC_EFWN_Pos); + return ((CANFD_ReadReg(&psCanfd->TXEFC) & CANFD_TXEFC_EFWN_Msk) >> CANFD_TXEFC_EFWN_Pos); } @@ -1707,7 +1704,7 @@ */ uint32_t CANFD_GetStatusFlag(CANFD_T *psCanfd, uint32_t u32IntTypeFlag) { - return (psCanfd->IR & u32IntTypeFlag); + return (CANFD_ReadReg(&psCanfd->IR) & u32IntTypeFlag); } @@ -1752,7 +1749,7 @@ void CANFD_ClearStatusFlag(CANFD_T *psCanfd, uint32_t u32InterruptFlag) { /* Write 1 to clear status flag. */ - psCanfd->IR |= u32InterruptFlag; + psCanfd->IR = CANFD_ReadReg(&psCanfd->IR) | u32InterruptFlag; } @@ -1772,12 +1769,12 @@ { if (pu8TxErrBuf) { - *pu8TxErrBuf = (uint8_t)((psCanfd->ECR >> CANFD_ECR_TEC_Pos) & CANFD_ECR_TEC_Msk); + *pu8TxErrBuf = (uint8_t)((CANFD_ReadReg(&psCanfd->ECR) >> CANFD_ECR_TEC_Pos) & CANFD_ECR_TEC_Msk); } if (pu8RxErrBuf) { - *pu8RxErrBuf = (uint8_t)((psCanfd->ECR >> CANFD_ECR_REC_Pos) & CANFD_ECR_REC_Msk); + *pu8RxErrBuf = (uint8_t)((CANFD_ReadReg(&psCanfd->ECR) >> CANFD_ECR_REC_Pos) & CANFD_ECR_REC_Msk); } } @@ -1788,47 +1785,38 @@ * @param[in] psCanfd The pointer of the specified CAN FD module. * @param[in] u8Enable TxErrBuf Buffer to store Tx Error Counter value. * - * @return None. + * @retval CANFD_OK CANFD operation OK. + * @retval CANFD_ERR_TIMEOUT CANFD operation abort due to timeout error. * * @details This function gets the CAN FD Bus Error Counter value for both Tx and Rx direction. * These values may be needed in the upper layer error handling. - * - * @note This function sets g_CANFD_i32ErrCode to CANFD_TIMEOUT_ERR if waiting CANFD time-out. */ -void CANFD_RunToNormal(CANFD_T *psCanfd, uint8_t u8Enable) +int32_t CANFD_RunToNormal(CANFD_T *psCanfd, uint8_t u8Enable) { - uint32_t u32TimeOutCount = CANFD_TIMEOUT; - - g_CANFD_i32ErrCode = 0; + uint32_t u32TimeOutCnt = CANFD_TIMEOUT; if (u8Enable) { /* start operation */ - psCanfd->CCCR &= ~(CANFD_CCCR_CCE_Msk | CANFD_CCCR_INIT_Msk); + psCanfd->CCCR = CANFD_ReadReg(&psCanfd->CCCR) & ~(CANFD_CCCR_CCE_Msk | CANFD_CCCR_INIT_Msk); while (psCanfd->CCCR & CANFD_CCCR_INIT_Msk) { - if(u32TimeOutCount-- == 0) - { - g_CANFD_i32ErrCode = CANFD_TIMEOUT_ERR; - break; - } + if (--u32TimeOutCnt == 0) return CANFD_ERR_TIMEOUT; } } else { /* init mode */ - psCanfd->CCCR |= CANFD_CCCR_INIT_Msk; + psCanfd->CCCR = CANFD_ReadReg(&psCanfd->CCCR) | CANFD_CCCR_INIT_Msk; while (!(psCanfd->CCCR & CANFD_CCCR_INIT_Msk)) { - if(u32TimeOutCount-- == 0) - { - g_CANFD_i32ErrCode = CANFD_TIMEOUT_ERR; - break; - } + if (--u32TimeOutCnt == 0) return CANFD_ERR_TIMEOUT; } } + + return CANFD_OK; } diff --git a/targets/TARGET_NUVOTON/TARGET_M460/objects.h b/targets/TARGET_NUVOTON/TARGET_M460/objects.h index 9c747f7..f62d34b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M460/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M460/objects.h @@ -125,7 +125,6 @@ CANName can; PinName pin_rd; PinName pin_td; - int index; }; struct trng_s { diff --git a/targets/TARGET_NUVOTON/TARGET_M480/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M480/analogin_api.c index 6212da0..9510d4d 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/analogin_api.c @@ -25,6 +25,7 @@ #include "PeripheralPins.h" #include "gpio_api.h" #include "nu_modutil.h" +#include "hal/PinNameAliases.h" static uint32_t eadc_modinit_mask = 0; @@ -66,6 +67,18 @@ {ADC_1_15, EADC1_MODULE, 0, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, }; +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) +/* Structure for extending sampling time on per-pin basis */ +struct nu_eadc_extsmpt { + PinName pin; + uint32_t value; +}; + +static struct nu_eadc_extsmpt eadc_extsmpt_arr[] = { + MBED_CONF_TARGET_EADC_EXTSMPT_LIST +}; +#endif + void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); @@ -102,6 +115,18 @@ // Configure the sample module Nmod for analog input channel Nch and software trigger source EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn); +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) + // Extend sampling time in EADC clocks on per-pin basis + struct nu_eadc_extsmpt *eadc_extsmpt_pos = eadc_extsmpt_arr; + struct nu_eadc_extsmpt *eadc_extsmpt_end = eadc_extsmpt_arr + sizeof (eadc_extsmpt_arr) / sizeof (eadc_extsmpt_arr[0]); + for (; eadc_extsmpt_pos != eadc_extsmpt_end; eadc_extsmpt_pos ++) { + if (eadc_extsmpt_pos->pin == pin) { + EADC_SetExtendSampleTime(eadc_base, chn, eadc_extsmpt_pos->value); + break; + } + } +#endif + eadc_modinit_mask |= 1 << chn; } diff --git a/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/inc/m480_ccap.h b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/inc/m480_ccap.h index 161c6f8..94fa6a3 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/inc/m480_ccap.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/inc/m480_ccap.h @@ -83,7 +83,6 @@ #define CCAP_INT_MDIEN_ENABLE (0x1ul<adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); @@ -82,6 +95,18 @@ adc_base->CHEN |= 1 << chn; } +#if defined(MBED_CONF_TARGET_ADC_SMPLCNT_LIST) + // Extend sampling time in EADC clocks on per-pin basis + struct nu_eadc_smplcnt *eadc_extsmpt_pos = eadc_smplcnt_arr; + struct nu_eadc_smplcnt *eadc_extsmpt_end = eadc_smplcnt_arr + sizeof (eadc_smplcnt_arr) / sizeof (eadc_smplcnt_arr[0]); + for (; eadc_extsmpt_pos != eadc_extsmpt_end; eadc_extsmpt_pos ++) { + if (eadc_extsmpt_pos->pin == pin) { + ADC_SetExtraSampleTime(adc_base, chn, eadc_extsmpt_pos->value); + break; + } + } +#endif + adc_modinit_mask |= 1 << chn; } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c index fc99b14..88bfd03 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c @@ -22,6 +22,7 @@ #include "pinmap.h" #include "PeripheralPins.h" #include "nu_modutil.h" +#include "hal/PinNameAliases.h" static uint32_t eadc_modinit_mask = 0; @@ -45,6 +46,18 @@ {ADC_1_7, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL} }; +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) +/* Structure for extending sampling time on per-pin basis */ +struct nu_eadc_extsmpt { + PinName pin; + uint32_t value; +}; + +static struct nu_eadc_extsmpt eadc_extsmpt_arr[] = { + MBED_CONF_TARGET_EADC_EXTSMPT_LIST +}; +#endif + void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); @@ -82,6 +95,18 @@ // Configure the sample module Nmod for analog input channel Nch and software trigger source EADC_ConfigSampleModule(eadc_base, smp_mod, EADC_SOFTWARE_TRIGGER, smp_chn); +#if defined(MBED_CONF_TARGET_EADC_EXTSMPT_LIST) + // Extend sampling time in EADC clocks on per-pin basis + struct nu_eadc_extsmpt *eadc_extsmpt_pos = eadc_extsmpt_arr; + struct nu_eadc_extsmpt *eadc_extsmpt_end = eadc_extsmpt_arr + sizeof (eadc_extsmpt_arr) / sizeof (eadc_extsmpt_arr[0]); + for (; eadc_extsmpt_pos != eadc_extsmpt_end; eadc_extsmpt_pos ++) { + if (eadc_extsmpt_pos->pin == pin) { + EADC_SetExtendSampleTime(eadc_base, smp_mod, eadc_extsmpt_pos->value); + break; + } + } +#endif + eadc_modinit_mask |= 1 << smp_mod; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/TOOLCHAIN_GCC_ARM/MIMXRT1170xxxxx.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/TOOLCHAIN_GCC_ARM/MIMXRT1170xxxxx.ld index 9b66db8..001599a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/TOOLCHAIN_GCC_ARM/MIMXRT1170xxxxx.ld +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/TOOLCHAIN_GCC_ARM/MIMXRT1170xxxxx.ld @@ -78,7 +78,7 @@ . = ALIGN(8); } > m_flash_config - ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config); + ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config); .ivt : AT(ivt_begin) { diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_ARM/startup_stm32f103xe.S b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_ARM/startup_stm32f103xe.S new file mode 100644 index 0000000..e66b712 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_ARM/startup_stm32f103xe.S @@ -0,0 +1,312 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f103xe.s +;* Author : MCD Application Team +;* Description : STM32F103xE Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_ARM/stm32f103xd.sct b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_ARM/stm32f103xd.sct new file mode 100644 index 0000000..35deee6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_ARM/stm32f103xd.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m3 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +# if defined(MBED_BOOT_STACK_SIZE) +# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +# else +# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +# endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_IAR/startup_stm32f103xe.S b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_IAR/startup_stm32f103xe.S new file mode 100644 index 0000000..1cca3db --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_IAR/startup_stm32f103xe.S @@ -0,0 +1,498 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f103xe.s +;* Author : MCD Application Team +;* Description : STM32F103xE Performance Line Devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + + END + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_IAR/stm32f103xd.icf b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_IAR/stm32f103xd.icf new file mode 100644 index 0000000..2039044 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xD/TOOLCHAIN_IAR/stm32f103xd.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 76; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x4000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_ARM/startup_stm32f103xg.S b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_ARM/startup_stm32f103xg.S new file mode 100644 index 0000000..7f65373 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_ARM/startup_stm32f103xg.S @@ -0,0 +1,312 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f103xg.s +;* Author : MCD Application Team +;* Description : STM32F103xG Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_ARM/stm32f103xg.sct b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_ARM/stm32f103xg.sct new file mode 100644 index 0000000..a3f155a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_ARM/stm32f103xg.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m3 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_IAR/startup_stm32f103xg.S b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_IAR/startup_stm32f103xg.S new file mode 100644 index 0000000..3a16b93 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_IAR/startup_stm32f103xg.S @@ -0,0 +1,495 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f103xg.s +;* Author : MCD Application Team +;* Description : STM32F103xG Performances Line Devices vector table for EWARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR address, +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + + END + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_IAR/stm32f103xg.icf b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_IAR/stm32f103xg.icf new file mode 100644 index 0000000..2039044 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103xG/TOOLCHAIN_IAR/stm32f103xg.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 76; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x4000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32F1/pin_device.h b/targets/TARGET_STM/TARGET_STM32F1/pin_device.h index 660403e..793badc 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32F1/pin_device.h @@ -109,6 +109,31 @@ case AFIO_REMAP_TIM4_ENABLE: __HAL_AFIO_REMAP_TIM4_ENABLE(); break; +#if defined(AFIO_MAPR2_TIM9_REMAP) + case AFIO_REMAP_TIM9_ENABLE: + __HAL_AFIO_REMAP_TIM9_ENABLE(); + break; +#endif +#if defined(AFIO_MAPR2_TIM10_REMAP) + case AFIO_REMAP_TIM10_ENABLE: + __HAL_AFIO_REMAP_TIM10_ENABLE(); + break; +#endif +#if defined(AFIO_MAPR2_TIM11_REMAP) + case AFIO_REMAP_TIM11_ENABLE: + __HAL_AFIO_REMAP_TIM11_ENABLE(); + break; +#endif +#if defined(AFIO_MAPR2_TIM13_REMAP) + case AFIO_REMAP_TIM13_ENABLE: + __HAL_AFIO_REMAP_TIM13_ENABLE(); + break; +#endif +#if defined(AFIO_MAPR2_TIM14_REMAP) + case AFIO_REMAP_TIM14_ENABLE: + __HAL_AFIO_REMAP_TIM14_ENABLE(); + break; +#endif default: break; } diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TOOLCHAIN_GCC_ARM/STM32F303XC.ld b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TOOLCHAIN_GCC_ARM/STM32F303XC.ld index e8e6b52..afc9639 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TOOLCHAIN_GCC_ARM/STM32F303XC.ld +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TOOLCHAIN_GCC_ARM/STM32F303XC.ld @@ -114,7 +114,7 @@ __etext = .; _sidata = .; - + .data : AT (__etext) { __data_start__ = .; @@ -162,7 +162,7 @@ . = ALIGN(32); __uninitialized_end = .; } > RAM - + .bss : { . = ALIGN(8); @@ -185,14 +185,13 @@ } > RAM .ram_ccm_section (NOLOAD): - { + { __ram_ccm_start__ = .; - *(.RAM_CCM_section) + *(.RAM_CCM_section) . = ORIGIN(RAM_CCM) + LENGTH(RAM_CCM); __ram_ccm_end__ = .; } >RAM_CCM - /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c index dd367f3..dcbffe1 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c @@ -88,7 +88,7 @@ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 }; -#if HSE_VALUE != 24000000 +#if HSE_VALUE != 4000000 && HSE_VALUE != 8000000 && HSE_VALUE != 16000000 && HSE_VALUE != 24000000 #error Unsupported externall clock value, check HSE_VALUE define #endif @@ -100,7 +100,16 @@ RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; +#if HSE_VALUE == 4000000 + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; +#elif HSE_VALUE == 8000000 + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; +#elif HSE_VALUE == 16000000 + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; +#elif HSE_VALUE == 24000000 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV6; +#endif + //! 170MHz as a core frequency for FDCAN is not suitable for many frequencies, //! as it provides low accuracy. When no FDCAN is used, the full capacity of 170 MHz //! should be standard. diff --git a/targets/TARGET_STM/TARGET_STM32G4/objects.h b/targets/TARGET_STM/TARGET_STM32G4/objects.h index 183cf54..69db11a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/objects.h +++ b/targets/TARGET_STM/TARGET_STM32G4/objects.h @@ -136,6 +136,8 @@ //#include "common_objects.h" #include "gpio_object.h" +#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 7 || (width) == 8 || (width) == 16 || (width) == 32) + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt index 9b26267..6c4d965 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt @@ -21,6 +21,7 @@ target_sources(mbed-stm32h723xg INTERFACE ${STARTUP_FILE} + system_clock.c ) mbed_set_linker_script(mbed-stm32h723xg ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/CMakeLists.txt index d27c221..3b3b20b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/CMakeLists.txt @@ -6,7 +6,6 @@ target_sources(mbed-nucleo-h723zg INTERFACE PeripheralPins.c - system_clock.c ) target_include_directories(mbed-nucleo-h723zg diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h index 6559955..161c860 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h @@ -40,11 +40,11 @@ #endif #if !defined(MBED_RAM1_START) -#define MBED_RAM_1START 0x24000000 +#define MBED_RAM1_START 0x24000000 #endif #if !defined(MBED_RAM1_SIZE) -#define MBED1_RAM_SIZE 0x50000 // 320 KB +#define MBED_RAM1_SIZE 0x50000 // 320 KB #endif #define NVIC_NUM_VECTORS 180 diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_NUCLEO_H745ZI_Q/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_NUCLEO_H745ZI_Q/CMakeLists.txt new file mode 100644 index 0000000..3e8bb19 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_NUCLEO_H745ZI_Q/CMakeLists.txt @@ -0,0 +1,46 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-nucleo-h745zi-q INTERFACE) + +target_sources(mbed-nucleo-h745zi-q + INTERFACE + PeripheralPins.c +) + +target_include_directories(mbed-nucleo-h745i + INTERFACE + . +) + +target_link_libraries(mbed-nucleo-h745zi-q INTERFACE mbed-stm32h745xi-cm7) + + +add_library(mbed-nucleo-h745i-cm7 INTERFACE) + +target_sources(mbed-nucleo-h745i-cm7 + INTERFACE + PeripheralPins.c +) + +target_include_directories(mbed-nucleo-h745zi-cm7 + INTERFACE + . +) + +target_link_libraries(mbed-nucleo-h745zi-cm7 INTERFACE mbed-stm32h745xi-cm7) + + +add_library(mbed-nucleo-h745zi-cm4 INTERFACE) + +target_sources(mbed-nucleo-h745zi-cm4 + INTERFACE + PeripheralPins.c +) + +target_include_directories(mbed-nucleo-h745i-cm4 + INTERFACE + . +) + +target_link_libraries(mbed-nucleo-h745zi-cm4 INTERFACE mbed-stm32h745xi-cm4) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_NUCLEO_H745ZI_Q/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_NUCLEO_H745ZI_Q/PeripheralPins.c new file mode 100644 index 0000000..deed9e7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_NUCLEO_H745ZI_Q/PeripheralPins.c @@ -0,0 +1,483 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2023 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H745ZITx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 // Connected to ETH_REF_CLK + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 // Connected to ETH_MDIO + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 // Connected to ETH_MDIO + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 // Connected to ETH_CRS_DV + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 // Connected to ETH_CRS_DV + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 // Connected to LD1 [Green Led] + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 // Connected to LD1 [Green Led] + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 // Connected to ETH_MDC + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 // Connected to ETH_MDC + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 // Connected to ETH_MDC + {PC_2C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 + {PC_3C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 // Connected to ETH_RXD0 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 // Connected to ETH_RXD0 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 // Connected to ETH_RXD1 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 // Connected to ETH_RXD1 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 + {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {NC, NC, 0} +}; + +// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { +// {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, +// {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, +// {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to USB_OTG_FS_SOF + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +// (update us_ticker_data.h file if another timer is chosen) +// TIM2 cannot be used because already used by the us_ticker (DUAL_CORE) +MBED_WEAK const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ETH_REF_CLK +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ETH_REF_CLK + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ETH_REF_CLK +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ETH_MDIO +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ETH_MDIO + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ETH_MDIO +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ETH_CRS_DV + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to ETH_CRS_DV + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ETH_CRS_DV + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to ETH_CRS_DV + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to USB_OTG_FS_SOF + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_OTG_FS_VBUS + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_OTG_FS_DM +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD1 [Green Led] + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LD1 [Green Led] + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD1 [Green Led] + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 +// {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ETH_TXD1 + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD3 [Red Led] + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD3 [Red Led] + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LD3 [Red Led] + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_MDIO + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_VBUS + {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to USB_OTG_FS_VBUS + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to USB_OTG_FS_DP + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ETH_TXD1 + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to LD3 [Red Led] + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to LD2 [Yellow Led] + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ETH_REF_CLK + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, // Connected to USB_OTG_FS_SOF + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to USB_OTG_FS_DM + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_REF_CLK + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DP + {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to USB_OTG_FS_DP + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red Led] + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD3 [Red Led] + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DM + {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to USB_OTG_FS_DM + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD1 [Green Led] + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ETH_TXD1 + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to ETH_TXD0 + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ETH_CRS_DV + {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // Connected to ETH_CRS_DV + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ETH_MDC + {PC_3C, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red Led] + {PC_2C, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_OTG_FS_VBUS + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_OTG_FS_DP + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ETH_TXD1 + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ETH_TX_EN + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to ETH_TXD0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_OTG_FS_DM + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to USB_OTG_FS_DM + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to USB_OTG_FS_DP + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to ETH_TXD1 + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to ETH_REF_CLK + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS + {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_FS[] = { +// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF // Connected to USB_OTG_FS_SOF + {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS // Connected to USB_OTG_FS_VBUS + {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID + {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM // Connected to USB_OTG_FS_DM + {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP // Connected to USB_OTG_FS_DP + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_HS[] = { +#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) +// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS // Connected to ETH_TXD1 + {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM // Connected to LD3 [Red Led] + {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP +#else /* MBED_CONF_TARGET_USB_SPEED */ + {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1 // Connected to LD1 [Green Led] + {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 // Connected to ETH_TXD1 + {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP + {PC_2C, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR + {PC_3C, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT +#endif /* MBED_CONF_TARGET_USB_SPEED */ + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_NUCLEO_H745ZI_Q/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_NUCLEO_H745ZI_Q/PinNames.h new file mode 100644 index 0000000..50c7eef --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_NUCLEO_H745ZI_Q/PinNames.h @@ -0,0 +1,335 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2023 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H745ZITx.xml + */ + +/* MBED TARGET LIST: NUCLEO_H745ZI_Q */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DUAL_PAD 0xF00 + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW + PC_2 = 0x22, + PC_2C = PC_2 | DUAL_PAD, // dual pad + PC_3 = 0x23, + PC_3C = PC_3 | DUAL_PAD, // dual pad + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_14 = 0x5E, + PF_15 = 0x5F, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PH_0 = 0x70, + PH_1 = 0x71, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino Uno (Rev3) pins + ARDUINO_UNO_A0 = PA_3, + ARDUINO_UNO_A1 = PC_0, + ARDUINO_UNO_A2 = PC_3C, + ARDUINO_UNO_A3 = PB_1, + ARDUINO_UNO_A4 = PC_2C, + ARDUINO_UNO_A5 = PF_11, + + ARDUINO_UNO_D0 = PB_7, + ARDUINO_UNO_D1 = PB_6, + ARDUINO_UNO_D2 = PG_14, + ARDUINO_UNO_D3 = PE_13, + ARDUINO_UNO_D4 = PE_14, + ARDUINO_UNO_D5 = PE_11, + ARDUINO_UNO_D6 = PA_8, + ARDUINO_UNO_D7 = PG_12, + ARDUINO_UNO_D8 = PG_9, + ARDUINO_UNO_D9 = PD_15, + ARDUINO_UNO_D10 = PD_14, + ARDUINO_UNO_D11 = PB_5, + ARDUINO_UNO_D12 = PA_6, + ARDUINO_UNO_D13 = PA_5, + ARDUINO_UNO_D14 = PB_9, + ARDUINO_UNO_D15 = PB_8, +#endif + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PD_9, +#endif + + /**** USB FS pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + + /**** USB HS pins ****/ + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2C, + USB_OTG_HS_ULPI_NXT = PC_3C, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, + + /**** ETHERNET pins ****/ + ETH_COL = PA_3, + ETH_CRS = PA_0, + ETH_CRS_DV = PA_7, + ETH_MDC = PC_1, + ETH_MDIO = PA_2, + ETH_PPS_OUT = PG_8, + ETH_PPS_OUT_ALT0 = PB_5, + ETH_REF_CLK = PA_1, + ETH_RXD0 = PC_4, + ETH_RXD1 = PC_5, + ETH_RXD2 = PB_0, + ETH_RXD3 = PB_1, + ETH_RX_CLK = PA_1, + ETH_RX_DV = PA_7, + ETH_RX_ER = PB_10, + ETH_TXD0 = PB_12, + ETH_TXD0_ALT0 = PG_13, + ETH_TXD1 = PB_13, + ETH_TXD1_ALT0 = PG_12, + ETH_TXD1_ALT1 = PG_14, + ETH_TXD2 = PC_2C, + ETH_TXD3 = PE_2, + ETH_TXD3_ALT0 = PB_8, + ETH_TX_CLK = PC_3C, + ETH_TX_EN = PB_11, + ETH_TX_EN_ALT0 = PG_11, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + DEBUG_JTCK_SWCLK = PA_14, + DEBUG_JTDI = PA_15, + DEBUG_JTDO_SWO = PB_3, + DEBUG_JTMS_SWDIO = PA_13, + DEBUG_JTRST = PB_4, + DEBUG_TRACECLK = PE_2, + DEBUG_TRACED0 = PE_3, + DEBUG_TRACED0_ALT0 = PC_1, + DEBUG_TRACED0_ALT1 = PG_13, + DEBUG_TRACED1 = PE_4, + DEBUG_TRACED1_ALT0 = PC_8, + DEBUG_TRACED1_ALT1 = PG_14, + DEBUG_TRACED2 = PE_5, + DEBUG_TRACED2_ALT0 = PD_2, + DEBUG_TRACED3 = PE_6, + DEBUG_TRACED3_ALT0 = PC_12, + DEBUG_TRGIO = PC_7, + PWR_CSLEEP = PC_3C, + PWR_CSTOP = PC_2C, + PWR_NDSTOP2 = PA_5, + PWR_PVD_IN = PB_7, + SYS_PWR_WKUP1 = PA_0, + SYS_PWR_WKUP2 = PA_2, + SYS_PWR_WKUP4 = PC_13, + SYS_PWR_WKUP6 = PC_1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 PB_0 // LD1 [Green Led] +#define LED2 PE_1 // LD2 [Yellow Led] +#define LED3 PB_14 // LD3 [Red Led] +#define BUTTON1 PC_13 // B1 [Blue PushButton] + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/system_clock.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/system_clock.c index 4644941..2803161 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/system_clock.c @@ -106,8 +106,9 @@ #if HSE_VALUE==25000000 RCC_OscInitStruct.PLL.PLLM = 5; // 5 MHz RCC_OscInitStruct.PLL.PLLN = 192; // 960 MHz -#else -#error Unsupported externall clock value, check HSE_VALUE define +#elif HSE_VALUE==8000000 + RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz + RCC_OscInitStruct.PLL.PLLN = 480; // 960 MHz #endif RCC_OscInitStruct.PLL.PLLP = 2; // PLLCLK = SYSCLK = 480 MHz RCC_OscInitStruct.PLL.PLLQ = 96; // PLL1Q used for FDCAN = 10 MHz diff --git a/targets/TARGET_STM/TARGET_STM32H7/objects.h b/targets/TARGET_STM/TARGET_STM32H7/objects.h index aa2bf28..5f94a8e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/objects.h +++ b/targets/TARGET_STM/TARGET_STM32H7/objects.h @@ -106,7 +106,11 @@ #if DEVICE_QSPI struct qspi_s { +#if defined(OCTOSPI1) + OSPI_HandleTypeDef handle; +#else QSPI_HandleTypeDef handle; +#endif QSPIName qspi; PinName io0; PinName io1; @@ -117,6 +121,24 @@ }; #endif +#if DEVICE_OSPI +struct ospi_s { + OSPI_HandleTypeDef handle; + OSPIName ospi; + PinName io0; + PinName io1; + PinName io2; + PinName io3; + PinName io4; + PinName io5; + PinName io6; + PinName io7; + PinName sclk; + PinName ssel; + PinName dqs; +}; +#endif + #define GPIO_IP_WITHOUT_BRR #if defined(DUAL_CORE) diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/STM32L1xx_HAL_Driver/stm32l1xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/STM32L1xx_HAL_Driver/stm32l1xx_hal_flash.h index 39fa45b..1fca7fc 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/STM32L1xx_HAL_Driver/stm32l1xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/STM32L1xx_HAL_Driver/stm32l1xx_hal_flash.h @@ -121,7 +121,9 @@ * @{ */ -#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) * 1024U) +#define FLASH_SIZE_RAW (uint32_t)(*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) +#define FLASH_SIZE (((FLASH_SIZE_RAW) == 0 ? 384 : ((FLASH_SIZE_RAW) == 1 ? 256 : (FLASH_SIZE_RAW))) * 1024) + #define FLASH_PAGE_SIZE (256U) /*!< FLASH Page Size in bytes */ /** diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index f3c27aa..293deda 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -546,7 +546,7 @@ irq_handler(can_irq_contexts[id], IRQ_TX); } } -#if (defined FDCAN_IT_RX_BUFFER_NEW_MESSAGE) +#if (defined FDCAN_IT_RX_BUFFER_NEW_MESSAGE) && !defined(TARGET_STM32H7) if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE); @@ -628,7 +628,7 @@ interrupts = FDCAN_IT_TX_COMPLETE; break; case IRQ_RX: -#if (defined FDCAN_IT_RX_BUFFER_NEW_MESSAGE) +#if (defined FDCAN_IT_RX_BUFFER_NEW_MESSAGE) && !defined(TARGET_STM32H7) interrupts = FDCAN_IT_RX_BUFFER_NEW_MESSAGE; #else interrupts = FDCAN_IT_RX_FIFO0_NEW_MESSAGE; @@ -1024,7 +1024,7 @@ msg->type = (CANType)(((uint8_t)0x02 & can->sFIFOMailBox[rxfifo_default].RIR) >> 1); /* Get the DLC */ - msg->len = (uint8_t)0x0F & can->sFIFOMailBox[rxfifo_default].RDTR; + msg->len = ((uint8_t)0x0F & can->sFIFOMailBox[rxfifo_default].RDTR < 8) ? ((uint8_t)0x0F & can->sFIFOMailBox[rxfifo_default].RDTR) : ((uint8_t) 8); /* Get the FMI */ // msg->FMI = (uint8_t)0xFF & (can->sFIFOMailBox[rxfifo_default].RDTR >> 8); /* Get the data field */ diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index 3478e95..266eeaa 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -893,7 +893,7 @@ * Return whether the given state is a state where we can start a new I2C transaction with the * STM32 HAL. */ -inline bool i2c_is_ready_for_transaction_start(stm_i2c_state state) +bool i2c_is_ready_for_transaction_start(stm_i2c_state state) { // Note: We can safely send a transaction start in the middle of any single byte operation; this creates a // repeated start. diff --git a/targets/TARGET_STM/ospi_api.c b/targets/TARGET_STM/ospi_api.c index f7afd63..4816fd0 100644 --- a/targets/TARGET_STM/ospi_api.c +++ b/targets/TARGET_STM/ospi_api.c @@ -336,9 +336,12 @@ pin_function(pinmap->dqs_pin, pinmap->dqs_function); pin_mode(pinmap->dqs_pin, PullNone); -#if defined(OCTOSPI2) +#if defined(OCTOSPIM) +#if defined(TARGET_STM32H7) + __HAL_RCC_OCTOSPIM_CLK_ENABLE(); +#else __HAL_RCC_OSPIM_CLK_ENABLE(); - +#endif OSPIM_CfgTypeDef OSPIM_Cfg_Struct = {0}; /* The OctoSPI IO Manager OCTOSPIM configuration is supported in a simplified mode in mbed-os diff --git a/targets/targets.json b/targets/targets.json index 7f67d09..1ca8daa 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1487,7 +1487,7 @@ "STM32F103xE" ] }, - "MCU_STM32F103xD": { + "MCU_STM32F103xD": { "inherits": [ "MCU_STM32F1" ], @@ -3021,7 +3021,8 @@ "MPU", "SERIAL_ASYNCH", "TRNG", - "CAN" + "CAN", + "CRC" ] }, "MCU_STM32G431xB": { @@ -3447,6 +3448,75 @@ "CORE_CM7" ] }, + "NUCLEO_H745ZI_Q_CM7": { + "inherits": [ + "MCU_STM32H745xI_CM7" + ], + "extra_labels_add": [ "NUCLEO_H745ZI_Q" ], + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "config": { + "d11_configuration": { + "help": "Value: PB_5 for the default board configuration, PA_7 in case of solder bridge update (SB33 on/ SB35 off)", + "value": "PB_5", + "macro_name": "STM32_D11_SPI_ETHERNET_PIN" + }, + "hse_value": { + "help": "HSE default value is 25MHz in HAL", + "value": "8000000", + "macro_name": "HSE_VALUE" + }, + "usb_speed": { + "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", + "value": "USE_USB_OTG_FS" + } + }, + "device_has_add": [ + "USBDEVICE" + ], + "overrides": { + "network-default-interface-type": "ETHERNET" + }, + "device_name": "STM32H745ZITx" + }, + "NUCLEO_H745ZI_Q_CM4": { + "inherits": [ + "MCU_STM32H745xI_CM4" + ], + "extra_labels_add": [ "NUCLEO_H745ZI_Q" ], + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "config": { + "d11_configuration": { + "help": "Value: PB_5 for the default board configuration, PA_7 in case of solder bridge update (SB33 on/ SB35 off)", + "value": "PB_5", + "macro_name": "STM32_D11_SPI_ETHERNET_PIN" + }, + "hse_value": { + "help": "HSE default value is 25MHz in HAL", + "value": "8000000", + "macro_name": "HSE_VALUE" + }, + "usb_speed": { + "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", + "value": "USE_USB_OTG_FS" + } + }, + "device_has_add": [ + "USBDEVICE" + ], + "overrides": { + "network-default-interface-type": "ETHERNET" + }, + "device_name": "STM32H745ZITx" + }, + "NUCLEO_H745ZI_Q" : { + "inherits" : [ + "NUCLEO_H745ZI_Q_CM7" + ] + }, "MCU_STM32H747xI": { "inherits": [ "MCU_STM32H7" @@ -7215,6 +7285,9 @@ "gpio-irq-debounce-sample-rate": { "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", "value": "GPIO_DBCTL_DBCLKSEL_16" + }, + "eadc-extsmpt-list": { + "help": "For EADC, comma separated {pin, value} list to extend sampling time in EADC clocks on per-pin basis. Value must be in the range [0, 255]." } }, "inherits": [ @@ -7327,6 +7400,9 @@ "gpio-irq-debounce-sample-rate": { "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", "value": "GPIO_DBCTL_DBCLKSEL_16" + }, + "eadc-extsmpt-list": { + "help": "For EADC, comma separated {pin, value} list to extend sampling time in EADC clocks on per-pin basis. Value must be in the range [0, 255]." } }, "inherits": [ @@ -7447,6 +7523,9 @@ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768", "value": "GPIO_DBCLKSEL_16" }, + "adc-smplcnt-list": { + "help": "For ADC, comma separated {pin, value} list to extend sampling time in ADC clocks on per-pin basis. Value must be in the range [0, 15]." + }, "clock-pll": { "help": "Choose clock source to clock PLL: NU_HXT_PLL or NU_HIRC_PLL", "macro_name": "NU_CLOCK_PLL", @@ -7584,6 +7663,9 @@ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", "value": "GPIO_DBCTL_DBCLKSEL_16" }, + "eadc-extsmpt-list": { + "help": "For EADC, comma separated {pin, value} list to extend sampling time in EADC clocks on per-pin basis. Value must be in the range [0, 255]." + }, "exclude-uno-spi-from-fpga-ci-test-shield-test": { "help": "Exclude UNO SPI pins (D8/D9/D10/D11/D12/D13) from FPGA CI Test Shield test for wiring to on-board SPI flash", "options": [false, true], @@ -7640,6 +7722,7 @@ "MPU", "WATCHDOG", "RESET_REASON", + "CAN", "EMAC", "USBDEVICE" ], @@ -7774,6 +7857,9 @@ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", "value": "GPIO_DBCTL_DBCLKSEL_16" }, + "eadc-extsmpt-list": { + "help": "For EADC, comma separated {pin, value} list to extend sampling time in EADC clocks on per-pin basis. Value must be in the range [0, 255]." + }, "usb-device-hsusbd": { "help": "Select high-speed USB device or not", "value": 0 @@ -8133,6 +8219,9 @@ "gpio-irq-debounce-sample-rate": { "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", "value": "GPIO_DBCTL_DBCLKSEL_16" + }, + "eadc-extsmpt-list": { + "help": "For EADC, comma separated {pin, value} list to extend sampling time in EADC clocks on per-pin basis. Value must be in the range [0, 255]." } }, "overrides": { @@ -8279,6 +8368,9 @@ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", "value": "GPIO_DBCTL_DBCLKSEL_16" }, + "eadc-extsmpt-list": { + "help": "For EADC, comma separated {pin, value} list to extend sampling time in EADC clocks on per-pin basis. Value must be in the range [0, 255]." + }, "hxt-enable": { "help": "Enable external high-speed crystal (HXT)", "value": 0, @@ -9219,6 +9311,9 @@ "gpio-irq-debounce-sample-rate": { "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", "value": "GPIO_DBCTL_DBCLKSEL_16" + }, + "eadc-extsmpt-list": { + "help": "For EADC, comma separated {pin, value} list to extend sampling time in EADC clocks on per-pin basis. Value must be in the range [0, 255]." } }, "inherits": [