diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct
deleted file mode 100644
index 7ff0133..0000000
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct
+++ /dev/null
@@ -1,52 +0,0 @@
-#! armcc -E
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START 0x00000000
-#endif
-
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE 0x20000
-#endif
-
-#if !defined(MBED_RAM_START)
- #define MBED_RAM_START 1FFFF000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
- #define MBED_RAM_SIZE 0x4000
-#endif
-
-#define MBED_RAM1_START (MBED_RAM_START+VECTOR_SIZE)
-
-
-#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
-# if defined(MBED_BOOT_STACK_SIZE)
-# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
-# else
-# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
-# endif
-#endif
-
-; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
-#define VECTOR_SIZE 0xC0
-
-#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE+VECTOR_SIZE)
-
-LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
-
- ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- RW_IRAM1 MBED_RAM1_START (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
- .ANY (+RW +ZI)
- }
-
- ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM1_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
- }
-
- ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; stack
- }
-}
diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.S b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.S
deleted file mode 100644
index b89135e..0000000
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.S
+++ /dev/null
@@ -1,328 +0,0 @@
-;/*****************************************************************************
-; * @file: startup_MKL25Z4.s
-; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
-; * MKL25Z4
-; * @version: 1.1
-; * @date: 2012-6-21
-; *
-; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-; *****************************************************************************/
-
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
- IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
-
-__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
- DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
- DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
- DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
- DCD Reserved20_IRQHandler ; Reserved interrupt 20
- DCD FTFA_IRQHandler ; FTFA interrupt
- DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
- DCD LLW_IRQHandler ; Low Leakage Wakeup
- DCD I2C0_IRQHandler ; I2C0 interrupt
- DCD I2C1_IRQHandler ; I2C0 interrupt 25
- DCD SPI0_IRQHandler ; SPI0 interrupt
- DCD SPI1_IRQHandler ; SPI1 interrupt
- DCD UART0_IRQHandler ; UART0 status/error interrupt
- DCD UART1_IRQHandler ; UART1 status/error interrupt
- DCD UART2_IRQHandler ; UART2 status/error interrupt
- DCD ADC0_IRQHandler ; ADC0 interrupt
- DCD CMP0_IRQHandler ; CMP0 interrupt
- DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
- DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
- DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
- DCD RTC_IRQHandler ; RTC interrupt
- DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
- DCD PIT_IRQHandler ; PIT timer interrupt
- DCD Reserved39_IRQHandler ; Reserved interrupt 39
- DCD USB0_IRQHandler ; USB0 interrupt
- DCD DAC0_IRQHandler ; DAC interrupt
- DCD TSI0_IRQHandler ; TSI0 interrupt
- DCD MCG_IRQHandler ; MCG interrupt
- DCD LPTimer_IRQHandler ; LPTimer interrupt
- DCD Reserved45_IRQHandler ; Reserved interrupt 45
- DCD PORTA_IRQHandler ; Port A interrupt
- DCD PORTD_IRQHandler ; Port D interrupt
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-; Flash Configuration
-; 16-byte flash configuration field that stores default protection settings (loaded on reset)
-; and security information that allows the MCU to restrict acces to the FTFL module.
-; Backdoor Comparison Key
-; Backdoor Key 0 <0x0-0xFF:2>
-; Backdoor Key 1 <0x0-0xFF:2>
-; Backdoor Key 2 <0x0-0xFF:2>
-; Backdoor Key 3 <0x0-0xFF:2>
-; Backdoor Key 4 <0x0-0xFF:2>
-; Backdoor Key 5 <0x0-0xFF:2>
-; Backdoor Key 6 <0x0-0xFF:2>
-; Backdoor Key 7 <0x0-0xFF:2>
-BackDoorK0 EQU 0xFF
-BackDoorK1 EQU 0xFF
-BackDoorK2 EQU 0xFF
-BackDoorK3 EQU 0xFF
-BackDoorK4 EQU 0xFF
-BackDoorK5 EQU 0xFF
-BackDoorK6 EQU 0xFF
-BackDoorK7 EQU 0xFF
-;
-; Program flash protection bytes (FPROT)
-; Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
-; Each bit protects a 1/32 region of the program flash memory.
-; FPROT0
-; Program flash protection bytes
-; 1/32 - 8/32 region
-; FPROT0.0
-; FPROT0.1
-; FPROT0.2
-; FPROT0.3
-; FPROT0.4
-; FPROT0.5
-; FPROT0.6
-; FPROT0.7
-nFPROT0 EQU 0x00
-FPROT0 EQU nFPROT0:EOR:0xFF
-;
-; FPROT1
-; Program Flash Region Protect Register 1
-; 9/32 - 16/32 region
-; FPROT1.0
-; FPROT1.1
-; FPROT1.2
-; FPROT1.3
-; FPROT1.4
-; FPROT1.5
-; FPROT1.6
-; FPROT1.7
-nFPROT1 EQU 0x00
-FPROT1 EQU nFPROT1:EOR:0xFF
-;
-; FPROT2
-; Program Flash Region Protect Register 2
-; 17/32 - 24/32 region
-; FPROT2.0
-; FPROT2.1
-; FPROT2.2
-; FPROT2.3
-; FPROT2.4
-; FPROT2.5
-; FPROT2.6
-; FPROT2.7
-nFPROT2 EQU 0x00
-FPROT2 EQU nFPROT2:EOR:0xFF
-;
-; FPROT3
-; Program Flash Region Protect Register 3
-; 25/32 - 32/32 region
-; FPROT3.0
-; FPROT3.1
-; FPROT3.2
-; FPROT3.3
-; FPROT3.4
-; FPROT3.5
-; FPROT3.6
-; FPROT3.7
-nFPROT3 EQU 0x00
-FPROT3 EQU nFPROT3:EOR:0xFF
-;
-;
-;
-; Flash nonvolatile option byte (FOPT)
-; Allows the user to customize the operation of the MCU at boot time.
-; LPBOOT0
-; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
-; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
-; LPBOOT1
-; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
-; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
-; NMI_DIS
-; <0=> NMI interrupts are always blocked
-; <1=> NMI pin/interrupts reset default to enabled
-; RESET_PIN_CFG
-; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
-; <1=> RESET pin is dedicated
-; FAST_INIT
-; <0=> Slower initialization
-; <1=> Fast Initialization
-FOPT EQU 0xFF
-;
-; Flash security byte (FSEC)
-; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
-; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
-; SEC
-; <2=> MCU security status is unsecure
-; <3=> MCU security status is secure
-; Flash Security
-; This bits define the security state of the MCU.
-; FSLACC
-; <2=> Freescale factory access denied
-; <3=> Freescale factory access granted
-; Freescale Failure Analysis Access Code
-; This bits define the security state of the MCU.
-; MEEN
-; <2=> Mass erase is disabled
-; <3=> Mass erase is enabled
-; Mass Erase Enable Bits
-; Enables and disables mass erase capability of the FTFL module
-; KEYEN
-; <2=> Backdoor key access enabled
-; <3=> Backdoor key access disabled
-; Backdoor key Security Enable
-; These bits enable and disable backdoor key access to the FTFL module.
-FSEC EQU 0xFE
-;
-
- IF :LNOT::DEF:RAM_TARGET
- AREA |.ARM.__at_0x400|, CODE, READONLY
- DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
- DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
- DCB FPROT0, FPROT1, FPROT2, FPROT3
- DCB FSEC, FOPT, 0xFF, 0xFF
- ENDIF
-
- AREA |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
- EXPORT DMA0_IRQHandler [WEAK]
- EXPORT DMA1_IRQHandler [WEAK]
- EXPORT DMA2_IRQHandler [WEAK]
- EXPORT DMA3_IRQHandler [WEAK]
- EXPORT Reserved20_IRQHandler [WEAK]
- EXPORT FTFA_IRQHandler [WEAK]
- EXPORT LVD_LVW_IRQHandler [WEAK]
- EXPORT LLW_IRQHandler [WEAK]
- EXPORT I2C0_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI0_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT ADC0_IRQHandler [WEAK]
- EXPORT CMP0_IRQHandler [WEAK]
- EXPORT TPM0_IRQHandler [WEAK]
- EXPORT TPM1_IRQHandler [WEAK]
- EXPORT TPM2_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT RTC_Seconds_IRQHandler [WEAK]
- EXPORT PIT_IRQHandler [WEAK]
- EXPORT Reserved39_IRQHandler [WEAK]
- EXPORT USB0_IRQHandler [WEAK]
- EXPORT DAC0_IRQHandler [WEAK]
- EXPORT TSI0_IRQHandler [WEAK]
- EXPORT MCG_IRQHandler [WEAK]
- EXPORT LPTimer_IRQHandler [WEAK]
- EXPORT Reserved45_IRQHandler [WEAK]
- EXPORT PORTA_IRQHandler [WEAK]
- EXPORT PORTD_IRQHandler [WEAK]
- EXPORT DefaultISR [WEAK]
-
-DMA0_IRQHandler
-DMA1_IRQHandler
-DMA2_IRQHandler
-DMA3_IRQHandler
-Reserved20_IRQHandler
-FTFA_IRQHandler
-LVD_LVW_IRQHandler
-LLW_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-ADC0_IRQHandler
-CMP0_IRQHandler
-TPM0_IRQHandler
-TPM1_IRQHandler
-TPM2_IRQHandler
-RTC_IRQHandler
-RTC_Seconds_IRQHandler
-PIT_IRQHandler
-Reserved39_IRQHandler
-USB0_IRQHandler
-DAC0_IRQHandler
-TSI0_IRQHandler
-MCG_IRQHandler
-LPTimer_IRQHandler
-Reserved45_IRQHandler
-PORTA_IRQHandler
-PORTD_IRQHandler
-DefaultISR
-
- B .
-
- ENDP
-
-
- ALIGN
- END
diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_STD/MKL25Z4.sct b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_STD/MKL25Z4.sct
index 0789bfe..0eaed7d 100644
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_STD/MKL25Z4.sct
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_STD/MKL25Z4.sct
@@ -1,5 +1,22 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0plus
+#if !defined(MBED_APP_START)
+#define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+#define MBED_APP_SIZE 0x20000
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x1FFFF000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x4000
+#endif
+
+
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
@@ -8,25 +25,28 @@
# endif
#endif
-#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
+; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+#define VECTOR_SIZE 0xC0
-LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
- ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
+
+#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
+#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (32k)
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
- ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
- ; 0x4000 - 0xC0 = 0x3F40
- RW_IRAM1 0x1FFFF0C0 0x3F40 {
+ RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE {
.ANY (+RW +ZI)
}
-
- ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x1FFFF000+0x4000-Stack_Size-AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE - RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - MBED_RAM1_START)) { ; Heap region growing up
}
- ARM_LIB_STACK 0x1FFFF000+0x4000 EMPTY -Stack_Size { ; Stack region growing down
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
}
}
-
diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/device/TOOLCHAIN_ARM_STD/MKL46Z4.sct b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/device/TOOLCHAIN_ARM_STD/MKL46Z4.sct
index 45dd786..b3b22fd 100644
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/device/TOOLCHAIN_ARM_STD/MKL46Z4.sct
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/device/TOOLCHAIN_ARM_STD/MKL46Z4.sct
@@ -1,5 +1,21 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0plus
+#if !defined(MBED_APP_START)
+#define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+#define MBED_APP_SIZE 0x40000
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x1FFFE000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x8000
+#endif
+
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
@@ -8,24 +24,29 @@
# endif
#endif
-#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
+#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
-LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
- ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+#define VECTOR_SIZE 0xC0
+
+#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
+#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (256k)
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
- ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+
; 0x8000 - 0xC0 = 0x7F40
- RW_IRAM1 0x1FFFE0C0 0x7F40 {
+ RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE {
.ANY (+RW +ZI)
}
-
- ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x1FFFE000+0x8000-Stack_Size-AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE - RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - MBED_RAM1_START)) { ; Heap region growing up
}
- ARM_LIB_STACK 0x1FFFE000+0x8000 EMPTY -Stack_Size { ; Stack region growing down
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
}
}
-
diff --git a/targets/targets.json b/targets/targets.json
index 0e31d36..3e1edcb 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -468,9 +468,6 @@
"gcc_arm": [
"std",
"small"
- ],
- "iar": [
- "std"
]
},
"supported_application_profiles": [
@@ -531,9 +528,6 @@
"gcc_arm": [
"std",
"small"
- ],
- "iar": [
- "std"
]
},
"supported_application_profiles": [
@@ -604,9 +598,6 @@
"gcc_arm": [
"std",
"small"
- ],
- "iar": [
- "std"
]
},
"supported_application_profiles": [
@@ -694,9 +685,6 @@
"gcc_arm": [
"std",
"small"
- ],
- "iar": [
- "std"
]
},
"supported_application_profiles": [
@@ -1172,9 +1160,6 @@
"gcc_arm": [
"std",
"small"
- ],
- "iar": [
- "std"
]
},
"supported_application_profiles": [