diff --git a/targets/TARGET_Maxim/CMakeLists.txt b/targets/TARGET_Maxim/CMakeLists.txt index bdbb751..e725bc8 100644 --- a/targets/TARGET_Maxim/CMakeLists.txt +++ b/targets/TARGET_Maxim/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# Copyright (c) 2022 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 @@ -6,6 +6,7 @@ add_subdirectory(TARGET_MAX32625 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_MAX32630 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_MAX32660 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_MAX32670 EXCLUDE_FROM_ALL) add_library(mbed-maxim INTERFACE) diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt b/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt index 9710d86..eb84b0d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt +++ b/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# Copyright (c) 2022 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 add_subdirectory(TARGET_MAX32670EVKIT EXCLUDE_FROM_ALL) @@ -27,16 +27,20 @@ ${MXM_PERIPH_DRIVER_DIR}/Include/${MXM_PARTNUMBER} ${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Include + ${MXM_SOURCE_DIR}/AES + ${MXM_SOURCE_DIR}/CRC ${MXM_SOURCE_DIR}/DMA ${MXM_SOURCE_DIR}/LP ${MXM_SOURCE_DIR}/FLC ${MXM_SOURCE_DIR}/GPIO - ${MXM_SOURCE_DIR}/I2C + ${MXM_SOURCE_DIR}/I2C + ${MXM_SOURCE_DIR}/I2S ${MXM_SOURCE_DIR}/ICC ${MXM_SOURCE_DIR}/RTC ${MXM_SOURCE_DIR}/SPI - ${MXM_SOURCE_DIR}/SPIMSS + ${MXM_SOURCE_DIR}/SYS ${MXM_SOURCE_DIR}/TMR + ${MXM_SOURCE_DIR}/TRNG ${MXM_SOURCE_DIR}/UART ${MXM_SOURCE_DIR}/WDT ) @@ -59,55 +63,63 @@ watchdog_api.c ${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Source/system_max32670.c - + + ${MXM_SOURCE_DIR}/AES/aes_me15.c + ${MXM_SOURCE_DIR}/AES/aes_revb.c + + ${MXM_SOURCE_DIR}/CRC/crc_me15.c + ${MXM_SOURCE_DIR}/CRC/crc_reva.c + ${MXM_SOURCE_DIR}/SYS/mxc_assert.c ${MXM_SOURCE_DIR}/SYS/mxc_delay.c ${MXM_SOURCE_DIR}/SYS/mxc_lock.c - ${MXM_SOURCE_DIR}/SYS/pins_me11.c - ${MXM_SOURCE_DIR}/SYS/sys_me11.c + ${MXM_SOURCE_DIR}/SYS/pins_me15.c + ${MXM_SOURCE_DIR}/SYS/sys_me15.c - ${MXM_SOURCE_DIR}/DMA/dma_me11.c + ${MXM_SOURCE_DIR}/DMA/dma_me15.c ${MXM_SOURCE_DIR}/DMA/dma_reva.c - ${MXM_SOURCE_DIR}/LP/lp_me11.c + ${MXM_SOURCE_DIR}/LP/lp_me15.c ${MXM_SOURCE_DIR}/FLC/flc_common.c - ${MXM_SOURCE_DIR}/FLC/flc_me11.c + ${MXM_SOURCE_DIR}/FLC/flc_me15.c ${MXM_SOURCE_DIR}/FLC/flc_reva.c + ${MXM_SOURCE_DIR}/FLC/flc_revb.c ${MXM_SOURCE_DIR}/GPIO/gpio_common.c - ${MXM_SOURCE_DIR}/GPIO/gpio_me11.c + ${MXM_SOURCE_DIR}/GPIO/gpio_me15.c ${MXM_SOURCE_DIR}/GPIO/gpio_reva.c - ${MXM_SOURCE_DIR}/I2C/i2c_me11.c + ${MXM_SOURCE_DIR}/I2C/i2c_me15.c ${MXM_SOURCE_DIR}/I2C/i2c_reva.c - ${MXM_SOURCE_DIR}/SPIMSS/spimss_me11.c - ${MXM_SOURCE_DIR}/SPIMSS/spimss_reva.c - ${MXM_SOURCE_DIR}/SPIMSS/i2s_me11.c - ${MXM_SOURCE_DIR}/SPIMSS/i2s_reva.c + ${MXM_SOURCE_DIR}/I2S/i2s_me15.c + ${MXM_SOURCE_DIR}/I2S/i2s_reva.c ${MXM_SOURCE_DIR}/ICC/icc_common.c - ${MXM_SOURCE_DIR}/ICC/icc_me11.c + ${MXM_SOURCE_DIR}/ICC/icc_me15.c ${MXM_SOURCE_DIR}/ICC/icc_reva.c - ${MXM_SOURCE_DIR}/RTC/rtc_me11.c + ${MXM_SOURCE_DIR}/RTC/rtc_me15.c ${MXM_SOURCE_DIR}/RTC/rtc_reva.c - ${MXM_SOURCE_DIR}/SPI/spi_me11.c + ${MXM_SOURCE_DIR}/SPI/spi_me15.c ${MXM_SOURCE_DIR}/SPI/spi_reva.c ${MXM_SOURCE_DIR}/TMR/tmr_common.c - ${MXM_SOURCE_DIR}/TMR/tmr_me11.c - ${MXM_SOURCE_DIR}/TMR/tmr_reva.c + ${MXM_SOURCE_DIR}/TMR/tmr_me15.c + ${MXM_SOURCE_DIR}/TMR/tmr_revb.c + + ${MXM_SOURCE_DIR}/TRNG/trng_me15.c + ${MXM_SOURCE_DIR}/TRNG/trng_revb.c ${MXM_SOURCE_DIR}/UART/uart_common.c - ${MXM_SOURCE_DIR}/UART/uart_me11.c - ${MXM_SOURCE_DIR}/UART/uart_reva.c + ${MXM_SOURCE_DIR}/UART/uart_me15.c + ${MXM_SOURCE_DIR}/UART/uart_revb.c ${MXM_SOURCE_DIR}/WDT/wdt_common.c - ${MXM_SOURCE_DIR}/WDT/wdt_me11.c - ${MXM_SOURCE_DIR}/WDT/wdt_reva.c + ${MXM_SOURCE_DIR}/WDT/wdt_me15.c + ${MXM_SOURCE_DIR}/WDT/wdt_revb.c ${STARTUP_FILE} ) diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/PeripheralPins.c b/targets/TARGET_Maxim/TARGET_MAX32670/PeripheralPins.c index 83486a0..0c59459 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/PeripheralPins.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/PeripheralPins.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (c) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -44,75 +44,89 @@ * the pointers to the "function" data members. */ - /************I2C***************/ const PinMap PinMap_I2C_SDA[] = { - { P0_9, I2C_0, 1 }, - { P0_3, I2C_1, 1 }, - { NC, NC, 0 } + { P0_7 , I2C_0, 1 }, // I2C0_SDA + { P0_13, I2C_1, 1 }, // I2C1_SDA + { P0_19, I2C_2, 1 }, // I2C2_SDA + { NC, NC, 0 } }; const PinMap PinMap_I2C_SCL[] = { - { P0_8, I2C_0, 1 }, - { P0_2, I2C_1, 1 }, - { NC, NC, 0 } + { P0_6, I2C_0, 1 }, // I2C0_SCL + { P0_12, I2C_1, 1 }, // I2C1_SCL + { P0_18, I2C_2, 1 }, // I2C2_SCL + { NC, NC, 0 } }; + /************UART***************/ const PinMap PinMap_UART_TX[] = { - {P0_4, UART_0, 2}, - {P0_10, UART_1, 2}, - {P0_0, UART_1, 3}, - {P0_6, UART_1, 3}, - {NC, NC, 0} + { P0_9 , UART_0, 1 }, // UART0A_TX + { P0_25, UART_0, 2 }, // UART0B_TX + { P0_29, UART_1, 1 }, // UART1A_TX + { P0_3, UART_1, 2 }, // UART1B_TX + { P0_15, UART_2, 2 }, // UART2B_TX + { P0_27, UART_3, 1 }, // LPUART0_TX + { NC, NC, 0 } }; const PinMap PinMap_UART_RX[] = { - {P0_5, UART_0, 2}, - {P0_11, UART_1, 2}, - {P0_1, UART_1, 3}, - {P0_7, UART_1, 3}, - {NC, NC, 0} + { P0_8, UART_0, 1 }, // UART0A_RX + { P0_24, UART_0, 2 }, // UART0B_RX + { P0_28, UART_1, 1 }, // UART1A_RX + { P0_2, UART_1, 2 }, // UART1B_RX + { P0_14, UART_2, 2 }, // UART2B_RX + { P0_26, UART_3, 1 }, // LPUART0_RX + { NC, NC, 0 } }; const PinMap PinMap_UART_CTS[] = { - {P0_6, UART_0, 2}, - {P0_12, UART_1, 2}, - {NC, NC, 0} + { P0_10, UART_0, 1 }, // UART0A_CTS + { P0_26, UART_0, 2 }, // UART0B_CTS + { P0_30, UART_1, 1 }, // UART1A_CTS + { P0_4, UART_1, 2 }, // UART1B_CTS + { P0_16, UART_2, 2 }, // UART2B_CTS + { P0_24, UART_3, 1 }, // LPUART0_CTS + { NC, NC, 0 } }; const PinMap PinMap_UART_RTS[] = { - {P0_7, UART_0, 2}, - {P0_13, UART_1, 2}, - {NC, NC, 0} + { P0_11, UART_0, 1 }, // UART0A_RTS + { P0_27, UART_0, 2 }, // UART0B_RTS + { P0_31, UART_1, 1 }, // UART1A_RTS + { P0_5, UART_1, 2 }, // UART1B_RTS + { P0_17, UART_2, 2 }, // UART2B_RTS + { P0_25, UART_3, 1 }, // LPUART0_RTS + { NC, NC, 0 } }; + /************SPI***************/ const PinMap PinMap_SPI_SCLK[] = { - { P0_6, SPI_0, 1 }, - { P0_12, SPI_1, 1 }, - { P0_2, SPI_1, 2 }, - { NC, NC, 0 } + { P0_4, SPI_0, 1 }, // SPI0_SCK + { P0_16, SPI_1, 1 }, // SPI1_SCK + { P1_3, SPI_2, 1 }, // SPI2_SCK + { NC, NC, 0 } }; const PinMap PinMap_SPI_MOSI[] = { - { P0_5, SPI_0, 1 }, - { P0_11, SPI_1, 1 }, - { P0_1, SPI_1, 2 }, - { NC, NC, 0 } + { P0_3, SPI_0, 1 }, // SPI0_MOSI + { P0_15, SPI_1, 1 }, // SPI1_MOSI + { P1_2, SPI_2, 1 }, // SPI2_MOSI + { NC, NC, 0 } }; const PinMap PinMap_SPI_MISO[] = { - { P0_4, SPI_0, 1 }, - { P0_10, SPI_1, 1 }, - { P0_0, SPI_1, 2 }, - { NC, NC, 0 } + { P0_2, SPI_0, 1 }, // SPI0_MISO + { P0_14, SPI_1, 1 }, // SPI1_MISO + { P1_1, SPI_2, 1 }, // SPI2_MISO + { NC, NC, 0 } }; const PinMap PinMap_SPI_SSEL[] = { - { P0_7, SPI_0, 1 }, - { P0_13, SPI_1, 1 }, - { P0_3, SPI_1, 2 }, - { NC, NC, 0 } + { P0_5, SPI_0, 1 }, // SPI0_SS + { P0_17, SPI_1, 1 }, // SPI1_SS + { P1_4, SPI_2, 1 }, // SPI2_SS + { NC, NC, 0 } }; - diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/PortNames.h b/targets/TARGET_Maxim/TARGET_MAX32670/PortNames.h index c87eb5b..e30ac95 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/PortNames.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/PortNames.h @@ -40,6 +40,7 @@ typedef enum { Port0 = 0, + Port1 = 1, } PortName; #ifdef __cplusplus diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/CMakeLists.txt b/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/CMakeLists.txt index 0c7da6c..15ea5ea 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/CMakeLists.txt +++ b/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2021 ARM Limited. All rights reserved. +# Copyright (c) 2022 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 add_library(mbed-max32670evkit INTERFACE) diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/PeripheralNames.h b/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/PeripheralNames.h index 57dcb77..b7d88f9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/PeripheralNames.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/PeripheralNames.h @@ -43,21 +43,25 @@ typedef enum { UART_0 = MXC_BASE_UART0, UART_1 = MXC_BASE_UART1, + UART_2 = MXC_BASE_UART2, + UART_3 = MXC_BASE_UART3, #if defined(MBED_CONF_TARGET_STDIO_UART) STDIO_UART = MBED_CONF_TARGET_STDIO_UART, #else - STDIO_UART = UART_1, + STDIO_UART = UART_0, #endif } UARTName; typedef enum { I2C_0 = MXC_BASE_I2C0, I2C_1 = MXC_BASE_I2C1, + I2C_2 = MXC_BASE_I2C2, } I2CName; typedef enum { - SPI_0 = MXC_BASE_SPI, - SPI_1 = MXC_BASE_SPIMSS, + SPI_0 = MXC_BASE_SPI0, + SPI_1 = MXC_BASE_SPI1, + SPI_2 = MXC_BASE_SPI2, } SPIName; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/PinNames.h b/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/PinNames.h index 3417f5c..700d816 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/PinNames.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/TARGET_MAX32670EVKIT/PinNames.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -31,7 +31,7 @@ ******************************************************************************* */ -/* MBED TARGET LIST: MAX32660EVSYS */ +/* MBED TARGET LIST: MAX32670EVKIT */ #ifndef MBED_PINNAMES_H #define MBED_PINNAMES_H @@ -55,61 +55,108 @@ #define NOT_CONNECTED (int)0xFFFFFFFF typedef enum { - P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, + // Port 0 + P0_0 = (0 << PORT_SHIFT), + P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, + P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23,P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31, + + // Port 1 + P1_0 = (1 << PORT_SHIFT), + P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, + P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23,P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31, // USB bridge connected UART pins #if defined(MBED_CONF_TARGET_STDIO_UART_TX) CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, #else - CONSOLE_TX = P0_10, + CONSOLE_TX = P0_9, #endif #if defined(MBED_CONF_TARGET_STDIO_UART_RX) CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, #else - CONSOLE_RX = P0_11, + CONSOLE_RX = P0_8, #endif STDIO_UART_TX = CONSOLE_TX, STDIO_UART_RX = CONSOLE_RX, // I2C pins - I2C0_SCL = P0_8, - I2C0_SDA = P0_9, - - I2C1_SCL = P0_2, - I2C1_SDA = P0_3, + I2C0_SCL = P0_6, + I2C0_SDA = P0_7, + // + I2C1_SCL = P0_12, + I2C1_SDA = P0_13, + // + I2C2_SCL = P0_18, + I2C2_SDA = P0_19, // SPI pins - SPI0_SCK = P0_6, - SPI0_MOSI = P0_5, - SPI0_MISO = P0_4, - SPI0_SS = P0_7, + SPI0_SCK = P0_4, + SPI0_MOSI = P0_3, + SPI0_MISO = P0_2, + SPI0_SS = P0_5, - SPI1A_SCK = P0_12, - SPI1A_MOSI = P0_11, - SPI1A_MISO = P0_10, - SPI1A_SS = P0_13, + SPI1_SCK = P0_16, + SPI1_MOSI = P0_15, + SPI1_MISO = P0_14, + SPI1_SS = P0_17, - SPI1B_SCK = P0_2, - SPI1B_MOSI = P0_1, - SPI1B_MISO = P0_0, - SPI1B_SS = P0_3, + SPI2_SCK = P1_3, + SPI2_MOSI = P1_2, + SPI2_MISO = P1_1, + SPI2_SS = P1_4, // UART pins - UART0_RX = P0_5, - UART0_TX = P0_4, - UART0_CTS = P0_6, - UART0_RTS = P0_7, + UART0A_RX = P0_8, + UART0A_TX = P0_9, + UART0A_CTS = P0_10, + UART0A_RTS = P0_11, - UART1A_RX = P0_11, - UART1A_TX = P0_10, - UART1A_CTS = P0_12, - UART1A_RTS = P0_13, + UART0B_RX = P0_24, + UART0B_TX = P0_25, + UART0B_CTS = P0_26, + UART0B_RTS = P0_27, - UART1B_RX = P0_1, - UART1B_TX = P0_0, + UART1A_RX = P0_28, + UART1A_TX = P0_29, + UART1A_CTS = P0_30, + UART1A_RTS = P0_31, - UART1C_RX = P0_7, - UART1C_TX = P0_6, + UART1B_RX = P0_2, + UART1B_TX = P0_3, + UART1B_CTS = P0_4, + UART1B_RTS = P0_5, + + UART2B_RX = P0_14, + UART2B_TX = P0_15, + UART2B_CTS = P0_16, + UART2B_RTS = P0_17, + + LPUART0_RX = P0_26, + LPUART0_TX = P0_27, + LPUART0_CTS = P0_24, + LPUART0_RTS = P0_25, + + // To simplify usage + UART0_RX = UART0A_RX, + UART0_TX = UART0A_TX, + UART0_CTS = UART0A_CTS, + UART0_RTS = UART0A_RTS, + + UART1_RX = UART1A_RX, + UART1_TX = UART1A_TX, + UART1_CTS = UART1A_CTS, + UART1_RTS = UART1A_RTS, + + UART2_RX = UART2B_RX, + UART2_TX = UART2B_TX, + UART2_CTS = UART2B_CTS, + UART2_RTS = UART2B_RTS, + + UART3_RX = LPUART0_RX, + UART3_TX = LPUART0_TX, + UART3_CTS = LPUART0_CTS, + UART3_RTS = LPUART0_RTS, + // Not connected NC = NOT_CONNECTED @@ -129,15 +176,14 @@ // Standardized LED and button names -#define LED1 P0_13 // RED Led -//#define LED2 P0_12 // for greentea ticker testing! +#define LED1 P0_22 // Red Led +#define LED2 P0_23 // Green Led // -#define LED_RED LED1 // -//#define LED_GREEN LED2 // +#define LED_RED LED1 // +#define LED_GREEN LED2 // // -#define BUTTON1 P0_12 // B1 PushButton - +#define BUTTON1 P0_21 // B1 PushButton #ifdef __cplusplus } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/device.h b/targets/TARGET_Maxim/TARGET_MAX32670/device.h index f503c54..48fa058 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/device.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/device.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_ARM_STD/MAX32670.sct b/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_ARM_STD/MAX32670.sct index 227d2db..6f9701c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_ARM_STD/MAX32670.sct +++ b/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_ARM_STD/MAX32670.sct @@ -1,11 +1,9 @@ #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; MAX32660 -; 256K FLASH (0x200000) @ 0x000000000 -; 96KB RAM (0x18000) @ 0x20000000 -; - 16KB RAM_0 (0x4000) @ 0x20000000 -; - 16KB RAM_1 (0x4000) @ 0x20004000 -; - 32KB RAM_2 (0x8000) @ 0x20008000 -; - 32KB RAM_3 (0x8000) @ 0x20010000 +; MAX32670 +; 384K FLASH (0x60000) @ 0x100000000 +; 160KB RAM (0x28000) @ 0x20000000 +; +; #include "../nvic_table.h" diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_ARM_STD/startup_max32670.S b/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_ARM_STD/startup_max32670.S index a179766..effcebb 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_ARM_STD/startup_max32670.S +++ b/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_ARM_STD/startup_max32670.S @@ -62,59 +62,104 @@ ; Device-specific Interrupts DCD PF_IRQHandler ; 0x10 0x0040 16: Power Fail DCD WDT0_IRQHandler ; 0x11 0x0044 17: Watchdog 0 - DCD RSV00_IRQHandler ; 0x12 0x0048 18: RSV00 + DCD RSV02_IRQHandler ; 0x12 0x0048 18: USB DCD RTC_IRQHandler ; 0x13 0x004C 19: RTC - DCD RSV01_IRQHandler ; 0x14 0x0050 20: RSV1 + DCD TRNG_IRQHandler ; 0x14 0x0050 20: True Random Number Gener DCD TMR0_IRQHandler ; 0x15 0x0054 21: Timer 0 DCD TMR1_IRQHandler ; 0x16 0x0058 22: Timer 1 DCD TMR2_IRQHandler ; 0x17 0x005C 23: Timer 2 - DCD RSV02_IRQHandler ; 0x18 0x0060 24: RSV02 - DCD RSV03_IRQHandler ; 0x19 0x0064 25: RSV03 - DCD RSV04_IRQHandler ; 0x1A 0x0068 26: RSV04 - DCD RSV05_IRQHandler ; 0x1B 0x006C 27: RSV05 - DCD RSV06_IRQHandler ; 0x1C 0x0070 28: RSV06 + DCD TMR3_IRQHandler ; 0x18 0x0060 24: Timer 3 + DCD TMR4_IRQHandler ; 0x19 0x0064 25: Timer 4 + DCD TMR5_IRQHandler ; 0x1A 0x0068 26: Timer 5 + DCD RSV11_IRQHandler ; 0x1B 0x006C 27: Reserved + DCD RSV12_IRQHandler ; 0x1C 0x0070 28: Reserved DCD I2C0_IRQHandler ; 0x1D 0x0074 29: I2C0 DCD UART0_IRQHandler ; 0x1E 0x0078 30: UART 0 DCD UART1_IRQHandler ; 0x1F 0x007C 31: UART 1 - DCD SPI0_IRQHandler ; 0x20 0x0080 32: SPIY17 - DCD SPI1_IRQHandler ; 0x21 0x0084 33: SPIMSS - DCD RSV07_IRQHandler ; 0x22 0x0088 34: RSV07 - DCD RSV08_IRQHandler ; 0x23 0x008C 35: RSV08 - DCD RSV09_IRQHandler ; 0x24 0x0090 36: RSV09 - DCD RSV10_IRQHandler ; 0x25 0x0094 37: RSV10 - DCD RSV11_IRQHandler ; 0x26 0x0098 38: RSV11 - DCD FLC_IRQHandler ; 0x27 0x009C 39: FLC + DCD SPI0_IRQHandler ; 0x20 0x0080 32: SPI0 + DCD SPI1_IRQHandler ; 0x21 0x0084 33: SPI1 + DCD SPI2_IRQHandler ; 0x22 0x0088 34: SPI2 + DCD RSV19_IRQHandler ; 0x23 0x008C 35: Reserved + DCD RSV20_IRQHandler ; 0x24 0x0090 36: Reserved + DCD RSV21_IRQHandler ; 0x25 0x0094 37: Reserved + DCD RSV22_IRQHandler ; 0x26 0x0098 38: Reserved + DCD FLC0_IRQHandler ; 0x27 0x009C 39: Flash Controller 0 DCD GPIO0_IRQHandler ; 0x28 0x00A0 40: GPIO0 - DCD RSV12_IRQHandler ; 0x29 0x00A4 41: RSV12 - DCD RSV13_IRQHandler ; 0x2A 0x00A8 42: RSV13 - DCD RSV14_IRQHandler ; 0x2B 0x00AC 43: RSV14 + DCD GPIO1_IRQHandler ; 0x29 0x00A4 41: GPIO1 + DCD RSV26_IRQHandler ; 0x2A 0x00A8 42: Reserved + DCD RSV27_IRQHandler ; 0x2B 0x00AC 43: Reserved DCD DMA0_IRQHandler ; 0x2C 0x00B0 44: DMA0 DCD DMA1_IRQHandler ; 0x2D 0x00B4 45: DMA1 DCD DMA2_IRQHandler ; 0x2E 0x00B8 46: DMA2 DCD DMA3_IRQHandler ; 0x2F 0x00BC 47: DMA3 - DCD RSV15_IRQHandler ; 0x30 0x00C0 48: RSV15 - DCD RSV16_IRQHandler ; 0x31 0x00C4 49: RSV16 - DCD RSV17_IRQHandler ; 0x32 0x00C8 50: RSV17 - DCD RSV18_IRQHandler ; 0x33 0x00CC 51: RSV18 + DCD RSV32_IRQHandler ; 0x30 0x00C0 48: Reserved + DCD RSV33_IRQHandler ; 0x31 0x00C4 49: Reserved + DCD UART2_IRQHandler ; 0x32 0x00C8 50: UART 2 + DCD RSV35_IRQHandler ; 0x33 0x00CC 51: Reserved DCD I2C1_IRQHandler ; 0x34 0x00D0 52: I2C1 - DCD RSV19_IRQHandler ; 0x35 0x00D4 53: RSV19 - DCD RSV20_IRQHandler ; 0x36 0x00D8 54: RSV20 - DCD RSV21_IRQHandler ; 0x37 0x00DC 55: RSV21 - DCD RSV22_IRQHandler ; 0x38 0x00E0 56: RSV22 - DCD RSV23_IRQHandler ; 0x39 0x00E4 57: RSV23 - DCD RSV24_IRQHandler ; 0x3A 0x00E8 58: RSV24 - DCD RSV25_IRQHandler ; 0x3B 0x00EC 59: RSV25 - DCD RSV26_IRQHandler ; 0x3C 0x00F0 60: RSV26 - DCD RSV27_IRQHandler ; 0x3D 0x00F4 61: RSV27 - DCD RSV28_IRQHandler ; 0x3E 0x00F8 62: RSV28 - DCD RSV29_IRQHandler ; 0x3F 0x00FC 63: RSV29 - DCD RSV30_IRQHandler ; 0x40 0x0100 64: RSV30 - DCD RSV31_IRQHandler ; 0x41 0x0104 65: RSV31 - DCD RSV32_IRQHandler ; 0x42 0x0108 66: RSV32 - DCD RSV33_IRQHandler ; 0x43 0x010C 67: RSV33 - DCD RSV34_IRQHandler ; 0x44 0x0110 68: RSV34 - DCD RSV35_IRQHandler ; 0x45 0x0114 69: RSV35 - DCD GPIOWAKE_IRQHandler ; 0x46 0x0118 70: GPIO Wakeup + DCD RSV37_IRQHandler ; 0x35 0x00D4 53: Reserved + DCD RSV38_IRQHandler ; 0x36 0x00D8 54: Reserved + DCD RSV39_IRQHandler ; 0x37 0x00DC 55: Reserved + DCD RSV40_IRQHandler ; 0x38 0x00E0 56: Reserved + DCD RSV41_IRQHandler ; 0x39 0x00E4 57: Reserved + DCD RSV42_IRQHandler ; 0x3A 0x00E8 58: Reserved + DCD RSV43_IRQHandler ; 0x3B 0x00EC 59: Reserved + DCD RSV44_IRQHandler ; 0x3C 0x00F0 60: Reserved + DCD RSV45_IRQHandler ; 0x3D 0x00F4 61: Reserved + DCD RSV46_IRQHandler ; 0x3E 0x00F8 62: Reserved + DCD RSV47_IRQHandler ; 0x3F 0x00FC 63: Reserved + DCD RSV48_IRQHandler ; 0x40 0x0100 64: Reserved + DCD RSV49_IRQHandler ; 0x41 0x0104 65: Reserved + DCD RSV50_IRQHandler ; 0x42 0x0108 66: Reserved + DCD RSV51_IRQHandler ; 0x43 0x010C 67: Reserved + DCD RSV52_IRQHandler ; 0x44 0x0110 68: Reserved + DCD RSV53_IRQHandler ; 0x45 0x0114 69: Reserved + DCD RSV54_IRQHandler ; 0x46 0x0118 70: Reserved + DCD RSV55_IRQHandler ; 0x47 0x011C 71: Reserved + DCD RSV56_IRQHandler ; 0x48 0x0120 72: Reserved + DCD WDT1_IRQHandler ; 0x49 0x0124 73: Watchdog 1 + DCD RSV57_IRQHandler ; 0x4A 0x0128 74: Reserved + DCD RSV58_IRQHandler ; 0x4B 0x012C 75: Reserved + DCD RSV59_IRQHandler ; 0x4C 0x0130 76: Reserved + DCD RSV61_IRQHandler ; 0x4D 0x0134 77: Reserved + DCD I2C2_IRQHandler ; 0x4E 0x0138 78: Reserved + DCD RSV63_IRQHandler ; 0x4F 0x013C 79: Reserved + DCD RSV64_IRQHandler ; 0x50 0x0140 80: Reserved + DCD RSV65_IRQHandler ; 0x51 0x0144 81: Reserved + DCD RSV66_IRQHandler ; 0x52 0x0148 82: Reserved + DCD RSV67_IRQHandler ; 0x53 0x014C 83: Reserved + DCD DMA4_IRQHandler ; 0x54 0x0150 84: DMA4 + DCD DMA5_IRQHandler ; 0x55 0x0154 85: DMA5 + DCD DMA6_IRQHandler ; 0x56 0x0158 86: DMA6 + DCD DMA7_IRQHandler ; 0x57 0x015C 87: DMA7 + DCD DMA8_IRQHandler ; 0x58 0x0160 88: DMA8 + DCD DMA9_IRQHandler ; 0x59 0x0164 89: DMA9 + DCD DMA10_IRQHandler ; 0x5A 0x0168 90: DMA10 + DCD DMA11_IRQHandler ; 0x5B 0x016C 91: DMA11 + DCD DMA12_IRQHandler ; 0x5C 0x0170 92: DMA12 + DCD DMA13_IRQHandler ; 0x5D 0x0174 93: DMA13 + DCD DMA14_IRQHandler ; 0x5E 0x0178 94: DMA14 + DCD DMA15_IRQHandler ; 0x5F 0x017C 95: DMA15 + DCD RSV80_IRQHandler ; 0x60 0x0180 96: Reserved + DCD RSV81_IRQHandler ; 0x61 0x0184 97: Reserved + DCD ECC_IRQHandler ; 0x62 0x0188 98: Error Correction + DCD RSV83_IRQHandler ; 0x63 0x018C 99: Reserved + DCD RSV84_IRQHandler ; 0x64 0x0190 100: Reserved + DCD RSV85_IRQHandler ; 0x65 0x0194 101: Reserved + DCD RSV86_IRQHandler ; 0x66 0x0198 102: Reserved + DCD RSV87_IRQHandler ; 0x67 0x019C 103: Reserved + DCD UART3_IRQHandler ; 0x68 0x01A0 104: UART 3 + DCD RSV89_IRQHandler ; 0x69 0x01A4 105: Reserved + DCD RSV90_IRQHandler ; 0x6A 0x01A8 106: UART 5 + DCD RSV91_IRQHandler ; 0x6B 0x01AC 107: Reserved + DCD RSV92_IRQHandler ; 0x6C 0x01B0 108: Reserved + DCD RSV93_IRQHandler ; 0x6D 0x01B1 109: Reserved + DCD RSV94_IRQHandler ; 0x6E 0x01B2 109: Reserved + DCD RSV95_IRQHandler ; 0x6D 0x01B1 109: Reserved + DCD RSV96_IRQHandler ; 0x6E 0x01B2 109: Reserved + DCD AES_IRQHandler ; 0x6D 0x01B1 109: AES + DCD CRC_IRQHandler ; 0x6E 0x01B2 109: CRC + DCD I2S_IRQHandler ; 0x6E 0x01B2 109: I2S __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors @@ -185,119 +230,208 @@ ENDP Default_Handler PROC - ; MAX32660 interrupts + ; MAX32670 interrupts EXPORT PF_IRQHandler [WEAK] ; 0x10 0x0040 16: Power Fail EXPORT WDT0_IRQHandler [WEAK] ; 0x11 0x0044 17: Watchdog 0 - EXPORT RSV00_IRQHandler [WEAK] ; 0x12 0x0048 18: RSV00 + EXPORT RSV02_IRQHandler [WEAK] ; 0x12 0x0048 18: Reserved EXPORT RTC_IRQHandler [WEAK] ; 0x13 0x004C 19: RTC - EXPORT RSV01_IRQHandler [WEAK] ; 0x14 0x0050 20: RSV01 + EXPORT TRNG_IRQHandler [WEAK] ; 0x14 0x0050 20: True Random Number Gener EXPORT TMR0_IRQHandler [WEAK] ; 0x15 0x0054 21: Timer 0 EXPORT TMR1_IRQHandler [WEAK] ; 0x16 0x0058 22: Timer 1 EXPORT TMR2_IRQHandler [WEAK] ; 0x17 0x005C 23: Timer 2 - EXPORT RSV02_IRQHandler [WEAK] ; 0x18 0x0060 24: RSV02 - EXPORT RSV03_IRQHandler [WEAK] ; 0x19 0x0064 25: RSV03 - EXPORT RSV04_IRQHandler [WEAK] ; 0x1A 0x0068 26: RSV04 - EXPORT RSV05_IRQHandler [WEAK] ; 0x1B 0x006C 27: RSV05 - EXPORT RSV06_IRQHandler [WEAK] ; 0x1C 0x0070 28: RSV06 + EXPORT TMR3_IRQHandler [WEAK] ; 0x18 0x0060 24: Timer 3 + EXPORT TMR4_IRQHandler [WEAK] ; 0x19 0x0064 25: Timer 4 + EXPORT TMR5_IRQHandler [WEAK] ; 0x1A 0x0068 26: Timer 5 + EXPORT RSV11_IRQHandler [WEAK] ; 0x1B 0x006C 27: Reserved + EXPORT RSV12_IRQHandler [WEAK] ; 0x1C 0x0070 28: Reserved EXPORT I2C0_IRQHandler [WEAK] ; 0x1D 0x0074 29: I2C0 EXPORT UART0_IRQHandler [WEAK] ; 0x1E 0x0078 30: UART 0 EXPORT UART1_IRQHandler [WEAK] ; 0x1F 0x007C 31: UART 1 - EXPORT SPI0_IRQHandler [WEAK] ; 0x20 0x0080 32: SPIY17 - EXPORT SPI1_IRQHandler [WEAK] ; 0x21 0x0084 33: SPIMSS - EXPORT RSV07_IRQHandler [WEAK] ; 0x22 0x0088 34: RSV07 - EXPORT RSV08_IRQHandler [WEAK] ; 0x23 0x008C 35: RSV08 - EXPORT RSV09_IRQHandler [WEAK] ; 0x24 0x0090 36: RSV09 - EXPORT RSV10_IRQHandler [WEAK] ; 0x25 0x0094 37: RSV10 - EXPORT RSV11_IRQHandler [WEAK] ; 0x26 0x0098 38: RSV11 - EXPORT FLC_IRQHandler [WEAK] ; 0x27 0x009C 39: FLC + EXPORT SPI0_IRQHandler [WEAK] ; 0x20 0x0080 32: SPI0 + EXPORT SPI1_IRQHandler [WEAK] ; 0x21 0x0084 33: SPI1 + EXPORT SPI2_IRQHandler [WEAK] ; 0x22 0x0088 34: SPI2 + EXPORT RSV19_IRQHandler [WEAK] ; 0x23 0x008C 35: Reserved + EXPORT RSV20_IRQHandler [WEAK] ; 0x24 0x0090 36: Reserved + EXPORT RSV21_IRQHandler [WEAK] ; 0x25 0x0094 37: Reserved + EXPORT RSV22_IRQHandler [WEAK] ; 0x26 0x0098 38: Reserved + EXPORT FLC0_IRQHandler [WEAK] ; 0x27 0x009C 39: Flash Controller 0 EXPORT GPIO0_IRQHandler [WEAK] ; 0x28 0x00A0 40: GPIO0 - EXPORT RSV12_IRQHandler [WEAK] ; 0x29 0x00A4 41: RSV12 - EXPORT RSV13_IRQHandler [WEAK] ; 0x2A 0x00A8 42: RSV13 - EXPORT RSV14_IRQHandler [WEAK] ; 0x2B 0x00AC 43: RSV14 + EXPORT GPIO1_IRQHandler [WEAK] ; 0x29 0x00A4 41: GPIO1 + EXPORT RSV26_IRQHandler [WEAK] ; 0x2A 0x00A8 42: Reserved + EXPORT RSV27_IRQHandler [WEAK] ; 0x2B 0x00AC 43: Reserved EXPORT DMA0_IRQHandler [WEAK] ; 0x2C 0x00B0 44: DMA0 EXPORT DMA1_IRQHandler [WEAK] ; 0x2D 0x00B4 45: DMA1 EXPORT DMA2_IRQHandler [WEAK] ; 0x2E 0x00B8 46: DMA2 EXPORT DMA3_IRQHandler [WEAK] ; 0x2F 0x00BC 47: DMA3 - EXPORT RSV15_IRQHandler [WEAK] ; 0x30 0x00C0 48: RSV15 - EXPORT RSV16_IRQHandler [WEAK] ; 0x31 0x00C4 49: RSV16 - EXPORT RSV17_IRQHandler [WEAK] ; 0x32 0x00C8 50: RSV17 - EXPORT RSV18_IRQHandler [WEAK] ; 0x33 0x00CC 51: RSV18 + EXPORT RSV32_IRQHandler [WEAK] ; 0x30 0x00C0 48: Reserved + EXPORT RSV33_IRQHandler [WEAK] ; 0x31 0x00C4 49: Reserved + EXPORT UART2_IRQHandler [WEAK] ; 0x32 0x00C8 50: UART 2 + EXPORT RSV35_IRQHandler [WEAK] ; 0x33 0x00CC 51: Reserved EXPORT I2C1_IRQHandler [WEAK] ; 0x34 0x00D0 52: I2C1 - EXPORT RSV19_IRQHandler [WEAK] ; 0x35 0x00D4 53: RSV19 - EXPORT RSV20_IRQHandler [WEAK] ; 0x36 0x00D8 54: RSV20 - EXPORT RSV21_IRQHandler [WEAK] ; 0x37 0x00DC 55: RSV21 - EXPORT RSV22_IRQHandler [WEAK] ; 0x38 0x00E0 56: RSV22 - EXPORT RSV23_IRQHandler [WEAK] ; 0x39 0x00E4 57: RSV23 - EXPORT RSV24_IRQHandler [WEAK] ; 0x3A 0x00E8 58: RSV24 - EXPORT RSV25_IRQHandler [WEAK] ; 0x3B 0x00EC 59: RSV25 - EXPORT RSV26_IRQHandler [WEAK] ; 0x3C 0x00F0 60: RSV26 - EXPORT RSV27_IRQHandler [WEAK] ; 0x3D 0x00F4 61: RSV27 - EXPORT RSV28_IRQHandler [WEAK] ; 0x3E 0x00F8 62: RSV28 - EXPORT RSV29_IRQHandler [WEAK] ; 0x3F 0x00FC 63: RSV29 - EXPORT RSV30_IRQHandler [WEAK] ; 0x40 0x0100 64: RSV30 - EXPORT RSV31_IRQHandler [WEAK] ; 0x41 0x0104 65: RSV31 - EXPORT RSV32_IRQHandler [WEAK] ; 0x42 0x0108 66: RSV32 - EXPORT RSV33_IRQHandler [WEAK] ; 0x43 0x010C 67: RSV33 - EXPORT RSV34_IRQHandler [WEAK] ; 0x44 0x0110 68: RSV34 - EXPORT RSV35_IRQHandler [WEAK] ; 0x45 0x0114 69: RSV35 - EXPORT GPIOWAKE_IRQHandler [WEAK] ; 0x46 0x0118 70: GPIO Wakeup + EXPORT RSV37_IRQHandler [WEAK] ; 0x35 0x00D4 53: Reserved + EXPORT RSV38_IRQHandler [WEAK] ; 0x36 0x00D8 54: Reserved + EXPORT RSV39_IRQHandler [WEAK] ; 0x37 0x00DC 55: Reserved + EXPORT RSV40_IRQHandler [WEAK] ; 0x38 0x00E0 56: Reserved + EXPORT RSV41_IRQHandler [WEAK] ; 0x39 0x00E4 57: Reserved + EXPORT RSV42_IRQHandler [WEAK] ; 0x3A 0x00E8 58: BTLE Reserved + EXPORT RSV43_IRQHandler [WEAK] ; 0x3B 0x00EC 59: Reserved + EXPORT RSV44_IRQHandler [WEAK] ; 0x3C 0x00F0 60: Reserved + EXPORT RSV45_IRQHandler [WEAK] ; 0x3D 0x00F4 61: Reserved + EXPORT RSV46_IRQHandler [WEAK] ; 0x3E 0x00F8 62: Reserved + EXPORT RSV47_IRQHandler [WEAK] ; 0x3F 0x00FC 63: Reserved + EXPORT RSV48_IRQHandler [WEAK] ; 0x40 0x0100 64: Reserved + EXPORT RSV49_IRQHandler [WEAK] ; 0x41 0x0104 65: Reserved + EXPORT RSV50_IRQHandler [WEAK] ; 0x42 0x0108 66: Reserved + EXPORT RSV51_IRQHandler [WEAK] ; 0x43 0x010C 67: BReserved + EXPORT RSV52_IRQHandler [WEAK] ; 0x44 0x0110 68: Reserved + EXPORT RSV53_IRQHandler [WEAK] ; 0x45 0x0114 69: Reserved + EXPORT RSV54_IRQHandler [WEAK] ; 0x46 0x0118 70: Reserved + EXPORT RSV55_IRQHandler [WEAK] ; 0x47 0x011C 71: Reserved + EXPORT RSV56_IRQHandler [WEAK] ; 0x48 0x0120 72: Reserved + EXPORT WDT1_IRQHandler [WEAK] ; 0x49 0x0124 73: Watchdog 1 + EXPORT RSV57_IRQHandler [WEAK] ; 0x4A 0x0128 74: Reserved + EXPORT RSV58_IRQHandler [WEAK] ; 0x4B 0x012C 75: Reserved + EXPORT RSV59_IRQHandler [WEAK] ; 0x4C 0x0130 76: Reserved + EXPORT RSV61_IRQHandler [WEAK] ; 0x4D 0x0134 77: Reserved + EXPORT I2C2_IRQHandler [WEAK] ; 0x4E 0x0138 78: I2C 1 + EXPORT RSV63_IRQHandler [WEAK] ; 0x4F 0x013C 79: Reserved + EXPORT RSV64_IRQHandler [WEAK] ; 0x50 0x0140 80: Reserved + EXPORT RSV65_IRQHandler [WEAK] ; 0x51 0x0144 81: Reserved + EXPORT RSV66_IRQHandler [WEAK] ; 0x52 0x0148 82: Reserved + EXPORT RSV67_IRQHandler [WEAK] ; 0x53 0x014C 83: Reserved + EXPORT DMA4_IRQHandler [WEAK] ; 0x54 0x0150 84: DMA4 + EXPORT DMA5_IRQHandler [WEAK] ; 0x55 0x0154 85: DMA5 + EXPORT DMA6_IRQHandler [WEAK] ; 0x56 0x0158 86: DMA6 + EXPORT DMA7_IRQHandler [WEAK] ; 0x57 0x015C 87: DMA7 + EXPORT DMA8_IRQHandler [WEAK] ; 0x58 0x0160 88: DMA8 + EXPORT DMA9_IRQHandler [WEAK] ; 0x59 0x0164 89: DMA9 + EXPORT DMA10_IRQHandler [WEAK] ; 0x5A 0x0168 90: DMA10 + EXPORT DMA11_IRQHandler [WEAK] ; 0x5B 0x016C 91: DMA11 + EXPORT DMA12_IRQHandler [WEAK] ; 0x5C 0x0170 92: DMA12 + EXPORT DMA13_IRQHandler [WEAK] ; 0x5D 0x0174 93: DMA13 + EXPORT DMA14_IRQHandler [WEAK] ; 0x5E 0x0178 94: DMA14 + EXPORT DMA15_IRQHandler [WEAK] ; 0x5F 0x017C 95: DMA15 + EXPORT RSV80_IRQHandler [WEAK] ; 0x60 0x0180 96: Reserved + EXPORT RSV81_IRQHandler [WEAK] ; 0x61 0x0184 97: Reserved + EXPORT ECC_IRQHandler [WEAK] ; 0x62 0x0188 98: Error Correction + EXPORT RSV83_IRQHandler [WEAK] ; 0x63 0x018C 99: Reserved + EXPORT RSV84_IRQHandler [WEAK] ; 0x64 0x0190 100: Reserved + EXPORT RSV85_IRQHandler [WEAK] ; 0x65 0x0194 101: Reserved + EXPORT RSV86_IRQHandler [WEAK] ; 0x66 0x0198 102: Reserved + EXPORT RSV87_IRQHandler [WEAK] ; 0x67 0x019C 103: Reserved + EXPORT UART3_IRQHandler [WEAK] ; 0x68 0x01A0 104: UART 3 + EXPORT RSV89_IRQHandler [WEAK] ; 0x69 0x01A4 105: Reserved + EXPORT RSV90_IRQHandler [WEAK] ; 0x6A 0x01A8 106: Reserved + EXPORT RSV91_IRQHandler [WEAK] ; 0x6B 0x01AC 107: Reserved + EXPORT RSV92_IRQHandler [WEAK] ; 0x6C 0x01B0 108: Reserved + EXPORT RSV93_IRQHandler [WEAK] ; 0x6D 0x01B4 109: Reserved + EXPORT RSV94_IRQHandler [WEAK] ; 0x6E 0x01B8 110: Reserved + EXPORT RSV95_IRQHandler [WEAK] ; 0x6F 0x01B1 109: Reserved + EXPORT RSV96_IRQHandler [WEAK] ; 0x70 0x01B2 109: Reserved + EXPORT AES_IRQHandler [WEAK] ; 0x71 0x01B1 109: AES + EXPORT CRC_IRQHandler [WEAK] ; 0x72 0x01B2 109: CRC + EXPORT I2S_IRQHandler [WEAK] ; 0x73 0x01B2 109: I2S PF_IRQHandler ; 0x10 0x0040 16: Power Fail WDT0_IRQHandler ; 0x11 0x0044 17: Watchdog 0 -RSV00_IRQHandler ; 0x12 0x0048 18: RSV00 +RSV02_IRQHandler ; 0x12 0x0048 18: Reserved RTC_IRQHandler ; 0x13 0x004C 19: RTC -RSV01_IRQHandler ; 0x14 0x0050 20: RSV01 +TRNG_IRQHandler ; 0x14 0x0050 20: True Random Number Gener TMR0_IRQHandler ; 0x15 0x0054 21: Timer 0 TMR1_IRQHandler ; 0x16 0x0058 22: Timer 1 TMR2_IRQHandler ; 0x17 0x005C 23: Timer 2 -RSV02_IRQHandler ; 0x18 0x0060 24: RSV02 -RSV03_IRQHandler ; 0x19 0x0064 25: RSV03 -RSV04_IRQHandler ; 0x1A 0x0068 26: RSV04 -RSV05_IRQHandler ; 0x1B 0x006C 27: RSV05 -RSV06_IRQHandler ; 0x1C 0x0070 28: RSV06 +TMR3_IRQHandler ; 0x18 0x0060 24: Timer 3 +TMR4_IRQHandler ; 0x19 0x0064 25: Timer 4 +TMR5_IRQHandler ; 0x1A 0x0068 26: Timer 5 +RSV11_IRQHandler ; 0x1B 0x006C 27: Reserved +RSV12_IRQHandler ; 0x1C 0x0070 28: Reserved I2C0_IRQHandler ; 0x1D 0x0074 29: I2C0 UART0_IRQHandler ; 0x1E 0x0078 30: UART 0 UART1_IRQHandler ; 0x1F 0x007C 31: UART 1 SPI0_IRQHandler ; 0x20 0x0080 32: SPI0 SPI1_IRQHandler ; 0x21 0x0084 33: SPI1 -RSV07_IRQHandler ; 0x22 0x0088 34: RSV07 -RSV08_IRQHandler ; 0x23 0x008C 35: RSV08 -RSV09_IRQHandler ; 0x24 0x0090 36: RSV09 -RSV10_IRQHandler ; 0x25 0x0094 37: RSV10 -RSV11_IRQHandler ; 0x26 0x0098 38: RSV11 -FLC_IRQHandler ; 0x27 0x009C 39: FLC +SPI2_IRQHandler ; 0x22 0x0088 34: SPI2 +RSV19_IRQHandler ; 0x23 0x008C 35: Reserved +RSV20_IRQHandler ; 0x24 0x0090 36: Reserved +RSV21_IRQHandler ; 0x25 0x0094 37: Reserved +RSV22_IRQHandler ; 0x26 0x0098 38: Reserved +FLC0_IRQHandler ; 0x27 0x009C 39: Flash Controller 0 GPIO0_IRQHandler ; 0x28 0x00A0 40: GPIO0 -RSV12_IRQHandler ; 0x29 0x00A4 41: RSV12 -RSV13_IRQHandler ; 0x2A 0x00A8 42: RSV13 -RSV14_IRQHandler ; 0x2B 0x00AC 43: RSV14 +GPIO1_IRQHandler ; 0x29 0x00A4 41: GPIO1 +RSV26_IRQHandler ; 0x2A 0x00A8 42: Reserved +RSV27_IRQHandler ; 0x2B 0x00AC 43: Reserved DMA0_IRQHandler ; 0x2C 0x00B0 44: DMA0 DMA1_IRQHandler ; 0x2D 0x00B4 45: DMA1 DMA2_IRQHandler ; 0x2E 0x00B8 46: DMA2 DMA3_IRQHandler ; 0x2F 0x00BC 47: DMA3 -RSV15_IRQHandler ; 0x30 0x00C0 48: RSV15 -RSV16_IRQHandler ; 0x31 0x00C4 49: RSV16 -RSV17_IRQHandler ; 0x32 0x00C8 50: RSV17 -RSV18_IRQHandler ; 0x33 0x00CC 51: RSV18 +RSV32_IRQHandler ; 0x30 0x00C0 48: Reserved +RSV33_IRQHandler ; 0x31 0x00C4 49: Reserved +UART2_IRQHandler ; 0x32 0x00C8 50: UART 2 +RSV35_IRQHandler ; 0x33 0x00CC 51: Reserved I2C1_IRQHandler ; 0x34 0x00D0 52: I2C1 -RSV19_IRQHandler ; 0x35 0x00D4 53: RSV19 -RSV20_IRQHandler ; 0x36 0x00D8 54: RSV20 -RSV21_IRQHandler ; 0x37 0x00DC 55: RSV21 -RSV22_IRQHandler ; 0x38 0x00E0 56: RSV22 -RSV23_IRQHandler ; 0x39 0x00E4 57: RSV23 -RSV24_IRQHandler ; 0x3A 0x00E8 58: RSV24 -RSV25_IRQHandler ; 0x3B 0x00EC 59: RSV25 -RSV26_IRQHandler ; 0x3C 0x00F0 60: RSV26 -RSV27_IRQHandler ; 0x3D 0x00F4 61: RSV27 -RSV28_IRQHandler ; 0x3E 0x00F8 62: RSV28 -RSV29_IRQHandler ; 0x3F 0x00FC 63: RSV29 -RSV30_IRQHandler ; 0x40 0x0100 64: RSV30 -RSV31_IRQHandler ; 0x41 0x0104 65: RSV31 -RSV32_IRQHandler ; 0x42 0x0108 66: RSV32 -RSV33_IRQHandler ; 0x43 0x010C 67: RSV33 -RSV34_IRQHandler ; 0x44 0x0110 68: RSV34 -RSV35_IRQHandler ; 0x45 0x0114 69: RSV35 -GPIOWAKE_IRQHandler ; 0x46 0x0118 70: GPIO Wakeup - +RSV37_IRQHandler ; 0x35 0x00D4 53: Reserved +RSV38_IRQHandler ; 0x36 0x00D8 54: Reserved +RSV39_IRQHandler ; 0x37 0x00DC 55: Reserved +RSV40_IRQHandler ; 0x38 0x00E0 56: Reserved +RSV41_IRQHandler ; 0x39 0x00E4 57: Reserved +RSV42_IRQHandler ; 0x3A 0x00E8 58: BTLE Reserved +RSV43_IRQHandler ; 0x3B 0x00EC 59: Reserved +RSV44_IRQHandler ; 0x3C 0x00F0 60: Reserved +RSV45_IRQHandler ; 0x3D 0x00F4 61: Reserved +RSV46_IRQHandler ; 0x3E 0x00F8 62: Reserved +RSV47_IRQHandler ; 0x3F 0x00FC 63: Reserved +RSV48_IRQHandler ; 0x40 0x0100 64: Reserved +RSV49_IRQHandler ; 0x41 0x0104 65: Reserved +RSV50_IRQHandler ; 0x42 0x0108 66: Reserved +RSV51_IRQHandler ; 0x43 0x010C 67: BReserved +RSV52_IRQHandler ; 0x44 0x0110 68: Reserved +RSV53_IRQHandler ; 0x45 0x0114 69: Reserved +RSV54_IRQHandler ; 0x46 0x0118 70: Reserved +RSV55_IRQHandler ; 0x47 0x011C 71: Reserved +RSV56_IRQHandler ; 0x48 0x0120 72: Reserved +WDT1_IRQHandler ; 0x49 0x0124 73: Watchdog 1 +RSV57_IRQHandler ; 0x4A 0x0128 74: Reserved +RSV58_IRQHandler ; 0x4B 0x012C 75: Reserved +RSV59_IRQHandler ; 0x4C 0x0130 76: Reserved +RSV61_IRQHandler ; 0x4D 0x0134 77: Reserved +I2C2_IRQHandler ; 0x4E 0x0138 78: I2C 1 +RSV63_IRQHandler ; 0x4F 0x013C 79: Reserved +RSV64_IRQHandler ; 0x50 0x0140 80: Reserved +RSV65_IRQHandler ; 0x51 0x0144 81: Reserved +RSV66_IRQHandler ; 0x52 0x0148 82: Reserved +RSV67_IRQHandler ; 0x53 0x014C 83: Reserved +DMA4_IRQHandler ; 0x54 0x0150 84: DMA4 +DMA5_IRQHandler ; 0x55 0x0154 85: DMA5 +DMA6_IRQHandler ; 0x56 0x0158 86: DMA6 +DMA7_IRQHandler ; 0x57 0x015C 87: DMA7 +DMA8_IRQHandler ; 0x58 0x0160 88: DMA8 +DMA9_IRQHandler ; 0x59 0x0164 89: DMA9 +DMA10_IRQHandler ; 0x5A 0x0168 90: DMA10 +DMA11_IRQHandler ; 0x5B 0x016C 91: DMA11 +DMA12_IRQHandler ; 0x5C 0x0170 92: DMA12 +DMA13_IRQHandler ; 0x5D 0x0174 93: DMA13 +DMA14_IRQHandler ; 0x5E 0x0178 94: DMA14 +DMA15_IRQHandler ; 0x5F 0x017C 95: DMA15 +RSV80_IRQHandler ; 0x60 0x0180 96: Reserved +RSV81_IRQHandler ; 0x61 0x0184 97: Reserved +ECC_IRQHandler ; 0x62 0x0188 98: Error Correction +RSV83_IRQHandler ; 0x63 0x018C 99: Reserved +RSV84_IRQHandler ; 0x64 0x0190 100: Reserved +RSV85_IRQHandler ; 0x65 0x0194 101: Reserved +RSV86_IRQHandler ; 0x66 0x0198 102: Reserved +RSV87_IRQHandler ; 0x67 0x019C 103: Reserved +UART3_IRQHandler ; 0x68 0x01A0 104: UART 3 +RSV89_IRQHandler ; 0x69 0x01A4 105: Reserved +RSV90_IRQHandler ; 0x6A 0x01A8 106: Reserved +RSV91_IRQHandler ; 0x6B 0x01AC 107: Reserved +RSV92_IRQHandler ; 0x6C 0x01B0 108: Reserved +RSV93_IRQHandler ; 0x6D 0x01B4 109: Reserved +RSV94_IRQHandler ; 0x6E 0x01B8 110: Reserved +RSV95_IRQHandler ; 0x6F 0x01B1 109: Reserved +RSV96_IRQHandler ; 0x70 0x01B2 109: Reserved +AES_IRQHandler ; 0x71 0x01B1 109: AES +CRC_IRQHandler ; 0x72 0x01B2 109: CRC +I2S_IRQHandler ; 0x73 0x01B2 109: I2S B . ENDP diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_GCC_ARM/startup_max32670.S b/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_GCC_ARM/startup_max32670.S index fa0cb61..eb5efd1 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_GCC_ARM/startup_max32670.S +++ b/targets/TARGET_Maxim/TARGET_MAX32670/device/TOOLCHAIN_GCC_ARM/startup_max32670.S @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -92,59 +92,104 @@ /* Device-specific Interrupts */ .long PF_IRQHandler /* 0x10 0x0040 16: Power Fail */ .long WDT0_IRQHandler /* 0x11 0x0044 17: Watchdog 0 */ - .long RSV00_IRQHandler /* 0x12 0x0048 18: RSV00 */ + .long RSV02_IRQHandler /* 0x12 0x0048 18: Reserved */ .long RTC_IRQHandler /* 0x13 0x004C 19: RTC */ - .long RSV1_IRQHandler /* 0x14 0x0050 20: RSV1 */ + .long TRNG_IRQHandler /* 0x14 0x0050 20: True Random Number Generator */ .long TMR0_IRQHandler /* 0x15 0x0054 21: Timer 0 */ .long TMR1_IRQHandler /* 0x16 0x0058 22: Timer 1 */ .long TMR2_IRQHandler /* 0x17 0x005C 23: Timer 2 */ - .long RSV02_IRQHandler /* 0x18 0x0060 24: RSV02 */ - .long RSV03_IRQHandler /* 0x19 0x0064 25: RSV03 */ - .long RSV04_IRQHandler /* 0x1A 0x0068 26: RSV04 */ - .long RSV05_IRQHandler /* 0x1B 0x006C 27: RSV05 */ - .long RSV06_IRQHandler /* 0x1C 0x0070 28: RSV06 */ + .long TMR3_IRQHandler /* 0x18 0x0060 24: Timer 3 */ + .long TMR4_IRQHandler /* 0x19 0x0064 25: Timer 4 */ + .long TMR5_IRQHandler /* 0x1A 0x0068 26: Timer 5 */ + .long RSV11_IRQHandler /* 0x1B 0x006C 27: Reserved */ + .long RSV12_IRQHandler /* 0x1C 0x0070 28: Reserved */ .long I2C0_IRQHandler /* 0x1D 0x0074 29: I2C0 */ .long UART0_IRQHandler /* 0x1E 0x0078 30: UART 0 */ .long UART1_IRQHandler /* 0x1F 0x007C 31: UART 1 */ - .long SPI0_IRQHandler /* 0x20 0x0080 32: SPIY17 */ - .long SPI1_IRQHandler /* 0x21 0x0084 33: SPIMSS */ - .long RSV07_IRQHandler /* 0x22 0x0088 34: RSV07 */ - .long RSV08_IRQHandler /* 0x23 0x008C 35: RSV08 */ - .long RSV09_IRQHandler /* 0x24 0x0090 36: RSV09 */ - .long RSV10_IRQHandler /* 0x25 0x0094 37: RSV10 */ - .long RSV11_IRQHandler /* 0x26 0x0098 38: RSV11 */ - .long FLC_IRQHandler /* 0x27 0x009C 39: FLC */ + .long SPI0_IRQHandler /* 0x20 0x0080 32: SPI0 */ + .long SPI1_IRQHandler /* 0x21 0x0084 33: SPI1 */ + .long SPI2_IRQHandler /* 0x22 0x0088 34: SPI2 */ + .long RSV19_IRQHandler /* 0x23 0x008C 35: Reserved */ + .long RSV20_IRQHandler /* 0x24 0x0090 36: Reserved */ + .long RSV21_IRQHandler /* 0x25 0x0094 37: Reserved */ + .long RSV22_IRQHandler /* 0x26 0x0098 38: Magstripe DSP */ + .long FLC0_IRQHandler /* 0x27 0x009C 39: Flash Controller 0 */ .long GPIO0_IRQHandler /* 0x28 0x00A0 40: GPIO0 */ - .long RSV12_IRQHandler /* 0x29 0x00A4 41: RSV12 */ - .long RSV13_IRQHandler /* 0x2A 0x00A8 42: RSV13 */ - .long RSV14_IRQHandler /* 0x2B 0x00AC 43: RSV14 */ + .long GPIO1_IRQHandler /* 0x29 0x00A4 41: GPIO2 */ + .long RSV26_IRQHandler /* 0x2A 0x00A8 42: GPIO3 */ + .long RSV27_IRQHandler /* 0x2B 0x00AC 43: Crypto */ .long DMA0_IRQHandler /* 0x2C 0x00B0 44: DMA0 */ .long DMA1_IRQHandler /* 0x2D 0x00B4 45: DMA1 */ .long DMA2_IRQHandler /* 0x2E 0x00B8 46: DMA2 */ .long DMA3_IRQHandler /* 0x2F 0x00BC 47: DMA3 */ - .long RSV15_IRQHandler /* 0x30 0x00C0 48: RSV15 */ - .long RSV16_IRQHandler /* 0x31 0x00C4 49: RSV16 */ - .long RSV17_IRQHandler /* 0x32 0x00C8 50: RSV17 */ - .long RSV18_IRQHandler /* 0x33 0x00CC 51: RSV18 */ + .long RSV32_IRQHandler /* 0x30 0x00C0 48: Reserved */ + .long RSV33_IRQHandler /* 0x31 0x00C4 49: Reserved */ + .long UART2_IRQHandler /* 0x32 0x00C8 50: UART 2 */ + .long RSV35_IRQHandler /* 0x33 0x00CC 51: Contactless Link Control */ .long I2C1_IRQHandler /* 0x34 0x00D0 52: I2C1 */ - .long RSV19_IRQHandler /* 0x35 0x00D4 53: RSV19 */ - .long RSV20_IRQHandler /* 0x36 0x00D8 54: RSV20 */ - .long RSV21_IRQHandler /* 0x37 0x00DC 55: RSV21 */ - .long RSV22_IRQHandler /* 0x38 0x00E0 56: RSV22 */ - .long RSV23_IRQHandler /* 0x39 0x00E4 57: RSV23 */ - .long RSV24_IRQHandler /* 0x3A 0x00E8 58: RSV24 */ - .long RSV25_IRQHandler /* 0x3B 0x00EC 59: RSV25 */ - .long RSV26_IRQHandler /* 0x3C 0x00F0 60: RSV26 */ - .long RSV27_IRQHandler /* 0x3D 0x00F4 61: RSV27 */ - .long RSV28_IRQHandler /* 0x3E 0x00F8 62: RSV28 */ - .long RSV29_IRQHandler /* 0x3F 0x00FC 63: RSV29 */ - .long RSV30_IRQHandler /* 0x40 0x0100 64: RSV30 */ - .long RSV31_IRQHandler /* 0x41 0x0104 65: RSV31 */ - .long RSV32_IRQHandler /* 0x42 0x0108 66: RSV32 */ - .long RSV33_IRQHandler /* 0x43 0x010C 67: RSV33 */ - .long RSV34_IRQHandler /* 0x44 0x0110 68: RSV34 */ - .long RSV35_IRQHandler /* 0x45 0x0114 69: RSV35 */ - .long GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIO Wakeup */ + .long RSV37_IRQHandler /* 0x35 0x00D4 53: Smart Card 1 */ + .long RSV38_IRQHandler /* 0x36 0x00D8 54: Reserved */ + .long RSV39_IRQHandler /* 0x37 0x00DC 55: Reserved */ + .long RSV40_IRQHandler /* 0x38 0x00E0 56: Reserved */ + .long RSV41_IRQHandler /* 0x39 0x00E4 57: Reserved */ + .long RSV42_IRQHandler /* 0x3A 0x00E8 58: Reserved */ + .long RSV43_IRQHandler /* 0x3B 0x00EC 59: Reserved */ + .long RSV44_IRQHandler /* 0x3C 0x00F0 60: Reserved */ + .long RSV45_IRQHandler /* 0x3D 0x00F4 61: Reserved */ + .long RSV46_IRQHandler /* 0x3E 0x00F8 62: Reserved */ + .long RSV47_IRQHandler /* 0x3F 0x00FC 63: Reserved */ + .long RSV48_IRQHandler /* 0x40 0x0100 64: Reserved */ + .long RSV49_IRQHandler /* 0x41 0x0104 65: Reserved */ + .long RSV50_IRQHandler /* 0x42 0x0108 66: Reserved */ + .long RSV51_IRQHandler /* 0x43 0x010C 67: Reserved */ + .long RSV52_IRQHandler /* 0x44 0x0110 68: Reserved */ + .long RSV53_IRQHandler /* 0x45 0x0114 69: Reserved */ + .long GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIOWAKE */ + .long RSV55_IRQHandler /* 0x47 0x011C 71: Reserved */ + .long RSV56_IRQHandler /* 0x48 0x0120 72: Reserved */ + .long WDT1_IRQHandler /* 0x49 0x0124 73: Watchdog 1 */ + .long RSV57_IRQHandler /* 0x4A 0x0128 74: Reserved */ + .long RSV58_IRQHandler /* 0x4B 0x012C 75: Reserved */ + .long RSV59_IRQHandler /* 0x4C 0x0130 76: Reserved */ + .long RSV61_IRQHandler /* 0x4D 0x0134 77: Reserved */ + .long I2C2_IRQHandler /* 0x4E 0x0138 78: I2C 2 */ + .long RSV63_IRQHandler /* 0x4F 0x013C 79: Reserved */ + .long RSV64_IRQHandler /* 0x50 0x0140 80: Reserved */ + .long RSV65_IRQHandler /* 0x51 0x0144 81: Reserved */ + .long RSV66_IRQHandler /* 0x52 0x0148 82: Reserved */ + .long RSV67_IRQHandler /* 0x53 0x014C 83: Reserved */ + .long DMA4_IRQHandler /* 0x54 0x0150 84: DMA4 */ + .long DMA5_IRQHandler /* 0x55 0x0154 85: DMA5 */ + .long DMA6_IRQHandler /* 0x56 0x0158 86: DMA6 */ + .long DMA7_IRQHandler /* 0x57 0x015C 87: DMA7 */ + .long DMA8_IRQHandler /* 0x58 0x0160 88: DMA8 */ + .long DMA9_IRQHandler /* 0x59 0x0164 89: DMA9 */ + .long DMA10_IRQHandler /* 0x5A 0x0168 90: DMA10 */ + .long DMA11_IRQHandler /* 0x5B 0x016C 91: DMA11 */ + .long DMA12_IRQHandler /* 0x5C 0x0170 92: DMA12 */ + .long DMA13_IRQHandler /* 0x5D 0x0174 93: DMA13 */ + .long DMA14_IRQHandler /* 0x5E 0x0178 94: DMA14 */ + .long DMA15_IRQHandler /* 0x5F 0x017C 95: DMA15 */ + .long RSV80_IRQHandler /* 0x60 0x0180 96: Reserved */ + .long RSV81_IRQHandler /* 0x61 0x0184 97: Reserved */ + .long ECC_IRQHandler /* 0x62 0x0188 98: Error Correction */ + .long RSV83_IRQHandler /* 0x63 0x018C 99: Reserved */ + .long RSV84_IRQHandler /* 0x64 0x0190 100: Reserved */ + .long RSV85_IRQHandler /* 0x65 0x0194 101: Reserved */ + .long RSV86_IRQHandler /* 0x66 0x0198 102: Reserved */ + .long RSV87_IRQHandler /* 0x67 0x019C 103: Reserved */ + .long UART3_IRQHandler /* 0x68 0x01A0 104: UART 3 */ + .long RSV89_IRQHandler /* 0x69 0x01A4 105: Reserved */ + .long RSV90_IRQHandler /* 0x6A 0x01A8 106: Reserved */ + .long RSV91_IRQHandler /* 0x6B 0x01AC 107: Reserved */ + .long RSV92_IRQHandler /* 0x6C 0x01B0 108: Reserved */ + .long RSV93_IRQHandler /* 0x6D 0x01B4 109: Reserved */ + .long RSV94_IRQHandler /* 0x6E 0x01B8 110: Reserved */ + .long RSV95_IRQHandler /* 0x6F 0x01BC 111: Reserved */ + .long RSV96_IRQHandler /* 0x70 0x01C0 112: Reserved */ + .long AES_IRQHandler /* 0x71 0x01C4 113: AES */ + .long CRC_IRQHandler /* 0x72 0x01C8 114: CRC */ + .long I2S_IRQHandler /* 0x73 0x01CC 115: I2S */ .text .thumb @@ -224,7 +269,7 @@ blx r0 .SPIN: - /* Enter LP2 if main() ever returns. */ + /* Enter LP2 if main() ever returns. */ wfi bl .SPIN @@ -255,58 +300,103 @@ /* Device-specific Interrupts */ def_irq_handler PF_IRQHandler /* 0x10 0x0040 16: Power Fail */ def_irq_handler WDT0_IRQHandler /* 0x11 0x0044 17: Watchdog 0 */ - def_irq_handler RSV00_IRQHandler /* 0x12 0x0048 18: RSV00 */ + def_irq_handler RSV02_IRQHandler /* 0x12 0x0048 18: Reserved */ def_irq_handler RTC_IRQHandler /* 0x13 0x004C 19: RTC */ - def_irq_handler RSV1_IRQHandler /* 0x14 0x0050 20: RSV1 */ + def_irq_handler TRNG_IRQHandler /* 0x14 0x0050 20: True Random Number Generator */ def_irq_handler TMR0_IRQHandler /* 0x15 0x0054 21: Timer 0 */ def_irq_handler TMR1_IRQHandler /* 0x16 0x0058 22: Timer 1 */ def_irq_handler TMR2_IRQHandler /* 0x17 0x005C 23: Timer 2 */ - def_irq_handler RSV02_IRQHandler /* 0x18 0x0060 24: RSV02 */ - def_irq_handler RSV03_IRQHandler /* 0x19 0x0064 25: RSV03 */ - def_irq_handler RSV04_IRQHandler /* 0x1A 0x0068 26: RSV04 */ - def_irq_handler RSV05_IRQHandler /* 0x1B 0x006C 27: RSV05 */ - def_irq_handler RSV06_IRQHandler /* 0x1C 0x0070 28: RSV06 */ + def_irq_handler TMR3_IRQHandler /* 0x18 0x0060 24: Timer 3 */ + def_irq_handler TMR4_IRQHandler /* 0x19 0x0064 25: Timer 4 */ + def_irq_handler TMR5_IRQHandler /* 0x1A 0x0068 26: Timer 5 */ + def_irq_handler RSV11_IRQHandler /* 0x1B 0x006C 27: Reserved */ + def_irq_handler RSV12_IRQHandler /* 0x1C 0x0070 28: Reserved */ def_irq_handler I2C0_IRQHandler /* 0x1D 0x0074 29: I2C0 */ def_irq_handler UART0_IRQHandler /* 0x1E 0x0078 30: UART 0 */ def_irq_handler UART1_IRQHandler /* 0x1F 0x007C 31: UART 1 */ - def_irq_handler SPI0_IRQHandler /* 0x20 0x0080 32: SPIY17 */ - def_irq_handler SPI1_IRQHandler /* 0x21 0x0084 33: SPIMSS */ - def_irq_handler RSV07_IRQHandler /* 0x22 0x0088 34: RSV07 */ - def_irq_handler RSV08_IRQHandler /* 0x23 0x008C 35: RSV08 */ - def_irq_handler RSV09_IRQHandler /* 0x24 0x0090 36: RSV09 */ - def_irq_handler RSV10_IRQHandler /* 0x25 0x0094 37: RSV10 */ - def_irq_handler RSV11_IRQHandler /* 0x26 0x0098 38: RSV11 */ - def_irq_handler FLC_IRQHandler /* 0x27 0x009C 39: FLC */ + def_irq_handler SPI0_IRQHandler /* 0x20 0x0080 32: SPI0 */ + def_irq_handler SPI1_IRQHandler /* 0x21 0x0084 33: SPI1 */ + def_irq_handler SPI2_IRQHandler /* 0x22 0x0088 34: SPI2 */ + def_irq_handler RSV19_IRQHandler /* 0x23 0x008C 35: Reserved */ + def_irq_handler RSV20_IRQHandler /* 0x24 0x0090 36: Reserved */ + def_irq_handler RSV21_IRQHandler /* 0x25 0x0094 37: Reserved */ + def_irq_handler RSV22_IRQHandler /* 0x26 0x0098 38: Magstripe DSP */ + def_irq_handler FLC0_IRQHandler /* 0x27 0x009C 39: Flash Controller 0 */ def_irq_handler GPIO0_IRQHandler /* 0x28 0x00A0 40: GPIO0 */ - def_irq_handler RSV12_IRQHandler /* 0x29 0x00A4 41: RSV12 */ - def_irq_handler RSV13_IRQHandler /* 0x2A 0x00A8 42: RSV13 */ - def_irq_handler RSV14_IRQHandler /* 0x2B 0x00AC 43: RSV14 */ + def_irq_handler GPIO1_IRQHandler /* 0x29 0x00A4 41: GPIO2 */ + def_irq_handler RSV26_IRQHandler /* 0x2A 0x00A8 42: GPIO3 */ + def_irq_handler RSV27_IRQHandler /* 0x2B 0x00AC 43: Crypto */ def_irq_handler DMA0_IRQHandler /* 0x2C 0x00B0 44: DMA0 */ def_irq_handler DMA1_IRQHandler /* 0x2D 0x00B4 45: DMA1 */ def_irq_handler DMA2_IRQHandler /* 0x2E 0x00B8 46: DMA2 */ def_irq_handler DMA3_IRQHandler /* 0x2F 0x00BC 47: DMA3 */ - def_irq_handler RSV15_IRQHandler /* 0x30 0x00C0 48: RSV15 */ - def_irq_handler RSV16_IRQHandler /* 0x31 0x00C4 49: RSV16 */ - def_irq_handler RSV17_IRQHandler /* 0x32 0x00C8 50: RSV17 */ - def_irq_handler RSV18_IRQHandler /* 0x33 0x00CC 51: RSV18 */ + def_irq_handler RSV32_IRQHandler /* 0x30 0x00C0 48: Reserved */ + def_irq_handler RSV33_IRQHandler /* 0x31 0x00C4 49: Reserved */ + def_irq_handler UART2_IRQHandler /* 0x32 0x00C8 50: UART 2 */ + def_irq_handler RSV35_IRQHandler /* 0x33 0x00CC 51: Contactless Link Control */ def_irq_handler I2C1_IRQHandler /* 0x34 0x00D0 52: I2C1 */ - def_irq_handler RSV19_IRQHandler /* 0x35 0x00D4 53: RSV19 */ - def_irq_handler RSV20_IRQHandler /* 0x36 0x00D8 54: RSV20 */ - def_irq_handler RSV21_IRQHandler /* 0x37 0x00DC 55: RSV21 */ - def_irq_handler RSV22_IRQHandler /* 0x38 0x00E0 56: RSV22 */ - def_irq_handler RSV23_IRQHandler /* 0x39 0x00E4 57: RSV23 */ - def_irq_handler RSV24_IRQHandler /* 0x3A 0x00E8 58: RSV24 */ - def_irq_handler RSV25_IRQHandler /* 0x3B 0x00EC 59: RSV25 */ - def_irq_handler RSV26_IRQHandler /* 0x3C 0x00F0 60: RSV26 */ - def_irq_handler RSV27_IRQHandler /* 0x3D 0x00F4 61: RSV27 */ - def_irq_handler RSV28_IRQHandler /* 0x3E 0x00F8 62: RSV28 */ - def_irq_handler RSV29_IRQHandler /* 0x3F 0x00FC 63: RSV29 */ - def_irq_handler RSV30_IRQHandler /* 0x40 0x0100 64: RSV30 */ - def_irq_handler RSV31_IRQHandler /* 0x41 0x0104 65: RSV31 */ - def_irq_handler RSV32_IRQHandler /* 0x42 0x0108 66: RSV32 */ - def_irq_handler RSV33_IRQHandler /* 0x43 0x010C 67: RSV33 */ - def_irq_handler RSV34_IRQHandler /* 0x44 0x0110 68: RSV34 */ - def_irq_handler RSV35_IRQHandler /* 0x45 0x0114 69: RSV35 */ - def_irq_handler GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIO Wakeup */ + def_irq_handler RSV37_IRQHandler /* 0x35 0x00D4 53: Smart Card 1 */ + def_irq_handler RSV38_IRQHandler /* 0x36 0x00D8 54: Reserved */ + def_irq_handler RSV39_IRQHandler /* 0x37 0x00DC 55: Reserved */ + def_irq_handler RSV40_IRQHandler /* 0x38 0x00E0 56: Reserved */ + def_irq_handler RSV41_IRQHandler /* 0x39 0x00E4 57: Reserved */ + def_irq_handler RSV42_IRQHandler /* 0x3A 0x00E8 58: Reserved */ + def_irq_handler RSV43_IRQHandler /* 0x3B 0x00EC 59: Reserved */ + def_irq_handler RSV44_IRQHandler /* 0x3C 0x00F0 60: Reserved */ + def_irq_handler RSV45_IRQHandler /* 0x3D 0x00F4 61: Reserved */ + def_irq_handler RSV46_IRQHandler /* 0x3E 0x00F8 62: Reserved */ + def_irq_handler RSV47_IRQHandler /* 0x3F 0x00FC 63: Reserved */ + def_irq_handler RSV48_IRQHandler /* 0x40 0x0100 64: Reserved */ + def_irq_handler RSV49_IRQHandler /* 0x41 0x0104 65: Reserved */ + def_irq_handler RSV50_IRQHandler /* 0x42 0x0108 66: Reserved */ + def_irq_handler RSV51_IRQHandler /* 0x43 0x010C 67: Reserved */ + def_irq_handler RSV52_IRQHandler /* 0x44 0x0110 68: Reserved */ + def_irq_handler RSV53_IRQHandler /* 0x45 0x0114 69: Reserved */ + def_irq_handler GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIOWAKE */ + def_irq_handler RSV55_IRQHandler /* 0x47 0x011C 71: Reserved */ + def_irq_handler RSV56_IRQHandler /* 0x48 0x0120 72: Reserved */ + def_irq_handler WDT1_IRQHandler /* 0x49 0x0124 73: Watchdog 1 */ + def_irq_handler RSV57_IRQHandler /* 0x4A 0x0128 74: Reserved */ + def_irq_handler RSV58_IRQHandler /* 0x4B 0x012C 75: Reserved */ + def_irq_handler RSV59_IRQHandler /* 0x4C 0x0130 76: Reserved */ + def_irq_handler RSV61_IRQHandler /* 0x4D 0x0134 77: Reserved */ + def_irq_handler I2C2_IRQHandler /* 0x4E 0x0138 78: I2C 2 */ + def_irq_handler RSV63_IRQHandler /* 0x4F 0x013C 79: Reserved */ + def_irq_handler RSV64_IRQHandler /* 0x50 0x0140 80: Reserved */ + def_irq_handler RSV65_IRQHandler /* 0x51 0x0144 81: Reserved */ + def_irq_handler RSV66_IRQHandler /* 0x52 0x0148 82: Reserved */ + def_irq_handler RSV67_IRQHandler /* 0x53 0x014C 83: Reserved */ + def_irq_handler DMA4_IRQHandler /* 0x54 0x0150 84: DMA4 */ + def_irq_handler DMA5_IRQHandler /* 0x55 0x0154 85: DMA5 */ + def_irq_handler DMA6_IRQHandler /* 0x56 0x0158 86: DMA6 */ + def_irq_handler DMA7_IRQHandler /* 0x57 0x015C 87: DMA7 */ + def_irq_handler DMA8_IRQHandler /* 0x58 0x0160 88: DMA8 */ + def_irq_handler DMA9_IRQHandler /* 0x59 0x0164 89: DMA9 */ + def_irq_handler DMA10_IRQHandler /* 0x5A 0x0168 90: DMA10 */ + def_irq_handler DMA11_IRQHandler /* 0x5B 0x016C 91: DMA11 */ + def_irq_handler DMA12_IRQHandler /* 0x5C 0x0170 92: DMA12 */ + def_irq_handler DMA13_IRQHandler /* 0x5D 0x0174 93: DMA13 */ + def_irq_handler DMA14_IRQHandler /* 0x5E 0x0178 94: DMA14 */ + def_irq_handler DMA15_IRQHandler /* 0x5F 0x017C 95: DMA15 */ + def_irq_handler RSV80_IRQHandler /* 0x60 0x0180 96: Reserved */ + def_irq_handler RSV81_IRQHandler /* 0x61 0x0184 97: Reserved */ + def_irq_handler ECC_IRQHandler /* 0x62 0x0188 98: Error Correction */ + def_irq_handler RSV83_IRQHandler /* 0x63 0x018C 99: Reserved */ + def_irq_handler RSV84_IRQHandler /* 0x64 0x0190 100: Reserved */ + def_irq_handler RSV85_IRQHandler /* 0x65 0x0194 101: Reserved */ + def_irq_handler RSV86_IRQHandler /* 0x66 0x0198 102: Reserved */ + def_irq_handler RSV87_IRQHandler /* 0x67 0x019C 103: Reserved */ + def_irq_handler UART3_IRQHandler /* 0x68 0x01A0 104: UART 3 */ + def_irq_handler RSV89_IRQHandler /* 0x69 0x01A4 105: Reserved */ + def_irq_handler RSV90_IRQHandler /* 0x6A 0x01A8 106: Reserved */ + def_irq_handler RSV91_IRQHandler /* 0x6B 0x01AC 107: Reserved */ + def_irq_handler RSV92_IRQHandler /* 0x6C 0x01B0 108: Reserved */ + def_irq_handler RSV93_IRQHandler /* 0x6D 0x01B4 109: Reserved */ + def_irq_handler RSV94_IRQHandler /* 0x6E 0x01B8 110: Reserved */ + def_irq_handler RSV95_IRQHandler /* 0x6F 0x01BC 111: Reserved */ + def_irq_handler RSV96_IRQHandler /* 0x70 0x01C0 112: Reserved */ + def_irq_handler AES_IRQHandler /* 0x71 0x01C4 113: AES */ + def_irq_handler CRC_IRQHandler /* 0x72 0x01C8 114: CRC */ + def_irq_handler I2S_IRQHandler /* 0x73 0x01CC 115: I2S */ .end diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/device/cmsis.h b/targets/TARGET_Maxim/TARGET_MAX32670/device/cmsis.h index 35470a6..4e41f75 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/device/cmsis.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/device/cmsis.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (c) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,7 +34,7 @@ #ifndef MBED_CMSIS_H #define MBED_CMSIS_H -#include "max32660.h" +#include "max32670.h" #include "nvic_table.h" #endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/device/nvic_table.h b/targets/TARGET_Maxim/TARGET_MAX32670/device/nvic_table.h index ce84217..e18bfd2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/device/nvic_table.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/device/nvic_table.h @@ -4,7 +4,7 @@ */ /* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -42,11 +42,11 @@ #define _NVIC_TABLE_H #if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 + #define MBED_APP_START 0x10000000 #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x40000 // 256 KB + #define MBED_APP_SIZE (0x60000 - 0x2000) // 384KB-8KB #endif #if !defined(MBED_RAM_START) @@ -54,10 +54,10 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x18000 // 96 KB +#define MBED_RAM_SIZE 0x28000 // 160 KB #endif -#define NVIC_NUM_VECTORS (16 + 55) // MXC_IRQ_COUNT +#define NVIC_NUM_VECTORS (16 + 100) // MXC_IRQ_COUNT #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START // Vectors positioned at start of RAM #endif /* _NVIC_TABLE_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/flash_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/flash_api.c index 7db4781..2ea8d55 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/flash_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/flash_api.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -108,7 +108,9 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { /* 1 sector = 1 page */ - if (address >= (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + if ( (address < MXC_FLASH_MEM_BASE) || + (address >= (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) + ) { return MBED_FLASH_INVALID_SIZE; } else { return MXC_FLASH_PAGE_SIZE; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/gpio_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/gpio_api.c index b85b1c4..12c55f3 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/gpio_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/gpio_api.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -51,15 +51,19 @@ return; } // Obtain pin number + unsigned int port = PINNAME_TO_PORT(name); unsigned int pin = PINNAME_TO_PIN(name); + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); + // Set register pointers - obj->reg_out = (uint32_t*)BITBAND(&MXC_GPIO0->out, pin); - obj->reg_in = (uint32_t*)BITBAND(&MXC_GPIO0->in, pin); + obj->reg_out = (uint32_t*)BITBAND(&gpio->out, pin); + obj->reg_in = (uint32_t*)BITBAND(&gpio->in, pin); obj->mode = PullNone; // Ensure that the GPIO clock is enabled - MXC_GCR->pclk_dis0 &= ~MXC_F_GCR_PCLK_DIS0_GPIO0D; + MXC_GCR->pclkdis0 &= ~MXC_F_GCR_PCLKDIS0_GPIO0; + MXC_GCR->pclkdis0 &= ~MXC_F_GCR_PCLKDIS0_GPIO1; } void gpio_mode(gpio_t *obj, PinMode mode) @@ -75,13 +79,16 @@ pin_function(name, 0); unsigned int pin = PINNAME_TO_PIN(name); + unsigned int port = PINNAME_TO_PORT(name); + + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); if (mode == PullUp) { - MXC_GPIO0->out |= 1 << pin; + gpio->out |= 1 << pin; } else if (mode == PullDown) { - MXC_GPIO0->out &= ~(1 << pin); + gpio->out &= ~(1 << pin); } else { // PullNone - MXC_GPIO0->out &= ~(1 << pin); + gpio->out &= ~(1 << pin); } break; case PIN_OUTPUT: diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/gpio_irq_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/gpio_irq_api.c index 0ff67e8..2955a69 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/gpio_irq_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/gpio_irq_api.c @@ -39,29 +39,29 @@ static gpio_irq_t *objs[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT] = {{0}}; static gpio_irq_handler irq_handler; -void gpio_irq_0(void) +static void handle_irq(unsigned int port) { uint32_t intfl, in_val; uint32_t mask; unsigned int pin; /* Get GPIO Register Structure */ - mxc_gpio_regs_t *gpio = MXC_GPIO0; //MXC_GPIO_GET_GPIO(port); + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); /* Read pin state */ in_val = gpio->in; /* Read interrupts */ - intfl = gpio->int_stat & gpio->int_en; + intfl = gpio->intfl & gpio->inten; mask = 1; /* Determine related routine*/ for (pin = 0; pin < MXC_CFG_GPIO_PINS_PORT; pin++) { if (intfl & mask) { - gpio->int_clr |= mask;/* clear interrupt */ + gpio->intfl_clr |= mask;/* clear interrupt */ gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL; - gpio_irq_t *obj = objs[0][pin]; + gpio_irq_t *obj = objs[port][pin]; if (obj && obj->id) { if ((event == IRQ_RISE) && obj->rise_en) { irq_handler(obj->id, IRQ_RISE); @@ -74,7 +74,10 @@ } } -int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id) +void gpio_irq_0(void) { handle_irq(0); } +void gpio_irq_1(void) { handle_irq(1); } + +int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uintptr_t id) { if (name == NC) { return -1; @@ -87,6 +90,11 @@ return 1; } + /* Do not allow second set if slot is allread allocated and not released */ + //if (objs[port][pin]) { + // return 1; + //} + obj->port = port; obj->pin = pin; obj->id = id; @@ -95,49 +103,58 @@ /* register handlers */ irq_handler = handler; NVIC_SetVector(GPIO0_IRQn, (uint32_t)gpio_irq_0); + if (port == Port1) { + NVIC_SetVector(GPIO1_IRQn, (uint32_t)gpio_irq_1); + } + + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); /* disable the interrupt locally */ - MXC_GPIO0->int_en &= ~(1 << pin); - + gpio->inten_clr |= (1 << pin); /* clear a pending request */ - MXC_GPIO0->int_stat |= (1 << pin); + gpio->intfl_clr |= (1 << pin); - NVIC_EnableIRQ(GPIO0_IRQn); + NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO0_IRQn + port)); return 0; } void gpio_irq_free(gpio_irq_t *obj) { - MXC_GPIO0->int_en &= ~(1 << obj->pin); + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(obj->port); + gpio->inten_clr |= (1 << obj->pin); objs[obj->port][obj->pin] = NULL; - } void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - /* Note that MAX32660 supports only one edge interrupt at a time */ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(obj->port); + if (event == IRQ_FALL) { obj->fall_en = enable; - MXC_GPIO0->int_mod |= (1 << obj->pin); - MXC_GPIO0->int_pol &= ~(1 << obj->pin); - MXC_GPIO0->int_en |= (1 << obj->pin); + gpio->intmode |= (1 << obj->pin); + gpio->intpol &= ~(1 << obj->pin); + gpio->dualedge &= ~(1 << obj->pin); + gpio->inten_set |= (1 << obj->pin); } else if (event == IRQ_RISE) { obj->rise_en = enable; - MXC_GPIO0->int_mod |= (1 << obj->pin); - MXC_GPIO0->int_pol |= (1 << obj->pin); - MXC_GPIO0->int_en |= (1 << obj->pin); + gpio->intmode |= (1 << obj->pin); + gpio->intpol |= (1 << obj->pin); + gpio->dualedge &= ~(1 << obj->pin); + gpio->inten_set |= (1 << obj->pin); } } void gpio_irq_enable(gpio_irq_t *obj) { - MXC_GPIO0->int_en |= (1 << obj->pin); + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(obj->port); + gpio->inten_set |= (1 << obj->pin); } void gpio_irq_disable(gpio_irq_t *obj) { - MXC_GPIO0->int_en &= ~(1 << obj->pin); + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(obj->port); + gpio->inten_clr |= (1 << obj->pin); } gpio_irq_t *gpio_irq_get_obj(PinName name) diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/gpio_object.h b/targets/TARGET_Maxim/TARGET_MAX32670/gpio_object.h index 8cce1bc..29f2854 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/gpio_object.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/gpio_object.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/i2c_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/i2c_api.c index 310a321..1dcc062 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/i2c_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/i2c_api.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (c) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -41,16 +41,6 @@ #include "pinmap.h" #include "PeripheralPins.h" -#ifndef MXC_I2CM_RX_TIMEOUT -#define MXC_I2CM_RX_TIMEOUT 0x5000 -#endif - -#ifndef I2C_ERROR -#define I2C_ERROR (MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | MXC_F_I2C_INT_FL0_ADDR_NACK_ER | \ - MXC_F_I2C_INT_FL0_DATA_ER | MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \ - MXC_F_I2C_INT_FL0_STOP_ER) -#endif - #define MBED_NAK 0 #define MBED_ACK 1 #define MBED_TIMEOUT 2 diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/lp_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32670/lp_ticker.c index 315352b..fca1e9d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/lp_ticker.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/lp_ticker.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -149,10 +149,18 @@ #include "tmr.h" -#define LP_TIMER MXC_TMR2 -#define LP_TIMER_IRQn TMR2_IRQn -#define LP_TIMER_PRESCALE TMR_PRES_1024 -#define LP_TIMER_FREQ ((HIRC96_FREQ/2) >> (MXC_V_TMR_CN_PRES_DIV_BY_1024+1)) +#if MBED_CONF_TARGET_LP_TICKER_TIMER == 0 + #define LP_TIMER MXC_TMR4 + #define LP_TIMER_IRQn TMR4_IRQn +#elif MBED_CONF_TARGET_LP_TICKER_TIMER == 1 + #define LP_TIMER MXC_TMR5 + #define LP_TIMER_IRQn TMR5_IRQn +#else + #error "Invalid low power timer selected" +#endif + +#define LP_TIMER_PRESCALE TMR_PRES_8 +#define LP_TIMER_FREQ (ERTCO_FREQ >> 3) #define LP_TIMER_WIDTH 32 //****************************************************************************** @@ -164,7 +172,7 @@ cfg.pres = LP_TIMER_PRESCALE; cfg.mode = TMR_MODE_COMPARE; cfg.bitMode = TMR_BIT_MODE_32; - cfg.clock = MXC_TMR_HFIO_CLK; + cfg.clock = MXC_TMR_32K_CLK; cfg.cmp_cnt = 0;//MXC_TMR_GetCompare(LP_TIMER); cfg.pol = 0; @@ -175,13 +183,25 @@ count = MXC_TMR_GetCount(LP_TIMER); // Configure and enable - MXC_TMR_Init(LP_TIMER, &cfg); + MXC_TMR_Init(LP_TIMER, &cfg, 0); + MXC_TMR_EnableWakeup(LP_TIMER, &cfg); MXC_TMR_SetCount(LP_TIMER, count); - MXC_TMR_Start(LP_TIMER); // Enable interrupts + MXC_TMR_EnableInt(LP_TIMER); NVIC_SetVector(LP_TIMER_IRQn, (uint32_t)lp_ticker_irq_handler); NVIC_EnableIRQ(LP_TIMER_IRQn); + +#if MBED_CONF_TARGET_LP_TICKER_TIMER == 0 + MXC_GCR->pm |= MXC_F_GCR_PM_LPTMR0_WE; +#elif MBED_CONF_TARGET_LP_TICKER_TIMER == 1 + MXC_GCR->pm |= MXC_F_GCR_PM_LPTMR1_WE; +#endif + + MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_ERTCO_EN; + + MXC_LP_EnableTimerWakeup(LP_TIMER); + MXC_TMR_Start(LP_TIMER); } //****************************************************************************** @@ -193,13 +213,21 @@ //****************************************************************************** uint32_t lp_ticker_read(void) { - return LP_TIMER->cnt; + uint32_t cnt; + + // read cnt register twice + cnt = LP_TIMER->cnt; + cnt = LP_TIMER->cnt; + //cnt = MXC_TMR_GetCount(LP_TIMER); + + return cnt; } //****************************************************************************** void lp_ticker_set_interrupt(timestamp_t timestamp) { - MXC_TMR_SetCompare(LP_TIMER, (timestamp) ? timestamp : 1); + //MXC_TMR_SetCompare(LP_TIMER, (timestamp) ? timestamp : 1); + LP_TIMER->cmp = timestamp ? timestamp : 1; } //****************************************************************************** @@ -233,4 +261,4 @@ #endif -#endif // DEVICE_LPTICKER \ No newline at end of file +#endif // DEVICE_LPTICKER diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/pinmap.c b/targets/TARGET_Maxim/TARGET_MAX32670/pinmap.c index c897bcc..d6520f0 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/pinmap.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/pinmap.c @@ -40,31 +40,50 @@ { MBED_ASSERT(name != (PinName)NC); - if ((function >= 0) && (function <= 0xF)) { + uint8_t port = PINNAME_TO_PORT(name); + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); + if ((function >= 0) && (function <= 0xF)) { // Set GPIO Function unsigned int pin_val = (1 << PINNAME_TO_PIN(name)); switch (function) { case 0: // GPIO_FUNC_IN - MXC_GPIO0->en0 |= pin_val; - MXC_GPIO0->en1 &= ~pin_val; + //gpio->en0 |= pin_val; + //gpio->en1 &= ~pin_val; + gpio->outen_clr = pin_val; + gpio->en0_set = pin_val; + gpio->en1_clr = pin_val; + gpio->en2_clr = pin_val; break; case 1: // GPIO_FUNC_OUT - MXC_GPIO0->en0 |= pin_val; - MXC_GPIO0->en1 &= ~pin_val; - MXC_GPIO0->out_en |= pin_val; + //gpio->en0 |= pin_val; + //gpio->en1 &= ~pin_val; + //gpio->outen |= pin_val; + gpio->outen_set = pin_val; + gpio->en0_set = pin_val; + gpio->en1_clr = pin_val; + gpio->en2_clr = pin_val; break; case 2: // GPIO_FUNC_ALT1 - MXC_GPIO0->en0 &= ~pin_val; - MXC_GPIO0->en1 &= ~pin_val; + //gpio->en0 &= ~pin_val; + //gpio->en1 &= ~pin_val; + gpio->en2_clr = pin_val; + gpio->en1_clr = pin_val; + gpio->en0_clr = pin_val; break; case 3: // GPIO_FUNC_ALT2 - MXC_GPIO0->en0 &= ~pin_val; - MXC_GPIO0->en1 |= pin_val; + //gpio->en0 &= ~pin_val; + //gpio->en1 |= pin_val; + gpio->en2_clr = pin_val; + gpio->en1_set = pin_val; + gpio->en0_clr = pin_val; break; case 4: // GPIO_FUNC_ALT3 - MXC_GPIO0->en0 |= pin_val; - MXC_GPIO0->en1 |= pin_val; + //gpio->en0 |= pin_val; + //gpio->en1 |= pin_val; + gpio->en2_set = pin_val; + gpio->en1_clr = pin_val; + gpio->en0_clr = pin_val; break; default: break; @@ -76,19 +95,22 @@ { MBED_ASSERT(name != (PinName)NC); + unsigned int port = PINNAME_TO_PORT(name); + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); + unsigned int pin_val = (1 << PINNAME_TO_PIN(name)); switch (mode) { case PullUp: - MXC_GPIO0->pad_cfg1 |= pin_val; - MXC_GPIO0->ps |= pin_val; + gpio->padctrl0 |= pin_val; + gpio->ps |= pin_val; break; case PullDown: - MXC_GPIO0->pad_cfg1 |= pin_val; - MXC_GPIO0->ps &= ~pin_val; + gpio->padctrl0 |= pin_val; + gpio->ps &= ~pin_val; break; case PullNone: - MXC_GPIO0->pad_cfg1 &= ~pin_val; - MXC_GPIO0->ps &= ~pin_val; + gpio->padctrl0 &= ~pin_val; + //gpio->ps &= ~pin_val; break; default: break; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/port_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/port_api.c index 67dd714..099720f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/port_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/port_api.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -44,7 +44,7 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection direction) { uint32_t pin_per_port; - mxc_gpio_regs_t *gpio = MXC_GPIO0; //MXC_GPIO_GET_GPIO(port); + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); obj->port = port; obj->mask = mask; obj->reg_out = &gpio->out; @@ -53,7 +53,9 @@ // Ensure that the GPIO clock is enabled if (port == Port0) { - MXC_GCR->pclk_dis0 &= ~MXC_F_GCR_PCLK_DIS0_GPIO0D; + MXC_GCR->pclkdis0 &= ~MXC_F_GCR_PCLKDIS0_GPIO0; + } else if (port == Port1) { + MXC_GCR->pclkdis0 &= ~MXC_F_GCR_PCLKDIS0_GPIO1; } // Obtain pin number of the port diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/rtc_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/rtc_api.c index c17c676..b7509e0 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/rtc_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/rtc_api.c @@ -44,7 +44,7 @@ void rtc_init(void) { // Enable clock - MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; + MXC_SYS_RTCClockEnable(); while(MXC_RTC_Start() == E_BUSY) { ; @@ -60,7 +60,7 @@ //****************************************************************************** int rtc_isenabled(void) { - return ((MXC_RTC->ctrl & MXC_F_RTC_CTRL_RTCE) >> MXC_F_RTC_CTRL_RTCE_POS); + return ((MXC_RTC->ctrl & MXC_F_RTC_CTRL_EN) >> MXC_F_RTC_CTRL_EN_POS); } //****************************************************************************** @@ -84,6 +84,11 @@ ; } + subsec &= 0xFFF; //It is 12 bits, 0xFFF = (1<<12)-1 + if (subsec > 2048) { + sec += 1; // rolover + } + return sec; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c index 6667883..8554dce1 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/serial_api.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -39,7 +39,7 @@ #include "gpio_api.h" #include "uart.h" #include "uart_regs.h" -#include "uart_reva_regs.h" +#include "uart_revb_regs.h" #include "PeripheralPins.h" #define DEFAULT_BAUD 9600 @@ -53,17 +53,13 @@ static serial_t *objs[MXC_UART_INSTANCES]; -#define UART_ER_IE (MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR | \ - MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR | \ - MXC_F_UART_REVA_INT_EN_RX_OVERRUN) +#define UART_ER_IE (MXC_F_UART_REVB_INT_EN_RX_FERR | \ + MXC_F_UART_REVB_INT_EN_RX_PAR | \ + MXC_F_UART_REVB_INT_EN_RX_OV) -#define UART_RX_IE (MXC_F_UART_INT_EN_RX_FIFO_LVL) +#define UART_RX_IE (MXC_F_UART_REVB_INT_EN_RX_THD) -#define UART_TX_IE (MXC_F_UART_INT_EN_TX_FIFO_AE | \ - MXC_F_UART_INT_EN_TX_FIFO_LVL) - -#define MXC_F_UART_THRESH_CTRL_TX_FIFO_DEFAULT_THRESH_VAL (1 << MXC_F_UART_CTRL1_TX_FIFO_LVL_POS) -#define MXC_F_UART_THRESH_CTRL_RX_FIFO_DEFAULT_THRESH_VAL (1 << MXC_F_UART_CTRL1_RX_FIFO_LVL_POS) +#define UART_TX_IE (MXC_F_UART_INT_EN_TX_HE) static void usurp_pin(PinName, int); @@ -89,13 +85,12 @@ obj->rx = rx; obj->map = MAP_A; - - if (uart == UART_1) { - if ( (tx == UART1B_TX) && (rx == UART1B_RX) ) { - obj->map = MAP_B; - } else if ( (tx == UART1C_TX) && (rx == UART1C_RX) ) { - obj->map = MAP_C; - } + if ( (tx == UART0B_TX) && (rx == UART0B_RX) ) { + obj->map = MAP_B; + } else if ( (tx == UART1B_TX) && (rx == UART1B_RX) ) { + obj->map = MAP_B; + } else if ( (tx == UART2B_TX) && (rx == UART2B_RX) ) { + obj->map = MAP_B; } // Manage stdio UART @@ -104,7 +99,7 @@ stdio_uart = *obj; } - MXC_UART_Init (obj->uart, DEFAULT_BAUD, obj->map); + MXC_UART_Init (obj->uart, DEFAULT_BAUD, MXC_UART_APB_CLK, obj->map); //MBED_ASSERT(retval == E_NO_ERROR); } @@ -118,7 +113,7 @@ //****************************************************************************** void serial_baud(serial_t *obj, int baudrate) { - MXC_UART_SetFrequency(obj->uart, baudrate); + MXC_UART_SetFrequency(obj->uart, baudrate, MXC_UART_APB_CLK); //MBED_ASSERT(retval == E_NO_ERROR); } @@ -133,10 +128,10 @@ MXC_UART_SetParity (obj->uart, MXC_UART_PARITY_DISABLE); break; case ParityOdd : - MXC_UART_SetParity (obj->uart, MXC_UART_PARITY_ODD); + MXC_UART_SetParity (obj->uart, MXC_UART_PARITY_ODD_0); break; case ParityEven: - MXC_UART_SetParity (obj->uart, MXC_UART_PARITY_EVEN); + MXC_UART_SetParity (obj->uart, MXC_UART_PARITY_EVEN_0); break; case ParityForced1: case ParityForced0: @@ -186,6 +181,8 @@ void uart0_handler(void) { uart_handler(objs[0]); } void uart1_handler(void) { uart_handler(objs[1]); } +void uart2_handler(void) { uart_handler(objs[2]); } +void uart3_handler(void) { uart_handler(objs[3]); } //****************************************************************************** void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) @@ -209,6 +206,14 @@ NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); NVIC_EnableIRQ(UART1_IRQn); break; + case 2: + NVIC_SetVector(UART2_IRQn, (uint32_t)uart2_handler); + NVIC_EnableIRQ(UART2_IRQn); + break; + case 3: + NVIC_SetVector(UART3_IRQn, (uint32_t)uart3_handler); + NVIC_EnableIRQ(UART3_IRQn); + break; default: MBED_ASSERT(0); } @@ -217,23 +222,21 @@ obj->uart->int_fl = obj->uart->int_fl; // Set TX Almost Empty level to interrupt when empty - obj->uart->ctrl1 = (MXC_F_UART_THRESH_CTRL_RX_FIFO_DEFAULT_THRESH_VAL | MXC_F_UART_THRESH_CTRL_TX_FIFO_DEFAULT_THRESH_VAL); - + MXC_UART_SetRXThreshold(obj->uart, 1); + if (irq == RxIrq) { // Enable RX FIFO Threshold Interrupt if (enable) { - obj->uart->int_en |= UART_RX_IE | UART_ER_IE; + MXC_UART_EnableInt(obj->uart, (UART_RX_IE | UART_ER_IE)); } else { - obj->uart->int_en &= ~(UART_RX_IE | UART_ER_IE); + MXC_UART_DisableInt(obj->uart, (UART_RX_IE | UART_ER_IE)); } } else if (irq == TxIrq) { // Enable TX Almost Empty Interrupt if (enable) { - //obj->uart->int_en |= MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY; - obj->uart->int_en |= UART_TX_IE | UART_ER_IE; + MXC_UART_EnableInt(obj->uart, (UART_TX_IE | UART_ER_IE)); } else { - //obj->uart->int_en &= ~MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY; - obj->uart->int_en &= ~(UART_TX_IE | UART_ER_IE); + MXC_UART_DisableInt(obj->uart, (UART_TX_IE | UART_ER_IE)); } } else { MBED_ASSERT(0); @@ -247,7 +250,7 @@ if (obj->rx != NC) { // Wait for data to be available - while( (obj->uart->stat & MXC_F_UART_STAT_RX_NUM) == 0); + while( (obj->uart->status & MXC_F_UART_STATUS_RX_LVL) == 0); c = obj->uart->fifo; } @@ -261,7 +264,6 @@ // Wait for room in the FIFO without blocking interrupts. while (MXC_UART_GetTXFIFOAvailable(obj->uart) == 0); - //obj->uart->int_fl |= MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY; obj->uart->fifo = (uint8_t)c; } } @@ -292,7 +294,7 @@ void serial_break_set(serial_t *obj) { // Make sure that nothing is being sent - while ( (obj->uart->stat & MXC_F_UART_REVA_STATUS_TX_BUSY) ); + while ( (obj->uart->status & MXC_F_UART_STATUS_TX_BUSY) ); // Configure TX to output 0 usurp_pin(obj->tx, 0); @@ -324,7 +326,7 @@ MBED_ASSERT(uart != (UARTName)NC); } - MXC_UART_SetFlowCtrl (obj->uart, MXC_UART_FLOW_EN_LOW, 1); + MXC_UART_SetFlowCtrl (obj->uart, MXC_UART_FLOW_EN, 1, obj->map); //MBED_ASSERT(retval == E_NO_ERROR); } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/sleep.c b/targets/TARGET_Maxim/TARGET_MAX32670/sleep.c index 37dfe6e..8f02d2a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/sleep.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/sleep.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,14 +35,22 @@ #include "sleep_api.h" #include "lp.h" #include "uart.h" +#include "tmr.h" +#include "tmr_revb.h" #if 0 static void prep_for_sleep(void) { + while(MXC_UART_ReadyForSleep(MXC_UART0) != E_NO_ERROR) { + ; + } while(MXC_UART_ReadyForSleep(MXC_UART1) != E_NO_ERROR) { ; } - while(MXC_UART_ReadyForSleep(MXC_UART0) != E_NO_ERROR) { + while(MXC_UART_ReadyForSleep(MXC_UART2) != E_NO_ERROR) { + ; + } + while(MXC_UART_ReadyForSleep(MXC_UART3) != E_NO_ERROR) { ; } } @@ -54,13 +62,6 @@ void hal_sleep(void) { prep_for_sleep(); - - /* Call MXC_LP_DisableBlockDetect function if the system runs from - a single supply only and VCORE is not connected to an external supply. - Bypassing the hardware detection of an external supply on VCORE - enables a faster wakeup time. - */ - MXC_LP_DisableBlockDetect(); /* Switch to sleep mode */ MXC_LP_EnterSleepMode(); @@ -68,19 +69,25 @@ void hal_deepsleep(void) { -#if 0 prep_for_sleep(); + + mxc_tmr_regs_t *tmr; - //MXC_LP_DisableBandGap(); - //MXC_LP_DisableVCorePORSignal(); - //MXC_LP_EnableRamRetReg(); - - MXC_LP_EnableFastWk(); - MXC_LP_ClearWakeStatus(); - - MXC_LP_DisableBlockDetect(); - MXC_LP_EnterDeepSleepMode(); -#else - hal_sleep(); +#if MBED_CONF_TARGET_US_TICKER_TIMER == 0 + tmr = MXC_TMR0; +#elif MBED_CONF_TARGET_US_TICKER_TIMER == 1 + tmr = MXC_TMR1; +#elif MBED_CONF_TARGET_US_TICKER_TIMER == 2 + tmr = MXC_TMR2; +#elif MBED_CONF_TARGET_US_TICKER_TIMER == 3 + tmr = MXC_TMR3; #endif + tmr->ctrl0 &= ~MXC_F_TMR_REVB_CTRL0_EN_A; + + MXC_LP_FastWakeupEnable(); + MXC_LP_EnterDeepSleepMode(); + + tmr->ctrl0 |= MXC_F_TMR_REVB_CTRL0_EN_A; + while(!(tmr->ctrl1 & MXC_F_TMR_REVB_CTRL1_CLKEN_A)); + } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/spi_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/spi_api.c index 8894314..ce0a79d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/spi_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/spi_api.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (c) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -38,53 +38,14 @@ #include "mxc_sys.h" #include "spi_regs.h" -#include "spimss_regs.h" -#include "spimss.h" #include "mxc_spi.h" #include "pinmap.h" #include "PeripheralPins.h" -#define SPI_NUM_0 0 // SPI17Y -#define SPI_NUM_1A 1 // SPIMSS MAPA -#define SPI_NUM_1B 2 // SPIMSS MAPB -#define SPI_NUM_MAX 3 // - -static unsigned int spi_speed = 1000000; -static unsigned int spi_mode = 0; static unsigned int g_drv_ssel = 1; -static int master_send(int spi_num, void *req) -{ - int error = E_NO_ERROR; - - if (spi_num == SPI_NUM_0) { - error = MXC_SPI_MasterTransaction((mxc_spi_req_t *)req); - } else if (spi_num < SPI_NUM_MAX) { - mxc_spimss_req_t spimss_req; - mxc_spi_req_t *req_tmp = (mxc_spi_req_t *)req; - - spimss_req.ssel = req_tmp->ssIdx; /**< Not Used*/ - spimss_req.deass = req_tmp->ssDeassert; /**< Not Used*/ - spimss_req.tx_data = req_tmp->txData; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ - spimss_req.rx_data = req_tmp->rxData; /**< Pointer to a buffer to store data received. NULL if undesired.*/ - spimss_req.width = DUMMY_1; /**< Not Used */ - /**< Number of transfer units to send from the \p tx_data buffer. */ - spimss_req.len = (req_tmp->txLen > req_tmp->rxLen)? req_tmp->txLen: req_tmp->rxLen; - spimss_req.bits = 8; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ - spimss_req.rx_num = req_tmp->rxCnt; /**< Number of bytes actually read into the \p rx_data buffer. */ - spimss_req.tx_num = req_tmp->txCnt; /**< Number of bytes actually sent from the \p tx_data buffer */ - spimss_req.callback = NULL; /**< Callback function if desired, NULL otherwise */ - - error = MXC_SPIMSS_MasterTrans(MXC_SPIMSS, &spimss_req); - } else { - return E_BAD_PARAM; - } - - return error; -} - //****************************************************************************** void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { @@ -110,25 +71,17 @@ MBED_ASSERT((SPIName)spi != (SPIName)NC); - if (spi == SPI_0) { - obj->spi = MXC_SPI0; - obj->index = SPI_NUM_0; + obj->spi = (mxc_spi_regs_t*)spi; - MXC_SPI_Init(obj->spi, 1, 0, 1, 0, spi_speed, g_drv_ssel); - MXC_SPI_SetDataSize(obj->spi, 8); - MXC_SPI_SetWidth(obj->spi, SPI_WIDTH_STANDARD); - } - else if(spi == SPI_1) { - obj->spi = (void *)MXC_SPIMSS; - - if (pinmap_function(mosi, PinMap_SPI_MOSI) == 1) { - obj->index = SPI_NUM_1A; - MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_A, g_drv_ssel); - } else { - obj->index = SPI_NUM_1B; - MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_B, g_drv_ssel); - } - } + int masterMode = 1; + int quadModeUsed = 0; + int numSlaves = 1; + int ssPolarity = 0; + unsigned int spi_speed = 1000000; + + MXC_SPI_Init(obj->spi, masterMode, quadModeUsed, numSlaves, ssPolarity, spi_speed, g_drv_ssel); + MXC_SPI_SetDataSize(obj->spi, 8); + MXC_SPI_SetWidth(obj->spi, SPI_WIDTH_STANDARD); // Configure Slave Slect Pin if defined if ((SPIName)spi_ssel != (SPIName)NC) { @@ -146,20 +99,8 @@ // Only supports master mode MBED_ASSERT(!slave); - spi_mode = mode; - - if (obj->index == SPI_NUM_0) { - MXC_SPI_SetDataSize(obj->spi, bits); - MXC_SPI_SetMode(obj->spi, (mxc_spi_mode_t)mode); - } - else if (obj->index < SPI_NUM_MAX) { - MXC_SPIMSS_Shutdown(obj->spi); - if (obj->index == SPI_NUM_1A) { - MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_A, g_drv_ssel); - } else { - MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_B, g_drv_ssel); - } - } + MXC_SPI_SetDataSize(obj->spi, bits); + MXC_SPI_SetMode(obj->spi, (mxc_spi_mode_t)mode); } ////****************************************************************************** @@ -167,20 +108,8 @@ { // Maximum frequency is the PeripheralClock MBED_ASSERT((unsigned int)hz <= PeripheralClock); - - if (obj->index == SPI_NUM_0) { - spi_speed = hz; - MXC_SPI_SetFrequency(obj->spi, spi_speed); - } - else if (obj->index < SPI_NUM_MAX) { - spi_speed = hz; - MXC_SPIMSS_Shutdown(obj->spi); - if (obj->index == SPI_NUM_1A) { - MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_A, g_drv_ssel); - } else { - MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_B, g_drv_ssel); - } - } + + MXC_SPI_SetFrequency(obj->spi, (unsigned int)hz); } ////****************************************************************************** @@ -204,7 +133,7 @@ req.completeCB = NULL; // Start transfer - master_send(obj->index, &req); + MXC_SPI_MasterTransaction(&req); return in; } @@ -227,11 +156,7 @@ req.rxCnt = 0; req.completeCB = NULL; - if (obj->index == SPI_NUM_0) { - MXC_SPI_SetDefaultTXData(obj->spi, write_fill); - } else { - MXC_SPIMSS_SetDefaultTXData(obj->spi, write_fill); - } + MXC_SPI_SetDefaultTXData(obj->spi, write_fill); core_util_critical_section_enter(); if (tx_length == rx_length) { @@ -240,7 +165,7 @@ req.rxData = (uint8_t *)rx_buffer; req.rxLen = rx_length; - master_send(obj->index, &req); + MXC_SPI_MasterTransaction(&req); } else if (tx_length < rx_length) { if (tx_length == 0) { req.txData = NULL; @@ -248,14 +173,14 @@ req.rxData = (uint8_t *)rx_buffer; req.rxLen = rx_length; - master_send(obj->index, &req); + MXC_SPI_MasterTransaction(&req); } else { req.txData = (uint8_t *)tx_buffer; req.txLen = tx_length; req.rxData = (uint8_t *)rx_buffer; req.rxLen = tx_length; - master_send(obj->index, &req); + MXC_SPI_MasterTransaction(&req); req.txData = NULL; req.txLen = 0; @@ -264,7 +189,7 @@ req.txCnt = 0; req.rxCnt = 0; - master_send(obj->index, &req); + MXC_SPI_MasterTransaction(&req); } } else { if (rx_length == 0) { @@ -273,14 +198,14 @@ req.rxData = NULL; req.rxLen = 0; - master_send(obj->index, &req); + MXC_SPI_MasterTransaction(&req); } else { req.txData = (uint8_t *)tx_buffer; req.txLen = rx_length; req.rxData = (uint8_t *)rx_buffer; req.rxLen = rx_length; - master_send(obj->index, &req); + MXC_SPI_MasterTransaction(&req); req.txData = (uint8_t *)&tx_buffer[rx_length]; req.txLen = tx_length-rx_length; @@ -289,7 +214,7 @@ req.txCnt = 0; req.rxCnt = 0; - master_send(obj->index, &req); + MXC_SPI_MasterTransaction(&req); } } core_util_critical_section_exit(); @@ -300,15 +225,7 @@ //****************************************************************************** int spi_busy(spi_t *obj) { - if (obj->index == SPI_NUM_0) { - return (((mxc_spi_regs_t *)obj->spi)->stat & MXC_F_SPI_STAT_BUSY); - } - else if (obj->index < SPI_NUM_MAX) { - unsigned int reg = ((mxc_spimss_regs_t *)obj->spi)->int_fl; - return (reg & MXC_F_SPIMSS_INT_FL_TXST) >> MXC_F_SPIMSS_INT_FL_TXST_POS; - } - - return 1; + return (((mxc_spi_regs_t *)obj->spi)->stat & MXC_F_SPI_STAT_BUSY); } //****************************************************************************** diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/us_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32670/us_ticker.c index 539751c..022aa01 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/us_ticker.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/us_ticker.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (c) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,10 +35,24 @@ #include "us_ticker_api.h" #include "tmr.h" -#define US_TIMER MXC_TMR1 -#define US_TIMER_IRQn TMR1_IRQn +#if MBED_CONF_TARGET_US_TICKER_TIMER == 0 + #define US_TIMER MXC_TMR0 + #define US_TIMER_IRQn TMR0_IRQn +#elif MBED_CONF_TARGET_US_TICKER_TIMER == 1 + #define US_TIMER MXC_TMR1 + #define US_TIMER_IRQn TMR1_IRQn +#elif MBED_CONF_TARGET_US_TICKER_TIMER == 2 + #define US_TIMER MXC_TMR2 + #define US_TIMER_IRQn TMR2_IRQn +#elif MBED_CONF_TARGET_US_TICKER_TIMER == 3 + #define US_TIMER MXC_TMR3 + #define US_TIMER_IRQn TMR3_IRQn +#else + #error "Invalid timer selected" +#endif + #define US_TIMER_PRESCALE TMR_PRES_32 -#define US_TIMER_FREQ ((HIRC96_FREQ/2) >> MXC_V_TMR_CN_PRES_DIV_BY_32) +#define US_TIMER_FREQ ((IPO_FREQ/2) >> MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32) #define US_TIMER_WIDTH 32 @@ -51,7 +65,7 @@ cfg.pres = US_TIMER_PRESCALE; cfg.mode = TMR_MODE_COMPARE; cfg.bitMode = TMR_BIT_MODE_32; - cfg.clock = MXC_TMR_HFIO_CLK; + cfg.clock = MXC_TMR_APB_CLK; cfg.cmp_cnt = 0;//MXC_TMR_GetCompare(US_TIMER); cfg.pol = 0; @@ -62,10 +76,12 @@ count = MXC_TMR_GetCount(US_TIMER); // Configure and enable - MXC_TMR_Init(US_TIMER, &cfg); + MXC_TMR_Init(US_TIMER, &cfg, 0); MXC_TMR_SetCount(US_TIMER, count); MXC_TMR_Start(US_TIMER); + MXC_TMR_EnableInt(US_TIMER); + // Enable interrupts NVIC_SetVector(US_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); NVIC_EnableIRQ(US_TIMER_IRQn); @@ -80,7 +96,8 @@ //****************************************************************************** uint32_t us_ticker_read(void) { - return US_TIMER->cnt; + //return US_TIMER->cnt; + return MXC_TMR_GetCount(US_TIMER); } //****************************************************************************** diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/watchdog_api.c b/targets/TARGET_Maxim/TARGET_MAX32670/watchdog_api.c index d94b117..c06a777 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/watchdog_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/watchdog_api.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (c) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -38,7 +38,7 @@ #include "mxc_sys.h" #include "wdt_regs.h" #include "wdt.h" -#include "system_max32660.h" +#include "system_max32670.h" watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) @@ -65,16 +65,24 @@ } else if (i < 16) { i = 16; // min } - - MXC_WDT_SetResetPeriod(MXC_WDT0, (mxc_wdt_period_t)(31-i) ); + mxc_wdt_cfg_t wdt_cfg; + + wdt_cfg.mode = MXC_WDT_COMPATIBILITY; + + wdt_cfg.upperResetPeriod = (mxc_wdt_period_t)(31-i); + wdt_cfg.lowerResetPeriod = (mxc_wdt_period_t)(31-i); + wdt_cfg.upperIntPeriod = (mxc_wdt_period_t)(31-i); + wdt_cfg.lowerIntPeriod = (mxc_wdt_period_t)(31-i); + + MXC_WDT_Init(MXC_WDT0, &wdt_cfg); + + MXC_WDT_SetResetPeriod(MXC_WDT0, &wdt_cfg); + //MXC_WDT_SetIntPeriod(MXC_WDT0, &wdt_cfg); hal_watchdog_kick(); - // WDT Enable RESET MXC_WDT_EnableReset(MXC_WDT0); - - // WDT Enable - MXC_WDT_Enable(MXC_WDT0); + MXC_WDT_Enable(MXC_WDT0); return WATCHDOG_STATUS_OK; } @@ -94,7 +102,7 @@ uint32_t hal_watchdog_get_reload_value(void) { - uint32_t rst_period = (MXC_WDT0->ctrl & MXC_F_WDT_CTRL_RST_PERIOD) >> MXC_F_WDT_CTRL_RST_PERIOD_POS; + uint32_t rst_period = (MXC_WDT0->ctrl & MXC_F_WDT_CTRL_RST_LATE_VAL) >> MXC_F_WDT_CTRL_RST_LATE_VAL_POS; uint32_t val = (1<<(31-rst_period)); return ( (float)val / (float)PeripheralClock) * 1000; diff --git a/targets/TARGET_Maxim/mbed_rtx.h b/targets/TARGET_Maxim/mbed_rtx.h index 927ea3a..21be30c 100644 --- a/targets/TARGET_Maxim/mbed_rtx.h +++ b/targets/TARGET_Maxim/mbed_rtx.h @@ -54,6 +54,12 @@ #define INITIAL_SP (0x20018000UL) #endif +#elif defined(TARGET_MAX32670) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20028000UL) +#endif + #endif #endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index 0597492..e18417b 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -6208,6 +6208,90 @@ "0421" ] }, + "MAX32670": { + "inherits": [ + "Target" + ], + "public": false, + "core": "Cortex-M4F", + "macros": [ + "TARGET=MAX32670", + "TARGET_REV=0x4131", + "MBED_MPU_CUSTOM" + ], + "extra_labels": [ + "Maxim", + "MAX32670" + ], + "supported_toolchains": [ + "GCC_ARM", + "ARM" + ], + "device_has": [ + "SERIAL", + "SERIAL_FC", + "STDIO_MESSAGES", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "USTICKER", + "LPTICKER", + "INTERRUPTIN", + "SPI", + "I2C", + "RTC", + "SLEEP", + "WATCHDOG", + "FLASH" + ], + "config": { + "stdio_uart": { + "help": "default STDIO port is defined in PeripheralNames.h file, but it can be overridden, default UART_0", + "value": null + }, + "stdio_uart_tx": { + "help": "default TX STDIO pins is defined in PinNames.h file, but it can be overridden, default P0_9", + "value": null + }, + "stdio_uart_rx": { + "help": "default RX STDIO pins is defined in PinNames.h file, but it can be overridden, default P0_8", + "value": null + }, + "us_ticker_timer": { + "help": "Select which timer (0-3) to use for us_ticker.c", + "value": 1 + }, + "lp_ticker_timer": { + "help": "Select which low power timer (0-1) to use for lp_ticker.c", + "value": 1 + } + }, + "supported_application_profiles" : ["full", "bare-metal"], + "supported_c_libs": { + "arm": [ + "std", + "small" + ], + "gcc_arm": [ + "std", + "small" + ] + } + }, + "MAX32670EVKIT": { + "inherits": [ + "MAX32670" + ], + "macros_add": [ + "OPEN_DRAIN_LEDS" + ], + "extra_labels_add": [ + "MAX32670EVKIT" + ], + "detect_code": [ + "0424" + ] + }, "EFM32": { "inherits": [ "Target"