diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.cpp b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.cpp new file mode 100644 index 0000000..4e4e504 --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.cpp @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "AP3CordioHCIDriver.h" +#include "AP3CordioHCITransportDriver.h" +#include "am_mcu_apollo.h" +#include "stdio.h" +#include + +#include "wsf_types.h" +#include "wsf_timer.h" +#include "bstream.h" +#include "wsf_msg.h" +#include "wsf_cs.h" + +#include "hci_drv_apollo3.h" + +using namespace ble; + +AP3CordioHCIDriver::AP3CordioHCIDriver(CordioHCITransportDriver &transport_driver) + : CordioHCIDriver(transport_driver) +{ + AP3CordioHCITransportDriver *p_trspt_drv = (AP3CordioHCITransportDriver *)&transport_driver; + _ptr_to_handle = &p_trspt_drv->handle; +} + +AP3CordioHCIDriver::~AP3CordioHCIDriver() {} + +void AP3CordioHCIDriver::do_initialize() +{ +#ifdef USE_AMBIQ_DRIVER + HciDrvRadioBoot(true); +#else + MBED_ASSERT(*_ptr_to_handle); + _ble_config = am_hal_ble_default_config; + MBED_ASSERT(am_hal_ble_power_control(*_ptr_to_handle, AM_HAL_BLE_POWER_ACTIVE) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_ble_config(*_ptr_to_handle, &_ble_config) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_ble_boot(*_ptr_to_handle) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_ble_tx_power_set(*_ptr_to_handle, 0x0F) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_ble_sleep_set(*_ptr_to_handle, false) == AM_HAL_STATUS_SUCCESS); + am_hal_ble_int_enable(*_ptr_to_handle, (AP3_STUPID_DEF_OF_BLECIRQ_BIT | AM_HAL_BLE_INT_ICMD | AM_HAL_BLE_INT_BLECSSTAT)); + NVIC_EnableIRQ(BLE_IRQn); +#endif +} +void AP3CordioHCIDriver::do_terminate() +{ +#ifdef USE_AMBIQ_DRIVER + HciDrvRadioShutdown(); +#else + am_hal_ble_power_control(*_ptr_to_handle, AM_HAL_BLE_POWER_OFF); +#endif +} + +ble::buf_pool_desc_t AP3CordioHCIDriver::get_buffer_pool_description() +{ + static union { + uint8_t buffer[9000]; + uint64_t align; + }; + static const wsfBufPoolDesc_t pool_desc[] = { + {16, 64}, + {32, 64}, + {64, 32}, + {128, 16}, + {272, 4}}; + return buf_pool_desc_t(buffer, pool_desc); +} + +ble::CordioHCIDriver &ble_cordio_get_hci_driver() +{ + static AP3CordioHCITransportDriver transport_driver; + + static AP3CordioHCIDriver hci_driver(transport_driver); + + return hci_driver; +} diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.h b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.h new file mode 100644 index 0000000..86cd236 --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef APOLLO3_CORDIO_HCI_DRIVER_H_ +#define APOLLO3_CORDIO_HCI_DRIVER_H_ + +#include "CordioHCIDriver.h" +#include "am_mcu_apollo.h" + +namespace ble +{ + class AP3CordioHCIDriver : public CordioHCIDriver + { + public: + AP3CordioHCIDriver( + CordioHCITransportDriver &transport_driver + /* specific constructor arguments*/); + + virtual ~AP3CordioHCIDriver(); + + virtual void do_initialize(); + + virtual void do_terminate(); + + virtual ble::buf_pool_desc_t get_buffer_pool_description(); + + private: + void **_ptr_to_handle; + am_hal_ble_config_t _ble_config; + }; +} // namespace ble + +#endif /* APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_ */ diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.cpp b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.cpp new file mode 100644 index 0000000..d71c99a --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.cpp @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "AP3CordioHCITransportDriver.h" +#include "am_mcu_apollo.h" +#include "stdio.h" +#include + +#include "wsf_types.h" +#include "wsf_timer.h" +#include "bstream.h" +#include "wsf_msg.h" +#include "wsf_cs.h" + +#include "hci_drv_apollo3.h" + +#define PRINT_DEBUG_HCI 0 + +#if PRINT_DEBUG_HCI +#include "mbed.h" +DigitalOut debugGPIO(D28, 0); +DigitalOut debugGPIO2(D25, 0); +#endif + +using namespace ble; + +#ifndef USE_AMBIQ_DRIVER +static uint8_t ample_buffer[256]; +void *ble_handle = NULL; +#endif + +AP3CordioHCITransportDriver::~AP3CordioHCITransportDriver() {} + +void AP3CordioHCITransportDriver::initialize() +{ +#ifdef USE_AMBIQ_DRIVER + wsfHandlerId_t handlerId = WsfOsSetNextHandler(HciDrvHandler); + HciDrvHandlerInit(handlerId); +#else + am_hal_ble_initialize(0, &handle); + ble_handle = handle; +#endif +} + +void AP3CordioHCITransportDriver::terminate() +{ +#ifdef USE_AMBIQ_DRIVER +#else + am_hal_ble_deinitialize(handle); + handle = NULL; + ble_handle = NULL; +#endif +} + +uint16_t AP3CordioHCITransportDriver::write(uint8_t packet_type, uint16_t len, uint8_t *data) +{ +#if PRINT_DEBUG_HCI + printf("sent tx packet_type: %02X data: ", packet_type); + for (int i = 0; i < len; i++) + { + printf(" %02X", data[i]); + } + printf("\r\n"); +#endif + + //Temporary workaround, random address not working, suppress it. + if (data[0] == 0x06 && data[1] == 0x20) + { +#if PRINT_DEBUG_HCI + printf("LE Set Advertising Params\r\n"); +#endif + data[8] = 0; + } + + uint16_t retLen = 0; +#ifdef USE_AMBIQ_DRIVER + retLen = ap3_hciDrvWrite(packet_type, len, data); +#else + if (handle) + { + uint16_t retVal = (uint16_t)am_hal_ble_blocking_hci_write(handle, packet_type, (uint32_t *)data, (uint16_t)len); + if (retVal == AM_HAL_STATUS_SUCCESS) + { + retLen = len; + } + } +#endif + +#if CORDIO_ZERO_COPY_HCI + WsfMsgFree(data); +#endif + + return retLen; +} + +#ifdef USE_AMBIQ_DRIVER +//Ugly Mutlifile implementation +void CordioHCITransportDriver_on_data_received(uint8_t *data, uint16_t len) +{ +#if PRINT_DEBUG_HCI + printf("data rx: "); + for (int i = 0; i < len; i++) + { + printf("%02X ", data[i]); + } + printf("\r\n"); +#endif + CordioHCITransportDriver::on_data_received(data, len); +} +#else +extern "C" void HciDrvIntService(void) +{ + uint32_t status = am_hal_ble_int_status(ble_handle, false); + if (status & AM_HAL_BLE_INT_BLECIRQ) + { + uint32_t len = 0; + am_hal_ble_blocking_hci_read(ble_handle, (uint32_t *)ample_buffer, &len); + CordioHCITransportDriver::on_data_received(ample_buffer, len); + } + am_hal_ble_int_clear(ble_handle, 0xFFFF); +} +#endif diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.h b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.h new file mode 100644 index 0000000..55f9220 --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_ +#define APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_ + +#include "CordioHCITransportDriver.h" + +#define AP3_STUPID_DEF_OF_BLECIRQ_BIT 0x00000080 // AM_BLEIF_INT_BLECIRQ + +namespace ble +{ + class AP3CordioHCITransportDriver : public CordioHCITransportDriver + { + public: + //AP3CordioHCITransportDriver(/* specific constructor arguments*/); + + virtual ~AP3CordioHCITransportDriver(); + + virtual void initialize(); + + virtual void terminate(); + + virtual uint16_t write(uint8_t packet_type, uint16_t len, uint8_t *data); + + void *handle; + + private: + // private driver declarations + }; +} // namespace ble + +extern "C" void CordioHCITransportDriver_on_data_received(uint8_t *data, uint16_t len); + +#endif /* APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_ */ diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.c b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.c new file mode 100644 index 0000000..79ab1a2 --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.c @@ -0,0 +1,1330 @@ +//***************************************************************************** +// +//! @file hci_drv_apollo3.c +//! +//! @brief HCI driver interface. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#if USE_AMBIQ_DRIVER + +#include +#include + +#include "wsf_types.h" +#include "wsf_timer.h" +#include "bstream.h" +#include "wsf_msg.h" +#include "wsf_cs.h" +#include "hci_core.h" +#include "dm_api.h" +#include "am_mcu_apollo.h" +#include "am_util.h" +#include "hci_drv_apollo3.h" + +#include +#include "stdio.h" + +extern void CordioHCITransportDriver_on_data_received(uint8_t *data, uint16_t len); + +//***************************************************************************** +// +// Use the interrupt-driven HCI driver? +// +//***************************************************************************** +#define USE_NONBLOCKING_HCI 1 +#define SKIP_FALLING_EDGES 0 + +//***************************************************************************** +// +// Enable the heartbeat command? +// +// Setting this to 1 will cause the MCU to send occasional HCI packets to the +// BLE core if there hasn't been any activity for a while. This can help catch +// communication issues that might otherwise go unnoticed. +// +//***************************************************************************** +#define ENABLE_BLE_HEARTBEAT 1 + +//***************************************************************************** +// +// Configurable buffer sizes. +// +//***************************************************************************** +#define NUM_HCI_WRITE_BUFFERS 8 +#define HCI_DRV_MAX_TX_PACKET 256 +#define HCI_DRV_MAX_RX_PACKET 256 + +//***************************************************************************** +// +// Configurable error-detection thresholds. +// +//***************************************************************************** +#define HEARTBEAT_TIMEOUT_MS (10000) //milli-seconds +#define HCI_DRV_MAX_IRQ_TIMEOUT 2000 +#define HCI_DRV_MAX_XTAL_RETRIES 10 +#define HCI_DRV_MAX_TX_RETRIES 10000 +#define HCI_DRV_MAX_HCI_TRANSACTIONS 10000 +#define HCI_DRV_MAX_READ_PACKET 4 // max read in a row at a time + +//***************************************************************************** +// +// Structure for holding outgoing HCI packets. +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32Length; + uint32_t pui32Data[HCI_DRV_MAX_TX_PACKET / 4]; +} +hci_drv_write_t; + +//***************************************************************************** +// +// Heartbeat implementation functions. +// +//***************************************************************************** +#if ENABLE_BLE_HEARTBEAT + +#define BLE_HEARTBEAT_START() \ + do { WsfTimerStartMs(&g_HeartBeatTimer, HEARTBEAT_TIMEOUT_MS); } while (0) + +#define BLE_HEARTBEAT_STOP() \ + do { WsfTimerStop(&g_HeartBeatTimer); } while (0) + +#define BLE_HEARTBEAT_RESTART() \ + do \ + { \ + WsfTimerStop(&g_HeartBeatTimer); \ + WsfTimerStartMs(&g_HeartBeatTimer, HEARTBEAT_TIMEOUT_MS); \ + } while (0) + +#else + +#define BLE_HEARTBEAT_START() +#define BLE_HEARTBEAT_STOP() +#define BLE_HEARTBEAT_RESTART() + +#endif + +//***************************************************************************** +// +// Global variables. +// +//***************************************************************************** + +// BLE module handle +void *BLE; + +//fixme: set the BLE MAC address to a special value +uint8_t g_BLEMacAddress[6] = {0x01,0x02,0x03,0x04,0x05,0x06}; + +// Global handle used to send BLE events about the Hci driver layer. +wsfHandlerId_t g_HciDrvHandleID = 0; +wsfTimer_t g_HeartBeatTimer; +wsfTimer_t g_WakeTimer; + +// Buffers for HCI write data. +hci_drv_write_t g_psWriteBuffers[NUM_HCI_WRITE_BUFFERS]; +am_hal_queue_t g_sWriteQueue; + +// Buffers for HCI read data. +uint32_t g_pui32ReadBuffer[HCI_DRV_MAX_RX_PACKET / 4]; +uint8_t *g_pui8ReadBuffer = (uint8_t *) g_pui32ReadBuffer; +volatile bool bReadBufferInUse = false; + +uint32_t g_ui32NumBytes = 0; +uint32_t g_consumed_bytes = 0; + +// Counters for tracking read data. +volatile uint32_t g_ui32InterruptsSeen = 0; + +void HciDrvEmptyWriteQueue(void); +//***************************************************************************** +// +// Forward declarations for HCI callbacks. +// +//***************************************************************************** +#if USE_NONBLOCKING_HCI +void hciDrvWriteCallback(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext); +void hciDrvReadCallback(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext); +#endif // USE_NONBLOCKING_HCI + +//***************************************************************************** +// +// Events for the HCI driver interface. +// +//***************************************************************************** +#define BLE_TRANSFER_NEEDED_EVENT 0x01 +#define BLE_HEARTBEAT_EVENT 0x02 +#define BLE_SET_WAKEUP 0x03 + +//***************************************************************************** +// +// Error-handling wrapper macro. +// +//***************************************************************************** +#define ERROR_CHECK_VOID(status) \ + { \ + uint32_t ui32ErrChkStatus; \ + if (0 != (ui32ErrChkStatus = (status))) \ + { \ + am_util_debug_printf("ERROR_CHECK_VOID "#status "\n"); \ + error_check(ui32ErrChkStatus); \ + return; \ + } \ + } + +#define ERROR_RETURN(status, retval) \ + if ((status)) \ + { \ + error_check(status); \ + return (retval); \ + } + +#define ERROR_RECOVER(status) \ + if ((status)) \ + { \ + am_hal_debug_gpio_toggle(BLE_DEBUG_TRACE_10); \ + error_check(status); \ + HciDrvRadioShutdown(); \ + HciDrvRadioBoot(0); \ + HciDrvEmptyWriteQueue(); \ + DmDevReset(); \ + return; \ + } + +//***************************************************************************** +// +// Debug section. +// +//***************************************************************************** +#if 0 +#define CRITICAL_PRINT(...) \ + do \ + { \ + AM_CRITICAL_BEGIN; \ + am_util_debug_printf(__VA_ARGS__); \ + AM_CRITICAL_END; \ + } while (0) +#else +#if 0 +#define CRITICAL_PRINT(...) printf(__VA_ARGS__); +#endif +#define CRITICAL_PRINT(...) +#endif + +#define ENABLE_IRQ_PIN 0 + +#define TASK_LEVEL_DELAYS 0 + + +//***************************************************************************** +// +// Function pointer for redirecting errors +// +//***************************************************************************** +hci_drv_error_handler_t g_hciDrvErrorHandler = 0; +static uint32_t g_ui32FailingStatus = 0; + +//***************************************************************************** +// +// By default, errors will be printed. If there is an error handler defined, +// they will be sent there intead. +// +//***************************************************************************** +static void +error_check(uint32_t ui32Status) +{ + // + // Don't do anything unless there's an error. + // + if (ui32Status) + { + // + // Set the global error status. If there's an error handler function, + // call it. Otherwise, just print the error status and wait. + // + g_ui32FailingStatus = ui32Status; + + if (g_hciDrvErrorHandler) + { + g_hciDrvErrorHandler(g_ui32FailingStatus); + } + else + { + CRITICAL_PRINT("Error detected: 0x%08x\n", g_ui32FailingStatus); + CRITICAL_PRINT("BSTATUS: 0x%08x\n", BLEIF->BSTATUS); + } + } +} + +//***************************************************************************** +// +// Other useful macros. +// +//***************************************************************************** + +#define BLE_IRQ_CHECK() (BLEIF->BSTATUS_b.BLEIRQ) + +// Ellisys HCI SPI tapping support + +// #define ELLISYS_HCI_LOG_SUPPORT 1 + +//***************************************************************************** +// +// Boot the radio. +// +//***************************************************************************** +void +HciDrvRadioBoot(bool bColdBoot) +{ + uint32_t ui32NumXtalRetries = 0; + + + g_ui32NumBytes = 0; + g_consumed_bytes = 0; +#if !defined(AM_DEBUG_BLE_TIMING) && defined(ELLISYS_HCI_LOG_SUPPORT) + am_hal_gpio_pincfg_t pincfg = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + pincfg.uFuncSel = 6; + am_hal_gpio_pinconfig(30, pincfg); + am_hal_gpio_pinconfig(31, pincfg); + am_hal_gpio_pinconfig(32, pincfg); + pincfg.uFuncSel = 4; + am_hal_gpio_pinconfig(33, pincfg); + pincfg.uFuncSel = 7; + am_hal_gpio_pinconfig(35, pincfg); +#endif + +#ifdef AM_DEBUG_BLE_TIMING + // + // Enable debug pins. + // + // 30.6 - SCLK + // 31.6 - MISO + // 32.6 - MOSI + // 33.4 - CSN + // 35.7 - SPI_STATUS + // + am_hal_gpio_pincfg_t pincfg = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + pincfg.uFuncSel = 6; + am_hal_gpio_pinconfig(30, pincfg); + am_hal_gpio_pinconfig(31, pincfg); + am_hal_gpio_pinconfig(32, pincfg); + pincfg.uFuncSel = 4; + am_hal_gpio_pinconfig(33, pincfg); + pincfg.uFuncSel = 7; + am_hal_gpio_pinconfig(35, pincfg); + pincfg.uFuncSel = 1; +#if ENABLE_IRQ_PIN + am_hal_gpio_pinconfig(41, pincfg); + am_hal_debug_gpio_pinconfig(BLE_DEBUG_TRACE_08); +#endif + + am_hal_gpio_pinconfig(11, g_AM_HAL_GPIO_OUTPUT); + +#endif // AM_DEBUG_BLE_TIMING + + // + // This pin is also used to generate BLE interrupts in the current + // implementation. + // + // 41.1 - BLE IRQ + // + //am_hal_gpio_pin_config(41, AM_HAL_GPIO_FUNC(1)); + + + // + // Configure and enable the BLE interface. + // + uint32_t ui32Status = AM_HAL_STATUS_FAIL; + while (ui32Status != AM_HAL_STATUS_SUCCESS) + { + ERROR_CHECK_VOID(am_hal_ble_initialize(0, &BLE)); + ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_ACTIVE)); + + am_hal_ble_config_t sBleConfig = + { + // Configure the HCI interface clock for 6 MHz + .ui32SpiClkCfg = AM_HAL_BLE_HCI_CLK_DIV8, + + // Set HCI read and write thresholds to 32 bytes each. + .ui32ReadThreshold = 32, + .ui32WriteThreshold = 32, + + // The MCU will supply the clock to the BLE core. + .ui32BleClockConfig = AM_HAL_BLE_CORE_MCU_CLK, +#if 0 + // Default settings for expected BLE clock drift (measured in PPM). + .ui32ClockDrift = 0, + .ui32SleepClockDrift = 50, + + // Default setting - AGC Enabled + .bAgcEnabled = true, + + // Default setting - Sleep Algo enabled + .bSleepEnabled = true, +#endif + // Apply the default patches when am_hal_ble_boot() is called. + .bUseDefaultPatches = true, + }; + + ERROR_CHECK_VOID(am_hal_ble_config(BLE, &sBleConfig)); + // + // Delay 1s for 32768Hz clock stability. This isn't required unless this is + // our first run immediately after a power-up. + // + if ( bColdBoot ) + { + am_util_delay_ms(1000); + } + // + // Attempt to boot the radio. + // + ui32Status = am_hal_ble_boot(BLE); + + // + // Check our status. + // + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + // + // If the radio is running, we can exit this loop. + // + break; + } + else if (ui32Status == AM_HAL_BLE_32K_CLOCK_UNSTABLE) + { + // + // If the radio is running, but the clock looks bad, we can try to + // restart. + // + ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_OFF)); + ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLE)); + + // + // We won't restart forever. After we hit the maximum number of + // retries, we'll just return with failure. + // + if (ui32NumXtalRetries++ < HCI_DRV_MAX_XTAL_RETRIES) + { + am_util_delay_ms(1000); + } + else + { + return; + } + } + else + { + ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_OFF)); + ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLE)); + // + // If the radio failed for some reason other than 32K Clock + // instability, we should just report the failure and return. + // + error_check(ui32Status); + return; + } + } + + // + // Set the BLE TX Output power to 0dBm. + // + am_hal_ble_tx_power_set(BLE, 0x8); + + // + // Enable interrupts for the BLE module. + // +#if USE_NONBLOCKING_HCI + am_hal_ble_int_clear(BLE, (AM_HAL_BLE_INT_CMDCMP | + AM_HAL_BLE_INT_DCMP | + AM_HAL_BLE_INT_BLECIRQ | + AM_HAL_BLE_INT_BLECSSTAT)); + + am_hal_ble_int_enable(BLE, (AM_HAL_BLE_INT_CMDCMP | + AM_HAL_BLE_INT_DCMP | + AM_HAL_BLE_INT_BLECIRQ | + AM_HAL_BLE_INT_BLECSSTAT)); + +#if SKIP_FALLING_EDGES +#else + if (APOLLO3_GE_B0) + { + am_hal_ble_int_clear(BLE, (AM_HAL_BLE_INT_BLECIRQN | + AM_HAL_BLE_INT_BLECSSTATN)); + + am_hal_ble_int_enable(BLE, (AM_HAL_BLE_INT_BLECIRQN | + AM_HAL_BLE_INT_BLECSSTATN)); + } +#endif + +#else + + am_hal_ble_int_clear(BLE, (AM_HAL_BLE_INT_CMDCMP | + AM_HAL_BLE_INT_DCMP | + AM_HAL_BLE_INT_BLECIRQ)); + + am_hal_ble_int_enable(BLE, (AM_HAL_BLE_INT_CMDCMP | + AM_HAL_BLE_INT_DCMP | + AM_HAL_BLE_INT_BLECIRQ)); +#endif + + CRITICAL_PRINT("INTEN: %d\n", BLEIF->INTEN_b.BLECSSTAT); + CRITICAL_PRINT("INTENREG: %d\n", BLEIF->INTEN); + + NVIC_EnableIRQ(BLE_IRQn); + + // + // Initialize a queue to help us keep track of HCI write buffers. + // + am_hal_queue_from_array(&g_sWriteQueue, g_psWriteBuffers); + + //WsfSetEvent(g_HciDrvHandleID, BLE_HEARTBEAT_EVENT); + // + // Reset the RX interrupt counter. + // + g_ui32InterruptsSeen = 0; + + return; +} + +//***************************************************************************** +// +// Shut down the BLE core. +// +//***************************************************************************** +void +HciDrvRadioShutdown(void) +{ + BLE_HEARTBEAT_STOP(); + + NVIC_DisableIRQ(BLE_IRQn); + + ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_OFF)); + + while ( PWRCTRL->DEVPWREN_b.PWRBLEL ) + { + } + + ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLE)); + + g_ui32NumBytes = 0; + g_consumed_bytes = 0; +} + +#if USE_NONBLOCKING_HCI +//***************************************************************************** +// +// Short Description. +// +//***************************************************************************** +static void +update_wake(void) +{ + AM_CRITICAL_BEGIN; + + // + // We want to set WAKE if there's something in the write queue, but not if + // SPISTATUS or IRQ is high. + // + if ( !am_hal_queue_empty(&g_sWriteQueue) && + (BLEIFn(0)->BSTATUS_b.SPISTATUS == 0) && + (BLE_IRQ_CHECK() == false)) + { + am_hal_ble_wakeup_set(BLE, 1); + + // + // If we've set wakeup, but IRQ came up at the same time, we should + // just lower WAKE again. + // + if (BLE_IRQ_CHECK() == true) + { + am_hal_ble_wakeup_set(BLE, 0); + } + } + + AM_CRITICAL_END; +} +#endif + +//***************************************************************************** +// +// Function used by the BLE stack to send HCI messages to the BLE controller. +// +// Internally, the Cordio BLE stack will allocate memory for an HCI message, +// +//***************************************************************************** +uint16_t +ap3_hciDrvWrite(uint8_t type, uint16_t len, uint8_t *pData) +{ + uint8_t *pui8Wptr; + hci_drv_write_t *psWriteBuffer; + + + // + // Check to see if we still have buffer space. + // + if (am_hal_queue_full(&g_sWriteQueue)) + { + CRITICAL_PRINT("ERROR: Ran out of HCI transmit queue slots.\n"); + ERROR_RETURN(HCI_DRV_TRANSMIT_QUEUE_FULL, len); + } + + if (len > (HCI_DRV_MAX_TX_PACKET-1)) // comparison compensates for the type byte at index 0. + { + CRITICAL_PRINT("ERROR: Trying to send an HCI packet larger than the hci driver buffer size (needs %d bytes of space).\n", + len); + + ERROR_RETURN(HCI_DRV_TX_PACKET_TOO_LARGE, len); + } + + // + // Get a pointer to the next item in the queue. + // + psWriteBuffer = am_hal_queue_next_slot(&g_sWriteQueue); + + // + // Set all of the fields in the hci write structure. + // + psWriteBuffer->ui32Length = len + 1; + + pui8Wptr = (uint8_t *) psWriteBuffer->pui32Data; + + *pui8Wptr++ = type; + + for (uint32_t i = 0; i < len; i++) + { + pui8Wptr[i] = pData[i]; + } + + // + // Advance the queue. + // + am_hal_queue_item_add(&g_sWriteQueue, 0, 1); + +#if USE_NONBLOCKING_HCI + // + // Wake up the BLE controller. + // + CRITICAL_PRINT("INFO: HCI write requested.\n"); + + update_wake(); + +#else + // + // Send an event to the BLE transfer handler function. + // + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); +#endif + +#ifdef AM_CUSTOM_BDADDR + if (type == HCI_CMD_TYPE) + { + uint16_t opcode; + BYTES_TO_UINT16(opcode, pData); + + if (HCI_OPCODE_RESET == opcode) + { + + extern uint8_t g_BLEMacAddress[6]; + am_hal_mcuctrl_device_t sDevice; + am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_DEVICEID, &sDevice); + g_BLEMacAddress[0] = sDevice.ui32ChipID0; + g_BLEMacAddress[1] = sDevice.ui32ChipID0 >> 8; + g_BLEMacAddress[2] = sDevice.ui32ChipID0 >> 16; + + HciVendorSpecificCmd(0xFC32, 6, g_BLEMacAddress); + } + } +#endif + + return len; +} + +//***************************************************************************** +// +// Save the handler ID of the HciDrvHandler so we can send it events through +// the WSF task system. +// +// Note: These two lines need to be added to the exactle initialization +// function at the beginning of all Cordio applications: +// +// handlerId = WsfOsSetNextHandler(HciDrvHandler); +// HciDrvHandler(handlerId); +// +//***************************************************************************** +void +HciDrvHandlerInit(wsfHandlerId_t handlerId) +{ + g_HciDrvHandleID = handlerId; + + g_HeartBeatTimer.handlerId = handlerId; + g_HeartBeatTimer.msg.event = BLE_HEARTBEAT_EVENT; + + g_WakeTimer.handlerId = handlerId; + g_WakeTimer.msg.event = BLE_SET_WAKEUP; +} + +//***************************************************************************** +// +// Simple interrupt handler to call +// +// Note: These two lines need to be added to the exactle initialization +// function at the beginning of all Cordio applications: +// +// handlerId = WsfOsSetNextHandler(HciDrvHandler); +// HciDrvHandler(handlerId); +// +//***************************************************************************** +void +HciDrvIntService(void) +{ +#if AM_DEBUG_BLE_TIMING + am_hal_gpio_state_write(11, AM_HAL_GPIO_OUTPUT_SET); +#endif + + // + // Read and clear the interrupt status. + // + uint32_t ui32Status = am_hal_ble_int_status(BLE, true); + am_hal_ble_int_clear(BLE, ui32Status); + +#if USE_NONBLOCKING_HCI + // + // Handle any DMA or Command Complete interrupts. + // + am_hal_ble_int_service(BLE, ui32Status); + + // + // If this was a BLEIRQ interrupt, attempt to start a read operation. If it + // was a STATUS interrupt, start a write operation. + // + if (ui32Status & AM_HAL_BLE_INT_BLECIRQ) + { + // CRITICAL_PRINT("INFO: IRQ INTERRUPT\n"); + + // + // Lower WAKE + // + //WsfTimerStop(&g_WakeTimer); + // CRITICAL_PRINT("IRQ Drop\n"); + am_hal_ble_wakeup_set(BLE, 0); + + // + // Prepare to read a message. + // + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + } + else if (ui32Status & AM_HAL_BLE_INT_BLECSSTAT) + { + // CRITICAL_PRINT("INFO: STATUS INTERRUPT\n"); + + // + // Check the queue and send the first message we have. + // + if ( !am_hal_queue_empty(&g_sWriteQueue) ) + { + uint32_t ui32WriteStatus = 0; + + hci_drv_write_t *psWriteBuffer = am_hal_queue_peek(&g_sWriteQueue); + + ui32WriteStatus = + am_hal_ble_nonblocking_hci_write(BLE, + AM_HAL_BLE_RAW, + psWriteBuffer->pui32Data, + psWriteBuffer->ui32Length, + hciDrvWriteCallback, + 0); + + // + // If it succeeded, we can pop the queue. + // + if (ui32WriteStatus == AM_HAL_STATUS_SUCCESS) + { + BLE_HEARTBEAT_RESTART(); + // CRITICAL_PRINT("INFO: HCI write sent.\n"); + } + else + { + // CRITICAL_PRINT("INFO: HCI write failed: %d\n", ui32WriteStatus); + } + } + } + +#else + // + // Advance an event counter to make sure we're keeping track of edges + // correctly. + // + g_ui32InterruptsSeen++; + + // + // Send an event to get processed in the HCI handler. + // + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); +#endif + +#if AM_DEBUG_BLE_TIMING + am_hal_gpio_state_write(11, AM_HAL_GPIO_OUTPUT_CLEAR); +#endif +} + +#if USE_NONBLOCKING_HCI + +//***************************************************************************** +// +// This function determines what to do when a write operation completes. +// +//***************************************************************************** +void +hciDrvWriteCallback(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext) +{ + CRITICAL_PRINT("INFO: HCI physical write complete.\n"); + + am_hal_queue_item_get(&g_sWriteQueue, 0, 1); + +#if TASK_LEVEL_DELAYS + + // Set a WSF timer to update wake later. + WsfTimerStartMs(&g_WakeTimer, 30); + +#else // TASK_LEVEL_DELAYS + + while ( BLEIFn(0)->BSTATUS_b.SPISTATUS ) + { + am_util_delay_us(5); + } + + // + // Check the write queue, and possibly set wake again. + // + if ( !am_hal_queue_empty(&g_sWriteQueue) ) + { + // + // In this case, we need to delay before setting wake. Instead of + // delaying here, we'll post an event to do it later. + // + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + } + +#endif // TASK_LEVEL_DELAYS +} + +//***************************************************************************** +// +// This function determines what to do when a read operation completes. +// +//***************************************************************************** +void +hciDrvReadCallback(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext) +{ + // + // Set a "transfer needed" event. + // + // CRITICAL_PRINT("INFO: HCI physical read complete.\n"); + g_ui32NumBytes = ui32Length; + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + +#if TASK_LEVEL_DELAYS + + // Set a WSF timer to update wake later. + WsfTimerStartMs(&g_WakeTimer, 30); + +#else // TASK_LEVEL_DELAYS + + while ( BLE_IRQ_CHECK() ) + { + am_util_delay_us(5); + } + + // + // Check the write queue, and possibly set wake. + // + if ( !am_hal_queue_empty(&g_sWriteQueue) ) + { + am_hal_ble_wakeup_set(BLE, 1); + } + +#endif // TASK_LEVEL_DELAYS +} + +//***************************************************************************** +// +// Event handler for HCI-related events. +// +// This handler can perform HCI reads or writes, and keeps the actions in the +// correct order. +// +//***************************************************************************** +void +HciDrvHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg) +{ + uint32_t ui32ErrorStatus; + + // + // If this handler was called in response to a heartbeat event, then it's + // time to run a benign HCI command. Normally, the BLE controller should + // handle this command without issue. If it doesn't acknowledge the + // command, we will eventually get an HCI command timeout error, which will + // alert us to the fact that the BLE core has become unresponsive in + // general. + // + if (pMsg->event == BLE_HEARTBEAT_EVENT) + { + HciReadLocalVerInfoCmd(); + BLE_HEARTBEAT_START(); + return; + } + + if (pMsg->event == BLE_SET_WAKEUP) + { + // + // Attempt to set WAKE again. + // + update_wake(); + return; + } + + // + // Check to see if we read any bytes over the HCI interface that we haven't + // already sent to the BLE stack. + // + if (g_ui32NumBytes > g_consumed_bytes) + { + CRITICAL_PRINT("INFO: HCI data transferred to stack.\n"); + // + // If we have any bytes saved, we should send them to the BLE stack + // now. + // + CordioHCITransportDriver_on_data_received(g_pui8ReadBuffer + g_consumed_bytes, + g_ui32NumBytes - g_consumed_bytes); + g_consumed_bytes = g_ui32NumBytes; + //g_consumed_bytes += hciTrSerialRxIncoming(g_pui8ReadBuffer + g_consumed_bytes, + // g_ui32NumBytes - g_consumed_bytes); + + // + // If the stack doesn't accept all of the bytes we had, we will need to + // keep the event set and come back later. Otherwise, we can just reset + // our variables and exit the loop. + // + if (g_consumed_bytes != g_ui32NumBytes) + { + CRITICAL_PRINT("INFO: HCI data split up.\n"); + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + return; + } + else + { + CRITICAL_PRINT("INFO: HCI RX packet complete.\n"); + g_ui32NumBytes = 0; + g_consumed_bytes = 0; + bReadBufferInUse = false; + } + } + + if ( BLE_IRQ_CHECK() ) + { + if (bReadBufferInUse == true) + { + CRITICAL_PRINT("Read buffer already in use.\n"); + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + return; + } + + // + // If the stack has used up all of the saved data we've accumulated so + // far, we should check to see if we need to read any *new* data. + // + CRITICAL_PRINT("INFO: HCI Read started.\n"); + bReadBufferInUse = true; + ui32ErrorStatus = am_hal_ble_nonblocking_hci_read(BLE, + g_pui32ReadBuffer, + hciDrvReadCallback, + 0); + + BLE_HEARTBEAT_RESTART(); + + if (g_ui32NumBytes > HCI_DRV_MAX_RX_PACKET) + { + CRITICAL_PRINT("ERROR: Trying to receive an HCI packet " + "larger than the hci driver buffer size " + "(needs %d bytes of space).\n", + g_ui32NumBytes); + + ERROR_CHECK_VOID(HCI_DRV_RX_PACKET_TOO_LARGE); + } + + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + // + // If the read didn't succeed for some physical reason, we need + // to know. We shouldn't get failures here. We checked the IRQ + // signal before calling the read function, and this driver + // only contains a single call to the blocking read function, + // so there shouldn't be any physical reason for the read to + // fail. + // + CRITICAL_PRINT("HCI READ failed with status %d. " + "Try recording with a logic analyzer " + "to catch the error.\n", + ui32ErrorStatus); + + ERROR_RECOVER(ui32ErrorStatus); + } + } +} +#else +//***************************************************************************** +// +// Event handler for HCI-related events. +// +// This handler can perform HCI reads or writes, and keeps the actions in the +// correct order. +// +//***************************************************************************** +void +HciDrvHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg) +{ + uint32_t ui32ErrorStatus, ui32TxRetries = 0; + uint32_t ui32NumHciTransactions = 0; + uint32_t read_hci_packet_count = 0; + + // + // If this handler was called in response to a heartbeat event, then it's + // time to run a benign HCI command. Normally, the BLE controller should + // handle this command without issue. If it doesn't acknowledge the + // command, we will eventually get an HCI command timeout error, which will + // alert us to the fact that the BLE core has become unresponsive in + // general. + // + if (pMsg->event == BLE_HEARTBEAT_EVENT) + { + HciReadLocalVerInfoCmd(); + BLE_HEARTBEAT_START(); + return; + } + + // + // Check to see if we read any bytes over the HCI interface that we haven't + // already sent to the BLE stack. + // + if (g_ui32NumBytes > g_consumed_bytes) + { + // + // If we have any bytes saved, we should send them to the BLE stack + // now. + // + CordioHCITransportDriver_on_data_received(g_pui8ReadBuffer + g_consumed_bytes, + g_ui32NumBytes - g_consumed_bytes); + g_consumed_bytes = g_ui32NumBytes; + // g_consumed_bytes += hciTrSerialRxIncoming(g_pui8ReadBuffer + g_consumed_bytes, + // g_ui32NumBytes - g_consumed_bytes); + + // + // If the stack doesn't accept all of the bytes we had, + // + if (g_consumed_bytes != g_ui32NumBytes) + { + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + return; + } + else + { + g_ui32NumBytes = 0; + g_consumed_bytes = 0; + } + } + + am_hal_debug_gpio_set(BLE_DEBUG_TRACE_01); + + // + // Loop indefinitely, checking to see if there are still tranfsers we need + // to complete. + // + while (ui32NumHciTransactions++ < HCI_DRV_MAX_HCI_TRANSACTIONS) + { + // + // Figure out what kind of transfer the BLE core will accept. + // + if ( BLE_IRQ_CHECK() ) + { + uint32_t ui32OldInterruptsSeen = g_ui32InterruptsSeen; + + am_hal_debug_gpio_set(BLE_DEBUG_TRACE_02); + + BLE_HEARTBEAT_RESTART(); + + // + // Is the BLE core asking for a read? If so, do that now. + // + g_ui32NumBytes = 0; + ui32ErrorStatus = am_hal_ble_blocking_hci_read(BLE, (uint32_t*)g_pui32ReadBuffer, &g_ui32NumBytes); + + if (g_ui32NumBytes > HCI_DRV_MAX_RX_PACKET) + { + CRITICAL_PRINT("ERROR: Trying to receive an HCI packet larger than the hci driver buffer size (needs %d bytes of space).", + g_ui32NumBytes); + + ERROR_CHECK_VOID(HCI_DRV_RX_PACKET_TOO_LARGE); + } + + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS) + { + + // + // If the read succeeded, we need to wait for the IRQ signal to + // go back down. If we don't we might inadvertently try to read + // the same packet twice. + // + uint32_t ui32IRQRetries; + for (ui32IRQRetries = 0; ui32IRQRetries < HCI_DRV_MAX_IRQ_TIMEOUT; ui32IRQRetries++) + { + if (BLE_IRQ_CHECK() == 0 || g_ui32InterruptsSeen != ui32OldInterruptsSeen) + { + break; + } + + am_util_delay_us(1); + } + + // + // Pass the data along to the stack. The stack should be able + // to read as much data as we send it. If it can't, we need to + // know that. + // + + CordioHCITransportDriver_on_data_received(g_pui8ReadBuffer, g_ui32NumBytes); + g_consumed_bytes = g_ui32NumBytes; + // g_consumed_bytes = hciTrSerialRxIncoming(g_pui8ReadBuffer, g_ui32NumBytes); + if (g_consumed_bytes != g_ui32NumBytes) + { + + // need to come back again + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + // take a break now + + // worst case disable BLE_IRQ + break; + } + + g_ui32NumBytes = 0; + g_consumed_bytes = 0; + + read_hci_packet_count++; + } + else + { + // + // If the read didn't succeed for some physical reason, we need + // to know. We shouldn't get failures here. We checked the IRQ + // signal before calling the read function, and this driver + // only contains a single call to the blocking read function, + // so there shouldn't be any physical reason for the read to + // fail. + // + CRITICAL_PRINT("HCI READ failed with status %d. Try recording with a logic analyzer to catch the error.\n", + ui32ErrorStatus); + + ERROR_RECOVER(ui32ErrorStatus); + } + + am_hal_debug_gpio_clear(BLE_DEBUG_TRACE_02); + + if (read_hci_packet_count >= HCI_DRV_MAX_READ_PACKET) + { + // It looks like there's time that we won't get interrupt even though + // there's packet waiting for host to grab. + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + + break; + } + + } + else + { + // + // If we don't have anything to read, we can start checking to see + // if we have things to write. + // + if (am_hal_queue_empty(&g_sWriteQueue)) + { + // + // If not, we're done! + // + break; + } + else + { + // + // If we do have something to write, just pop a single item + // from the queue and send it. + // + am_hal_debug_gpio_set(BLE_DEBUG_TRACE_07); + hci_drv_write_t *psWriteBuffer = am_hal_queue_peek(&g_sWriteQueue); + + ui32ErrorStatus = am_hal_ble_blocking_hci_write(BLE, + AM_HAL_BLE_RAW, + psWriteBuffer->pui32Data, + psWriteBuffer->ui32Length); + + // + // If we managed to actually send a packet, we can go ahead and + // advance the queue. + // + if (ui32ErrorStatus == AM_HAL_STATUS_SUCCESS) + { + // + // Restart the heartbeat timer. + // + BLE_HEARTBEAT_RESTART(); + + am_hal_queue_item_get(&g_sWriteQueue, 0, 1); + + ui32TxRetries = 0; + // Resetting the cumulative count + ui32NumHciTransactions = 0; + } + else + { + // + // If we fail too many times in a row, we should throw an + // error to avoid a lock-up. + // + ui32TxRetries++; + + if (ui32TxRetries > HCI_DRV_MAX_TX_RETRIES) + { + // we need to come back again later. + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + break; + } + } + + } + } + } + + if (ui32NumHciTransactions == HCI_DRV_MAX_HCI_TRANSACTIONS) + { + CRITICAL_PRINT("ERROR: Maximum number of successive HCI transactions exceeded.\n"); + ERROR_RECOVER(HCI_DRV_TOO_MANY_PACKETS); + } + + am_hal_debug_gpio_clear(BLE_DEBUG_TRACE_01); +} +#endif + +//***************************************************************************** +// +// Register an error handler for the HCI driver. +// +//***************************************************************************** +void +HciDrvErrorHandlerSet(hci_drv_error_handler_t pfnErrorHandler) +{ + g_hciDrvErrorHandler = pfnErrorHandler; +} + +/*************************************************************************************************/ +/*! + * \fn HciVsA3_SetRfPowerLevelEx + * + * \brief Vendor specific command for settting Radio transmit power level + * for Nationz. + * + * \param txPowerlevel valid range from 0 to 15 in decimal. + * + * \return true when success, otherwise false + */ +/*************************************************************************************************/ +bool_t +HciVsA3_SetRfPowerLevelEx(txPowerLevel_t txPowerlevel) +{ + switch (txPowerlevel) { + + case TX_POWER_LEVEL_MINUS_10P0_dBm: + am_hal_ble_tx_power_set(BLE,0x04); + return true; + break; + case TX_POWER_LEVEL_0P0_dBm: + am_hal_ble_tx_power_set(BLE,0x08); + return true; + break; + case TX_POWER_LEVEL_PLUS_3P0_dBm: + am_hal_ble_tx_power_set(BLE,0x0F); + return true; + break; + default: + return false; + break; + } +} + +/*************************************************************************************************/ +/*! + * \fn HciDrvBleSleepSet + * + * \brief Set BLE sleep enable/disable for the BLE core. + * + * \param enable 'true' set sleep enable, 'false' set sleep disable + * + * \return none + */ +/*************************************************************************************************/ +void +HciDrvBleSleepSet(bool enable) +{ + am_hal_ble_sleep_set(BLE, enable); +} + +//***************************************************************************** +// +// Clear the HCI write queue +// +//***************************************************************************** +void +HciDrvEmptyWriteQueue(void) +{ + am_hal_queue_from_array(&g_sWriteQueue, g_psWriteBuffers); +} + +#endif diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.h b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.h new file mode 100644 index 0000000..6fab822 --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +//! @file hci_drv_apollo3.h +//! +//! @brief Support functions for the Nationz BTLE radio in Apollo3. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.3.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef HCI_DRV_APOLLO3_H +#define HCI_DRV_APOLLO3_H + +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** + // + // NATIONZ vendor specific events + // + //***************************************************************************** + + // Tx power level in dBm. + typedef enum + { + TX_POWER_LEVEL_MINUS_10P0_dBm = 0x3, + TX_POWER_LEVEL_0P0_dBm = 0x8, + TX_POWER_LEVEL_PLUS_3P0_dBm = 0xF, + TX_POWER_LEVEL_INVALID = 0x10, + } txPowerLevel_t; + +#define HCI_DRV_SPECIFIC_ERROR_START 0x09000000 + typedef enum + { + HCI_DRV_TRANSMIT_QUEUE_FULL = HCI_DRV_SPECIFIC_ERROR_START, + HCI_DRV_TX_PACKET_TOO_LARGE, + HCI_DRV_RX_PACKET_TOO_LARGE, + HCI_DRV_BLE_STACK_UNABLE_TO_ACCEPT_PACKET, + HCI_DRV_PACKET_TRANSMIT_FAILED, + HCI_DRV_IRQ_STUCK_HIGH, + HCI_DRV_TOO_MANY_PACKETS, + } hci_drv_error_t; + + typedef void (*hci_drv_error_handler_t)(uint32_t ui32Error); + + bool_t HciVsA3_SetRfPowerLevelEx(txPowerLevel_t txPowerlevel); + void HciVsA3_ConstantTransmission(uint8_t txchannel); + void HciVsA3_CarrierWaveMode(uint8_t txchannel); + + //***************************************************************************** + // + // Hci driver functions unique to Apollo3 + // + //***************************************************************************** + extern void HciDrvHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg); + extern void HciDrvHandlerInit(wsfHandlerId_t handlerId); + extern void HciDrvIntService(void); + + uint16_t ap3_hciDrvWrite(uint8_t type, uint16_t len, uint8_t *pData); + + extern void HciDrvRadioBoot(bool bColdBoot); + extern void HciDrvRadioShutdown(void); + +#ifdef __cplusplus +}; +#endif + +#endif // HCI_DRV_APOLLO3_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.c new file mode 100644 index 0000000..d28ba41 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.c @@ -0,0 +1,949 @@ +/* +SPDX-License-Identifier: Beerware + +"THE BEER-WARE LICENSE" (Revision 42): + added this file. As long as you retain this notice you +can do whatever you want with this stuff. If we meet some day, and you think +this stuff is worth it, you can buy me a beer in return + +Owen Lyke +*/ + +//***************************************************************************** +// +//! @file HM01B0.c +//! +// +//***************************************************************************** + +#include "am_mcu_apollo.h" +#include "am_bsp.h" +#include "am_util.h" +#include "HM01B0.h" +#include "HM01B0_Walking1s_01.h" +#include "platform.h" + +#define read_vsync() (AM_REGVAL(AM_REGADDR(GPIO, RDA)) & (1 << HM01B0_PIN_VSYNC)) +#define read_hsync() (AM_REGVAL(AM_REGADDR(GPIO, RDA)) & (1 << HM01B0_PIN_HSYNC)) +#define read_pclk() (AM_REGVAL(AM_REGADDR(GPIO, RDA)) & (1 << HM01B0_PIN_PCLK)) +#define read_byte() (APBDMA->BBINPUT) + +const am_hal_gpio_pincfg_t g_HM01B0_pin_int = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN +}; + +//***************************************************************************** +// +//! @brief Write HM01B0 registers +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui16Reg - Register address. +//! @param pui8Value - Pointer to the data to be written. +//! @param ui32NumBytes - Length of the data in bytes to be written. +//! +//! This function writes value to HM01B0 registers. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_write_reg(hm01b0_cfg_t *psCfg, \ + uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes) +{ + am_hal_iom_transfer_t Transaction; + + // + // Create the transaction. + // + Transaction.ui32InstrLen = sizeof(uint16_t); + Transaction.ui32Instr = (ui16Reg & 0x0000FFFF); + Transaction.eDirection = AM_HAL_IOM_TX; + Transaction.ui32NumBytes = ui32NumBytes; + Transaction.pui32TxBuffer = (uint32_t *) pui8Value; + Transaction.uPeerInfo.ui32I2CDevAddr = (uint32_t) psCfg->ui16SlvAddr; + Transaction.bContinue = false; + Transaction.ui8RepeatCount = 0; + Transaction.ui32PauseCondition = 0; + Transaction.ui32StatusSetClr = 0; + + // + // Execute the transction over IOM. + // + if (am_hal_iom_blocking_transfer(psCfg->pIOMHandle, &Transaction)) + { + return HM01B0_ERR_I2C; + } + + return HM01B0_ERR_OK; + +} + +//***************************************************************************** +// +//! @brief Read HM01B0 registers +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui16Reg - Register address. +//! @param pui8Value - Pointer to the buffer for read data to be put into. +//! @param ui32NumBytes - Length of the data to be read. +//! +//! This function reads value from HM01B0 registers. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_read_reg(hm01b0_cfg_t *psCfg, \ + uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes) +{ + am_hal_iom_transfer_t Transaction; + + // + // Create the transaction. + // + Transaction.ui32InstrLen = sizeof(uint16_t); + Transaction.ui32Instr = (ui16Reg & 0x0000FFFF); + Transaction.eDirection = AM_HAL_IOM_RX; + Transaction.ui32NumBytes = ui32NumBytes; + Transaction.pui32RxBuffer = (uint32_t *) pui8Value;; + Transaction.uPeerInfo.ui32I2CDevAddr = (uint32_t) psCfg->ui16SlvAddr; + Transaction.bContinue = false; + Transaction.ui8RepeatCount = 0; + Transaction.ui32PauseCondition = 0; + Transaction.ui32StatusSetClr = 0; + + // + // Execute the transction over IOM. + // + if (am_hal_iom_blocking_transfer(psCfg->pIOMHandle, &Transaction)) + { + return HM01B0_ERR_I2C; + } + + return HM01B0_ERR_OK; +} + +//***************************************************************************** +// +//! @brief Load HM01B0 a given script +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psScrip - Pointer to the script to be loaded. +//! @param ui32ScriptCmdNum - Number of entries in a given script. +//! +//! This function loads HM01B0 a given script. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_load_script(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + for (uint32_t idx = 0; idx < ui32ScriptCmdNum; idx++) + { + ui32Err = hm01b0_write_reg(psCfg, \ + (psScript + idx)->ui16Reg, \ + &((psScript + idx)->ui8Val), \ + sizeof(uint8_t)); + if (ui32Err != HM01B0_ERR_OK) + { + break; + } + } + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Power up HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function powers up HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_power_up(hm01b0_cfg_t *psCfg) +{ + // place holder +} + +//***************************************************************************** +// +//! @brief Power down HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function powers up HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_power_down(hm01b0_cfg_t *psCfg) +{ + // place holder +} + +//***************************************************************************** +// +//! @brief Enable MCLK +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function utilizes CTimer to generate MCLK for HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_mclk_enable(hm01b0_cfg_t *psCfg) +{ +#define MCLK_UI64PATTERN 0x55555555 +#define MCLK_UI64PATTERNLEN 31 + + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0); + + // + // Set up timer. + // + am_hal_ctimer_clear(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment); + + am_hal_ctimer_config_single(psCfg->ui32CTimerModule, + psCfg->ui32CTimerSegment, + ( + AM_HAL_CTIMER_FN_PTN_REPEAT | + AM_HAL_CTIMER_HFRC_12MHZ + ) + ); + + // + // Set the pattern in the CMPR registers. + // + am_hal_ctimer_compare_set(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment, 0, + (uint32_t)(MCLK_UI64PATTERN & 0xFFFF)); + am_hal_ctimer_compare_set(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment, 1, + (uint32_t)((MCLK_UI64PATTERN >> 16) & 0xFFFF)); + + // + // Set the timer trigger and pattern length. + // + am_hal_ctimer_config_trigger(psCfg->ui32CTimerModule, + psCfg->ui32CTimerSegment, + ( + (MCLK_UI64PATTERNLEN << CTIMER_AUX0_TMRA0LMT_Pos) | + (CTIMER_AUX0_TMRB0TRIG_DIS << CTIMER_AUX0_TMRA0TRIG_Pos) + ) + ); + + // + // Configure timer output pin. + // + am_hal_ctimer_output_config(psCfg->ui32CTimerModule, + psCfg->ui32CTimerSegment, + psCfg->ui32CTimerOutputPin, + AM_HAL_CTIMER_OUTPUT_NORMAL, + AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA); + + // + // Start the timer. + // + am_hal_ctimer_start(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment); + +} + +//***************************************************************************** +// +//! @brief Disable MCLK +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function disable CTimer to stop MCLK for HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_mclk_disable(hm01b0_cfg_t *psCfg) +{ + // + // Stop the timer. + // + am_hal_ctimer_stop(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment); + am_hal_gpio_pinconfig(psCfg->ui32CTimerOutputPin, g_AM_HAL_GPIO_DISABLE); + +} + +//***************************************************************************** +// +//! @brief Initialize interfaces +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function initializes interfaces. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_init_if(hm01b0_cfg_t *psCfg) +{ + void *pIOMHandle = NULL; + + if ( psCfg->ui32IOMModule > AM_REG_IOM_NUM_MODULES ) + { + return HM01B0_ERR_I2C; + } + + // + // Enable fault detection. + // +#if AM_APOLLO3_MCUCTRL + am_hal_mcuctrl_control(AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE, 0); +#else // AM_APOLLO3_MCUCTRL + am_hal_mcuctrl_fault_capture_enable(); +#endif // AM_APOLLO3_MCUCTRL + + // + // Initialize the IOM instance. + // Enable power to the IOM instance. + // Configure the IOM for Serial operation during initialization. + // Enable the IOM. + // + if (am_hal_iom_initialize(psCfg->ui32IOMModule, &pIOMHandle) || + am_hal_iom_power_ctrl(pIOMHandle, AM_HAL_SYSCTRL_WAKE, false) || + am_hal_iom_configure(pIOMHandle, &(psCfg->sIOMCfg)) || + am_hal_iom_enable(pIOMHandle)) + { + return HM01B0_ERR_I2C; + } + else + { + // + // Configure the IOM pins. + // + am_bsp_iom_pins_enable(psCfg->ui32IOMModule, psCfg->eIOMMode); + + psCfg->pIOMHandle = pIOMHandle; + } + + // initialize pins for camera parallel interface. + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD0); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD1); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD2); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD3); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD4); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD5); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD6); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD7); + + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD0); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD1); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD2); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD3); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD4); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD5); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD6); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD7); + + am_hal_gpio_fast_pinconfig((uint64_t)0x1 << psCfg->ui8PinD0 | + (uint64_t)0x1 << psCfg->ui8PinD1 | + (uint64_t)0x1 << psCfg->ui8PinD2 | + (uint64_t)0x1 << psCfg->ui8PinD3 | + (uint64_t)0x1 << psCfg->ui8PinD4 | + (uint64_t)0x1 << psCfg->ui8PinD5 | + (uint64_t)0x1 << psCfg->ui8PinD6 | + (uint64_t)0x1 << psCfg->ui8PinD7, + g_AM_HAL_GPIO_INPUT, 0); + + am_hal_gpio_pinconfig(psCfg->ui8PinVSYNC, g_AM_HAL_GPIO_INPUT); + am_hal_gpio_pinconfig(psCfg->ui8PinHSYNC, g_AM_HAL_GPIO_INPUT); + am_hal_gpio_pinconfig(psCfg->ui8PinPCLK, g_AM_HAL_GPIO_INPUT); + + am_hal_gpio_pinconfig(psCfg->ui8PinTrig, g_AM_HAL_GPIO_OUTPUT); + + am_hal_gpio_pinconfig(psCfg->ui8PinInt, g_AM_HAL_GPIO_DISABLE); + // am_hal_gpio_pinconfig(psCfg->ui8PinInt, g_HM01B0_pin_int); + // am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(psCfg->ui8PinInt)); + // am_hal_gpio_interrupt_enable(AM_HAL_GPIO_BIT(psCfg->ui8PinInt)); + // NVIC_EnableIRQ(GPIO_IRQn); + + return HM01B0_ERR_OK; +} + +//***************************************************************************** +// +//! @brief Deinitialize interfaces +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function deinitializes interfaces. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_deinit_if(hm01b0_cfg_t *psCfg) +{ + am_hal_iom_disable(psCfg->pIOMHandle); + am_hal_iom_uninitialize(psCfg->pIOMHandle); + + am_hal_gpio_pinconfig(psCfg->ui8PinSCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(psCfg->ui8PinSDA, g_AM_HAL_GPIO_DISABLE); + + // initialize pins for camera parallel interface. + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD0); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD1); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD2); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD3); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD4); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD5); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD6); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD7); + + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD0); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD1); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD2); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD3); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD4); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD5); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD6); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD7); + + am_hal_gpio_pinconfig(psCfg->ui8PinVSYNC, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(psCfg->ui8PinHSYNC, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(psCfg->ui8PinPCLK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(psCfg->ui8PinTrig, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(psCfg->ui8PinInt, g_AM_HAL_GPIO_DISABLE); + + + return HM01B0_ERR_OK; +} + +//***************************************************************************** +// +//! @brief Get HM01B0 Model ID +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui16MID - Pointer to buffer for the read back model ID. +//! +//! This function reads back HM01B0 model ID. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_modelid(hm01b0_cfg_t *psCfg, uint16_t *pui16MID) +{ + uint8_t ui8Data[1]; + uint32_t ui32Err; + + *pui16MID = 0x0000; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_MODEL_ID_H, ui8Data, sizeof(ui8Data)); + if (ui32Err == HM01B0_ERR_OK) + { + *pui16MID |= (ui8Data[0] << 8); + } + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_MODEL_ID_L, ui8Data, sizeof(ui8Data)); + if (ui32Err == HM01B0_ERR_OK) + { + *pui16MID |= ui8Data[0]; + } + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Initialize HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psScript - Pointer to HM01B0 initialization script. +//! @param ui32ScriptCmdNum - No. of commands in HM01B0 initialization script. +//! +//! This function initilizes HM01B0 with a given script. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_init_system(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum) +{ + return hm01b0_load_script(psCfg, psScript, ui32ScriptCmdNum); +} + +//***************************************************************************** +// +//! @brief Set HM01B0 in the walking 1s test mode +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function sets HM01B0 in the walking 1s test mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_test_walking1s(hm01b0_cfg_t *psCfg) +{ + uint32_t ui32ScriptCmdNum = sizeof(sHM01b0TestModeScript_Walking1s) / sizeof(hm_script_t); + hm_script_t *psScript = (hm_script_t *)sHM01b0TestModeScript_Walking1s; + + return hm01b0_load_script(psCfg, psScript, ui32ScriptCmdNum); +} + +//***************************************************************************** +// +//! @brief Check the data read from HM01B0 in the walking 1s test mode +//! +//! @param pui8Buffer - Pointer to data buffer. +//! @param ui32BufferLen - Buffer length +//! @param ui32PrintCnt - Number of mismatched data to be printed out +//! +//! This function sets HM01B0 in the walking 1s test mode. +//! +//! @return Error code. +// +//***************************************************************************** +void hm01b0_test_walking1s_check_data_sanity(uint8_t *pui8Buffer, uint32_t ui32BufferLen, uint32_t ui32PrintCnt) +{ + uint8_t ui8ByteData = *pui8Buffer; + uint32_t ui32MismatchCnt = 0x00; + + for (uint32_t ui32Idx = 0; ui32Idx < ui32BufferLen; ui32Idx++) + { + if (*(pui8Buffer + ui32Idx) != ui8ByteData) + { + if (ui32PrintCnt) + { + am_util_stdio_printf("[0x%08X] actual 0x%02X expected 0x%02X\n", ui32Idx, *(pui8Buffer + ui32Idx), ui8ByteData); + am_util_delay_ms(1); + ui32PrintCnt--; + } + ui32MismatchCnt++; + } + + if (ui8ByteData) + ui8ByteData = ui8ByteData << 1; + else + ui8ByteData = 0x01; + } + + am_util_stdio_printf("Mismatch Rate %d/%d\n", ui32MismatchCnt, ui32BufferLen); + +} + +//***************************************************************************** +// +//! @brief Software reset HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function resets HM01B0 by issuing a reset command. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_reset_sw(hm01b0_cfg_t *psCfg) +{ + uint8_t ui8Data[1] = {0x00}; + return hm01b0_write_reg(psCfg, HM01B0_REG_SW_RESET, ui8Data, sizeof(ui8Data)); +} + +//***************************************************************************** +// +//! @brief Get current HM01B0 operation mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui8Mode - Pointer to buffer +//! - for the read back operation mode to be put into +//! +//! This function get HM01B0 operation mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_mode(hm01b0_cfg_t *psCfg, uint8_t *pui8Mode) +{ + uint8_t ui8Data[1] = {0x01}; + uint32_t ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_MODE_SELECT, ui8Data, sizeof(ui8Data)); + + *pui8Mode = ui8Data[0]; + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Set HM01B0 operation mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui8Mode - Operation mode. One of: +//! HM01B0_REG_MODE_SELECT_STANDBY +//! HM01B0_REG_MODE_SELECT_STREAMING +//! HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES +//! HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER +//! @param ui8FrameCnt - Frame count for HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES. +//! - Discarded if other modes. +//! +//! This function set HM01B0 operation mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_set_mode(hm01b0_cfg_t *psCfg, uint8_t ui8Mode, uint8_t ui8FrameCnt) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + + if (ui8Mode == HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES) + { + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_PMU_PROGRAMMABLE_FRAMECNT, &ui8FrameCnt, sizeof(ui8FrameCnt)); + } + + if(ui32Err == HM01B0_ERR_OK) + { + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_MODE_SELECT, &ui8Mode, sizeof(ui8Mode)); + } + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Activate the updated settings to HM01B0. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! Some settings updated to HM01B0 will only be affected after calling this function +//! 1. AE settings +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_cmd_update(hm01b0_cfg_t *psCfg) +{ + uint8_t ui8Data = HM01B0_REG_GRP_PARAM_HOLD_HOLD; + + return hm01b0_write_reg(psCfg, HM01B0_REG_GRP_PARAM_HOLD, &ui8Data, sizeof(ui8Data)); +} + +//***************************************************************************** +// +//! @brief Get HM01B0 AE convergance +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psAECfg - Pointer to the structure hm01b0_ae_cfg_t. +//! +//! This function checks if AE is converged or not and returns ui32Err accordingly. +//! If caller needs detailed AE settings, psAECfg has to be non NULL. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_ae(hm01b0_cfg_t *psCfg, hm01b0_ae_cfg_t *psAECfg) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + uint8_t ui8AETargetMean; + uint8_t ui8AEMinMean; + uint8_t ui8AEMean; + uint8_t ui8ConvergeInTh; + uint8_t ui8ConvergeOutTh; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_AE_TARGET_MEAN, &ui8AETargetMean, sizeof(ui8AETargetMean)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_AE_MIN_MEAN, &ui8AEMinMean, sizeof(ui8AEMinMean)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_CONVERGE_IN_TH, &ui8ConvergeInTh, sizeof(ui8ConvergeInTh)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_CONVERGE_OUT_TH, &ui8ConvergeOutTh, sizeof(ui8ConvergeOutTh)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, 0x2020, &ui8AEMean, sizeof(ui8AEMean)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + if ((ui8AEMean < (ui8AETargetMean - ui8ConvergeInTh)) || (ui8AEMean > (ui8AETargetMean + ui8ConvergeInTh))) + ui32Err = HM01B0_ERR_AE_NOT_CONVERGED; + + if (psAECfg) + { + psAECfg->ui8AETargetMean = ui8AETargetMean; + psAECfg->ui8AEMinMean = ui8AEMinMean; + psAECfg->ui8ConvergeInTh = ui8ConvergeInTh; + psAECfg->ui8ConvergeOutTh = ui8ConvergeOutTh; + psAECfg->ui8AEMean = ui8AEMean; + } + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief AE calibration. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui8CalFrames - Frame counts for calibratoin. +//! @param pui8Buffer - Pointer to the frame buffer. +//! @param ui32BufferLen - Framebuffer size. +//! +//! This function lets HM01B0 AE settled as much as possible within a given frame counts. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_cal_ae(hm01b0_cfg_t *psCfg, uint8_t ui8CalFrames, uint8_t *pui8Buffer, uint32_t ui32BufferLen) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + hm01b0_ae_cfg_t sAECfg; + + am_util_stdio_printf("[%s] +\n", __func__); + + hm01b0_set_mode(psCfg, HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES, ui8CalFrames); + + for (uint8_t i = 0; i < ui8CalFrames; i++) + { + + hm01b0_blocking_read_oneframe(psCfg, pui8Buffer, ui32BufferLen); + + ui32Err = hm01b0_get_ae(psCfg, &sAECfg); + + am_util_stdio_printf("AE Calibration(0x%02X) TargetMean 0x%02X, ConvergeInTh 0x%02X, AEMean 0x%02X\n", \ + ui32Err, sAECfg.ui8AETargetMean, sAECfg.ui8ConvergeInTh, sAECfg.ui8AEMean); + + // if AE calibration is done in ui8CalFrames, just exit to save some time. + if (ui32Err == HM01B0_ERR_OK) + break; + } + + hm01b0_set_mode(psCfg, HM01B0_REG_MODE_SELECT_STANDBY, 0); + + am_util_stdio_printf("[%s] -\n", __func__); + + return ui32Err; +} + + +//***************************************************************************** +// +//! @brief Save HM01B0 exposure gain settings. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t +//! +//! This function saves HM01B0 exposure gain settings. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_save_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + uint8_t ui8IntegrationH; + uint8_t ui8IntegrationL; + uint8_t ui8AGain; + uint8_t ui8DGain_H; + uint8_t ui8DGain_L; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_INTEGRATION_H, &ui8IntegrationH, sizeof(ui8IntegrationH)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_INTEGRATION_L, &ui8IntegrationL, sizeof(ui8IntegrationL)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_ANALOG_GAIN, &ui8AGain, sizeof(ui8AGain)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_H, &ui8DGain_H, sizeof(ui8DGain_H)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_L, &ui8DGain_L, sizeof(ui8DGain_L)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + if (psExpoGainCtrl) + { + psExpoGainCtrl->ui8IntegrationH = ui8IntegrationH; + psExpoGainCtrl->ui8IntegrationL = ui8IntegrationL; + psExpoGainCtrl->ui8AGain = ui8AGain; + psExpoGainCtrl->ui8DGain_H = ui8DGain_H; + psExpoGainCtrl->ui8DGain_L = ui8DGain_L; + } + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Restore HM01B0 exposure gain settings. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t +//! +//! This function restores HM01B0 exposure gain settings. The call flow shall be +//! hm01b0_restore_exposure_gains() -> hm01b0_cmd_update() -> hm01b0_set_mode() +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_restore_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + uint8_t ui8Tmp; + + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_INTEGRATION_H, &(psExpoGainCtrl->ui8IntegrationH), sizeof(psExpoGainCtrl->ui8IntegrationH)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_INTEGRATION_L, &(psExpoGainCtrl->ui8IntegrationL), sizeof(psExpoGainCtrl->ui8IntegrationL)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_ANALOG_GAIN, &ui8Tmp, sizeof(ui8Tmp)); + ui8Tmp = (ui8Tmp & ~(0x7 << 4)) | (psExpoGainCtrl->ui8AGain & (0x7 << 4)); + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_ANALOG_GAIN, &ui8Tmp, sizeof(ui8Tmp)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_H, &ui8Tmp, sizeof(ui8Tmp)); + ui8Tmp = (ui8Tmp & ~(0x3 << 0)) | (psExpoGainCtrl->ui8DGain_H & (0x3 << 0)); + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_H, &ui8Tmp, sizeof(ui8Tmp)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_L, &ui8Tmp, sizeof(ui8Tmp)); + ui8Tmp = (ui8Tmp & ~(0x3F << 2)) | (psExpoGainCtrl->ui8DGain_L & (0x3F << 2)); + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_L, &ui8Tmp, sizeof(ui8Tmp)); + + return ui32Err; + +} + +//***************************************************************************** +// +//! @brief Hardware trigger HM01B0 to stream. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param bTrigger - True to start streaming +//! - False to stop streaming +//! +//! This function triggers HM01B0 to stream by toggling the TRIG pin. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_hardware_trigger_streaming(hm01b0_cfg_t *psCfg, bool bTrigger) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + uint8_t ui8Mode; + + ui32Err = hm01b0_get_mode(psCfg, &ui8Mode); + + if (ui32Err != HM01B0_ERR_OK) + goto end; + + if (ui8Mode != HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER) + { + ui32Err = HM01B0_ERR_MODE; + goto end; + } + + if (bTrigger) + { + am_hal_gpio_output_set(psCfg->ui8PinTrig); + } + else + { + am_hal_gpio_output_clear(psCfg->ui8PinTrig); + } + +end: + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Set HM01B0 mirror mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param bHmirror - Horizontal mirror +//! @param bVmirror - Vertical mirror +//! +//! This function set HM01B0 mirror mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_set_mirror(hm01b0_cfg_t *psCfg, bool bHmirror, bool bVmirror) +{ + uint8_t ui8Data = 0x00; + uint32_t ui32Err = HM01B0_ERR_OK; + + if (bHmirror) + { + ui8Data |= HM01B0_REG_IMAGE_ORIENTATION_HMIRROR; + } + + if (bVmirror) + { + ui8Data |= HM01B0_REG_IMAGE_ORIENTATION_VMIRROR; + } + + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_IMAGE_ORIENTATION, &ui8Data, sizeof(ui8Data)); + + if (ui32Err == HM01B0_ERR_OK) + { + ui8Data = HM01B0_REG_GRP_PARAM_HOLD_HOLD; + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_GRP_PARAM_HOLD, &ui8Data, sizeof(ui8Data)); + } + + return ui32Err; + +} + +//***************************************************************************** +// +//! @brief Read data of one frame from HM01B0. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui8Buffer - Pointer to the frame buffer. +//! @param ui32BufferLen - Framebuffer size. +//! +//! This function read data of one frame from HM01B0. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_blocking_read_oneframe(hm01b0_cfg_t *psCfg, uint8_t *pui8Buffer, uint32_t ui32BufferLen) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + uint32_t ui32Idx = 0x00; + + am_util_stdio_printf("[%s] +\n", __func__); + + uint32_t ui32HsyncCnt = 0x00; + + while((ui32HsyncCnt < HM01B0_PIXEL_Y_NUM)) + { + while (0x00 == read_hsync()); + + // read one row + while(read_hsync()) + { + while(0x00 == read_pclk()); + + *(pui8Buffer + ui32Idx++) = read_byte(); + + if (ui32Idx == ui32BufferLen) { + goto end; + } + + while(read_pclk()); + } + + ui32HsyncCnt++; + } + +end: + am_util_stdio_printf("[%s] - Byte Counts %d\n", __func__, ui32Idx); + + return ui32Err; + +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.h new file mode 100644 index 0000000..4d1dd97 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.h @@ -0,0 +1,501 @@ +/* +SPDX-License-Identifier: Beerware + +"THE BEER-WARE LICENSE" (Revision 42): + added this file. As long as you retain this notice you +can do whatever you want with this stuff. If we meet some day, and you think +this stuff is worth it, you can buy me a beer in return + +Owen Lyke +*/ + +//***************************************************************************** +// +//! @file HM01B0.h +// +//***************************************************************************** +#ifndef HM01B0_H +#define HM01B0_H + +#ifdef __cplusplus +extern "C" +{ +#endif +#include "am_mcu_apollo.h" +#include "am_bsp.h" +#include "am_util.h" + +#define HM01B0_DRV_VERSION (0) +#define HM01B0_DRV_SUBVERSION (5) + +#define HM01B0_DEFAULT_ADDRESS (0x24) + +#define HM01B0_PIXEL_X_NUM (324) +#define HM01B0_PIXEL_Y_NUM (244) + +#define HM01B0_REG_MODEL_ID_H (0x0000) +#define HM01B0_REG_MODEL_ID_L (0x0001) +#define HM01B0_REG_SILICON_REV (0x0002) +#define HM01B0_REG_FRAME_COUNT (0x0005) +#define HM01B0_REG_PIXEL_ORDER (0x0006) + +#define HM01B0_REG_MODE_SELECT (0x0100) +#define HM01B0_REG_IMAGE_ORIENTATION (0x0101) +#define HM01B0_REG_SW_RESET (0x0103) +#define HM01B0_REG_GRP_PARAM_HOLD (0x0104) + +#define HM01B0_REG_INTEGRATION_H (0x0202) +#define HM01B0_REG_INTEGRATION_L (0x0203) +#define HM01B0_REG_ANALOG_GAIN (0x0205) +#define HM01B0_REG_DIGITAL_GAIN_H (0x020E) +#define HM01B0_REG_DIGITAL_GAIN_L (0x020F) + +#define HM01B0_REG_AE_TARGET_MEAN (0x2101) +#define HM01B0_REG_AE_MIN_MEAN (0x2102) +#define HM01B0_REG_CONVERGE_IN_TH (0x2103) +#define HM01B0_REG_CONVERGE_OUT_TH (0x2104) + + +#define HM01B0_REG_I2C_ID_SEL (0x3400) +#define HM01B0_REG_I2C_ID_REG (0x3401) + +#define HM01B0_REG_PMU_PROGRAMMABLE_FRAMECNT (0x3020) + +// #define HM01B0_REG_MODE_SELECT (0x0100) +#define HM01B0_REG_MODE_SELECT_STANDBY (0x00) +#define HM01B0_REG_MODE_SELECT_STREAMING (0x01) +#define HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES (0x03) +#define HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER (0x05) + +// #define HM01B0_REG_IMAGE_ORIENTATION (0x0101) +#define HM01B0_REG_IMAGE_ORIENTATION_DEFAULT (0x00) +#define HM01B0_REG_IMAGE_ORIENTATION_HMIRROR (0x01) +#define HM01B0_REG_IMAGE_ORIENTATION_VMIRROR (0x02) +#define HM01B0_REG_IMAGE_ORIENTATION_HVMIRROR (HM01B0_REG_IMAGE_ORIENTATION_HMIRROR | HM01B0_REG_IMAGE_ORIENTATION_HVMIRROR) + +// #define HM01B0_REG_GRP_PARAM_HOLD (0x0104) +#define HM01B0_REG_GRP_PARAM_HOLD_CONSUME (0x00) +#define HM01B0_REG_GRP_PARAM_HOLD_HOLD (0x01) + +enum +{ + HM01B0_ERR_OK = 0x00, + HM01B0_ERR_I2C, + HM01B0_ERR_MODE, + HM01B0_ERR_AE_NOT_CONVERGED, +}; + +typedef struct +{ + uint16_t ui16Reg; + uint8_t ui8Val; +} hm_script_t; + +typedef struct +{ + uint16_t ui16SlvAddr; + am_hal_iom_mode_e eIOMMode; + uint32_t ui32IOMModule; + am_hal_iom_config_t sIOMCfg; + void *pIOMHandle; + + uint32_t ui32CTimerModule; + uint32_t ui32CTimerSegment; + uint32_t ui32CTimerOutputPin; + + uint8_t ui8PinSCL; + uint8_t ui8PinSDA; + uint8_t ui8PinD0; + uint8_t ui8PinD1; + uint8_t ui8PinD2; + uint8_t ui8PinD3; + uint8_t ui8PinD4; + uint8_t ui8PinD5; + uint8_t ui8PinD6; + uint8_t ui8PinD7; + uint8_t ui8PinVSYNC; + uint8_t ui8PinHSYNC; + uint8_t ui8PinPCLK; + + uint8_t ui8PinTrig; + uint8_t ui8PinInt; + void (*pfnGpioIsr)(void); +} hm01b0_cfg_t; + +typedef struct +{ + uint8_t ui8AETargetMean; + uint8_t ui8AEMinMean; + uint8_t ui8ConvergeInTh; + uint8_t ui8ConvergeOutTh; + uint8_t ui8AEMean; +} hm01b0_ae_cfg_t; + +typedef struct +{ + uint8_t ui8IntegrationH; + uint8_t ui8IntegrationL; + uint8_t ui8AGain; + uint8_t ui8DGain_H; + uint8_t ui8DGain_L; +} hm01b0_snr_expo_gain_ctrl_t; + +//***************************************************************************** +// +//! @brief Write HM01B0 registers +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui16Reg - Register address. +//! @param pui8Value - Pointer to the data to be written. +//! @param ui32NumBytes - Length of the data in bytes to be written. +//! +//! This function writes value to HM01B0 registers. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_write_reg(hm01b0_cfg_t *psCfg, \ + uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes); + +//***************************************************************************** +// +//! @brief Read HM01B0 registers +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui16Reg - Register address. +//! @param pui8Value - Pointer to the buffer for read data to be put into. +//! @param ui32NumBytes - Length of the data to be read. +//! +//! This function reads value from HM01B0 registers. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_read_reg(hm01b0_cfg_t *psCfg, \ + uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes); + +//***************************************************************************** +// +//! @brief Load HM01B0 a given script +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psScrip - Pointer to the script to be loaded. +//! @param ui32ScriptCmdNum - Number of entries in a given script. +//! +//! This function loads HM01B0 a given script. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_load_script(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum); + +//***************************************************************************** +// +//! @brief Power up HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function powers up HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_power_up(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Power down HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function powers up HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_power_down(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Enable MCLK +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function utilizes CTimer to generate MCLK for HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_mclk_enable(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Disable MCLK +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function disable CTimer to stop MCLK for HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_mclk_disable(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Initialize interfaces +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function initializes interfaces. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_init_if(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Deinitialize interfaces +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function deinitializes interfaces. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_deinit_if(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Get HM01B0 Model ID +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui16MID - Pointer to buffer for the read back model ID. +//! +//! This function reads back HM01B0 model ID. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_modelid(hm01b0_cfg_t *psCfg, uint16_t *pui16MID); + +//***************************************************************************** +// +//! @brief Initialize HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psScript - Pointer to HM01B0 initialization script. +//! @param ui32ScriptCmdNum - No. of commands in HM01B0 initialization script. +//! +//! This function initilizes HM01B0 with a given script. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_init_system(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum); + +//***************************************************************************** +// +//! @brief Set HM01B0 in the walking 1s test mode +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function sets HM01B0 in the walking 1s test mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_test_walking1s(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Check the data read from HM01B0 in the walking 1s test mode +//! +//! @param pui8Buffer - Pointer to data buffer. +//! @param ui32BufferLen - Buffer length +//! @param ui32PrintCnt - Number of mismatched data to be printed out +//! +//! This function sets HM01B0 in the walking 1s test mode. +//! +//! @return Error code. +// +//***************************************************************************** +void hm01b0_test_walking1s_check_data_sanity(uint8_t *pui8Buffer, uint32_t ui32BufferLen, uint32_t ui32PrintCnt); + +//***************************************************************************** +// +//! @brief Software reset HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function resets HM01B0 by issuing a reset command. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_reset_sw(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Get current HM01B0 operation mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui8Mode - Pointer to buffer +//! - for the read back operation mode to be put into +//! +//! This function get HM01B0 operation mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_mode(hm01b0_cfg_t *psCfg, uint8_t *pui8Mode); + +//***************************************************************************** +// +//! @brief Set HM01B0 operation mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui8Mode - Operation mode. One of: +//! HM01B0_REG_MODE_SELECT_STANDBY +//! HM01B0_REG_MODE_SELECT_STREAMING +//! HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES +//! HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER +//! @param framecnt - Frame count for HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES. +//! - Discarded if other modes. +//! +//! This function set HM01B0 operation mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_set_mode(hm01b0_cfg_t *psCfg, uint8_t ui8Mode, uint8_t framecnt); + + +//***************************************************************************** +// +//! @brief Activate the updated settings to HM01B0. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! Some settings updated to HM01B0 will only be affected after calling this function +//! 1. AE settings +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_cmd_update(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Get HM01B0 AE settings +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psAECfg - Pointer to the structure hm01b0_ae_cfg_t. +//! +//! This function checks if AE is converged or not and returns ui32Err accordingly. +//! If caller needs detailed AE settings, psAECfg has to be non NULL. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_ae(hm01b0_cfg_t *psCfg, hm01b0_ae_cfg_t *psAECfg); + +//***************************************************************************** +// +//! @brief AE calibration. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui8CalFrames - Frame counts for calibratoin. +//! @param pui8Buffer - Pointer to the frame buffer. +//! @param ui32BufferLen - Framebuffer size. +//! +//! This function lets HM01B0 AE settled as much as possible within a given frame counts. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_cal_ae(hm01b0_cfg_t *psCfg, uint8_t ui8CalFrames, uint8_t *pui8Buffer, uint32_t ui32BufferLen); + +//***************************************************************************** +// +//! @brief Save HM01B0 exposure gain settings. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t +//! +//! This function saves HM01B0 exposure gain settings. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_save_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl); + +//***************************************************************************** +// +//! @brief Restore HM01B0 exposure gain settings. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t +//! +//! This function restores HM01B0 exposure gain settings. The call flow shall be +//! hm01b0_restore_exposure_gains() -> hm01b0_cmd_update() -> hm01b0_set_mode() +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_restore_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl); + +//***************************************************************************** +// +//! @brief Hardware trigger HM01B0 to stream. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param bTrigger - True to start streaming +//! - False to stop streaming +//! +//! This function triggers HM01B0 to stream by toggling the TRIG pin. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_hardware_trigger_streaming(hm01b0_cfg_t *psCfg, bool bTrigger); + +//***************************************************************************** +// +//! @brief Set HM01B0 mirror mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param bHmirror - Horizontal mirror +//! @param bVmirror - Vertical mirror +//! +//! This function set HM01B0 mirror mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_set_mirror(hm01b0_cfg_t *psCfg, bool bHmirror, bool bVmirror); + + +//***************************************************************************** +// +//! @brief Read data of one frame from HM01B0. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui8Buffer - Pointer to the frame buffer. +//! @param ui32BufferLen - Framebuffer size. +//! +//! This function read data of one frame from HM01B0. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_blocking_read_oneframe(hm01b0_cfg_t *psCfg, \ + uint8_t *pui8Buffer, uint32_t ui32BufferLen); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CTIMER_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_RAW8_QVGA_8bits_lsb_5fps.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_RAW8_QVGA_8bits_lsb_5fps.h new file mode 100644 index 0000000..0b40f62 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_RAW8_QVGA_8bits_lsb_5fps.h @@ -0,0 +1,243 @@ +/* +SPDX-License-Identifier: Beerware + +"THE BEER-WARE LICENSE" (Revision 42): + added this file. As long as you retain this notice you +can do whatever you want with this stuff. If we meet some day, and you think +this stuff is worth it, you can buy me a beer in return + +Owen Lyke +*/ + +#include "HM01B0.h" + +const hm_script_t sHM01B0InitScript[] = +{ +// ;************************************************************************* +// ; Sensor: HM01B0 +// ; I2C ID: 24 +// ; Resolution: 324x244 +// ; Lens: +// ; Flicker: +// ; Frequency: +// ; Description: AE control enable +// ; 8-bit mode, LSB first +// ; +// ; +// ; Note: +// ; +// ; $Revision: 1338 $ +// ; $Date:: 2017-04-11 15:43:45 +0800#$ +// ;************************************************************************* +// +// // --------------------------------------------------- +// // HUB system initial +// // --------------------------------------------------- +// W 20 8A04 01 2 1 +// W 20 8A00 22 2 1 +// W 20 8A01 00 2 1 +// W 20 8A02 01 2 1 +// W 20 0035 93 2 1 ; [3]&[1] hub616 20bits in, [5:4]=1 mclk=48/2=24mhz +// W 20 0036 00 2 1 +// W 20 0011 09 2 1 +// W 20 0012 B6 2 1 +// W 20 0014 08 2 1 +// W 20 0015 98 2 1 +// ;W 20 0130 16 2 1 ; 3m soc, signal buffer control +// ;W 20 0100 44 2 1 ; [6] hub616 20bits in +// W 20 0100 04 2 1 ; [6] hub616 20bits in +// W 20 0121 01 2 1 ; [0] Q1 Intf enable, [1]:4bit mode, [2] msb first, [3] serial mode +// W 20 0150 00 2 1 ; +// W 20 0150 04 2 1 ; +// +// +// //--------------------------------------------------- +// // Initial +// //--------------------------------------------------- +// W 24 0103 00 2 1 ; software reset-> was 0x22 + {0x0103, 0x00,}, +// W 24 0100 00 2 1; power up + {0x0100, 0x00,}, +// +// +// +// //--------------------------------------------------- +// // Analog +// //--------------------------------------------------- +// L HM01B0_analog_setting.txt + {0x1003, 0x08,}, + {0x1007, 0x08,}, + {0x3044, 0x0A,}, + {0x3045, 0x00,}, + {0x3047, 0x0A,}, + {0x3050, 0xC0,}, + {0x3051, 0x42,}, + {0x3052, 0x50,}, + {0x3053, 0x00,}, + {0x3054, 0x03,}, + {0x3055, 0xF7,}, + {0x3056, 0xF8,}, + {0x3057, 0x29,}, + {0x3058, 0x1F,}, + {0x3059, 0x1E,}, + {0x3064, 0x00,}, + {0x3065, 0x04,}, +// +// +// //--------------------------------------------------- +// // Digital function +// //--------------------------------------------------- +// +// // BLC +// W 24 1000 43 2 1 ; BLC_on, IIR + {0x1000, 0x43,}, +// W 24 1001 40 2 1 ; [6] : BLC dithering en + {0x1001, 0x40,}, +// W 24 1002 32 2 1 ; // blc_darkpixel_thd + {0x1002, 0x32,}, +// +// // Dgain +// W 24 0350 7F 2 1 ; Dgain Control + {0x0350, 0x7F,}, +// +// // BLI +// W 24 1006 01 2 1 ; [0] : bli enable + {0x1006, 0x01,}, +// +// // DPC +// W 24 1008 00 2 1 ; [2:0] : DPC option 0: DPC off 1 : mono 3 : bayer1 5 : bayer2 + {0x1008, 0x00,}, +// W 24 1009 A0 2 1 ; cluster hot pixel th + {0x1009, 0xA0,}, +// W 24 100A 60 2 1 ; cluster cold pixel th + {0x100A, 0x60,}, +// W 24 100B 90 2 1 ; single hot pixel th + {0x100B, 0x90,}, +// W 24 100C 40 2 1 ; single cold pixel th + {0x100C, 0x40,}, +// // +// advance VSYNC by 1 row + {0x3022, 0x01,}, +// W 24 1012 00 2 1 ; Sync. enable VSYNC shift + {0x1012, 0x01,}, + +// +// // ROI Statistic +// W 24 2000 07 2 1 ; [0] : AE stat en [1] : MD LROI stat en [2] : MD GROI stat en [3] : RGB stat ratio en [4] : IIR selection (1 -> 16, 0 -> 8) + {0x2000, 0x07,}, +// W 24 2003 00 2 1 ; MD GROI 0 y start HB + {0x2003, 0x00,}, +// W 24 2004 1C 2 1 ; MD GROI 0 y start LB + {0x2004, 0x1C,}, +// W 24 2007 00 2 1 ; MD GROI 1 y start HB + {0x2007, 0x00,}, +// W 24 2008 58 2 1 ; MD GROI 1 y start LB + {0x2008, 0x58,}, +// W 24 200B 00 2 1 ; MD GROI 2 y start HB + {0x200B, 0x00,}, +// W 24 200C 7A 2 1 ; MD GROI 2 y start LB + {0x200C, 0x7A,}, +// W 24 200F 00 2 1 ; MD GROI 3 y start HB + {0x200F, 0x00,}, +// W 24 2010 B8 2 1 ; MD GROI 3 y start LB + {0x2010, 0xB8,}, +// +// W 24 2013 00 2 1 ; MD LRIO y start HB + {0x2013, 0x00,}, +// W 24 2014 58 2 1 ; MD LROI y start LB + {0x2014, 0x58,}, +// W 24 2017 00 2 1 ; MD LROI y end HB + {0x2017, 0x00,}, +// W 24 2018 9B 2 1 ; MD LROI y end LB + {0x2018, 0x9B,}, +// +// // AE +// W 24 2100 01 2 1 ; [0]: AE control enable + {0x2100, 0x01,}, +// W 24 2104 07 2 1 ; converge out th + {0x2104, 0x07,}, +// W 24 2105 0C 2 1 ; max INTG Hb + {0x2105, 0x0C,}, +// W 24 2106 78 2 1 ; max INTG Lb + {0x2106, 0x78,}, +// W 24 2108 03 2 1 ; max AGain in full + {0x2108, 0x03,}, +// W 24 2109 03 2 1 ; max AGain in bin2 + {0x2109, 0x03,}, +// W 24 210B 80 2 1 ; max DGain + {0x210B, 0x80,}, +// W 24 210F 00 2 1 ; FS 60Hz Hb + {0x210F, 0x00,}, +// W 24 2110 85 2 1 ; FS 60Hz Lb + {0x2110, 0x85,}, +// W 24 2111 00 2 1 ; Fs 50Hz Hb + {0x2111, 0x00,}, +// W 24 2112 A0 2 1 ; FS 50Hz Lb + {0x2112, 0xA0,}, +// +// +// // MD +// W 24 2150 03 2 1 ; [0] : MD LROI en [1] : MD GROI en + {0x2150, 0x03,}, +// +// +// //--------------------------------------------------- +// // frame rate : 5 FPS +// //--------------------------------------------------- +// W 24 0340 0C 2 1 ; smia frame length Hb + {0x0340, 0x0C,}, +// W 24 0341 7A 2 1 ; smia frame length Lb 3192 + {0x0341, 0x7A,}, +// +// W 24 0342 01 2 1 ; smia line length Hb + {0x0342, 0x01,}, +// W 24 0343 77 2 1 ; smia line length Lb 375 + {0x0343, 0x77,}, +// +// //--------------------------------------------------- +// // Resolution : QVGA 324x244 +// //--------------------------------------------------- +// W 24 3010 01 2 1 ; [0] : window mode 0 : full frame 324x324 1 : QVGA + {0x3010, 0x01,}, +// +// +// W 24 0383 01 2 1 ; + {0x0383, 0x01,}, +// W 24 0387 01 2 1 ; + {0x0387, 0x01,}, +// W 24 0390 00 2 1 ; + {0x0390, 0x00,}, +// +// //--------------------------------------------------- +// // bit width Selection +// //--------------------------------------------------- +// W 24 3011 70 2 1 ; [0] : 6 bit mode enable + {0x3011, 0x70,}, +// +// +// W 24 3059 02 2 1 ; [7]: Self OSC En, [6]: 4bit mode, [5]: serial mode, [4:0]: keep value as 0x02 + {0x3059, 0x02,}, +// W 24 3060 01 2 1 ; [5]: gated_clock, [4]: msb first, + {0x3060, 0x20,}, +// ; [3:2]: vt_reg_div -> div by 4/8/1/2 +// ; [1;0]: vt_sys_div -> div by 8/4/2/1 +// +// + {0x0101, 0x01,}, +// //--------------------------------------------------- +// // CMU update +// //--------------------------------------------------- +// +// W 24 0104 01 2 1 ; was 0100 + {0x0104, 0x01,}, +// +// +// +// //--------------------------------------------------- +// // Turn on rolling shutter +// //--------------------------------------------------- +// W 24 0100 01 2 1 ; was 0005 ; mode_select 00 : standby - wait fir I2C SW trigger 01 : streaming 03 : output "N" frame, then enter standby 04 : standby - wait for HW trigger (level), then continuous video out til HW TRIG goes off 06 : standby - wait for HW trigger (edge), then output "N" frames then enter standby + {0x0100, 0x00,}, +// +// ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +}; diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_Walking1s_01.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_Walking1s_01.h new file mode 100644 index 0000000..13de459 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_Walking1s_01.h @@ -0,0 +1,24 @@ +/* +SPDX-License-Identifier: Beerware + +"THE BEER-WARE LICENSE" (Revision 42): + added this file. As long as you retain this notice you +can do whatever you want with this stuff. If we meet some day, and you think +this stuff is worth it, you can buy me a beer in return + +Owen Lyke +*/ + +#include "HM01B0.h" + +const hm_script_t sHM01b0TestModeScript_Walking1s[] = +{ + {0x2100, 0x00,}, //W 24 2100 00 2 1 ; AE + {0x1000, 0x00,}, //W 24 1000 00 2 1 ; BLC + {0x1008, 0x00,}, //W 24 1008 00 2 1 ; DPC + {0x0205, 0x00,}, //W 24 0205 00 2 1 ; AGain + {0x020E, 0x01,}, //W 24 020E 01 2 1 ; DGain + {0x020F, 0x00,}, //W 24 020F 00 2 1 ; DGain + {0x0601, 0x11,}, //W 24 0601 11 2 1 ; Test pattern + {0x0104, 0x01,}, //W 24 0104 01 2 1 ; +}; diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/platform.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/platform.h new file mode 100644 index 0000000..f906e4a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/platform.h @@ -0,0 +1,60 @@ +/* +SPDX-License-Identifier: Beerware + +"THE BEER-WARE LICENSE" (Revision 42): + added this file. As long as you retain this notice you +can do whatever you want with this stuff. If we meet some day, and you think +this stuff is worth it, you can buy me a beer in return + +Owen Lyke +*/ + +#ifndef HM01B0_PLATFORM_H +#define HM01B0_PLATFORM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define HM01B0_PIN_D0 AM_BSP_GPIO_CAMERA_HM01B0_D0 +#define HM01B0_PIN_D1 AM_BSP_GPIO_CAMERA_HM01B0_D1 +#define HM01B0_PIN_D2 AM_BSP_GPIO_CAMERA_HM01B0_D2 +#define HM01B0_PIN_D3 AM_BSP_GPIO_CAMERA_HM01B0_D3 +#define HM01B0_PIN_D4 AM_BSP_GPIO_CAMERA_HM01B0_D4 +#define HM01B0_PIN_D5 AM_BSP_GPIO_CAMERA_HM01B0_D5 +#define HM01B0_PIN_D6 AM_BSP_GPIO_CAMERA_HM01B0_D6 +#define HM01B0_PIN_D7 AM_BSP_GPIO_CAMERA_HM01B0_D7 +#define HM01B0_PIN_VSYNC AM_BSP_GPIO_CAMERA_HM01B0_VSYNC +#define HM01B0_PIN_HSYNC AM_BSP_GPIO_CAMERA_HM01B0_HSYNC +#define HM01B0_PIN_PCLK AM_BSP_GPIO_CAMERA_HM01B0_PCLK +#define HM01B0_PIN_SCL AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN +#define HM01B0_PIN_SDA AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN + + +// Some boards do not support TRIG or INT pins +#ifdef AM_BSP_GPIO_CAMERA_HM01B0_TRIG +#define HM01B0_PIN_TRIG AM_BSP_GPIO_CAMERA_HM01B0_TRIG +#endif // AM_BSP_GPIO_CAMERA_HM01B0_TRIG + +#ifdef AM_BSP_GPIO_CAMERA_HM01B0_INT +#define HM01B0_PIN_INT AM_BSP_GPIO_CAMERA_HM01B0_INT +#endif // AM_BSP_GPIO_CAMERA_HM01B0_INT + + +// Define AP3B's CTIMER and output pin for HM01B0 MCLK generation +#define HM01B0_MCLK_GENERATOR_MOD AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD +#define HM01B0_MCLK_GENERATOR_SEG AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG +#define HM01B0_PIN_MCLK AM_BSP_CAMERA_HM01B0_MCLK_PIN + +// Deifne I2C controller and SCL(pin8)/SDA(pin9) are configured automatically. +#define HM01B0_IOM_MODE AM_HAL_IOM_I2C_MODE +#define HM01B0_IOM_MODULE AM_BSP_CAMERA_HM01B0_I2C_IOM +#define HM01B0_I2C_CLOCK_FREQ AM_HAL_IOM_100KHZ + + +#ifdef __cplusplus +} +#endif + +#endif // HM01B0_PLATFORM_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.c new file mode 100644 index 0000000..04e3425 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include "lis2dh12_platform_apollo3.h" + +/* + * @brief Write generic device register (platform dependent) + * + * @param handle customizable argument. In this examples is used in + * order to select the correct sensor bus handler. + * @param reg register to write + * @param bufp pointer to data to write in register reg + * @param len number of consecutive register to write + * + */ +int32_t lis2dh12_write_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len) +{ + uint32_t retVal32 = 0; + lis2dh12_platform_apollo3_if_t* pif = (lis2dh12_platform_apollo3_if_t*)handle; + am_hal_iom_transfer_t iomTransfer = {0}; + + if( bufp == NULL ) { return AM_HAL_STATUS_FAIL; } + if( pif == NULL ) { return AM_HAL_STATUS_FAIL; } + if( pif->iomHandle == NULL) { return AM_HAL_STATUS_FAIL; } + + // Set up transfer + iomTransfer.uPeerInfo.ui32I2CDevAddr = pif->addCS; + iomTransfer.ui32InstrLen = 1; + iomTransfer.ui32Instr = (reg | 0x80); + iomTransfer.ui32NumBytes = len; + iomTransfer.eDirection = AM_HAL_IOM_TX; + iomTransfer.pui32TxBuffer = (uint32_t*)bufp; + iomTransfer.pui32RxBuffer = NULL; + iomTransfer.bContinue = false; + + if( pif->useSPI ){ + // ToDo: Support SPI w/ CS assertion + } + + // Send the transfer + retVal32 = am_hal_iom_blocking_transfer(pif->iomHandle, &iomTransfer); + + if( pif->useSPI ){ + // ToDo: Support SPI / CS de-assertion + } + + if( retVal32 != AM_HAL_STATUS_SUCCESS ){ return retVal32; } + + return 0; +} + +/* + * @brief Read generic device register (platform dependent) + * + * @param handle customizable argument. In this examples is used in + * order to select the correct sensor bus handler. + * @param reg register to read + * @param bufp pointer to buffer that store the data read + * @param len number of consecutive register to read + * + */ +int32_t lis2dh12_read_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len) +{ + uint32_t retVal32 = 0; + lis2dh12_platform_apollo3_if_t* pif = (lis2dh12_platform_apollo3_if_t*)handle; + am_hal_iom_transfer_t iomTransfer = {0}; + + if( bufp == NULL ) { return AM_HAL_STATUS_FAIL; } + if( pif == NULL ) { return AM_HAL_STATUS_FAIL; } + if( pif->iomHandle == NULL) { return AM_HAL_STATUS_FAIL; } + + // Set up first transfer + iomTransfer.uPeerInfo.ui32I2CDevAddr = pif->addCS; + iomTransfer.ui32InstrLen = 1; + iomTransfer.ui32Instr = (reg | 0x80); + iomTransfer.ui32NumBytes = 0; + iomTransfer.eDirection = AM_HAL_IOM_TX; + iomTransfer.bContinue = true; + + if( pif->useSPI ){ + // ToDo: Support SPI w/ CS assertion + } + + // Send the first transfer + retVal32 = am_hal_iom_blocking_transfer(pif->iomHandle, &iomTransfer); + if( retVal32 != AM_HAL_STATUS_SUCCESS ){ return retVal32; } + + // Change direction, and add the rx buffer + iomTransfer.eDirection = AM_HAL_IOM_RX; + iomTransfer.pui32RxBuffer = (uint32_t*)bufp; + iomTransfer.ui32NumBytes = len; + iomTransfer.bContinue = false; + + // Send the second transfer + retVal32 = am_hal_iom_blocking_transfer(pif->iomHandle, &iomTransfer); + + if( retVal32 != AM_HAL_STATUS_SUCCESS ){ return retVal32; } + + return 0; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.h new file mode 100644 index 0000000..a1c45df --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#ifndef _LIS2DH12_PLATFORM_APOLLO3_H_ +#define _LIS2DH12_PLATFORM_APOLLO3_H_ + +#include "am_mcu_apollo.h" +#include "lis2dh12_reg.h" + +#ifdef __cplusplus + extern "C" { +#endif + +typedef struct _lis2dh12_platform_apollo3_if_t { + void* iomHandle; // IO Master instance + uint8_t addCS; // I2C mode: the 7-bit I2C address (either 0x18 or 0x19 depeding on SA0 pin) + // SPI mode: the Apollo3 pad to use for chip select + bool useSPI; // Set 'true' if using SPI mode, else 'false' +}lis2dh12_platform_apollo3_if_t; + +int32_t lis2dh12_write_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len); +int32_t lis2dh12_read_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len); + +#ifdef __cplusplus +} +#endif + +#endif // _LIS2DH12_PLATFORM_APOLLO3_H_ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.c new file mode 100644 index 0000000..9c87e1d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.c @@ -0,0 +1,2399 @@ +/* + ****************************************************************************** + * @file lis2dh12_reg.c + * @author Sensors Software Solution Team + * @brief LIS2DH12 driver file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2018 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ +// SPDX-License-Identifier: BSD-3-Clause + +#include "lis2dh12_reg.h" + + +/** + * @defgroup LIS2DH12 + * @brief This file provides a set of functions needed to drive the + * lis2dh12 enanced inertial module. + * @{ + * + */ + +/** + * @defgroup LIS2DH12_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_read_reg(lis2dh12_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_write_reg(lis2dh12_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @} + * + */ + + /** + * @defgroup LIS2DH12_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float lis2dh12_from_fs2_hr_to_mg(int16_t lsb) +{ + return ( (float)lsb / 16.0f ) * 1.0f; +} + +float lis2dh12_from_fs4_hr_to_mg(int16_t lsb) +{ + return ( (float)lsb / 16.0f ) * 2.0f; +} + +float lis2dh12_from_fs8_hr_to_mg(int16_t lsb) +{ + return ( (float)lsb / 16.0f ) * 4.0f; +} + +float lis2dh12_from_fs16_hr_to_mg(int16_t lsb) +{ + return ( (float)lsb / 16.0f ) * 12.0f; +} + +float lis2dh12_from_lsb_hr_to_celsius(int16_t lsb) +{ + return ( ( (float)lsb / 64.0f ) / 4.0f ) + 25.0f; +} + +float lis2dh12_from_fs2_nm_to_mg(int16_t lsb) +{ + return ( (float)lsb / 64.0f ) * 4.0f; +} + +float lis2dh12_from_fs4_nm_to_mg(int16_t lsb) +{ + return ( (float)lsb / 64.0f ) * 8.0f; +} + +float lis2dh12_from_fs8_nm_to_mg(int16_t lsb) +{ + return ( (float)lsb / 64.0f ) * 16.0f; +} + +float lis2dh12_from_fs16_nm_to_mg(int16_t lsb) +{ + return ( (float)lsb / 64.0f ) * 48.0f; +} + +float lis2dh12_from_lsb_nm_to_celsius(int16_t lsb) +{ + return ( ( (float)lsb / 64.0f ) / 4.0f ) + 25.0f; +} + +float lis2dh12_from_fs2_lp_to_mg(int16_t lsb) +{ + return ( (float)lsb / 256.0f ) * 16.0f; +} + +float lis2dh12_from_fs4_lp_to_mg(int16_t lsb) +{ + return ( (float)lsb / 256.0f ) * 32.0f; +} + +float lis2dh12_from_fs8_lp_to_mg(int16_t lsb) +{ + return ( (float)lsb / 256.0f ) * 64.0f; +} + +float lis2dh12_from_fs16_lp_to_mg(int16_t lsb) +{ + return ( (float)lsb / 256.0f ) * 192.0f; +} + +float lis2dh12_from_lsb_lp_to_celsius(int16_t lsb) +{ + return ( ( (float)lsb / 256.0f ) * 1.0f ) + 25.0f; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Data_generation + * @brief This section group all the functions concerning data generation. + * @{ + * + */ + +/** + * @brief Temperature status register.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temp_status_reg_get(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, buff, 1); + return ret; +} +/** + * @brief Temperature data available.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tda in reg STATUS_REG_AUX + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temp_data_ready_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_status_reg_aux_t status_reg_aux; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, + (uint8_t*)&status_reg_aux, 1); + *val = status_reg_aux.tda; + + return ret; +} +/** + * @brief Temperature data overrun.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tor in reg STATUS_REG_AUX + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temp_data_ovr_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_status_reg_aux_t status_reg_aux; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, + (uint8_t*)&status_reg_aux, 1); + *val = status_reg_aux.tor; + + return ret; +} +/** + * @brief Temperature output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temperature_raw_get(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_OUT_TEMP_L, buff, 2); + return ret; +} +/** + * @brief Temperature sensor enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of temp_en in reg TEMP_CFG_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temperature_meas_set(lis2dh12_ctx_t *ctx, + lis2dh12_temp_en_t val) +{ + lis2dh12_temp_cfg_reg_t temp_cfg_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1); + + if (ret == 0) { + temp_cfg_reg.temp_en = (uint8_t) val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1); + } + return ret; +} + +/** + * @brief Temperature sensor enable.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of temp_en in reg TEMP_CFG_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temperature_meas_get(lis2dh12_ctx_t *ctx, + lis2dh12_temp_en_t *val) +{ + lis2dh12_temp_cfg_reg_t temp_cfg_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1); + switch (temp_cfg_reg.temp_en) { + case LIS2DH12_TEMP_DISABLE: + *val = LIS2DH12_TEMP_DISABLE; + break; + case LIS2DH12_TEMP_ENABLE: + *val = LIS2DH12_TEMP_ENABLE; + break; + default: + *val = LIS2DH12_TEMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lpen in reg CTRL_REG1 + * and HR in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_operating_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_op_md_t val) +{ + lis2dh12_ctrl_reg1_t ctrl_reg1; + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, + (uint8_t*)&ctrl_reg1, 1); + if (ret == 0) { + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, + (uint8_t*)&ctrl_reg4, 1); + } + if (ret == 0) { + if ( val == LIS2DH12_HR_12bit ) { + ctrl_reg1.lpen = 0; + ctrl_reg4.hr = 1; + } + if (val == LIS2DH12_NM_10bit) { + ctrl_reg1.lpen = 0; + ctrl_reg4.hr = 0; + } + if (val == LIS2DH12_LP_8bit) { + ctrl_reg1.lpen = 1; + ctrl_reg4.hr = 0; + } + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1); + } + if (ret == 0) { + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief Operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of lpen in reg CTRL_REG1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_operating_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_op_md_t *val) +{ + lis2dh12_ctrl_reg1_t ctrl_reg1; + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1); + if (ret == 0) { + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if ( ctrl_reg1.lpen == PROPERTY_ENABLE ) { + *val = LIS2DH12_LP_8bit; + } + if (ctrl_reg4.hr == PROPERTY_ENABLE ) { + *val = LIS2DH12_HR_12bit; + } else { + *val = LIS2DH12_NM_10bit; + } + } + return ret; +} + +/** + * @brief Output data rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of odr in reg CTRL_REG1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_data_rate_set(lis2dh12_ctx_t *ctx, lis2dh12_odr_t val) +{ + lis2dh12_ctrl_reg1_t ctrl_reg1; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1); + + if (ret == 0) { + ctrl_reg1.odr = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1); + } + return ret; +} + +/** + * @brief Output data rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of odr in reg CTRL_REG1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_data_rate_get(lis2dh12_ctx_t *ctx, lis2dh12_odr_t *val) +{ + lis2dh12_ctrl_reg1_t ctrl_reg1; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1); + switch (ctrl_reg1.odr) { + case LIS2DH12_POWER_DOWN: + *val = LIS2DH12_POWER_DOWN; + break; + case LIS2DH12_ODR_1Hz: + *val = LIS2DH12_ODR_1Hz; + break; + case LIS2DH12_ODR_10Hz: + *val = LIS2DH12_ODR_10Hz; + break; + case LIS2DH12_ODR_25Hz: + *val = LIS2DH12_ODR_25Hz; + break; + case LIS2DH12_ODR_50Hz: + *val = LIS2DH12_ODR_50Hz; + break; + case LIS2DH12_ODR_100Hz: + *val = LIS2DH12_ODR_100Hz; + break; + case LIS2DH12_ODR_200Hz: + *val = LIS2DH12_ODR_200Hz; + break; + case LIS2DH12_ODR_400Hz: + *val = LIS2DH12_ODR_400Hz; + break; + case LIS2DH12_ODR_1kHz620_LP: + *val = LIS2DH12_ODR_1kHz620_LP; + break; + case LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP: + *val = LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP; + break; + default: + *val = LIS2DH12_POWER_DOWN; + break; + } + return ret; +} + +/** + * @brief High pass data from internal filter sent to output register + * and FIFO. + * + * @param ctx read / write interface definitions + * @param val change the values of fds in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_on_outputs_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + if (ret == 0) { + ctrl_reg2.fds = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + } + return ret; +} + +/** + * @brief High pass data from internal filter sent to output register + * and FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fds in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_on_outputs_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + *val = (uint8_t)ctrl_reg2.fds; + + return ret; +} + +/** + * @brief High-pass filter cutoff frequency selection.[set] + * + * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz + * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz + * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz + * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz + * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz + * + * @param ctx read / write interface definitions + * @param val change the values of hpcf in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_bandwidth_set(lis2dh12_ctx_t *ctx, + lis2dh12_hpcf_t val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + if (ret == 0) { + ctrl_reg2.hpcf = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + } + return ret; +} + +/** + * @brief High-pass filter cutoff frequency selection.[get] + * + * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz + * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz + * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz + * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz + * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz + * + * @param ctx read / write interface definitions + * @param val get the values of hpcf in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_bandwidth_get(lis2dh12_ctx_t *ctx, + lis2dh12_hpcf_t *val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + switch (ctrl_reg2.hpcf) { + case LIS2DH12_AGGRESSIVE: + *val = LIS2DH12_AGGRESSIVE; + break; + case LIS2DH12_STRONG: + *val = LIS2DH12_STRONG; + break; + case LIS2DH12_MEDIUM: + *val = LIS2DH12_MEDIUM; + break; + case LIS2DH12_LIGHT: + *val = LIS2DH12_LIGHT; + break; + default: + *val = LIS2DH12_LIGHT; + break; + } + return ret; +} + +/** + * @brief High-pass filter mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of hpm in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_hpm_t val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + if (ret == 0) { + ctrl_reg2.hpm = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + } + return ret; +} + +/** + * @brief High-pass filter mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of hpm in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_hpm_t *val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + switch (ctrl_reg2.hpm) { + case LIS2DH12_NORMAL_WITH_RST: + *val = LIS2DH12_NORMAL_WITH_RST; + break; + case LIS2DH12_REFERENCE_MODE: + *val = LIS2DH12_REFERENCE_MODE; + break; + case LIS2DH12_NORMAL: + *val = LIS2DH12_NORMAL; + break; + case LIS2DH12_AUTORST_ON_INT: + *val = LIS2DH12_AUTORST_ON_INT; + break; + default: + *val = LIS2DH12_NORMAL_WITH_RST; + break; + } + return ret; +} + +/** + * @brief Full-scale configuration.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fs in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_full_scale_set(lis2dh12_ctx_t *ctx, lis2dh12_fs_t val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if (ret == 0) { + ctrl_reg4.fs = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief Full-scale configuration.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of fs in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_full_scale_get(lis2dh12_ctx_t *ctx, lis2dh12_fs_t *val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + switch (ctrl_reg4.fs) { + case LIS2DH12_2g: + *val = LIS2DH12_2g; + break; + case LIS2DH12_4g: + *val = LIS2DH12_4g; + break; + case LIS2DH12_8g: + *val = LIS2DH12_8g; + break; + case LIS2DH12_16g: + *val = LIS2DH12_16g; + break; + default: + *val = LIS2DH12_2g; + break; + } + return ret; +} + +/** + * @brief Block Data Update.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of bdu in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_block_data_update_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if (ret == 0) { + ctrl_reg4.bdu = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief Block Data Update.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of bdu in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_block_data_update_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + *val = (uint8_t)ctrl_reg4.bdu; + + return ret; +} + +/** + * @brief Reference value for interrupt generation.[set] + * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_filter_reference_set(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_REFERENCE, buff, 1); + return ret; +} + +/** + * @brief Reference value for interrupt generation.[get] + * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_filter_reference_get(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_REFERENCE, buff, 1); + return ret; +} +/** + * @brief Acceleration set of data available.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of zyxda in reg STATUS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_xl_data_ready_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_status_reg_t status_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t*)&status_reg, 1); + *val = status_reg.zyxda; + + return ret; +} +/** + * @brief Acceleration set of data overrun.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of zyxor in reg STATUS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_xl_data_ovr_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_status_reg_t status_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t*)&status_reg, 1); + *val = status_reg.zyxor; + + return ret; +} +/** + * @brief Acceleration output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_acceleration_raw_get(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_OUT_X_L, buff, 6); + return ret; +} +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Common + * @brief This section group common usefull functions + * @{ + * + */ + +/** + * @brief DeviceWhoamI .[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_device_id_get(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_WHO_AM_I, buff, 1); + return ret; +} +/** + * @brief Self Test.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of st in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_self_test_set(lis2dh12_ctx_t *ctx, lis2dh12_st_t val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if (ret == 0) { + ctrl_reg4.st = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief Self Test.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of st in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_self_test_get(lis2dh12_ctx_t *ctx, lis2dh12_st_t *val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + switch (ctrl_reg4.st) { + case LIS2DH12_ST_DISABLE: + *val = LIS2DH12_ST_DISABLE; + break; + case LIS2DH12_ST_POSITIVE: + *val = LIS2DH12_ST_POSITIVE; + break; + case LIS2DH12_ST_NEGATIVE: + *val = LIS2DH12_ST_NEGATIVE; + break; + default: + *val = LIS2DH12_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Big/Little Endian data selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of ble in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_data_format_set(lis2dh12_ctx_t *ctx, lis2dh12_ble_t val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if (ret == 0) { + ctrl_reg4.ble = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief Big/Little Endian data selection.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of ble in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_data_format_get(lis2dh12_ctx_t *ctx, lis2dh12_ble_t *val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + switch (ctrl_reg4.ble) { + case LIS2DH12_LSB_AT_LOW_ADD: + *val = LIS2DH12_LSB_AT_LOW_ADD; + break; + case LIS2DH12_MSB_AT_LOW_ADD: + *val = LIS2DH12_MSB_AT_LOW_ADD; + break; + default: + *val = LIS2DH12_LSB_AT_LOW_ADD; + break; + } + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of boot in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_boot_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.boot = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of boot in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_boot_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + *val = (uint8_t)ctrl_reg5.boot; + + return ret; +} + +/** + * @brief Info about device status.[get] + * + * @param ctx read / write interface definitions + * @param val register STATUS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_status_get(lis2dh12_ctx_t *ctx, lis2dh12_status_reg_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t*) val, 1); + return ret; +} +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Interrupts_generator_1 + * @brief This section group all the functions that manage the first + * interrupts generator + * @{ + * + */ + +/** + * @brief Interrupt generator 1 configuration register.[set] + * + * @param ctx read / write interface definitions + * @param val register INT1_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_int1_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_CFG, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Interrupt generator 1 configuration register.[get] + * + * @param ctx read / write interface definitions + * @param val register INT1_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_int1_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_CFG, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Interrupt generator 1 source register.[get] + * + * @param ctx read / write interface definitions + * @param val Registers INT1_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_source_get(lis2dh12_ctx_t *ctx, + lis2dh12_int1_src_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_SRC, (uint8_t*) val, 1); + return ret; +} +/** + * @brief User-defined threshold value for xl interrupt event on + * generator 1.[set] + * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg INT1_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_int1_ths_t int1_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t*)&int1_ths, 1); + if (ret == 0) { + int1_ths.ths = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_THS, (uint8_t*)&int1_ths, 1); + } + return ret; +} + +/** + * @brief User-defined threshold value for xl interrupt event on + * generator 1.[get] + * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg INT1_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_int1_ths_t int1_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t*)&int1_ths, 1); + *val = (uint8_t)int1_ths.ths; + + return ret; +} + +/** + * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be + * recognized.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of d in reg INT1_DURATION + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_duration_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_int1_duration_t int1_duration; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION, (uint8_t*)&int1_duration, 1); + if (ret == 0) { + int1_duration.d = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_DURATION, (uint8_t*)&int1_duration, 1); + } + return ret; +} + +/** + * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be + * recognized.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of d in reg INT1_DURATION + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_duration_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_int1_duration_t int1_duration; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION, (uint8_t*)&int1_duration, 1); + *val = (uint8_t)int1_duration.d; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Interrupts_generator_2 + * @brief This section group all the functions that manage the second + * interrupts generator + * @{ + * + */ + +/** + * @brief Interrupt generator 2 configuration register.[set] + * + * @param ctx read / write interface definitions + * @param val registers INT2_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_int2_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_CFG, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Interrupt generator 2 configuration register.[get] + * + * @param ctx read / write interface definitions + * @param val registers INT2_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_int2_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_CFG, (uint8_t*) val, 1); + return ret; +} +/** + * @brief Interrupt generator 2 source register.[get] + * + * @param ctx read / write interface definitions + * @param val registers INT2_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_source_get(lis2dh12_ctx_t *ctx, + lis2dh12_int2_src_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_SRC, (uint8_t*) val, 1); + return ret; +} +/** + * @brief User-defined threshold value for xl interrupt event on + * generator 2.[set] + * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg INT2_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_int2_ths_t int2_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t*)&int2_ths, 1); + if (ret == 0) { + int2_ths.ths = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_THS, (uint8_t*)&int2_ths, 1); + } + return ret; +} + +/** + * @brief User-defined threshold value for xl interrupt event on + * generator 2.[get] + * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg INT2_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_int2_ths_t int2_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t*)&int2_ths, 1); + *val = (uint8_t)int2_ths.ths; + + return ret; +} + +/** + * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be + * recognized .[set] + * + * @param ctx read / write interface definitions + * @param val change the values of d in reg INT2_DURATION + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_duration_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_int2_duration_t int2_duration; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION, (uint8_t*)&int2_duration, 1); + if (ret == 0) { + int2_duration.d = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_DURATION, (uint8_t*)&int2_duration, 1); + } + return ret; +} + +/** + * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be + * recognized.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of d in reg INT2_DURATION + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_duration_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_int2_duration_t int2_duration; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION, (uint8_t*)&int2_duration, 1); + *val = (uint8_t)int2_duration.d; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Interrupt_pins + * @brief This section group all the functions that manage interrup pins + * @{ + * + */ + +/** + * @brief High-pass filter on interrupts/tap generator.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of hp in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_int_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_hp_t val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + if (ret == 0) { + ctrl_reg2.hp = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + } + return ret; +} + +/** + * @brief High-pass filter on interrupts/tap generator.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of hp in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_int_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_hp_t *val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + switch (ctrl_reg2.hp) { + case LIS2DH12_DISC_FROM_INT_GENERATOR: + *val = LIS2DH12_DISC_FROM_INT_GENERATOR; + break; + case LIS2DH12_ON_INT1_GEN: + *val = LIS2DH12_ON_INT1_GEN; + break; + case LIS2DH12_ON_INT2_GEN: + *val = LIS2DH12_ON_INT2_GEN; + break; + case LIS2DH12_ON_TAP_GEN: + *val = LIS2DH12_ON_TAP_GEN; + break; + case LIS2DH12_ON_INT1_INT2_GEN: + *val = LIS2DH12_ON_INT1_INT2_GEN; + break; + case LIS2DH12_ON_INT1_TAP_GEN: + *val = LIS2DH12_ON_INT1_TAP_GEN; + break; + case LIS2DH12_ON_INT2_TAP_GEN: + *val = LIS2DH12_ON_INT2_TAP_GEN; + break; + case LIS2DH12_ON_INT1_INT2_TAP_GEN: + *val = LIS2DH12_ON_INT1_INT2_TAP_GEN; + break; + default: + *val = LIS2DH12_DISC_FROM_INT_GENERATOR; + break; + } + return ret; +} + +/** + * @brief Int1 pin routing configuration register.[set] + * + * @param ctx read / write interface definitions + * @param val registers CTRL_REG3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_int1_config_set(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg3_t *val) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG3, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Int1 pin routing configuration register.[get] + * + * @param ctx read / write interface definitions + * @param val registers CTRL_REG3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_int1_config_get(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg3_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG3, (uint8_t*) val, 1); + return ret; +} +/** + * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled + * on INT2 pin when 6D bit on + * INT2_CFG (34h) is set to 1. + * + * @param ctx read / write interface definitions + * @param val change the values of d4d_int2 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_pin_detect_4d_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.d4d_int2 = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on + * INT2_CFG (34h) is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of d4d_int2 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_pin_detect_4d_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + *val = (uint8_t)ctrl_reg5.d4d_int2; + + return ret; +} + +/** + * @brief Latch interrupt request on INT2_SRC (35h) register, with + * INT2_SRC (35h) register cleared by reading INT2_SRC(35h) + * itself.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lir_int2 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_pin_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int2_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.lir_int2 = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief Latch interrupt request on INT2_SRC (35h) register, with + * INT2_SRC (35h) register cleared by reading INT2_SRC(35h) + * itself.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of lir_int2 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_pin_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int2_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + switch (ctrl_reg5.lir_int2) { + case LIS2DH12_INT2_PULSED: + *val = LIS2DH12_INT2_PULSED; + break; + case LIS2DH12_INT2_LATCHED: + *val = LIS2DH12_INT2_LATCHED; + break; + default: + *val = LIS2DH12_INT2_PULSED; + break; + } + return ret; +} + +/** + * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit + * on INT1_CFG(30h) is set to 1.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of d4d_int1 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_pin_detect_4d_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.d4d_int1 = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on + * INT1_CFG(30h) is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of d4d_int1 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_pin_detect_4d_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + *val = (uint8_t)ctrl_reg5.d4d_int1; + + return ret; +} + +/** + * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h) + * register cleared by reading INT1_SRC (31h) itself.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lir_int1 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_pin_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int1_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.lir_int1 = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h) + * register cleared by reading INT1_SRC (31h) itself.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of lir_int1 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_pin_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int1_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + switch (ctrl_reg5.lir_int1) { + case LIS2DH12_INT1_PULSED: + *val = LIS2DH12_INT1_PULSED; + break; + case LIS2DH12_INT1_LATCHED: + *val = LIS2DH12_INT1_LATCHED; + break; + default: + *val = LIS2DH12_INT1_PULSED; + break; + } + return ret; +} + +/** + * @brief Int2 pin routing configuration register.[set] + * + * @param ctx read / write interface definitions + * @param val registers CTRL_REG6 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_int2_config_set(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg6_t *val) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG6, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Int2 pin routing configuration register.[get] + * + * @param ctx read / write interface definitions + * @param val registers CTRL_REG6 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_int2_config_get(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg6_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG6, (uint8_t*) val, 1); + return ret; +} +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Fifo + * @brief This section group all the functions concerning the fifo usage + * @{ + * + */ + +/** + * @brief FIFO enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fifo_en in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.fifo_en = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief FIFO enable.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fifo_en in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + *val = (uint8_t)ctrl_reg5.fifo_en; + + return ret; +} + +/** + * @brief FIFO watermark level selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fth in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_watermark_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + if (ret == 0) { + fifo_ctrl_reg.fth = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + } + return ret; +} + +/** + * @brief FIFO watermark level selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fth in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_watermark_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + *val = (uint8_t)fifo_ctrl_reg.fth; + + return ret; +} + +/** + * @brief Trigger FIFO selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tr in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_trigger_event_set(lis2dh12_ctx_t *ctx, + lis2dh12_tr_t val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + if (ret == 0) { + fifo_ctrl_reg.tr = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + } + return ret; +} + +/** + * @brief Trigger FIFO selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of tr in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_trigger_event_get(lis2dh12_ctx_t *ctx, + lis2dh12_tr_t *val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + switch (fifo_ctrl_reg.tr) { + case LIS2DH12_INT1_GEN: + *val = LIS2DH12_INT1_GEN; + break; + case LIS2DH12_INT2_GEN: + *val = LIS2DH12_INT2_GEN; + break; + default: + *val = LIS2DH12_INT1_GEN; + break; + } + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fm in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_fm_t val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + if (ret == 0) { + fifo_ctrl_reg.fm = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + } + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of fm in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_fm_t *val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + switch (fifo_ctrl_reg.fm) { + case LIS2DH12_BYPASS_MODE: + *val = LIS2DH12_BYPASS_MODE; + break; + case LIS2DH12_FIFO_MODE: + *val = LIS2DH12_FIFO_MODE; + break; + case LIS2DH12_DYNAMIC_STREAM_MODE: + *val = LIS2DH12_DYNAMIC_STREAM_MODE; + break; + case LIS2DH12_STREAM_TO_FIFO_MODE: + *val = LIS2DH12_STREAM_TO_FIFO_MODE; + break; + default: + *val = LIS2DH12_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief FIFO status register.[get] + * + * @param ctx read / write interface definitions + * @param val registers FIFO_SRC_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_status_get(lis2dh12_ctx_t *ctx, + lis2dh12_fifo_src_reg_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*) val, 1); + return ret; +} +/** + * @brief FIFO stored data level.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fss in reg FIFO_SRC_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_data_level_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_fifo_src_reg_t fifo_src_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1); + *val = (uint8_t)fifo_src_reg.fss; + + return ret; +} +/** + * @brief Empty FIFO status flag.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of empty in reg FIFO_SRC_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_empty_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_fifo_src_reg_t fifo_src_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1); + *val = (uint8_t)fifo_src_reg.empty; + + return ret; +} +/** + * @brief FIFO overrun status flag.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_ovr_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_fifo_src_reg_t fifo_src_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1); + *val = (uint8_t)fifo_src_reg.ovrn_fifo; + + return ret; +} +/** + * @brief FIFO watermark status.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of wtm in reg FIFO_SRC_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_fth_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_fifo_src_reg_t fifo_src_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1); + *val = (uint8_t)fifo_src_reg.wtm; + + return ret; +} +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Tap_generator + * @brief This section group all the functions that manage the tap and + * double tap event generation + * @{ + * + */ + +/** + * @brief Tap/Double Tap generator configuration register.[set] + * + * @param ctx read / write interface definitions + * @param val registers CLICK_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_conf_set(lis2dh12_ctx_t *ctx, lis2dh12_click_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_CFG, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Tap/Double Tap generator configuration register.[get] + * + * @param ctx read / write interface definitions + * @param val registers CLICK_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_conf_get(lis2dh12_ctx_t *ctx, lis2dh12_click_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_CFG, (uint8_t*) val, 1); + return ret; +} +/** + * @brief Tap/Double Tap generator source register.[get] + * + * @param ctx read / write interface definitions + * @param val registers CLICK_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_source_get(lis2dh12_ctx_t *ctx, lis2dh12_click_src_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_SRC, (uint8_t*) val, 1); + return ret; +} +/** + * @brief User-defined threshold value for Tap/Double Tap event.[set] + * 1 LSB = full scale/128 + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg CLICK_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_click_ths_t click_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + if (ret == 0) { + click_ths.ths = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + } + return ret; +} + +/** + * @brief User-defined threshold value for Tap/Double Tap event.[get] + * 1 LSB = full scale/128 + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg CLICK_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_click_ths_t click_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + *val = (uint8_t)click_ths.ths; + + return ret; +} + +/** + * @brief If the LIR_Click bit is not set, the interrupt is kept high + * for the duration of the latency window. + * If the LIR_Click bit is set, the interrupt is kept high until the + * CLICK_SRC(39h) register is read.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lir_click in reg CLICK_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_click_t val) +{ + lis2dh12_click_ths_t click_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + if (ret == 0) { + click_ths.lir_click = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + } + return ret; +} + +/** + * @brief If the LIR_Click bit is not set, the interrupt is kept high + * for the duration of the latency window. + * If the LIR_Click bit is set, the interrupt is kept high until the + * CLICK_SRC(39h) register is read.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of lir_click in reg CLICK_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_click_t *val) +{ + lis2dh12_click_ths_t click_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + switch (click_ths.lir_click) { + case LIS2DH12_TAP_PULSED: + *val = LIS2DH12_TAP_PULSED; + break; + case LIS2DH12_TAP_LATCHED: + *val = LIS2DH12_TAP_LATCHED; + break; + default: + *val = LIS2DH12_TAP_PULSED; + break; + } + return ret; +} + +/** + * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse + * between the start of the click-detection procedure and when the + * acceleration falls back below the threshold.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tli in reg TIME_LIMIT + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_shock_dur_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_time_limit_t time_limit; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT, (uint8_t*)&time_limit, 1); + if (ret == 0) { + time_limit.tli = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_LIMIT, (uint8_t*)&time_limit, 1); + } + return ret; +} + +/** + * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between + * the start of the click-detection procedure and when the + * acceleration falls back below the threshold.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tli in reg TIME_LIMIT + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_shock_dur_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_time_limit_t time_limit; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT, (uint8_t*)&time_limit, 1); + *val = (uint8_t)time_limit.tli; + + return ret; +} + +/** + * @brief The time (1 LSB = 1/ODR) interval that starts after the first + * click detection where the click-detection procedure is + * disabled, in cases where the device is configured for + * double-click detection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tla in reg TIME_LATENCY + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_quiet_dur_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_time_latency_t time_latency; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY, (uint8_t*)&time_latency, 1); + if (ret == 0) { + time_latency.tla = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_LATENCY, (uint8_t*)&time_latency, 1); + } + return ret; +} + +/** + * @brief The time (1 LSB = 1/ODR) interval that starts after the first + * click detection where the click-detection procedure is + * disabled, in cases where the device is configured for + * double-click detection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tla in reg TIME_LATENCY + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_quiet_dur_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_time_latency_t time_latency; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY, (uint8_t*)&time_latency, 1); + *val = (uint8_t)time_latency.tla; + + return ret; +} + +/** + * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse + * after the end of the latency interval in which the click-detection + * procedure can start, in cases where the device is configured + * for double-click detection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tw in reg TIME_WINDOW + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_double_tap_timeout_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_time_window_t time_window; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW, (uint8_t*)&time_window, 1); + if (ret == 0) { + time_window.tw = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_WINDOW, (uint8_t*)&time_window, 1); + } + return ret; +} + +/** + * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse + * after the end of the latency interval in which the + * click-detection procedure can start, in cases where the device + * is configured for double-click detection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tw in reg TIME_WINDOW + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_double_tap_timeout_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_time_window_t time_window; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW, (uint8_t*)&time_window, 1); + *val = (uint8_t)time_window.tw; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Activity_inactivity + * @brief This section group all the functions concerning activity + * inactivity functionality + * @{ + * + */ + +/** + * @brief Sleep-to-wake, return-to-sleep activation threshold in + * low-power mode.[set] + * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of acth in reg ACT_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_act_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_act_ths_t act_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t*)&act_ths, 1); + if (ret == 0) { + act_ths.acth = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_ACT_THS, (uint8_t*)&act_ths, 1); + } + return ret; +} + +/** + * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power + * mode.[get] + * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of acth in reg ACT_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_act_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_act_ths_t act_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t*)&act_ths, 1); + *val = (uint8_t)act_ths.acth; + + return ret; +} + +/** + * @brief Sleep-to-wake, return-to-sleep.[set] + * duration = (8*1[LSb]+1)/ODR + * + * @param ctx read / write interface definitions + * @param val change the values of actd in reg ACT_DUR + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_act_timeout_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_act_dur_t act_dur; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t*)&act_dur, 1); + if (ret == 0) { + act_dur.actd = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t*)&act_dur, 1); + } + return ret; +} + +/** + * @brief Sleep-to-wake, return-to-sleep.[get] + * duration = (8*1[LSb]+1)/ODR + * + * @param ctx read / write interface definitions + * @param val change the values of actd in reg ACT_DUR + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_act_timeout_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_act_dur_t act_dur; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t*)&act_dur, 1); + *val = (uint8_t)act_dur.actd; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Serial_interface + * @brief This section group all the functions concerning serial + * interface management + * @{ + * + */ + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sdo_pu_disc in reg CTRL_REG0 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_sdo_sa0_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_sdo_pu_disc_t val) +{ + lis2dh12_ctrl_reg0_t ctrl_reg0; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1); + if (ret == 0) { + ctrl_reg0.sdo_pu_disc = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1); + } + return ret; +} + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of sdo_pu_disc in reg CTRL_REG0 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_sdo_sa0_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_sdo_pu_disc_t *val) +{ + lis2dh12_ctrl_reg0_t ctrl_reg0; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1); + switch (ctrl_reg0.sdo_pu_disc) { + case LIS2DH12_PULL_UP_DISCONNECT: + *val = LIS2DH12_PULL_UP_DISCONNECT; + break; + case LIS2DH12_PULL_UP_CONNECT: + *val = LIS2DH12_PULL_UP_CONNECT; + break; + default: + *val = LIS2DH12_PULL_UP_DISCONNECT; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sim in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_spi_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_sim_t val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if (ret == 0) { + ctrl_reg4.sim = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of sim in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_spi_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_sim_t *val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + switch (ctrl_reg4.sim) { + case LIS2DH12_SPI_4_WIRE: + *val = LIS2DH12_SPI_4_WIRE; + break; + case LIS2DH12_SPI_3_WIRE: + *val = LIS2DH12_SPI_3_WIRE; + break; + default: + *val = LIS2DH12_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.h new file mode 100644 index 0000000..3ca4f62 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.h @@ -0,0 +1,764 @@ +/* + ****************************************************************************** + * @file lis2dh12_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lis2dh12_reg.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2018 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ +// SPDX-License-Identifier: BSD-3-Clause + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LIS2DH12_REGS_H +#define LIS2DH12_REGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include + +/** @addtogroup LIS2DH12 + * @{ + * + */ + +/** @defgroup LIS2DH12_sensors_common_types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +/** + * @defgroup axisXbitXX_t + * @brief These unions are useful to represent different sensors data type. + * These unions are not need by the driver. + * + * REMOVING the unions you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ + +typedef union{ + int16_t i16bit[3]; + uint8_t u8bit[6]; +} axis3bit16_t; + +typedef union{ + int16_t i16bit; + uint8_t u8bit[2]; +} axis1bit16_t; + +typedef union{ + int32_t i32bit[3]; + uint8_t u8bit[12]; +} axis3bit32_t; + +typedef union{ + int32_t i32bit; + uint8_t u8bit[4]; +} axis1bit32_t; + +/** + * @} + * + */ + +typedef struct{ + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +#endif /* MEMS_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @addtogroup LIS3MDL_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*lis2dh12_write_ptr)(void *, uint8_t, uint8_t*, uint16_t); +typedef int32_t (*lis2dh12_read_ptr) (void *, uint8_t, uint8_t*, uint16_t); + +typedef struct { + /** Component mandatory fields **/ + lis2dh12_write_ptr write_reg; + lis2dh12_read_ptr read_reg; + /** Customizable optional pointer **/ + void *handle; +} lis2dh12_ctx_t; + +/** + * @} + * + */ + +/** @defgroup LIS2DH12_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ +#define LIS2DH12_I2C_ADD_L 0x31U +#define LIS2DH12_I2C_ADD_H 0x33U + +/** Device Identification (Who am I) **/ +#define LIS2DH12_ID 0x33U + +/** + * @} + * + */ + +#define LIS2DH12_STATUS_REG_AUX 0x07U +typedef struct { + uint8_t not_used_01 : 2; + uint8_t tda : 1; + uint8_t not_used_02 : 3; + uint8_t tor : 1; + uint8_t not_used_03 : 1; +} lis2dh12_status_reg_aux_t; + +#define LIS2DH12_OUT_TEMP_L 0x0CU +#define LIS2DH12_OUT_TEMP_H 0x0DU +#define LIS2DH12_WHO_AM_I 0x0FU + +#define LIS2DH12_CTRL_REG0 0x1EU +typedef struct { + uint8_t not_used_01 : 7; + uint8_t sdo_pu_disc : 1; +} lis2dh12_ctrl_reg0_t; + +#define LIS2DH12_TEMP_CFG_REG 0x1FU +typedef struct { + uint8_t not_used_01 : 6; + uint8_t temp_en : 2; +} lis2dh12_temp_cfg_reg_t; + +#define LIS2DH12_CTRL_REG1 0x20U +typedef struct { + uint8_t xen : 1; + uint8_t yen : 1; + uint8_t zen : 1; + uint8_t lpen : 1; + uint8_t odr : 4; +} lis2dh12_ctrl_reg1_t; + +#define LIS2DH12_CTRL_REG2 0x21U +typedef struct { + uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ + uint8_t fds : 1; + uint8_t hpcf : 2; + uint8_t hpm : 2; +} lis2dh12_ctrl_reg2_t; + +#define LIS2DH12_CTRL_REG3 0x22U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t i1_overrun : 1; + uint8_t i1_wtm : 1; + uint8_t not_used_02 : 1; + uint8_t i1_zyxda : 1; + uint8_t i1_ia2 : 1; + uint8_t i1_ia1 : 1; + uint8_t i1_click : 1; +} lis2dh12_ctrl_reg3_t; + +#define LIS2DH12_CTRL_REG4 0x23U +typedef struct { + uint8_t sim : 1; + uint8_t st : 2; + uint8_t hr : 1; + uint8_t fs : 2; + uint8_t ble : 1; + uint8_t bdu : 1; +} lis2dh12_ctrl_reg4_t; + +#define LIS2DH12_CTRL_REG5 0x24U +typedef struct { + uint8_t d4d_int2 : 1; + uint8_t lir_int2 : 1; + uint8_t d4d_int1 : 1; + uint8_t lir_int1 : 1; + uint8_t not_used_01 : 2; + uint8_t fifo_en : 1; + uint8_t boot : 1; +} lis2dh12_ctrl_reg5_t; + +#define LIS2DH12_CTRL_REG6 0x25U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t int_polarity : 1; + uint8_t not_used_02 : 1; + uint8_t i2_act : 1; + uint8_t i2_boot : 1; + uint8_t i2_ia2 : 1; + uint8_t i2_ia1 : 1; + uint8_t i2_click : 1; +} lis2dh12_ctrl_reg6_t; + +#define LIS2DH12_REFERENCE 0x26U +#define LIS2DH12_STATUS_REG 0x27U +typedef struct { + uint8_t xda : 1; + uint8_t yda : 1; + uint8_t zda : 1; + uint8_t zyxda : 1; + uint8_t _xor : 1; + uint8_t yor : 1; + uint8_t zor : 1; + uint8_t zyxor : 1; +} lis2dh12_status_reg_t; + +#define LIS2DH12_OUT_X_L 0x28U +#define LIS2DH12_OUT_X_H 0x29U +#define LIS2DH12_OUT_Y_L 0x2AU +#define LIS2DH12_OUT_Y_H 0x2BU +#define LIS2DH12_OUT_Z_L 0x2CU +#define LIS2DH12_OUT_Z_H 0x2DU +#define LIS2DH12_FIFO_CTRL_REG 0x2EU +typedef struct { + uint8_t fth : 5; + uint8_t tr : 1; + uint8_t fm : 2; +} lis2dh12_fifo_ctrl_reg_t; + +#define LIS2DH12_FIFO_SRC_REG 0x2FU +typedef struct { + uint8_t fss : 5; + uint8_t empty : 1; + uint8_t ovrn_fifo : 1; + uint8_t wtm : 1; +} lis2dh12_fifo_src_reg_t; + +#define LIS2DH12_INT1_CFG 0x30U +typedef struct { + uint8_t xlie : 1; + uint8_t xhie : 1; + uint8_t ylie : 1; + uint8_t yhie : 1; + uint8_t zlie : 1; + uint8_t zhie : 1; + uint8_t _6d : 1; + uint8_t aoi : 1; +} lis2dh12_int1_cfg_t; + +#define LIS2DH12_INT1_SRC 0x31U +typedef struct { + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t ia : 1; + uint8_t not_used_01 : 1; +} lis2dh12_int1_src_t; + +#define LIS2DH12_INT1_THS 0x32U +typedef struct { + uint8_t ths : 7; + uint8_t not_used_01 : 1; +} lis2dh12_int1_ths_t; + +#define LIS2DH12_INT1_DURATION 0x33U +typedef struct { + uint8_t d : 7; + uint8_t not_used_01 : 1; +} lis2dh12_int1_duration_t; + +#define LIS2DH12_INT2_CFG 0x34U +typedef struct { + uint8_t xlie : 1; + uint8_t xhie : 1; + uint8_t ylie : 1; + uint8_t yhie : 1; + uint8_t zlie : 1; + uint8_t zhie : 1; + uint8_t _6d : 1; + uint8_t aoi : 1; +} lis2dh12_int2_cfg_t; + +#define LIS2DH12_INT2_SRC 0x35U +typedef struct { + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t ia : 1; + uint8_t not_used_01 : 1; +} lis2dh12_int2_src_t; + +#define LIS2DH12_INT2_THS 0x36U +typedef struct { + uint8_t ths : 7; + uint8_t not_used_01 : 1; +} lis2dh12_int2_ths_t; + +#define LIS2DH12_INT2_DURATION 0x37U +typedef struct { + uint8_t d : 7; + uint8_t not_used_01 : 1; +} lis2dh12_int2_duration_t; + +#define LIS2DH12_CLICK_CFG 0x38U +typedef struct { + uint8_t xs : 1; + uint8_t xd : 1; + uint8_t ys : 1; + uint8_t yd : 1; + uint8_t zs : 1; + uint8_t zd : 1; + uint8_t not_used_01 : 2; +} lis2dh12_click_cfg_t; + +#define LIS2DH12_CLICK_SRC 0x39U +typedef struct { + uint8_t x : 1; + uint8_t y : 1; + uint8_t z : 1; + uint8_t sign : 1; + uint8_t sclick : 1; + uint8_t dclick : 1; + uint8_t ia : 1; + uint8_t not_used_01 : 1; +} lis2dh12_click_src_t; + +#define LIS2DH12_CLICK_THS 0x3AU +typedef struct { + uint8_t ths : 7; + uint8_t lir_click : 1; +} lis2dh12_click_ths_t; + +#define LIS2DH12_TIME_LIMIT 0x3BU +typedef struct { + uint8_t tli : 7; + uint8_t not_used_01 : 1; +} lis2dh12_time_limit_t; + +#define LIS2DH12_TIME_LATENCY 0x3CU +typedef struct { + uint8_t tla : 8; +} lis2dh12_time_latency_t; + +#define LIS2DH12_TIME_WINDOW 0x3DU +typedef struct { + uint8_t tw : 8; +} lis2dh12_time_window_t; + +#define LIS2DH12_ACT_THS 0x3EU +typedef struct { + uint8_t acth : 7; + uint8_t not_used_01 : 1; +} lis2dh12_act_ths_t; + +#define LIS2DH12_ACT_DUR 0x3FU +typedef struct { + uint8_t actd : 8; +} lis2dh12_act_dur_t; + +/** + * @defgroup LIS2DH12_Register_Union + * @brief This union group all the registers that has a bitfield + * description. + * This union is usefull but not need by the driver. + * + * REMOVING this union you are complient with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union{ + lis2dh12_status_reg_aux_t status_reg_aux; + lis2dh12_ctrl_reg0_t ctrl_reg0; + lis2dh12_temp_cfg_reg_t temp_cfg_reg; + lis2dh12_ctrl_reg1_t ctrl_reg1; + lis2dh12_ctrl_reg2_t ctrl_reg2; + lis2dh12_ctrl_reg3_t ctrl_reg3; + lis2dh12_ctrl_reg4_t ctrl_reg4; + lis2dh12_ctrl_reg5_t ctrl_reg5; + lis2dh12_ctrl_reg6_t ctrl_reg6; + lis2dh12_status_reg_t status_reg; + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + lis2dh12_fifo_src_reg_t fifo_src_reg; + lis2dh12_int1_cfg_t int1_cfg; + lis2dh12_int1_src_t int1_src; + lis2dh12_int1_ths_t int1_ths; + lis2dh12_int1_duration_t int1_duration; + lis2dh12_int2_cfg_t int2_cfg; + lis2dh12_int2_src_t int2_src; + lis2dh12_int2_ths_t int2_ths; + lis2dh12_int2_duration_t int2_duration; + lis2dh12_click_cfg_t click_cfg; + lis2dh12_click_src_t click_src; + lis2dh12_click_ths_t click_ths; + lis2dh12_time_limit_t time_limit; + lis2dh12_time_latency_t time_latency; + lis2dh12_time_window_t time_window; + lis2dh12_act_ths_t act_ths; + lis2dh12_act_dur_t act_dur; + bitwise_t bitwise; + uint8_t byte; +} lis2dh12_reg_t; + +/** + * @} + * + */ + +int32_t lis2dh12_read_reg(lis2dh12_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); +int32_t lis2dh12_write_reg(lis2dh12_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); + +extern float lis2dh12_from_fs2_hr_to_mg(int16_t lsb); +extern float lis2dh12_from_fs4_hr_to_mg(int16_t lsb); +extern float lis2dh12_from_fs8_hr_to_mg(int16_t lsb); +extern float lis2dh12_from_fs16_hr_to_mg(int16_t lsb); +extern float lis2dh12_from_lsb_hr_to_celsius(int16_t lsb); + +extern float lis2dh12_from_fs2_nm_to_mg(int16_t lsb); +extern float lis2dh12_from_fs4_nm_to_mg(int16_t lsb); +extern float lis2dh12_from_fs8_nm_to_mg(int16_t lsb); +extern float lis2dh12_from_fs16_nm_to_mg(int16_t lsb); +extern float lis2dh12_from_lsb_nm_to_celsius(int16_t lsb); + +extern float lis2dh12_from_fs2_lp_to_mg(int16_t lsb); +extern float lis2dh12_from_fs4_lp_to_mg(int16_t lsb); +extern float lis2dh12_from_fs8_lp_to_mg(int16_t lsb); +extern float lis2dh12_from_fs16_lp_to_mg(int16_t lsb); +extern float lis2dh12_from_lsb_lp_to_celsius(int16_t lsb); + +int32_t lis2dh12_temp_status_reg_get(lis2dh12_ctx_t *ctx, uint8_t *buff); +int32_t lis2dh12_temp_data_ready_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_temp_data_ovr_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_temperature_raw_get(lis2dh12_ctx_t *ctx, uint8_t *buff); + +typedef enum { + LIS2DH12_TEMP_DISABLE = 0, + LIS2DH12_TEMP_ENABLE = 3, +} lis2dh12_temp_en_t; +int32_t lis2dh12_temperature_meas_set(lis2dh12_ctx_t *ctx, + lis2dh12_temp_en_t val); +int32_t lis2dh12_temperature_meas_get(lis2dh12_ctx_t *ctx, + lis2dh12_temp_en_t *val); + +typedef enum { + LIS2DH12_HR_12bit = 0, + LIS2DH12_NM_10bit = 1, + LIS2DH12_LP_8bit = 2, +} lis2dh12_op_md_t; +int32_t lis2dh12_operating_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_op_md_t val); +int32_t lis2dh12_operating_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_op_md_t *val); + +typedef enum { + LIS2DH12_POWER_DOWN = 0x00, + LIS2DH12_ODR_1Hz = 0x01, + LIS2DH12_ODR_10Hz = 0x02, + LIS2DH12_ODR_25Hz = 0x03, + LIS2DH12_ODR_50Hz = 0x04, + LIS2DH12_ODR_100Hz = 0x05, + LIS2DH12_ODR_200Hz = 0x06, + LIS2DH12_ODR_400Hz = 0x07, + LIS2DH12_ODR_1kHz620_LP = 0x08, + LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, +} lis2dh12_odr_t; +int32_t lis2dh12_data_rate_set(lis2dh12_ctx_t *ctx, lis2dh12_odr_t val); +int32_t lis2dh12_data_rate_get(lis2dh12_ctx_t *ctx, lis2dh12_odr_t *val); + +int32_t lis2dh12_high_pass_on_outputs_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_high_pass_on_outputs_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_AGGRESSIVE = 0, + LIS2DH12_STRONG = 1, + LIS2DH12_MEDIUM = 2, + LIS2DH12_LIGHT = 3, +} lis2dh12_hpcf_t; +int32_t lis2dh12_high_pass_bandwidth_set(lis2dh12_ctx_t *ctx, + lis2dh12_hpcf_t val); +int32_t lis2dh12_high_pass_bandwidth_get(lis2dh12_ctx_t *ctx, + lis2dh12_hpcf_t *val); + +typedef enum { + LIS2DH12_NORMAL_WITH_RST = 0, + LIS2DH12_REFERENCE_MODE = 1, + LIS2DH12_NORMAL = 2, + LIS2DH12_AUTORST_ON_INT = 3, +} lis2dh12_hpm_t; +int32_t lis2dh12_high_pass_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_hpm_t val); +int32_t lis2dh12_high_pass_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_hpm_t *val); + +typedef enum { + LIS2DH12_2g = 0, + LIS2DH12_4g = 1, + LIS2DH12_8g = 2, + LIS2DH12_16g = 3, +} lis2dh12_fs_t; +int32_t lis2dh12_full_scale_set(lis2dh12_ctx_t *ctx, lis2dh12_fs_t val); +int32_t lis2dh12_full_scale_get(lis2dh12_ctx_t *ctx, lis2dh12_fs_t *val); + +int32_t lis2dh12_block_data_update_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_block_data_update_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_filter_reference_set(lis2dh12_ctx_t *ctx, uint8_t *buff); +int32_t lis2dh12_filter_reference_get(lis2dh12_ctx_t *ctx, uint8_t *buff); + +int32_t lis2dh12_xl_data_ready_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_xl_data_ovr_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_acceleration_raw_get(lis2dh12_ctx_t *ctx, uint8_t *buff); + +int32_t lis2dh12_device_id_get(lis2dh12_ctx_t *ctx, uint8_t *buff); + +typedef enum { + LIS2DH12_ST_DISABLE = 0, + LIS2DH12_ST_POSITIVE = 1, + LIS2DH12_ST_NEGATIVE = 2, +} lis2dh12_st_t; +int32_t lis2dh12_self_test_set(lis2dh12_ctx_t *ctx, lis2dh12_st_t val); +int32_t lis2dh12_self_test_get(lis2dh12_ctx_t *ctx, lis2dh12_st_t *val); + +typedef enum { + LIS2DH12_LSB_AT_LOW_ADD = 0, + LIS2DH12_MSB_AT_LOW_ADD = 1, +} lis2dh12_ble_t; +int32_t lis2dh12_data_format_set(lis2dh12_ctx_t *ctx, lis2dh12_ble_t val); +int32_t lis2dh12_data_format_get(lis2dh12_ctx_t *ctx, lis2dh12_ble_t *val); + +int32_t lis2dh12_boot_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_boot_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_status_get(lis2dh12_ctx_t *ctx, lis2dh12_status_reg_t *val); + +int32_t lis2dh12_int1_gen_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_int1_cfg_t *val); +int32_t lis2dh12_int1_gen_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_int1_cfg_t *val); + +int32_t lis2dh12_int1_gen_source_get(lis2dh12_ctx_t *ctx, + lis2dh12_int1_src_t *val); + +int32_t lis2dh12_int1_gen_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int1_gen_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_int1_gen_duration_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int1_gen_duration_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_int2_gen_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_int2_cfg_t *val); +int32_t lis2dh12_int2_gen_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_int2_cfg_t *val); + +int32_t lis2dh12_int2_gen_source_get(lis2dh12_ctx_t *ctx, + lis2dh12_int2_src_t *val); + +int32_t lis2dh12_int2_gen_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int2_gen_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_int2_gen_duration_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int2_gen_duration_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_DISC_FROM_INT_GENERATOR = 0, + LIS2DH12_ON_INT1_GEN = 1, + LIS2DH12_ON_INT2_GEN = 2, + LIS2DH12_ON_TAP_GEN = 4, + LIS2DH12_ON_INT1_INT2_GEN = 3, + LIS2DH12_ON_INT1_TAP_GEN = 5, + LIS2DH12_ON_INT2_TAP_GEN = 6, + LIS2DH12_ON_INT1_INT2_TAP_GEN = 7, +} lis2dh12_hp_t; +int32_t lis2dh12_high_pass_int_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_hp_t val); +int32_t lis2dh12_high_pass_int_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_hp_t *val); + +int32_t lis2dh12_pin_int1_config_set(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg3_t *val); +int32_t lis2dh12_pin_int1_config_get(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg3_t *val); + +int32_t lis2dh12_int2_pin_detect_4d_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int2_pin_detect_4d_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_INT2_PULSED = 0, + LIS2DH12_INT2_LATCHED = 1, +} lis2dh12_lir_int2_t; +int32_t lis2dh12_int2_pin_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int2_t val); +int32_t lis2dh12_int2_pin_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int2_t *val); + +int32_t lis2dh12_int1_pin_detect_4d_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int1_pin_detect_4d_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_INT1_PULSED = 0, + LIS2DH12_INT1_LATCHED = 1, +} lis2dh12_lir_int1_t; +int32_t lis2dh12_int1_pin_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int1_t val); +int32_t lis2dh12_int1_pin_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int1_t *val); + +int32_t lis2dh12_pin_int2_config_set(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg6_t *val); +int32_t lis2dh12_pin_int2_config_get(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg6_t *val); + +int32_t lis2dh12_fifo_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_fifo_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_fifo_watermark_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_fifo_watermark_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_INT1_GEN = 0, + LIS2DH12_INT2_GEN = 1, +} lis2dh12_tr_t; +int32_t lis2dh12_fifo_trigger_event_set(lis2dh12_ctx_t *ctx, + lis2dh12_tr_t val); +int32_t lis2dh12_fifo_trigger_event_get(lis2dh12_ctx_t *ctx, + lis2dh12_tr_t *val); + +typedef enum { + LIS2DH12_BYPASS_MODE = 0, + LIS2DH12_FIFO_MODE = 1, + LIS2DH12_DYNAMIC_STREAM_MODE = 2, + LIS2DH12_STREAM_TO_FIFO_MODE = 3, +} lis2dh12_fm_t; +int32_t lis2dh12_fifo_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_fm_t val); +int32_t lis2dh12_fifo_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_fm_t *val); + +int32_t lis2dh12_fifo_status_get(lis2dh12_ctx_t *ctx, + lis2dh12_fifo_src_reg_t *val); + +int32_t lis2dh12_fifo_data_level_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_fifo_empty_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_fifo_ovr_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_fifo_fth_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_tap_conf_set(lis2dh12_ctx_t *ctx, lis2dh12_click_cfg_t *val); +int32_t lis2dh12_tap_conf_get(lis2dh12_ctx_t *ctx, lis2dh12_click_cfg_t *val); + +int32_t lis2dh12_tap_source_get(lis2dh12_ctx_t *ctx, + lis2dh12_click_src_t *val); + +int32_t lis2dh12_tap_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_tap_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_TAP_PULSED = 0, + LIS2DH12_TAP_LATCHED = 1, +} lis2dh12_lir_click_t; +int32_t lis2dh12_tap_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_click_t val); +int32_t lis2dh12_tap_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_click_t *val); + +int32_t lis2dh12_shock_dur_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_shock_dur_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_quiet_dur_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_quiet_dur_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_double_tap_timeout_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_double_tap_timeout_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_act_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_act_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_act_timeout_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_act_timeout_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_PULL_UP_DISCONNECT = 0, + LIS2DH12_PULL_UP_CONNECT = 1, +} lis2dh12_sdo_pu_disc_t; +int32_t lis2dh12_pin_sdo_sa0_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_sdo_pu_disc_t val); +int32_t lis2dh12_pin_sdo_sa0_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_sdo_pu_disc_t *val); + +typedef enum { + LIS2DH12_SPI_4_WIRE = 0, + LIS2DH12_SPI_3_WIRE = 1, +} lis2dh12_sim_t; +int32_t lis2dh12_spi_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_sim_t val); +int32_t lis2dh12_spi_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_sim_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIS2DH12_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h new file mode 100644 index 0000000..4246531 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h @@ -0,0 +1,117 @@ +/* +Copyright (c) 2019 SparkFun Electronics + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. +*/ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D0 = 25, + D1 = 24, + D2 = 35, + D3 = 4, + D4 = 22, + D5 = 23, + D6 = 27, + D7 = 28, + D8 = 32, + D9 = 12, + D10 = 13, + D11 = 7, + D12 = 6, + D13 = 5, + D14 = 40, + D15 = 39, + D16 = 29, + D17 = 11, + D18 = 34, + D19 = 33, + D20 = 16, + D21 = 31, + + // Analog naming + A0 = D16, + A1 = D17, + A2 = D18, + A3 = D19, + A4 = D20, + A5 = D21, + A6 = D2, + // A7 = ?? + A8 = D8, + A9 = D9, + A10 = D10, + + // LEDs + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = A5, + + // LED naming by digital pin number + LED13 = AM_BSP_GPIO_LED13, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + SERIAL1_TX = D1, + SERIAL1_RX = D0, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.c new file mode 100644 index 0000000..50dd4ab --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.c @@ -0,0 +1,1063 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.h new file mode 100644 index 0000000..a1346b9 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.h @@ -0,0 +1,254 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 0 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 4 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED13 AM_BSP_GPIO_LED_BLUE + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The RedBoard Artemis PWM LED is pad 5 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 2 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERA +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERA2C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.c new file mode 100644 index 0000000..291e05e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.c @@ -0,0 +1,861 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 13. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_5_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.h new file mode 100644 index 0000000..a68be45 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.h @@ -0,0 +1,584 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 13. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 36 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h new file mode 100644 index 0000000..073a6ae --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D0 = 0, + D1 = 1, + D2 = 2, + D3 = 3, + D4 = 4, + D5 = 5, + D6 = 6, + D7 = 7, + D8 = 8, + D9 = 9, + D10 = 10, + D11 = 11, + D12 = 12, + D13 = 13, + D14 = 14, + D15 = 15, + D16 = 16, + D17 = 17, + D18 = 18, + D19 = 19, + // D20 = ?? + // D21 = ?? + D22 = 22, + D23 = 23, + D24 = 24, + D25 = 25, + D26 = 26, + D27 = 27, + D28 = 28, + D29 = 29, + // D30 = ?? + D31 = 31, + D32 = 32, + D33 = 33, + D34 = 34, + D35 = 35, + D36 = 36, + D37 = 37, + D38 = 38, + D39 = 39, + D40 = 40, + D41 = 41, + D42 = 42, + D43 = 43, + D44 = 44, + D45 = 45, + + // Analog naming + A11 = D11, + A12 = D12, + A13 = D13, + A16 = D16, + A29 = D29, + A31 = D31, + A32 = D32, + A33 = D33, + A34 = D34, + A35 = D35, + + // LEDs + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = D42, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + SERIAL1_TX = D24, + SERIAL1_RX = D25, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.c new file mode 100644 index 0000000..50dd4ab --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.c @@ -0,0 +1,1063 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.h new file mode 100644 index 0000000..0c1d8b6 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.h @@ -0,0 +1,255 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 0 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 4 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED37 AM_BSP_GPIO_LED_BLUE + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The ATP PWM LED is pad 5 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 2 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERA +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERA2C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.c new file mode 100644 index 0000000..0461c40 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.c @@ -0,0 +1,861 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_5_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.h new file mode 100644 index 0000000..d7d63c3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.h @@ -0,0 +1,584 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 36 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h new file mode 100644 index 0000000..553cbb9 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D13 = 13, + D16 = 16, + D23 = 23, + D24 = 24, + D25 = 25, + D26 = 26, + D27 = 27, + D28 = 28, + D29 = 29, + // D30 = 30, ?? + D31 = 31, + D32 = 32, + D33 = 33, + D34 = 34, + D35 = 35, + D36 = 36, + D37 = 37, + D38 = 38, + D39 = 39, + D40 = 40, + D41 = 41, + D42 = 42, + D43 = 43, + D44 = 44, + D45 = 45, + + // Analog naming + A13 = D13, + A16 = D16, + A29 = D29, + A31 = D31, + A32 = D32, + A33 = D33, + A34 = D34, + A35 = D35, + + // LEDs + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = D24, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // Accelerometer + ACC_SCL = QWIIC_SCL, + ACC_SDA = QWIIC_SDA, + + // Camera + CAM_SCL = QWIIC_SCL, + CAM_SDA = QWIIC_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.c new file mode 100644 index 0000000..50dd4ab --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.c @@ -0,0 +1,1063 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.h new file mode 100644 index 0000000..b423be0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.h @@ -0,0 +1,294 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +// artmbed hardware version: v01 (there will need to be changes when migrating to v02 or v10) + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Camera +// +//***************************************************************************** +#define AM_BSP_CAMERA_HM01B0_MCLK_PIN 18 +#define AM_BSP_CAMERA_HM01B0_I2C_IOM 1 +#define AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA +#define AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL +#define g_AM_BSP_CAMERA_HM01B0_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA +#define g_AM_BSP_CAMERA_HM01B0_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD 1 +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG AM_HAL_CTIMER_TIMERA + + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + +//***************************************************************************** +// +// Accelerometer. +// +//***************************************************************************** +#define AM_BSP_ACCELEROMETER_I2C_IOM 1 +#define AM_BSP_ACCELEROMETER_I2C_ADDRESS 0x19 +#define AM_BSP_ACCELEROMETER_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA +#define AM_BSP_ACCELEROMETER_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL +#define g_AM_BSP_ACCELEROMETER_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA +#define g_AM_BSP_ACCELEROMETER_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 4 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM4_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM4_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM4_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM4_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM4_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM4_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 1 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL + + +// //***************************************************************************** +// // +// // Button definitions. +// // +// //***************************************************************************** +// #define AM_BSP_NUM_BUTTONS 0 +// extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS]; + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED23 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED_STAT AM_BSP_GPIO_LED_BLUE + + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The ARTMBED LED0 is pad 23 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 3 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB3C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.c new file mode 100644 index 0000000..782e9ab --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.c @@ -0,0 +1,1017 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0 = +{ + .uFuncSel = AM_HAL_PIN_0_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1 = +{ + .uFuncSel = AM_HAL_PIN_1_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2 = +{ + .uFuncSel = AM_HAL_PIN_2_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3 = +{ + .uFuncSel = AM_HAL_PIN_3_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4 = +{ + .uFuncSel = AM_HAL_PIN_4_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5 = +{ + .uFuncSel = AM_HAL_PIN_5_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6 = +{ + .uFuncSel = AM_HAL_PIN_6_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7 = +{ + .uFuncSel = AM_HAL_PIN_7_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC = +{ + .uFuncSel = AM_HAL_PIN_15_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC = +{ + .uFuncSel = AM_HAL_PIN_17_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK = +{ + .uFuncSel = AM_HAL_PIN_19_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG = +{ + .uFuncSel = AM_HAL_PIN_14_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT = +{ + .uFuncSel = AM_HAL_PIN_10_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_11_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_12_PDMCLK +}; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labeled STAT. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_23_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_22_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.h new file mode 100644 index 0000000..712c70b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.h @@ -0,0 +1,688 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D0 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D1 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D2 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D3 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D4 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D5 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D6 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D7 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_VSYNC 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_HSYNC 17 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_PCLK 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_TRIG 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_INT 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labeled STAT. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h new file mode 100644 index 0000000..05ef59d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D0 = 0, + D1 = 1, + D2 = 2, + D3 = 3, + D4 = 4, + D5 = 5, + D6 = 6, + D7 = 7, + D8 = 8, + D9 = 9 + D10 = 10, + D11 = 11, + D12 = 12, + D13 = 13, + D14 = 14, + D15 = 15, + D16 = 16, + D17 = 17, + D18 = 18, + D19 = 19, + D20 = 20, + D21 = 21, + D22 = 22, + D23 = 23, + D24 = 24, + D25 = 25, + D26 = 26, + D27 = 27, + D28 = 28, + D29 = 29, + // D30 = NC + D31 = 31, + D32 = 32, + D33 = 33, + D34 = 34, + D35 = 35, + D36 = 36, + D37 = 37, + D38 = 38, + D39 = 39, + D40 = 40, + D41 = 41, + D42 = 42, + D43 = 43, + D44 = 44, + D45 = 45, + + // Analog naming + A11 = D11, + A12 = D12, + A13 = D13, + A16 = D16, + A29 = D29, + A31 = D31, + A32 = D32, + A33 = D33, + A34 = D34, + A35 = D35, + + // Not connected + NC = NC_VAL +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.c new file mode 100644 index 0000000..f1586a4 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.c @@ -0,0 +1,1026 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = {0}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.h new file mode 100644 index 0000000..b7c8952 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.h @@ -0,0 +1,186 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#undef AM_BSP_NUM_LEDS +#ifdef AM_BSP_NUM_LEDS +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; +#endif // AM_BSP_NUM_LEDS + + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.c new file mode 100644 index 0000000..f2533e8 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.c @@ -0,0 +1,819 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.h new file mode 100644 index 0000000..ab71bdd --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.h @@ -0,0 +1,552 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h new file mode 100644 index 0000000..dcb283d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D0 = 13, + D1 = 33, + D2 = 11, + D3 = 29, + D4 = 18, + D5 = 31, + D6 = 43, + D7 = 42, + D8 = 38, + D9 = 39, + D10 = 40, + D11 = 5, + D12 = 7, + D13 = 6, + D14 = 35, + D15 = 32, + D16 = 12, + + // Analog naming + A0 = D0, + A1 = D1, + A2 = D2, + A3 = D3, + A5 = D5, + A14 = D14, + A15 = D15, + A16 = D16, + + // LEDs + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = D8, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + I2C1_SCL = AM_BSP_GPIO_IOM3_SCL, + I2C1_SDA = AM_BSP_GPIO_IOM3_SDA, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + SERIAL1_TX = D9, + SERIAL1_RX = D10, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.c new file mode 100644 index 0000000..50dd4ab --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.c @@ -0,0 +1,1063 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.h new file mode 100644 index 0000000..4c1a0ae --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.h @@ -0,0 +1,255 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 0 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 2 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM2_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM2_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM2_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM2_SCL + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED19 AM_BSP_GPIO_LED_BLUE + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The RedBoard Artemis Nano LED is pad 19 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 1 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB1C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.c new file mode 100644 index 0000000..b733343 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.c @@ -0,0 +1,861 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 19. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_19_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.h new file mode 100644 index 0000000..25284be --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.h @@ -0,0 +1,584 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 19. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 36 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h new file mode 100644 index 0000000..91a299b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D0 = 25, + D1 = 24, + D2 = 44, + D3 = 35, + D4 = 4, + D5 = 22, + D6 = 23, + D7 = 27, + D8 = 28, + D9 = 32, + D10 = 14, + D11 = 7, + D12 = 6, + D13 = 5, + D14 = 40, + D15 = 39, + D16 = 43, + D17 = 42, + D18 = 26, + D19 = 33, + D20 = 13, + D21 = 11, + D22 = 29, + D23 = 12, + D24 = 31, + + // Analog naming + A0 = D19, + A1 = D20, + A2 = D21, + A3 = D22, + A4 = D23, + A5 = D24, + A6 = D3, + + //BUTTONs + SW1 = AM_BSP_GPIO_BUTTON0, + + // LEDs + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = D2, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + SERIAL1_TX = D1, + SERIAL1_RX = D0, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.c new file mode 100644 index 0000000..50dd4ab --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.c @@ -0,0 +1,1063 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.h new file mode 100644 index 0000000..36c8593 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.h @@ -0,0 +1,267 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 0 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 4 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL + + +//***************************************************************************** +// +// Button definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_BUTTONS 1 +extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS]; + +#define AM_BSP_GPIO_BUTTON10 AM_BSP_GPIO_BUTTON0 +#define AM_BSP_GPIO_SWCH AM_BSP_GPIO_BUTTON0 + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED18 AM_BSP_GPIO_LED_BLUE + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The Artemis Thing Plus PWM LED is pad 26 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 0 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB0C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.c new file mode 100644 index 0000000..470fe84 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.c @@ -0,0 +1,874 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 18. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_26_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// BUTTON0 pin: Labeled 10 on the Artemis Thing Plus. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON0 = +{ + .uFuncSel = AM_HAL_PIN_14_GPIO, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.h new file mode 100644 index 0000000..b7d4b0f --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.h @@ -0,0 +1,592 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 36 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 18. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// BUTTON0 pin: Labeled 10 on the Artemis Thing Plus. +// +//***************************************************************************** +#define AM_BSP_GPIO_BUTTON0 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON0; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/PinNames.h new file mode 100644 index 0000000..fe674b0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/PinNames.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D1 = 1, + D38 = 38, + D36 = 36, + D3 = 3, + + // // Analog naming + // No analog pins + + // mbed buttons + BUTTON1 = AM_BSP_GPIO_BUTTON0, + + // LEDs + LED_RED = AM_BSP_GPIO_LED_RED, + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + LED_GREEN = AM_BSP_GPIO_LED_GREEN, + LED_YELLOW = AM_BSP_GPIO_LED_YELLOW, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = AM_BSP_GPIO_LED1, + LED3 = AM_BSP_GPIO_LED2, + LED4 = AM_BSP_GPIO_LED3, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + // The SFE_EDGE does not expose a complete IOM peripheral for SPI + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.c new file mode 100644 index 0000000..75f7aad --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.c @@ -0,0 +1,1066 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED1, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED2, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED3, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M} +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.h new file mode 100644 index 0000000..1aa2bc5 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.h @@ -0,0 +1,290 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Camera +// +//***************************************************************************** +#define AM_BSP_CAMERA_HM01B0_MCLK_PIN 13 +#define AM_BSP_CAMERA_HM01B0_I2C_IOM 1 +#define AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA +#define AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL +#define g_AM_BSP_CAMERA_HM01B0_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA +#define g_AM_BSP_CAMERA_HM01B0_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD 0 +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG AM_HAL_CTIMER_TIMERB + +//***************************************************************************** +// +// Accelerometer. +// +//***************************************************************************** +#define AM_BSP_ACCELEROMETER_I2C_IOM 3 +#define AM_BSP_ACCELEROMETER_I2C_ADDRESS 0x19 +#define AM_BSP_ACCELEROMETER_I2C_SDA_PIN AM_BSP_GPIO_IOM3_SDA +#define AM_BSP_ACCELEROMETER_I2C_SCL_PIN AM_BSP_GPIO_IOM3_SCL +#define g_AM_BSP_ACCELEROMETER_I2C_SCL g_AM_BSP_GPIO_IOM3_SCL +#define g_AM_BSP_ACCELEROMETER_I2C_SDA g_AM_BSP_GPIO_IOM3_SDA +#define AM_BSP_ACCELEROMETER_INT1_PIN 17 +#define AM_BSP_ACCELEROMETER_INT2_PIN 0 + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +// The SparkFun Edge does not have a complete IOMaster broken out + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 4 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL + + +//***************************************************************************** +// +// Button definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_BUTTONS 1 +extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS]; + +#define AM_BSP_GPIO_BUTTON0 AM_BSP_GPIO_BUTTON14 + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 4 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED1 1 +#define AM_BSP_LED2 2 +#define AM_BSP_LED3 3 + +#define AM_BSP_LED_RED AM_BSP_LED0 +#define AM_BSP_LED_BLUE AM_BSP_LED1 +#define AM_BSP_LED_GREEN AM_BSP_LED2 +#define AM_BSP_LED_YELLOW AM_BSP_LED3 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_RED +#define AM_BSP_GPIO_LED1 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED2 AM_BSP_GPIO_LED_GREEN +#define AM_BSP_GPIO_LED3 AM_BSP_GPIO_LED_YELLOW + +#define AM_BSP_GPIO_LED46 AM_BSP_GPIO_LED_RED +#define AM_BSP_GPIO_LED37 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED44 AM_BSP_GPIO_LED_GREEN +#define AM_BSP_GPIO_LED47 AM_BSP_GPIO_LED_YELLOW + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The Edge LED0 is pin 46 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 6 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERA +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERA6C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.c new file mode 100644 index 0000000..fc0d917 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.c @@ -0,0 +1,1073 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0 = +{ + .uFuncSel = AM_HAL_PIN_24_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1 = +{ + .uFuncSel = AM_HAL_PIN_25_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2 = +{ + .uFuncSel = AM_HAL_PIN_26_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3 = +{ + .uFuncSel = AM_HAL_PIN_27_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4 = +{ + .uFuncSel = AM_HAL_PIN_28_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5 = +{ + .uFuncSel = AM_HAL_PIN_5_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6 = +{ + .uFuncSel = AM_HAL_PIN_6_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7 = +{ + .uFuncSel = AM_HAL_PIN_7_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC = +{ + .uFuncSel = AM_HAL_PIN_15_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC = +{ + .uFuncSel = AM_HAL_PIN_22_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK = +{ + .uFuncSel = AM_HAL_PIN_23_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG = +{ + .uFuncSel = AM_HAL_PIN_12_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT = +{ + .uFuncSel = AM_HAL_PIN_4_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_DVDDEN pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN = +{ + .uFuncSel = AM_HAL_PIN_10_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// MIC0 pin: Analog microphone near camera connector. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC0 = +{ + .uFuncSel = AM_HAL_PIN_11_ADCSE2 +}; + +//***************************************************************************** +// +// MIC1 pin: Analog microphone near LEDs. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC1 = +{ + .uFuncSel = AM_HAL_PIN_29_ADCSE1 +}; + +//***************************************************************************** +// +// BUTTON14 pin: Labeled 14 on the SparkFun Edge. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON14 = +{ + .uFuncSel = AM_HAL_PIN_14_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// LED_RED pin: The RED LED labelled 46. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_RED = +{ + .uFuncSel = AM_HAL_PIN_46_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 37. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_37_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_GREEN pin: The GREEN LED labelled 44. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_GREEN = +{ + .uFuncSel = AM_HAL_PIN_44_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_YELLOW pin: The YELLOW LED labelled 47. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_YELLOW = +{ + .uFuncSel = AM_HAL_PIN_47_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.h new file mode 100644 index 0000000..4245ffe --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.h @@ -0,0 +1,728 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D0 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D1 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D2 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D3 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D4 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D5 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D6 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D7 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_VSYNC 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_HSYNC 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_PCLK 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_TRIG 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_INT 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT; + +//***************************************************************************** +// +// CAMERA_HM01B0_DVDDEN pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN; + +//***************************************************************************** +// +// MIC0 pin: Analog microphone near camera connector. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC0 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC0; + +//***************************************************************************** +// +// MIC1 pin: Analog microphone near LEDs. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC1 29 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC1; + +//***************************************************************************** +// +// BUTTON14 pin: Labeled 14 on the SparkFun Edge. +// +//***************************************************************************** +#define AM_BSP_GPIO_BUTTON14 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON14; + +//***************************************************************************** +// +// LED_RED pin: The RED LED labelled 46. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_RED 46 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_RED; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 37. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// LED_GREEN pin: The GREEN LED labelled 44. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_GREEN 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_GREEN; + +//***************************************************************************** +// +// LED_YELLOW pin: The YELLOW LED labelled 47. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_YELLOW 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_YELLOW; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/PinNames.h new file mode 100644 index 0000000..d6f6656 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/PinNames.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D16 = 16, + D31 = 31, + D45 = 45, + D44 = 44, + + // Analog naming + A16 = D16, + A31 = D31, + + // LEDs + LED_RED = AM_BSP_GPIO_LED_RED, + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + LED_GREEN = AM_BSP_GPIO_LED_GREEN, + LED_YELLOW = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = AM_BSP_GPIO_LED1, + LED3 = AM_BSP_GPIO_LED2, + LED4 = AM_BSP_GPIO_LED3, + + // LED naming by digital pin number + LED19 = AM_BSP_GPIO_LED19, + LED18 = AM_BSP_GPIO_LED18, + LED17 = AM_BSP_GPIO_LED17, + LED37 = AM_BSP_GPIO_LED37, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.c new file mode 100644 index 0000000..75f7aad --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.c @@ -0,0 +1,1066 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED1, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED2, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED3, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M} +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.h new file mode 100644 index 0000000..b1f646f --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.h @@ -0,0 +1,302 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Camera +// +//***************************************************************************** +#define AM_BSP_CAMERA_HM01B0_MCLK_PIN 26 +#define AM_BSP_CAMERA_HM01B0_I2C_IOM 1 +#define AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA +#define AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD 0 +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG AM_HAL_CTIMER_TIMERB + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + +//***************************************************************************** +// +// Accelerometer. +// +//***************************************************************************** +#define AM_BSP_ACCELEROMETER_I2C_IOM 3 +#define AM_BSP_ACCELEROMETER_I2C_ADDRESS 0x19 +#define AM_BSP_ACCELEROMETER_I2C_SDA_PIN AM_BSP_GPIO_IOM3_SDA +#define AM_BSP_ACCELEROMETER_I2C_SCL_PIN AM_BSP_GPIO_IOM3_SCL +#define g_AM_BSP_ACCELEROMETER_I2C_SDA g_AM_BSP_GPIO_IOM3_SDA +#define g_AM_BSP_ACCELEROMETER_I2C_SCL g_AM_BSP_GPIO_IOM3_SCL + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +// Note: Edge2 can use SPI via the Qwiic connector and GPIO 44 +#define AM_BSP_PRIM_SPI_IOM 4 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM4_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM4_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM4_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM4_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM4_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM4_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 4 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL + + +// //***************************************************************************** +// // +// // Button definitions. +// // +// //***************************************************************************** +// #define AM_BSP_NUM_BUTTONS 0 +// extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS]; + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 4 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED1 1 +#define AM_BSP_LED2 2 +#define AM_BSP_LED3 3 + +#define AM_BSP_LED_RED AM_BSP_LED0 +#define AM_BSP_LED_BLUE AM_BSP_LED1 +#define AM_BSP_LED_GREEN AM_BSP_LED2 +#define AM_BSP_LED_YELLOW AM_BSP_LED3 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_RED +#define AM_BSP_GPIO_LED1 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED2 AM_BSP_GPIO_LED_GREEN +#define AM_BSP_GPIO_LED3 AM_BSP_GPIO_LED_YELLOW + +#define AM_BSP_GPIO_LED19 AM_BSP_GPIO_LED_RED +#define AM_BSP_GPIO_LED18 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED17 AM_BSP_GPIO_LED_GREEN +#define AM_BSP_GPIO_LED37 AM_BSP_GPIO_LED_YELLOW + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The Edge2 LED0 is pin 19 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 1 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB1C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.c new file mode 100644 index 0000000..b657a7e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.c @@ -0,0 +1,1061 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0 = +{ + .uFuncSel = AM_HAL_PIN_14_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1 = +{ + .uFuncSel = AM_HAL_PIN_11_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2 = +{ + .uFuncSel = AM_HAL_PIN_25_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3 = +{ + .uFuncSel = AM_HAL_PIN_34_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4 = +{ + .uFuncSel = AM_HAL_PIN_6_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5 = +{ + .uFuncSel = AM_HAL_PIN_5_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6 = +{ + .uFuncSel = AM_HAL_PIN_35_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7 = +{ + .uFuncSel = AM_HAL_PIN_28_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC = +{ + .uFuncSel = AM_HAL_PIN_15_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC = +{ + .uFuncSel = AM_HAL_PIN_27_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK = +{ + .uFuncSel = AM_HAL_PIN_7_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG = +{ + .uFuncSel = AM_HAL_PIN_13_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT = +{ + .uFuncSel = AM_HAL_PIN_23_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_DVDDEN pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN = +{ + .uFuncSel = AM_HAL_PIN_32_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_29_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_12_PDMCLK +}; + +//***************************************************************************** +// +// LED_RED pin: The RED LED labelled 19. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_RED = +{ + .uFuncSel = AM_HAL_PIN_19_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 18. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_18_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_GREEN pin: The GREEN LED labelled 17. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_GREEN = +{ + .uFuncSel = AM_HAL_PIN_17_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_YELLOW pin: The YELLOW LED labelled 37. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_YELLOW = +{ + .uFuncSel = AM_HAL_PIN_37_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.h new file mode 100644 index 0000000..23b3ea3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.h @@ -0,0 +1,720 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D0 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D1 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D2 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D3 34 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D4 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D5 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D6 35 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D7 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_VSYNC 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_HSYNC 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_PCLK 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_TRIG 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_INT 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT; + +//***************************************************************************** +// +// CAMERA_HM01B0_DVDDEN pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN 32 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 29 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// LED_RED pin: The RED LED labelled 19. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_RED 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_RED; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 18. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 18 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// LED_GREEN pin: The GREEN LED labelled 17. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_GREEN 17 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_GREEN; + +//***************************************************************************** +// +// LED_YELLOW pin: The YELLOW LED labelled 37. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_YELLOW 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_YELLOW; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/AMA3B1KK.sct b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/AMA3B1KK.sct new file mode 100644 index 0000000..2ae3499 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/AMA3B1KK.sct @@ -0,0 +1,55 @@ +#! armcc -E + +; +; Copyright (c) 2019-2020 SparkFun Electronics +; SPDX-License-Identifier: MIT +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), to deal +; in the Software without restriction, including without limitation the rights +; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +; copies of the Software, and to permit persons to whom the Software is +; furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included in +; all copies or substantial portions of the Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +; SOFTWARE. +; + + +#define MBED_APP_START 0x0000C000 +#define MBED_APP_SIZE 0x000F4000 +#define MBED_RAM_START 0x10000000 +#define MBED_RAM_SIZE 0x60000 +#define MBED_RAM0_START MBED_RAM_START +#define MBED_RAM0_SIZE 0x100 +#define MBED_RAM1_START (MBED_RAM0_START + MBED_RAM0_SIZE) +#define MBED_RAM1_SIZE (MBED_RAM_SIZE - (MBED_RAM0_SIZE)) +#define Stack_Size MBED_BOOT_STACK_SIZE +#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+MBED_RAM0_SIZE) + + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM0 MBED_RAM0_START UNINIT MBED_RAM0_SIZE { ;no init section + *(*nvictable) + } + RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { + .ANY (+RW +ZI) + } + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { + } + ARM_LIB_STACK MBED_RAM1_START+MBED_RAM1_SIZE-8 EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/startup_keil.S b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/startup_keil.S new file mode 100644 index 0000000..ccfea3a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/startup_keil.S @@ -0,0 +1,345 @@ +;****************************************************************************** +; +;! @file startup_keil.s +;! +;! @brief Definitions for Apollo3 interrupt handlers, the vector table, and the stack. +; +;****************************************************************************** + +;****************************************************************************** +; +; Copyright (c) 2020, Ambiq Micro +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; Third party software included in this distribution is subject to the +; additional license terms as defined in the /docs/licenses directory. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +; This is part of revision 2.4.2 of the AmbiqSuite Development Package. +; +;****************************************************************************** +; SPDX-License-Identifier: BSD-3-Clause + + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** +; +; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and +; am_usagefault_isr does not work if am_fault_isr is defined externally. +; Therefore, we'll explicitly use am_fault_isr in the table for those vectors. +; + + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; The MPU fault handler + DCD BusFault_Handler ; The bus fault handler + DCD UsageFault_Handler ; The usage fault handler + DCD SecureFault_Handler ; Secure fault handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall handler + DCD DebugMon_Handler ; Debug monitor handler + DCD 0 ; Reserved + DCD PendSV_Handler ; The PendSV handler + DCD SysTick_Handler ; The SysTick handler + + ; + ; Peripheral Interrupts + ; + DCD am_brownout_isr ; 0: Reserved + DCD am_watchdog_isr ; 1: Reserved + DCD am_rtc_isr ; 2: RTC + DCD am_vcomp_isr ; 3: Voltage Comparator + DCD am_ioslave_ios_isr ; 4: I/O Slave general + DCD am_ioslave_acc_isr ; 5: I/O Slave access + DCD am_iomaster0_isr ; 6: I/O Master 0 + DCD am_iomaster1_isr ; 7: I/O Master 1 + DCD am_iomaster2_isr ; 8: I/O Master 2 + DCD am_iomaster3_isr ; 9: I/O Master 3 + DCD am_iomaster4_isr ; 10: I/O Master 4 + DCD am_iomaster5_isr ; 11: I/O Master 5 + DCD HciDrvIntService ; 12: BLEIF + DCD am_gpio_isr ; 13: GPIO + DCD am_ctimer_isr ; 14: CTIMER + DCD am_uart_isr ; 15: UART0 + DCD am_uart1_isr ; 16: UART1 + DCD am_scard_isr ; 17: SCARD + DCD am_adc_isr ; 18: ADC + DCD am_pdm0_isr ; 19: PDM + DCD am_mspi0_isr ; 20: MSPI0 + DCD am_software0_isr ; 21: SOFTWARE0 + DCD am_stimer_isr ; 22: SYSTEM TIMER + DCD am_stimer_cmpr0_isr ; 23: SYSTEM TIMER COMPARE0 + DCD am_stimer_cmpr1_isr ; 24: SYSTEM TIMER COMPARE1 + DCD am_stimer_cmpr2_isr ; 25: SYSTEM TIMER COMPARE2 + DCD am_stimer_cmpr3_isr ; 26: SYSTEM TIMER COMPARE3 + DCD am_stimer_cmpr4_isr ; 27: SYSTEM TIMER COMPARE4 + DCD am_stimer_cmpr5_isr ; 28: SYSTEM TIMER COMPARE5 + DCD am_stimer_cmpr6_isr ; 29: SYSTEM TIMER COMPARE6 + DCD am_stimer_cmpr7_isr ; 30: SYSTEM TIMER COMPARE7 + DCD am_clkgen_isr ; 31: CLKGEN + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +;****************************************************************************** +; +; Place code immediately following vector table. +; +;****************************************************************************** +;****************************************************************************** +; +; The Patch table. +; +; The patch table should pad the vector table size to a total of 64 entries +; (16 core + 48 periph) such that code begins at offset 0x100. +; +;****************************************************************************** + EXPORT __Patchable +__Patchable + DCD 0 ; 32 + DCD 0 ; 33 + DCD 0 ; 34 + DCD 0 ; 35 + DCD 0 ; 36 + DCD 0 ; 37 + DCD 0 ; 38 + DCD 0 ; 39 + DCD 0 ; 40 + DCD 0 ; 41 + DCD 0 ; 42 + DCD 0 ; 43 + DCD 0 ; 44 + DCD 0 ; 45 + DCD 0 ; 46 + DCD 0 ; 47 + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; + ; Enable the FPU. + ; + MOVW R0, #0xED88 + MOVT R0, #0xE000 + LDR R1, [R0] + ORR R1, #0x00F00000 + STR R1, [R0] + DSB + ISB + + ; + ; Branch to main. + ; + LDR R0, =__main + BX R0 + + ENDP + +;****************************************************************************** +; +; Weak Exception Handlers. +; +;****************************************************************************** + +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SecureFault_Handler\ + PROC + EXPORT SecureFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +am_default_isr\ + PROC + EXPORT am_brownout_isr [WEAK] + EXPORT am_watchdog_isr [WEAK] + EXPORT am_rtc_isr [WEAK] + EXPORT am_vcomp_isr [WEAK] + EXPORT am_ioslave_ios_isr [WEAK] + EXPORT am_ioslave_acc_isr [WEAK] + EXPORT am_iomaster0_isr [WEAK] + EXPORT am_iomaster1_isr [WEAK] + EXPORT am_iomaster2_isr [WEAK] + EXPORT am_iomaster3_isr [WEAK] + EXPORT am_iomaster4_isr [WEAK] + EXPORT am_iomaster5_isr [WEAK] + EXPORT HciDrvIntService [WEAK] + EXPORT am_gpio_isr [WEAK] + EXPORT am_ctimer_isr [WEAK] + EXPORT am_uart_isr [WEAK] + EXPORT am_uart0_isr [WEAK] + EXPORT am_uart1_isr [WEAK] + EXPORT am_scard_isr [WEAK] + EXPORT am_adc_isr [WEAK] + EXPORT am_pdm0_isr [WEAK] + EXPORT am_mspi0_isr [WEAK] + EXPORT am_software0_isr [WEAK] + EXPORT am_stimer_isr [WEAK] + EXPORT am_stimer_cmpr0_isr [WEAK] + EXPORT am_stimer_cmpr1_isr [WEAK] + EXPORT am_stimer_cmpr2_isr [WEAK] + EXPORT am_stimer_cmpr3_isr [WEAK] + EXPORT am_stimer_cmpr4_isr [WEAK] + EXPORT am_stimer_cmpr5_isr [WEAK] + EXPORT am_stimer_cmpr6_isr [WEAK] + EXPORT am_stimer_cmpr7_isr [WEAK] + EXPORT am_clkgen_isr [WEAK] + +am_brownout_isr +am_watchdog_isr +am_rtc_isr +am_vcomp_isr +am_ioslave_ios_isr +am_ioslave_acc_isr +am_iomaster0_isr +am_iomaster1_isr +am_iomaster2_isr +am_iomaster3_isr +am_iomaster4_isr +am_iomaster5_isr +HciDrvIntService +am_gpio_isr +am_ctimer_isr +am_uart_isr +am_uart0_isr +am_uart1_isr +am_scard_isr +am_adc_isr +am_pdm0_isr +am_mspi0_isr +am_software0_isr +am_stimer_isr +am_stimer_cmpr0_isr +am_stimer_cmpr1_isr +am_stimer_cmpr2_isr +am_stimer_cmpr3_isr +am_stimer_cmpr4_isr +am_stimer_cmpr5_isr +am_stimer_cmpr6_isr +am_stimer_cmpr7_isr +am_clkgen_isr + + ; all device interrupts go here unless the weak label is over + ; ridden in the linker hard spin so the debugger will know it + ; was an unhandled interrupt request a come-from-buffer or + ; instruction trace hardware would sure be nice if you get here + B . + + ENDP + + + +;****************************************************************************** +; +; Align the end of the section. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; All Done +; +;****************************************************************************** + END + + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/AMA3B1KK.ld b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/AMA3B1KK.ld new file mode 100644 index 0000000..8445c55 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/AMA3B1KK.ld @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +/* stack: dynamic */ +/* heap: dynamic */ +#define MBED_APP_START 0x0000C000 +#define MBED_APP_LENGTH 0x000F4000 +#define MBED_RAM_START 0x10000000 +#define MBED_RAM_SIZE 384K +#define MBED_BOOT_STACK_SIZE 0x400 +#define MBED_RAM0_START MBED_RAM_START +#define MBED_RAM0_SIZE 0x100 +#define MBED_RAM1_START (MBED_RAM0_START + MBED_RAM0_SIZE) +#define MBED_RAM1_SIZE (MBED_RAM_SIZE - (MBED_RAM0_SIZE)) + +ENTRY(Reset_Handler) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_LENGTH /*Modified from 0xC000 to work with SparkFun SVL*/ + RAM_NVIC (rwx) : ORIGIN = MBED_RAM0_START, LENGTH = MBED_RAM0_SIZE + RAM (rwx) : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE +} + +SECTIONS +{ + /* text: executable code */ + /* located in _flash_ */ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) + KEEP(*(.ble_patch)) + *(.text) + *(.text*) + +/* __init_array_start = .; + KEEP(*(.init_array*)) + __init_array_end = .; */ /* does this mess up _init()?' it was from Arduinoland (aka owen) */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* .rodata */ + . = ALIGN(4); + *(.rodata) + *(.rodata*) + + KEEP(*(.eh_frame*)) + + . = ALIGN(4); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = ALIGN(8); + + .data : AT (__etext) + { + __data_start__ = .; + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + + /* bss: zero-initialized symbols */ + /* don't require flash memory to remember their value */ + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(8); + _ebss = .; + __bss_end__ = .; + } > RAM + + /* heap: RAM memory that can be dynamically allocated in the upward direction (increasing memory addresses) */ + /* _sheap is used to identify the beginning of available dynamic memory */ + .heap (NOLOAD): + { + . = ALIGN(4); + __end__ = .; + PROVIDE( end = . ); + _sheap = .; + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE-8; + __HeapLimit = .; + } >RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later*/ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + *(.stack*) + } > RAM + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section*/ + __StackTop = ORIGIN(RAM) + LENGTH(RAM)-8; + __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + PROVIDE(_sstack = __StackTop); + /* Check if data + heap + stack exceeds RAM limit*/ + /*ASSERT(1, "region RAM overflowed with stack")*/ + /* test test test */ +} \ No newline at end of file diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/startup_gcc.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/startup_gcc.c new file mode 100644 index 0000000..8e6da12 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/startup_gcc.c @@ -0,0 +1,347 @@ +//***************************************************************************** +// +//! @file startup_gcc.c +//! +//! @brief Definitions for interrupt handlers, the vector table, and the stack. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "apollo3.h" +#include + +//***************************************************************************** +// +// Forward declaration of interrupt handlers. +// +//***************************************************************************** +extern void Reset_Handler(void) __attribute((naked)); +extern void NMI_Handler(void) __attribute((weak)); +extern void HardFault_Handler(void) __attribute((weak)); +extern void MemManage_Handler(void) __attribute((weak, alias("HardFault_Handler"))); +extern void BusFault_Handler(void) __attribute((weak, alias("HardFault_Handler"))); +extern void UsageFault_Handler(void) __attribute((weak, alias("HardFault_Handler"))); +extern void SecureFault_Handler(void) __attribute((weak)); +extern void SVC_Handler(void) __attribute((weak, alias("am_default_isr"))); +extern void DebugMon_Handler(void) __attribute((weak, alias("am_default_isr"))); +extern void PendSV_Handler(void) __attribute((weak, alias("am_default_isr"))); +extern void SysTick_Handler(void) __attribute((weak, alias("am_default_isr"))); + +extern void am_brownout_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_watchdog_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_rtc_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_vcomp_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_ioslave_ios_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_ioslave_acc_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster0_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster1_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster2_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster3_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster4_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster5_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void HciDrvIntService(void); //__attribute((weak, alias("am_default_isr"))); +extern void am_gpio_isr(void); //__attribute((weak, alias("am_default_isr"))); +extern void am_ctimer_isr(void); //__attribute((weak, alias("am_default_isr"))); +extern void am_uart_isr(void); //__attribute((weak, alias("am_default_isr"))); +extern void am_uart1_isr(void); //__attribute((weak, alias("am_default_isr"))); +extern void am_scard_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_adc_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_pdm0_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_mspi0_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_software0_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr0_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr1_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr2_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr3_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr4_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr5_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr6_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr7_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_clkgen_isr(void) __attribute((weak, alias("am_default_isr"))); + +extern void am_default_isr(void) __attribute((weak)); + +// // Entry Point for mbed boot sequence +// extern void __main(void); +// extern void _start(void); +extern void mbed_init(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +// '__stack' accesses the linker-provided address for the start of the stack +// (which is a high address - stack goes top to bottom) +extern void *__stack; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and +// am_usagefault_isr does not work if am_fault_isr is defined externally. +// Therefore, we'll explicitly use am_fault_isr in the table for those vectors. +// +//***************************************************************************** +__attribute__((section(".isr_vector"))) void (*const g_am_pfnVectors[])(void) = + { + (void (*)(void))(&__stack), // The initial stack pointer (provided by linker script) + Reset_Handler, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + MemManage_Handler, // The MemManage_Handler + BusFault_Handler, // The BusFault_Handler + UsageFault_Handler, // The UsageFault_Handler + SecureFault_Handler, // The SecureFault_Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // + // Peripheral Interrupts + // + am_brownout_isr, // 0: Brownout (rstgen) + am_watchdog_isr, // 1: Watchdog + am_rtc_isr, // 2: RTC + am_vcomp_isr, // 3: Voltage Comparator + am_ioslave_ios_isr, // 4: I/O Slave general + am_ioslave_acc_isr, // 5: I/O Slave access + am_iomaster0_isr, // 6: I/O Master 0 + am_iomaster1_isr, // 7: I/O Master 1 + am_iomaster2_isr, // 8: I/O Master 2 + am_iomaster3_isr, // 9: I/O Master 3 + am_iomaster4_isr, // 10: I/O Master 4 + am_iomaster5_isr, // 11: I/O Master 5 + HciDrvIntService, // 12: BLEIF + am_gpio_isr, // 13: GPIO + am_ctimer_isr, // 14: CTIMER + am_uart_isr, // 15: UART0 + am_uart1_isr, // 16: UART1 + am_scard_isr, // 17: SCARD + am_adc_isr, // 18: ADC + am_pdm0_isr, // 19: PDM + am_mspi0_isr, // 20: MSPI0 + am_software0_isr, // 21: SOFTWARE0 + am_stimer_isr, // 22: SYSTEM TIMER + am_stimer_cmpr0_isr, // 23: SYSTEM TIMER COMPARE0 + am_stimer_cmpr1_isr, // 24: SYSTEM TIMER COMPARE1 + am_stimer_cmpr2_isr, // 25: SYSTEM TIMER COMPARE2 + am_stimer_cmpr3_isr, // 26: SYSTEM TIMER COMPARE3 + am_stimer_cmpr4_isr, // 27: SYSTEM TIMER COMPARE4 + am_stimer_cmpr5_isr, // 28: SYSTEM TIMER COMPARE5 + am_stimer_cmpr6_isr, // 29: SYSTEM TIMER COMPARE6 + am_stimer_cmpr7_isr, // 30: SYSTEM TIMER COMPARE7 + am_clkgen_isr, // 31: CLKGEN +}; + +//****************************************************************************** +// +// Place code immediately following vector table. +// +//****************************************************************************** +//****************************************************************************** +// +// The Patch table. +// +// The patch table should pad the vector table size to a total of 64 entries +// (16 core + 48 periph) such that code begins at offset 0x100. +// +//****************************************************************************** +__attribute__((section(".ble_patch"))) +uint32_t const __Patchable[] = + { + 0, // 32 + 0, // 33 + 0, // 34 + 0, // 35 + 0, // 36 + 0, // 37 + 0, // 38 + 0, // 39 + 0, // 40 + 0, // 41 + 0, // 42 + 0, // 43 + 0, // 44 + 0, // 45 + 0, // 46 + 0, // 47 +}; + +// //***************************************************************************** +// // +// // The following are constructs created by the linker, indicating where the +// // the "data" and "bss" segments reside in memory. The initializers for the +// // "data" segment resides immediately following the "text" segment. +// // +// //***************************************************************************** +// extern uint32_t _etext; +// extern uint32_t __data_start__; +// extern uint32_t __data_end__; +// extern uint32_t _sbss; +// extern uint32_t _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. +// +//***************************************************************************** +#if defined(__GNUC_STDC_INLINE__) +void Reset_Handler(void) +{ + // + // Set the vector table pointer. + // + __asm(" ldr r0, =0xE000ED08\n" + " ldr r1, =g_am_pfnVectors\n" + " str r1, [r0]"); + + // // + // // Set the stack pointer. + // // + __asm(" ldr sp, [r1]"); + +#ifndef NOFPU + // // + // // Enable the FPU. + // // + __asm("ldr r0, =0xE000ED88\n" + "ldr r1,[r0]\n" + "orr r1,#(0xF << 20)\n" + "str r1,[r0]\n" + "dsb\n" + "isb\n"); +#endif + + // // Start mbed boot sequence https://os.mbed.com/docs/mbed-os/v5.15/reference/bootstrap.html + // SystemInit(); + // _start(); + + // + // Copy the data segment initializers from flash to SRAM. + // + __asm(" ldr r0, =__etext\n" + " ldr r1, =__data_start__\n" + " ldr r2, =__data_end__\n" + "copy_loop:\n" + " cmp r1, r2\n" + " beq copy_end\n" + " ldr r3, [r0], #4\n" + " str r3, [r1], #4\n" + " b copy_loop\n" + "copy_end:\n"); + + // // + // // Zero fill the bss segment. + // // + __asm("LDR R0, =_start\n" + "BX R0\n"); + // + // If main returns then execute a break point instruction + // + __asm(" bkpt "); +} +#else +#error GNU STDC inline not supported. +#endif + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +void NMI_Handler(void) +{ + // + // Go into an infinite loop. + // + while (1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void HardFault_Handler(void) +{ + // + // Go into an infinite loop. + // + while (1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void am_default_isr(void) +{ + // + // Go into an infinite loop. + // + while (1) + { + } +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralNames.h new file mode 100644 index 0000000..4c3a534 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralNames.h @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// SPDX-License-Identifier: Apache-2.0 +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define STDIO_UART UART_0 + +typedef enum { + UART_0 = 0, + UART_1, + + UART_NUM, + UART_ANY +} UARTName; + +typedef enum { + IOM_0 = 0, + IOM_1, + IOM_2, + IOM_3, + IOM_4, + IOM_5, + + IOM_NUM, + IOM_ANY +} IOMName; + +typedef IOMName SPIName; +typedef IOMName I2CName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.c new file mode 100644 index 0000000..c1cfec5 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.c @@ -0,0 +1,2219 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// UART0_TX_1 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_1 = { + .uFuncSel = AM_HAL_PIN_1_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_7 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_7 = { + .uFuncSel = AM_HAL_PIN_7_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_16 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_16 = { + .uFuncSel = AM_HAL_PIN_16_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_20 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_20 = { + .uFuncSel = AM_HAL_PIN_20_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_22 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_22 = { + .uFuncSel = AM_HAL_PIN_22_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_26 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_26 = { + .uFuncSel = AM_HAL_PIN_26_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_28 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_28 = { + .uFuncSel = AM_HAL_PIN_28_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_30 pin: UART0 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_30 = { + .uFuncSel = AM_HAL_PIN_30_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_TX_39 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_39 = { + .uFuncSel = AM_HAL_PIN_39_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_41 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_41 = { + .uFuncSel = AM_HAL_PIN_41_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_44 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_44 = { + .uFuncSel = AM_HAL_PIN_44_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_48 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_48 = { + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_8 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_8 = { + .uFuncSel = AM_HAL_PIN_8_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_10 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_10 = { + .uFuncSel = AM_HAL_PIN_10_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_12 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_12 = { + .uFuncSel = AM_HAL_PIN_12_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_14 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_14 = { + .uFuncSel = AM_HAL_PIN_14_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_18 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_18 = { + .uFuncSel = AM_HAL_PIN_18_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_20 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_20 = { + .uFuncSel = AM_HAL_PIN_20_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_24 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_24 = { + .uFuncSel = AM_HAL_PIN_24_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_35 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_35 = { + .uFuncSel = AM_HAL_PIN_35_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_37 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_37 = { + .uFuncSel = AM_HAL_PIN_37_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_39 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_39 = { + .uFuncSel = AM_HAL_PIN_39_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_42 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_42 = { + .uFuncSel = AM_HAL_PIN_42_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_46 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_46 = { + .uFuncSel = AM_HAL_PIN_46_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_2 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_2 = { + .uFuncSel = AM_HAL_PIN_2_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_11 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_11 = { + .uFuncSel = AM_HAL_PIN_11_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_17 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_17 = { + .uFuncSel = AM_HAL_PIN_17_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_21 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_21 = { + .uFuncSel = AM_HAL_PIN_21_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_23 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_23 = { + .uFuncSel = AM_HAL_PIN_23_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_27 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_27 = { + .uFuncSel = AM_HAL_PIN_27_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_29 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_29 = { + .uFuncSel = AM_HAL_PIN_29_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_31 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_31 = { + .uFuncSel = AM_HAL_PIN_31_UART0RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_34 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_34 = { + .uFuncSel = AM_HAL_PIN_34_UART0RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_40 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_40 = { + .uFuncSel = AM_HAL_PIN_40_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_45 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_45 = { + .uFuncSel = AM_HAL_PIN_45_UART0RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_49 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_49 = { + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// UART1_RX_2 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_2 = { + .uFuncSel = AM_HAL_PIN_2_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_4 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_4 = { + .uFuncSel = AM_HAL_PIN_4_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_9 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_9 = { + .uFuncSel = AM_HAL_PIN_9_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_13 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_13 = { + .uFuncSel = AM_HAL_PIN_13_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_15 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_15 = { + .uFuncSel = AM_HAL_PIN_15_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_19 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_19 = { + .uFuncSel = AM_HAL_PIN_19_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_21 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_21 = { + .uFuncSel = AM_HAL_PIN_21_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_25 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_25 = { + .uFuncSel = AM_HAL_PIN_25_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_36 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_36 = { + .uFuncSel = AM_HAL_PIN_36_UART1RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_38 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_38 = { + .uFuncSel = AM_HAL_PIN_38_UART1RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_40 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_40 = { + .uFuncSel = AM_HAL_PIN_40_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_43 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_43 = { + .uFuncSel = AM_HAL_PIN_43_UART1RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_47 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_47 = { + .uFuncSel = AM_HAL_PIN_47_UART1RX +}; + +//***************************************************************************** +// +// UART0_RTS_3 pin: UART0 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_3 = { + .uFuncSel = AM_HAL_PIN_3_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_RTS_5 pin: UART0 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_5 = { + .uFuncSel = AM_HAL_PIN_5_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_RTS_13 pin: UART0 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_13 = { + .uFuncSel = AM_HAL_PIN_13_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_RTS_18 pin: UART0 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_18 = { + .uFuncSel = AM_HAL_PIN_18_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_RTS_34 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_34 = { + .uFuncSel = AM_HAL_PIN_34_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_35 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_35 = { + .uFuncSel = AM_HAL_PIN_35_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_37 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_37 = { + .uFuncSel = AM_HAL_PIN_37_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_41 pin: UART0 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_41 = { + .uFuncSel = AM_HAL_PIN_41_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_RTS_10 pin: UART1 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_10 = { + .uFuncSel = AM_HAL_PIN_10_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_RTS_16 pin: UART1 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_16 = { + .uFuncSel = AM_HAL_PIN_16_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_RTS_20 pin: UART1 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_20 = { + .uFuncSel = AM_HAL_PIN_20_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_RTS_30 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_30 = { + .uFuncSel = AM_HAL_PIN_30_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_31 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_31 = { + .uFuncSel = AM_HAL_PIN_31_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_34 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_34 = { + .uFuncSel = AM_HAL_PIN_34_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_41 pin: UART1 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_41 = { + .uFuncSel = AM_HAL_PIN_41_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_RTS_44 pin: UART1 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_44 = { + .uFuncSel = AM_HAL_PIN_44_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_CTS_4 pin: UART0 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_4 = { + .uFuncSel = AM_HAL_PIN_4_UART0CTS +}; + +//***************************************************************************** +// +// UART0_CTS_6 pin: UART0 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_6 = { + .uFuncSel = AM_HAL_PIN_6_UART0CTS +}; + +//***************************************************************************** +// +// UART0_CTS_12 pin: UART0 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_12 = { + .uFuncSel = AM_HAL_PIN_12_UART0CTS +}; + +//***************************************************************************** +// +// UART0_CTS_24 pin: UART0 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_24 = { + .uFuncSel = AM_HAL_PIN_24_UART0CTS +}; + +//***************************************************************************** +// +// UART0_CTS_29 pin: UART0 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_29 = { + .uFuncSel = AM_HAL_PIN_29_UART0CTS +}; + +//***************************************************************************** +// +// UART0_CTS_33 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_33 = { + .uFuncSel = AM_HAL_PIN_33_UART0CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_CTS_36 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_36 = { + .uFuncSel = AM_HAL_PIN_36_UART0CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_CTS_38 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_38 = { + .uFuncSel = AM_HAL_PIN_38_UART0CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_11 pin: UART1 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_11 = { + .uFuncSel = AM_HAL_PIN_11_UART1CTS +}; + +//***************************************************************************** +// +// UART1_CTS_17 pin: UART1 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_17 = { + .uFuncSel = AM_HAL_PIN_17_UART1CTS +}; + +//***************************************************************************** +// +// UART1_CTS_21 pin: UART1 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_21 = { + .uFuncSel = AM_HAL_PIN_21_UART1CTS +}; + +//***************************************************************************** +// +// UART1_CTS_26 pin: UART1 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_26 = { + .uFuncSel = AM_HAL_PIN_26_UART1CTS +}; + +//***************************************************************************** +// +// UART1_CTS_29 pin: UART1 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_29 = { + .uFuncSel = AM_HAL_PIN_29_UART1CTS +}; + +//***************************************************************************** +// +// UART1_CTS_32 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_32 = { + .uFuncSel = AM_HAL_PIN_32_UART1CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_36 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_36 = { + .uFuncSel = AM_HAL_PIN_36_UART1CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_45 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_45 = { + .uFuncSel = AM_HAL_PIN_45_UART1CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_CS = { + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_CS3 = { + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_MISO = { + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_MOSI = { + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SCK = { + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SCL = { + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SDA = { + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_CS = { + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_MISO = { + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_MOSI = { + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SCK = { + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SCL = { + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SDA = { + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_CS = { + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_MISO = { + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_MOSI = { + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SCK = { + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SCL = { + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SDA = { + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_CS = { + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_MISO = { + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_MOSI = { + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SCK = { + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SCL = { + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SDA = { + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_CS = { + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_MISO = { + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_MOSI = { + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SCK = { + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SCL = { + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SDA = { + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_CS = { + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_MISO = { + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_MOSI = { + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SCK = { + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SCL = { + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SDA = { + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_CE0 = { + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_CE1 = { + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D0 = { + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D1 = { + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D2 = { + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D3 = { + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D4 = { + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D5 = { + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D6 = { + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D7 = { + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_SCK = { + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_CE = { + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_MISO = { + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_MOSI = { + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SCK = { + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SCL = { + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SDA = { + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// NCE_0 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_0 = { + .uFuncSel = AM_HAL_PIN_0_NCE0 +}; + +//***************************************************************************** +// +// NCE_1 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_1 = { + .uFuncSel = AM_HAL_PIN_1_NCE1 +}; + +//***************************************************************************** +// +// NCE_2 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_2 = { + .uFuncSel = AM_HAL_PIN_2_NCE2 +}; + +//***************************************************************************** +// +// NCE_3 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_3 = { + .uFuncSel = AM_HAL_PIN_3_NCE3 +}; + +//***************************************************************************** +// +// NCE_4 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_4 = { + .uFuncSel = AM_HAL_PIN_4_NCE4 +}; + +//***************************************************************************** +// +// NCE_7 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_7 = { + .uFuncSel = AM_HAL_PIN_7_NCE7 +}; + +//***************************************************************************** +// +// NCE_8 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_8 = { + .uFuncSel = AM_HAL_PIN_8_NCE8 +}; + +//***************************************************************************** +// +// NCE_9 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_9 = { + .uFuncSel = AM_HAL_PIN_9_NCE9 +}; + +//***************************************************************************** +// +// NCE_10 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_10 = { + .uFuncSel = AM_HAL_PIN_10_NCE10 +}; + +//***************************************************************************** +// +// NCE_11 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_11 = { + .uFuncSel = AM_HAL_PIN_11_NCE11 +}; + +//***************************************************************************** +// +// NCE_12 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_12 = { + .uFuncSel = AM_HAL_PIN_12_NCE12 +}; + +//***************************************************************************** +// +// NCE_13 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_13 = { + .uFuncSel = AM_HAL_PIN_13_NCE13 +}; + +//***************************************************************************** +// +// NCE_14 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_14 = { + .uFuncSel = AM_HAL_PIN_14_NCE14 +}; + +//***************************************************************************** +// +// NCE_15 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_15 = { + .uFuncSel = AM_HAL_PIN_15_NCE15 +}; + +//***************************************************************************** +// +// NCE_16 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_16 = { + .uFuncSel = AM_HAL_PIN_16_NCE16 +}; + +//***************************************************************************** +// +// NCE_17 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_17 = { + .uFuncSel = AM_HAL_PIN_17_NCE17 +}; + +//***************************************************************************** +// +// NCE_18 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_18 = { + .uFuncSel = AM_HAL_PIN_18_NCE18 +}; + +//***************************************************************************** +// +// NCE_19 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_19 = { + .uFuncSel = AM_HAL_PIN_19_NCE19 +}; + +//***************************************************************************** +// +// NCE_20 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_20 = { + .uFuncSel = AM_HAL_PIN_20_NCE20 +}; + +//***************************************************************************** +// +// NCE_21 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_21 = { + .uFuncSel = AM_HAL_PIN_21_NCE21 +}; + +//***************************************************************************** +// +// NCE_22 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_22 = { + .uFuncSel = AM_HAL_PIN_22_NCE22 +}; + +//***************************************************************************** +// +// NCE_23 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_23 = { + .uFuncSel = AM_HAL_PIN_23_NCE23 +}; + +//***************************************************************************** +// +// NCE_24 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_24 = { + .uFuncSel = AM_HAL_PIN_24_NCE24 +}; + +//***************************************************************************** +// +// NCE_25 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_25 = { + .uFuncSel = AM_HAL_PIN_25_NCE25 +}; + +//***************************************************************************** +// +// NCE_26 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_26 = { + .uFuncSel = AM_HAL_PIN_26_NCE26 +}; + +//***************************************************************************** +// +// NCE_27 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_27 = { + .uFuncSel = AM_HAL_PIN_27_NCE27 +}; + +//***************************************************************************** +// +// NCE_28 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_28 = { + .uFuncSel = AM_HAL_PIN_28_NCE28 +}; + +//***************************************************************************** +// +// NCE_29 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_29 = { + .uFuncSel = AM_HAL_PIN_29_NCE29 +}; + +//***************************************************************************** +// +// NCE_30 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_30 = { + .uFuncSel = AM_HAL_PIN_30_NCE30 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_31 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_31 = { + .uFuncSel = AM_HAL_PIN_31_NCE31 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_32 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_32 = { + .uFuncSel = AM_HAL_PIN_32_NCE32 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_33 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_33 = { + .uFuncSel = AM_HAL_PIN_33_NCE33 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_34 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_34 = { + .uFuncSel = AM_HAL_PIN_34_NCE34 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_35 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_35 = { + .uFuncSel = AM_HAL_PIN_35_NCE35 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_36 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_36 = { + .uFuncSel = AM_HAL_PIN_36_NCE36 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_37 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_37 = { + .uFuncSel = AM_HAL_PIN_37_NCE37 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_38 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_38 = { + .uFuncSel = AM_HAL_PIN_38_NCE38 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_41 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_41 = { + .uFuncSel = AM_HAL_PIN_41_NCE41 +}; + +//***************************************************************************** +// +// NCE_42 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_42 = { + .uFuncSel = AM_HAL_PIN_42_NCE42 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_43 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_43 = { + .uFuncSel = AM_HAL_PIN_43_NCE43 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_44 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_44 = { + .uFuncSel = AM_HAL_PIN_44_NCE44 +}; + +//***************************************************************************** +// +// NCE_45 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_45 = { + .uFuncSel = AM_HAL_PIN_45_NCE45 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_46 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_46 = { + .uFuncSel = AM_HAL_PIN_46_NCE46 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_47 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_47 = { + .uFuncSel = AM_HAL_PIN_47_NCE47 +}; + +//***************************************************************************** +// +// NCE_48 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_48 = { + .uFuncSel = AM_HAL_PIN_48_NCE48 +}; + +//***************************************************************************** +// +// NCE_49 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_49 = { + .uFuncSel = AM_HAL_PIN_49_NCE49 +}; + +//***************************************************************************** +// +// PDM_DATA_11 pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_11 = { + .uFuncSel = AM_HAL_PIN_11_PDMDATA +}; + +//***************************************************************************** +// +// PDM_DATA_15 pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_15 = { + .uFuncSel = AM_HAL_PIN_15_PDMDATA +}; + +//***************************************************************************** +// +// PDM_DATA_29 pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_29 = { + .uFuncSel = AM_HAL_PIN_29_PDMDATA +}; + +//***************************************************************************** +// +// PDM_DATA_34 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_34 = { + .uFuncSel = AM_HAL_PIN_34_PDMDATA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_DATA_36 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_36 = { + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_DATA_45 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_45 = { + .uFuncSel = AM_HAL_PIN_45_PDMDATA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_CLK_10 pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_10 = { + .uFuncSel = AM_HAL_PIN_10_PDMCLK +}; + +//***************************************************************************** +// +// PDM_CLK_12 pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_12 = { + .uFuncSel = AM_HAL_PIN_12_PDMCLK +}; + +//***************************************************************************** +// +// PDM_CLK_14 pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_14 = { + .uFuncSel = AM_HAL_PIN_14_PDMCLK +}; + +//***************************************************************************** +// +// PDM_CLK_22 pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_22 = { + .uFuncSel = AM_HAL_PIN_22_PDMCLK +}; + +//***************************************************************************** +// +// PDM_CLK_37 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_37 = { + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_CLK_46 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_46 = { + .uFuncSel = AM_HAL_PIN_46_PDMCLK +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_15 pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_15 = { + .uFuncSel = AM_HAL_PIN_15_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO = { + .uFuncSel = AM_HAL_PIN_22_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// ITM_SWO_24 pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_24 = { + .uFuncSel = AM_HAL_PIN_24_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// ITM_SWO_33 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_33 = { + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_41 pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_41 = { + .uFuncSel = AM_HAL_PIN_41_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// ITM_SWO_45 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_45 = { + .uFuncSel = AM_HAL_PIN_45_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_46 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_46 = { + .uFuncSel = AM_HAL_PIN_46_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// CORE_SWDCK_14 pin: Cortex Serial Wire Debug Clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDCK_14 = { + .uFuncSel = AM_HAL_PIN_14_SWDCK +}; + +//***************************************************************************** +// +// CORE_SWDCK_20 pin: Cortex Serial Wire Debug Clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDCK_20 = { + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// CORE_SWDIO_15 pin: Cortex Serial Wire Debug I/O. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDIO_15 = { + .uFuncSel = AM_HAL_PIN_15_SWDIO +}; + +//***************************************************************************** +// +// CORE_SWDIO_21 pin: Cortex Serial Wire Debug I/O. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDIO_21 = { + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.h new file mode 100644 index 0000000..faa977b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.h @@ -0,0 +1,1818 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef _APOLLO3_PERIPHERAL_PIN_CONFIGS_H_ +#define _APOLLO3_PERIPHERAL_PIN_CONFIGS_H_ + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// UART0_TX_1 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_1 1 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_1; + +//***************************************************************************** +// +// UART0_TX_7 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_7 7 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_7; + +//***************************************************************************** +// +// UART0_TX_16 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_16 16 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_16; + +//***************************************************************************** +// +// UART0_TX_20 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_20 20 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_20; + +//***************************************************************************** +// +// UART0_TX_22 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_22 22 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_22; + +//***************************************************************************** +// +// UART0_TX_26 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_26 26 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_26; + +//***************************************************************************** +// +// UART0_TX_28 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_28 28 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_28; + +//***************************************************************************** +// +// UART0_TX_30 pin: UART0 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_TX_30 30 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_30; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_TX_39 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_39 39 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_39; + +//***************************************************************************** +// +// UART0_TX_41 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_41 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_41; + +//***************************************************************************** +// +// UART0_TX_44 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_44 44 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_44; + +//***************************************************************************** +// +// UART0_TX_48 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_48 48 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_48; + +//***************************************************************************** +// +// UART1_TX_8 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_8 8 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_8; + +//***************************************************************************** +// +// UART1_TX_10 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_10 10 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_10; + +//***************************************************************************** +// +// UART1_TX_12 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_12 12 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_12; + +//***************************************************************************** +// +// UART1_TX_14 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_14 14 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_14; + +//***************************************************************************** +// +// UART1_TX_18 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_18 18 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_18; + +//***************************************************************************** +// +// UART1_TX_20 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_20 20 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_20; + +//***************************************************************************** +// +// UART1_TX_24 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_24 24 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_24; + +//***************************************************************************** +// +// UART1_TX_35 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_TX_35 35 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_35; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_37 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_TX_37 37 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_37; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_39 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_39 39 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_39; + +//***************************************************************************** +// +// UART1_TX_42 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_TX_42 42 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_42; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_46 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_TX_46 46 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_46; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_2 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_2 2 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_2; + +//***************************************************************************** +// +// UART0_RX_11 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_11 11 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_11; + +//***************************************************************************** +// +// UART0_RX_17 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_17 17 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_17; + +//***************************************************************************** +// +// UART0_RX_21 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_21 21 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_21; + +//***************************************************************************** +// +// UART0_RX_23 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_23 23 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_23; + +//***************************************************************************** +// +// UART0_RX_27 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_27 27 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_27; + +//***************************************************************************** +// +// UART0_RX_29 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_29 29 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_29; + +//***************************************************************************** +// +// UART0_RX_31 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RX_31 31 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_31; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_34 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RX_34 34 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_34; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_40 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_40 40 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_40; + +//***************************************************************************** +// +// UART0_RX_45 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RX_45 45 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_45; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_49 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_49 49 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_49; + +//***************************************************************************** +// +// UART1_RX_2 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_2 2 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_2; + +//***************************************************************************** +// +// UART1_RX_4 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_4 4 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_4; + +//***************************************************************************** +// +// UART1_RX_9 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_9 9 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_9; + +//***************************************************************************** +// +// UART1_RX_13 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_13 13 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_13; + +//***************************************************************************** +// +// UART1_RX_15 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_15 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_15; + +//***************************************************************************** +// +// UART1_RX_19 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_19 19 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_19; + +//***************************************************************************** +// +// UART1_RX_21 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_21 21 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_21; + +//***************************************************************************** +// +// UART1_RX_25 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_25 25 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_25; + +//***************************************************************************** +// +// UART1_RX_36 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RX_36 36 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_36; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_38 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RX_38 38 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_38; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_40 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_40 40 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_40; + +//***************************************************************************** +// +// UART1_RX_43 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RX_43 43 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_43; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_47 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_47 47 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_47; + +//***************************************************************************** +// +// UART0_RTS_3 pin: UART0 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RTS_3 3 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_3; + +//***************************************************************************** +// +// UART0_RTS_5 pin: UART0 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RTS_5 5 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_5; + +//***************************************************************************** +// +// UART0_RTS_13 pin: UART0 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RTS_13 13 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_13; + +//***************************************************************************** +// +// UART0_RTS_18 pin: UART0 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RTS_18 18 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_18; + +//***************************************************************************** +// +// UART0_RTS_34 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RTS_34 34 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_34; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_35 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RTS_35 35 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_35; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_37 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RTS_37 37 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_37; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_41 pin: UART0 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RTS_41 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_41; + +//***************************************************************************** +// +// UART1_RTS_10 pin: UART1 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RTS_10 10 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_10; + +//***************************************************************************** +// +// UART1_RTS_16 pin: UART1 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RTS_16 16 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_16; + +//***************************************************************************** +// +// UART1_RTS_20 pin: UART1 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RTS_20 20 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_20; + +//***************************************************************************** +// +// UART1_RTS_30 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RTS_30 30 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_30; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_31 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RTS_31 31 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_31; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_34 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RTS_34 34 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_34; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_41 pin: UART1 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RTS_41 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_41; + +//***************************************************************************** +// +// UART1_RTS_44 pin: UART1 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RTS_44 44 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_44; + +//***************************************************************************** +// +// UART0_CTS_4 pin: UART0 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_CTS_4 4 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_4; + +//***************************************************************************** +// +// UART0_CTS_6 pin: UART0 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_CTS_6 6 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_6; + +//***************************************************************************** +// +// UART0_CTS_12 pin: UART0 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_CTS_12 12 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_12; + +//***************************************************************************** +// +// UART0_CTS_24 pin: UART0 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_CTS_24 24 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_24; + +//***************************************************************************** +// +// UART0_CTS_29 pin: UART0 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_CTS_29 29 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_29; + +//***************************************************************************** +// +// UART0_CTS_33 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_CTS_33 33 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_33; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_CTS_36 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_CTS_36 36 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_36; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_CTS_38 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_CTS_38 38 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_38; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_11 pin: UART1 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_CTS_11 11 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_11; + +//***************************************************************************** +// +// UART1_CTS_17 pin: UART1 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_CTS_17 17 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_17; + +//***************************************************************************** +// +// UART1_CTS_21 pin: UART1 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_CTS_21 21 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_21; + +//***************************************************************************** +// +// UART1_CTS_26 pin: UART1 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_CTS_26 26 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_26; + +//***************************************************************************** +// +// UART1_CTS_29 pin: UART1 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_CTS_29 29 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_29; + +//***************************************************************************** +// +// UART1_CTS_32 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_CTS_32 32 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_32; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_36 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_CTS_36 36 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_36; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_45 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_CTS_45 45 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_45; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_CS; +#define AP3_PER_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_CS3; +#define AP3_PER_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_CS; +#define AP3_PER_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_CS; +#define AP3_PER_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_CS; +#define AP3_PER_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_MISO; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_MOSI; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SCK; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SCL; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SDA; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_CS; +#define AP3_PER_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_CS; +#define AP3_PER_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AP3_PER_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_CE0; +#define AP3_PER_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AP3_PER_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_CE1; +#define AP3_PER_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AP3_PER_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AP3_PER_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AP3_PER_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AP3_PER_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AP3_PER_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AP3_PER_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AP3_PER_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AP3_PER_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AP3_PER_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AP3_PER_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_CE; +#define AP3_PER_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SDA; + +//***************************************************************************** +// +// NCE_0 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_0 0 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_0; + +//***************************************************************************** +// +// NCE_1 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_1 1 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_1; + +//***************************************************************************** +// +// NCE_2 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_2 2 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_2; + +//***************************************************************************** +// +// NCE_3 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_3 3 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_3; + +//***************************************************************************** +// +// NCE_4 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_4 4 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_4; + +//***************************************************************************** +// +// NCE_7 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_7 7 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_7; + +//***************************************************************************** +// +// NCE_8 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_8 8 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_8; + +//***************************************************************************** +// +// NCE_9 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_9 9 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_9; + +//***************************************************************************** +// +// NCE_10 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_10 10 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_10; + +//***************************************************************************** +// +// NCE_11 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_11 11 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_11; + +//***************************************************************************** +// +// NCE_12 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_12 12 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_12; + +//***************************************************************************** +// +// NCE_13 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_13 13 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_13; + +//***************************************************************************** +// +// NCE_14 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_14 14 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_14; + +//***************************************************************************** +// +// NCE_15 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_15 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_15; + +//***************************************************************************** +// +// NCE_16 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_16 16 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_16; + +//***************************************************************************** +// +// NCE_17 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_17 17 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_17; + +//***************************************************************************** +// +// NCE_18 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_18 18 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_18; + +//***************************************************************************** +// +// NCE_19 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_19 19 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_19; + +//***************************************************************************** +// +// NCE_20 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_20 20 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_20; + +//***************************************************************************** +// +// NCE_21 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_21 21 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_21; + +//***************************************************************************** +// +// NCE_22 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_22 22 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_22; + +//***************************************************************************** +// +// NCE_23 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_23 23 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_23; + +//***************************************************************************** +// +// NCE_24 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_24 24 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_24; + +//***************************************************************************** +// +// NCE_25 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_25 25 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_25; + +//***************************************************************************** +// +// NCE_26 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_26 26 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_26; + +//***************************************************************************** +// +// NCE_27 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_27 27 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_27; + +//***************************************************************************** +// +// NCE_28 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_28 28 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_28; + +//***************************************************************************** +// +// NCE_29 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_29 29 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_29; + +//***************************************************************************** +// +// NCE_30 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_30 30 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_30; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_31 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_31 31 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_31; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_32 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_32 32 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_32; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_33 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_33 33 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_33; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_34 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_34 34 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_34; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_35 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_35 35 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_35; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_36 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_36 36 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_36; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_37 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_37 37 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_37; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_38 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_38 38 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_38; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_41 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_41 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_41; + +//***************************************************************************** +// +// NCE_42 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_42 42 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_42; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_43 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_43 43 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_43; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_44 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_44 44 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_44; + +//***************************************************************************** +// +// NCE_45 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_45 45 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_45; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_46 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_46 46 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_46; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_47 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_47 47 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_47; + +//***************************************************************************** +// +// NCE_48 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_48 48 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_48; + +//***************************************************************************** +// +// NCE_49 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_49 49 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_49; + +//***************************************************************************** +// +// PDM_DATA_11 pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_DATA_11 11 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_11; + +//***************************************************************************** +// +// PDM_DATA_15 pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_DATA_15 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_15; + +//***************************************************************************** +// +// PDM_DATA_29 pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_DATA_29 29 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_29; + +//***************************************************************************** +// +// PDM_DATA_34 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_PDM_DATA_34 34 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_34; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_DATA_36 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_PDM_DATA_36 36 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_36; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_DATA_45 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_PDM_DATA_45 45 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_45; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_CLK_10 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_CLK_10 10 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_10; + +//***************************************************************************** +// +// PDM_CLK_12 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_CLK_12 12 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_12; + +//***************************************************************************** +// +// PDM_CLK_14 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_CLK_14 14 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_14; + +//***************************************************************************** +// +// PDM_CLK_22 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_CLK_22 22 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_22; + +//***************************************************************************** +// +// PDM_CLK_37 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_PDM_CLK_37 37 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_37; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_CLK_46 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_PDM_CLK_46 46 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_46; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_15 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AP3_PER_ITM_SWO_15 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_15; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AP3_PER_ITM_SWO 22 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO; + +//***************************************************************************** +// +// ITM_SWO_24 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AP3_PER_ITM_SWO_24 24 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_24; + +//***************************************************************************** +// +// ITM_SWO_33 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_ITM_SWO_33 33 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_33; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_41 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AP3_PER_ITM_SWO_41 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_41; + +//***************************************************************************** +// +// ITM_SWO_45 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_ITM_SWO_45 45 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_45; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_46 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_ITM_SWO_46 46 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_46; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// CORE_SWDCK_14 pin: Cortex Serial Wire Debug Clock. +// +//***************************************************************************** +#define AP3_PER_CORE_SWDCK_14 14 +extern const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDCK_14; + +//***************************************************************************** +// +// CORE_SWDCK_20 pin: Cortex Serial Wire Debug Clock. +// +//***************************************************************************** +#define AP3_PER_CORE_SWDCK_20 20 +extern const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDCK_20; + +//***************************************************************************** +// +// CORE_SWDIO_15 pin: Cortex Serial Wire Debug I/O. +// +//***************************************************************************** +#define AP3_PER_CORE_SWDIO_15 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDIO_15; + +//***************************************************************************** +// +// CORE_SWDIO_21 pin: Cortex Serial Wire Debug I/O. +// +//***************************************************************************** +#define AP3_PER_CORE_SWDIO_21 21 +extern const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDIO_21; + + +#ifdef __cplusplus +} +#endif + +#endif // _APOLLO3_PERIPHERAL_PIN_CONFIGS_H_ + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.c new file mode 100644 index 0000000..1eb737d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.c @@ -0,0 +1,258 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// SPDX-License-Identifier: Apache-2.0 +#include "PeripheralPins.h" +#include "PeripheralPinConfigs.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, 0, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {NC, NC, 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {NC, NC, 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {AP3_PER_IOM0_SDA, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SDA}, + {AP3_PER_IOM1_SDA, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SDA}, + {AP3_PER_IOM2_SDA, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SDA}, + {AP3_PER_IOM4_SDA, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SDA}, + {AP3_PER_IOM5_SDA, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SDA}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_IOM3_SDA, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SDA}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {AP3_PER_IOM0_SCL, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SCL}, + {AP3_PER_IOM1_SCL, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SCL}, + {AP3_PER_IOM2_SCL, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SCL}, + {AP3_PER_IOM4_SCL, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SCL}, + {AP3_PER_IOM5_SCL, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SCL}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_IOM3_SCL, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SCL}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {AP3_PER_UART0_TX_1, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_1}, + {AP3_PER_UART0_TX_7, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_7}, + {AP3_PER_UART0_TX_16, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_16}, + {AP3_PER_UART0_TX_20, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_20}, + {AP3_PER_UART0_TX_22, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_22}, + {AP3_PER_UART0_TX_26, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_26}, + {AP3_PER_UART0_TX_28, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_28}, + {AP3_PER_UART0_TX_39, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_39}, + {AP3_PER_UART0_TX_41, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_41}, + {AP3_PER_UART0_TX_44, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_44}, + {AP3_PER_UART0_TX_48, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_48}, + {AP3_PER_UART1_TX_8, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_8}, + {AP3_PER_UART1_TX_10, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_10}, + {AP3_PER_UART1_TX_12, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_12}, + {AP3_PER_UART1_TX_14, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_14}, + {AP3_PER_UART1_TX_18, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_18}, + {AP3_PER_UART1_TX_20, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_20}, + {AP3_PER_UART1_TX_24, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_24}, + {AP3_PER_UART1_TX_39, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_39}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_UART0_TX_30, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_30}, + {AP3_PER_UART1_TX_35, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_35}, + {AP3_PER_UART1_TX_37, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_37}, + {AP3_PER_UART1_TX_42, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_42}, + {AP3_PER_UART1_TX_46, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_46}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {AP3_PER_UART0_RX_2, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_2}, + {AP3_PER_UART0_RX_11, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_11}, + {AP3_PER_UART0_RX_17, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_17}, + {AP3_PER_UART0_RX_21, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_21}, + {AP3_PER_UART0_RX_23, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_23}, + {AP3_PER_UART0_RX_27, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_27}, + {AP3_PER_UART0_RX_29, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_29}, + {AP3_PER_UART0_RX_40, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_40}, + {AP3_PER_UART0_RX_49, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_49}, + {AP3_PER_UART1_RX_2, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_2}, + {AP3_PER_UART1_RX_4, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_4}, + {AP3_PER_UART1_RX_9, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_9}, + {AP3_PER_UART1_RX_13, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_13}, + {AP3_PER_UART1_RX_15, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_15}, + {AP3_PER_UART1_RX_19, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_19}, + {AP3_PER_UART1_RX_21, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_21}, + {AP3_PER_UART1_RX_25, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_25}, + {AP3_PER_UART1_RX_40, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_40}, + {AP3_PER_UART1_RX_47, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_47}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_UART0_RX_31, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_31}, + {AP3_PER_UART0_RX_34, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_34}, + {AP3_PER_UART0_RX_45, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_45}, + {AP3_PER_UART1_RX_36, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_36}, + {AP3_PER_UART1_RX_38, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_38}, + {AP3_PER_UART1_RX_43, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_43}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {3, UART_0, AM_HAL_PIN_3_UART0RTS}, + {5, UART_0, AM_HAL_PIN_5_UART0RTS}, + {13, UART_0, AM_HAL_PIN_13_UART0RTS}, + {18, UART_0, AM_HAL_PIN_18_UART0RTS}, + {41, UART_0, AM_HAL_PIN_41_UART0RTS}, + {10, UART_1, AM_HAL_PIN_10_UART1RTS}, + {16, UART_1, AM_HAL_PIN_16_UART1RTS}, + {20, UART_1, AM_HAL_PIN_20_UART1RTS}, + {41, UART_1, AM_HAL_PIN_41_UART1RTS}, + {44, UART_1, AM_HAL_PIN_44_UART1RTS}, +#if defined (AM_PACKAGE_BGA) + {34, UART_0, AM_HAL_PIN_34_UART0RTS}, + {35, UART_0, AM_HAL_PIN_35_UART0RTS}, + {37, UART_0, AM_HAL_PIN_37_UART0RTS}, + {30, UART_1, AM_HAL_PIN_30_UART1RTS}, + {31, UART_1, AM_HAL_PIN_31_UART1RTS}, + {34, UART_1, AM_HAL_PIN_34_UART1RTS}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {4, UART_0, AM_HAL_PIN_4_UART0CTS}, + {6, UART_0, AM_HAL_PIN_6_UART0CTS}, + {12, UART_0, AM_HAL_PIN_12_UART0CTS}, + {24, UART_0, AM_HAL_PIN_24_UART0CTS}, + {29, UART_0, AM_HAL_PIN_29_UART0CTS}, + {11, UART_1, AM_HAL_PIN_11_UART1CTS}, + {17, UART_1, AM_HAL_PIN_17_UART1CTS}, + {21, UART_1, AM_HAL_PIN_21_UART1CTS}, + {26, UART_1, AM_HAL_PIN_26_UART1CTS}, + {29, UART_1, AM_HAL_PIN_29_UART1CTS}, +#if defined (AM_PACKAGE_BGA) + {33, UART_0, AM_HAL_PIN_33_UART0CTS}, + {36, UART_0, AM_HAL_PIN_36_UART0CTS}, + {38, UART_0, AM_HAL_PIN_38_UART0CTS}, + {32, UART_1, AM_HAL_PIN_32_UART1CTS}, + {36, UART_1, AM_HAL_PIN_36_UART1CTS}, + {45, UART_1, AM_HAL_PIN_45_UART1CTS}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {AP3_PER_IOM0_SCK, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SCK}, + {AP3_PER_IOM1_SCK, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SCK}, + {AP3_PER_IOM2_SCK, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SCK}, + {AP3_PER_IOM4_SCK, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SCK}, + {AP3_PER_IOM5_SCK, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SCK}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_IOM3_SCK, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SCK}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {AP3_PER_IOM0_MOSI, IOM_0, (uint32_t) &g_AP3_PER_IOM0_MOSI}, + {AP3_PER_IOM1_MOSI, IOM_1, (uint32_t) &g_AP3_PER_IOM1_MOSI}, + {AP3_PER_IOM2_MOSI, IOM_2, (uint32_t) &g_AP3_PER_IOM2_MOSI}, + {AP3_PER_IOM4_MOSI, IOM_4, (uint32_t) &g_AP3_PER_IOM4_MOSI}, + {AP3_PER_IOM5_MOSI, IOM_5, (uint32_t) &g_AP3_PER_IOM5_MOSI}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_IOM3_MOSI, IOM_3, (uint32_t) &g_AP3_PER_IOM3_MOSI}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {AP3_PER_IOM0_MISO, IOM_0, (uint32_t) &g_AP3_PER_IOM0_MISO}, + {AP3_PER_IOM1_MISO, IOM_1, (uint32_t) &g_AP3_PER_IOM1_MISO}, + {AP3_PER_IOM2_MISO, IOM_2, (uint32_t) &g_AP3_PER_IOM2_MISO}, + {AP3_PER_IOM4_MISO, IOM_4, (uint32_t) &g_AP3_PER_IOM4_MISO}, + {AP3_PER_IOM5_MISO, IOM_5, (uint32_t) &g_AP3_PER_IOM5_MISO}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_IOM3_MISO, IOM_3, (uint32_t) &g_AP3_PER_IOM3_MISO}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {AP3_PER_NCE_0, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_0}, + {AP3_PER_NCE_1, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_1}, + {AP3_PER_NCE_2, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_2}, + {AP3_PER_NCE_3, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_3}, + {AP3_PER_NCE_4, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_4}, + {AP3_PER_NCE_7, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_7}, + {AP3_PER_NCE_8, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_8}, + {AP3_PER_NCE_9, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_9}, + {AP3_PER_NCE_10, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_10}, + {AP3_PER_NCE_11, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_11}, + {AP3_PER_NCE_12, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_12}, + {AP3_PER_NCE_13, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_13}, + {AP3_PER_NCE_14, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_14}, + {AP3_PER_NCE_15, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_15}, + {AP3_PER_NCE_16, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_16}, + {AP3_PER_NCE_17, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_17}, + {AP3_PER_NCE_18, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_18}, + {AP3_PER_NCE_19, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_19}, + {AP3_PER_NCE_20, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_20}, + {AP3_PER_NCE_21, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_21}, + {AP3_PER_NCE_22, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_22}, + {AP3_PER_NCE_23, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_23}, + {AP3_PER_NCE_24, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_24}, + {AP3_PER_NCE_25, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_25}, + {AP3_PER_NCE_26, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_26}, + {AP3_PER_NCE_27, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_27}, + {AP3_PER_NCE_28, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_28}, + {AP3_PER_NCE_29, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_29}, + {AP3_PER_NCE_41, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_41}, + {AP3_PER_NCE_44, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_44}, + {AP3_PER_NCE_47, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_47}, + {AP3_PER_NCE_48, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_48}, + {AP3_PER_NCE_49, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_49}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_NCE_30, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_30}, + {AP3_PER_NCE_31, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_31}, + {AP3_PER_NCE_32, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_32}, + {AP3_PER_NCE_33, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_33}, + {AP3_PER_NCE_34, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_34}, + {AP3_PER_NCE_35, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_35}, + {AP3_PER_NCE_36, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_36}, + {AP3_PER_NCE_37, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_37}, + {AP3_PER_NCE_38, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_38}, + {AP3_PER_NCE_42, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_42}, + {AP3_PER_NCE_43, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_43}, + {AP3_PER_NCE_45, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_45}, + {AP3_PER_NCE_46, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_46}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {NC, NC, 0} +}; diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.h new file mode 100644 index 0000000..f0d1c3c --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.h @@ -0,0 +1,73 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2018-2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// SPDX-License-Identifier: Apache-2.0 +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +//*** I2C *** +#if DEVICE_I2C +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; +#endif + +//*** PWM *** +#if DEVICE_PWMOUT +extern const PinMap PinMap_PWM_OUT[]; +#endif + +//*** SERIAL *** +#if DEVICE_SERIAL +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif + +//*** SPI *** +#if DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif + +//*** ADC *** +#if DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +#endif + +//*** DAC *** +#if DEVICE_ANALOGOUT +extern const PinMap PinMap_DAC[]; +#endif + +//*** QSPI *** +#if DEVICE_QSPI +extern const PinMap PinMap_QSPI_SCLK[]; +extern const PinMap PinMap_QSPI_SSEL[]; +extern const PinMap PinMap_QSPI_DATA0[]; +extern const PinMap PinMap_QSPI_DATA1[]; +extern const PinMap PinMap_QSPI_DATA2[]; +extern const PinMap PinMap_QSPI_DATA3[]; +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis.h new file mode 100644 index 0000000..840f172 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "am_mcu_apollo.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis_nvic.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis_nvic.h new file mode 100644 index 0000000..41e919f --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis_nvic.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 32 + 16) // CORE + MCU Peripherals + BLE Patch +#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of RAM + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/device.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/device.h new file mode 100644 index 0000000..8bafaf4 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/device.h @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +//======================================= +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" +#include "extensions.h" +#include "us_ticker_defines.h" + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/extensions.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/extensions.h new file mode 100644 index 0000000..dd3890a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/extensions.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _MBED_APOLLO3_EXTENSIONS_H_ +#define _MBED_APOLLO3_EXTENSIONS_H_ + +#include "pinmap.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void pinmap_config(PinName pin, const PinMap *map); +void pin_config(PinName pin, am_hal_gpio_pincfg_t pincfg); + +#ifdef __cplusplus +} +#endif + +#endif // _MBED_APOLLO3_EXTENSIONS_H_ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/flash_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/flash_api.c new file mode 100644 index 0000000..4f6863d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/flash_api.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "flash_api.h" +#include + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + if (!ISADDRFLASH(address)) { + return -1; + } + uint32_t status = am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, AM_HAL_FLASH_ADDR2INST(address), AM_HAL_FLASH_ADDR2PAGE(address)); + if (status != AM_HAL_STATUS_SUCCESS) { + return -1; + } + return 0; +} + +int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) +{ + memcpy(data, (void *)address, size); + return 0; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + if (address & 0x03) { + return -1; + } + if (((uint32_t)data) & 0x03) { + return -1; + } + uint32_t words = (size + 3) / 4; + uint32_t status = am_hal_flash_program_main(AM_HAL_FLASH_PROGRAM_KEY, (uint32_t *)data, (uint32_t *)address, words); + if (status != AM_HAL_STATUS_SUCCESS) { + return -1; + } + return 0; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if (address > AM_HAL_FLASH_LARGEST_VALID_ADDR) { + return -1; + } + return AM_HAL_FLASH_PAGE_SIZE; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return 4; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return AM_HAL_FLASH_ADDR; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return AM_HAL_FLASH_TOTAL_SIZE; +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + return 0xFF; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_api.c new file mode 100644 index 0000000..8ca3e34 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_api.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "mbed_assert.h" +#include "gpio_api.h" + +/** Set the given pin as GPIO + * + * @param pin The pin to be set as GPIO + * @return The GPIO port mask for this pin + **/ +uint32_t gpio_set(PinName pin) +{ + MBED_ASSERT(pin != (PinName)NC); + return (uint32_t)AM_HAL_GPIO_BIT(pin); +} + +/** Checks if gpio object is connected (pin was not initialized with NC) + * @param obj The GPIO object + * @return 0 if object was initialized with NC + * @return non-zero if object was initialized with a valid PinName + **/ +int gpio_is_connected(const gpio_t *obj) +{ + MBED_ASSERT(obj != NULL); + return (int)(((PinName)obj->pad == (PinName)NC) ? 0 : 1); +} + +/** Initialize the GPIO pin + * + * @param obj The GPIO object to initialize + * @param pin The GPIO pin to initialize (may be NC) + */ +void gpio_init(gpio_t *obj, PinName pin) +{ + MBED_ASSERT(obj != NULL); + obj->pad = (ap3_uart_pad_t)pin; + return; +} +/** Set the input pin mode + * + * @param obj The GPIO object (must be connected) + * @param mode The pin mode to be set + */ +void gpio_mode(gpio_t *obj, PinMode mode) +{ + MBED_ASSERT(gpio_is_connected(obj)); + MBED_ASSERT(mode < (PinMode)PinModeElements); + am_hal_gpio_pincfg_allow_t pinConfigBools; + + obj->cfg.uFuncSel = AP3_PINCFG_FUNCSEL_GPIO; // gpio + + if (mode & (PinMode)PowerSwNone) { + obj->cfg.ePowerSw = AM_HAL_GPIO_PIN_POWERSW_NONE; + pinConfigBools.ePowerSw = true; + } + if (mode & (PinMode)PowerSwVDD) { + obj->cfg.ePowerSw = AM_HAL_GPIO_PIN_POWERSW_VDD; + pinConfigBools.ePowerSw = true; + } + if (mode & (PinMode)PowerSwVSS) { + obj->cfg.ePowerSw = AM_HAL_GPIO_PIN_POWERSW_VSS; + pinConfigBools.ePowerSw = true; + } + + if (mode & (PinMode)PullNone) { + obj->cfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_NONE; + pinConfigBools.ePullup = true; + } + if (mode & (PinMode)PullUp) { + obj->cfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_WEAK; + pinConfigBools.ePullup = true; + } + if (mode & (PinMode)PullDown) { + obj->cfg.ePullup = AM_HAL_GPIO_PIN_PULLDOWN; + pinConfigBools.ePullup = true; + } + + if (mode & (PinMode)DriveStrength2mA) { + obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA; + pinConfigBools.eDriveStrength = true; + } + if (mode & (PinMode)DriveStrength4mA) { + obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA; + pinConfigBools.eDriveStrength = true; + } + if (mode & (PinMode)DriveStrength8mA) { + obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA; + pinConfigBools.eDriveStrength = true; + } + if (mode & (PinMode)DriveStrength12mA) { + obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA; + pinConfigBools.eDriveStrength = true; + } + + if (mode & (PinMode)OutDisable) { + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE; + pinConfigBools.eGPOutcfg = true; + } + if (mode & (PinMode)OutPushPull) { + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL; + pinConfigBools.eGPOutcfg = true; + } + if (mode & (PinMode)OutOpenDrain) { + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN; + pinConfigBools.eGPOutcfg = true; + } + if (mode & (PinMode)OutTristate) { + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_TRISTATE; + pinConfigBools.eGPOutcfg = true; + } + + if (mode & (PinMode)InAuto) { + obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_AUTO; + pinConfigBools.eGPInput = true; + } + if (mode & (PinMode)InNone) { + obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE; + pinConfigBools.eGPInput = true; + } + if (mode & (PinMode)InEnable) { + obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE; + pinConfigBools.eGPInput = true; + } + + if (mode & (PinMode)ReadPin) { + obj->cfg.eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN; + pinConfigBools.eGPRdZero = true; + } + if (mode & (PinMode)ReadZero) { + obj->cfg.eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_ZERO; + pinConfigBools.eGPRdZero = true; + } + + ap3_hal_gpio_pinconfig_partial((uint32_t)(obj->pad), obj->cfg, pinConfigBools); //padRegMsk.byte, GPConfigMsk.byte, padAltCfgMsk.byte); // apply configuration +} + +/** Set the pin direction + * + * @param obj The GPIO object (must be connected) + * @param direction The pin direction to be set + */ +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + MBED_ASSERT(gpio_is_connected(obj)); + MBED_ASSERT(direction < (PinDirection)PIN_DIR_ELEMENTS); + am_hal_gpio_pincfg_allow_t pinConfigBools; + + if (direction == (PinDirection)PIN_INPUT) { + obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE; + pinConfigBools.eGPInput = true; + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE; + pinConfigBools.eGPOutcfg = true; + } else if (direction == (PinDirection)PIN_OUTPUT) { + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL; + pinConfigBools.eGPOutcfg = true; + obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA; + pinConfigBools.eDriveStrength = true; + obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE; + pinConfigBools.eGPInput = true; + } else { + MBED_ASSERT(false); + } + + ap3_hal_gpio_pinconfig_partial((uint32_t)(obj->pad), obj->cfg, pinConfigBools); //padRegMsk.byte, GPConfigMsk.byte, padAltCfgMsk.byte); // apply configuration +} + +/** Set the output value + * + * @param obj The GPIO object (must be connected) + * @param value The value to be set + */ +void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(gpio_is_connected(obj)); + (value) ? am_hal_gpio_output_set(obj->pad) : am_hal_gpio_output_clear(obj->pad); +} + +/** Read the input value + * + * @param obj The GPIO object (must be connected) + * @return An integer value 1 or 0 + */ +int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(gpio_is_connected(obj)); + uint32_t ui32BaseAddr = (obj->pad) / 8; + uint32_t ui32BaseShift = (((obj->pad) % 8) * 4) + 1; + uint8_t output = ((AM_REGVAL(&GPIO->CFGA + ui32BaseAddr) >> ui32BaseShift) & 0x03); + + return (output) ? (int)am_hal_gpio_output_read(obj->pad) : (int)am_hal_gpio_input_read(obj->pad); + return 0; +} + +/** Get the pins that support all GPIO tests + * + * Return a PinMap array of pins that support GPIO. The + * array is terminated with {NC, NC, 0}. + * + * Targets should override the weak implementation of this + * function to provide the actual pinmap for GPIO testing. + * + * @return PinMap array + */ +const PinMap *gpio_pinmap(void) +{ + MBED_ASSERT(false); + return NULL; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c new file mode 100644 index 0000000..06fcb40 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "gpio_irq_api.h" +#include "objects.h" + +#if DEVICE_INTERRUPTIN + +#ifdef __cplusplus +extern "C" +{ +#endif + +uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, am_hal_gpio_intdir_e eIntDir); +/** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL +*/ +typedef struct gpio_irq_s gpio_irq_t; + +typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); +extern void am_gpio_isr(void); +static ap3_gpio_irq_control_t gpio_irq_control[AP3_GPIO_MAX_PADS]; + +/** +* \defgroup hal_gpioirq GPIO IRQ HAL functions +* +* # Defined behavior +* * ::gpio_irq_init initializes the GPIO IRQ pin +* * ::gpio_irq_init attaches the interrupt handler +* * ::gpio_irq_free releases the GPIO IRQ pin +* * ::gpio_irq_set enables/disables pin IRQ event +* * ::gpio_irq_enable enables GPIO IRQ +* * ::gpio_irq_disable disables GPIO IRQ +* +* # Undefined behavior +* * Calling other function before ::gpio_irq_init +* +* @{ +*/ + +/** Initialize the GPIO IRQ pin +* +* @param obj The GPIO object to initialize +* @param pin The GPIO pin name +* @param handler The handler to be attached to GPIO IRQ +* @param id The object ID (id != 0, 0 is reserved) +* @return -1 if pin is NC, 0 otherwise +*/ +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + //grab the correct irq control object + ap3_gpio_irq_control_t *control = &gpio_irq_control[pin]; + + //Register locally + control->pad = pin; + control->handler = handler; + control->id = id; + control->events = IRQ_NONE; + + //Attach to object + obj->control = control; + + //Make sure the interrupt is set to none to reflect the new events value + ap3_gpio_enable_interrupts(control->pad, AM_HAL_GPIO_PIN_INTDIR_NONE); + + //Enable GPIO IRQ's in the NVIC + gpio_irq_enable(obj); + NVIC_SetVector((IRQn_Type)GPIO_IRQn, (uint32_t)am_gpio_isr); + NVIC_EnableIRQ((IRQn_Type)GPIO_IRQn); + return 0; +} + +void am_gpio_isr(void) +{ + //call the handler for the interrupt + uint64_t gpio_int_mask = 0x00; + am_hal_gpio_interrupt_status_get(true, &gpio_int_mask); + uint32_t pinNum = 0; + while (gpio_int_mask) { + if (gpio_int_mask & 0x0000000000000001) { + am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(pinNum)); + ap3_gpio_irq_control_t irq_ctrl = gpio_irq_control[pinNum]; + ((gpio_irq_handler)irq_ctrl.handler)(irq_ctrl.id, irq_ctrl.events); + } + gpio_int_mask >>= 1; + pinNum++; + } +} + +/** Release the GPIO IRQ PIN +* +* @param obj The gpio object +*/ +void gpio_irq_free(gpio_irq_t *obj) +{ +} + +/** Enable/disable pin IRQ event +* +* @param obj The GPIO object +* @param event The GPIO IRQ event +* @param enable The enable flag +*/ +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + //Clear state + obj->control->events &= (~event); + if (enable) { + //Reset if enabled + obj->control->events |= event; + } + + // Map enabled events to a value the reflects the ambiq hal/register values + am_hal_gpio_intdir_e ap3_int_dir = 0x00; + switch (obj->control->events) { + case IRQ_NONE: + ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_NONE; + break; + case IRQ_RISE: + ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_LO2HI; + break; + case IRQ_FALL: + ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_HI2LO; + break; + case (IRQ_RISE | IRQ_FALL): + ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_BOTH; + break; + } + + ap3_gpio_enable_interrupts(obj->control->pad, ap3_int_dir); +} + +/** Enable GPIO IRQ +* +* This is target dependent, as it might enable the entire port or just a pin +* @param obj The GPIO object +*/ +void gpio_irq_enable(gpio_irq_t *obj) +{ + am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(obj->control->pad)); + am_hal_gpio_interrupt_enable(AM_HAL_GPIO_BIT(obj->control->pad)); +} + +/** Disable GPIO IRQ +* +* This is target dependent, as it might disable the entire port or just a pin +* @param obj The GPIO object +*/ +void gpio_irq_disable(gpio_irq_t *obj) +{ + am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(obj->control->pad)); + am_hal_gpio_interrupt_disable(AM_HAL_GPIO_BIT(obj->control->pad)); +} + +/**@}*/ +uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, am_hal_gpio_intdir_e eIntDir) +{ + //GPConfigReg_t GPCfgMask = {.bit.INCFG = 1, .bit.INTD = 1}; + // uint32_t ap3_hal_gpio_pinconfig_partial(ui32Pin, bfGpioCfg, 0, uint8_t GPCfgMask, 0); + uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg; + bool bClearEnable = false; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (ui32Pin >= AM_HAL_GPIO_MAX_PADS) { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Initialize the PADREG accumulator variables. + // + ui32GPCfg = ui32Padreg = ui32AltPadCfg = 0; + + // + // Map the requested interrupt direction settings into the Apollo3 + // GPIOCFG register field, which is a 4-bit field: + // [INTD(1):OUTCFG(2):INCFG(1)]. + // Bit0 of eIntDir maps to GPIOCFG.INTD (b3). + // Bit1 of eIntDir maps to GPIOCFG.INCFG (b0). + // + ui32GPCfg |= (((eIntDir >> 0) & 0x1) << GPIOCFG_FLD_INTD_S) | (((eIntDir >> 1) & 0x1) << GPIOCFG_FLD_INCFG_S); + + // + // At this point, the configuration variable, ui32GpioCfg + // value is set (at bit position 0) and ready to write + // to their respective register bitfields. + // + uint32_t ui32GPCfgAddr; + uint32_t ui32GPCfgClearMask; + uint32_t ui32GPCfgShft; + + ui32GPCfgShft = ((ui32Pin & 0x7) << 2); + + ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3); + + ui32GPCfgClearMask = ~((uint32_t)0xF << ui32GPCfgShft); + + // + // Get the new values into their rightful bit positions. + // + ui32GPCfg <<= ui32GPCfgShft; + + AM_CRITICAL_BEGIN + + if (bClearEnable) { + // + // We're configuring a mode that requires clearing the Enable bit. + // + am_hal_gpio_output_tristate_disable(ui32Pin); + } + + GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key; + + // Here's where the magic happens + AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg; + + GPIO->PADKEY = 0; + + AM_CRITICAL_END + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_pinconfig() + +#ifdef __cplusplus +} +#endif +/** @}*/ +#endif //DEVICE_INTERRUPTIN diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/i2c_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/i2c_api.c new file mode 100644 index 0000000..669068d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/i2c_api.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if DEVICE_I2C + +#include "i2c_api.h" +#include "iom_api.h" +#include "PeripheralPins.h" +#include "mbed_assert.h" + +#define DEFAULT_CLK_FREQ (AM_HAL_IOM_400KHZ) + +static am_hal_iom_transfer_t xfer = {0}; + +I2CName i2c_get_peripheral_name(PinName sda, PinName scl) +{ + uint32_t iom_sda = pinmap_peripheral(sda, i2c_master_sda_pinmap()); + uint32_t iom_scl = pinmap_peripheral(scl, i2c_master_scl_pinmap()); + + uint32_t iom = pinmap_merge(iom_sda, iom_scl); + + if ((int)iom == NC) { + return IOM_NUM; + } + + return (I2CName)iom; +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + MBED_ASSERT(obj); + + // iom determination + I2CName iom = i2c_get_peripheral_name(sda, scl); + MBED_ASSERT((int)iom != IOM_NUM); + + // iom configuration + obj->i2c.iom_obj.iom.inst = (uint32_t)iom; + obj->i2c.iom_obj.iom.cfg.eInterfaceMode = AM_HAL_IOM_I2C_MODE; + obj->i2c.iom_obj.iom.cfg.ui32ClockFreq = DEFAULT_CLK_FREQ; + obj->i2c.iom_obj.iom.cfg.pNBTxnBuf = NULL; + obj->i2c.iom_obj.iom.cfg.ui32NBTxnBufLength = 0; + + // pin configuration + if ((int)sda != NC) { + pinmap_config(sda, i2c_master_sda_pinmap()); + } + if ((int)scl != NC) { + pinmap_config(scl, i2c_master_scl_pinmap()); + } + + // invariant xfer settings + xfer.ui32InstrLen = 0; + xfer.ui32Instr = 0; + xfer.ui8RepeatCount = 0; + xfer.ui8Priority = 1; + xfer.ui32PauseCondition = 0; + xfer.ui32StatusSetClr = 0; + + // initialization + iom_init(&obj->i2c.iom_obj); +} + +void i2c_free(i2c_t *obj) +{ + MBED_ASSERT(obj); + iom_deinit(&obj->i2c.iom_obj); +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + MBED_ASSERT(obj); + if (hz > AM_HAL_IOM_MAX_FREQ) { + hz = AM_HAL_IOM_MAX_FREQ; + } + obj->i2c.iom_obj.iom.cfg.ui32ClockFreq = hz; + iom_init(&obj->i2c.iom_obj); +} + +int i2c_start(i2c_t *obj) +{ + MBED_ASSERT(obj); + MBED_ASSERT(0); + return I2C_ERROR_NO_SLAVE; +} + +int i2c_stop(i2c_t *obj) +{ + MBED_ASSERT(obj); + MBED_ASSERT(0); + return I2C_ERROR_NO_SLAVE; +} + +int i2c_read(i2c_t *obj, int address8bit, char *data, int length, int stop) +{ + MBED_ASSERT(obj); + + int handled_chars = 0; + + xfer.uPeerInfo.ui32I2CDevAddr = (address8bit >> 1); + xfer.eDirection = AM_HAL_IOM_RX; + xfer.ui32NumBytes = length; + xfer.pui32RxBuffer = (uint32_t *)data; + xfer.pui32TxBuffer = NULL; + xfer.bContinue = (stop) ? false : true; + uint32_t status = am_hal_iom_blocking_transfer(obj->i2c.iom_obj.iom.handle, &xfer); + if (AM_HAL_STATUS_SUCCESS != status) { + return I2C_ERROR_NO_SLAVE; + } + handled_chars += xfer.ui32NumBytes; + + return handled_chars; +} + +int i2c_write(i2c_t *obj, int address8bit, const char *data, int length, int stop) +{ + MBED_ASSERT(obj); + + int handled_chars = 0; + + xfer.uPeerInfo.ui32I2CDevAddr = (address8bit >> 1); + xfer.eDirection = AM_HAL_IOM_TX; + xfer.ui32NumBytes = length; + xfer.pui32TxBuffer = (uint32_t *)data; + xfer.pui32RxBuffer = NULL; + xfer.bContinue = (stop) ? false : true; + uint32_t status = am_hal_iom_blocking_transfer(obj->i2c.iom_obj.iom.handle, &xfer); + if (AM_HAL_STATUS_SUCCESS != status) { + return I2C_ERROR_NO_SLAVE; + } + handled_chars += xfer.ui32NumBytes; + + return handled_chars; +} + +void i2c_reset(i2c_t *obj) +{ + MBED_ASSERT(obj); + MBED_ASSERT(0); +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + MBED_ASSERT(obj); + MBED_ASSERT(0); + return I2C_ERROR_NO_SLAVE; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + MBED_ASSERT(obj); + MBED_ASSERT(0); + return I2C_ERROR_NO_SLAVE; +} + +const PinMap *i2c_master_sda_pinmap(void) +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap(void) +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap(void) +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap(void) +{ + return PinMap_I2C_SCL; +} + +#endif // DEVICE_I2C diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.c new file mode 100644 index 0000000..bb86f37 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "iom_api.h" +#include "mbed_assert.h" + +void iom_init(iom_t *obj) +{ + MBED_ASSERT(obj); + + if (obj->iom.handle) { + iom_deinit(obj); + } + + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_initialize(obj->iom.inst, &obj->iom.handle)); + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_power_ctrl(obj->iom.handle, AM_HAL_SYSCTRL_WAKE, false)); + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_configure(obj->iom.handle, &obj->iom.cfg)); + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_enable(obj->iom.handle)); + + // this merely configures the internal peripheral - the desired pins still need to be configured +} + +void iom_deinit(iom_t *obj) +{ + MBED_ASSERT(obj); + + if (!obj->iom.handle) { + return; + } + + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_disable(obj->iom.handle)); + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_power_ctrl(obj->iom.handle, AM_HAL_SYSCTRL_DEEPSLEEP, false)); + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_uninitialize(obj->iom.handle)); + + obj->iom.handle = NULL; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.h new file mode 100644 index 0000000..d0bba0f --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_IOM_API_H +#define MBED_IOM_API_H + +#include "hal/dma_api.h" +#include "hal/buffer.h" + +#include "am_mcu_apollo.h" + +#include "objects_iom.h" + +/** Asynch IOM HAL structure + */ +typedef struct { + struct iom_s iom; /**< Target specific SPI structure */ + // struct buffer_s tx_buff; /**< Tx buffer */ + // struct buffer_s rx_buff; /**< Rx buffer */ +} iom_t; + +void iom_init(iom_t *obj); +void iom_deinit(iom_t *obj); + +#endif // MBED_IOM_API_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/isr.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/isr.c new file mode 100644 index 0000000..0558ab2 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/isr.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "am_mcu_apollo.h" +#include "lp_ticker_defines.h" +volatile bool someFlagThatGetSetinISR = false; + +void am_ctimer_isr(void) +{ + uint32_t ui32Status; + + // + // Check and clear any active CTIMER interrupts. + // + ui32Status = am_hal_ctimer_int_status_get(true); + am_hal_ctimer_int_clear(ui32Status); + // // + // // Run handlers for the various possible timer events. + // // + am_hal_ctimer_int_service(ui32Status); + + //am_hal_ctimer_int_service(am_hal_ctimer_int_status_get(true)); // get enabled interrupt status and then service those only +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker.c new file mode 100644 index 0000000..a285de7 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "lp_ticker_api.h" +#include "lp_ticker_defines.h" +#include "platform/mbed_critical.h" + +#if DEVICE_LPTICKER + +static bool lp_ticker_initialized = false; + +/* LP ticker is driven by 32kHz clock and counter length is 24 bits. */ +const ticker_info_t *lp_ticker_get_info() +{ + static const ticker_info_t info = { + LP_TICKER_FREQ, + LP_TICKER_BITS + }; + return &info; +} + +void lp_ticker_init(void) +{ + if (lp_ticker_initialized) { + lp_ticker_disable_interrupt(); + return; + } + am_hal_ctimer_int_register(LP_TICKER_AM_HAL_CTIMER_CMPR_INT, lp_ticker_irq_handler); + am_hal_ctimer_config_single(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER, + (LP_TICKER_AM_HAL_CTIMER_TIME_KEEPER_FN | LP_TICKER_AM_HAL_CTIMER_SRC)); + am_hal_ctimer_config_single(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER, + (LP_TICKER_AM_HAL_CTIMER_INT_COUNTER_FN | LP_TICKER_AM_HAL_CTIMER_SRC | AM_HAL_CTIMER_INT_ENABLE)); + am_hal_ctimer_int_enable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); + NVIC_EnableIRQ(CTIMER_IRQn); + am_hal_ctimer_start(LP_TICKER_AM_HAL_CTIMER_NUMBER, LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER); + lp_ticker_initialized = true; +} + +void lp_ticker_free(void) +{ + am_hal_ctimer_stop(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER); + + am_hal_ctimer_clear(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER); + lp_ticker_initialized = false; +} + +uint32_t lp_ticker_read() +{ + return am_hal_ctimer_read(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER); +} + +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + am_hal_ctimer_int_enable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); + am_hal_ctimer_clear(LP_TICKER_AM_HAL_CTIMER_NUMBER, LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER); + // am_hal_ctimer_config_single(LP_TICKER_AM_HAL_CTIMER_NUMBER, + // LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER, + // (LP_TICKER_AM_HAL_CTIMER_INT_COUNTER_FN | LP_TICKER_AM_HAL_CTIMER_SRC | AM_HAL_CTIMER_INT_ENABLE | CTIMER_CTRL0_TMRA0IE1_Msk)); + am_hal_ctimer_start(LP_TICKER_AM_HAL_CTIMER_NUMBER, LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER); + uint32_t delta = (uint32_t)timestamp - lp_ticker_read(); + am_hal_ctimer_compare_set(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER, + LP_TICKER_AM_HAL_CTIMER_CMPR_REG, + (uint32_t)delta); +} + +void lp_ticker_fire_interrupt(void) +{ + am_hal_ctimer_int_enable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); + am_hal_ctimer_int_set(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); +} + +void lp_ticker_disable_interrupt(void) +{ + am_hal_ctimer_int_disable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); +} + +void lp_ticker_clear_interrupt(void) +{ + am_hal_ctimer_int_clear(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); +} + +#endif // DEVICE_LPTICKER diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker_defines.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker_defines.h new file mode 100644 index 0000000..f46cf8a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker_defines.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +// #ifndef MBED_US_TICKER_DEFINES_H +// #define MBED_US_TICKER_DEFINES_H + +#include "am_mcu_apollo.h" + +#define LP_TICKER_FREQ 32768 +#define LP_TICKER_AM_HAL_CTIMER_SRC AM_HAL_CTIMER_XT_32_768KHZ + +#define LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER AM_HAL_CTIMER_TIMERA +#define LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER AM_HAL_CTIMER_TIMERB +#define LP_TICKER_AM_HAL_CTIMER_NUMBER 7 +#define LP_TICKER_AM_HAL_CTIMER_TIME_KEEPER_FN AM_HAL_CTIMER_FN_CONTINUOUS +#define LP_TICKER_AM_HAL_CTIMER_INT_COUNTER_FN AM_HAL_CTIMER_FN_ONCE +#define LP_TICKER_AM_HAL_CTIMER_CMPR_REG 0 // CMPR0 reg used with CTIMER_FN_CONTINUOUS mode +#define LP_TICKER_AM_HAL_CTIMER_CMPR_INT AM_HAL_CTIMER_INT_TIMERB7C0 +//#define LP_TICKER_AM_HAL_CTIMER_CMPR_INT1 AM_HAL_CTIMER_INT_TIMERA7C1 + +// Automatic configuration + +#if (LP_TICKER_AM_HAL_CTIMER_SEGMENT == AM_HAL_CTIMER_BOTH) +#define LP_TICKER_BITS 32 +#else +#define LP_TICKER_BITS 16 +#endif // (LP_TICKER_AM_HAL_CTIMER_SEGMENT == AM_HAL_CTIMER_BOTH) + +// #endif // MBED_US_TICKER_DEFINES_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/mbed_rtx.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/mbed_rtx.h new file mode 100644 index 0000000..6448395 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/mbed_rtx.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +/* This file is required, but doesn't actually need to do anything. */ + +#define INITIAL_SP MBED_RAM1_START + MBED_RAM1_SIZE - 8 + +#endif /* MBED_MBED_RTX_H */ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects.h new file mode 100644 index 0000000..f94c642 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// SPDX-License-Identifier: Apache-2.0 +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "am_mcu_apollo.h" +#include "am_bsp.h" +#include "am_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "objects_flash.h" +#include "objects_gpio.h" +#include "objects_uart.h" +#include "objects_iom.h" +#include "objects_spi.h" +#include "objects_i2c.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_flash.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_flash.h new file mode 100644 index 0000000..e9e2ccb --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_flash.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_FLASH_H +#define MBED_OBJECTS_FLASH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +struct flash_u { + uint32_t reserved; //No information needs to be passed to api right now +}; + +struct flash_s { + struct flash_u flash; +}; + +#ifdef __cplusplus +} +#endif + +#endif // MBED_OBJECTS_FLASH_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h new file mode 100644 index 0000000..67685c3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_GPIO_H +#define MBED_OBJECTS_GPIO_H + +#include "am_hal_gpio.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef uint32_t ap3_gpio_pad_t; + +typedef enum { + PIN_INPUT = 0x00, + PIN_OUTPUT, + + PIN_DIR_ELEMENTS +} PinDirection; + +enum sPinMode { + sPowerSwNone = 0x00, + sPowerSwVDD, + sPowerSwVSS, + sPullNone, + sPullUp, + sPullDown, + sPullUp1K5, + sPullUp6K, + sPullUp12K, + sPullUp24K, + sDriveStrength2mA, + sDriveStrength4mA, + sDriveStrength8mA, + sDriveStrength12mA, + sOutDisable, + sOutPushPull, + sOutOpenDrain, + sOutTristate, + sInAuto, + sInNone, + sInEnable, + sReadPin, + sReadZero, + + sPinModeElements +}; + +#define PinModeEntry(e) e = (1 << s##e) + +typedef enum { + PinModeEntry(PowerSwNone), + PinModeEntry(PowerSwVDD), + PinModeEntry(PowerSwVSS), + PowerSwDefault = PowerSwNone, + + PinModeEntry(PullNone), + PinModeEntry(PullUp), + PinModeEntry(PullDown), + PinModeEntry(PullUp1K5), + PinModeEntry(PullUp6K), + PinModeEntry(PullUp12K), + PinModeEntry(PullUp24K), + PullDefault = PullNone, + + PinModeEntry(DriveStrength2mA), + PinModeEntry(DriveStrength4mA), + PinModeEntry(DriveStrength8mA), + PinModeEntry(DriveStrength12mA), + DriveStrengthDefault = DriveStrength12mA, + + PinModeEntry(OutDisable), + PinModeEntry(OutPushPull), + PinModeEntry(OutOpenDrain), + PinModeEntry(OutTristate), + OutDefault = OutPushPull, + + PinModeEntry(InAuto), + PinModeEntry(InNone), + PinModeEntry(InEnable), + InDefault = InEnable, + + PinModeEntry(ReadPin), + PinModeEntry(ReadZero), + ReadDefault = ReadPin, + + PinModeEntry(PinModeElements) +} PinMode; + +typedef struct _gpio_t { + ap3_gpio_pad_t pad; + am_hal_gpio_pincfg_t cfg; +} gpio_t; + +typedef struct ap3_gpio_irq_control_t { + ap3_gpio_pad_t pad; + uint32_t id; + void *handler; + uint8_t events; +} ap3_gpio_irq_control_t; + +typedef struct gpio_irq_s { + ap3_gpio_irq_control_t *control; +} gpio_irq_s; + +#define AP3_PINCFG_FUNCSEL_GPIO 3 + +#define AP3_GPIO_MAX_PADS (50) +#define PADREG_FLD_76_S 6 +#define PADREG_FLD_FNSEL_S 3 +#define PADREG_FLD_DRVSTR_S 2 +#define PADREG_FLD_INPEN_S 1 +#define PADREG_FLD_PULLUP_S 0 + +#define GPIOCFG_FLD_INTD_S 3 +#define GPIOCFG_FLD_OUTCFG_S 1 +#define GPIOCFG_FLD_INCFG_S 0 + +#ifdef __cplusplus +} +#endif + +#endif // MBED_OBJECTS_GPIO_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_i2c.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_i2c.h new file mode 100644 index 0000000..2f3e073 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_i2c.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_I2C_H +#define MBED_OBJECTS_I2C_H + +#include "objects_iom.h" + +#if DEVICE_I2C_ASYNCH +struct i2c_s { + iom_t iom_obj; +}; +#else +struct i2c_u { + iom_t iom_obj; +}; +struct i2c_s { + struct i2c_u i2c; +}; +#endif // DEVICE_I2C_ASYNCH + +#endif // MBED_OBJECTS_I2C_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_iom.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_iom.h new file mode 100644 index 0000000..635cd7f --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_iom.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_IOM_H +#define MBED_OBJECTS_IOM_H + +#include "am_hal_iom.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +struct iom_s { + uint32_t inst; // IOM module instance + void *handle; // IOM handle + am_hal_iom_config_t cfg; // IOM configuration +}; + +#ifdef __cplusplus +} +#endif + +#endif // MBED_OBJECTS_IOM_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_spi.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_spi.h new file mode 100644 index 0000000..3cc8e17 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_spi.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_SPI_H +#define MBED_OBJECTS_SPI_H + +#include "iom_api.h" + +#if DEVICE_SPI_ASYNCH +struct spi_s { + iom_t iom_obj; +}; +#else +struct spi_u { + iom_t iom_obj; +}; +struct spi_s { + struct spi_u spi; +}; +#endif // DEVICE_SPI_ASYNCH + +#endif // MBED_OBJECTS_SPI_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_uart.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_uart.h new file mode 100644 index 0000000..576e6f2 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_uart.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_UART_H +#define MBED_OBJECTS_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef uint32_t ap3_uart_pad_t; +typedef uint32_t ap3_uart_inst_t; + +typedef struct _ap3_uart_pad_map_elem_t { + ap3_uart_pad_t pad; + uint8_t funcsel; +} ap3_uart_pad_map_elem_t; + +typedef struct _ap3_uart_control_t { + ap3_uart_inst_t inst; // UART module instance + void *handle; // UART handle + am_hal_uart_config_t cfg; // UART configuration + uint32_t serial_irq_id; +} ap3_uart_control_t; + +#if DEVICE_SERIAL_ASYNCH +struct serial_s { + ap3_uart_control_t *uart_control; +}; +#else +struct serial_u { + ap3_uart_control_t *uart_control; +}; +struct serial_s { + struct serial_u serial; +}; +#endif // DEVICE_SERIAL_ASYNCH + +#ifdef __cplusplus +} +#endif + +#endif // MBED_OBJECTS_UART_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/pinmap.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/pinmap.c new file mode 100644 index 0000000..9aa95f6 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/pinmap.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" + +#include "extensions.h" +#include "am_mcu_apollo.h" + +void pin_config(PinName pin, am_hal_gpio_pincfg_t pincfg) +{ + if (pin == (PinName)NC) { + return; + } + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_gpio_pinconfig(pin, pincfg)); +} + +void pinmap_config(PinName pin, const PinMap *map) +{ + // fully configure a pin by a pin map entry + if (pin == NC) { + return; + } + + am_hal_gpio_pincfg_t pincfg; + while (map->pin != NC) { + if (map->pin == pin) { + pincfg = *((am_hal_gpio_pincfg_t *)(map->function)); + pin_config(pin, pincfg); + return; + } + map++; + } + MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "could not pinmap_config", pin); +} + +void pin_function(PinName pin, int function) +{ + // am_hal_gpio_pincfg_t cfg = {0}; + // cfg.uFuncSel = function; + // am_hal_gpio_pinconfig((uint32_t)(pin), cfg); // apply configuration + +#define PADREG_FLD_FNSEL_S 3 + + uint32_t ui32Padreg; + uint32_t ui32Funcsel; + + MBED_ASSERT(pin < AM_HAL_GPIO_MAX_PADS); + + // + // Initialize the PADREG accumulator variables. + // + ui32Padreg = 0; + + // Get the requested function + ui32Funcsel = (uint32_t)function; + + ui32Padreg |= ui32Funcsel << PADREG_FLD_FNSEL_S; + + // + // At this point, the configuration variable ui32Padreg, + // values is set (at bit position 0) and ready to write + // to its respective register bitfields. + // + uint32_t ui32PadregAddr; + uint32_t ui32PadClearMask; + uint32_t ui32PadShft; + + ui32PadregAddr = AM_REGADDR(GPIO, PADREGA) + (pin & ~0x3); + + ui32PadShft = ((pin & 0x3) << 3); + ui32PadClearMask = ~((uint32_t)0x38 << ui32PadShft); + + // Get the new values into their rightful bit positions. + ui32Padreg <<= ui32PadShft; + + AM_CRITICAL_BEGIN + + GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key; + + AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) | ui32Padreg; + + GPIO->PADKEY = 0; + + AM_CRITICAL_END +} + +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(0); + // gpio_t obj = { + // .pad = (ap3_gpio_pad_t)pin, + // .cfg = {0}, + // }; + // gpio_mode(gpio_t * obj, PinMode mode) +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c new file mode 100644 index 0000000..83d23f3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if DEVICE_SERIAL + +#include "serial_api.h" + +#include "mbed_assert.h" +#include "PeripheralPins.h" + +// globals +int stdio_uart_inited = 0; +serial_t stdio_uart; +bool value = false; + +// interrupt variables +static uart_irq_handler irq_handler; +static ap3_uart_control_t ap3_uart_control[AM_REG_UART_NUM_MODULES]; + +// forward declarations +extern void am_uart_isr(void); +extern void am_uart1_isr(void); +void uart_configure_pin_function(PinName pin, UARTName uart, const PinMap *map); + +/** + * \defgroup hal_GeneralSerial Serial Configuration Functions + * + * # Defined behavior + * * ::serial_init initializes the ::serial_t + * * ::serial_init sets the default parameters for serial peripheral (9600 bps, 8N1 format) + * * ::serial_init configures the specified pins + * * ::serial_free releases the serial peripheral + * * ::serial_baud configures the baud rate + * * at least 9600 bps the baud rate must be supported + * * ::serial_format configures the transmission format (number of bits, parity and the number of stop bits) + * * at least 8N1 format must be supported + * * ::serial_irq_handler registers the interrupt handler which will be invoked when the interrupt fires. + * * ::serial_irq_set enables or disables the serial RX or TX IRQ. + * * If `RxIrq` is enabled by ::serial_irq_set, ::serial_irq_handler will be invoked whenever + * Receive Data Register Full IRQ is generated. + * * If `TxIrq` is enabled by ::serial_irq_set, ::serial_irq_handler will be invoked whenever + * Transmit Data Register Empty IRQ is generated. + * * If the interrupt condition holds true, when the interrupt is enabled with ::serial_irq_set, + * the ::serial_irq_handler is called instantly. + * * ::serial_getc returns the character from serial buffer. + * * ::serial_getc is a blocking call (waits for the character). + * * ::serial_putc sends a character. + * * ::serial_putc is a blocking call (waits for a peripheral to be available). + * * ::serial_readable returns non-zero value if a character can be read, 0 otherwise. + * * ::serial_writable returns non-zero value if a character can be written, 0 otherwise. + * * ::serial_clear clears the ::serial_t RX/TX buffers + * * ::serial_break_set sets the break signal. + * * ::serial_break_clear clears the break signal. + * * ::serial_pinout_tx configures the TX pin as an output (to be used in half-duplex mode). + * * ::serial_set_flow_control configures serial flow control. + * * ::serial_set_flow_control sets flow control in the hardware if a serial peripheral supports it, + * otherwise software emulation is used. + * * ::serial_tx_asynch starts the serial asynchronous transfer. + * * ::serial_tx_asynch writes `tx_length` bytes from the `tx` to the bus. + * * ::serial_tx_asynch must support 8 data bits + * * The callback given to ::serial_tx_asynch is invoked when the transfer completes. + * * ::serial_tx_asynch specifies the logical OR of events to be registered. + * * The ::serial_tx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm. + * * ::serial_rx_asynch starts the serial asynchronous transfer. + * * ::serial_rx_asynch reads `rx_length` bytes to the `rx` buffer. + * * ::serial_rx_asynch must support 8 data bits + * * The callback given to ::serial_rx_asynch is invoked when the transfer completes. + * * ::serial_rx_asynch specifies the logical OR of events to be registered. + * * The ::serial_rx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm. + * * ::serial_rx_asynch specifies a character in range 0-254 to be matched, 255 is a reserved value. + * * If SERIAL_EVENT_RX_CHARACTER_MATCH event is not registered, the `char_match` is ignored. + * * The SERIAL_EVENT_RX_CHARACTER_MATCH event is set in the callback when SERIAL_EVENT_RX_CHARACTER_MATCH event is + * registered AND `char_match` is present in the received data. + * * ::serial_tx_active returns non-zero if the TX transaction is ongoing, 0 otherwise. + * * ::serial_rx_active returns non-zero if the RX transaction is ongoing, 0 otherwise. + * * ::serial_irq_handler_asynch returns event flags if a transfer termination condition was met, otherwise returns 0. + * * ::serial_irq_handler_asynch takes no longer than one packet transfer time (packet_bits / baudrate) to execute. + * * ::serial_tx_abort_asynch aborts the ongoing TX transaction. + * * ::serial_tx_abort_asynch disables the enabled interupt for TX. + * * ::serial_tx_abort_asynch flushes the TX hardware buffer if TX FIFO is used. + * * ::serial_rx_abort_asynch aborts the ongoing RX transaction. + * * ::serial_rx_abort_asynch disables the enabled interupt for RX. + * * ::serial_rx_abort_asynch flushes the TX hardware buffer if RX FIFO is used. + * * Correct operation guaranteed when interrupt latency is shorter than one packet transfer time (packet_bits / baudrate) + * if the flow control is not used. + * * Correct operation guaranteed regardless of interrupt latency if the flow control is used. + * + * # Undefined behavior + * * Calling ::serial_init multiple times on the same `serial_t` without ::serial_free. + * * Passing invalid pin to ::serial_init, ::serial_pinout_tx. + * * Calling any function other than ::serial_init on am uninitialized or freed `serial_t`. + * * Passing an invalid pointer as `obj` to any function. + * * Passing an invalid pointer as `handler` to ::serial_irq_handler, ::serial_tx_asynch, ::serial_rx_asynch. + * * Calling ::serial_tx_abort while no async TX transfer is being processed. + * * Calling ::serial_rx_abort while no async RX transfer is being processed. + * * Devices behavior is undefined when the interrupt latency is longer than one packet transfer time + * (packet_bits / baudrate) if the flow control is not used. + * @{ + */ + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, serial_tx_pinmap()); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, serial_rx_pinmap()); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart != NC); + obj->serial.uart_control = &ap3_uart_control[uart]; + obj->serial.uart_control->inst = uart; + + // config uart pins + pinmap_config(tx, serial_tx_pinmap()); + pinmap_config(rx, serial_rx_pinmap()); + + if (!obj->serial.uart_control->handle) { + // if handle uninitialized this is first time set up + // ensure that HAL queueing is disabled (we want to use the FIFOs directly) + obj->serial.uart_control->cfg.pui8RxBuffer = NULL; + obj->serial.uart_control->cfg.pui8TxBuffer = NULL; + obj->serial.uart_control->cfg.ui32RxBufferSize = 0; + obj->serial.uart_control->cfg.ui32TxBufferSize = 0; + + obj->serial.uart_control->cfg.ui32FifoLevels = AM_HAL_UART_RX_FIFO_7_8; + + // start UART instance + MBED_ASSERT(am_hal_uart_initialize(uart, &(obj->serial.uart_control->handle)) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_uart_power_control(obj->serial.uart_control->handle, AM_HAL_SYSCTRL_WAKE, false) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_uart_configure_fifo(obj->serial.uart_control->handle, &(obj->serial.uart_control->cfg), false) == AM_HAL_STATUS_SUCCESS); + + // set default format + serial_format(obj, 8, ParityNone, 1); + } +} + +void serial_free(serial_t *obj) +{ + // nothing to do unless resources are allocated for members of the serial_s serial member of obj + // assuming mbed handles obj and its members +} + +void serial_baud(serial_t *obj, int baudrate) +{ + obj->serial.uart_control->cfg.ui32BaudRate = (uint32_t)baudrate; + MBED_ASSERT(am_hal_uart_configure_fifo(obj->serial.uart_control->handle, &(obj->serial.uart_control->cfg), false) == AM_HAL_STATUS_SUCCESS); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + uint32_t am_hal_data_bits = 0; + switch (data_bits) { + case 5: + am_hal_data_bits = AM_HAL_UART_DATA_BITS_5; + break; + case 6: + am_hal_data_bits = AM_HAL_UART_DATA_BITS_6; + break; + case 7: + am_hal_data_bits = AM_HAL_UART_DATA_BITS_7; + break; + case 8: + am_hal_data_bits = AM_HAL_UART_DATA_BITS_8; + break; + default: + MBED_ASSERT(0); + break; + } + + uint32_t am_hal_parity = AM_HAL_UART_PARITY_NONE; + switch (parity) { + case ParityNone: + am_hal_parity = AM_HAL_UART_PARITY_NONE; + break; + case ParityOdd: + am_hal_parity = AM_HAL_UART_PARITY_ODD; + break; + case ParityEven: + am_hal_parity = AM_HAL_UART_PARITY_EVEN; + break; + default: // fall-through intentional after default + case ParityForced1: + case ParityForced0: + MBED_ASSERT(0); + break; + } + + uint32_t am_hal_stop_bits = 0; + switch (stop_bits) { + case 1: + am_hal_stop_bits = AM_HAL_UART_ONE_STOP_BIT; + break; + case 2: + am_hal_stop_bits = AM_HAL_UART_TWO_STOP_BITS; + break; + default: + MBED_ASSERT(0); + } + + obj->serial.uart_control->cfg.ui32DataBits = (uint32_t)am_hal_data_bits; + obj->serial.uart_control->cfg.ui32Parity = (uint32_t)am_hal_parity; + obj->serial.uart_control->cfg.ui32StopBits = (uint32_t)am_hal_stop_bits; + MBED_ASSERT(am_hal_uart_configure_fifo(obj->serial.uart_control->handle, &(obj->serial.uart_control->cfg), false) == AM_HAL_STATUS_SUCCESS); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + obj->serial.uart_control->serial_irq_id = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + MBED_ASSERT(obj->serial.uart_control->handle != NULL); + if (enable) { + switch (irq) { + case RxIrq: + MBED_ASSERT(am_hal_uart_interrupt_enable(obj->serial.uart_control->handle, AM_HAL_UART_INT_RX) == AM_HAL_STATUS_SUCCESS); + break; + case TxIrq: + MBED_ASSERT(am_hal_uart_interrupt_enable(obj->serial.uart_control->handle, AM_HAL_UART_INT_TXCMP) == AM_HAL_STATUS_SUCCESS); + break; + default: + break; + } + // NVIC_SetVector(uart_irqs[obj->serial.index], vector); + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + obj->serial.uart_control->inst)); + } else { // disable + switch (irq) { + case RxIrq: + MBED_ASSERT(am_hal_uart_interrupt_disable(obj->serial.uart_control->handle, AM_HAL_UART_INT_RX) == AM_HAL_STATUS_SUCCESS); + break; + case TxIrq: + MBED_ASSERT(am_hal_uart_interrupt_disable(obj->serial.uart_control->handle, AM_HAL_UART_INT_TXCMP) == AM_HAL_STATUS_SUCCESS); + break; + default: + break; + } + } +} + +int serial_getc(serial_t *obj) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + + uint8_t rx_c = 0x00; + volatile uint32_t bytes_read = 0x00; + am_hal_uart_transfer_t am_hal_uart_xfer_read_single = { + .ui32Direction = AM_HAL_UART_READ, + .pui8Data = (uint8_t *) &rx_c, + .ui32NumBytes = 1, + .ui32TimeoutMs = 0, + .pui32BytesTransferred = (uint32_t *) &bytes_read, + }; + + do { + am_hal_uart_transfer(obj->serial.uart_control->handle, &am_hal_uart_xfer_read_single); + } while (bytes_read == 0); + + return (int)rx_c; +} + +void serial_putc(serial_t *obj, int c) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + + volatile uint32_t bytes_sent = 0; + am_hal_uart_transfer_t am_hal_uart_xfer_write_single = { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *)(&c), + .ui32NumBytes = 1, + .ui32TimeoutMs = 0, + .pui32BytesTransferred = (uint32_t *) &bytes_sent, + }; + + do { + am_hal_uart_transfer(obj->serial.uart_control->handle, &am_hal_uart_xfer_write_single); + } while (bytes_sent == 0); +} + +int serial_readable(serial_t *obj) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + return !(UARTn(obj->serial.uart_control->inst)->FR_b.RXFE); +} + +int serial_writable(serial_t *obj) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + return !(UARTn(obj->serial.uart_control->inst)->FR_b.TXFF); +} + +void serial_clear(serial_t *obj) +{ + // todo: + MBED_ASSERT(0); +} + +void serial_break_set(serial_t *obj) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + UARTn(obj->serial.uart_control->inst)->LCRH |= UART0_LCRH_BRK_Msk; +} + +void serial_break_clear(serial_t *obj) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + UARTn(obj->serial.uart_control->inst)->LCRH &= ~UART0_LCRH_BRK_Msk; +} + +void serial_pinout_tx(PinName tx) +{ + // todo: vestigial? + MBED_ASSERT(0); +} + +#if DEVICE_SERIAL_FC + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + // todo: + MBED_ASSERT(0); +} + +void serial_set_flow_control_direct(serial_t *obj, FlowControl type, const serial_fc_pinmap_t *pinmap) +{ + // todo: + MBED_ASSERT(0); +} +#endif + +const PinMap *serial_tx_pinmap(void) +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap(void) +{ + return PinMap_UART_RX; +} + +#if DEVICE_SERIAL_FC + +const PinMap *serial_cts_pinmap(void) +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap(void) +{ + return PinMap_UART_RTS; +} +#endif + +static inline void uart_irq(uint32_t instance) +{ + void *handle = ap3_uart_control[instance].handle; + MBED_ASSERT(handle != NULL); + + // check flags + uint32_t status = 0x00; + MBED_ASSERT(am_hal_uart_interrupt_status_get(handle, &status, true) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_uart_interrupt_clear(handle, status) == AM_HAL_STATUS_SUCCESS); + + if (ap3_uart_control[instance].serial_irq_id != 0) { + if (status & AM_HAL_UART_INT_TXCMP) { // for transmit complete + if (irq_handler) { + irq_handler(ap3_uart_control[instance].serial_irq_id, TxIrq); + } + } + if (status & AM_HAL_UART_INT_RX) { // for receive complete + if (irq_handler) { + irq_handler(ap3_uart_control[instance].serial_irq_id, RxIrq); + } + } + } +} + +extern void am_uart_isr(void) +{ + uart_irq(UART_0); +} + +extern void am_uart1_isr(void) +{ + uart_irq(UART_1); +} + +#ifdef __cplusplus +} +#endif + +#endif + +/** @}*/ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/spi_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/spi_api.c new file mode 100644 index 0000000..fb44cbd --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/spi_api.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if DEVICE_SPI + +#include "spi_api.h" +#include "iom_api.h" +#include "PeripheralPins.h" +#include "mbed_assert.h" + +#include + +#define DEFAULT_CLK_FREQ (4000000) +#define DEFAULT_SPI_MODE (AM_HAL_IOM_SPI_MODE_0) + +static am_hal_iom_transfer_t xfer = {0}; + +SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) +{ + uint32_t iom_mosi = pinmap_peripheral(mosi, spi_master_mosi_pinmap()); + uint32_t iom_miso = pinmap_peripheral(miso, spi_master_miso_pinmap()); + uint32_t iom_sclk = pinmap_peripheral(sclk, spi_master_clk_pinmap()); + + uint32_t iom; + + if (miso == NC) { + iom = pinmap_merge(iom_mosi, iom_sclk); + } else if (mosi == NC) { + iom = pinmap_merge(iom_miso, iom_sclk); + } else { + uint32_t iom_data = pinmap_merge(iom_mosi, iom_miso); + iom = pinmap_merge(iom_data, iom_sclk); + } + + if ((int)iom == NC) { + return IOM_NUM; + } + + return (SPIName)iom; +} + +void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap) +{ + MBED_ASSERT(cap); + + SPIName iom_ssel = (SPIName)pinmap_peripheral(ssel, spi_master_cs_pinmap()); + + cap->minimum_frequency = 0; + cap->maximum_frequency = AM_HAL_IOM_MAX_FREQ; + cap->word_length = 0x00000080; + cap->slave_delay_between_symbols_ns = 0; + cap->clk_modes = 0x0F; + cap->support_slave_mode = (iom_ssel == IOM_ANY) ? true : false; + cap->hw_cs_handle = false; + cap->async_mode = false; + cap->tx_rx_buffers_equal_length = false; +} + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + MBED_ASSERT(obj); + + MBED_ASSERT((int)ssel == NC); + + // iom determination + SPIName iom = spi_get_peripheral_name(mosi, miso, sclk); + MBED_ASSERT((int)iom != IOM_NUM); + MBED_ASSERT((int)iom != IOM_ANY); + + // iom configuration + obj->spi.iom_obj.iom.inst = (uint32_t)iom; + obj->spi.iom_obj.iom.cfg.eInterfaceMode = AM_HAL_IOM_SPI_MODE; + obj->spi.iom_obj.iom.cfg.ui32ClockFreq = DEFAULT_CLK_FREQ; + obj->spi.iom_obj.iom.cfg.eSpiMode = DEFAULT_SPI_MODE; + obj->spi.iom_obj.iom.cfg.pNBTxnBuf = NULL; + obj->spi.iom_obj.iom.cfg.ui32NBTxnBufLength = 0; + + // invariant xfer settings + xfer.ui32InstrLen = 0; + xfer.ui32Instr = 0; + xfer.bContinue = false; + xfer.ui8RepeatCount = 0; + xfer.ui8Priority = 1; + xfer.ui32PauseCondition = 0; + xfer.ui32StatusSetClr = 0; + + // pin configuration + pinmap_config(sclk, spi_master_clk_pinmap()); + if ((int)mosi != NC) { + pinmap_config(mosi, spi_master_mosi_pinmap()); + } + if ((int)miso != NC) { + pinmap_config(miso, spi_master_miso_pinmap()); + } + if ((int)ssel != NC) { + pinmap_config(ssel, spi_master_cs_pinmap()); + } + + // initialization + iom_init(&obj->spi.iom_obj); +} + +void spi_free(spi_t *obj) +{ + iom_deinit(&obj->spi.iom_obj); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + MBED_ASSERT(obj); + obj->spi.iom_obj.iom.cfg.eSpiMode = (am_hal_iom_spi_mode_e)mode; + iom_init(&obj->spi.iom_obj); +} + +void spi_frequency(spi_t *obj, int hz) +{ + MBED_ASSERT(obj); + obj->spi.iom_obj.iom.cfg.ui32ClockFreq = (uint32_t)hz; + iom_init(&obj->spi.iom_obj); +} + +int spi_master_write(spi_t *obj, int value) +{ + uint32_t rxval = 0; + spi_master_block_write(obj, (const char *)&value, 1, (char *)&rxval, 1, 0x00); + return rxval; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + MBED_ASSERT(obj); + + int chars_handled = 0; + + // perform a duplex xfer for the smaller of the two buffers + xfer.eDirection = AM_HAL_IOM_FULLDUPLEX; + xfer.ui32NumBytes = (tx_length > rx_length) ? rx_length : tx_length; + xfer.pui32RxBuffer = (uint32_t *)rx_buffer; + xfer.pui32TxBuffer = (uint32_t *)tx_buffer; + + if (xfer.ui32NumBytes) { + uint32_t status = am_hal_iom_spi_blocking_fullduplex(obj->spi.iom_obj.iom.handle, &xfer); + if (AM_HAL_STATUS_SUCCESS != status) { + return 0; + } + chars_handled += xfer.ui32NumBytes; + } + + // handle difference between buffers + if (tx_length != rx_length) { + bool Rw = (rx_length >= tx_length); + + // set up common config + xfer.eDirection = (Rw) ? AM_HAL_IOM_RX : AM_HAL_IOM_TX; + xfer.ui32NumBytes = (Rw) ? (rx_length - tx_length) : (tx_length - rx_length); + xfer.pui32RxBuffer = (Rw) ? (uint32_t *)(rx_buffer + chars_handled) : NULL; + xfer.pui32TxBuffer = (Rw) ? NULL : (uint32_t *)(tx_buffer + chars_handled); + + uint32_t status = AM_HAL_STATUS_SUCCESS; + if (!Rw || (write_fill == 0x00)) { + // when transmitting (w) or reading with a zero fill just use a simplex transfer + status = am_hal_iom_blocking_transfer(obj->spi.iom_obj.iom.handle, &xfer); + if (AM_HAL_STATUS_SUCCESS != status) { + return chars_handled; + } + chars_handled += xfer.ui32NumBytes; + } else { + // when reading with a nonzero fill use a duplex transfer + uint8_t fill[xfer.ui32NumBytes]; + memset(fill, write_fill, xfer.ui32NumBytes); + xfer.eDirection = AM_HAL_IOM_FULLDUPLEX; + xfer.pui32TxBuffer = (uint32_t *)&fill; + uint32_t status = am_hal_iom_spi_blocking_fullduplex(obj->spi.iom_obj.iom.handle, &xfer); + if (AM_HAL_STATUS_SUCCESS != status) { + return chars_handled; + } + chars_handled += xfer.ui32NumBytes; + } + } + + return chars_handled; +} + +int spi_slave_receive(spi_t *obj) +{ + MBED_ASSERT(0); + return 0; +} + +int spi_slave_read(spi_t *obj) +{ + MBED_ASSERT(0); + return 0; +} + +void spi_slave_write(spi_t *obj, int value) +{ + MBED_ASSERT(0); +} + +int spi_busy(spi_t *obj) +{ + MBED_ASSERT(0); + return 0; +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +#endif // DEVICE_SPI diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker.c new file mode 100644 index 0000000..9c962b2 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "us_ticker_api.h" +#include +/** + * \defgroup hal_us_ticker Microsecond Ticker + * Low level interface to the microsecond ticker of a target + * + * # Defined behavior + * * Has a reported frequency between 250KHz and 8MHz for counters which are less than 32 bits wide - Verified by test ::us_ticker_info_test + * * Has a reported frequency up to 100MHz for counters which are 32 bits wide - Verified by test ::us_ticker_info_test + * * Has a counter that is at least 16 bits wide - Verified by test ::us_ticker_info_test + * * All behavior defined by the @ref hal_ticker_shared "ticker specification" + * + * # Undefined behavior + * * See the @ref hal_ticker_shared "ticker specification" + * + * @see hal_us_ticker_tests + * + * # Compile-time optimization macros + * + + * @{ + */ + +/** + * \defgroup hal_us_ticker_tests Microsecond Ticker tests + * Tests to validate the proper implementation of the microsecond ticker + * + * To run the microsecond ticker hal tests use the command: + * + * mbed test -t -m -n tests-mbed_hal-common_ticker*,tests-mbed_hal-us_ticker* + * + * @see hal_ticker_tests + * + */ +/* HAL us ticker */ + +static bool us_ticker_initialized = false; + +/** Initialize the ticker + * + * Initialize or re-initialize the ticker. This resets all the + * clocking and prescaler registers, along with disabling + * the compare interrupt. + * + * @note Initialization properties tested by ::ticker_init_test + * + */ +void us_ticker_init(void) +{ + if (us_ticker_initialized) { + am_hal_stimer_int_disable(US_TICKER_STIMER_INT_COMPARE); + return; + } + + NVIC_SetVector(STIMER_CMPR0_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(STIMER_CMPR0_IRQn); + am_hal_stimer_config(AM_HAL_STIMER_CFG_CLEAR | AM_HAL_STIMER_CFG_FREEZE); + am_hal_stimer_config(US_TICKER_FREQ); + us_ticker_initialized = true; +} + +/** Deinitialize the us ticker + * + * Powerdown the us ticker in preparation for sleep, powerdown, or reset. + * + * After this function is called, no other ticker functions should be called + * except us_ticker_init(), calling any function other than init is undefined. + * + * @note This function stops the ticker from counting. + * + */ +void us_ticker_free(void) +{ + am_hal_stimer_config(AM_HAL_STIMER_CFG_FREEZE); + am_hal_stimer_int_disable(US_TICKER_STIMER_INT_COMPARE); + us_ticker_initialized = false; +} + +/** Read the current counter + * + * Read the current counter value without performing frequency conversions. + * If no rollover has occurred, the seconds passed since us_ticker_init() + * was called can be found by dividing the ticks returned by this function + * by the frequency returned by ::us_ticker_get_info. + * + * @return The current timer's counter value in ticks + * + */ +uint32_t us_ticker_read(void) +{ + return am_hal_stimer_counter_get(); +} + +/** Set interrupt for specified timestamp + * + * @param timestamp The time in ticks to be set + * + * @note no special handling needs to be done for times in the past + * as the common timer code will detect this and call + * us_ticker_fire_interrupt() if this is the case + * + * @note calling this function with timestamp of more than the supported + * number of bits returned by ::us_ticker_get_info results in undefined + * behavior. + * + */ +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + + uint32_t instance = 0; + switch (US_TICKER_STIMER_INT_COMPARE) { + default: + case AM_HAL_STIMER_INT_COMPAREA: + instance = 0; + break; + case AM_HAL_STIMER_INT_COMPAREB: + instance = 1; + break; + case AM_HAL_STIMER_INT_COMPAREC: + instance = 2; + break; + case AM_HAL_STIMER_INT_COMPARED: + instance = 3; + break; + case AM_HAL_STIMER_INT_COMPAREE: + instance = 4; + break; + case AM_HAL_STIMER_INT_COMPAREF: + instance = 5; + break; + case AM_HAL_STIMER_INT_COMPAREG: + instance = 6; + break; + case AM_HAL_STIMER_INT_COMPAREH: + instance = 7; + break; + } + + am_hal_stimer_int_enable(US_TICKER_STIMER_INT_COMPARE); + timestamp_t now = (timestamp_t)am_hal_stimer_counter_get(); + am_hal_stimer_compare_delta_set(instance, (timestamp - now)); + CTIMER->STCFG |= (AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << instance); +} + +/** Disable us ticker interrupt + * + */ +void us_ticker_disable_interrupt(void) +{ + am_hal_stimer_int_disable(US_TICKER_STIMER_INT_COMPARE); +} + +/** Clear us ticker interrupt + * + */ +void us_ticker_clear_interrupt(void) +{ + am_hal_stimer_int_clear(US_TICKER_STIMER_INT_COMPARE); +} + +/** Set pending interrupt that should be fired right away. + * + * The ticker should be initialized prior calling this function. + * + */ +void us_ticker_fire_interrupt(void) +{ + am_hal_stimer_int_enable(US_TICKER_STIMER_INT_COMPARE); + am_hal_stimer_int_set(US_TICKER_STIMER_INT_COMPARE); +} + +/** Get frequency and counter bits of this ticker.*/ +const ticker_info_t *us_ticker_get_info(void) +{ + static const ticker_info_t info = { + 3000000, // 3 MHz + 32 // 32 bit counter + }; + return &info; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker_defines.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker_defines.h new file mode 100644 index 0000000..45a4f4e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker_defines.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_US_TICKER_DEFINES_H +#define MBED_US_TICKER_DEFINES_H + +// * US_TICKER_PERIOD_NUM, US_TICKER_PERIOD_DEN: These denote the ratio (numerator, denominator) +// * of the ticker period to a microsecond. For example, an 8MHz ticker would have NUM = 1, DEN = 8; +// * a 1MHz ticker would have NUM = 1, DEN = 1; a 250kHz ticker would have NUM = 4, DEN = 1. +// * Both numerator and denominator must be 16 bits or less. +#define US_TICKER_FREQ AM_HAL_STIMER_HFRC_3MHZ +#define US_TICKER_PERIOD_NUM 1 +#define US_TICKER_PERIOD_DEN 3 + +// * +// * US_TICKER_MASK: The value mask for the ticker - eg 0x07FFFFFF for a 27-bit ticker. +// * +#define US_TICKER_MASK 0xFFFFFFFF + +#define US_TICKER_COMPARE_INSTANCE A +#define US_TICKER_STIMER_INT_COMPARE_CONCATENATOR(a, b) a##b +#define US_TICKER_STIMER_INT_COMPARE_EVALUATOR(a, b) US_TICKER_STIMER_INT_COMPARE_CONCATENATOR(a, b) +#define US_TICKER_STIMER_INT_COMPARE US_TICKER_STIMER_INT_COMPARE_EVALUATOR(AM_HAL_STIMER_INT_COMPARE, US_TICKER_COMPARE_INSTANCE) + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/ARM/Lib/ARM/libarm_cortexM4lf_math.a b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/ARM/Lib/ARM/libarm_cortexM4lf_math.a new file mode 100644 index 0000000..66efc87 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/ARM/Lib/ARM/libarm_cortexM4lf_math.a Binary files differ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/apollo3.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/apollo3.h new file mode 100644 index 0000000..a6aab00 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/apollo3.h @@ -0,0 +1,23505 @@ +/* + * Copyright (c) 2019, Ambiq Micro + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * Third party software included in this distribution is subject to the + * additional license terms as defined in the /docs/licenses directory. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * @file apollo3.h + * @brief CMSIS HeaderFile + * @version 1.0 + * @date 13. January 2020 + * @note Generated by SVDConv V3.3.27 on Monday, 13.01.2020 14:44:43 + * from File './apollo3.svd', + * last modified on Monday, 13.01.2020 20:44:43 + */ +// SPDX-License-Identifier: BSD-3-Clause + + +/** @addtogroup Ambiq Micro + * @{ + */ + + +/** @addtogroup apollo3 + * @{ + */ + + +#ifndef APOLLO3_H +#define APOLLO3_H + +#ifdef OVERFLOW +#define OVERFLOW_RESTORE OVERFLOW +#undef OVERFLOW +#endif // OVERFLOW + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== apollo3 Specific Interrupt Numbers =========================================== */ + BROWNOUT_IRQn = 0, /*!< 0 BROWNOUT */ + WDT_IRQn = 1, /*!< 1 WDT */ + RTC_IRQn = 2, /*!< 2 RTC */ + VCOMP_IRQn = 3, /*!< 3 VCOMP */ + IOSLAVE_IRQn = 4, /*!< 4 IOSLAVE */ + IOSLAVEACC_IRQn = 5, /*!< 5 IOSLAVEACC */ + IOMSTR0_IRQn = 6, /*!< 6 IOMSTR0 */ + IOMSTR1_IRQn = 7, /*!< 7 IOMSTR1 */ + IOMSTR2_IRQn = 8, /*!< 8 IOMSTR2 */ + IOMSTR3_IRQn = 9, /*!< 9 IOMSTR3 */ + IOMSTR4_IRQn = 10, /*!< 10 IOMSTR4 */ + IOMSTR5_IRQn = 11, /*!< 11 IOMSTR5 */ + BLE_IRQn = 12, /*!< 12 BLE */ + GPIO_IRQn = 13, /*!< 13 GPIO */ + CTIMER_IRQn = 14, /*!< 14 CTIMER */ + UART0_IRQn = 15, /*!< 15 UART0 */ + UART1_IRQn = 16, /*!< 16 UART1 */ + SCARD_IRQn = 17, /*!< 17 SCARD */ + ADC_IRQn = 18, /*!< 18 ADC */ + PDM_IRQn = 19, /*!< 19 PDM */ + MSPI0_IRQn = 20, /*!< 20 MSPI0 */ + STIMER_IRQn = 22, /*!< 22 STIMER */ + STIMER_CMPR0_IRQn = 23, /*!< 23 STIMER_CMPR0 */ + STIMER_CMPR1_IRQn = 24, /*!< 24 STIMER_CMPR1 */ + STIMER_CMPR2_IRQn = 25, /*!< 25 STIMER_CMPR2 */ + STIMER_CMPR3_IRQn = 26, /*!< 26 STIMER_CMPR3 */ + STIMER_CMPR4_IRQn = 27, /*!< 27 STIMER_CMPR4 */ + STIMER_CMPR5_IRQn = 28, /*!< 28 STIMER_CMPR5 */ + STIMER_CMPR6_IRQn = 29, /*!< 29 STIMER_CMPR6 */ + STIMER_CMPR7_IRQn = 30, /*!< 30 STIMER_CMPR7 */ + CLKGEN_IRQn = 31 /*!< 31 CLKGEN */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0100U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_apollo3.h" /*!< apollo3 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog Digital Converter Control (ADC) + */ + +typedef struct { /*!< (@ 0x50010000) ADC Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t ADCEN : 1; /*!< [0..0] This bit enables the ADC module. While the ADC is enabled, + the ADCCFG and SLOT Configuration regsiter settings must + remain stable and unchanged. All configuration register + settings, slot configuration settings and window comparison + settings should be written prior to setting the ADCEN bit + to '1'. */ + uint32_t : 1; + __IOM uint32_t RPTEN : 1; /*!< [2..2] This bit enables Repeating Scan Mode. */ + __IOM uint32_t LPMODE : 1; /*!< [3..3] Select power mode to enter between active scans. */ + __IOM uint32_t CKMODE : 1; /*!< [4..4] Clock mode register */ + uint32_t : 3; + __IOM uint32_t REFSEL : 2; /*!< [9..8] Select the ADC reference voltage. */ + uint32_t : 2; + __IOM uint32_t DFIFORDEN : 1; /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable + FIFO pop upon reading the FIFOPR register. */ + uint32_t : 3; + __IOM uint32_t TRIGSEL : 3; /*!< [18..16] Select the ADC trigger source. */ + __IOM uint32_t TRIGPOL : 1; /*!< [19..19] This bit selects the ADC trigger polarity for external + off chip triggers. */ + uint32_t : 4; + __IOM uint32_t CLKSEL : 2; /*!< [25..24] Select the source and frequency for the ADC clock. + All values not enumerated below are undefined. */ + } CFG_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) ADC Power Status */ + + struct { + __IOM uint32_t PWDSTAT : 1; /*!< [0..0] Indicates the power-status of the ADC. */ + } STAT_b; + } ; + + union { + __IOM uint32_t SWT; /*!< (@ 0x00000008) Software trigger */ + + struct { + __IOM uint32_t SWT : 8; /*!< [7..0] Writing 0x37 to this register generates a software trigger. */ + } SWT_b; + } ; + + union { + __IOM uint32_t SL0CFG; /*!< (@ 0x0000000C) Slot 0 Configuration Register */ + + struct { + __IOM uint32_t SLEN0 : 1; /*!< [0..0] This bit enables slot 0 for ADC conversions. */ + __IOM uint32_t WCEN0 : 1; /*!< [1..1] This bit enables the window compare function for slot + 0. */ + uint32_t : 6; + __IOM uint32_t CHSEL0 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE0 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL0 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL0CFG_b; + } ; + + union { + __IOM uint32_t SL1CFG; /*!< (@ 0x00000010) Slot 1 Configuration Register */ + + struct { + __IOM uint32_t SLEN1 : 1; /*!< [0..0] This bit enables slot 1 for ADC conversions. */ + __IOM uint32_t WCEN1 : 1; /*!< [1..1] This bit enables the window compare function for slot + 1. */ + uint32_t : 6; + __IOM uint32_t CHSEL1 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE1 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL1 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL1CFG_b; + } ; + + union { + __IOM uint32_t SL2CFG; /*!< (@ 0x00000014) Slot 2 Configuration Register */ + + struct { + __IOM uint32_t SLEN2 : 1; /*!< [0..0] This bit enables slot 2 for ADC conversions. */ + __IOM uint32_t WCEN2 : 1; /*!< [1..1] This bit enables the window compare function for slot + 2. */ + uint32_t : 6; + __IOM uint32_t CHSEL2 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE2 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL2 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL2CFG_b; + } ; + + union { + __IOM uint32_t SL3CFG; /*!< (@ 0x00000018) Slot 3 Configuration Register */ + + struct { + __IOM uint32_t SLEN3 : 1; /*!< [0..0] This bit enables slot 3 for ADC conversions. */ + __IOM uint32_t WCEN3 : 1; /*!< [1..1] This bit enables the window compare function for slot + 3. */ + uint32_t : 6; + __IOM uint32_t CHSEL3 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE3 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL3 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL3CFG_b; + } ; + + union { + __IOM uint32_t SL4CFG; /*!< (@ 0x0000001C) Slot 4 Configuration Register */ + + struct { + __IOM uint32_t SLEN4 : 1; /*!< [0..0] This bit enables slot 4 for ADC conversions. */ + __IOM uint32_t WCEN4 : 1; /*!< [1..1] This bit enables the window compare function for slot + 4. */ + uint32_t : 6; + __IOM uint32_t CHSEL4 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE4 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL4 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL4CFG_b; + } ; + + union { + __IOM uint32_t SL5CFG; /*!< (@ 0x00000020) Slot 5 Configuration Register */ + + struct { + __IOM uint32_t SLEN5 : 1; /*!< [0..0] This bit enables slot 5 for ADC conversions. */ + __IOM uint32_t WCEN5 : 1; /*!< [1..1] This bit enables the window compare function for slot + 5. */ + uint32_t : 6; + __IOM uint32_t CHSEL5 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE5 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL5 : 3; /*!< [26..24] Select number of measurements to average in the accumulate + divide module for this slot. */ + } SL5CFG_b; + } ; + + union { + __IOM uint32_t SL6CFG; /*!< (@ 0x00000024) Slot 6 Configuration Register */ + + struct { + __IOM uint32_t SLEN6 : 1; /*!< [0..0] This bit enables slot 6 for ADC conversions. */ + __IOM uint32_t WCEN6 : 1; /*!< [1..1] This bit enables the window compare function for slot + 6. */ + uint32_t : 6; + __IOM uint32_t CHSEL6 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE6 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL6 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL6CFG_b; + } ; + + union { + __IOM uint32_t SL7CFG; /*!< (@ 0x00000028) Slot 7 Configuration Register */ + + struct { + __IOM uint32_t SLEN7 : 1; /*!< [0..0] This bit enables slot 7 for ADC conversions. */ + __IOM uint32_t WCEN7 : 1; /*!< [1..1] This bit enables the window compare function for slot + 7. */ + uint32_t : 6; + __IOM uint32_t CHSEL7 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE7 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL7 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL7CFG_b; + } ; + + union { + __IOM uint32_t WULIM; /*!< (@ 0x0000002C) Window Comparator Upper Limits Register */ + + struct { + __IOM uint32_t ULIM : 20; /*!< [19..0] Sets the upper limit for the window comparator. */ + } WULIM_b; + } ; + + union { + __IOM uint32_t WLLIM; /*!< (@ 0x00000030) Window Comparator Lower Limits Register */ + + struct { + __IOM uint32_t LLIM : 20; /*!< [19..0] Sets the lower limit for the window comparator. */ + } WLLIM_b; + } ; + + union { + __IOM uint32_t SCWLIM; /*!< (@ 0x00000034) Scale Window Comparator Limits */ + + struct { + __IOM uint32_t SCWLIMEN : 1; /*!< [0..0] Scale the window limits compare values per precision + mode. When set to 0x0 (default), the values in the 20-bit + limits registers will compare directly with the FIFO values + regardless of the precision mode the slot is configured + to. When set to 0x1, the compare values will be divided + by the difference in precision bits while performing the + window limit comparisons. */ + } SCWLIM_b; + } ; + + union { + __IOM uint32_t FIFO; /*!< (@ 0x00000038) FIFO Data and Valid Count Register */ + + struct { + __IOM uint32_t DATA : 20; /*!< [19..0] Oldest data in the FIFO. */ + __IOM uint32_t COUNT : 8; /*!< [27..20] Number of valid entries in the ADC FIFO. */ + __IOM uint32_t SLOTNUM : 3; /*!< [30..28] Slot number associated with this FIFO data. */ + __IOM uint32_t RSVD : 1; /*!< [31..31] RESERVED. */ + } FIFO_b; + } ; + + union { + __IOM uint32_t FIFOPR; /*!< (@ 0x0000003C) FIFO Data and Valid Count Register */ + + struct { + __IOM uint32_t DATA : 20; /*!< [19..0] Oldest data in the FIFO. */ + __IOM uint32_t COUNT : 8; /*!< [27..20] Number of valid entries in the ADC FIFO. */ + __IOM uint32_t SLOTNUMPR : 3; /*!< [30..28] Slot number associated with this FIFO data. */ + __IOM uint32_t RSVDPR : 1; /*!< [31..31] RESERVED. */ + } FIFOPR_b; + } ; + __IM uint32_t RESERVED[112]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) ADC Interrupt registers: Enable */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) ADC Interrupt registers: Status */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) ADC Interrupt registers: Clear */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) ADC Interrupt registers: Set */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ + } INTSET_b; + } ; + __IM uint32_t RESERVED1[12]; + + union { + __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */ + + struct { + __IOM uint32_t DFIFO75 : 1; /*!< [0..0] Trigger DMA upon FIFO 75 percent Full */ + __IOM uint32_t DFIFOFULL : 1; /*!< [1..1] Trigger DMA upon FIFO 100 percent Full */ + } DMATRIGEN_b; + } ; + + union { + __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */ + + struct { + __IOM uint32_t D75STAT : 1; /*!< [0..0] Triggered DMA from FIFO 75 percent Full */ + __IOM uint32_t DFULLSTAT : 1; /*!< [1..1] Triggered DMA from FIFO 100 percent Full */ + } DMATRIGSTAT_b; + } ; + __IM uint32_t RESERVED2[14]; + + union { + __IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable */ + uint32_t : 1; + __IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */ + uint32_t : 5; + __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ + __IOM uint32_t DMADYNPRI : 1; /*!< [9..9] Enables dynamic priority based on FIFO fullness. When + FIFO is full, priority is automatically set to HIGH. Otherwise, + DMAPRI is used. */ + uint32_t : 6; + __IOM uint32_t DMAHONSTAT : 1; /*!< [16..16] Halt New ADC conversions until DMA Status DMAERR and + DMACPL Cleared. */ + __IOM uint32_t DMAMSK : 1; /*!< [17..17] Mask the FIFOCNT and SLOTNUM when transferring FIFO + contents to memory */ + __IOM uint32_t DPWROFF : 1; /*!< [18..18] Power Off the ADC System upon DMACPL. */ + } DMACFG_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */ + + struct { + uint32_t : 2; + __IOM uint32_t TOTCOUNT : 16; /*!< [17..2] Total Transfer Count */ + } DMATOTCOUNT_b; + } ; + + union { + __IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */ + + struct { + __IOM uint32_t LTARGADDR : 19; /*!< [18..0] DMA Target Address */ + __IOM uint32_t UTARGADDR : 13; /*!< [31..19] SRAM Target */ + } DMATARGADDR_b; + } ; + + union { + __IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */ + + struct { + __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress */ + __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete */ + __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error */ + } DMASTAT_b; + } ; +} ADC_Type; /*!< Size = 660 (0x294) */ + + + +/* =========================================================================================================================== */ +/* ================ APBDMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief APB DMA Register Interfaces (APBDMA) + */ + +typedef struct { /*!< (@ 0x40011000) APBDMA Structure */ + + union { + __IOM uint32_t BBVALUE; /*!< (@ 0x00000000) Control Register */ + + struct { + __IOM uint32_t DATAOUT : 8; /*!< [7..0] Data Output Values */ + uint32_t : 8; + __IOM uint32_t PIN : 8; /*!< [23..16] PIO values */ + } BBVALUE_b; + } ; + + union { + __IOM uint32_t BBSETCLEAR; /*!< (@ 0x00000004) Set/Clear Register */ + + struct { + __IOM uint32_t SET : 8; /*!< [7..0] Write 1 to Set PIO value (set hier priority than clear + if both bit set) */ + uint32_t : 8; + __IOM uint32_t CLEAR : 8; /*!< [23..16] Write 1 to Clear PIO value */ + } BBSETCLEAR_b; + } ; + + union { + __IOM uint32_t BBINPUT; /*!< (@ 0x00000008) PIO Input Values */ + + struct { + __IOM uint32_t DATAIN : 8; /*!< [7..0] PIO values */ + } BBINPUT_b; + } ; + __IM uint32_t RESERVED[5]; + + union { + __IOM uint32_t DEBUGDATA; /*!< (@ 0x00000020) PIO Input Values */ + + struct { + __IOM uint32_t DEBUGDATA : 32; /*!< [31..0] Debug Data */ + } DEBUGDATA_b; + } ; + __IM uint32_t RESERVED1[7]; + + union { + __IOM uint32_t DEBUG; /*!< (@ 0x00000040) PIO Input Values */ + + struct { + __IOM uint32_t DEBUGEN : 4; /*!< [3..0] Debug Enable */ + } DEBUG_b; + } ; +} APBDMA_Type; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ BLEIF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief BLE Interface (BLEIF) + */ + +typedef struct { /*!< (@ 0x5000C000) BLEIF Structure */ + + union { + __IOM uint32_t FIFO; /*!< (@ 0x00000000) FIFO Access Port */ + + struct { + __IOM uint32_t FIFO : 32; /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return + valid information. */ + } FIFO_b; + } ; + __IM uint32_t RESERVED[63]; + + union { + __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) FIFO size and remaining slots open values */ + + struct { + __IOM uint32_t FIFO0SIZ : 8; /*!< [7..0] The number of valid data bytes currently in the FIFO + 0 (written by MCU, read by interface) */ + __IOM uint32_t FIFO0REM : 8; /*!< [15..8] The number of remaining data bytes slots currently in + FIFO 0 (written by MCU, read by interface) */ + __IOM uint32_t FIFO1SIZ : 8; /*!< [23..16] The number of valid data bytes currently in FIFO 1 + (written by interface, read by MCU) */ + __IOM uint32_t FIFO1REM : 8; /*!< [31..24] The number of remaining data bytes slots currently + in FIFO 1 (written by interface, read by MCU) */ + } FIFOPTR_b; + } ; + + union { + __IOM uint32_t FIFOTHR; /*!< (@ 0x00000104) FIFO Threshold Configuration */ + + struct { + __IOM uint32_t FIFORTHR : 6; /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable + the read FIFO level from activating the threshold interrupt. + If this field is non-zero, it will trigger a threshold + interrupt when the read fifo contains FIFORTHR valid bytes + of data, as indicated by the FIFO1SIZ field. This is intended + to signal when a data transfer of FIFORTHR bytes can be + done from the IOM module to the host via the read fifo + to support large IOM read operations. */ + uint32_t : 2; + __IOM uint32_t FIFOWTHR : 6; /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable + the write FIFO level from activating the threshold interrupt. + If this field is non-zero, it will trigger a threshold + interrupt when the write fifo contains FIFOWTHR free bytes, + as indicated by the FIFO0REM field. This is intended to + signal when a transfer of FIFOWTHR bytes can be done from + the host to the IOM write fifo to support large IOM write + operations. */ + } FIFOTHR_b; + } ; + + union { + __IOM uint32_t FIFOPOP; /*!< (@ 0x00000108) FIFO POP register */ + + struct { + __IOM uint32_t FIFODOUT : 32; /*!< [31..0] This register will return the read data indicated by + the current read pointer on reads. If the POPWR control + bit in the FIFOCTRL register is reset (0), the fifo read + pointer will be advanced by one word as a result of the + read.If the POPWR bit is set (1), the fifo read pointer + will only be advanced after a write operation to this register. + The write data is ignored for this register.If less than + a even word multiple is available, and the command is completed, + the module will return the word containing */ + } FIFOPOP_b; + } ; + + union { + __IOM uint32_t FIFOPUSH; /*!< (@ 0x0000010C) FIFO PUSH register */ + + struct { + __IOM uint32_t FIFODIN : 32; /*!< [31..0] This register is used to write the FIFORAM in FIFO mode + and will cause a push event to occur to the next open slot + within the FIFORAM. Writing to this register will cause + the write point to increment by 1 word(4 bytes). */ + } FIFOPUSH_b; + } ; + + union { + __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000110) FIFO Control Register */ + + struct { + __IOM uint32_t POPWR : 1; /*!< [0..0] Selects the mode in which 'pop' events are done for the + fifo read operations. A value of '1' will prevent a pop + event on a read operation, and will require a write to + the FIFOPOP register to create a pop event.A value of '0' + in this register will allow a pop event to occur on the + read of the FIFOPOP register, and may cause inadvertant + fifo pops when used in a debugging mode. */ + __IOM uint32_t FIFORSTN : 1; /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset + fifo, and then write to 1 to remove the reset. */ + } FIFOCTRL_b; + } ; + + union { + __IOM uint32_t FIFOLOC; /*!< (@ 0x00000114) FIFO Pointers */ + + struct { + __IOM uint32_t FIFOWPTR : 4; /*!< [3..0] Current FIFO write pointer. Value is the index into the + outgoing FIFO (FIFO0), which is used during write operations + to external devices. */ + uint32_t : 4; + __IOM uint32_t FIFORPTR : 4; /*!< [11..8] Current FIFO read pointer. Used to index into the incoming + FIFO (FIFO1), which is used to store read data returned + from external devices during a read operation. */ + } FIFOLOC_b; + } ; + __IM uint32_t RESERVED1[58]; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x00000200) I/O Clock Configuration */ + + struct { + __IOM uint32_t IOCLKEN : 1; /*!< [0..0] Enable for the interface clock. Must be enabled prior + to executing any IO operations. */ + uint32_t : 7; + __IOM uint32_t FSEL : 3; /*!< [10..8] Select the input clock frequency. */ + __IOM uint32_t CLK32KEN : 1; /*!< [11..11] Enable for the 32Khz clock to the BLE module */ + __IOM uint32_t DIV3 : 1; /*!< [12..12] Enable of the divide by 3 of the source IOCLK. */ + } CLKCFG_b; + } ; + __IM uint32_t RESERVED2[2]; + + union { + __IOM uint32_t CMD; /*!< (@ 0x0000020C) Command and offset Register */ + + struct { + __IOM uint32_t CMD : 5; /*!< [4..0] Command for submodule. */ + __IOM uint32_t OFFSETCNT : 2; /*!< [6..5] Number of offset bytes to use for the command - 0, 1, + 2, 3 are valid selections. The second (byte 1) and third + byte (byte 2) are read from the OFFSETHI register, and + the low order byte is pulled from this register in the + OFFSETLO field.Offset bytes are transmitted highest byte + first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted + first, then OFFSETHI[7:0] then OFFSETLO.If offsetcnt == + 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.If + offsetcnt == 1, only OFFSETLO will be transmitted. */ + __IOM uint32_t CONT : 1; /*!< [7..7] Contine to hold the bus after the current transaction + if set to a 1 with a new command issued. */ + __IOM uint32_t TSIZE : 12; /*!< [19..8] Defines the transaction size in bytes. The offset transfer + is not included in this size. */ + __IOM uint32_t CMDSEL : 2; /*!< [21..20] Command Specific selection information */ + uint32_t : 2; + __IOM uint32_t OFFSETLO : 8; /*!< [31..24] This register holds the low order byte of offset to + be used in the transaction. The number of offset bytes + to use is set with bits 1:0 of the command. Offset bytes + are transferred starting from the highest byte first. */ + } CMD_b; + } ; + + union { + __IOM uint32_t CMDRPT; /*!< (@ 0x00000210) Command Repeat Register */ + + struct { + __IOM uint32_t CMDRPT : 5; /*!< [4..0] Count of number of times to repeat the next command. */ + } CMDRPT_b; + } ; + + union { + __IOM uint32_t OFFSETHI; /*!< (@ 0x00000214) High order offset bytes */ + + struct { + __IOM uint32_t OFFSETHI : 16; /*!< [15..0] Holds the high order bytes of the 2 or 3 byte offset + phase of a transaction. */ + } OFFSETHI_b; + } ; + + union { + __IOM uint32_t CMDSTAT; /*!< (@ 0x00000218) Command status */ + + struct { + __IOM uint32_t CCMD : 5; /*!< [4..0] current command that is being executed */ + __IOM uint32_t CMDSTAT : 3; /*!< [7..5] The current status of the command execution. */ + __IOM uint32_t CTSIZE : 12; /*!< [19..8] The current number of bytes still to be transferred + with this command. This field will count down to zero. */ + } CMDSTAT_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000220) IO Master Interrupts: Enable */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation + is done to a empty read FIFO. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in + the B2M_STATE signal from the BLE Core. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal + from the BLE Core is asserted, indicating the availability + of read data from the BLE Core. */ + __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS + signal from the BLE Core is asserted, indicating that SPI + writes can be done to the BLE Core.Transfers to the BLE + Core should only be done when this signal is high. */ + __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write + with the register address bit 0 set to 1. The low address + bits in the CQ address fields are unused and bit 0 can + be used to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error + occurs, the system will stop processing and halt operations + to allow software to take recovery actions */ + __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the + sleep state */ + __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned + into the active state Revision B: Falling BLE Core IRQ + signal. Asserted when the BLE_IRQ signal from the BLE Core + is de-asserted (1 -> 0) */ + __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned + into shutdown state Revision B: Falling BLE Core Status + signal. Asserted when the BLE_STATUS signal from the BLE + Core is de-asserted (1 -> 0) */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000224) IO Master Interrupts: Status */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation + is done to a empty read FIFO. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in + the B2M_STATE signal from the BLE Core. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal + from the BLE Core is asserted, indicating the availability + of read data from the BLE Core. */ + __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS + signal from the BLE Core is asserted, indicating that SPI + writes can be done to the BLE Core.Transfers to the BLE + Core should only be done when this signal is high. */ + __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write + with the register address bit 0 set to 1. The low address + bits in the CQ address fields are unused and bit 0 can + be used to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error + occurs, the system will stop processing and halt operations + to allow software to take recovery actions */ + __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the + sleep state */ + __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned + into the active state Revision B: Falling BLE Core IRQ + signal. Asserted when the BLE_IRQ signal from the BLE Core + is de-asserted (1 -> 0) */ + __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned + into shutdown state Revision B: Falling BLE Core Status + signal. Asserted when the BLE_STATUS signal from the BLE + Core is de-asserted (1 -> 0) */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000228) IO Master Interrupts: Clear */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation + is done to a empty read FIFO. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in + the B2M_STATE signal from the BLE Core. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal + from the BLE Core is asserted, indicating the availability + of read data from the BLE Core. */ + __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS + signal from the BLE Core is asserted, indicating that SPI + writes can be done to the BLE Core.Transfers to the BLE + Core should only be done when this signal is high. */ + __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write + with the register address bit 0 set to 1. The low address + bits in the CQ address fields are unused and bit 0 can + be used to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error + occurs, the system will stop processing and halt operations + to allow software to take recovery actions */ + __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the + sleep state */ + __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned + into the active state Revision B: Falling BLE Core IRQ + signal. Asserted when the BLE_IRQ signal from the BLE Core + is de-asserted (1 -> 0) */ + __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned + into shutdown state Revision B: Falling BLE Core Status + signal. Asserted when the BLE_STATUS signal from the BLE + Core is de-asserted (1 -> 0) */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000022C) IO Master Interrupts: Set */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation + is done to a empty read FIFO. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in + the B2M_STATE signal from the BLE Core. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal + from the BLE Core is asserted, indicating the availability + of read data from the BLE Core. */ + __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS + signal from the BLE Core is asserted, indicating that SPI + writes can be done to the BLE Core.Transfers to the BLE + Core should only be done when this signal is high. */ + __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write + with the register address bit 0 set to 1. The low address + bits in the CQ address fields are unused and bit 0 can + be used to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error + occurs, the system will stop processing and halt operations + to allow software to take recovery actions */ + __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the + sleep state */ + __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned + into the active state Revision B: Falling BLE Core IRQ + signal. Asserted when the BLE_IRQ signal from the BLE Core + is de-asserted (1 -> 0) */ + __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned + into shutdown state Revision B: Falling BLE Core Status + signal. Asserted when the BLE_STATUS signal from the BLE + Core is de-asserted (1 -> 0) */ + } INTSET_b; + } ; + + union { + __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000230) DMA Trigger Enable Register */ + + struct { + __IOM uint32_t DCMDCMPEN : 1; /*!< [0..0] Trigger DMA upon command complete. Enables the trigger + of the DMA when a command is completed. When this event + is triggered, the number of words transferred will be the + lesser of the remaining TOTCOUNT bytes, or the number of + bytes in the FIFO when the command completed. If this is + disabled, and the number of bytes in the FIFO is equal + or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT + bytes will be done to ensure read data is stored when the + DMA is completed. */ + __IOM uint32_t DTHREN : 1; /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations + (IOM writes), the trigger will assert when the write FIFO + has (WTHR/4) number of words free in the write FIFO, and + will transfer (WTHR/4) number of wordsor, if the number + of words left to transfer is less than the WTHR value, + will transfer the remaining byte count.For P2M DMA operations, + the trigger will assert when the read FIFO has (RTHR/4) + words available in the read FIFO, and will transfer (RTHR/4) + words to SRAM. This trigger will NOT asser */ + } DMATRIGEN_b; + } ; + + union { + __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000234) DMA Trigger Status Register */ + + struct { + __IOM uint32_t DCMDCMP : 1; /*!< [0..0] Triggered DMA from Command complete event. Bit is read + only and can be cleared by disabling the DCMDCMP trigger + enable or by disabling DMA. */ + __IOM uint32_t DTHR : 1; /*!< [1..1] Triggered DMA from THR event. Bit is read only and can + be cleared by disabling the DTHR trigger enable or by disabling + DMA. */ + __IOM uint32_t DTOTCMP : 1; /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data + in the FIFO was enough to complete the DMA operation (greater + than or equal to current TOTCOUNT) when the command completed. + This trigger is default active when the DCMDCMP trigger + isdisabled and there is enough data in the FIFO to complete + the DMA operation. */ + } DMATRIGSTAT_b; + } ; + + union { + __IOM uint32_t DMACFG; /*!< (@ 0x00000238) DMA Configuration Register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA + operation. This should be the last DMA related register + set prior to issuing the command */ + __IOM uint32_t DMADIR : 1; /*!< [1..1] Direction */ + uint32_t : 6; + __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ + __IOM uint32_t DPWROFF : 1; /*!< [9..9] Power off module after DMA is complete. If this bit is + active, the module will request to power off the supply + it is attached to. If there are other units still requiring + power from the same domain, power down will not be performed. */ + } DMACFG_b; + } ; + + union { + __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x0000023C) DMA Total Transfer Count */ + + struct { + __IOM uint32_t TOTCOUNT : 12; /*!< [11..0] Triggered DMA from Command complete event occured. Bit + is read only and can be cleared by disabling the DTHR trigger + enable or by disabling DMA. */ + } DMATOTCOUNT_b; + } ; + + union { + __IOM uint32_t DMATARGADDR; /*!< (@ 0x00000240) DMA Target Address Register */ + + struct { + __IOM uint32_t TARGADDR : 20; /*!< [19..0] Bits [19:0] of the target byte address for source of + DMA (either read or write). The address can be any byte + alignment, and does not have to be word aligned. In cases + of non-word aligned addresses, the DMA logic will take + care for ensuring only the target bytes are read/written. */ + uint32_t : 8; + __IOM uint32_t TARGADDR28 : 1; /*!< [28..28] Bit 28 of the target byte address for source of DMA + (either read or write). In cases of non-word aligned addresses, + the DMA logic will take care for ensuring only the target + bytes are read/written.Setting to '1' will select the SRAM. + Setting to '0' will select the flash */ + } DMATARGADDR_b; + } ; + + union { + __IOM uint32_t DMASTAT; /*!< (@ 0x00000244) DMA Status Register */ + + struct { + __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that + a DMA transfer is active. The DMA transfer may be waiting + on data, transferring data, or waiting for priority.All + of these will be indicated with a 1. A 0 will indicate + that the DMA is fully complete and no further transactions + will be done. This bit is read only. */ + __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA + operation. This bit can be cleared by writing to 0. */ + __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals that an error + was encountered during the DMA operation. */ + } DMASTAT_b; + } ; + + union { + __IOM uint32_t CQCFG; /*!< (@ 0x00000248) Command Queue Configuration Register */ + + struct { + __IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing + of the command queue and fetches of address/data pairs + will proceed from the word address within the CQADDR register. + Can be disabledusing a CQ executed write to this bit as + well. */ + __IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue dma request. */ + } CQCFG_b; + } ; + + union { + __IOM uint32_t CQADDR; /*!< (@ 0x0000024C) CQ Target Read Address Register */ + + struct { + uint32_t : 2; + __IOM uint32_t CQADDR : 18; /*!< [19..2] Bits 19:2 of target byte address for source of CQ (read + only). The buffer must be aligned on a word boundary */ + uint32_t : 8; + __IOM uint32_t CQADDR28 : 1; /*!< [28..28] Bit 28 of target byte address for source of CQ (read + only). Used to denote Flash (0) or SRAM (1) access */ + } CQADDR_b; + } ; + + union { + __IOM uint32_t CQSTAT; /*!< (@ 0x00000250) Command Queue Status Register */ + + struct { + __IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will + indicate that a CQ transfer is active and this will remain + active even when paused waiting for external event. */ + __IOM uint32_t CQPAUSED : 1; /*!< [1..1] Command queue operation is currently paused. */ + __IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit + signals that an error was encountered during the CQ operation. */ + } CQSTAT_b; + } ; + + union { + __IOM uint32_t CQFLAGS; /*!< (@ 0x00000254) Command Queue Flag Register */ + + struct { + __IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software + controllable and bits [15:8] are hardware status. */ + __IOM uint32_t CQIRQMASK : 16; /*!< [31..16] Provides for a per-bit mask of the flags used to invoke + an interrupt. A '1' in the bit position will enable the + pause event to trigger the interrupt, if the CQWT_int interrupt + is enabled.Bits definitions are the same as CQPAUSE */ + } CQFLAGS_b; + } ; + + union { + __IOM uint32_t CQSETCLEAR; /*!< (@ 0x00000258) Command Queue Flag Set/Clear Register */ + + struct { + __IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any + SWFLAG with a '1' in the corresponding bit position of + this field */ + __IOM uint32_t CQFTGL : 8; /*!< [15..8] Toggle the indicated bit. Will toggle the value of any + SWFLAG with a '1' in the corresponding bit position of + this field */ + __IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG + with a '1' in the corresponding bit position of this field */ + } CQSETCLEAR_b; + } ; + + union { + __IOM uint32_t CQPAUSEEN; /*!< (@ 0x0000025C) Command Queue Pause Enable Register */ + + struct { + __IOM uint32_t CQPEN : 16; /*!< [15..0] Enables the specified event to pause command processing + when active */ + } CQPAUSEEN_b; + } ; + + union { + __IOM uint32_t CQCURIDX; /*!< (@ 0x00000260) IOM Command Queue current index value . Compared + to the CQENDIDX reg contents to generate + the IDXEQ Pause event for command queue */ + + struct { + __IOM uint32_t CQCURIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX + register field. If the values match, the IDXEQ pause event + will be activated, which will cause the pausing of command + quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ + } CQCURIDX_b; + } ; + + union { + __IOM uint32_t CQENDIDX; /*!< (@ 0x00000264) IOM Command Queue current index value . Compared + to the CQCURIDX reg contents to generate + the IDXEQ Pause event for command queue */ + + struct { + __IOM uint32_t CQENDIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX + register field. If the values match, the IDXEQ pause event + will be activated, which will cause the pausing of command + quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ + } CQENDIDX_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000268) IOM Module Status Register */ + + struct { + __IOM uint32_t ERR : 1; /*!< [0..0] Bit has been deprecated. Please refer to the other error + indicators. This will always return 0. */ + __IOM uint32_t CMDACT : 1; /*!< [1..1] Indicates if the active I/O Command is currently processing + a transaction, or command is complete, but the FIFO pointers + are still syncronizing internally. This bit will go high + atthe start of the transaction, and will go low when the + command is complete, and the data and pointers within the + FIFO have been syncronized. */ + __IOM uint32_t IDLEST : 1; /*!< [2..2] indicates if the active I/O state machine is IDLE. Note + - The state machine could be in idle state due to holdoffs + from data availability, or as the command gets propagated + into the logic from the registers. */ + } STATUS_b; + } ; + __IM uint32_t RESERVED4[37]; + + union { + __IOM uint32_t MSPICFG; /*!< (@ 0x00000300) SPI module master configuration */ + + struct { + __IOM uint32_t SPOL : 1; /*!< [0..0] This bit selects SPI polarity. */ + __IOM uint32_t SPHA : 1; /*!< [1..1] Selects the SPI phase; When 1, will shift the sampling + edge by 1/2 clock. */ + __IOM uint32_t FULLDUP : 1; /*!< [2..2] Full Duplex mode. Capture read data during writes operations */ + uint32_t : 13; + __IOM uint32_t WTFC : 1; /*!< [16..16] Enables flow control of new write transactions based + on the SPI_STATUS signal from the BLE Core. */ + __IOM uint32_t RDFC : 1; /*!< [17..17] Enables flow control of new read transactions based + on the SPI_STATUS signal from the BLE Core. */ + uint32_t : 3; + __IOM uint32_t WTFCPOL : 1; /*!< [21..21] Selects the write flow control signal polarity. The + transfers are halted when the selected flow control signal + is OPPOSITE polarity of this bit. (For example: WTFCPOL + = 0 will allow a SPI_STATUS=1 to pause transfers). */ + __IOM uint32_t RDFCPOL : 1; /*!< [22..22] Selects the read flow control signal polarity. When + set, the clock will be held low until the flow control + is de-asserted. */ + __IOM uint32_t SPILSB : 1; /*!< [23..23] Selects data transfer as MSB first (0) or LSB first + (1) for the data portion of the SPI transaction. The offset + bytes are always transmitted MSB first. */ + __IOM uint32_t DINDLY : 3; /*!< [26..24] Delay tap to use for the input signal (MISO). This + gives more hold time on the input data. */ + __IOM uint32_t DOUTDLY : 3; /*!< [29..27] Delay tap to use for the output signal (MOSI). This + give more hold time on the output data. */ + __IOM uint32_t MSPIRST : 1; /*!< [30..30] Bit is deprecated. setting it will have no effect. */ + } MSPICFG_b; + } ; + + union { + __IOM uint32_t BLECFG; /*!< (@ 0x00000304) BLE Core Control */ + + struct { + __IOM uint32_t PWRSMEN : 1; /*!< [0..0] Enable the power state machine for automatic sequencing + and control of power states of the BLE Core module. */ + __IOM uint32_t BLERSTN : 1; /*!< [1..1] Reset line to the BLE Core. This will reset the BLE core + when asserted ('0') and must be written to '1' prior to + performing any BTLE related operations to the core. */ + __IOM uint32_t WAKEUPCTL : 2; /*!< [3..2] WAKE signal override. Controls the source of the WAKE + signal to the BLE Core. */ + __IOM uint32_t DCDCFLGCTL : 2; /*!< [5..4] DCDCFLG signal override. The value of this field will + be sent to the BLE Core when the PWRSM is off. Otherwise, + the value is supplied from internal logic. */ + __IOM uint32_t BLEHREQCTL : 2; /*!< [7..6] BLEH power on request override. The value of this field + will be sent to the BLE Core when the PWRSM is off. Otherwise, + the value is supplied from internal logic. */ + __IOM uint32_t WT4ACTOFF : 1; /*!< [8..8] Debug control of BLEIF power state machine. Allows transition + into the active state in the BLEIF state without waiting + for dcdc req from BLE Core. */ + __IOM uint32_t MCUFRCSLP : 1; /*!< [9..9] Force power state machine to go to the sleep state. Intended + for debug only. Has no effect on the actual BLE Core state, + only the state of the BLEIF interface state machine. */ + __IOM uint32_t FRCCLK : 1; /*!< [10..10] Force the clock in the BLEIF to be always running */ + __IOM uint32_t STAYASLEEP : 1; /*!< [11..11] Set to prevent the BLE power control module from waking + up the BLE Core after going into power down. To be used + for graceful shutdown, set by software prior to powering + off and will allow assertion of reset from sleep state. */ + __IOM uint32_t PWRISOCTL : 2; /*!< [13..12] Configuration of BLEH isolation control for power related + signals. */ + __IOM uint32_t SPIISOCTL : 2; /*!< [15..14] Configuration of BLEH isolation controls for SPI related + signals. */ + } BLECFG_b; + } ; + + union { + __IOM uint32_t PWRCMD; /*!< (@ 0x00000308) BLE Power command interface */ + + struct { + __IOM uint32_t WAKEREQ : 1; /*!< [0..0] Wake request from the MCU. When asserted (1), the BLE + Interface logic will assert the wakeup request signal to + the BLE Core. Only recognized when in the sleep state */ + __IOM uint32_t RESTART : 1; /*!< [1..1] Restart the BLE Core after going into the shutdown state. + Only valid when in the shutdown state. */ + } PWRCMD_b; + } ; + + union { + __IOM uint32_t BSTATUS; /*!< (@ 0x0000030C) BLE Core status */ + + struct { + __IOM uint32_t B2MSTATE : 3; /*!< [2..0] State of the BLE Core logic. */ + __IOM uint32_t SPISTATUS : 1; /*!< [3..3] Value of the SPISTATUS signal from the BLE Core. The + signal is asserted when the BLE Core is able to accept + write data via the SPI interface. Data should be transmitted + to theBLE core only when this signal is 1. The hardware + will automatically wait for this signal prior to performing + a write operation if flow control is active. */ + __IOM uint32_t DCDCREQ : 1; /*!< [4..4] Value of the DCDCREQ signal from the BLE Core. The DCDCREQ + signal is sent from the core to the BLEIF module when the + BLE core requires BLEH power to be active. When activated, + this isindicated by DCDCFLAG going to 1. */ + __IOM uint32_t DCDCFLAG : 1; /*!< [5..5] Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG + is a signal to the BLE Core indicating that the BLEH ppower + is active. */ + __IOM uint32_t WAKEUP : 1; /*!< [6..6] Value of the WAKEUP signal to the BLE Core . The WAKEUP + signals is sent from the BLEIF to the BLECORE to request + the BLE Core transition from sleep state to active state. */ + __IOM uint32_t BLEIRQ : 1; /*!< [7..7] Status of the BLEIRQ signal from the BLE Core. A value + of 1 idicates that read data is available in the core and + a read operation needs to be performed. */ + __IOM uint32_t PWRST : 3; /*!< [10..8] Current status of the power state machine */ + __IOM uint32_t BLEHACK : 1; /*!< [11..11] Value of the BLEHACK signal from the power control + unit. If the signal is '1', the BLEH power is active and + ready for use. */ + __IOM uint32_t BLEHREQ : 1; /*!< [12..12] Value of the BLEHREQ signal to the power control unit. + The BLEHREQ signal is sent from the BLEIF module to the + power control module to request the BLEH power up. When + the BLEHACK signal is asserted,BLEH power is stable and + ready for use. */ + } BSTATUS_b; + } ; + __IM uint32_t RESERVED5[64]; + + union { + __IOM uint32_t BLEDBG; /*!< (@ 0x00000410) BLEIF Master Debug Register */ + + struct { + __IOM uint32_t DBGEN : 1; /*!< [0..0] Debug Enable. Setting this bit will enable the update + of data within this register, otherwise it is clock gated + for power savings */ + __IOM uint32_t IOCLKON : 1; /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active + when this bit is '1'. Otherwise, the clock is controlled + with gating from the logic as needed. */ + __IOM uint32_t APBCLKON : 1; /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active + when this bit is '1'. Otherwise, the clock is controlled + with gating from the logic as needed. */ + __IOM uint32_t DBGDATA : 29; /*!< [31..3] Debug data */ + } BLEDBG_b; + } ; +} BLEIF_Type; /*!< Size = 1044 (0x414) */ + + + +/* =========================================================================================================================== */ +/* ================ CACHECTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Flash Cache Controller (CACHECTRL) + */ + +typedef struct { /*!< (@ 0x40018000) CACHECTRL Structure */ + + union { + __IOM uint32_t CACHECFG; /*!< (@ 0x00000000) Flash Cache Control Register */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] Enables the flash cache controller and enables power + to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE + should be set to enable caching for each type of access. */ + __IOM uint32_t LRU : 1; /*!< [1..1] Sets the cache repleacment policy. 0=LRR (least recently + replaced), 1=LRU (least recently used). LRR minimizes writes + to the TAG SRAM. */ + __IOM uint32_t ENABLE_NC0 : 1; /*!< [2..2] Enable Non-cacheable region 0. See NCR0 registers to + define the region. */ + __IOM uint32_t ENABLE_NC1 : 1; /*!< [3..3] Enable Non-cacheable region 1. See NCR1 registers to + define the region. */ + __IOM uint32_t CONFIG : 4; /*!< [7..4] Sets the cache configuration */ + __IOM uint32_t ICACHE_ENABLE : 1; /*!< [8..8] Enable Flash Instruction Caching */ + __IOM uint32_t DCACHE_ENABLE : 1; /*!< [9..9] Enable Flash Data Caching. */ + __IOM uint32_t CACHE_CLKGATE : 1; /*!< [10..10] Enable clock gating of cache TAG RAM. Software should + enable this bit for optimal power efficiency. */ + __IOM uint32_t CACHE_LS : 1; /*!< [11..11] Enable LS (light sleep) of cache RAMs. Software should + DISABLE this bit since cache activity is too high to benefit + from LS usage. */ + uint32_t : 8; + __IOM uint32_t DATA_CLKGATE : 1; /*!< [20..20] Enable aggressive clock gating of entire data array. + This bit should be set to 1 for optimal power efficiency. */ + uint32_t : 3; + __IOM uint32_t ENABLE_MONITOR : 1; /*!< [24..24] Enable Cache Monitoring Stats. Cache monitoring consumes + additional power and should only be enabled when profiling + code and counters will increment when this bit is set. + Counter values will be retained when this is set to 0, + allowing software to enable/disable counting for multiple + code segments. */ + } CACHECFG_b; + } ; + + union { + __IOM uint32_t FLASHCFG; /*!< (@ 0x00000004) Flash Control Register */ + + struct { + __IOM uint32_t RD_WAIT : 4; /*!< [3..0] Sets read waitstates for normal (fast) operation. A value + of 1 is recommended. */ + __IOM uint32_t SEDELAY : 3; /*!< [6..4] Sets SE delay (flash address setup). A value of 5 is + recommended. */ + uint32_t : 1; + __IOM uint32_t LPM_RD_WAIT : 4; /*!< [11..8] Sets flash waitstates when in LPM Mode 2 (RD_WAIT in + LPM mode 2 only) */ + __IOM uint32_t LPMMODE : 2; /*!< [13..12] Controls flash low power modes (control of LPM pin). */ + } FLASHCFG_b; + } ; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Cache Control */ + + struct { + __IOM uint32_t INVALIDATE : 1; /*!< [0..0] Writing a 1 to this bitfield invalidates the flash cache + contents. */ + __IOM uint32_t RESET_STAT : 1; /*!< [1..1] Reset Cache Statistics. When written to a 1, the cache + monitor counters will be cleared. The monitor counters + can be reset only when the CACHECFG.ENABLE_MONITOR bit + is set. */ + __IOM uint32_t CACHE_READY : 1; /*!< [2..2] Cache Ready Status (enabled and not processing an invalidate + operation) */ + uint32_t : 1; + __IOM uint32_t FLASH0_SLM_STATUS : 1; /*!< [4..4] Flash Sleep Mode Status. 1 indicates that flash0 is in + sleep mode, 0 indicates flash0 is in normal mode. */ + __IOM uint32_t FLASH0_SLM_DISABLE : 1; /*!< [5..5] Disable Flash Sleep Mode. Write 1 to wake flash0 from + sleep mode (reading the array will also automatically wake + it). */ + __IOM uint32_t FLASH0_SLM_ENABLE : 1; /*!< [6..6] Enable Flash Sleep Mode. Write to 1 to put flash 0 into + sleep mode. NOTE: there is a 5us latency after waking flash + until the first access will be returned. */ + uint32_t : 1; + __IOM uint32_t FLASH1_SLM_STATUS : 1; /*!< [8..8] Flash Sleep Mode Status. 1 indicates that flash1 is in + sleep mode, 0 indicates flash1 is in normal mode. */ + __IOM uint32_t FLASH1_SLM_DISABLE : 1; /*!< [9..9] Disable Flash Sleep Mode. Write 1 to wake flash1 from + sleep mode (reading the array will also automatically wake + it). */ + __IOM uint32_t FLASH1_SLM_ENABLE : 1; /*!< [10..10] Enable Flash Sleep Mode. Write to 1 to put flash 1 + into sleep mode. NOTE: there is a 5us latency after waking + flash until the first access will be returned. */ + } CTRL_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t NCR0START; /*!< (@ 0x00000010) Flash Cache Noncachable Region 0 Start */ + + struct { + uint32_t : 4; + __IOM uint32_t ADDR : 23; /*!< [26..4] Start address for non-cacheable region 0 */ + } NCR0START_b; + } ; + + union { + __IOM uint32_t NCR0END; /*!< (@ 0x00000014) Flash Cache Noncachable Region 0 End */ + + struct { + uint32_t : 4; + __IOM uint32_t ADDR : 23; /*!< [26..4] End address for non-cacheable region 0 */ + } NCR0END_b; + } ; + + union { + __IOM uint32_t NCR1START; /*!< (@ 0x00000018) Flash Cache Noncachable Region 1 Start */ + + struct { + uint32_t : 4; + __IOM uint32_t ADDR : 23; /*!< [26..4] Start address for non-cacheable region 1 */ + } NCR1START_b; + } ; + + union { + __IOM uint32_t NCR1END; /*!< (@ 0x0000001C) Flash Cache Noncachable Region 1 End */ + + struct { + uint32_t : 4; + __IOM uint32_t ADDR : 23; /*!< [26..4] End address for non-cacheable region 1 */ + } NCR1END_b; + } ; + __IM uint32_t RESERVED1[8]; + + union { + __IOM uint32_t DMON0; /*!< (@ 0x00000040) Data Cache Total Accesses */ + + struct { + __IOM uint32_t DACCESS_COUNT : 32; /*!< [31..0] Total accesses to data cache. All performance metrics + should be relative to the number of accesses performed. */ + } DMON0_b; + } ; + + union { + __IOM uint32_t DMON1; /*!< (@ 0x00000044) Data Cache Tag Lookups */ + + struct { + __IOM uint32_t DLOOKUP_COUNT : 32; /*!< [31..0] Total tag lookups from data cache. */ + } DMON1_b; + } ; + + union { + __IOM uint32_t DMON2; /*!< (@ 0x00000048) Data Cache Hits */ + + struct { + __IOM uint32_t DHIT_COUNT : 32; /*!< [31..0] Cache hits from lookup operations. */ + } DMON2_b; + } ; + + union { + __IOM uint32_t DMON3; /*!< (@ 0x0000004C) Data Cache Line Hits */ + + struct { + __IOM uint32_t DLINE_COUNT : 32; /*!< [31..0] Cache hits from line cache */ + } DMON3_b; + } ; + + union { + __IOM uint32_t IMON0; /*!< (@ 0x00000050) Instruction Cache Total Accesses */ + + struct { + __IOM uint32_t IACCESS_COUNT : 32; /*!< [31..0] Total accesses to Instruction cache */ + } IMON0_b; + } ; + + union { + __IOM uint32_t IMON1; /*!< (@ 0x00000054) Instruction Cache Tag Lookups */ + + struct { + __IOM uint32_t ILOOKUP_COUNT : 32; /*!< [31..0] Total tag lookups from Instruction cache */ + } IMON1_b; + } ; + + union { + __IOM uint32_t IMON2; /*!< (@ 0x00000058) Instruction Cache Hits */ + + struct { + __IOM uint32_t IHIT_COUNT : 32; /*!< [31..0] Cache hits from lookup operations */ + } IMON2_b; + } ; + + union { + __IOM uint32_t IMON3; /*!< (@ 0x0000005C) Instruction Cache Line Hits */ + + struct { + __IOM uint32_t ILINE_COUNT : 32; /*!< [31..0] Cache hits from line cache */ + } IMON3_b; + } ; +} CACHECTRL_Type; /*!< Size = 96 (0x60) */ + + + +/* =========================================================================================================================== */ +/* ================ CLKGEN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock Generator (CLKGEN) + */ + +typedef struct { /*!< (@ 0x40004000) CLKGEN Structure */ + + union { + __IOM uint32_t CALXT; /*!< (@ 0x00000000) XT Oscillator Control */ + + struct { + __IOM uint32_t CALXT : 11; /*!< [10..0] XT Oscillator calibration value. This register will + enable the hardware to increase or decrease the number + of cycles in a 16KHz clock derived from the original 32KHz + version. The most significant bit is the sign. A '1' is + a reduction, and a '0' is an addition. This calibration + value will add or reduce the number of cycles programmed + here across a 32 second interval. The maximum value that + is effective is from -1024 to 1023. */ + } CALXT_b; + } ; + + union { + __IOM uint32_t CALRC; /*!< (@ 0x00000004) RC Oscillator Control */ + + struct { + __IOM uint32_t CALRC : 18; /*!< [17..0] LFRC Oscillator calibration value. This register will + enable the hardware to increase or decrease the number + of cycles in a 512 Hz clock derived from the original 1024 + version. The most significant bit is the sign. A '1' is + a reduction, and a '0' is an addition. This calibration + value will add or reduce the number of cycles programmed + here across a 32 second interval. The range is from -131072 + (decimal) to 131071 (decimal). This register is normally + used in conjuction with ACALCTR register. The CAL */ + } CALRC_b; + } ; + + union { + __IOM uint32_t ACALCTR; /*!< (@ 0x00000008) Autocalibration Counter */ + + struct { + __IOM uint32_t ACALCTR : 24; /*!< [23..0] Autocalibration Counter result. Bits 17 down to 0 of + this is feed directly to the CALRC register if ACAL register + in OCTRL register is set to 1024SEC or 512SEC. */ + } ACALCTR_b; + } ; + + union { + __IOM uint32_t OCTRL; /*!< (@ 0x0000000C) Oscillator Control */ + + struct { + __IOM uint32_t STOPXT : 1; /*!< [0..0] Stop the XT Oscillator to the RTC */ + __IOM uint32_t STOPRC : 1; /*!< [1..1] Stop the LFRC Oscillator to the RTC */ + uint32_t : 4; + __IOM uint32_t FOS : 1; /*!< [6..6] Oscillator switch on failure function. If this is set, + then LFRC clock source will switch from XT to RC. */ + __IOM uint32_t OSEL : 1; /*!< [7..7] Selects the RTC oscillator (1 => LFRC, 0 => XT) */ + __IOM uint32_t ACAL : 3; /*!< [10..8] Autocalibration control. This selects the source to + be used in the autocalibration flow. This flow can also + be used to measure an internal clock against an external + clock source, with the external clock normally used as + the reference. */ + } OCTRL_b; + } ; + + union { + __IOM uint32_t CLKOUT; /*!< (@ 0x00000010) CLKOUT Frequency Select */ + + struct { + __IOM uint32_t CKSEL : 6; /*!< [5..0] CLKOUT signal select */ + uint32_t : 1; + __IOM uint32_t CKEN : 1; /*!< [7..7] Enable the CLKOUT signal */ + } CLKOUT_b; + } ; + + union { + __IOM uint32_t CLKKEY; /*!< (@ 0x00000014) Key Register for Clock Control Register */ + + struct { + __IOM uint32_t CLKKEY : 32; /*!< [31..0] Key register value. */ + } CLKKEY_b; + } ; + + union { + __IOM uint32_t CCTRL; /*!< (@ 0x00000018) HFRC Clock Control */ + + struct { + __IOM uint32_t CORESEL : 1; /*!< [0..0] Core Clock divisor */ + } CCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x0000001C) Clock Generator Status */ + + struct { + __IOM uint32_t OMODE : 1; /*!< [0..0] Current RTC oscillator (1 => LFRC, 0 => XT). After an + RTC oscillator change, it may take up to 2 seconds for + this field to reflect the new oscillator. */ + __IOM uint32_t OSCF : 1; /*!< [1..1] XT Oscillator is enabled but not oscillating */ + } STATUS_b; + } ; + + union { + __IOM uint32_t HFADJ; /*!< (@ 0x00000020) HFRC Adjustment */ + + struct { + __IOM uint32_t HFADJEN : 1; /*!< [0..0] HFRC adjustment control */ + __IOM uint32_t HFADJCK : 3; /*!< [3..1] Repeat period for HFRC adjustment */ + uint32_t : 4; + __IOM uint32_t HFXTADJ : 12; /*!< [19..8] Target HFRC adjustment value. */ + __IOM uint32_t HFWARMUP : 1; /*!< [20..20] XT warmup period for HFRC adjustment */ + __IOM uint32_t HFADJGAIN : 3; /*!< [23..21] Gain control for HFRC adjustment */ + } HFADJ_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CLOCKENSTAT; /*!< (@ 0x00000028) Clock Enable Status */ + + struct { + __IOM uint32_t CLOCKENSTAT : 32; /*!< [31..0] Clock enable status */ + } CLOCKENSTAT_b; + } ; + + union { + __IOM uint32_t CLOCKEN2STAT; /*!< (@ 0x0000002C) Clock Enable Status */ + + struct { + __IOM uint32_t CLOCKEN2STAT : 32; /*!< [31..0] Clock enable status 2 */ + } CLOCKEN2STAT_b; + } ; + + union { + __IOM uint32_t CLOCKEN3STAT; /*!< (@ 0x00000030) Clock Enable Status */ + + struct { + __IOM uint32_t CLOCKEN3STAT : 32; /*!< [31..0] Clock enable status 3 */ + } CLOCKEN3STAT_b; + } ; + + union { + __IOM uint32_t FREQCTRL; /*!< (@ 0x00000034) HFRC Frequency Control register */ + + struct { + __IOM uint32_t BURSTREQ : 1; /*!< [0..0] Frequency Burst Enable Request */ + __IOM uint32_t BURSTACK : 1; /*!< [1..1] Frequency Burst Request Acknowledge. Frequency burst + requested is always acknowledged whether burst is granted + or not depending on feature enable. */ + __IOM uint32_t BURSTSTATUS : 1; /*!< [2..2] This represents frequency burst status. */ + } FREQCTRL_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t BLEBUCKTONADJ; /*!< (@ 0x0000003C) BLE BUCK TON ADJUST */ + + struct { + __IOM uint32_t TONLOWTHRESHOLD : 10; /*!< [9..0] TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) + #15(47KHz) #53(12Khz) #14D(3Khz) */ + __IOM uint32_t TONHIGHTHRESHOLD : 10; /*!< [19..10] TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) + #2A(47Khz) #A6(12Khz) #29A(3Khz) */ + __IOM uint32_t TONADJUSTPERIOD : 2; /*!< [21..20] TON ADJUST PERIOD */ + __IOM uint32_t TONADJUSTEN : 1; /*!< [22..22] TON ADJUST ENABLE */ + __IOM uint32_t ZEROLENDETECTTRIM : 4; /*!< [26..23] BLEBUCK ZERO LENGTH DETECT TRIM */ + __IOM uint32_t ZEROLENDETECTEN : 1; /*!< [27..27] BLEBUCK ZERO LENGTH DETECT ENABLE */ + } BLEBUCKTONADJ_b; + } ; + __IM uint32_t RESERVED2[48]; + + union { + __IOM uint32_t INTRPTEN; /*!< (@ 0x00000100) CLKGEN Interrupt Register: Enable */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + } INTRPTEN_b; + } ; + + union { + __IOM uint32_t INTRPTSTAT; /*!< (@ 0x00000104) CLKGEN Interrupt Register: Status */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + } INTRPTSTAT_b; + } ; + + union { + __IOM uint32_t INTRPTCLR; /*!< (@ 0x00000108) CLKGEN Interrupt Register: Clear */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + } INTRPTCLR_b; + } ; + + union { + __IOM uint32_t INTRPTSET; /*!< (@ 0x0000010C) CLKGEN Interrupt Register: Set */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + } INTRPTSET_b; + } ; +} CLKGEN_Type; /*!< Size = 272 (0x110) */ + + + +/* =========================================================================================================================== */ +/* ================ CTIMER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Counter/Timer (CTIMER) + */ + +typedef struct { /*!< (@ 0x40008000) CTIMER Structure */ + + union { + __IOM uint32_t TMR0; /*!< (@ 0x00000000) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA0 : 16; /*!< [15..0] Counter/Timer A0. */ + __IOM uint32_t CTTMRB0 : 16; /*!< [31..16] Counter/Timer B0. */ + } TMR0_b; + } ; + + union { + __IOM uint32_t CMPRA0; /*!< (@ 0x00000004) Counter/Timer A0 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A0 : 16; /*!< [15..0] Counter/Timer A0 Compare Register 0. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR1A0 : 16; /*!< [31..16] Counter/Timer A0 Compare Register 1. Holds the upper + limit for timer half A. */ + } CMPRA0_b; + } ; + + union { + __IOM uint32_t CMPRB0; /*!< (@ 0x00000008) Counter/Timer B0 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B0 : 16; /*!< [15..0] Counter/Timer B0 Compare Register 0. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR1B0 : 16; /*!< [31..16] Counter/Timer B0 Compare Register 1. Holds the upper + limit for timer half B. */ + } CMPRB0_b; + } ; + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x0000000C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA0EN : 1; /*!< [0..0] Counter/Timer A0 Enable bit. */ + __IOM uint32_t TMRA0CLK : 5; /*!< [5..1] Counter/Timer A0 Clock Select. */ + __IOM uint32_t TMRA0FN : 3; /*!< [8..6] Counter/Timer A0 Function Select. */ + __IOM uint32_t TMRA0IE0 : 1; /*!< [9..9] Counter/Timer A0 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA0IE1 : 1; /*!< [10..10] Counter/Timer A0 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA0CLR : 1; /*!< [11..11] Counter/Timer A0 Clear bit. */ + __IOM uint32_t TMRA0POL : 1; /*!< [12..12] Counter/Timer A0 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB0EN : 1; /*!< [16..16] Counter/Timer B0 Enable bit. */ + __IOM uint32_t TMRB0CLK : 5; /*!< [21..17] Counter/Timer B0 Clock Select. */ + __IOM uint32_t TMRB0FN : 3; /*!< [24..22] Counter/Timer B0 Function Select. */ + __IOM uint32_t TMRB0IE0 : 1; /*!< [25..25] Counter/Timer B0 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB0IE1 : 1; /*!< [26..26] Counter/Timer B0 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB0CLR : 1; /*!< [27..27] Counter/Timer B0 Clear bit. */ + __IOM uint32_t TMRB0POL : 1; /*!< [28..28] Counter/Timer B0 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK0 : 1; /*!< [31..31] Counter/Timer A0/B0 Link bit. */ + } CTRL0_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CMPRAUXA0; /*!< (@ 0x00000014) Counter/Timer A0 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A0 : 16; /*!< [15..0] Counter/Timer A0 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A0 : 16; /*!< [31..16] Counter/Timer A0 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA0_b; + } ; + + union { + __IOM uint32_t CMPRAUXB0; /*!< (@ 0x00000018) Counter/Timer B0 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B0 : 16; /*!< [15..0] Counter/Timer B0 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B0 : 16; /*!< [31..16] Counter/Timer B0 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB0_b; + } ; + + union { + __IOM uint32_t AUX0; /*!< (@ 0x0000001C) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA0LMT : 7; /*!< [6..0] Counter/Timer A0 Pattern Limit Count. */ + __IOM uint32_t TMRA0TRIG : 4; /*!< [10..7] Counter/Timer A0 Trigger Select. */ + __IOM uint32_t TMRA0NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA0TINV : 1; /*!< [12..12] Counter/Timer A0 Invert on trigger. */ + __IOM uint32_t TMRA0POL23 : 1; /*!< [13..13] Counter/Timer A0 Upper output polarity */ + __IOM uint32_t TMRA0EN23 : 1; /*!< [14..14] Counter/Timer A0 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB0LMT : 6; /*!< [21..16] Counter/Timer B0 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB0TRIG : 4; /*!< [26..23] Counter/Timer B0 Trigger Select. */ + __IOM uint32_t TMRB0NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB0TINV : 1; /*!< [28..28] Counter/Timer B0 Invert on trigger. */ + __IOM uint32_t TMRB0POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB0EN23 : 1; /*!< [30..30] Counter/Timer B0 Upper compare enable. */ + } AUX0_b; + } ; + + union { + __IOM uint32_t TMR1; /*!< (@ 0x00000020) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA1 : 16; /*!< [15..0] Counter/Timer A1. */ + __IOM uint32_t CTTMRB1 : 16; /*!< [31..16] Counter/Timer B1. */ + } TMR1_b; + } ; + + union { + __IOM uint32_t CMPRA1; /*!< (@ 0x00000024) Counter/Timer A1 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A1 : 16; /*!< [15..0] Counter/Timer A1 Compare Register 0. */ + __IOM uint32_t CMPR1A1 : 16; /*!< [31..16] Counter/Timer A1 Compare Register 1. */ + } CMPRA1_b; + } ; + + union { + __IOM uint32_t CMPRB1; /*!< (@ 0x00000028) Counter/Timer B1 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B1 : 16; /*!< [15..0] Counter/Timer B1 Compare Register 0. */ + __IOM uint32_t CMPR1B1 : 16; /*!< [31..16] Counter/Timer B1 Compare Register 1. */ + } CMPRB1_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x0000002C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA1EN : 1; /*!< [0..0] Counter/Timer A1 Enable bit. */ + __IOM uint32_t TMRA1CLK : 5; /*!< [5..1] Counter/Timer A1 Clock Select. */ + __IOM uint32_t TMRA1FN : 3; /*!< [8..6] Counter/Timer A1 Function Select. */ + __IOM uint32_t TMRA1IE0 : 1; /*!< [9..9] Counter/Timer A1 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA1IE1 : 1; /*!< [10..10] Counter/Timer A1 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA1CLR : 1; /*!< [11..11] Counter/Timer A1 Clear bit. */ + __IOM uint32_t TMRA1POL : 1; /*!< [12..12] Counter/Timer A1 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB1EN : 1; /*!< [16..16] Counter/Timer B1 Enable bit. */ + __IOM uint32_t TMRB1CLK : 5; /*!< [21..17] Counter/Timer B1 Clock Select. */ + __IOM uint32_t TMRB1FN : 3; /*!< [24..22] Counter/Timer B1 Function Select. */ + __IOM uint32_t TMRB1IE0 : 1; /*!< [25..25] Counter/Timer B1 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB1IE1 : 1; /*!< [26..26] Counter/Timer B1 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB1CLR : 1; /*!< [27..27] Counter/Timer B1 Clear bit. */ + __IOM uint32_t TMRB1POL : 1; /*!< [28..28] Counter/Timer B1 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK1 : 1; /*!< [31..31] Counter/Timer A1/B1 Link bit. */ + } CTRL1_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t CMPRAUXA1; /*!< (@ 0x00000034) Counter/Timer A1 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A1 : 16; /*!< [15..0] Counter/Timer A1 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A1 : 16; /*!< [31..16] Counter/Timer A1 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA1_b; + } ; + + union { + __IOM uint32_t CMPRAUXB1; /*!< (@ 0x00000038) Counter/Timer B1 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B1 : 16; /*!< [15..0] Counter/Timer B1 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B1 : 16; /*!< [31..16] Counter/Timer B1 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB1_b; + } ; + + union { + __IOM uint32_t AUX1; /*!< (@ 0x0000003C) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA1LMT : 7; /*!< [6..0] Counter/Timer A1 Pattern Limit Count. */ + __IOM uint32_t TMRA1TRIG : 4; /*!< [10..7] Counter/Timer A1 Trigger Select. */ + __IOM uint32_t TMRA1NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA1TINV : 1; /*!< [12..12] Counter/Timer A1 Invert on trigger. */ + __IOM uint32_t TMRA1POL23 : 1; /*!< [13..13] Counter/Timer A1 Upper output polarity */ + __IOM uint32_t TMRA1EN23 : 1; /*!< [14..14] Counter/Timer A1 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB1LMT : 6; /*!< [21..16] Counter/Timer B1 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB1TRIG : 4; /*!< [26..23] Counter/Timer B1 Trigger Select. */ + __IOM uint32_t TMRB1NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB1TINV : 1; /*!< [28..28] Counter/Timer B1 Invert on trigger. */ + __IOM uint32_t TMRB1POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB1EN23 : 1; /*!< [30..30] Counter/Timer B1 Upper compare enable. */ + } AUX1_b; + } ; + + union { + __IOM uint32_t TMR2; /*!< (@ 0x00000040) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA2 : 16; /*!< [15..0] Counter/Timer A2. */ + __IOM uint32_t CTTMRB2 : 16; /*!< [31..16] Counter/Timer B2. */ + } TMR2_b; + } ; + + union { + __IOM uint32_t CMPRA2; /*!< (@ 0x00000044) Counter/Timer A2 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A2 : 16; /*!< [15..0] Counter/Timer A2 Compare Register 0. */ + __IOM uint32_t CMPR1A2 : 16; /*!< [31..16] Counter/Timer A2 Compare Register 1. */ + } CMPRA2_b; + } ; + + union { + __IOM uint32_t CMPRB2; /*!< (@ 0x00000048) Counter/Timer B2 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B2 : 16; /*!< [15..0] Counter/Timer B2 Compare Register 0. */ + __IOM uint32_t CMPR1B2 : 16; /*!< [31..16] Counter/Timer B2 Compare Register 1. */ + } CMPRB2_b; + } ; + + union { + __IOM uint32_t CTRL2; /*!< (@ 0x0000004C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA2EN : 1; /*!< [0..0] Counter/Timer A2 Enable bit. */ + __IOM uint32_t TMRA2CLK : 5; /*!< [5..1] Counter/Timer A2 Clock Select. */ + __IOM uint32_t TMRA2FN : 3; /*!< [8..6] Counter/Timer A2 Function Select. */ + __IOM uint32_t TMRA2IE0 : 1; /*!< [9..9] Counter/Timer A2 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA2IE1 : 1; /*!< [10..10] Counter/Timer A2 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA2CLR : 1; /*!< [11..11] Counter/Timer A2 Clear bit. */ + __IOM uint32_t TMRA2POL : 1; /*!< [12..12] Counter/Timer A2 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB2EN : 1; /*!< [16..16] Counter/Timer B2 Enable bit. */ + __IOM uint32_t TMRB2CLK : 5; /*!< [21..17] Counter/Timer B2 Clock Select. */ + __IOM uint32_t TMRB2FN : 3; /*!< [24..22] Counter/Timer B2 Function Select. */ + __IOM uint32_t TMRB2IE0 : 1; /*!< [25..25] Counter/Timer B2 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB2IE1 : 1; /*!< [26..26] Counter/Timer B2 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB2CLR : 1; /*!< [27..27] Counter/Timer B2 Clear bit. */ + __IOM uint32_t TMRB2POL : 1; /*!< [28..28] Counter/Timer B2 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK2 : 1; /*!< [31..31] Counter/Timer A2/B2 Link bit. */ + } CTRL2_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t CMPRAUXA2; /*!< (@ 0x00000054) Counter/Timer A2 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A2 : 16; /*!< [15..0] Counter/Timer A2 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A2 : 16; /*!< [31..16] Counter/Timer A2 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA2_b; + } ; + + union { + __IOM uint32_t CMPRAUXB2; /*!< (@ 0x00000058) Counter/Timer B2 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B2 : 16; /*!< [15..0] Counter/Timer B2 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B2 : 16; /*!< [31..16] Counter/Timer B2 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB2_b; + } ; + + union { + __IOM uint32_t AUX2; /*!< (@ 0x0000005C) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA2LMT : 7; /*!< [6..0] Counter/Timer A2 Pattern Limit Count. */ + __IOM uint32_t TMRA2TRIG : 4; /*!< [10..7] Counter/Timer A2 Trigger Select. */ + __IOM uint32_t TMRA2NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA2TINV : 1; /*!< [12..12] Counter/Timer A2 Invert on trigger. */ + __IOM uint32_t TMRA2POL23 : 1; /*!< [13..13] Counter/Timer A2 Upper output polarity */ + __IOM uint32_t TMRA2EN23 : 1; /*!< [14..14] Counter/Timer A2 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB2LMT : 6; /*!< [21..16] Counter/Timer B2 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB2TRIG : 4; /*!< [26..23] Counter/Timer B2 Trigger Select. */ + __IOM uint32_t TMRB2NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB2TINV : 1; /*!< [28..28] Counter/Timer B2 Invert on trigger. */ + __IOM uint32_t TMRB2POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB2EN23 : 1; /*!< [30..30] Counter/Timer B2 Upper compare enable. */ + } AUX2_b; + } ; + + union { + __IOM uint32_t TMR3; /*!< (@ 0x00000060) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA3 : 16; /*!< [15..0] Counter/Timer A3. */ + __IOM uint32_t CTTMRB3 : 16; /*!< [31..16] Counter/Timer B3. */ + } TMR3_b; + } ; + + union { + __IOM uint32_t CMPRA3; /*!< (@ 0x00000064) Counter/Timer A3 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A3 : 16; /*!< [15..0] Counter/Timer A3 Compare Register 0. */ + __IOM uint32_t CMPR1A3 : 16; /*!< [31..16] Counter/Timer A3 Compare Register 1. */ + } CMPRA3_b; + } ; + + union { + __IOM uint32_t CMPRB3; /*!< (@ 0x00000068) Counter/Timer B3 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B3 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 0. */ + __IOM uint32_t CMPR1B3 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 1. */ + } CMPRB3_b; + } ; + + union { + __IOM uint32_t CTRL3; /*!< (@ 0x0000006C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA3EN : 1; /*!< [0..0] Counter/Timer A3 Enable bit. */ + __IOM uint32_t TMRA3CLK : 5; /*!< [5..1] Counter/Timer A3 Clock Select. */ + __IOM uint32_t TMRA3FN : 3; /*!< [8..6] Counter/Timer A3 Function Select. */ + __IOM uint32_t TMRA3IE0 : 1; /*!< [9..9] Counter/Timer A3 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA3IE1 : 1; /*!< [10..10] Counter/Timer A3 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA3CLR : 1; /*!< [11..11] Counter/Timer A3 Clear bit. */ + __IOM uint32_t TMRA3POL : 1; /*!< [12..12] Counter/Timer A3 output polarity. */ + uint32_t : 2; + __IOM uint32_t ADCEN : 1; /*!< [15..15] Special Timer A3 enable for ADC function. */ + __IOM uint32_t TMRB3EN : 1; /*!< [16..16] Counter/Timer B3 Enable bit. */ + __IOM uint32_t TMRB3CLK : 5; /*!< [21..17] Counter/Timer B3 Clock Select. */ + __IOM uint32_t TMRB3FN : 3; /*!< [24..22] Counter/Timer B3 Function Select. */ + __IOM uint32_t TMRB3IE0 : 1; /*!< [25..25] Counter/Timer B3 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB3IE1 : 1; /*!< [26..26] Counter/Timer B3 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB3CLR : 1; /*!< [27..27] Counter/Timer B3 Clear bit. */ + __IOM uint32_t TMRB3POL : 1; /*!< [28..28] Counter/Timer B3 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK3 : 1; /*!< [31..31] Counter/Timer A3/B3 Link bit. */ + } CTRL3_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t CMPRAUXA3; /*!< (@ 0x00000074) Counter/Timer A3 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A3 : 16; /*!< [15..0] Counter/Timer A3 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A3 : 16; /*!< [31..16] Counter/Timer A3 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA3_b; + } ; + + union { + __IOM uint32_t CMPRAUXB3; /*!< (@ 0x00000078) Counter/Timer B3 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B3 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B3 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB3_b; + } ; + + union { + __IOM uint32_t AUX3; /*!< (@ 0x0000007C) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA3LMT : 7; /*!< [6..0] Counter/Timer A3 Pattern Limit Count. */ + __IOM uint32_t TMRA3TRIG : 4; /*!< [10..7] Counter/Timer A3 Trigger Select. */ + __IOM uint32_t TMRA3NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA3TINV : 1; /*!< [12..12] Counter/Timer A3 Invert on trigger. */ + __IOM uint32_t TMRA3POL23 : 1; /*!< [13..13] Counter/Timer A3 Upper output polarity */ + __IOM uint32_t TMRA3EN23 : 1; /*!< [14..14] Counter/Timer A3 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB3LMT : 6; /*!< [21..16] Counter/Timer B3 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB3TRIG : 4; /*!< [26..23] Counter/Timer B3 Trigger Select. */ + __IOM uint32_t TMRB3NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB3TINV : 1; /*!< [28..28] Counter/Timer B3 Invert on trigger. */ + __IOM uint32_t TMRB3POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB3EN23 : 1; /*!< [30..30] Counter/Timer B3 Upper compare enable. */ + } AUX3_b; + } ; + + union { + __IOM uint32_t TMR4; /*!< (@ 0x00000080) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA4 : 16; /*!< [15..0] Counter/Timer A4. */ + __IOM uint32_t CTTMRB4 : 16; /*!< [31..16] Counter/Timer B4. */ + } TMR4_b; + } ; + + union { + __IOM uint32_t CMPRA4; /*!< (@ 0x00000084) Counter/Timer A4 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A4 : 16; /*!< [15..0] Counter/Timer A4 Compare Register 0. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR1A4 : 16; /*!< [31..16] Counter/Timer A4 Compare Register 1. Holds the upper + limit for timer half A. */ + } CMPRA4_b; + } ; + + union { + __IOM uint32_t CMPRB4; /*!< (@ 0x00000088) Counter/Timer B4 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B4 : 16; /*!< [15..0] Counter/Timer B4 Compare Register 0. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR1B4 : 16; /*!< [31..16] Counter/Timer B4 Compare Register 1. Holds the upper + limit for timer half B. */ + } CMPRB4_b; + } ; + + union { + __IOM uint32_t CTRL4; /*!< (@ 0x0000008C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA4EN : 1; /*!< [0..0] Counter/Timer A4 Enable bit. */ + __IOM uint32_t TMRA4CLK : 5; /*!< [5..1] Counter/Timer A4 Clock Select. */ + __IOM uint32_t TMRA4FN : 3; /*!< [8..6] Counter/Timer A4 Function Select. */ + __IOM uint32_t TMRA4IE0 : 1; /*!< [9..9] Counter/Timer A4 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA4IE1 : 1; /*!< [10..10] Counter/Timer A4 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA4CLR : 1; /*!< [11..11] Counter/Timer A4 Clear bit. */ + __IOM uint32_t TMRA4POL : 1; /*!< [12..12] Counter/Timer A4 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB4EN : 1; /*!< [16..16] Counter/Timer B4 Enable bit. */ + __IOM uint32_t TMRB4CLK : 5; /*!< [21..17] Counter/Timer B4 Clock Select. */ + __IOM uint32_t TMRB4FN : 3; /*!< [24..22] Counter/Timer B4 Function Select. */ + __IOM uint32_t TMRB4IE0 : 1; /*!< [25..25] Counter/Timer B4 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB4IE1 : 1; /*!< [26..26] Counter/Timer B4 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB4CLR : 1; /*!< [27..27] Counter/Timer B4 Clear bit. */ + __IOM uint32_t TMRB4POL : 1; /*!< [28..28] Counter/Timer B4 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK4 : 1; /*!< [31..31] Counter/Timer A4/B4 Link bit. */ + } CTRL4_b; + } ; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t CMPRAUXA4; /*!< (@ 0x00000094) Counter/Timer A4 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A4 : 16; /*!< [15..0] Counter/Timer A4 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A4 : 16; /*!< [31..16] Counter/Timer A4 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA4_b; + } ; + + union { + __IOM uint32_t CMPRAUXB4; /*!< (@ 0x00000098) Counter/Timer B4 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B4 : 16; /*!< [15..0] Counter/Timer B4 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B4 : 16; /*!< [31..16] Counter/Timer B4 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB4_b; + } ; + + union { + __IOM uint32_t AUX4; /*!< (@ 0x0000009C) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA4LMT : 7; /*!< [6..0] Counter/Timer A4 Pattern Limit Count. */ + __IOM uint32_t TMRA4TRIG : 4; /*!< [10..7] Counter/Timer A4 Trigger Select. */ + __IOM uint32_t TMRA4NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA4TINV : 1; /*!< [12..12] Counter/Timer A4 Invert on trigger. */ + __IOM uint32_t TMRA4POL23 : 1; /*!< [13..13] Counter/Timer A4 Upper output polarity */ + __IOM uint32_t TMRA4EN23 : 1; /*!< [14..14] Counter/Timer A4 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB4LMT : 6; /*!< [21..16] Counter/Timer B4 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB4TRIG : 4; /*!< [26..23] Counter/Timer B4 Trigger Select. */ + __IOM uint32_t TMRB4NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB4TINV : 1; /*!< [28..28] Counter/Timer B4 Invert on trigger. */ + __IOM uint32_t TMRB4POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB4EN23 : 1; /*!< [30..30] Counter/Timer B4 Upper compare enable. */ + } AUX4_b; + } ; + + union { + __IOM uint32_t TMR5; /*!< (@ 0x000000A0) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA5 : 16; /*!< [15..0] Counter/Timer A5. */ + __IOM uint32_t CTTMRB5 : 16; /*!< [31..16] Counter/Timer B5. */ + } TMR5_b; + } ; + + union { + __IOM uint32_t CMPRA5; /*!< (@ 0x000000A4) Counter/Timer A5 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A5 : 16; /*!< [15..0] Counter/Timer A5 Compare Register 0. */ + __IOM uint32_t CMPR1A5 : 16; /*!< [31..16] Counter/Timer A5 Compare Register 1. */ + } CMPRA5_b; + } ; + + union { + __IOM uint32_t CMPRB5; /*!< (@ 0x000000A8) Counter/Timer B5 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B5 : 16; /*!< [15..0] Counter/Timer B5 Compare Register 0. */ + __IOM uint32_t CMPR1B5 : 16; /*!< [31..16] Counter/Timer B5 Compare Register 1. */ + } CMPRB5_b; + } ; + + union { + __IOM uint32_t CTRL5; /*!< (@ 0x000000AC) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA5EN : 1; /*!< [0..0] Counter/Timer A5 Enable bit. */ + __IOM uint32_t TMRA5CLK : 5; /*!< [5..1] Counter/Timer A5 Clock Select. */ + __IOM uint32_t TMRA5FN : 3; /*!< [8..6] Counter/Timer A5 Function Select. */ + __IOM uint32_t TMRA5IE0 : 1; /*!< [9..9] Counter/Timer A5 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA5IE1 : 1; /*!< [10..10] Counter/Timer A5 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA5CLR : 1; /*!< [11..11] Counter/Timer A5 Clear bit. */ + __IOM uint32_t TMRA5POL : 1; /*!< [12..12] Counter/Timer A5 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB5EN : 1; /*!< [16..16] Counter/Timer B5 Enable bit. */ + __IOM uint32_t TMRB5CLK : 5; /*!< [21..17] Counter/Timer B5 Clock Select. */ + __IOM uint32_t TMRB5FN : 3; /*!< [24..22] Counter/Timer B5 Function Select. */ + __IOM uint32_t TMRB5IE0 : 1; /*!< [25..25] Counter/Timer B5 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB5IE1 : 1; /*!< [26..26] Counter/Timer B5 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB5CLR : 1; /*!< [27..27] Counter/Timer B5 Clear bit. */ + __IOM uint32_t TMRB5POL : 1; /*!< [28..28] Counter/Timer B5 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK5 : 1; /*!< [31..31] Counter/Timer A5/B5 Link bit. */ + } CTRL5_b; + } ; + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t CMPRAUXA5; /*!< (@ 0x000000B4) Counter/Timer A5 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A5 : 16; /*!< [15..0] Counter/Timer A5 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A5 : 16; /*!< [31..16] Counter/Timer A5 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA5_b; + } ; + + union { + __IOM uint32_t CMPRAUXB5; /*!< (@ 0x000000B8) Counter/Timer B5 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B5 : 16; /*!< [15..0] Counter/Timer B5 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B5 : 16; /*!< [31..16] Counter/Timer B5 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB5_b; + } ; + + union { + __IOM uint32_t AUX5; /*!< (@ 0x000000BC) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA5LMT : 7; /*!< [6..0] Counter/Timer A5 Pattern Limit Count. */ + __IOM uint32_t TMRA5TRIG : 4; /*!< [10..7] Counter/Timer A5 Trigger Select. */ + __IOM uint32_t TMRA5NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA5TINV : 1; /*!< [12..12] Counter/Timer A5 Invert on trigger. */ + __IOM uint32_t TMRA5POL23 : 1; /*!< [13..13] Counter/Timer A5 Upper output polarity */ + __IOM uint32_t TMRA5EN23 : 1; /*!< [14..14] Counter/Timer A5 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB5LMT : 6; /*!< [21..16] Counter/Timer B5 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB5TRIG : 4; /*!< [26..23] Counter/Timer B5 Trigger Select. */ + __IOM uint32_t TMRB5NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB5TINV : 1; /*!< [28..28] Counter/Timer B5 Invert on trigger. */ + __IOM uint32_t TMRB5POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB5EN23 : 1; /*!< [30..30] Counter/Timer B5 Upper compare enable. */ + } AUX5_b; + } ; + + union { + __IOM uint32_t TMR6; /*!< (@ 0x000000C0) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA6 : 16; /*!< [15..0] Counter/Timer A6. */ + __IOM uint32_t CTTMRB6 : 16; /*!< [31..16] Counter/Timer B6. */ + } TMR6_b; + } ; + + union { + __IOM uint32_t CMPRA6; /*!< (@ 0x000000C4) Counter/Timer A6 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A6 : 16; /*!< [15..0] Counter/Timer A6 Compare Register 0. */ + __IOM uint32_t CMPR1A6 : 16; /*!< [31..16] Counter/Timer A6 Compare Register 1. */ + } CMPRA6_b; + } ; + + union { + __IOM uint32_t CMPRB6; /*!< (@ 0x000000C8) Counter/Timer B6 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B6 : 16; /*!< [15..0] Counter/Timer B6 Compare Register 0. */ + __IOM uint32_t CMPR1B6 : 16; /*!< [31..16] Counter/Timer B6 Compare Register 1. */ + } CMPRB6_b; + } ; + + union { + __IOM uint32_t CTRL6; /*!< (@ 0x000000CC) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA6EN : 1; /*!< [0..0] Counter/Timer A6 Enable bit. */ + __IOM uint32_t TMRA6CLK : 5; /*!< [5..1] Counter/Timer A6 Clock Select. */ + __IOM uint32_t TMRA6FN : 3; /*!< [8..6] Counter/Timer A6 Function Select. */ + __IOM uint32_t TMRA6IE0 : 1; /*!< [9..9] Counter/Timer A6 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA6IE1 : 1; /*!< [10..10] Counter/Timer A6 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA6CLR : 1; /*!< [11..11] Counter/Timer A6 Clear bit. */ + __IOM uint32_t TMRA6POL : 1; /*!< [12..12] Counter/Timer A6 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB6EN : 1; /*!< [16..16] Counter/Timer B6 Enable bit. */ + __IOM uint32_t TMRB6CLK : 5; /*!< [21..17] Counter/Timer B6 Clock Select. */ + __IOM uint32_t TMRB6FN : 3; /*!< [24..22] Counter/Timer B6 Function Select. */ + __IOM uint32_t TMRB6IE0 : 1; /*!< [25..25] Counter/Timer B6 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB6IE1 : 1; /*!< [26..26] Counter/Timer B6 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB6CLR : 1; /*!< [27..27] Counter/Timer B6 Clear bit. */ + __IOM uint32_t TMRB6POL : 1; /*!< [28..28] Counter/Timer B6 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK6 : 1; /*!< [31..31] Counter/Timer A6/B6 Link bit. */ + } CTRL6_b; + } ; + __IM uint32_t RESERVED6; + + union { + __IOM uint32_t CMPRAUXA6; /*!< (@ 0x000000D4) Counter/Timer A6 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A6 : 16; /*!< [15..0] Counter/Timer A6 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A6 : 16; /*!< [31..16] Counter/Timer A6 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA6_b; + } ; + + union { + __IOM uint32_t CMPRAUXB6; /*!< (@ 0x000000D8) Counter/Timer B6 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B6 : 16; /*!< [15..0] Counter/Timer B6 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B6 : 16; /*!< [31..16] Counter/Timer B6 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB6_b; + } ; + + union { + __IOM uint32_t AUX6; /*!< (@ 0x000000DC) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA6LMT : 7; /*!< [6..0] Counter/Timer A6 Pattern Limit Count. */ + __IOM uint32_t TMRA6TRIG : 4; /*!< [10..7] Counter/Timer A6 Trigger Select. */ + __IOM uint32_t TMRA6NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA6TINV : 1; /*!< [12..12] Counter/Timer A6 Invert on trigger. */ + __IOM uint32_t TMRA6POL23 : 1; /*!< [13..13] Counter/Timer A6 Upper output polarity */ + __IOM uint32_t TMRA6EN23 : 1; /*!< [14..14] Counter/Timer A6 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB6LMT : 6; /*!< [21..16] Counter/Timer B6 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB6TRIG : 4; /*!< [26..23] Counter/Timer B6 Trigger Select. */ + __IOM uint32_t TMRB6NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB6TINV : 1; /*!< [28..28] Counter/Timer B6 Invert on trigger. */ + __IOM uint32_t TMRB6POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB6EN23 : 1; /*!< [30..30] Counter/Timer B6 Upper compare enable. */ + } AUX6_b; + } ; + + union { + __IOM uint32_t TMR7; /*!< (@ 0x000000E0) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA7 : 16; /*!< [15..0] Counter/Timer A7. */ + __IOM uint32_t CTTMRB7 : 16; /*!< [31..16] Counter/Timer B7. */ + } TMR7_b; + } ; + + union { + __IOM uint32_t CMPRA7; /*!< (@ 0x000000E4) Counter/Timer A7 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A7 : 16; /*!< [15..0] Counter/Timer A7 Compare Register 0. */ + __IOM uint32_t CMPR1A7 : 16; /*!< [31..16] Counter/Timer A7 Compare Register 1. */ + } CMPRA7_b; + } ; + + union { + __IOM uint32_t CMPRB7; /*!< (@ 0x000000E8) Counter/Timer B7 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B7 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 0. */ + __IOM uint32_t CMPR1B7 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 1. */ + } CMPRB7_b; + } ; + + union { + __IOM uint32_t CTRL7; /*!< (@ 0x000000EC) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA7EN : 1; /*!< [0..0] Counter/Timer A7 Enable bit. */ + __IOM uint32_t TMRA7CLK : 5; /*!< [5..1] Counter/Timer A7 Clock Select. */ + __IOM uint32_t TMRA7FN : 3; /*!< [8..6] Counter/Timer A7 Function Select. */ + __IOM uint32_t TMRA7IE0 : 1; /*!< [9..9] Counter/Timer A7 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA7IE1 : 1; /*!< [10..10] Counter/Timer A7 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA7CLR : 1; /*!< [11..11] Counter/Timer A7 Clear bit. */ + __IOM uint32_t TMRA7POL : 1; /*!< [12..12] Counter/Timer A7 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB7EN : 1; /*!< [16..16] Counter/Timer B7 Enable bit. */ + __IOM uint32_t TMRB7CLK : 5; /*!< [21..17] Counter/Timer B7 Clock Select. */ + __IOM uint32_t TMRB7FN : 3; /*!< [24..22] Counter/Timer B7 Function Select. */ + __IOM uint32_t TMRB7IE0 : 1; /*!< [25..25] Counter/Timer B7 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB7IE1 : 1; /*!< [26..26] Counter/Timer B7 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB7CLR : 1; /*!< [27..27] Counter/Timer B7 Clear bit. */ + __IOM uint32_t TMRB7POL : 1; /*!< [28..28] Counter/Timer B7 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK7 : 1; /*!< [31..31] Counter/Timer A7/B7 Link bit. */ + } CTRL7_b; + } ; + __IM uint32_t RESERVED7; + + union { + __IOM uint32_t CMPRAUXA7; /*!< (@ 0x000000F4) Counter/Timer A7 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A7 : 16; /*!< [15..0] Counter/Timer A7 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A7 : 16; /*!< [31..16] Counter/Timer A7 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA7_b; + } ; + + union { + __IOM uint32_t CMPRAUXB7; /*!< (@ 0x000000F8) Counter/Timer B7 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B7 : 16; /*!< [15..0] Counter/Timer B7 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B7 : 16; /*!< [31..16] Counter/Timer B7 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB7_b; + } ; + + union { + __IOM uint32_t AUX7; /*!< (@ 0x000000FC) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA7LMT : 7; /*!< [6..0] Counter/Timer A7 Pattern Limit Count. */ + __IOM uint32_t TMRA7TRIG : 4; /*!< [10..7] Counter/Timer A7 Trigger Select. */ + __IOM uint32_t TMRA7NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA7TINV : 1; /*!< [12..12] Counter/Timer A7 Invert on trigger. */ + __IOM uint32_t TMRA7POL23 : 1; /*!< [13..13] Counter/Timer A7 Upper output polarity */ + __IOM uint32_t TMRA7EN23 : 1; /*!< [14..14] Counter/Timer A7 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB7LMT : 6; /*!< [21..16] Counter/Timer B7 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB7TRIG : 4; /*!< [26..23] Counter/Timer B7 Trigger Select. */ + __IOM uint32_t TMRB7NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB7TINV : 1; /*!< [28..28] Counter/Timer B7 Invert on trigger. */ + __IOM uint32_t TMRB7POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB7EN23 : 1; /*!< [30..30] Counter/Timer B7 Upper compare enable. */ + } AUX7_b; + } ; + + union { + __IOM uint32_t GLOBEN; /*!< (@ 0x00000100) Counter/Timer Global Enable */ + + struct { + __IOM uint32_t ENA0 : 1; /*!< [0..0] Alternate enable for A0 */ + __IOM uint32_t ENB0 : 1; /*!< [1..1] Alternate enable for B0 */ + __IOM uint32_t ENA1 : 1; /*!< [2..2] Alternate enable for A1 */ + __IOM uint32_t ENB1 : 1; /*!< [3..3] Alternate enable for B1 */ + __IOM uint32_t ENA2 : 1; /*!< [4..4] Alternate enable for A2 */ + __IOM uint32_t ENB2 : 1; /*!< [5..5] Alternate enable for B2 */ + __IOM uint32_t ENA3 : 1; /*!< [6..6] Alternate enable for A3 */ + __IOM uint32_t ENB3 : 1; /*!< [7..7] Alternate enable for B3. */ + __IOM uint32_t ENA4 : 1; /*!< [8..8] Alternate enable for A4 */ + __IOM uint32_t ENB4 : 1; /*!< [9..9] Alternate enable for B4 */ + __IOM uint32_t ENA5 : 1; /*!< [10..10] Alternate enable for A5 */ + __IOM uint32_t ENB5 : 1; /*!< [11..11] Alternate enable for B5 */ + __IOM uint32_t ENA6 : 1; /*!< [12..12] Alternate enable for A6 */ + __IOM uint32_t ENB6 : 1; /*!< [13..13] Alternate enable for B6 */ + __IOM uint32_t ENA7 : 1; /*!< [14..14] Alternate enable for A7 */ + __IOM uint32_t ENB7 : 1; /*!< [15..15] Alternate enable for B7. */ + } GLOBEN_b; + } ; + + union { + __IOM uint32_t OUTCFG0; /*!< (@ 0x00000104) Counter/Timer Output Config 0 */ + + struct { + __IOM uint32_t CFG0 : 3; /*!< [2..0] Pad output 0 configuration */ + __IOM uint32_t CFG1 : 3; /*!< [5..3] Pad output 1 configuration */ + __IOM uint32_t CFG2 : 3; /*!< [8..6] Pad output 2 configuration */ + __IOM uint32_t CFG3 : 3; /*!< [11..9] Pad output 3 configuration */ + __IOM uint32_t CFG4 : 3; /*!< [14..12] Pad output 4 configuration */ + uint32_t : 1; + __IOM uint32_t CFG5 : 3; /*!< [18..16] Pad output 5 configuration */ + __IOM uint32_t CFG6 : 3; /*!< [21..19] Pad output 6 configuration */ + __IOM uint32_t CFG7 : 3; /*!< [24..22] Pad output 7 configuration */ + __IOM uint32_t CFG8 : 3; /*!< [27..25] Pad output 8 configuration */ + __IOM uint32_t CFG9 : 3; /*!< [30..28] Pad output 9 configuration */ + } OUTCFG0_b; + } ; + + union { + __IOM uint32_t OUTCFG1; /*!< (@ 0x00000108) Counter/Timer Output Config 1 */ + + struct { + __IOM uint32_t CFG10 : 3; /*!< [2..0] Pad output 10 configuration */ + __IOM uint32_t CFG11 : 3; /*!< [5..3] Pad output 11 configuration */ + __IOM uint32_t CFG12 : 3; /*!< [8..6] Pad output 12 configuration */ + __IOM uint32_t CFG13 : 3; /*!< [11..9] Pad output 13 configuration */ + __IOM uint32_t CFG14 : 3; /*!< [14..12] Pad output 14 configuration */ + uint32_t : 1; + __IOM uint32_t CFG15 : 3; /*!< [18..16] Pad output 15 configuration */ + __IOM uint32_t CFG16 : 3; /*!< [21..19] Pad output 16 configuration */ + __IOM uint32_t CFG17 : 3; /*!< [24..22] Pad output 17 configuration */ + __IOM uint32_t CFG18 : 3; /*!< [27..25] Pad output 18 configuration */ + __IOM uint32_t CFG19 : 3; /*!< [30..28] Pad output 19 configuration */ + } OUTCFG1_b; + } ; + + union { + __IOM uint32_t OUTCFG2; /*!< (@ 0x0000010C) Counter/Timer Output Config 2 */ + + struct { + __IOM uint32_t CFG20 : 3; /*!< [2..0] Pad output 20 configuration */ + __IOM uint32_t CFG21 : 3; /*!< [5..3] Pad output 21 configuration */ + __IOM uint32_t CFG22 : 3; /*!< [8..6] Pad output 22 configuration */ + __IOM uint32_t CFG23 : 3; /*!< [11..9] Pad output 23 configuration */ + __IOM uint32_t CFG24 : 3; /*!< [14..12] Pad output 24 configuration */ + uint32_t : 1; + __IOM uint32_t CFG25 : 3; /*!< [18..16] Pad output 25 configuration */ + __IOM uint32_t CFG26 : 3; /*!< [21..19] Pad output 26 configuration */ + __IOM uint32_t CFG27 : 3; /*!< [24..22] Pad output 27 configuration */ + __IOM uint32_t CFG28 : 3; /*!< [27..25] Pad output 28 configuration */ + __IOM uint32_t CFG29 : 3; /*!< [30..28] Pad output 29 configuration */ + } OUTCFG2_b; + } ; + __IM uint32_t RESERVED8; + + union { + __IOM uint32_t OUTCFG3; /*!< (@ 0x00000114) Counter/Timer Output Config 3 */ + + struct { + __IOM uint32_t CFG30 : 3; /*!< [2..0] Pad output 30 configuration */ + __IOM uint32_t CFG31 : 3; /*!< [5..3] Pad output 31 configuration */ + } OUTCFG3_b; + } ; + + union { + __IOM uint32_t INCFG; /*!< (@ 0x00000118) Counter/Timer Input Config */ + + struct { + __IOM uint32_t CFGA0 : 1; /*!< [0..0] CTIMER A0 input configuration */ + __IOM uint32_t CFGB0 : 1; /*!< [1..1] CTIMER B0 input configuration */ + __IOM uint32_t CFGA1 : 1; /*!< [2..2] CTIMER A1 input configuration */ + __IOM uint32_t CFGB1 : 1; /*!< [3..3] CTIMER B1 input configuration */ + __IOM uint32_t CFGA2 : 1; /*!< [4..4] CTIMER A2 input configuration */ + __IOM uint32_t CFGB2 : 1; /*!< [5..5] CTIMER B2 input configuration */ + __IOM uint32_t CFGA3 : 1; /*!< [6..6] CTIMER A3 input configuration */ + __IOM uint32_t CFGB3 : 1; /*!< [7..7] CTIMER B3 input configuration */ + __IOM uint32_t CFGA4 : 1; /*!< [8..8] CTIMER A4 input configuration */ + __IOM uint32_t CFGB4 : 1; /*!< [9..9] CTIMER B4 input configuration */ + __IOM uint32_t CFGA5 : 1; /*!< [10..10] CTIMER A5 input configuration */ + __IOM uint32_t CFGB5 : 1; /*!< [11..11] CTIMER B5 input configuration */ + __IOM uint32_t CFGA6 : 1; /*!< [12..12] CTIMER A6 input configuration */ + __IOM uint32_t CFGB6 : 1; /*!< [13..13] CTIMER B6 input configuration */ + __IOM uint32_t CFGA7 : 1; /*!< [14..14] CTIMER A7 input configuration */ + __IOM uint32_t CFGB7 : 1; /*!< [15..15] CTIMER B7 input configuration */ + } INCFG_b; + } ; + __IM uint32_t RESERVED9[9]; + + union { + __IOM uint32_t STCFG; /*!< (@ 0x00000140) Configuration Register */ + + struct { + __IOM uint32_t CLKSEL : 4; /*!< [3..0] Selects an appropriate clock source and divider to use + for the System Timer clock. */ + uint32_t : 4; + __IOM uint32_t COMPARE_A_EN : 1; /*!< [8..8] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_B_EN : 1; /*!< [9..9] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_C_EN : 1; /*!< [10..10] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_D_EN : 1; /*!< [11..11] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_E_EN : 1; /*!< [12..12] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_F_EN : 1; /*!< [13..13] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_G_EN : 1; /*!< [14..14] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_H_EN : 1; /*!< [15..15] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + uint32_t : 14; + __IOM uint32_t CLEAR : 1; /*!< [30..30] Set this bit to one to clear the System Timer register. + If this bit is set to '1', the system timer register will + stay cleared. It needs to be set to '0' for the system + timer to start running. */ + __IOM uint32_t FREEZE : 1; /*!< [31..31] Set this bit to one to freeze the clock input to the + COUNTER register. Once frozen, the value can be safely + written from the MCU. Unfreeze to resume. */ + } STCFG_b; + } ; + + union { + __IOM uint32_t STTMR; /*!< (@ 0x00000144) System Timer Count Register (Real Time Counter) */ + + struct { + __IOM uint32_t STTMR : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } STTMR_b; + } ; + + union { + __IOM uint32_t CAPTURECONTROL; /*!< (@ 0x00000148) Capture Control Register */ + + struct { + __IOM uint32_t CAPTURE0 : 1; /*!< [0..0] Selects whether capture is enabled for the specified + capture register. */ + __IOM uint32_t CAPTURE1 : 1; /*!< [1..1] Selects whether capture is enabled for the specified + capture register. */ + __IOM uint32_t CAPTURE2 : 1; /*!< [2..2] Selects whether capture is enabled for the specified + capture register. */ + __IOM uint32_t CAPTURE3 : 1; /*!< [3..3] Selects whether capture is enabled for the specified + capture register. */ + } CAPTURECONTROL_b; + } ; + __IM uint32_t RESERVED10; + + union { + __IOM uint32_t SCMPR0; /*!< (@ 0x00000150) Compare Register A */ + + struct { + __IOM uint32_t SCMPR0 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_A_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR0_b; + } ; + + union { + __IOM uint32_t SCMPR1; /*!< (@ 0x00000154) Compare Register B */ + + struct { + __IOM uint32_t SCMPR1 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_B_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR1_b; + } ; + + union { + __IOM uint32_t SCMPR2; /*!< (@ 0x00000158) Compare Register C */ + + struct { + __IOM uint32_t SCMPR2 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_C_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR2_b; + } ; + + union { + __IOM uint32_t SCMPR3; /*!< (@ 0x0000015C) Compare Register D */ + + struct { + __IOM uint32_t SCMPR3 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_D_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR3_b; + } ; + + union { + __IOM uint32_t SCMPR4; /*!< (@ 0x00000160) Compare Register E */ + + struct { + __IOM uint32_t SCMPR4 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_E_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR4_b; + } ; + + union { + __IOM uint32_t SCMPR5; /*!< (@ 0x00000164) Compare Register F */ + + struct { + __IOM uint32_t SCMPR5 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_F_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR5_b; + } ; + + union { + __IOM uint32_t SCMPR6; /*!< (@ 0x00000168) Compare Register G */ + + struct { + __IOM uint32_t SCMPR6 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_G_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR6_b; + } ; + + union { + __IOM uint32_t SCMPR7; /*!< (@ 0x0000016C) Compare Register H */ + + struct { + __IOM uint32_t SCMPR7 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_H_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR7_b; + } ; + __IM uint32_t RESERVED11[28]; + + union { + __IOM uint32_t SCAPT0; /*!< (@ 0x000001E0) Capture Register A */ + + struct { + __IOM uint32_t SCAPT0 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT0_b; + } ; + + union { + __IOM uint32_t SCAPT1; /*!< (@ 0x000001E4) Capture Register B */ + + struct { + __IOM uint32_t SCAPT1 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT1_b; + } ; + + union { + __IOM uint32_t SCAPT2; /*!< (@ 0x000001E8) Capture Register C */ + + struct { + __IOM uint32_t SCAPT2 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT2_b; + } ; + + union { + __IOM uint32_t SCAPT3; /*!< (@ 0x000001EC) Capture Register D */ + + struct { + __IOM uint32_t SCAPT3 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT3_b; + } ; + + union { + __IOM uint32_t SNVR0; /*!< (@ 0x000001F0) System Timer NVRAM_A Register */ + + struct { + __IOM uint32_t SNVR0 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR0_b; + } ; + + union { + __IOM uint32_t SNVR1; /*!< (@ 0x000001F4) System Timer NVRAM_B Register */ + + struct { + __IOM uint32_t SNVR1 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR1_b; + } ; + + union { + __IOM uint32_t SNVR2; /*!< (@ 0x000001F8) System Timer NVRAM_C Register */ + + struct { + __IOM uint32_t SNVR2 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR2_b; + } ; + + union { + __IOM uint32_t SNVR3; /*!< (@ 0x000001FC) System Timer NVRAM_D Register */ + + struct { + __IOM uint32_t SNVR3 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR3_b; + } ; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) Counter/Timer Interrupts: Enable */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Counter/Timer Interrupts: Status */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Counter/Timer Interrupts: Clear */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Counter/Timer Interrupts: Set */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ + } INTSET_b; + } ; + __IM uint32_t RESERVED12[60]; + + union { + __IOM uint32_t STMINTEN; /*!< (@ 0x00000300) STIMER Interrupt registers: Enable */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTEN_b; + } ; + + union { + __IOM uint32_t STMINTSTAT; /*!< (@ 0x00000304) STIMER Interrupt registers: Status */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTSTAT_b; + } ; + + union { + __IOM uint32_t STMINTCLR; /*!< (@ 0x00000308) STIMER Interrupt registers: Clear */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTCLR_b; + } ; + + union { + __IOM uint32_t STMINTSET; /*!< (@ 0x0000030C) STIMER Interrupt registers: Set */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTSET_b; + } ; +} CTIMER_Type; /*!< Size = 784 (0x310) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose IO (GPIO) + */ + +typedef struct { /*!< (@ 0x40010000) GPIO Structure */ + + union { + __IOM uint32_t PADREGA; /*!< (@ 0x00000000) Pad Configuration Register A (Pads 3-0) */ + + struct { + __IOM uint32_t PAD0PULL : 1; /*!< [0..0] Pad 0 pullup enable */ + __IOM uint32_t PAD0INPEN : 1; /*!< [1..1] Pad 0 input enable */ + __IOM uint32_t PAD0STRNG : 1; /*!< [2..2] Pad 0 drive strength */ + __IOM uint32_t PAD0FNCSEL : 3; /*!< [5..3] Pad 0 function select */ + __IOM uint32_t PAD0RSEL : 2; /*!< [7..6] Pad 0 pullup resistor selection. */ + __IOM uint32_t PAD1PULL : 1; /*!< [8..8] Pad 1 pullup enable */ + __IOM uint32_t PAD1INPEN : 1; /*!< [9..9] Pad 1 input enable */ + __IOM uint32_t PAD1STRNG : 1; /*!< [10..10] Pad 1 drive strength */ + __IOM uint32_t PAD1FNCSEL : 3; /*!< [13..11] Pad 1 function select */ + __IOM uint32_t PAD1RSEL : 2; /*!< [15..14] Pad 1 pullup resistor selection. */ + __IOM uint32_t PAD2PULL : 1; /*!< [16..16] Pad 2 pullup enable */ + __IOM uint32_t PAD2INPEN : 1; /*!< [17..17] Pad 2 input enable */ + __IOM uint32_t PAD2STRNG : 1; /*!< [18..18] Pad 2 drive strength */ + __IOM uint32_t PAD2FNCSEL : 3; /*!< [21..19] Pad 2 function select */ + uint32_t : 2; + __IOM uint32_t PAD3PULL : 1; /*!< [24..24] Pad 3 pullup enable */ + __IOM uint32_t PAD3INPEN : 1; /*!< [25..25] Pad 3 input enable. */ + __IOM uint32_t PAD3STRNG : 1; /*!< [26..26] Pad 3 drive strength. */ + __IOM uint32_t PAD3FNCSEL : 3; /*!< [29..27] Pad 3 function select */ + __IOM uint32_t PAD3PWRUP : 1; /*!< [30..30] Pad 3 VDD power switch enable */ + } PADREGA_b; + } ; + + union { + __IOM uint32_t PADREGB; /*!< (@ 0x00000004) Pad Configuration Register B (Pads 7-4) */ + + struct { + __IOM uint32_t PAD4PULL : 1; /*!< [0..0] Pad 4 pullup enable */ + __IOM uint32_t PAD4INPEN : 1; /*!< [1..1] Pad 4 input enable */ + __IOM uint32_t PAD4STRNG : 1; /*!< [2..2] Pad 4 drive strength */ + __IOM uint32_t PAD4FNCSEL : 3; /*!< [5..3] Pad 4 function select */ + uint32_t : 2; + __IOM uint32_t PAD5PULL : 1; /*!< [8..8] Pad 5 pullup enable */ + __IOM uint32_t PAD5INPEN : 1; /*!< [9..9] Pad 5 input enable */ + __IOM uint32_t PAD5STRNG : 1; /*!< [10..10] Pad 5 drive strength */ + __IOM uint32_t PAD5FNCSEL : 3; /*!< [13..11] Pad 5 function select */ + __IOM uint32_t PAD5RSEL : 2; /*!< [15..14] Pad 5 pullup resistor selection. */ + __IOM uint32_t PAD6PULL : 1; /*!< [16..16] Pad 6 pullup enable */ + __IOM uint32_t PAD6INPEN : 1; /*!< [17..17] Pad 6 input enable */ + __IOM uint32_t PAD6STRNG : 1; /*!< [18..18] Pad 6 drive strength */ + __IOM uint32_t PAD6FNCSEL : 3; /*!< [21..19] Pad 6 function select */ + __IOM uint32_t PAD6RSEL : 2; /*!< [23..22] Pad 6 pullup resistor selection. */ + __IOM uint32_t PAD7PULL : 1; /*!< [24..24] Pad 7 pullup enable */ + __IOM uint32_t PAD7INPEN : 1; /*!< [25..25] Pad 7 input enable */ + __IOM uint32_t PAD7STRNG : 1; /*!< [26..26] Pad 7 drive strength */ + __IOM uint32_t PAD7FNCSEL : 3; /*!< [29..27] Pad 7 function select */ + } PADREGB_b; + } ; + + union { + __IOM uint32_t PADREGC; /*!< (@ 0x00000008) Pad Configuration Register C (Pads 11-8) */ + + struct { + __IOM uint32_t PAD8PULL : 1; /*!< [0..0] Pad 8 pullup enable */ + __IOM uint32_t PAD8INPEN : 1; /*!< [1..1] Pad 8 input enable */ + __IOM uint32_t PAD8STRNG : 1; /*!< [2..2] Pad 8 drive strength */ + __IOM uint32_t PAD8FNCSEL : 3; /*!< [5..3] Pad 8 function select */ + __IOM uint32_t PAD8RSEL : 2; /*!< [7..6] Pad 8 pullup resistor selection. */ + __IOM uint32_t PAD9PULL : 1; /*!< [8..8] Pad 9 pullup enable */ + __IOM uint32_t PAD9INPEN : 1; /*!< [9..9] Pad 9 input enable */ + __IOM uint32_t PAD9STRNG : 1; /*!< [10..10] Pad 9 drive strength */ + __IOM uint32_t PAD9FNCSEL : 3; /*!< [13..11] Pad 9 function select */ + __IOM uint32_t PAD9RSEL : 2; /*!< [15..14] Pad 9 pullup resistor selection */ + __IOM uint32_t PAD10PULL : 1; /*!< [16..16] Pad 10 pullup enable */ + __IOM uint32_t PAD10INPEN : 1; /*!< [17..17] Pad 10 input enable */ + __IOM uint32_t PAD10STRNG : 1; /*!< [18..18] Pad 10 drive strength */ + __IOM uint32_t PAD10FNCSEL : 3; /*!< [21..19] Pad 10 function select */ + uint32_t : 2; + __IOM uint32_t PAD11PULL : 1; /*!< [24..24] Pad 11 pullup enable */ + __IOM uint32_t PAD11INPEN : 1; /*!< [25..25] Pad 11 input enable */ + __IOM uint32_t PAD11STRNG : 1; /*!< [26..26] Pad 11 drive strength */ + __IOM uint32_t PAD11FNCSEL : 3; /*!< [29..27] Pad 11 function select */ + } PADREGC_b; + } ; + + union { + __IOM uint32_t PADREGD; /*!< (@ 0x0000000C) Pad Configuration Register D (Pads 15-12) */ + + struct { + __IOM uint32_t PAD12PULL : 1; /*!< [0..0] Pad 12 pullup enable */ + __IOM uint32_t PAD12INPEN : 1; /*!< [1..1] Pad 12 input enable */ + __IOM uint32_t PAD12STRNG : 1; /*!< [2..2] Pad 12 drive strength */ + __IOM uint32_t PAD12FNCSEL : 3; /*!< [5..3] Pad 12 function select */ + uint32_t : 2; + __IOM uint32_t PAD13PULL : 1; /*!< [8..8] Pad 13 pullup enable */ + __IOM uint32_t PAD13INPEN : 1; /*!< [9..9] Pad 13 input enable */ + __IOM uint32_t PAD13STRNG : 1; /*!< [10..10] Pad 13 drive strength */ + __IOM uint32_t PAD13FNCSEL : 3; /*!< [13..11] Pad 13 function select */ + uint32_t : 2; + __IOM uint32_t PAD14PULL : 1; /*!< [16..16] Pad 14 pullup enable */ + __IOM uint32_t PAD14INPEN : 1; /*!< [17..17] Pad 14 input enable */ + __IOM uint32_t PAD14STRNG : 1; /*!< [18..18] Pad 14 drive strength */ + __IOM uint32_t PAD14FNCSEL : 3; /*!< [21..19] Pad 14 function select */ + uint32_t : 2; + __IOM uint32_t PAD15PULL : 1; /*!< [24..24] Pad 15 pullup enable */ + __IOM uint32_t PAD15INPEN : 1; /*!< [25..25] Pad 15 input enable */ + __IOM uint32_t PAD15STRNG : 1; /*!< [26..26] Pad 15 drive strength */ + __IOM uint32_t PAD15FNCSEL : 3; /*!< [29..27] Pad 15 function select */ + } PADREGD_b; + } ; + + union { + __IOM uint32_t PADREGE; /*!< (@ 0x00000010) Pad Configuration Register E (Pads 19-16) */ + + struct { + __IOM uint32_t PAD16PULL : 1; /*!< [0..0] Pad 16 pullup enable */ + __IOM uint32_t PAD16INPEN : 1; /*!< [1..1] Pad 16 input enable */ + __IOM uint32_t PAD16STRNG : 1; /*!< [2..2] Pad 16 drive strength */ + __IOM uint32_t PAD16FNCSEL : 3; /*!< [5..3] Pad 16 function select */ + uint32_t : 2; + __IOM uint32_t PAD17PULL : 1; /*!< [8..8] Pad 17 pullup enable */ + __IOM uint32_t PAD17INPEN : 1; /*!< [9..9] Pad 17 input enable */ + __IOM uint32_t PAD17STRNG : 1; /*!< [10..10] Pad 17 drive strength */ + __IOM uint32_t PAD17FNCSEL : 3; /*!< [13..11] Pad 17 function select */ + uint32_t : 2; + __IOM uint32_t PAD18PULL : 1; /*!< [16..16] Pad 18 pullup enable */ + __IOM uint32_t PAD18INPEN : 1; /*!< [17..17] Pad 18 input enable */ + __IOM uint32_t PAD18STRNG : 1; /*!< [18..18] Pad 18 drive strength */ + __IOM uint32_t PAD18FNCSEL : 3; /*!< [21..19] Pad 18 function select */ + uint32_t : 2; + __IOM uint32_t PAD19PULL : 1; /*!< [24..24] Pad 19 pullup enable */ + __IOM uint32_t PAD19INPEN : 1; /*!< [25..25] Pad 19 input enable */ + __IOM uint32_t PAD19STRNG : 1; /*!< [26..26] Pad 19 drive strength */ + __IOM uint32_t PAD19FNCSEL : 3; /*!< [29..27] Pad 19 function select */ + } PADREGE_b; + } ; + + union { + __IOM uint32_t PADREGF; /*!< (@ 0x00000014) Pad Configuration Register F (Pads 23-20) */ + + struct { + __IOM uint32_t PAD20PULL : 1; /*!< [0..0] Pad 20 pulldown enable */ + __IOM uint32_t PAD20INPEN : 1; /*!< [1..1] Pad 20 input enable */ + __IOM uint32_t PAD20STRNG : 1; /*!< [2..2] Pad 20 drive strength */ + __IOM uint32_t PAD20FNCSEL : 3; /*!< [5..3] Pad 20 function select */ + uint32_t : 2; + __IOM uint32_t PAD21PULL : 1; /*!< [8..8] Pad 21 pullup enable */ + __IOM uint32_t PAD21INPEN : 1; /*!< [9..9] Pad 21 input enable */ + __IOM uint32_t PAD21STRNG : 1; /*!< [10..10] Pad 21 drive strength */ + __IOM uint32_t PAD21FNCSEL : 3; /*!< [13..11] Pad 21 function select */ + uint32_t : 2; + __IOM uint32_t PAD22PULL : 1; /*!< [16..16] Pad 22 pullup enable */ + __IOM uint32_t PAD22INPEN : 1; /*!< [17..17] Pad 22 input enable */ + __IOM uint32_t PAD22STRNG : 1; /*!< [18..18] Pad 22 drive strength */ + __IOM uint32_t PAD22FNCSEL : 3; /*!< [21..19] Pad 22 function select */ + uint32_t : 2; + __IOM uint32_t PAD23PULL : 1; /*!< [24..24] Pad 23 pullup enable */ + __IOM uint32_t PAD23INPEN : 1; /*!< [25..25] Pad 23 input enable */ + __IOM uint32_t PAD23STRNG : 1; /*!< [26..26] Pad 23 drive strength */ + __IOM uint32_t PAD23FNCSEL : 3; /*!< [29..27] Pad 23 function select */ + } PADREGF_b; + } ; + + union { + __IOM uint32_t PADREGG; /*!< (@ 0x00000018) Pad Configuration Register G (Pads 27-24) */ + + struct { + __IOM uint32_t PAD24PULL : 1; /*!< [0..0] Pad 24 pullup enable */ + __IOM uint32_t PAD24INPEN : 1; /*!< [1..1] Pad 24 input enable */ + __IOM uint32_t PAD24STRNG : 1; /*!< [2..2] Pad 24 drive strength */ + __IOM uint32_t PAD24FNCSEL : 3; /*!< [5..3] Pad 24 function select */ + uint32_t : 2; + __IOM uint32_t PAD25PULL : 1; /*!< [8..8] Pad 25 pullup enable */ + __IOM uint32_t PAD25INPEN : 1; /*!< [9..9] Pad 25 input enable */ + __IOM uint32_t PAD25STRNG : 1; /*!< [10..10] Pad 25 drive strength */ + __IOM uint32_t PAD25FNCSEL : 3; /*!< [13..11] Pad 25 function select */ + __IOM uint32_t PAD25RSEL : 2; /*!< [15..14] Pad 25 pullup resistor selection. */ + __IOM uint32_t PAD26PULL : 1; /*!< [16..16] Pad 26 pullup enable */ + __IOM uint32_t PAD26INPEN : 1; /*!< [17..17] Pad 26 input enable */ + __IOM uint32_t PAD26STRNG : 1; /*!< [18..18] Pad 26 drive strength */ + __IOM uint32_t PAD26FNCSEL : 3; /*!< [21..19] Pad 26 function select */ + uint32_t : 2; + __IOM uint32_t PAD27PULL : 1; /*!< [24..24] Pad 27 pullup enable */ + __IOM uint32_t PAD27INPEN : 1; /*!< [25..25] Pad 27 input enable */ + __IOM uint32_t PAD27STRNG : 1; /*!< [26..26] Pad 27 drive strength */ + __IOM uint32_t PAD27FNCSEL : 3; /*!< [29..27] Pad 27 function select */ + __IOM uint32_t PAD27RSEL : 2; /*!< [31..30] Pad 27 pullup resistor selection. */ + } PADREGG_b; + } ; + + union { + __IOM uint32_t PADREGH; /*!< (@ 0x0000001C) Pad Configuration Register H (Pads 31-28) */ + + struct { + __IOM uint32_t PAD28PULL : 1; /*!< [0..0] Pad 28 pullup enable */ + __IOM uint32_t PAD28INPEN : 1; /*!< [1..1] Pad 28 input enable */ + __IOM uint32_t PAD28STRNG : 1; /*!< [2..2] Pad 28 drive strength */ + __IOM uint32_t PAD28FNCSEL : 3; /*!< [5..3] Pad 28 function select */ + uint32_t : 2; + __IOM uint32_t PAD29PULL : 1; /*!< [8..8] Pad 29 pullup enable */ + __IOM uint32_t PAD29INPEN : 1; /*!< [9..9] Pad 29 input enable */ + __IOM uint32_t PAD29STRNG : 1; /*!< [10..10] Pad 29 drive strength */ + __IOM uint32_t PAD29FNCSEL : 3; /*!< [13..11] Pad 29 function select */ + uint32_t : 2; + __IOM uint32_t PAD30PULL : 1; /*!< [16..16] Pad 30 pullup enable */ + __IOM uint32_t PAD30INPEN : 1; /*!< [17..17] Pad 30 input enable */ + __IOM uint32_t PAD30STRNG : 1; /*!< [18..18] Pad 30 drive strength */ + __IOM uint32_t PAD30FNCSEL : 3; /*!< [21..19] Pad 30 function select */ + uint32_t : 2; + __IOM uint32_t PAD31PULL : 1; /*!< [24..24] Pad 31 pullup enable */ + __IOM uint32_t PAD31INPEN : 1; /*!< [25..25] Pad 31 input enable */ + __IOM uint32_t PAD31STRNG : 1; /*!< [26..26] Pad 31 drive strength */ + __IOM uint32_t PAD31FNCSEL : 3; /*!< [29..27] Pad 31 function select */ + } PADREGH_b; + } ; + + union { + __IOM uint32_t PADREGI; /*!< (@ 0x00000020) Pad Configuration Register I (Pads 35-32) */ + + struct { + __IOM uint32_t PAD32PULL : 1; /*!< [0..0] Pad 32 pullup enable */ + __IOM uint32_t PAD32INPEN : 1; /*!< [1..1] Pad 32 input enable */ + __IOM uint32_t PAD32STRNG : 1; /*!< [2..2] Pad 32 drive strength */ + __IOM uint32_t PAD32FNCSEL : 3; /*!< [5..3] Pad 32 function select */ + uint32_t : 2; + __IOM uint32_t PAD33PULL : 1; /*!< [8..8] Pad 33 pullup enable */ + __IOM uint32_t PAD33INPEN : 1; /*!< [9..9] Pad 33 input enable */ + __IOM uint32_t PAD33STRNG : 1; /*!< [10..10] Pad 33 drive strength */ + __IOM uint32_t PAD33FNCSEL : 3; /*!< [13..11] Pad 33 function select */ + uint32_t : 2; + __IOM uint32_t PAD34PULL : 1; /*!< [16..16] Pad 34 pullup enable */ + __IOM uint32_t PAD34INPEN : 1; /*!< [17..17] Pad 34 input enable */ + __IOM uint32_t PAD34STRNG : 1; /*!< [18..18] Pad 34 drive strength */ + __IOM uint32_t PAD34FNCSEL : 3; /*!< [21..19] Pad 34 function select */ + uint32_t : 2; + __IOM uint32_t PAD35PULL : 1; /*!< [24..24] Pad 35 pullup enable */ + __IOM uint32_t PAD35INPEN : 1; /*!< [25..25] Pad 35 input enable */ + __IOM uint32_t PAD35STRNG : 1; /*!< [26..26] Pad 35 drive strength */ + __IOM uint32_t PAD35FNCSEL : 3; /*!< [29..27] Pad 35 function select */ + } PADREGI_b; + } ; + + union { + __IOM uint32_t PADREGJ; /*!< (@ 0x00000024) Pad Configuration Register J (Pads 39-36) */ + + struct { + __IOM uint32_t PAD36PULL : 1; /*!< [0..0] Pad 36 pullup enable */ + __IOM uint32_t PAD36INPEN : 1; /*!< [1..1] Pad 36 input enable */ + __IOM uint32_t PAD36STRNG : 1; /*!< [2..2] Pad 36 drive strength */ + __IOM uint32_t PAD36FNCSEL : 3; /*!< [5..3] Pad 36 function select */ + __IOM uint32_t PAD36PWRUP : 1; /*!< [6..6] Pad 36 VDD power switch enable */ + uint32_t : 1; + __IOM uint32_t PAD37PULL : 1; /*!< [8..8] Pad 37 pullup enable */ + __IOM uint32_t PAD37INPEN : 1; /*!< [9..9] Pad 37 input enable */ + __IOM uint32_t PAD37STRNG : 1; /*!< [10..10] Pad 37 drive strength */ + __IOM uint32_t PAD37FNCSEL : 3; /*!< [13..11] Pad 37 function select */ + uint32_t : 1; + __IOM uint32_t PAD37PWRDN : 1; /*!< [15..15] Pad 37 VSS power switch enable */ + __IOM uint32_t PAD38PULL : 1; /*!< [16..16] Pad 38 pullup enable */ + __IOM uint32_t PAD38INPEN : 1; /*!< [17..17] Pad 38 input enable */ + __IOM uint32_t PAD38STRNG : 1; /*!< [18..18] Pad 38 drive strength */ + __IOM uint32_t PAD38FNCSEL : 3; /*!< [21..19] Pad 38 function select */ + uint32_t : 2; + __IOM uint32_t PAD39PULL : 1; /*!< [24..24] Pad 39 pullup enable */ + __IOM uint32_t PAD39INPEN : 1; /*!< [25..25] Pad 39 input enable */ + __IOM uint32_t PAD39STRNG : 1; /*!< [26..26] Pad 39 drive strength */ + __IOM uint32_t PAD39FNCSEL : 3; /*!< [29..27] Pad 39 function select */ + __IOM uint32_t PAD39RSEL : 2; /*!< [31..30] Pad 39 pullup resistor selection. */ + } PADREGJ_b; + } ; + + union { + __IOM uint32_t PADREGK; /*!< (@ 0x00000028) Pad Configuration Register K (Pads 43-40) */ + + struct { + __IOM uint32_t PAD40PULL : 1; /*!< [0..0] Pad 40 pullup enable */ + __IOM uint32_t PAD40INPEN : 1; /*!< [1..1] Pad 40 input enable */ + __IOM uint32_t PAD40STRNG : 1; /*!< [2..2] Pad 40 drive strength */ + __IOM uint32_t PAD40FNCSEL : 3; /*!< [5..3] Pad 40 function select */ + __IOM uint32_t PAD40RSEL : 2; /*!< [7..6] Pad 40 pullup resistor selection. */ + __IOM uint32_t PAD41PULL : 1; /*!< [8..8] Pad 41 pullup enable */ + __IOM uint32_t PAD41INPEN : 1; /*!< [9..9] Pad 41 input enable */ + __IOM uint32_t PAD41STRNG : 1; /*!< [10..10] Pad 41 drive strength */ + __IOM uint32_t PAD41FNCSEL : 3; /*!< [13..11] Pad 41 function select */ + uint32_t : 1; + __IOM uint32_t PAD41PWRDN : 1; /*!< [15..15] Pad 41 power switch enable */ + __IOM uint32_t PAD42PULL : 1; /*!< [16..16] Pad 42 pullup enable */ + __IOM uint32_t PAD42INPEN : 1; /*!< [17..17] Pad 42 input enable */ + __IOM uint32_t PAD42STRNG : 1; /*!< [18..18] Pad 42 drive strength */ + __IOM uint32_t PAD42FNCSEL : 3; /*!< [21..19] Pad 42 function select */ + __IOM uint32_t PAD42RSEL : 2; /*!< [23..22] Pad 42 pullup resistor selection. */ + __IOM uint32_t PAD43PULL : 1; /*!< [24..24] Pad 43 pullup enable */ + __IOM uint32_t PAD43INPEN : 1; /*!< [25..25] Pad 43 input enable */ + __IOM uint32_t PAD43STRNG : 1; /*!< [26..26] Pad 43 drive strength */ + __IOM uint32_t PAD43FNCSEL : 3; /*!< [29..27] Pad 43 function select */ + __IOM uint32_t PAD43RSEL : 2; /*!< [31..30] Pad 43 pullup resistor selection. */ + } PADREGK_b; + } ; + + union { + __IOM uint32_t PADREGL; /*!< (@ 0x0000002C) Pad Configuration Register L (Pads 47-44) */ + + struct { + __IOM uint32_t PAD44PULL : 1; /*!< [0..0] Pad 44 pullup enable */ + __IOM uint32_t PAD44INPEN : 1; /*!< [1..1] Pad 44 input enable */ + __IOM uint32_t PAD44STRNG : 1; /*!< [2..2] Pad 44 drive strength */ + __IOM uint32_t PAD44FNCSEL : 3; /*!< [5..3] Pad 44 function select */ + uint32_t : 2; + __IOM uint32_t PAD45PULL : 1; /*!< [8..8] Pad 45 pullup enable */ + __IOM uint32_t PAD45INPEN : 1; /*!< [9..9] Pad 45 input enable */ + __IOM uint32_t PAD45STRNG : 1; /*!< [10..10] Pad 45 drive strength */ + __IOM uint32_t PAD45FNCSEL : 3; /*!< [13..11] Pad 45 function select */ + uint32_t : 2; + __IOM uint32_t PAD46PULL : 1; /*!< [16..16] Pad 46 pullup enable */ + __IOM uint32_t PAD46INPEN : 1; /*!< [17..17] Pad 46 input enable */ + __IOM uint32_t PAD46STRNG : 1; /*!< [18..18] Pad 46 drive strength */ + __IOM uint32_t PAD46FNCSEL : 3; /*!< [21..19] Pad 46 function select */ + uint32_t : 2; + __IOM uint32_t PAD47PULL : 1; /*!< [24..24] Pad 47 pullup enable */ + __IOM uint32_t PAD47INPEN : 1; /*!< [25..25] Pad 47 input enable */ + __IOM uint32_t PAD47STRNG : 1; /*!< [26..26] Pad 47 drive strength */ + __IOM uint32_t PAD47FNCSEL : 3; /*!< [29..27] Pad 47 function select */ + } PADREGL_b; + } ; + + union { + __IOM uint32_t PADREGM; /*!< (@ 0x00000030) Pad Configuration Register M (Pads 49-48) */ + + struct { + __IOM uint32_t PAD48PULL : 1; /*!< [0..0] Pad 48 pullup enable */ + __IOM uint32_t PAD48INPEN : 1; /*!< [1..1] Pad 48 input enable */ + __IOM uint32_t PAD48STRNG : 1; /*!< [2..2] Pad 48 drive strength */ + __IOM uint32_t PAD48FNCSEL : 3; /*!< [5..3] Pad 48 function select */ + __IOM uint32_t PAD48RSEL : 2; /*!< [7..6] Pad 48 pullup resistor selection. */ + __IOM uint32_t PAD49PULL : 1; /*!< [8..8] Pad 49 pullup enable */ + __IOM uint32_t PAD49INPEN : 1; /*!< [9..9] Pad 49 input enable */ + __IOM uint32_t PAD49STRNG : 1; /*!< [10..10] Pad 49 drive strength */ + __IOM uint32_t PAD49FNCSEL : 3; /*!< [13..11] Pad 49 function select */ + __IOM uint32_t PAD49RSEL : 2; /*!< [15..14] Pad 49 pullup resistor selection. */ + } PADREGM_b; + } ; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t CFGA; /*!< (@ 0x00000040) GPIO Configuration Register A (Pads 7-0) */ + + struct { + __IOM uint32_t GPIO0INCFG : 1; /*!< [0..0] GPIO0 input enable. */ + __IOM uint32_t GPIO0OUTCFG : 2; /*!< [2..1] GPIO0 output configuration. */ + __IOM uint32_t GPIO0INTD : 1; /*!< [3..3] GPIO0 interrupt direction. */ + __IOM uint32_t GPIO1INCFG : 1; /*!< [4..4] GPIO1 input enable. */ + __IOM uint32_t GPIO1OUTCFG : 2; /*!< [6..5] GPIO1 output configuration. */ + __IOM uint32_t GPIO1INTD : 1; /*!< [7..7] GPIO1 interrupt direction. */ + __IOM uint32_t GPIO2INCFG : 1; /*!< [8..8] GPIO2 input enable. */ + __IOM uint32_t GPIO2OUTCFG : 2; /*!< [10..9] GPIO2 output configuration. */ + __IOM uint32_t GPIO2INTD : 1; /*!< [11..11] GPIO2 interrupt direction. */ + __IOM uint32_t GPIO3INCFG : 1; /*!< [12..12] GPIO3 input enable. */ + __IOM uint32_t GPIO3OUTCFG : 2; /*!< [14..13] GPIO3 output configuration. */ + __IOM uint32_t GPIO3INTD : 1; /*!< [15..15] GPIO3 interrupt direction. */ + __IOM uint32_t GPIO4INCFG : 1; /*!< [16..16] GPIO4 input enable. */ + __IOM uint32_t GPIO4OUTCFG : 2; /*!< [18..17] GPIO4 output configuration. */ + __IOM uint32_t GPIO4INTD : 1; /*!< [19..19] GPIO4 interrupt direction. */ + __IOM uint32_t GPIO5INCFG : 1; /*!< [20..20] GPIO5 input enable. */ + __IOM uint32_t GPIO5OUTCFG : 2; /*!< [22..21] GPIO5 output configuration. */ + __IOM uint32_t GPIO5INTD : 1; /*!< [23..23] GPIO5 interrupt direction. */ + __IOM uint32_t GPIO6INCFG : 1; /*!< [24..24] GPIO6 input enable. */ + __IOM uint32_t GPIO6OUTCFG : 2; /*!< [26..25] GPIO6 output configuration. */ + __IOM uint32_t GPIO6INTD : 1; /*!< [27..27] GPIO6 interrupt direction. */ + __IOM uint32_t GPIO7INCFG : 1; /*!< [28..28] GPIO7 input enable. */ + __IOM uint32_t GPIO7OUTCFG : 2; /*!< [30..29] GPIO7 output configuration. */ + __IOM uint32_t GPIO7INTD : 1; /*!< [31..31] GPIO7 interrupt direction, nCE polarity. */ + } CFGA_b; + } ; + + union { + __IOM uint32_t CFGB; /*!< (@ 0x00000044) GPIO Configuration Register B (Pads 15-8) */ + + struct { + __IOM uint32_t GPIO8INCFG : 1; /*!< [0..0] GPIO8 input enable. */ + __IOM uint32_t GPIO8OUTCFG : 2; /*!< [2..1] GPIO8 output configuration. */ + __IOM uint32_t GPIO8INTD : 1; /*!< [3..3] GPIO8 interrupt direction. */ + __IOM uint32_t GPIO9INCFG : 1; /*!< [4..4] GPIO9 input enable. */ + __IOM uint32_t GPIO9OUTCFG : 2; /*!< [6..5] GPIO9 output configuration. */ + __IOM uint32_t GPIO9INTD : 1; /*!< [7..7] GPIO9 interrupt direction. */ + __IOM uint32_t GPIO10INCFG : 1; /*!< [8..8] GPIO10 input enable. */ + __IOM uint32_t GPIO10OUTCFG : 2; /*!< [10..9] GPIO10 output configuration. */ + __IOM uint32_t GPIO10INTD : 1; /*!< [11..11] GPIO10 interrupt direction. */ + __IOM uint32_t GPIO11INCFG : 1; /*!< [12..12] GPIO11 input enable. */ + __IOM uint32_t GPIO11OUTCFG : 2; /*!< [14..13] GPIO11 output configuration. */ + __IOM uint32_t GPIO11INTD : 1; /*!< [15..15] GPIO11 interrupt direction. */ + __IOM uint32_t GPIO12INCFG : 1; /*!< [16..16] GPIO12 input enable. */ + __IOM uint32_t GPIO12OUTCFG : 2; /*!< [18..17] GPIO12 output configuration. */ + __IOM uint32_t GPIO12INTD : 1; /*!< [19..19] GPIO12 interrupt direction. */ + __IOM uint32_t GPIO13INCFG : 1; /*!< [20..20] GPIO13 input enable. */ + __IOM uint32_t GPIO13OUTCFG : 2; /*!< [22..21] GPIO13 output configuration. */ + __IOM uint32_t GPIO13INTD : 1; /*!< [23..23] GPIO13 interrupt direction. */ + __IOM uint32_t GPIO14INCFG : 1; /*!< [24..24] GPIO14 input enable. */ + __IOM uint32_t GPIO14OUTCFG : 2; /*!< [26..25] GPIO14 output configuration. */ + __IOM uint32_t GPIO14INTD : 1; /*!< [27..27] GPIO14 interrupt direction. */ + __IOM uint32_t GPIO15INCFG : 1; /*!< [28..28] GPIO15 input enable. */ + __IOM uint32_t GPIO15OUTCFG : 2; /*!< [30..29] GPIO15 output configuration. */ + __IOM uint32_t GPIO15INTD : 1; /*!< [31..31] GPIO15 interrupt direction. */ + } CFGB_b; + } ; + + union { + __IOM uint32_t CFGC; /*!< (@ 0x00000048) GPIO Configuration Register C (Pads 23-16) */ + + struct { + __IOM uint32_t GPIO16INCFG : 1; /*!< [0..0] GPIO16 input enable. */ + __IOM uint32_t GPIO16OUTCFG : 2; /*!< [2..1] GPIO16 output configuration. */ + __IOM uint32_t GPIO16INTD : 1; /*!< [3..3] GPIO16 interrupt direction. */ + __IOM uint32_t GPIO17INCFG : 1; /*!< [4..4] GPIO17 input enable. */ + __IOM uint32_t GPIO17OUTCFG : 2; /*!< [6..5] GPIO17 output configuration. */ + __IOM uint32_t GPIO17INTD : 1; /*!< [7..7] GPIO17 interrupt direction. */ + __IOM uint32_t GPIO18INCFG : 1; /*!< [8..8] GPIO18 input enable. */ + __IOM uint32_t GPIO18OUTCFG : 2; /*!< [10..9] GPIO18 output configuration. */ + __IOM uint32_t GPIO18INTD : 1; /*!< [11..11] GPIO18 interrupt direction. */ + __IOM uint32_t GPIO19INCFG : 1; /*!< [12..12] GPIO19 input enable. */ + __IOM uint32_t GPIO19OUTCFG : 2; /*!< [14..13] GPIO19 output configuration. */ + __IOM uint32_t GPIO19INTD : 1; /*!< [15..15] GPIO19 interrupt direction. */ + __IOM uint32_t GPIO20INCFG : 1; /*!< [16..16] GPIO20 input enable. */ + __IOM uint32_t GPIO20OUTCFG : 2; /*!< [18..17] GPIO20 output configuration. */ + __IOM uint32_t GPIO20INTD : 1; /*!< [19..19] GPIO20 interrupt direction. */ + __IOM uint32_t GPIO21INCFG : 1; /*!< [20..20] GPIO21 input enable. */ + __IOM uint32_t GPIO21OUTCFG : 2; /*!< [22..21] GPIO21 output configuration. */ + __IOM uint32_t GPIO21INTD : 1; /*!< [23..23] GPIO21 interrupt direction. */ + __IOM uint32_t GPIO22INCFG : 1; /*!< [24..24] GPIO22 input enable. */ + __IOM uint32_t GPIO22OUTCFG : 2; /*!< [26..25] GPIO22 output configuration. */ + __IOM uint32_t GPIO22INTD : 1; /*!< [27..27] GPIO22 interrupt direction. */ + __IOM uint32_t GPIO23INCFG : 1; /*!< [28..28] GPIO23 input enable. */ + __IOM uint32_t GPIO23OUTCFG : 2; /*!< [30..29] GPIO23 output configuration. */ + __IOM uint32_t GPIO23INTD : 1; /*!< [31..31] GPIO23 interrupt direction. */ + } CFGC_b; + } ; + + union { + __IOM uint32_t CFGD; /*!< (@ 0x0000004C) GPIO Configuration Register D (Pads 31-24) */ + + struct { + __IOM uint32_t GPIO24INCFG : 1; /*!< [0..0] GPIO24 input enable. */ + __IOM uint32_t GPIO24OUTCFG : 2; /*!< [2..1] GPIO24 output configuration. */ + __IOM uint32_t GPIO24INTD : 1; /*!< [3..3] GPIO24 interrupt direction. */ + __IOM uint32_t GPIO25INCFG : 1; /*!< [4..4] GPIO25 input enable. */ + __IOM uint32_t GPIO25OUTCFG : 2; /*!< [6..5] GPIO25 output configuration. */ + __IOM uint32_t GPIO25INTD : 1; /*!< [7..7] GPIO25 interrupt direction. */ + __IOM uint32_t GPIO26INCFG : 1; /*!< [8..8] GPIO26 input enable. */ + __IOM uint32_t GPIO26OUTCFG : 2; /*!< [10..9] GPIO26 output configuration. */ + __IOM uint32_t GPIO26INTD : 1; /*!< [11..11] GPIO26 interrupt direction. */ + __IOM uint32_t GPIO27INCFG : 1; /*!< [12..12] GPIO27 input enable. */ + __IOM uint32_t GPIO27OUTCFG : 2; /*!< [14..13] GPIO27 output configuration. */ + __IOM uint32_t GPIO27INTD : 1; /*!< [15..15] GPIO27 interrupt direction. */ + __IOM uint32_t GPIO28INCFG : 1; /*!< [16..16] GPIO28 input enable. */ + __IOM uint32_t GPIO28OUTCFG : 2; /*!< [18..17] GPIO28 output configuration. */ + __IOM uint32_t GPIO28INTD : 1; /*!< [19..19] GPIO28 interrupt direction. */ + __IOM uint32_t GPIO29INCFG : 1; /*!< [20..20] GPIO29 input enable. */ + __IOM uint32_t GPIO29OUTCFG : 2; /*!< [22..21] GPIO29 output configuration. */ + __IOM uint32_t GPIO29INTD : 1; /*!< [23..23] GPIO29 interrupt direction. */ + __IOM uint32_t GPIO30INCFG : 1; /*!< [24..24] GPIO30 input enable. */ + __IOM uint32_t GPIO30OUTCFG : 2; /*!< [26..25] GPIO30 output configuration. */ + __IOM uint32_t GPIO30INTD : 1; /*!< [27..27] GPIO30 interrupt direction. */ + __IOM uint32_t GPIO31INCFG : 1; /*!< [28..28] GPIO31 input enable. */ + __IOM uint32_t GPIO31OUTCFG : 2; /*!< [30..29] GPIO31 output configuration. */ + __IOM uint32_t GPIO31INTD : 1; /*!< [31..31] GPIO31 interrupt direction. */ + } CFGD_b; + } ; + + union { + __IOM uint32_t CFGE; /*!< (@ 0x00000050) GPIO Configuration Register E (Pads 39-32) */ + + struct { + __IOM uint32_t GPIO32INCFG : 1; /*!< [0..0] GPIO32 input enable. */ + __IOM uint32_t GPIO32OUTCFG : 2; /*!< [2..1] GPIO32 output configuration. */ + __IOM uint32_t GPIO32INTD : 1; /*!< [3..3] GPIO32 interrupt direction. */ + __IOM uint32_t GPIO33INCFG : 1; /*!< [4..4] GPIO33 input enable. */ + __IOM uint32_t GPIO33OUTCFG : 2; /*!< [6..5] GPIO33 output configuration. */ + __IOM uint32_t GPIO33INTD : 1; /*!< [7..7] GPIO33 interrupt direction. */ + __IOM uint32_t GPIO34INCFG : 1; /*!< [8..8] GPIO34 input enable. */ + __IOM uint32_t GPIO34OUTCFG : 2; /*!< [10..9] GPIO34 output configuration. */ + __IOM uint32_t GPIO34INTD : 1; /*!< [11..11] GPIO34 interrupt direction. */ + __IOM uint32_t GPIO35INCFG : 1; /*!< [12..12] GPIO35 input enable. */ + __IOM uint32_t GPIO35OUTCFG : 2; /*!< [14..13] GPIO35 output configuration. */ + __IOM uint32_t GPIO35INTD : 1; /*!< [15..15] GPIO35 interrupt direction. */ + __IOM uint32_t GPIO36INCFG : 1; /*!< [16..16] GPIO36 input enable. */ + __IOM uint32_t GPIO36OUTCFG : 2; /*!< [18..17] GPIO36 output configuration. */ + __IOM uint32_t GPIO36INTD : 1; /*!< [19..19] GPIO36 interrupt direction. */ + __IOM uint32_t GPIO37INCFG : 1; /*!< [20..20] GPIO37 input enable. */ + __IOM uint32_t GPIO37OUTCFG : 2; /*!< [22..21] GPIO37 output configuration. */ + __IOM uint32_t GPIO37INTD : 1; /*!< [23..23] GPIO37 interrupt direction. */ + __IOM uint32_t GPIO38INCFG : 1; /*!< [24..24] GPIO38 input enable. */ + __IOM uint32_t GPIO38OUTCFG : 2; /*!< [26..25] GPIO38 output configuration. */ + __IOM uint32_t GPIO38INTD : 1; /*!< [27..27] GPIO38 interrupt direction. */ + __IOM uint32_t GPIO39INCFG : 1; /*!< [28..28] GPIO39 input enable. */ + __IOM uint32_t GPIO39OUTCFG : 2; /*!< [30..29] GPIO39 output configuration. */ + __IOM uint32_t GPIO39INTD : 1; /*!< [31..31] GPIO39 interrupt direction. */ + } CFGE_b; + } ; + + union { + __IOM uint32_t CFGF; /*!< (@ 0x00000054) GPIO Configuration Register F (Pads 47-40) */ + + struct { + __IOM uint32_t GPIO40INCFG : 1; /*!< [0..0] GPIO40 input enable. */ + __IOM uint32_t GPIO40OUTCFG : 2; /*!< [2..1] GPIO40 output configuration. */ + __IOM uint32_t GPIO40INTD : 1; /*!< [3..3] GPIO40 interrupt direction. */ + __IOM uint32_t GPIO41INCFG : 1; /*!< [4..4] GPIO41 input enable. */ + __IOM uint32_t GPIO41OUTCFG : 2; /*!< [6..5] GPIO41 output configuration. */ + __IOM uint32_t GPIO41INTD : 1; /*!< [7..7] GPIO41 interrupt direction. */ + __IOM uint32_t GPIO42INCFG : 1; /*!< [8..8] GPIO42 input enable. */ + __IOM uint32_t GPIO42OUTCFG : 2; /*!< [10..9] GPIO42 output configuration. */ + __IOM uint32_t GPIO42INTD : 1; /*!< [11..11] GPIO42 interrupt direction. */ + __IOM uint32_t GPIO43INCFG : 1; /*!< [12..12] GPIO43 input enable. */ + __IOM uint32_t GPIO43OUTCFG : 2; /*!< [14..13] GPIO43 output configuration. */ + __IOM uint32_t GPIO43INTD : 1; /*!< [15..15] GPIO43 interrupt direction. */ + __IOM uint32_t GPIO44INCFG : 1; /*!< [16..16] GPIO44 input enable. */ + __IOM uint32_t GPIO44OUTCFG : 2; /*!< [18..17] GPIO44 output configuration. */ + __IOM uint32_t GPIO44INTD : 1; /*!< [19..19] GPIO44 interrupt direction. */ + __IOM uint32_t GPIO45INCFG : 1; /*!< [20..20] GPIO45 input enable. */ + __IOM uint32_t GPIO45OUTCFG : 2; /*!< [22..21] GPIO45 output configuration. */ + __IOM uint32_t GPIO45INTD : 1; /*!< [23..23] GPIO45 interrupt direction. */ + __IOM uint32_t GPIO46INCFG : 1; /*!< [24..24] GPIO46 input enable. */ + __IOM uint32_t GPIO46OUTCFG : 2; /*!< [26..25] GPIO46 output configuration. */ + __IOM uint32_t GPIO46INTD : 1; /*!< [27..27] GPIO46 interrupt direction. */ + __IOM uint32_t GPIO47INCFG : 1; /*!< [28..28] GPIO47 input enable. */ + __IOM uint32_t GPIO47OUTCFG : 2; /*!< [30..29] GPIO47 output configuration. */ + __IOM uint32_t GPIO47INTD : 1; /*!< [31..31] GPIO47 interrupt direction. */ + } CFGF_b; + } ; + + union { + __IOM uint32_t CFGG; /*!< (@ 0x00000058) GPIO Configuration Register G (Pads 49-48) */ + + struct { + __IOM uint32_t GPIO48INCFG : 1; /*!< [0..0] GPIO48 input enable. */ + __IOM uint32_t GPIO48OUTCFG : 2; /*!< [2..1] GPIO48 output configuration. */ + __IOM uint32_t GPIO48INTD : 1; /*!< [3..3] GPIO48 interrupt direction. */ + __IOM uint32_t GPIO49INCFG : 1; /*!< [4..4] GPIO49 input enable. */ + __IOM uint32_t GPIO49OUTCFG : 2; /*!< [6..5] GPIO49 output configuration. */ + __IOM uint32_t GPIO49INTD : 1; /*!< [7..7] GPIO49 interrupt direction. */ + } CFGG_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t PADKEY; /*!< (@ 0x00000060) Key Register for all pad configuration registers */ + + struct { + __IOM uint32_t PADKEY : 32; /*!< [31..0] Key register value. */ + } PADKEY_b; + } ; + __IM uint32_t RESERVED2[7]; + + union { + __IOM uint32_t RDA; /*!< (@ 0x00000080) GPIO Input Register A */ + + struct { + __IOM uint32_t RDA : 32; /*!< [31..0] GPIO31-0 read data. */ + } RDA_b; + } ; + + union { + __IOM uint32_t RDB; /*!< (@ 0x00000084) GPIO Input Register B */ + + struct { + __IOM uint32_t RDB : 18; /*!< [17..0] GPIO49-32 read data. */ + } RDB_b; + } ; + + union { + __IOM uint32_t WTA; /*!< (@ 0x00000088) GPIO Output Register A */ + + struct { + __IOM uint32_t WTA : 32; /*!< [31..0] GPIO31-0 write data. */ + } WTA_b; + } ; + + union { + __IOM uint32_t WTB; /*!< (@ 0x0000008C) GPIO Output Register B */ + + struct { + __IOM uint32_t WTB : 18; /*!< [17..0] GPIO49-32 write data. */ + } WTB_b; + } ; + + union { + __IOM uint32_t WTSA; /*!< (@ 0x00000090) GPIO Output Register A Set */ + + struct { + __IOM uint32_t WTSA : 32; /*!< [31..0] Set the GPIO31-0 write data. */ + } WTSA_b; + } ; + + union { + __IOM uint32_t WTSB; /*!< (@ 0x00000094) GPIO Output Register B Set */ + + struct { + __IOM uint32_t WTSB : 18; /*!< [17..0] Set the GPIO49-32 write data. */ + } WTSB_b; + } ; + + union { + __IOM uint32_t WTCA; /*!< (@ 0x00000098) GPIO Output Register A Clear */ + + struct { + __IOM uint32_t WTCA : 32; /*!< [31..0] Clear the GPIO31-0 write data. */ + } WTCA_b; + } ; + + union { + __IOM uint32_t WTCB; /*!< (@ 0x0000009C) GPIO Output Register B Clear */ + + struct { + __IOM uint32_t WTCB : 18; /*!< [17..0] Clear the GPIO49-32 write data. */ + } WTCB_b; + } ; + + union { + __IOM uint32_t ENA; /*!< (@ 0x000000A0) GPIO Enable Register A */ + + struct { + __IOM uint32_t ENA : 32; /*!< [31..0] GPIO31-0 output enables */ + } ENA_b; + } ; + + union { + __IOM uint32_t ENB; /*!< (@ 0x000000A4) GPIO Enable Register B */ + + struct { + __IOM uint32_t ENB : 18; /*!< [17..0] GPIO49-32 output enables */ + } ENB_b; + } ; + + union { + __IOM uint32_t ENSA; /*!< (@ 0x000000A8) GPIO Enable Register A Set */ + + struct { + __IOM uint32_t ENSA : 32; /*!< [31..0] Set the GPIO31-0 output enables */ + } ENSA_b; + } ; + + union { + __IOM uint32_t ENSB; /*!< (@ 0x000000AC) GPIO Enable Register B Set */ + + struct { + __IOM uint32_t ENSB : 18; /*!< [17..0] Set the GPIO49-32 output enables */ + } ENSB_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t ENCA; /*!< (@ 0x000000B4) GPIO Enable Register A Clear */ + + struct { + __IOM uint32_t ENCA : 32; /*!< [31..0] Clear the GPIO31-0 output enables */ + } ENCA_b; + } ; + + union { + __IOM uint32_t ENCB; /*!< (@ 0x000000B8) GPIO Enable Register B Clear */ + + struct { + __IOM uint32_t ENCB : 18; /*!< [17..0] Clear the GPIO49-32 output enables */ + } ENCB_b; + } ; + + union { + __IOM uint32_t STMRCAP; /*!< (@ 0x000000BC) STIMER Capture Control */ + + struct { + __IOM uint32_t STSEL0 : 6; /*!< [5..0] STIMER Capture 0 Select. */ + __IOM uint32_t STPOL0 : 1; /*!< [6..6] STIMER Capture 0 Polarity. */ + uint32_t : 1; + __IOM uint32_t STSEL1 : 6; /*!< [13..8] STIMER Capture 1 Select. */ + __IOM uint32_t STPOL1 : 1; /*!< [14..14] STIMER Capture 1 Polarity. */ + uint32_t : 1; + __IOM uint32_t STSEL2 : 6; /*!< [21..16] STIMER Capture 2 Select. */ + __IOM uint32_t STPOL2 : 1; /*!< [22..22] STIMER Capture 2 Polarity. */ + uint32_t : 1; + __IOM uint32_t STSEL3 : 6; /*!< [29..24] STIMER Capture 3 Select. */ + __IOM uint32_t STPOL3 : 1; /*!< [30..30] STIMER Capture 3 Polarity. */ + } STMRCAP_b; + } ; + + union { + __IOM uint32_t IOM0IRQ; /*!< (@ 0x000000C0) IOM0 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM0IRQ : 6; /*!< [5..0] IOMSTR0 IRQ pad select. */ + } IOM0IRQ_b; + } ; + + union { + __IOM uint32_t IOM1IRQ; /*!< (@ 0x000000C4) IOM1 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM1IRQ : 6; /*!< [5..0] IOMSTR1 IRQ pad select. */ + } IOM1IRQ_b; + } ; + + union { + __IOM uint32_t IOM2IRQ; /*!< (@ 0x000000C8) IOM2 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM2IRQ : 6; /*!< [5..0] IOMSTR2 IRQ pad select. */ + } IOM2IRQ_b; + } ; + + union { + __IOM uint32_t IOM3IRQ; /*!< (@ 0x000000CC) IOM3 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM3IRQ : 6; /*!< [5..0] IOMSTR3 IRQ pad select. */ + } IOM3IRQ_b; + } ; + + union { + __IOM uint32_t IOM4IRQ; /*!< (@ 0x000000D0) IOM4 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM4IRQ : 6; /*!< [5..0] IOMSTR4 IRQ pad select. */ + } IOM4IRQ_b; + } ; + + union { + __IOM uint32_t IOM5IRQ; /*!< (@ 0x000000D4) IOM5 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM5IRQ : 6; /*!< [5..0] IOMSTR5 IRQ pad select. */ + } IOM5IRQ_b; + } ; + + union { + __IOM uint32_t BLEIFIRQ; /*!< (@ 0x000000D8) BLEIF Flow Control IRQ Select */ + + struct { + __IOM uint32_t BLEIFIRQ : 6; /*!< [5..0] BLEIF IRQ pad select. */ + } BLEIFIRQ_b; + } ; + + union { + __IOM uint32_t GPIOOBS; /*!< (@ 0x000000DC) GPIO Observation Mode Sample register */ + + struct { + __IOM uint32_t OBS_DATA : 16; /*!< [15..0] Sample of the data output on the GPIO observation port. + May have async sampling issues, as the data is not synronized + to the read operation. Intended for debug purposes only */ + } GPIOOBS_b; + } ; + + union { + __IOM uint32_t ALTPADCFGA; /*!< (@ 0x000000E0) Alternate Pad Configuration reg0 (Pads 0-3) */ + + struct { + __IOM uint32_t PAD0_DS1 : 1; /*!< [0..0] Pad 0 high order drive strength selection. Used in conjunction + with PAD0STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD0_SR : 1; /*!< [4..4] Pad 0 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD1_DS1 : 1; /*!< [8..8] Pad 1 high order drive strength selection. Used in conjunction + with PAD1STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD1_SR : 1; /*!< [12..12] Pad 1 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD2_DS1 : 1; /*!< [16..16] Pad 2 high order drive strength selection. Used in + conjunction with PAD2STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD2_SR : 1; /*!< [20..20] Pad 2 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD3_DS1 : 1; /*!< [24..24] Pad 3 high order drive strength selection. Used in + conjunction with PAD3STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD3_SR : 1; /*!< [28..28] Pad 3 slew rate selection. */ + } ALTPADCFGA_b; + } ; + + union { + __IOM uint32_t ALTPADCFGB; /*!< (@ 0x000000E4) Alternate Pad Configuration reg1 (Pads 4-7) */ + + struct { + __IOM uint32_t PAD4_DS1 : 1; /*!< [0..0] Pad 4 high order drive strength selection. Used in conjunction + with PAD4STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD4_SR : 1; /*!< [4..4] Pad 4 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD5_DS1 : 1; /*!< [8..8] Pad 5 high order drive strength selection. Used in conjunction + with PAD5STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD5_SR : 1; /*!< [12..12] Pad 5 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD6_DS1 : 1; /*!< [16..16] Pad 6 high order drive strength selection. Used in + conjunction with PAD6STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD6_SR : 1; /*!< [20..20] Pad 6 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD7_DS1 : 1; /*!< [24..24] Pad 7 high order drive strength selection. Used in + conjunction with PAD7STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD7_SR : 1; /*!< [28..28] Pad 7 slew rate selection. */ + } ALTPADCFGB_b; + } ; + + union { + __IOM uint32_t ALTPADCFGC; /*!< (@ 0x000000E8) Alternate Pad Configuration reg2 (Pads 8-11) */ + + struct { + __IOM uint32_t PAD8_DS1 : 1; /*!< [0..0] Pad 8 high order drive strength selection. Used in conjunction + with PAD8STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD8_SR : 1; /*!< [4..4] Pad 8 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD9_DS1 : 1; /*!< [8..8] Pad 9 high order drive strength selection. Used in conjunction + with PAD9STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD9_SR : 1; /*!< [12..12] Pad 9 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD10_DS1 : 1; /*!< [16..16] Pad 10 high order drive strength selection. Used in + conjunction with PAD10STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD10_SR : 1; /*!< [20..20] Pad 10 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD11_DS1 : 1; /*!< [24..24] Pad 11 high order drive strength selection. Used in + conjunction with PAD11STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD11_SR : 1; /*!< [28..28] Pad 11 slew rate selection. */ + } ALTPADCFGC_b; + } ; + + union { + __IOM uint32_t ALTPADCFGD; /*!< (@ 0x000000EC) Alternate Pad Configuration reg3 (Pads 12-15) */ + + struct { + __IOM uint32_t PAD12_DS1 : 1; /*!< [0..0] Pad 12 high order drive strength selection. Used in conjunction + with PAD12STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD12_SR : 1; /*!< [4..4] Pad 12 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD13_DS1 : 1; /*!< [8..8] Pad 13 high order drive strength selection. Used in conjunction + with PAD13STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD13_SR : 1; /*!< [12..12] Pad 13 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD14_DS1 : 1; /*!< [16..16] Pad 14 high order drive strength selection. Used in + conjunction with PAD14STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD14_SR : 1; /*!< [20..20] Pad 14 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD15_DS1 : 1; /*!< [24..24] Pad 15 high order drive strength selection. Used in + conjunction with PAD15STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD15_SR : 1; /*!< [28..28] Pad 15 slew rate selection. */ + } ALTPADCFGD_b; + } ; + + union { + __IOM uint32_t ALTPADCFGE; /*!< (@ 0x000000F0) Alternate Pad Configuration reg4 (Pads 16-19) */ + + struct { + __IOM uint32_t PAD16_DS1 : 1; /*!< [0..0] Pad 16 high order drive strength selection. Used in conjunction + with PAD16STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD16_SR : 1; /*!< [4..4] Pad 16 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD17_DS1 : 1; /*!< [8..8] Pad 17 high order drive strength selection. Used in conjunction + with PAD17STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD17_SR : 1; /*!< [12..12] Pad 17 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD18_DS1 : 1; /*!< [16..16] Pad 18 high order drive strength selection. Used in + conjunction with PAD18STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD18_SR : 1; /*!< [20..20] Pad 18 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD19_DS1 : 1; /*!< [24..24] Pad 19 high order drive strength selection. Used in + conjunction with PAD19STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD19_SR : 1; /*!< [28..28] Pad 19 slew rate selection. */ + } ALTPADCFGE_b; + } ; + + union { + __IOM uint32_t ALTPADCFGF; /*!< (@ 0x000000F4) Alternate Pad Configuration reg5 (Pads 20-23) */ + + struct { + __IOM uint32_t PAD20_DS1 : 1; /*!< [0..0] Pad 20 high order drive strength selection. Used in conjunction + with PAD20STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD20_SR : 1; /*!< [4..4] Pad 20 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD21_DS1 : 1; /*!< [8..8] Pad 21 high order drive strength selection. Used in conjunction + with PAD21STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD21_SR : 1; /*!< [12..12] Pad 21 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD22_DS1 : 1; /*!< [16..16] Pad 22 high order drive strength selection. Used in + conjunction with PAD22STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD22_SR : 1; /*!< [20..20] Pad 22 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD23_DS1 : 1; /*!< [24..24] Pad 23 high order drive strength selection. Used in + conjunction with PAD23STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD23_SR : 1; /*!< [28..28] Pad 23 slew rate selection. */ + } ALTPADCFGF_b; + } ; + + union { + __IOM uint32_t ALTPADCFGG; /*!< (@ 0x000000F8) Alternate Pad Configuration reg6 (Pads 24-27) */ + + struct { + __IOM uint32_t PAD24_DS1 : 1; /*!< [0..0] Pad 24 high order drive strength selection. Used in conjunction + with PAD24STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD24_SR : 1; /*!< [4..4] Pad 24 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD25_DS1 : 1; /*!< [8..8] Pad 25 high order drive strength selection. Used in conjunction + with PAD25STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD25_SR : 1; /*!< [12..12] Pad 25 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD26_DS1 : 1; /*!< [16..16] Pad 26 high order drive strength selection. Used in + conjunction with PAD26STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD26_SR : 1; /*!< [20..20] Pad 26 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD27_DS1 : 1; /*!< [24..24] Pad 27 high order drive strength selection. Used in + conjunction with PAD27STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD27_SR : 1; /*!< [28..28] Pad 27 slew rate selection. */ + } ALTPADCFGG_b; + } ; + + union { + __IOM uint32_t ALTPADCFGH; /*!< (@ 0x000000FC) Alternate Pad Configuration reg7 (Pads 28-31) */ + + struct { + __IOM uint32_t PAD28_DS1 : 1; /*!< [0..0] Pad 28 high order drive strength selection. Used in conjunction + with PAD28STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD28_SR : 1; /*!< [4..4] Pad 28 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD29_DS1 : 1; /*!< [8..8] Pad 29 high order drive strength selection. Used in conjunction + with PAD29STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD29_SR : 1; /*!< [12..12] Pad 29 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD30_DS1 : 1; /*!< [16..16] Pad 30 high order drive strength selection. Used in + conjunction with PAD30STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD30_SR : 1; /*!< [20..20] Pad 30 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD31_DS1 : 1; /*!< [24..24] Pad 31 high order drive strength selection. Used in + conjunction with PAD31STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD31_SR : 1; /*!< [28..28] Pad 31 slew rate selection. */ + } ALTPADCFGH_b; + } ; + + union { + __IOM uint32_t ALTPADCFGI; /*!< (@ 0x00000100) Alternate Pad Configuration reg8 (Pads 32-35) */ + + struct { + __IOM uint32_t PAD32_DS1 : 1; /*!< [0..0] Pad 32 high order drive strength selection. Used in conjunction + with PAD32STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD32_SR : 1; /*!< [4..4] Pad 32 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD33_DS1 : 1; /*!< [8..8] Pad 33 high order drive strength selection. Used in conjunction + with PAD33STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD33_SR : 1; /*!< [12..12] Pad 33 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD34_DS1 : 1; /*!< [16..16] Pad 34 high order drive strength selection. Used in + conjunction with PAD34STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD34_SR : 1; /*!< [20..20] Pad 34 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD35_DS1 : 1; /*!< [24..24] Pad 35 high order drive strength selection. Used in + conjunction with PAD35STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD35_SR : 1; /*!< [28..28] Pad 35 slew rate selection. */ + } ALTPADCFGI_b; + } ; + + union { + __IOM uint32_t ALTPADCFGJ; /*!< (@ 0x00000104) Alternate Pad Configuration reg9 (Pads 36-39) */ + + struct { + __IOM uint32_t PAD36_DS1 : 1; /*!< [0..0] Pad 36 high order drive strength selection. Used in conjunction + with PAD36STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD36_SR : 1; /*!< [4..4] Pad 36 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD37_DS1 : 1; /*!< [8..8] Pad 37 high order drive strength selection. Used in conjunction + with PAD37STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD37_SR : 1; /*!< [12..12] Pad 37 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD38_DS1 : 1; /*!< [16..16] Pad 38 high order drive strength selection. Used in + conjunction with PAD38STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD38_SR : 1; /*!< [20..20] Pad 38 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD39_DS1 : 1; /*!< [24..24] Pad 39 high order drive strength selection. Used in + conjunction with PAD39STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD39_SR : 1; /*!< [28..28] Pad 39 slew rate selection. */ + } ALTPADCFGJ_b; + } ; + + union { + __IOM uint32_t ALTPADCFGK; /*!< (@ 0x00000108) Alternate Pad Configuration reg10 (Pads 40-43) */ + + struct { + __IOM uint32_t PAD40_DS1 : 1; /*!< [0..0] Pad 40 high order drive strength selection. Used in conjunction + with PAD40STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD40_SR : 1; /*!< [4..4] Pad 40 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD41_DS1 : 1; /*!< [8..8] Pad 41 high order drive strength selection. Used in conjunction + with PAD41STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD41_SR : 1; /*!< [12..12] Pad 41 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD42_DS1 : 1; /*!< [16..16] Pad 42 high order drive strength selection. Used in + conjunction with PAD42STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD42_SR : 1; /*!< [20..20] Pad 42 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD43_DS1 : 1; /*!< [24..24] Pad 43 high order drive strength selection. Used in + conjunction with PAD43STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD43_SR : 1; /*!< [28..28] Pad 43 slew rate selection. */ + } ALTPADCFGK_b; + } ; + + union { + __IOM uint32_t ALTPADCFGL; /*!< (@ 0x0000010C) Alternate Pad Configuration reg11 (Pads 44-47) */ + + struct { + __IOM uint32_t PAD44_DS1 : 1; /*!< [0..0] Pad 44 high order drive strength selection. Used in conjunction + with PAD44STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD44_SR : 1; /*!< [4..4] Pad 44 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD45_DS1 : 1; /*!< [8..8] Pad 45 high order drive strength selection. Used in conjunction + with PAD45STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD45_SR : 1; /*!< [12..12] Pad 45 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD46_DS1 : 1; /*!< [16..16] Pad 46 high order drive strength selection. Used in + conjunction with PAD46STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD46_SR : 1; /*!< [20..20] Pad 46 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD47_DS1 : 1; /*!< [24..24] Pad 47 high order drive strength selection. Used in + conjunction with PAD47STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD47_SR : 1; /*!< [28..28] Pad 47 slew rate selection. */ + } ALTPADCFGL_b; + } ; + + union { + __IOM uint32_t ALTPADCFGM; /*!< (@ 0x00000110) Alternate Pad Configuration reg12 (Pads 48-49) */ + + struct { + __IOM uint32_t PAD48_DS1 : 1; /*!< [0..0] Pad 48 high order drive strength selection. Used in conjunction + with PAD48STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD48_SR : 1; /*!< [4..4] Pad 48 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD49_DS1 : 1; /*!< [8..8] Pad 49 high order drive strength selection. Used in conjunction + with PAD49STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD49_SR : 1; /*!< [12..12] Pad 49 slew rate selection. */ + } ALTPADCFGM_b; + } ; + + union { + __IOM uint32_t SCDET; /*!< (@ 0x00000114) SCARD Card Detect select */ + + struct { + __IOM uint32_t SCDET : 6; /*!< [5..0] SCARD card detect pad select. */ + } SCDET_b; + } ; + + union { + __IOM uint32_t CTENCFG; /*!< (@ 0x00000118) Counter/Timer Enable Config */ + + struct { + __IOM uint32_t EN0 : 1; /*!< [0..0] CT0 Enable */ + __IOM uint32_t EN1 : 1; /*!< [1..1] CT1 Enable */ + __IOM uint32_t EN2 : 1; /*!< [2..2] CT2 Enable */ + __IOM uint32_t EN3 : 1; /*!< [3..3] CT3 Enable */ + __IOM uint32_t EN4 : 1; /*!< [4..4] CT4 Enable */ + __IOM uint32_t EN5 : 1; /*!< [5..5] CT5 Enable */ + __IOM uint32_t EN6 : 1; /*!< [6..6] CT6 Enable */ + __IOM uint32_t EN7 : 1; /*!< [7..7] CT7 Enable */ + __IOM uint32_t EN8 : 1; /*!< [8..8] CT8 Enable */ + __IOM uint32_t EN9 : 1; /*!< [9..9] CT9 Enable */ + __IOM uint32_t EN10 : 1; /*!< [10..10] CT10 Enable */ + __IOM uint32_t EN11 : 1; /*!< [11..11] CT11 Enable */ + __IOM uint32_t EN12 : 1; /*!< [12..12] CT12 Enable */ + __IOM uint32_t EN13 : 1; /*!< [13..13] CT13 Enable */ + __IOM uint32_t EN14 : 1; /*!< [14..14] CT14 Enable */ + __IOM uint32_t EN15 : 1; /*!< [15..15] CT15 Enable */ + __IOM uint32_t EN16 : 1; /*!< [16..16] CT16 Enable */ + __IOM uint32_t EN17 : 1; /*!< [17..17] CT17 Enable */ + __IOM uint32_t EN18 : 1; /*!< [18..18] CT18 Enable */ + __IOM uint32_t EN19 : 1; /*!< [19..19] CT19 Enable */ + __IOM uint32_t EN20 : 1; /*!< [20..20] CT20 Enable */ + __IOM uint32_t EN21 : 1; /*!< [21..21] CT21 Enable */ + __IOM uint32_t EN22 : 1; /*!< [22..22] CT22 Enable */ + __IOM uint32_t EN23 : 1; /*!< [23..23] CT23 Enable */ + __IOM uint32_t EN24 : 1; /*!< [24..24] CT24 Enable */ + __IOM uint32_t EN25 : 1; /*!< [25..25] CT25 Enable */ + __IOM uint32_t EN26 : 1; /*!< [26..26] CT26 Enable */ + __IOM uint32_t EN27 : 1; /*!< [27..27] CT27 Enable */ + __IOM uint32_t EN28 : 1; /*!< [28..28] CT28 Enable */ + __IOM uint32_t EN29 : 1; /*!< [29..29] CT29 Enable */ + __IOM uint32_t EN30 : 1; /*!< [30..30] CT30 Enable */ + __IOM uint32_t EN31 : 1; /*!< [31..31] CT31 Enable */ + } CTENCFG_b; + } ; + __IM uint32_t RESERVED4[57]; + + union { + __IOM uint32_t INT0EN; /*!< (@ 0x00000200) GPIO Interrupt Registers 31-0: Enable */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0EN_b; + } ; + + union { + __IOM uint32_t INT0STAT; /*!< (@ 0x00000204) GPIO Interrupt Registers 31-0: Status */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0STAT_b; + } ; + + union { + __IOM uint32_t INT0CLR; /*!< (@ 0x00000208) GPIO Interrupt Registers 31-0: Clear */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0CLR_b; + } ; + + union { + __IOM uint32_t INT0SET; /*!< (@ 0x0000020C) GPIO Interrupt Registers 31-0: Set */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0SET_b; + } ; + + union { + __IOM uint32_t INT1EN; /*!< (@ 0x00000210) GPIO Interrupt Registers 49-32: Enable */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1EN_b; + } ; + + union { + __IOM uint32_t INT1STAT; /*!< (@ 0x00000214) GPIO Interrupt Registers 49-32: Status */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1STAT_b; + } ; + + union { + __IOM uint32_t INT1CLR; /*!< (@ 0x00000218) GPIO Interrupt Registers 49-32: Clear */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1CLR_b; + } ; + + union { + __IOM uint32_t INT1SET; /*!< (@ 0x0000021C) GPIO Interrupt Registers 49-32: Set */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1SET_b; + } ; +} GPIO_Type; /*!< Size = 544 (0x220) */ + + + +/* =========================================================================================================================== */ +/* ================ IOM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO Peripheral Master (IOM0) + */ + +typedef struct { /*!< (@ 0x50004000) IOM0 Structure */ + + union { + __IOM uint32_t FIFO; /*!< (@ 0x00000000) FIFO Access Port */ + + struct { + __IOM uint32_t FIFO : 32; /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return + valid information. */ + } FIFO_b; + } ; + __IM uint32_t RESERVED[63]; + + union { + __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) FIFO size and remaining slots open values */ + + struct { + __IOM uint32_t FIFO0SIZ : 8; /*!< [7..0] The number of valid data bytes currently in the FIFO + 0 (written by MCU, read by interface) */ + __IOM uint32_t FIFO0REM : 8; /*!< [15..8] The number of remaining data bytes slots currently in + FIFO 0 (written by MCU, read by interface) */ + __IOM uint32_t FIFO1SIZ : 8; /*!< [23..16] The number of valid data bytes currently in FIFO 1 + (written by interface, read by MCU) */ + __IOM uint32_t FIFO1REM : 8; /*!< [31..24] The number of remaining data bytes slots currently + in FIFO 1 (written by interface, read by MCU) */ + } FIFOPTR_b; + } ; + + union { + __IOM uint32_t FIFOTHR; /*!< (@ 0x00000104) FIFO Threshold Configuration */ + + struct { + __IOM uint32_t FIFORTHR : 6; /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable + the read FIFO level from activating the threshold interrupt. + If this field is non-zero, it will trigger a threshold + interrupt when the read fifo contains FIFORTHR valid bytes + of data, as indicated by the FIFO1SIZ field. This is intended + to signal when a data transfer of FIFORTHR bytes can be + done from the IOM module to the host via the read fifo + to support large IOM read operations. */ + uint32_t : 2; + __IOM uint32_t FIFOWTHR : 6; /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable + the write FIFO level from activating the threshold interrupt. + If this field is non-zero, it will trigger a threshold + interrupt when the write fifo contains FIFOWTHR free bytes, + as indicated by the FIFO0REM field. This is intended to + signal when a transfer of FIFOWTHR bytes can be done from + the host to the IOM write fifo to support large IOM write + operations. */ + } FIFOTHR_b; + } ; + + union { + __IOM uint32_t FIFOPOP; /*!< (@ 0x00000108) FIFO POP register */ + + struct { + __IOM uint32_t FIFODOUT : 32; /*!< [31..0] This register will return the read data indicated by + the current read pointer on reads. If the POPWR control + bit in the FIFOCTRL register is reset (0), the fifo read + pointer will be advanced by one word as a result of the + read.If the POPWR bit is set (1), the fifo read pointer + will only be advanced after a write operation to this register. + The write data is ignored for this register.If less than + a even word multiple is available, and the command is completed, + the module will return the word containing */ + } FIFOPOP_b; + } ; + + union { + __IOM uint32_t FIFOPUSH; /*!< (@ 0x0000010C) FIFO PUSH register */ + + struct { + __IOM uint32_t FIFODIN : 32; /*!< [31..0] This register is used to write the FIFORAM in FIFO mode + and will cause a push event to occur to the next open slot + within the FIFORAM. Writing to this register will cause + the write point to increment by 1 word(4 bytes). */ + } FIFOPUSH_b; + } ; + + union { + __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000110) FIFO Control Register */ + + struct { + __IOM uint32_t POPWR : 1; /*!< [0..0] Selects the mode in which 'pop' events are done for the + fifo read operations. A value of '1' will prevent a pop + event on a read operation, and will require a write to + the FIFOPOP register to create a pop event.A value of '0' + in this register will allow a pop event to occur on the + read of the FIFOPOP register, and may cause inadvertant + fifo pops when used in a debugging mode. */ + __IOM uint32_t FIFORSTN : 1; /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset + fifo, and then write to 1 to remove the reset. */ + } FIFOCTRL_b; + } ; + + union { + __IOM uint32_t FIFOLOC; /*!< (@ 0x00000114) FIFO Pointers */ + + struct { + __IOM uint32_t FIFOWPTR : 4; /*!< [3..0] Current FIFO write pointer. Value is the index into the + outgoing FIFO (FIFO0), which is used during write operations + to external devices. */ + uint32_t : 4; + __IOM uint32_t FIFORPTR : 4; /*!< [11..8] Current FIFO read pointer. Used to index into the incoming + FIFO (FIFO1), which is used to store read data returned + from external devices during a read operation. */ + } FIFOLOC_b; + } ; + __IM uint32_t RESERVED1[58]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Master Interrupts: Enable */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software + tries to pop from an empty fifo. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has + been received on the I2C bus. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master + on the bus has signaled a START command. */ + __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master + on the bus has signaled a STOP command. */ + __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration + is enabled and has been lost to another master on the bus. */ + __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with + the register address bit 0 set to 1. The low address bits + in the CQ address fields are unused and bit 0 can be used + to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Master Interrupts: Status */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software + tries to pop from an empty fifo. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has + been received on the I2C bus. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master + on the bus has signaled a START command. */ + __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master + on the bus has signaled a STOP command. */ + __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration + is enabled and has been lost to another master on the bus. */ + __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with + the register address bit 0 set to 1. The low address bits + in the CQ address fields are unused and bit 0 can be used + to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Master Interrupts: Clear */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software + tries to pop from an empty fifo. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has + been received on the I2C bus. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master + on the bus has signaled a START command. */ + __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master + on the bus has signaled a STOP command. */ + __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration + is enabled and has been lost to another master on the bus. */ + __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with + the register address bit 0 set to 1. The low address bits + in the CQ address fields are unused and bit 0 can be used + to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Master Interrupts: Set */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software + tries to pop from an empty fifo. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has + been received on the I2C bus. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master + on the bus has signaled a START command. */ + __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master + on the bus has signaled a STOP command. */ + __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration + is enabled and has been lost to another master on the bus. */ + __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with + the register address bit 0 set to 1. The low address bits + in the CQ address fields are unused and bit 0 can be used + to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ + } INTSET_b; + } ; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x00000210) I/O Clock Configuration */ + + struct { + __IOM uint32_t IOCLKEN : 1; /*!< [0..0] Enable for the interface clock. Must be enabled prior + to executing any IO operations. */ + uint32_t : 7; + __IOM uint32_t FSEL : 3; /*!< [10..8] Select the input clock frequency. */ + __IOM uint32_t DIV3 : 1; /*!< [11..11] Enable divide by 3 of the source IOCLK. Division by + 3 is done before the DIVEN programmable divider, and if + enabledwill provide the divided by 3 clock as the source + to the programmable divider. */ + __IOM uint32_t DIVEN : 1; /*!< [12..12] Enable clock division by TOTPER and LOWPER */ + uint32_t : 3; + __IOM uint32_t LOWPER : 8; /*!< [23..16] Clock low clock count minus 1. This provides the number + of clocks the divided clock will be low when the DIVEN + = 1.Only applicable when DIVEN = 1. */ + __IOM uint32_t TOTPER : 8; /*!< [31..24] Clock total clock count minus 1. This provides the + total period of the divided clock -1 when the DIVEN is + active. Thesource clock is selected by FSEL. Only applicable + when DIVEN = 1. */ + } CLKCFG_b; + } ; + + union { + __IOM uint32_t SUBMODCTRL; /*!< (@ 0x00000214) Submodule control */ + + struct { + __IOM uint32_t SMOD0EN : 1; /*!< [0..0] Submodule 0 enable (1) or disable (0) */ + __IOM uint32_t SMOD0TYPE : 3; /*!< [3..1] Submodule 0 module type. This is the SPI Master interface. */ + __IOM uint32_t SMOD1EN : 1; /*!< [4..4] Submodule 1 enable (1) or disable (0) */ + __IOM uint32_t SMOD1TYPE : 3; /*!< [7..5] Submodule 0 module type. This is the I2C Master interface */ + } SUBMODCTRL_b; + } ; + + union { + __IOM uint32_t CMD; /*!< (@ 0x00000218) Command and offset Register */ + + struct { + __IOM uint32_t CMD : 5; /*!< [4..0] Command for submodule. */ + __IOM uint32_t OFFSETCNT : 2; /*!< [6..5] Number of offset bytes to use for the command - 0, 1, + 2, 3 are valid selections. The second (byte 1) and third + byte (byte 2) are read from the OFFSETHI register, and + the low order byte is pulled from this register in the + OFFSETLO field.Offset bytes are transmitted highest byte + first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted + first, then OFFSETHI[7:0] then OFFSETLO.If offsetcnt == + 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.If + offsetcnt == 1, only OFFSETLO will be transmitted. */ + __IOM uint32_t CONT : 1; /*!< [7..7] Contine to hold the bus after the current transaction + if set to a 1 with a new command issued. */ + __IOM uint32_t TSIZE : 12; /*!< [19..8] Defines the transaction size in bytes. The offset transfer + is not included in this size. */ + __IOM uint32_t CMDSEL : 2; /*!< [21..20] Command Specific selection information. Not used in + Master I2C. Used as CEn select for Master SPI transactions */ + uint32_t : 2; + __IOM uint32_t OFFSETLO : 8; /*!< [31..24] This register holds the low order byte of offset to + be used in the transaction. The number of offset bytes + to use is set with bits 1:0 of the command. */ + } CMD_b; + } ; + + union { + __IOM uint32_t DCX; /*!< (@ 0x0000021C) DCX Control Register */ + + struct { + __IOM uint32_t CE0OUT : 1; /*!< [0..0] Revision A: MUST NOT be programmed! Revision B: Enable + DCX output for CE0 output. */ + __IOM uint32_t CE1OUT : 1; /*!< [1..1] Revision A: MUST NOT be programmed! Revision B: Enable + DCX output for CE1 output. */ + __IOM uint32_t CE2OUT : 1; /*!< [2..2] Revision A: MUST NOT be programmed! Revision B: Enable + DCX output for CE2 output. */ + __IOM uint32_t CE3OUT : 1; /*!< [3..3] Revision A: MUST NOT be programmed! Revision B: Enable + DCX output for CE3 output. */ + __IOM uint32_t DCXEN : 1; /*!< [4..4] Revision A: MUST NOT be programmed! Revision B: Bit 4: + DCX Signaling Enable via other CE signals. The selected + DCX signal (unused CE pin) will be driven low during write + of offset byte, and high during transmission of data bytes. */ + } DCX_b; + } ; + + union { + __IOM uint32_t OFFSETHI; /*!< (@ 0x00000220) High order 2 bytes of 3 byte offset for IO transaction */ + + struct { + __IOM uint32_t OFFSETHI : 16; /*!< [15..0] Holds the high order 2 bytes of the 3 byte addressing/offset + field to use with IO commands. The number of offset bytes + to use is specified in the command register */ + } OFFSETHI_b; + } ; + + union { + __IOM uint32_t CMDSTAT; /*!< (@ 0x00000224) Command status */ + + struct { + __IOM uint32_t CCMD : 5; /*!< [4..0] current command that is being executed */ + __IOM uint32_t CMDSTAT : 3; /*!< [7..5] The current status of the command execution. */ + __IOM uint32_t CTSIZE : 12; /*!< [19..8] The current number of bytes still to be transferred + with this command. This field will count down to zero. */ + } CMDSTAT_b; + } ; + __IM uint32_t RESERVED2[6]; + + union { + __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */ + + struct { + __IOM uint32_t DCMDCMPEN : 1; /*!< [0..0] Trigger DMA upon command complete. Enables the trigger + of the DMA when a command is completed. When this event + is triggered, the number of words transferred will be the + lesser of the remaining TOTCOUNT bytes, or */ + __IOM uint32_t DTHREN : 1; /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations + (IOM writes), the trigger will assert when the write FIFO + has (WTHR/4) number of words free in the write FIFO, and + will transfer (WTHR/4) number of wordsor, if the number + of words left to transfer is less than the WTHR value, + will transfer the remaining byte count.For P2M DMA operations, + the trigger will assert when the read FIFO has (RTHR/4) + words available in the read FIFO, and will transfer (RTHR/4) + words to SRAM. This trigger will NOT asser */ + } DMATRIGEN_b; + } ; + + union { + __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */ + + struct { + __IOM uint32_t DCMDCMP : 1; /*!< [0..0] Triggered DMA from Command complete event. Bit is read + only and can be cleared by disabling the DCMDCMP trigger + enable or by disabling DMA. */ + __IOM uint32_t DTHR : 1; /*!< [1..1] Triggered DMA from THR event. Bit is read only and can + be cleared by disabling the DTHR trigger enable or by disabling + DMA. */ + __IOM uint32_t DTOTCMP : 1; /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data + in the FIFO was enough to complete the DMA operation (greater + than or equal to current TOTCOUNT) when the command completed. + This trigger is default active when the DCMDCMP trigger + isdisabled and there is enough data in the FIFO to complete + the DMA operation. */ + } DMATRIGSTAT_b; + } ; + __IM uint32_t RESERVED3[14]; + + union { + __IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA + operation. This should be the last DMA related register + set prior to issuing the command */ + __IOM uint32_t DMADIR : 1; /*!< [1..1] Direction */ + uint32_t : 6; + __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ + __IOM uint32_t DPWROFF : 1; /*!< [9..9] Power off module after DMA is complete. If this bit is + active, the module will request to power off the supply + it is attached to. If there are other units still requiring + power from the same domain, power down will not be performed. */ + } DMACFG_b; + } ; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */ + + struct { + __IOM uint32_t TOTCOUNT : 12; /*!< [11..0] Triggered DMA from Command complete event occured. Bit + is read only and can be cleared by disabling the DTHR trigger + enable or by disabling DMA. */ + } DMATOTCOUNT_b; + } ; + + union { + __IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */ + + struct { + __IOM uint32_t TARGADDR : 20; /*!< [19..0] Bits [19:0] of the target byte address for source of + DMA (either read or write). The address can be any byte + alignment, and does not have to be word aligned. In cases + of non-word aligned addresses, the DMA logic will take + care for ensuring only the target bytes are read/written. */ + uint32_t : 8; + __IOM uint32_t TARGADDR28 : 1; /*!< [28..28] Bit 28 of the target byte address for source of DMA + (either read or write). In cases of non-word aligned addresses, + the DMA logic will take care for ensuring only the target + bytes are read/written.Setting to '1' will select the SRAM. + Setting to '0' will select the flash */ + } DMATARGADDR_b; + } ; + + union { + __IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */ + + struct { + __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that + a DMA transfer is active. The DMA transfer may be waiting + on data, transferring data, or waiting for priority.All + of these will be indicated with a 1. A 0 will indicate + that the DMA is fully complete and no further transactions + will be done. This bit is read only. */ + __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA + operation. This bit can be cleared by writing to 0, and + will also be cleared when a new DMA is started. */ + __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals an error was + encountered during the DMA operation. The bit can be cleared + by writing to 0. Once set, this bit will remain set until + cleared by software. */ + } DMASTAT_b; + } ; + + union { + __IOM uint32_t CQCFG; /*!< (@ 0x00000294) Command Queue Configuration Register */ + + struct { + __IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing + of the command queue and fetches of address/data pairs + will proceed from the word address within the CQADDR register. + Can be disabled using a CQ executed write to this bit as + well. */ + __IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue dma request */ + } CQCFG_b; + } ; + + union { + __IOM uint32_t CQADDR; /*!< (@ 0x00000298) CQ Target Read Address Register */ + + struct { + uint32_t : 2; + __IOM uint32_t CQADDR : 18; /*!< [19..2] Bits 19:2 of target byte address for source of CQ. The + buffer must be aligned on a word boundary */ + uint32_t : 8; + __IOM uint32_t CQADDR28 : 1; /*!< [28..28] Bit 28 of target byte address for source of CQ. Used + to denote Flash (0) or SRAM (1) access */ + } CQADDR_b; + } ; + + union { + __IOM uint32_t CQSTAT; /*!< (@ 0x0000029C) Command Queue Status Register */ + + struct { + __IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will + indicate that a CQ transfer is active and this will remain + active even when paused waiting for external event. */ + __IOM uint32_t CQPAUSED : 1; /*!< [1..1] Command queue operation is currently paused. */ + __IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit + signals that an error was encountered during the CQ operation. */ + } CQSTAT_b; + } ; + + union { + __IOM uint32_t CQFLAGS; /*!< (@ 0x000002A0) Command Queue Flag Register */ + + struct { + __IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software + controllable and bits [15:8] are hardware status. */ + __IOM uint32_t CQIRQMASK : 16; /*!< [31..16] Mask the bits used to generate the command queue interrupt. + A '1' in the bit position will enable the pause event to + trigger the interrupt, if the CQWT_int interrupt is enabled. + Bits definitions are the same as CQPAUSE */ + } CQFLAGS_b; + } ; + + union { + __IOM uint32_t CQSETCLEAR; /*!< (@ 0x000002A4) Command Queue Flag Set/Clear Register */ + + struct { + __IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any + SWFLAG with a '1' in the corresponding bit position of + this field */ + __IOM uint32_t CQFTGL : 8; /*!< [15..8] Toggle the indicated bit. Will toggle the value of any + SWFLAG with a '1' in the corresponding bit position of + this field */ + __IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG + with a '1' in the corresponding bit position of this field */ + } CQSETCLEAR_b; + } ; + + union { + __IOM uint32_t CQPAUSEEN; /*!< (@ 0x000002A8) Command Queue Pause Enable Register */ + + struct { + __IOM uint32_t CQPEN : 16; /*!< [15..0] Enables the specified event to pause command processing + when active */ + } CQPAUSEEN_b; + } ; + + union { + __IOM uint32_t CQCURIDX; /*!< (@ 0x000002AC) IOM Command Queue current index value . Compared + to the CQENDIDX reg contents to generate + the IDXEQ Pause event for command queue */ + + struct { + __IOM uint32_t CQCURIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX + register field. If the values match, the IDXEQ pause event + will be activated, which will cause the pausing of command + quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ + } CQCURIDX_b; + } ; + + union { + __IOM uint32_t CQENDIDX; /*!< (@ 0x000002B0) IOM Command Queue current index value . Compared + to the CQCURIDX reg contents to generate + the IDXEQ Pause event for command queue */ + + struct { + __IOM uint32_t CQENDIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX + register field. If the values match, the IDXEQ pause event + will be activated, which will cause the pausing of command + quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ + } CQENDIDX_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x000002B4) IOM Module Status Register */ + + struct { + __IOM uint32_t ERR : 1; /*!< [0..0] Bit has been deprecated. Please refer to the other error + indicators. This will always return 0. */ + __IOM uint32_t CMDACT : 1; /*!< [1..1] Indicates if the active I/O Command is currently processing + a transaction, or command is complete, but the FIFO pointers + are still syncronizing internally. This bit will go high + atthe start of the transaction, and will go low when the + command is complete, and the data and pointers within the + FIFO have been syncronized. */ + __IOM uint32_t IDLEST : 1; /*!< [2..2] indicates if the active I/O state machine is IDLE. Note + - The state machine could be in idle state due to holdoffs + from data availability, or as the command gets propagated + into the logic from the registers. */ + } STATUS_b; + } ; + __IM uint32_t RESERVED5[18]; + + union { + __IOM uint32_t MSPICFG; /*!< (@ 0x00000300) SPI module master configuration */ + + struct { + __IOM uint32_t SPOL : 1; /*!< [0..0] selects SPI polarity. */ + __IOM uint32_t SPHA : 1; /*!< [1..1] selects SPI phase. */ + __IOM uint32_t FULLDUP : 1; /*!< [2..2] Enables full duplex mode for Master SPI write operations. + Data will be captured simultaneously into the read fifo */ + uint32_t : 13; + __IOM uint32_t WTFC : 1; /*!< [16..16] enables write mode flow control. */ + __IOM uint32_t RDFC : 1; /*!< [17..17] enables read mode flow control. */ + __IOM uint32_t MOSIINV : 1; /*!< [18..18] inverts MOSI when flow control is enabled. */ + uint32_t : 1; + __IOM uint32_t WTFCIRQ : 1; /*!< [20..20] selects the write mode flow control signal. */ + __IOM uint32_t WTFCPOL : 1; /*!< [21..21] selects the write flow control signal polarity. The + transfers are halted when the selected flow control signal + is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 + will allow a IRQ=1 to pause transfers). */ + __IOM uint32_t RDFCPOL : 1; /*!< [22..22] selects the read flow control signal polarity. */ + __IOM uint32_t SPILSB : 1; /*!< [23..23] Selects data transfer as MSB first (0) or LSB first + (1) for the data portion of the SPI transaction. The offset + bytes are always transmitted MSB first. */ + __IOM uint32_t DINDLY : 3; /*!< [26..24] Delay tap to use for the input signal (MISO). This + gives more hold time on the input data. */ + __IOM uint32_t DOUTDLY : 3; /*!< [29..27] Delay tap to use for the output signal (MOSI). This + give more hold time on the output data */ + __IOM uint32_t MSPIRST : 1; /*!< [30..30] Not used. To reset the module, toggle the SMOD_EN for + the module */ + } MSPICFG_b; + } ; + __IM uint32_t RESERVED6[63]; + + union { + __IOM uint32_t MI2CCFG; /*!< (@ 0x00000400) I2C Master configuration */ + + struct { + __IOM uint32_t ADDRSZ : 1; /*!< [0..0] Sets the I2C master device address size to either 7b + (0) or 10b (1). */ + __IOM uint32_t I2CLSB : 1; /*!< [1..1] Direction of data transmit and receive, MSB(0) or LSB(1) + first. Default per I2C specification is MSB first. This + applies to both read and write data, and read data will + be bit */ + __IOM uint32_t ARBEN : 1; /*!< [2..2] Enables multi-master arbitration for the I2C master. + If the bus is known to have only a single master, this + function can be disabled to save clock cycles on I2C transactions */ + uint32_t : 1; + __IOM uint32_t SDADLY : 2; /*!< [5..4] Delay to enable on the SDA output. Values are 0x0-0x3. */ + __IOM uint32_t MI2CRST : 1; /*!< [6..6] Not used. To reset the module, toggle the SMOD_EN for + the module */ + uint32_t : 1; + __IOM uint32_t SCLENDLY : 4; /*!< [11..8] Number of IOCLK cycles to delay the rising edge of the + SCL output en (clock will go low on this edge). Used to + allow clock shaping. */ + __IOM uint32_t SDAENDLY : 4; /*!< [15..12] Number of IOCLK cycles to delay the SDA output en (all + transitions affected). Used to delay data relative to clock */ + __IOM uint32_t SMPCNT : 8; /*!< [23..16] Number of Base clk cycles to wait before sampling the + SCL clock to determine if a clock stretch event has occured */ + __IOM uint32_t STRDIS : 1; /*!< [24..24] Disable detection of clock stretch events smaller than + 1 cycle */ + } MI2CCFG_b; + } ; + + union { + __IOM uint32_t DEVCFG; /*!< (@ 0x00000404) I2C Device Configuration register */ + + struct { + __IOM uint32_t DEVADDR : 10; /*!< [9..0] I2C address of the device that the Master will use to + target for read/write operations. This can be either a + 7b or 10b address. */ + } DEVCFG_b; + } ; + __IM uint32_t RESERVED7[2]; + + union { + __IOM uint32_t IOMDBG; /*!< (@ 0x00000410) IOM Debug Register */ + + struct { + __IOM uint32_t DBGEN : 1; /*!< [0..0] Debug Enable. Setting bit will enable the update of data + within this register, otherwise it is clock gated for power + savings */ + __IOM uint32_t IOCLKON : 1; /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active + when this bit is '1'. Otherwise, the clock is controlled + with gating from the logic as needed. */ + __IOM uint32_t APBCLKON : 1; /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active + when this bit is '1'. Otherwise, the clock is controlled + with gating from the logic as needed. */ + __IOM uint32_t DBGDATA : 29; /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used + to select between different debug data available in the + DBG0 and DBG1 registers. */ + } IOMDBG_b; + } ; +} IOM0_Type; /*!< Size = 1044 (0x414) */ + + + +/* =========================================================================================================================== */ +/* ================ IOSLAVE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C/SPI Slave (IOSLAVE) + */ + +typedef struct { /*!< (@ 0x50000000) IOSLAVE Structure */ + __IM uint32_t RESERVED[64]; + + union { + __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) Current FIFO Pointer */ + + struct { + __IOM uint32_t FIFOPTR : 8; /*!< [7..0] Current FIFO pointer. */ + __IOM uint32_t FIFOSIZ : 8; /*!< [15..8] The number of bytes currently in the hardware FIFO. */ + } FIFOPTR_b; + } ; + + union { + __IOM uint32_t FIFOCFG; /*!< (@ 0x00000104) FIFO Configuration */ + + struct { + __IOM uint32_t FIFOBASE : 5; /*!< [4..0] These bits hold the base address of the I/O FIFO in 8 + byte segments. The IO Slave FIFO is situated in LRAM at + (FIFOBASE*8) to (FIFOMAX*8-1). */ + uint32_t : 3; + __IOM uint32_t FIFOMAX : 6; /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments. + It is also the beginning of the RAM area of the LRAM. Note + that no RAM area is configured if FIFOMAX is set to 0x1F. */ + uint32_t : 10; + __IOM uint32_t ROBASE : 6; /*!< [29..24] Defines the read-only area. The IO Slave read-only + area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1) */ + } FIFOCFG_b; + } ; + + union { + __IOM uint32_t FIFOTHR; /*!< (@ 0x00000108) FIFO Threshold Configuration */ + + struct { + __IOM uint32_t FIFOTHR : 8; /*!< [7..0] FIFO size interrupt threshold. */ + } FIFOTHR_b; + } ; + + union { + __IOM uint32_t FUPD; /*!< (@ 0x0000010C) FIFO Update Status */ + + struct { + __IOM uint32_t FIFOUPD : 1; /*!< [0..0] This bit indicates that a FIFO update is underway. */ + __IOM uint32_t IOREAD : 1; /*!< [1..1] This bitfield indicates an IO read is active. */ + } FUPD_b; + } ; + + union { + __IOM uint32_t FIFOCTR; /*!< (@ 0x00000110) Overall FIFO Counter */ + + struct { + __IOM uint32_t FIFOCTR : 10; /*!< [9..0] Virtual FIFO byte count */ + } FIFOCTR_b; + } ; + + union { + __IOM uint32_t FIFOINC; /*!< (@ 0x00000114) Overall FIFO Counter Increment */ + + struct { + __IOM uint32_t FIFOINC : 10; /*!< [9..0] Increment the Overall FIFO Counter by this value on a + write */ + } FIFOINC_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000118) I/O Slave Configuration */ + + struct { + __IOM uint32_t IFCSEL : 1; /*!< [0..0] This bit selects the I/O interface. */ + __IOM uint32_t SPOL : 1; /*!< [1..1] This bit selects SPI polarity. */ + __IOM uint32_t LSB : 1; /*!< [2..2] This bit selects the transfer bit ordering. */ + uint32_t : 1; + __IOM uint32_t STARTRD : 1; /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read. */ + uint32_t : 3; + __IOM uint32_t I2CADDR : 12; /*!< [19..8] 7-bit or 10-bit I2C device address. */ + uint32_t : 11; + __IOM uint32_t IFCEN : 1; /*!< [31..31] IOSLAVE interface enable. */ + } CFG_b; + } ; + + union { + __IOM uint32_t PRENC; /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode */ + + struct { + __IOM uint32_t PRENC : 5; /*!< [4..0] These bits hold the priority encode of the REGACC interrupts. */ + } PRENC_b; + } ; + + union { + __IOM uint32_t IOINTCTL; /*!< (@ 0x00000120) I/O Interrupt Control */ + + struct { + __IOM uint32_t IOINTEN : 8; /*!< [7..0] These read-only bits indicate whether the IOINT interrupts + are enabled. */ + __IOM uint32_t IOINT : 8; /*!< [15..8] These bits read the IOINT interrupts. */ + __IOM uint32_t IOINTCLR : 1; /*!< [16..16] This bit clears all of the IOINT interrupts when written + with a 1. */ + uint32_t : 7; + __IOM uint32_t IOINTSET : 8; /*!< [31..24] These bits set the IOINT interrupts when written with + a 1. */ + } IOINTCTL_b; + } ; + + union { + __IOM uint32_t GENADD; /*!< (@ 0x00000124) General Address Data */ + + struct { + __IOM uint32_t GADATA : 8; /*!< [7..0] The data supplied on the last General Address reference. */ + } GENADD_b; + } ; + __IM uint32_t RESERVED1[54]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Slave Interrupts: Enable */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Slave Interrupts: Status */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Slave Interrupts: Clear */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Slave Interrupts: Set */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTSET_b; + } ; + + union { + __IOM uint32_t REGACCINTEN; /*!< (@ 0x00000210) Register Access Interrupts: Enable */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTEN_b; + } ; + + union { + __IOM uint32_t REGACCINTSTAT; /*!< (@ 0x00000214) Register Access Interrupts: Status */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTSTAT_b; + } ; + + union { + __IOM uint32_t REGACCINTCLR; /*!< (@ 0x00000218) Register Access Interrupts: Clear */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTCLR_b; + } ; + + union { + __IOM uint32_t REGACCINTSET; /*!< (@ 0x0000021C) Register Access Interrupts: Set */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTSET_b; + } ; +} IOSLAVE_Type; /*!< Size = 544 (0x220) */ + + + +/* =========================================================================================================================== */ +/* ================ MCUCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MCU Miscellaneous Control Logic (MCUCTRL) + */ + +typedef struct { /*!< (@ 0x40020000) MCUCTRL Structure */ + + union { + __IOM uint32_t CHIPPN; /*!< (@ 0x00000000) Chip Information Register */ + + struct { + __IOM uint32_t PARTNUM : 32; /*!< [31..0] BCD part number. */ + } CHIPPN_b; + } ; + + union { + __IOM uint32_t CHIPID0; /*!< (@ 0x00000004) Unique Chip ID 0 */ + + struct { + __IOM uint32_t CHIPID0 : 32; /*!< [31..0] Unique chip ID 0. */ + } CHIPID0_b; + } ; + + union { + __IOM uint32_t CHIPID1; /*!< (@ 0x00000008) Unique Chip ID 1 */ + + struct { + __IOM uint32_t CHIPID1 : 32; /*!< [31..0] Unique chip ID 1. */ + } CHIPID1_b; + } ; + + union { + __IOM uint32_t CHIPREV; /*!< (@ 0x0000000C) Chip Revision */ + + struct { + __IOM uint32_t REVMIN : 4; /*!< [3..0] Minor Revision ID. */ + __IOM uint32_t REVMAJ : 4; /*!< [7..4] Major Revision ID. */ + __IOM uint32_t SIPART : 12; /*!< [19..8] Silicon Part ID */ + } CHIPREV_b; + } ; + + union { + __IOM uint32_t VENDORID; /*!< (@ 0x00000010) Unique Vendor ID */ + + struct { + __IOM uint32_t VENDORID : 32; /*!< [31..0] Unique Vendor ID */ + } VENDORID_b; + } ; + + union { + __IOM uint32_t SKU; /*!< (@ 0x00000014) Unique Chip SKU */ + + struct { + __IOM uint32_t ALLOWBURST : 1; /*!< [0..0] Allow Burst feature */ + __IOM uint32_t ALLOWBLE : 1; /*!< [1..1] Allow BLE feature */ + __IOM uint32_t SECBOOT : 1; /*!< [2..2] Secure boot feature allowed */ + } SKU_b; + } ; + + union { + __IOM uint32_t FEATUREENABLE; /*!< (@ 0x00000018) Feature Enable on Burst and BLE */ + + struct { + __IOM uint32_t BLEREQ : 1; /*!< [0..0] Controls the BLE functionality */ + __IOM uint32_t BLEACK : 1; /*!< [1..1] ACK for BLEREQ */ + __IOM uint32_t BLEAVAIL : 1; /*!< [2..2] AVAILABILITY of the BLE functionality */ + uint32_t : 1; + __IOM uint32_t BURSTREQ : 1; /*!< [4..4] Controls the Burst functionality */ + __IOM uint32_t BURSTACK : 1; /*!< [5..5] ACK for BURSTREQ */ + __IOM uint32_t BURSTAVAIL : 1; /*!< [6..6] Availability of Burst functionality */ + } FEATUREENABLE_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t DEBUGGER; /*!< (@ 0x00000020) Debugger Control */ + + struct { + __IOM uint32_t LOCKOUT : 1; /*!< [0..0] Lockout of debugger (SWD). */ + } DEBUGGER_b; + } ; + __IM uint32_t RESERVED1[55]; + + union { + __IOM uint32_t BODCTRL; /*!< (@ 0x00000100) BOD control Register */ + + struct { + __IOM uint32_t BODLPWD : 1; /*!< [0..0] BODL Power Down. */ + __IOM uint32_t BODHPWD : 1; /*!< [1..1] BODH Power Down. */ + __IOM uint32_t BODCPWD : 1; /*!< [2..2] BODC Power Down. */ + __IOM uint32_t BODFPWD : 1; /*!< [3..3] BODF Power Down. */ + __IOM uint32_t BODLVREFSEL : 1; /*!< [4..4] BODL External Reference Select. Note: the SWE mux select + in PWRSEQ2SWE must be set for this to take effect. */ + __IOM uint32_t BODHVREFSEL : 1; /*!< [5..5] BODH External Reference Select. Note: the SWE mux select + in PWRSEQ2SWE must be set for this to take effect. */ + } BODCTRL_b; + } ; + + union { + __IOM uint32_t ADCPWRDLY; /*!< (@ 0x00000104) ADC Power Up Delay Control */ + + struct { + __IOM uint32_t ADCPWR0 : 8; /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK + increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments + for ADC_CLKSEL = 0x2. */ + __IOM uint32_t ADCPWR1 : 8; /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments + for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL + = 0x2. */ + } ADCPWRDLY_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t ADCCAL; /*!< (@ 0x0000010C) ADC Calibration Control */ + + struct { + __IOM uint32_t CALONPWRUP : 1; /*!< [0..0] Run ADC Calibration on initial power up sequence */ + __IOM uint32_t ADCCALIBRATED : 1; /*!< [1..1] Status for ADC Calibration */ + } ADCCAL_b; + } ; + + union { + __IOM uint32_t ADCBATTLOAD; /*!< (@ 0x00000110) ADC Battery Load Enable */ + + struct { + __IOM uint32_t BATTLOAD : 1; /*!< [0..0] Enable the ADC battery load resistor */ + } ADCBATTLOAD_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t ADCTRIM; /*!< (@ 0x00000118) ADC Trims */ + + struct { + __IOM uint32_t ADCREFKEEPIBTRIM : 2; /*!< [1..0] ADC Reference Ibias trim */ + uint32_t : 4; + __IOM uint32_t ADCREFBUFTRIM : 5; /*!< [10..6] ADC Reference buffer trim */ + __IOM uint32_t ADCRFBUFIBTRIM : 2; /*!< [12..11] ADC reference buffer input bias trim */ + } ADCTRIM_b; + } ; + + union { + __IOM uint32_t ADCREFCOMP; /*!< (@ 0x0000011C) ADC Reference Keeper and Comparator Control */ + + struct { + __IOM uint32_t ADC_REFCOMP_OUT : 1; /*!< [0..0] Output of the ADC reference comparator */ + uint32_t : 7; + __IOM uint32_t ADCREFKEEPTRIM : 5; /*!< [12..8] ADC Reference Keeper Trim */ + uint32_t : 3; + __IOM uint32_t ADCRFCMPEN : 1; /*!< [16..16] ADC Reference comparator power down */ + } ADCREFCOMP_b; + } ; + + union { + __IOM uint32_t XTALCTRL; /*!< (@ 0x00000120) XTAL Oscillator Control */ + + struct { + __IOM uint32_t XTALSWE : 1; /*!< [0..0] XTAL Software Override Enable. */ + __IOM uint32_t FDBKDSBLXTAL : 1; /*!< [1..1] XTAL Oscillator Disable Feedback. */ + __IOM uint32_t BYPCMPRXTAL : 1; /*!< [2..2] XTAL Oscillator Bypass Comparator. */ + __IOM uint32_t PDNBCOREXTAL : 1; /*!< [3..3] XTAL Oscillator Power Down Core. */ + __IOM uint32_t PDNBCMPRXTAL : 1; /*!< [4..4] XTAL Oscillator Power Down Comparator. */ + __IOM uint32_t PWDBODXTAL : 1; /*!< [5..5] XTAL Power down on brown out. */ + __IOM uint32_t XTALIBUFTRIM : 2; /*!< [7..6] XTAL IBUFF trim */ + __IOM uint32_t XTALICOMPTRIM : 2; /*!< [9..8] XTAL ICOMP trim */ + } XTALCTRL_b; + } ; + + union { + __IOM uint32_t XTALGENCTRL; /*!< (@ 0x00000124) XTAL Oscillator General Control */ + + struct { + __IOM uint32_t ACWARMUP : 2; /*!< [1..0] Auto-calibration delay control */ + __IOM uint32_t XTALBIASTRIM : 6; /*!< [7..2] XTAL BIAS trim */ + __IOM uint32_t XTALKSBIASTRIM : 6; /*!< [13..8] XTAL IBIAS Kick start trim. This trim value is used + during the startup process to enable a faster lock. */ + } XTALGENCTRL_b; + } ; + __IM uint32_t RESERVED4[28]; + + union { + __IOM uint32_t MISCCTRL; /*!< (@ 0x00000198) Miscellaneous control register. */ + + struct { + __IOM uint32_t RESERVED_RW_0 : 5; /*!< [4..0] Reserved bits, always leave unchanged. The MISCCTRL register + must be modified via atomic RMW, leaving this bit field + completely unmodified. Failure to do so will result in + unpredictable behavior. */ + __IOM uint32_t BLE_RESETN : 1; /*!< [5..5] BLE reset signal. */ + } MISCCTRL_b; + } ; + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t BOOTLOADER; /*!< (@ 0x000001A0) Bootloader and secure boot functions */ + + struct { + __IOM uint32_t BOOTLOADERLOW : 1; /*!< [0..0] Determines whether the bootloader code is visible at + address 0x00000000 or not. Resets to 1, write 1 to clear. */ + __IOM uint32_t SBLOCK : 1; /*!< [1..1] Secure boot lock. Always resets to 1, write 1 to clear. + Enables system visibility to bootloader until set. */ + __IOM uint32_t PROTLOCK : 1; /*!< [2..2] Flash protection lock. Always resets to 1, write 1 to + clear. Enables writes to flash protection register set. */ + uint32_t : 23; + __IOM uint32_t SECBOOTFEATURE : 2; /*!< [27..26] Indicates whether the secure boot feature is enabled. */ + __IOM uint32_t SECBOOT : 2; /*!< [29..28] Indicates whether the secure boot on cold reset is + enabled */ + __IOM uint32_t SECBOOTONRST : 2; /*!< [31..30] Indicates whether the secure boot on warm reset is + enabled */ + } BOOTLOADER_b; + } ; + + union { + __IOM uint32_t SHADOWVALID; /*!< (@ 0x000001A4) Register to indicate whether the shadow registers + have been successfully loaded from the Flash + Information Space. */ + + struct { + __IOM uint32_t VALID : 1; /*!< [0..0] Indicates whether the shadow registers contain valid + data from the Flash Information Space. */ + __IOM uint32_t BLDSLEEP : 1; /*!< [1..1] Indicates whether the bootloader should sleep or deep + sleep if no image loaded. */ + __IOM uint32_t INFO0_VALID : 1; /*!< [2..2] Indicates whether INFO0 contains valid data */ + } SHADOWVALID_b; + } ; + __IM uint32_t RESERVED6[2]; + + union { + __IOM uint32_t SCRATCH0; /*!< (@ 0x000001B0) Scratch register that is not reset by any reset */ + + struct { + __IOM uint32_t SCRATCH0 : 32; /*!< [31..0] Scratch register 0. */ + } SCRATCH0_b; + } ; + + union { + __IOM uint32_t SCRATCH1; /*!< (@ 0x000001B4) Scratch register that is not reset by any reset */ + + struct { + __IOM uint32_t SCRATCH1 : 32; /*!< [31..0] Scratch register 1. */ + } SCRATCH1_b; + } ; + __IM uint32_t RESERVED7[2]; + + union { + __IOM uint32_t ICODEFAULTADDR; /*!< (@ 0x000001C0) ICODE bus address which was present when a bus + fault occurred. */ + + struct { + __IOM uint32_t ICODEFAULTADDR : 32; /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred. + Once an address is captured in this field, it is held until + the corresponding Fault Observed bit is cleared in the + FAULTSTATUS register. */ + } ICODEFAULTADDR_b; + } ; + + union { + __IOM uint32_t DCODEFAULTADDR; /*!< (@ 0x000001C4) DCODE bus address which was present when a bus + fault occurred. */ + + struct { + __IOM uint32_t DCODEFAULTADDR : 32; /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred. + Once an address is captured in this field, it is held until + the corresponding Fault Observed bit is cleared in the + FAULTSTATUS register. */ + } DCODEFAULTADDR_b; + } ; + + union { + __IOM uint32_t SYSFAULTADDR; /*!< (@ 0x000001C8) System bus address which was present when a bus + fault occurred. */ + + struct { + __IOM uint32_t SYSFAULTADDR : 32; /*!< [31..0] SYS bus address observed when a Bus Fault occurred. + Once an address is captured in this field, it is held until + the corresponding Fault Observed bit is cleared in the + FAULTSTATUS register. */ + } SYSFAULTADDR_b; + } ; + + union { + __IOM uint32_t FAULTSTATUS; /*!< (@ 0x000001CC) Reflects the status of the bus decoders' fault + detection. Any write to this register will + clear all of the status bits within the + register. */ + + struct { + __IOM uint32_t ICODEFAULT : 1; /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a + fault has been detected, and the ICODEFAULTADDR register + will contain the bus address which generated the fault. */ + __IOM uint32_t DCODEFAULT : 1; /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault + has been detected, and the DCODEFAULTADDR register will + contain the bus address which generated the fault. */ + __IOM uint32_t SYSFAULT : 1; /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault + has been detected, and the SYSFAULTADDR register will contain + the bus address which generated the fault. */ + } FAULTSTATUS_b; + } ; + + union { + __IOM uint32_t FAULTCAPTUREEN; /*!< (@ 0x000001D0) Enable the fault capture registers */ + + struct { + __IOM uint32_t FAULTCAPTUREEN : 1; /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture + monitors are enabled and addresses which generate a hard + fault are captured into the FAULTADDR registers. */ + } FAULTCAPTUREEN_b; + } ; + __IM uint32_t RESERVED8[11]; + + union { + __IOM uint32_t DBGR1; /*!< (@ 0x00000200) Read-only debug register 1 */ + + struct { + __IOM uint32_t ONETO8 : 32; /*!< [31..0] Read-only register for communication validation */ + } DBGR1_b; + } ; + + union { + __IOM uint32_t DBGR2; /*!< (@ 0x00000204) Read-only debug register 2 */ + + struct { + __IOM uint32_t COOLCODE : 32; /*!< [31..0] Read-only register for communication validation */ + } DBGR2_b; + } ; + __IM uint32_t RESERVED9[6]; + + union { + __IOM uint32_t PMUENABLE; /*!< (@ 0x00000220) Control bit to enable/disable the PMU */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] PMU Enable Control bit. When set, the MCU's PMU will + place the MCU into the lowest power consuming Deep Sleep + mode upon execution of a WFI instruction (dependent on + the setting of the SLEEPDEEP bit in the ARM SCR register). + When cleared, regardless of the requested sleep mode, the + PMU will not enter the lowest power Deep Sleep mode, instead + entering the Sleep mode. */ + } PMUENABLE_b; + } ; + __IM uint32_t RESERVED10[11]; + + union { + __IOM uint32_t TPIUCTRL; /*!< (@ 0x00000250) TPIU Control Register. Determines the clock enable + and frequency for the M4's TPIU interface. */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled + and data can be streamed out of the MCU's SWO port using + the ARM ITM and TPIU modules. */ + uint32_t : 7; + __IOM uint32_t CLKSEL : 3; /*!< [10..8] This field selects the frequency of the ARM M4 TPIU + port. */ + } TPIUCTRL_b; + } ; + __IM uint32_t RESERVED11[4]; + + union { + __IOM uint32_t OTAPOINTER; /*!< (@ 0x00000264) OTA (Over the Air) Update Pointer/Status. Reset + only by POA */ + + struct { + __IOM uint32_t OTAVALID : 1; /*!< [0..0] Indicates that an OTA update is valid */ + __IOM uint32_t OTASBLUPDATE : 1; /*!< [1..1] Indicates that the sbl_init has been updated */ + __IOM uint32_t OTAPOINTER : 30; /*!< [31..2] Flash page pointer with updated OTA image */ + } OTAPOINTER_b; + } ; + __IM uint32_t RESERVED12[6]; + + union { + __IOM uint32_t APBDMACTRL; /*!< (@ 0x00000280) DMA Control Register. Determines misc settings + for DMA operation */ + + struct { + __IOM uint32_t DMA_ENABLE : 1; /*!< [0..0] Enable the DMA controller. When disabled, DMA requests + will be ignored by the controller */ + __IOM uint32_t DECODEABORT : 1; /*!< [1..1] APB Decode Abort. When set, the APB bridge will issue + a data abort (bus fault) on transactions to peripherals + that are powered down. When set to 0, writes are quietly + discarded and reads return 0. */ + uint32_t : 6; + __IOM uint32_t HYSTERESIS : 8; /*!< [15..8] This field determines how long the DMA will remain active + during deep sleep before shutting down and returning the + system to full deep sleep. Values are based on a 94KHz + clock and are roughly 10 us increments for a range of ~10 + us to 2.55 ms */ + } APBDMACTRL_b; + } ; + + union { + __IOM uint32_t SRAMMODE; /*!< (@ 0x00000284) SRAM Controller mode bits */ + + struct { + __IOM uint32_t IPREFETCH : 1; /*!< [0..0] When set, instruction accesses to the SRAM banks will + be pre-fetched (normally 2 cycle read access). Generally, + this mode bit should be set for improved performance when + executing instructions from SRAM. */ + __IOM uint32_t IPREFETCH_CACHE : 1; /*!< [1..1] Secondary pre-fetch feature that will cache pre-fetched + data across bus wait states (requires IPREFETCH to be set). */ + uint32_t : 2; + __IOM uint32_t DPREFETCH : 1; /*!< [4..4] When set, data bus accesses to the SRAM banks will be + pre-fetched (normally 2 cycle read access). Use of this + mode bit is only recommended if the work flow has a large + number of sequential accesses. */ + __IOM uint32_t DPREFETCH_CACHE : 1; /*!< [5..5] Secondary pre-fetch feature that will cache pre-fetched + data across bus wait states (requires DPREFETCH to be set). */ + } SRAMMODE_b; + } ; + __IM uint32_t RESERVED13[48]; + + union { + __IOM uint32_t KEXTCLKSEL; /*!< (@ 0x00000348) Key Register to enable the use of external clock + selects via the EXTCLKSEL reg */ + + struct { + __IOM uint32_t KEXTCLKSEL : 32; /*!< [31..0] Key register value. */ + } KEXTCLKSEL_b; + } ; + __IM uint32_t RESERVED14[2]; + + union { + __IOM uint32_t SIMOBUCK2; /*!< (@ 0x00000354) SIMO Buck Control Reg 2 */ + + struct { + __IOM uint32_t RESERVED_RW_0 : 16; /*!< [15..0] Reserved bits, always leave unchanged. The SIMOBUCK2 + register must be modified via atomic RMW, leaving this + bit field completely unmodified. Failure to do so will + result in unpredictable behavior. */ + __IOM uint32_t SIMOBUCKCORELPHIGHTONTRIM : 4;/*!< [19..16] simobuck_core_lp_high_ton_trim */ + __IOM uint32_t SIMOBUCKCORELPLOWTONTRIM : 4;/*!< [23..20] simobuck_core_lp_low_ton_trim */ + __IOM uint32_t RESERVED_RW_24 : 8; /*!< [31..24] Reserved bits, always leave unchanged. The SIMOBUCK2 + register must be modified via atomic RMW, leaving this + bit field completely unmodified. Failure to do so will + result in unpredictable behavior. */ + } SIMOBUCK2_b; + } ; + + union { + __IOM uint32_t SIMOBUCK3; /*!< (@ 0x00000358) SIMO Buck Control Reg 3 */ + + struct { + __IOM uint32_t SIMOBUCKCORELPHIGHTOFFTRIM : 4;/*!< [3..0] simobuck_core_lp_high_toff_trim */ + __IOM uint32_t SIMOBUCKCORELPLOWTOFFTRIM : 4;/*!< [7..4] simobuck_core_lp_low_toff_trim */ + __IOM uint32_t SIMOBUCKMEMLPHIGHTOFFTRIM : 4;/*!< [11..8] simobuck_mem_lp_high_toff_trim */ + __IOM uint32_t SIMOBUCKMEMLPLOWTOFFTRIM : 4;/*!< [15..12] simobuck_mem_lp_low_toff_trim */ + __IOM uint32_t RESERVED_RW_16 : 11; /*!< [26..16] Reserved bits, always leave unchanged. The SIMOBUCK3 + register must be modified via atomic RMW, leaving this + bit field completely unmodified. Failure to do so will + result in unpredictable behavior. */ + __IOM uint32_t SIMOBUCKMEMLPHIGHTONTRIM : 4;/*!< [30..27] simobuck_mem_lp_high_ton_trim */ + __IOM uint32_t RESERVED_RW_31 : 1; /*!< [31..31] Reserved bits, always leave unchanged. The SIMOBUCK2 + register must be modified via atomic RMW, leaving this + bit field completely unmodified. Failure to do so will + result in unpredictable behavior. */ + } SIMOBUCK3_b; + } ; + + union { + __IOM uint32_t SIMOBUCK4; /*!< (@ 0x0000035C) SIMO Buck Control Reg 4 */ + + struct { + __IOM uint32_t SIMOBUCKMEMLPLOWTONTRIM : 4;/*!< [3..0] simobuck_mem_lp_low_ton_trim */ + uint32_t : 17; + __IOM uint32_t SIMOBUCKCLKDIVSEL : 2; /*!< [22..21] simobuck_clkdiv_sel */ + uint32_t : 1; + __IOM uint32_t SIMOBUCKCOMP2TIMEOUTEN : 1;/*!< [24..24] simobuck_comp2_timeout_en */ + } SIMOBUCK4_b; + } ; + __IM uint32_t RESERVED15[2]; + + union { + __IOM uint32_t BLEBUCK2; /*!< (@ 0x00000368) BLEBUCK2 Control Reg */ + + struct { + __IOM uint32_t BLEBUCKTONLOWTRIM : 6; /*!< [5..0] blebuck_ton_low_trim */ + __IOM uint32_t BLEBUCKTONHITRIM : 6; /*!< [11..6] blebuck_ton_hi_trim */ + __IOM uint32_t BLEBUCKTOND2ATRIM : 6; /*!< [17..12] blebuck_ton_trim */ + } BLEBUCK2_b; + } ; + __IM uint32_t RESERVED16[13]; + + union { + __IOM uint32_t FLASHWPROT0; /*!< (@ 0x000003A0) Flash Write Protection Bits */ + + struct { + __IOM uint32_t FW0BITS : 32; /*!< [31..0] Write protect flash 0x00000000 - 0x0007FFFF. Each bit + provides write protection for 16KB chunks of flash data + space. Bits are cleared by writing a 1 to the bit. When + read, 0 indicates the region is protected. Bits are sticky + (can be set when PROTLOCK is 1, but only cleared by reset) */ + } FLASHWPROT0_b; + } ; + + union { + __IOM uint32_t FLASHWPROT1; /*!< (@ 0x000003A4) Flash Write Protection Bits */ + + struct { + __IOM uint32_t FW1BITS : 32; /*!< [31..0] Write protect flash 0x00080000 - 0x000FFFFF. Each bit + provides write protection for 16KB chunks of flash data + space. Bits are cleared by writing a 1 to the bit. When + read, 0 indicates the region is protected. Bits are sticky + (can be set when PROTLOCK is 1, but only cleared by reset) */ + } FLASHWPROT1_b; + } ; + __IM uint32_t RESERVED17[2]; + + union { + __IOM uint32_t FLASHRPROT0; /*!< (@ 0x000003B0) Flash Read Protection Bits */ + + struct { + __IOM uint32_t FR0BITS : 32; /*!< [31..0] Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each + bit provides read protection for 16KB chunks of flash. + Bits are cleared by writing a 1 to the bit. When read, + 0 indicates the region is protected. Bits are sticky (can + be set when PROTLOCK is 1, but only cleared by reset) */ + } FLASHRPROT0_b; + } ; + + union { + __IOM uint32_t FLASHRPROT1; /*!< (@ 0x000003B4) Flash Read Protection Bits */ + + struct { + __IOM uint32_t FR1BITS : 32; /*!< [31..0] Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each + bit provides read protection for 16KB chunks of flash. + Bits are cleared by writing a 1 to the bit. When read, + 0 indicates the region is protected. Bits are sticky (can + be set when PROTLOCK is 1, but only cleared by reset) */ + } FLASHRPROT1_b; + } ; + __IM uint32_t RESERVED18[2]; + + union { + __IOM uint32_t DMASRAMWRITEPROTECT0; /*!< (@ 0x000003C0) SRAM write-protection bits. */ + + struct { + __IOM uint32_t DMA_WPROT0 : 32; /*!< [31..0] Write protect SRAM from DMA. Each bit provides write + protection for an 8KB region of memory. When set to 1, + the region will be protected from DMA writes, when set + to 0, DMA may write the region. */ + } DMASRAMWRITEPROTECT0_b; + } ; + + union { + __IOM uint32_t DMASRAMWRITEPROTECT1; /*!< (@ 0x000003C4) SRAM write-protection bits. */ + + struct { + __IOM uint32_t DMA_WPROT1 : 16; /*!< [15..0] Write protect SRAM from DMA. Each bit provides write + protection for an 8KB region of memory. When set to 1, + the region will be protected from DMA writes, when set + to 0, DMA may write the region. */ + } DMASRAMWRITEPROTECT1_b; + } ; + __IM uint32_t RESERVED19[2]; + + union { + __IOM uint32_t DMASRAMREADPROTECT0; /*!< (@ 0x000003D0) SRAM read-protection bits. */ + + struct { + __IOM uint32_t DMA_RPROT0 : 32; /*!< [31..0] Read protect SRAM from DMA. Each bit provides write + protection for an 8KB region of memory. When set to 1, + the region will be protected from DMA reads, when set to + 0, DMA may read the region. */ + } DMASRAMREADPROTECT0_b; + } ; + + union { + __IOM uint32_t DMASRAMREADPROTECT1; /*!< (@ 0x000003D4) SRAM read-protection bits. */ + + struct { + __IOM uint32_t DMA_RPROT1 : 16; /*!< [15..0] Read protect SRAM from DMA. Each bit provides write + protection for an 8KB region of memory. When set to 1, + the region will be protected from DMA reads, when set to + 0, DMA may read the region. */ + } DMASRAMREADPROTECT1_b; + } ; +} MCUCTRL_Type; /*!< Size = 984 (0x3d8) */ + + + +/* =========================================================================================================================== */ +/* ================ MSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Multi-bit SPI Master (MSPI) + */ + +typedef struct { /*!< (@ 0x50014000) MSPI Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) MSPI PIO Transfer Control/Status */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Write to 1 to initiate a PIO transaction on the bus (typically + the entire register should be written at once with this + bit set). */ + __IOM uint32_t STATUS : 1; /*!< [1..1] Command status: 1 indicates command has completed. Cleared + by writing 1 to this bit or starting a new transfer. */ + __IOM uint32_t BUSY : 1; /*!< [2..2] Command status: 1 indicates controller is busy (command + in progress) */ + __IOM uint32_t QUADCMD : 1; /*!< [3..3] Flag indicating that the operation is a command that + should be replicated to both devices in paired QUAD mode. + This is typically only used when reading/writing configuration + registers in paired flash devices (do not set for memory + transfers). */ + uint32_t : 2; + __IOM uint32_t BIGENDIAN : 1; /*!< [6..6] 1 indicates data in FIFO is in big endian format (MSB + first); 0 indicates little endian data (default, LSB first). */ + __IOM uint32_t ENTURN : 1; /*!< [7..7] Indicates whether TX->RX turnaround cycles should be + enabled for this operation (see TURNAROUND field in CFG + register). */ + __IOM uint32_t SENDA : 1; /*!< [8..8] Indicates whether an address phase should be sent (see + ADDR register and ASIZE field in CFG register) */ + __IOM uint32_t SENDI : 1; /*!< [9..9] Indicates whether an instruction phase should be sent + (see INSTR field and ISIZE field in CFG register) */ + __IOM uint32_t TXRX : 1; /*!< [10..10] 1 Indicates a TX operation, 0 indicates an RX operation + of XFERBYTES */ + __IOM uint32_t PIOSCRAMBLE : 1; /*!< [11..11] Enables data scrambling for PIO operations. This should + only be used for data operations and never for commands + to a device. */ + uint32_t : 4; + __IOM uint32_t XFERBYTES : 16; /*!< [31..16] Number of bytes to transmit or receive (based on TXRX + bit) */ + } CTRL_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000004) MSPI Transfer Configuration */ + + struct { + __IOM uint32_t DEVCFG : 4; /*!< [3..0] Flash configuration for XIP and AUTO DMA operations. + Controls value for SER (Slave Enable) for XIP operations + and address generation for DMA/XIP modes. Also used to + configure SPIFRF (frame format). */ + __IOM uint32_t ASIZE : 2; /*!< [5..4] Address Size. Address bytes to send from ADDR register */ + __IOM uint32_t ISIZE : 1; /*!< [6..6] Instruction Sizeenum name = I8 value = 0x0 desc = Instruction + is 1 byteenum name = I16 value = 0x1 desc = Instruction + is 2 bytes */ + __IOM uint32_t SEPIO : 1; /*!< [7..7] Separate IO configuration. This bit should be set when + the target device has separate MOSI and MISO pins. Respective + IN/OUT bits below should be set to map pins. */ + __IOM uint32_t TURNAROUND : 6; /*!< [13..8] Number of turnaround cycles (for TX->RX transitions). + Qualified by ENTURN or XIPENTURN bit field. */ + uint32_t : 2; + __IOM uint32_t CPHA : 1; /*!< [16..16] Serial clock phase. */ + __IOM uint32_t CPOL : 1; /*!< [17..17] Serial clock polarity. */ + } CFG_b; + } ; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x00000008) MSPI Transfer Address */ + + struct { + __IOM uint32_t ADDR : 32; /*!< [31..0] Optional Address field to send (after optional instruction + field) - qualified by ASIZE in CMD register. NOTE: This + register is aliased to DMADEVADDR. */ + } ADDR_b; + } ; + + union { + __IOM uint32_t INSTR; /*!< (@ 0x0000000C) MSPI Transfer Instruction */ + + struct { + __IOM uint32_t INSTR : 16; /*!< [15..0] Optional Instruction field to send (1st byte) - qualified + by ISEND/ISIZE */ + } INSTR_b; + } ; + + union { + __IOM uint32_t TXFIFO; /*!< (@ 0x00000010) TX Data FIFO */ + + struct { + __IOM uint32_t TXFIFO : 32; /*!< [31..0] Data to be transmitted. Data should normally be aligned + to the LSB (pad the upper bits with zeros) unless BIGENDIAN + is set. */ + } TXFIFO_b; + } ; + + union { + __IOM uint32_t RXFIFO; /*!< (@ 0x00000014) RX Data FIFO */ + + struct { + __IOM uint32_t RXFIFO : 32; /*!< [31..0] Receive data. Data is aligned to the LSB (padded zeros + on upper bits) unless BIGENDIAN is set. */ + } RXFIFO_b; + } ; + + union { + __IOM uint32_t TXENTRIES; /*!< (@ 0x00000018) TX FIFO Entries */ + + struct { + __IOM uint32_t TXENTRIES : 5; /*!< [4..0] Number of 32-bit words/entries in TX FIFO */ + } TXENTRIES_b; + } ; + + union { + __IOM uint32_t RXENTRIES; /*!< (@ 0x0000001C) RX FIFO Entries */ + + struct { + __IOM uint32_t RXENTRIES : 5; /*!< [4..0] Number of 32-bit words/entries in RX FIFO */ + } RXENTRIES_b; + } ; + + union { + __IOM uint32_t THRESHOLD; /*!< (@ 0x00000020) TX/RX FIFO Threshold Levels */ + + struct { + __IOM uint32_t TXTHRESH : 5; /*!< [4..0] Number of entries in TX FIFO that cause TXF interrupt */ + uint32_t : 3; + __IOM uint32_t RXTHRESH : 5; /*!< [12..8] Number of entries in TX FIFO that cause RXE interrupt */ + } THRESHOLD_b; + } ; + __IM uint32_t RESERVED[55]; + + union { + __IOM uint32_t MSPICFG; /*!< (@ 0x00000100) MSPI Module Configuration */ + + struct { + __IOM uint32_t APBCLK : 1; /*!< [0..0] Enable continuous APB clock. For power-efficient operation, + APBCLK should be set to 0. */ + __IOM uint32_t RXCAP : 1; /*!< [1..1] Controls RX data capture phase. A setting of 0 (NORMAL) + captures read data at the normal capture point relative + to the internal clock launch point. However, to accommodate + chip/pad/board delays, a setting of RXCAP of 1 is expected + to be used to align the capture point with the return data + window. This bit is used in conjunction with RXNEG to provide + 4 unique capture points, all about 10 ns apart. */ + __IOM uint32_t RXNEG : 1; /*!< [2..2] Adjusts the RX capture phase to the negedge of the 48MHz + internal clock (~10 ns early). For normal operation, it + is expected that RXNEG will be set to 0. */ + __IOM uint32_t TXNEG : 1; /*!< [3..3] Launches TX data a half clock cycle (~10 ns) early. This + should normally be programmed to zero (NORMAL). */ + __IOM uint32_t IOMSEL : 3; /*!< [6..4] Selects which IOM is selected for CQ handshake status. */ + uint32_t : 1; + __IOM uint32_t CLKDIV : 6; /*!< [13..8] Clock Divider. Allows dividing 48 MHz base clock by + integer multiples. Enumerations are provided for common + frequency, but any integer divide from 48 MHz is allowed. + Odd divide ratios will result in a 33/66 percent duty cycle + with a long low clock pulse (to allow longer round-trip + for read data). */ + uint32_t : 15; + __IOM uint32_t FIFORESET : 1; /*!< [29..29] Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal + operation. May be used to manually flush the FIFO in error + handling. */ + __IOM uint32_t IPRSTN : 1; /*!< [30..30] IP block reset. Write to 0 to put the transfer module + in reset or 1 for normal operation. This may be required + after error conditions to clear the transfer on the bus. */ + __IOM uint32_t PRSTN : 1; /*!< [31..31] Peripheral reset. Master reset to the entire MSPI module + (DMA, XIP, and transfer state machines). 1=normal operation, + 0=in reset. */ + } MSPICFG_b; + } ; + + union { + __IOM uint32_t PADCFG; /*!< (@ 0x00000104) MSPI Output Pad Configuration */ + + struct { + __IOM uint32_t OUT3 : 1; /*!< [0..0] Output pad 3 configuration. 0=data[3] 1=CLK */ + __IOM uint32_t OUT4 : 1; /*!< [1..1] Output pad 4 configuration. 0=data[4] 1=data[0] */ + __IOM uint32_t OUT5 : 1; /*!< [2..2] Output pad 5 configuration. 0=data[5] 1=data[1] */ + __IOM uint32_t OUT6 : 1; /*!< [3..3] Output pad 6 configuration. 0=data[6] 1=data[2] */ + __IOM uint32_t OUT7 : 1; /*!< [4..4] Output pad 7 configuration. 0=data[7] 1=data[3] */ + uint32_t : 11; + __IOM uint32_t IN0 : 2; /*!< [17..16] Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] + 3=pad[5] */ + __IOM uint32_t IN1 : 1; /*!< [18..18] Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5] */ + __IOM uint32_t IN2 : 1; /*!< [19..19] Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6] */ + __IOM uint32_t IN3 : 1; /*!< [20..20] Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7] */ + __IOM uint32_t REVCS : 1; /*!< [21..21] Reverse CS connections. Allows CS1 to be associated + with lower data lanes and CS0 to be associated with upper + data lines */ + } PADCFG_b; + } ; + + union { + __IOM uint32_t PADOUTEN; /*!< (@ 0x00000108) MSPI Output Enable Pad Configuration */ + + struct { + __IOM uint32_t OUTEN : 9; /*!< [8..0] Output pad enable configuration. Indicates which pads + should be driven. Bits [3:0] are Quad0 data, [7:4] are + Quad1 data, and [8] is clock. */ + } PADOUTEN_b; + } ; + + union { + __IOM uint32_t FLASH; /*!< (@ 0x0000010C) Configuration for XIP/DMA support of SPI flash + modules. */ + + struct { + __IOM uint32_t XIPEN : 1; /*!< [0..0] Enable the XIP (eXecute In Place) function which effectively + enables the address decoding of the MSPI device in the + flash/cache address space at address 0x04000000-0x07FFFFFF. */ + uint32_t : 1; + __IOM uint32_t XIPACK : 2; /*!< [3..2] Controls transmission of Micron XIP acknowledge cycles + (Micron Flash devices only) */ + __IOM uint32_t XIPBIGENDIAN : 1; /*!< [4..4] Indicates whether XIP/AUTO DMA data transfers are in + big or little endian format */ + __IOM uint32_t XIPENTURN : 1; /*!< [5..5] Indicates whether XIP/AUTO DMA operations should enable + TX->RX turnaround cycles */ + __IOM uint32_t XIPSENDA : 1; /*!< [6..6] Indicates whether XIP/AUTO DMA operations should send + an an address phase (see DMADEVADDR register and ASIZE + field in CFG) */ + __IOM uint32_t XIPSENDI : 1; /*!< [7..7] Indicates whether XIP/AUTO DMA operations should send + an instruction (see READINSTR field and ISIZE field in + CFG) */ + __IOM uint32_t XIPMIXED : 3; /*!< [10..8] Reserved. Set to 0x0 */ + uint32_t : 5; + __IOM uint32_t WRITEINSTR : 8; /*!< [23..16] Write command sent for DMA operations */ + __IOM uint32_t READINSTR : 8; /*!< [31..24] Read command sent to flash for DMA/XIP operations */ + } FLASH_b; + } ; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t SCRAMBLING; /*!< (@ 0x00000120) External Flash Scrambling Controls */ + + struct { + __IOM uint32_t SCRSTART : 10; /*!< [9..0] Scrambling region start address [25:16] (64K block granularity). + The START block is the FIRST block included in the scrambled + address range. */ + uint32_t : 6; + __IOM uint32_t SCREND : 10; /*!< [25..16] Scrambling region end address [25:16] (64K block granularity). + The END block is the LAST block included in the scrambled + address range. */ + uint32_t : 5; + __IOM uint32_t SCRENABLE : 1; /*!< [31..31] Enables Data Scrambling Region. When 1 reads and writes + to the range will be scrambled. When 0, data will be read/written + unmodified. Address range is specified in 64K granularity + and the START/END ranges are included within the range. */ + } SCRAMBLING_b; + } ; + __IM uint32_t RESERVED2[55]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) MSPI Master Interrupts: Enable */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are + layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */ + __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ + __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to + a full FIFO). */ + __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from + an empty FIFO) */ + __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- + MSPI bus pins will stall) */ + __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ + __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ + __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ + performs an operation where address bit[0] is set. Useful + for triggering CURIDX interrupts. */ + __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ + __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ + __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must + be aligned to word (4-byte) start address. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) MSPI Master Interrupts: Status */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are + layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */ + __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ + __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to + a full FIFO). */ + __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from + an empty FIFO) */ + __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- + MSPI bus pins will stall) */ + __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ + __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ + __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ + performs an operation where address bit[0] is set. Useful + for triggering CURIDX interrupts. */ + __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ + __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ + __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must + be aligned to word (4-byte) start address. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) MSPI Master Interrupts: Clear */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are + layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */ + __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ + __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to + a full FIFO). */ + __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from + an empty FIFO) */ + __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- + MSPI bus pins will stall) */ + __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ + __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ + __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ + performs an operation where address bit[0] is set. Useful + for triggering CURIDX interrupts. */ + __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ + __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ + __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must + be aligned to word (4-byte) start address. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) MSPI Master Interrupts: Set */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are + layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */ + __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ + __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to + a full FIFO). */ + __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from + an empty FIFO) */ + __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- + MSPI bus pins will stall) */ + __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ + __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ + __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ + performs an operation where address bit[0] is set. Useful + for triggering CURIDX interrupts. */ + __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ + __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ + __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must + be aligned to word (4-byte) start address. */ + } INTSET_b; + } ; + __IM uint32_t RESERVED3[16]; + + union { + __IOM uint32_t DMACFG; /*!< (@ 0x00000250) DMA Configuration */ + + struct { + __IOM uint32_t DMAEN : 2; /*!< [1..0] DMA Enable. Setting this bit to EN will start the DMA + operation */ + __IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */ + __IOM uint32_t DMAPRI : 2; /*!< [4..3] Sets the Priority of the DMA request */ + uint32_t : 13; + __IOM uint32_t DMAPWROFF : 1; /*!< [18..18] Power off MSPI domain upon completion of DMA operation. */ + } DMACFG_b; + } ; + + union { + __IOM uint32_t DMASTAT; /*!< (@ 0x00000254) DMA Status */ + + struct { + __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that + a DMA transfer is active. The DMA transfer may be waiting + on data, transferring data, or waiting for priority. All + of these will be indicated with a 1. A 0 will indicate + that the DMA is fully complete and no further transactions + will be done. */ + __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA + operation. */ + __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals that an error + was encountered during the DMA operation. */ + __IOM uint32_t SCRERR : 1; /*!< [3..3] Scrambling Access Alignment Error. This active high bit + signals that a scrambling operation was specified for a + non-word aligned DEVADDR. */ + } DMASTAT_b; + } ; + + union { + __IOM uint32_t DMATARGADDR; /*!< (@ 0x00000258) DMA Target Address */ + + struct { + __IOM uint32_t TARGADDR : 32; /*!< [31..0] Target byte address for source of DMA (either read or + write). In cases of non-word aligned addresses, the DMA + logic will take care for ensuring only the target bytes + are read/written. */ + } DMATARGADDR_b; + } ; + + union { + __IOM uint32_t DMADEVADDR; /*!< (@ 0x0000025C) DMA Device Address */ + + struct { + __IOM uint32_t DEVADDR : 32; /*!< [31..0] SPI Device address for automated DMA transactions (both + read and write). */ + } DMADEVADDR_b; + } ; + + union { + __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000260) DMA Total Transfer Count */ + + struct { + __IOM uint32_t TOTCOUNT : 16; /*!< [15..0] Total Transfer Count in bytes. */ + } DMATOTCOUNT_b; + } ; + + union { + __IOM uint32_t DMABCOUNT; /*!< (@ 0x00000264) DMA BYTE Transfer Count */ + + struct { + __IOM uint32_t BCOUNT : 8; /*!< [7..0] Burst transfer size in bytes. This is the number of bytes + transferred when a FIFO trigger event occurs. Recommended + values are 16 or 32. */ + } DMABCOUNT_b; + } ; + __IM uint32_t RESERVED4[4]; + + union { + __IOM uint32_t DMATHRESH; /*!< (@ 0x00000278) DMA Transmit Trigger Threshold */ + + struct { + __IOM uint32_t DMATHRESH : 4; /*!< [3..0] DMA transfer FIFO level trigger. For read operations, + DMA is triggered when the FIFO level is greater than this + value. For write operations, DMA is triggered when the + FIFO level is less than this level. Each DMA operation + will consist of BCOUNT bytes. */ + } DMATHRESH_b; + } ; + __IM uint32_t RESERVED5[9]; + + union { + __IOM uint32_t CQCFG; /*!< (@ 0x000002A0) Command Queue Configuration */ + + struct { + __IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing + of the command queue */ + __IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue DMA request */ + __IOM uint32_t CQPWROFF : 1; /*!< [2..2] Power off MSPI domain upon completion of DMA operation. */ + __IOM uint32_t CQAUTOCLEARMASK : 1; /*!< [3..3] Enable clear of CQMASK after each pause operation. This + may be useful when using software flags to pause CQ. */ + } CQCFG_b; + } ; + __IM uint32_t RESERVED6; + + union { + __IOM uint32_t CQADDR; /*!< (@ 0x000002A8) CQ Target Read Address */ + + struct { + __IOM uint32_t CQADDR : 29; /*!< [28..0] Address of command queue buffer in SRAM or flash. The + buffer address must be aligned to a word boundary. */ + } CQADDR_b; + } ; + + union { + __IOM uint32_t CQSTAT; /*!< (@ 0x000002AC) Command Queue Status */ + + struct { + __IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will + indicate that a CQ transfer is active and this will remain + active even when paused waiting for external event. */ + __IOM uint32_t CQCPL : 1; /*!< [1..1] Command queue operation Complete. This signals the end + of the command queue operation. */ + __IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit + signals that an error was encountered during the CQ operation. */ + __IOM uint32_t CQPAUSED : 1; /*!< [3..3] Command queue is currently paused status. */ + } CQSTAT_b; + } ; + + union { + __IOM uint32_t CQFLAGS; /*!< (@ 0x000002B0) Command Queue Flags */ + + struct { + __IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software + controllable and bits [15:8] are hardware status. */ + } CQFLAGS_b; + } ; + + union { + __IOM uint32_t CQSETCLEAR; /*!< (@ 0x000002B4) Command Queue Flag Set/Clear */ + + struct { + __IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Set has priority over clear if + both are high. */ + __IOM uint32_t CQFTOGGLE : 8; /*!< [15..8] Toggle CQFlag status bits */ + __IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. */ + } CQSETCLEAR_b; + } ; + + union { + __IOM uint32_t CQPAUSE; /*!< (@ 0x000002B8) Command Queue Pause Mask */ + + struct { + __IOM uint32_t CQMASK : 16; /*!< [15..0] CQ will pause processing when ALL specified events are + satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK. */ + } CQPAUSE_b; + } ; + __IM uint32_t RESERVED7; + + union { + __IOM uint32_t CQCURIDX; /*!< (@ 0x000002C0) Command Queue Current Index */ + + struct { + __IOM uint32_t CQCURIDX : 8; /*!< [7..0] Can be used to indicate the current position of the command + queue by having CQ operations write this field. A CQ hardware + status flag indicates when CURIDX and ENDIDX are not equal, + allowing SW to pause the CQ processing until the end index + is updated. */ + } CQCURIDX_b; + } ; + + union { + __IOM uint32_t CQENDIDX; /*!< (@ 0x000002C4) Command Queue End Index */ + + struct { + __IOM uint32_t CQENDIDX : 8; /*!< [7..0] Can be used to indicate the end position of the command + queue. A CQ hardware status bit indices when CURIDX != + ENDIDX so that the CQ can be paused when it reaches the + end pointer. */ + } CQENDIDX_b; + } ; +} MSPI_Type; /*!< Size = 712 (0x2c8) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PDM Audio (PDM) + */ + +typedef struct { /*!< (@ 0x50011000) PDM Structure */ + + union { + __IOM uint32_t PCFG; /*!< (@ 0x00000000) PDM Configuration Register */ + + struct { + __IOM uint32_t PDMCOREEN : 1; /*!< [0..0] Data Streaming Control. */ + __IOM uint32_t SOFTMUTE : 1; /*!< [1..1] Soft mute control. */ + __IOM uint32_t CYCLES : 3; /*!< [4..2] Number of clocks during gain-setting changes. */ + __IOM uint32_t HPCUTOFF : 4; /*!< [8..5] High pass filter coefficients. */ + __IOM uint32_t ADCHPD : 1; /*!< [9..9] High pass filter control. */ + __IOM uint32_t SINCRATE : 7; /*!< [16..10] SINC decimation rate. */ + __IOM uint32_t MCLKDIV : 2; /*!< [18..17] PDM_CLK frequency divisor. */ + uint32_t : 2; + __IOM uint32_t PGALEFT : 5; /*!< [25..21] Left channel PGA gain. */ + __IOM uint32_t PGARIGHT : 5; /*!< [30..26] Right channel PGA gain. */ + __IOM uint32_t LRSWAP : 1; /*!< [31..31] Left/right channel swap. */ + } PCFG_b; + } ; + + union { + __IOM uint32_t VCFG; /*!< (@ 0x00000004) Voice Configuration Register */ + + struct { + uint32_t : 3; + __IOM uint32_t CHSET : 2; /*!< [4..3] Set PCM channels. */ + uint32_t : 3; + __IOM uint32_t PCMPACK : 1; /*!< [8..8] PCM data packing enable. */ + uint32_t : 7; + __IOM uint32_t SELAP : 1; /*!< [16..16] Select PDM input clock source. */ + __IOM uint32_t DMICKDEL : 1; /*!< [17..17] PDM clock sampling delay. */ + uint32_t : 1; + __IOM uint32_t BCLKINV : 1; /*!< [19..19] I2S BCLK input inversion. */ + __IOM uint32_t I2SEN : 1; /*!< [20..20] I2S interface enable. */ + uint32_t : 5; + __IOM uint32_t PDMCLKEN : 1; /*!< [26..26] Enable the serial clock. */ + __IOM uint32_t PDMCLKSEL : 3; /*!< [29..27] Select the PDM input clock. */ + __IOM uint32_t RSTB : 1; /*!< [30..30] Reset the IP core. */ + __IOM uint32_t IOCLKEN : 1; /*!< [31..31] Enable the IO clock. */ + } VCFG_b; + } ; + + union { + __IOM uint32_t VOICESTAT; /*!< (@ 0x00000008) Voice Status Register */ + + struct { + __IOM uint32_t FIFOCNT : 6; /*!< [5..0] Valid 32-bit entries currently in the FIFO. */ + } VOICESTAT_b; + } ; + + union { + __IOM uint32_t FIFOREAD; /*!< (@ 0x0000000C) FIFO Read */ + + struct { + __IOM uint32_t FIFOREAD : 32; /*!< [31..0] FIFO read data. */ + } FIFOREAD_b; + } ; + + union { + __IOM uint32_t FIFOFLUSH; /*!< (@ 0x00000010) FIFO Flush */ + + struct { + __IOM uint32_t FIFOFLUSH : 1; /*!< [0..0] FIFO FLUSH. */ + } FIFOFLUSH_b; + } ; + + union { + __IOM uint32_t FIFOTHR; /*!< (@ 0x00000014) FIFO Threshold */ + + struct { + __IOM uint32_t FIFOTHR : 5; /*!< [4..0] FIFO Threshold value. When the FIFO count is equal to, + or larger than this value (in words), a THR interrupt is + generated (if enabled) */ + } FIFOTHR_b; + } ; + __IM uint32_t RESERVED[122]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Master Interrupts: Enable */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ + __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Master Interrupts: Status */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ + __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Master Interrupts: Clear */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ + __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Master Interrupts: Set */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ + __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ + } INTSET_b; + } ; + __IM uint32_t RESERVED1[12]; + + union { + __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */ + + struct { + __IOM uint32_t DTHR : 1; /*!< [0..0] Trigger DMA upon when FIFO iss filled to level indicated + by the FIFO THRESHOLD,at granularity of 16 bytes only */ + __IOM uint32_t DTHR90 : 1; /*!< [1..1] Trigger DMA at FIFO 90 percent full. This signal is also + used internally for AUTOHIP function */ + } DMATRIGEN_b; + } ; + + union { + __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */ + + struct { + __IOM uint32_t DTHRSTAT : 1; /*!< [0..0] Triggered DMA from FIFO reaching threshold */ + __IOM uint32_t DTHR90STAT : 1; /*!< [1..1] Triggered DMA from FIFO reaching 90 percent full */ + } DMATRIGSTAT_b; + } ; + __IM uint32_t RESERVED2[14]; + + union { + __IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable */ + uint32_t : 1; + __IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */ + uint32_t : 5; + __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ + __IOM uint32_t DAUTOHIP : 1; /*!< [9..9] Raise priority to high on fifo full, and DMAPRI set to + low */ + __IOM uint32_t DPWROFF : 1; /*!< [10..10] Power Off the ADC System upon DMACPL. */ + } DMACFG_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */ + + struct { + __IOM uint32_t TOTCOUNT : 20; /*!< [19..0] Total Transfer Count. The transfer count must be a multiple + of the THR setting to avoid DMA overruns. */ + } DMATOTCOUNT_b; + } ; + + union { + __IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */ + + struct { + __IOM uint32_t LTARGADDR : 20; /*!< [19..0] DMA Target Address. This register is not updated with + the current address of the DMA, but will remain static + with the original address during the DMA transfer. */ + __IOM uint32_t UTARGADDR : 12; /*!< [31..20] SRAM Target */ + } DMATARGADDR_b; + } ; + + union { + __IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */ + + struct { + __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress */ + __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete */ + __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error */ + } DMASTAT_b; + } ; +} PDM_Type; /*!< Size = 660 (0x294) */ + + + +/* =========================================================================================================================== */ +/* ================ PWRCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PWR Controller Register Bank (PWRCTRL) + */ + +typedef struct { /*!< (@ 0x40021000) PWRCTRL Structure */ + + union { + __IOM uint32_t SUPPLYSRC; /*!< (@ 0x00000000) Voltage Regulator Select Register */ + + struct { + __IOM uint32_t BLEBUCKEN : 1; /*!< [0..0] Enables and Selects the BLE Buck as the supply for the + BLE power domain or for Burst LDO. It takes the initial + value from Customer INFO space. Buck will be powered up + only if there is an active request for BLEH domain or Burst + mode and appropriate feature is allowed. */ + } SUPPLYSRC_b; + } ; + + union { + __IOM uint32_t SUPPLYSTATUS; /*!< (@ 0x00000004) Voltage Regulators status */ + + struct { + __IOM uint32_t SIMOBUCKON : 1; /*!< [0..0] Indicates whether the Core/Mem low-voltage domains are + supplied from the LDO or the Buck. */ + __IOM uint32_t BLEBUCKON : 1; /*!< [1..1] Indicates whether the BLE (if supported) domain and burst + (if supported) domain is supplied from the LDO or the Buck. + Buck will be powered up only if there is an active request + for BLEH domain or Burst mode and appropriate reature is + allowed. */ + } SUPPLYSTATUS_b; + } ; + + union { + __IOM uint32_t DEVPWREN; /*!< (@ 0x00000008) Device Power Enables */ + + struct { + __IOM uint32_t PWRIOS : 1; /*!< [0..0] Power up IO Slave */ + __IOM uint32_t PWRIOM0 : 1; /*!< [1..1] Power up IO Master 0 */ + __IOM uint32_t PWRIOM1 : 1; /*!< [2..2] Power up IO Master 1 */ + __IOM uint32_t PWRIOM2 : 1; /*!< [3..3] Power up IO Master 2 */ + __IOM uint32_t PWRIOM3 : 1; /*!< [4..4] Power up IO Master 3 */ + __IOM uint32_t PWRIOM4 : 1; /*!< [5..5] Power up IO Master 4 */ + __IOM uint32_t PWRIOM5 : 1; /*!< [6..6] Power up IO Master 5 */ + __IOM uint32_t PWRUART0 : 1; /*!< [7..7] Power up UART Controller 0 */ + __IOM uint32_t PWRUART1 : 1; /*!< [8..8] Power up UART Controller 1 */ + __IOM uint32_t PWRADC : 1; /*!< [9..9] Power up ADC Digital Controller */ + __IOM uint32_t PWRSCARD : 1; /*!< [10..10] Power up SCARD Controller */ + __IOM uint32_t PWRMSPI : 1; /*!< [11..11] Power up MSPI Controller */ + __IOM uint32_t PWRPDM : 1; /*!< [12..12] Power up PDM block */ + __IOM uint32_t PWRBLEL : 1; /*!< [13..13] Power up BLE controller */ + } DEVPWREN_b; + } ; + + union { + __IOM uint32_t MEMPWDINSLEEP; /*!< (@ 0x0000000C) Powerdown SRAM banks in Deep Sleep mode */ + + struct { + __IOM uint32_t DTCMPWDSLP : 3; /*!< [2..0] power down DTCM in deep sleep */ + __IOM uint32_t SRAMPWDSLP : 10; /*!< [12..3] Selects which SRAM banks are powered down in deep sleep + mode, causing the contents of the bank to be lost. */ + __IOM uint32_t FLASH0PWDSLP : 1; /*!< [13..13] Powerdown flash0 in deep sleep */ + __IOM uint32_t FLASH1PWDSLP : 1; /*!< [14..14] Powerdown flash1 in deep sleep */ + uint32_t : 16; + __IOM uint32_t CACHEPWDSLP : 1; /*!< [31..31] power down cache in deep sleep */ + } MEMPWDINSLEEP_b; + } ; + + union { + __IOM uint32_t MEMPWREN; /*!< (@ 0x00000010) Enables individual banks of the MEMORY array */ + + struct { + __IOM uint32_t DTCM : 3; /*!< [2..0] Power up DTCM */ + __IOM uint32_t SRAM : 10; /*!< [12..3] Power up SRAM groups */ + __IOM uint32_t FLASH0 : 1; /*!< [13..13] Power up Flash0 */ + __IOM uint32_t FLASH1 : 1; /*!< [14..14] Power up Flash1 */ + uint32_t : 15; + __IOM uint32_t CACHEB0 : 1; /*!< [30..30] Power up Cache Bank 0. This works in conjunction with + Cache enable from flash_cache module. To power up cache + bank0, cache has to be enabled and this bit has to be set. */ + __IOM uint32_t CACHEB2 : 1; /*!< [31..31] Power up Cache Bank 2. This works in conjunction with + Cache enable from flash_cache module. To power up cache + bank2, cache has to be enabled and this bit has to be set. */ + } MEMPWREN_b; + } ; + + union { + __IOM uint32_t MEMPWRSTATUS; /*!< (@ 0x00000014) Mem Power ON Status */ + + struct { + __IOM uint32_t DTCM00 : 1; /*!< [0..0] This bit is 1 if power is supplied to DTCM GROUP0_0 */ + __IOM uint32_t DTCM01 : 1; /*!< [1..1] This bit is 1 if power is supplied to DTCM GROUP0_1 */ + __IOM uint32_t DTCM1 : 1; /*!< [2..2] This bit is 1 if power is supplied to DTCM GROUP1 */ + __IOM uint32_t SRAM0 : 1; /*!< [3..3] This bit is 1 if power is supplied to SRAM GROUP0 */ + __IOM uint32_t SRAM1 : 1; /*!< [4..4] This bit is 1 if power is supplied to SRAM GROUP1 */ + __IOM uint32_t SRAM2 : 1; /*!< [5..5] This bit is 1 if power is supplied to SRAM GROUP2 */ + __IOM uint32_t SRAM3 : 1; /*!< [6..6] This bit is 1 if power is supplied to SRAM GROUP3 */ + __IOM uint32_t SRAM4 : 1; /*!< [7..7] This bit is 1 if power is supplied to SRAM GROUP4 */ + __IOM uint32_t SRAM5 : 1; /*!< [8..8] This bit is 1 if power is supplied to SRAM GROUP5 */ + __IOM uint32_t SRAM6 : 1; /*!< [9..9] This bit is 1 if power is supplied to SRAM GROUP6 */ + __IOM uint32_t SRAM7 : 1; /*!< [10..10] This bit is 1 if power is supplied to SRAM GROUP7 */ + __IOM uint32_t SRAM8 : 1; /*!< [11..11] This bit is 1 if power is supplied to SRAM GROUP8 */ + __IOM uint32_t SRAM9 : 1; /*!< [12..12] This bit is 1 if power is supplied to SRAM GROUP9 */ + __IOM uint32_t FLASH0 : 1; /*!< [13..13] This bit is 1 if power is supplied to FLASH 0 */ + __IOM uint32_t FLASH1 : 1; /*!< [14..14] This bit is 1 if power is supplied to FLASH 1 */ + __IOM uint32_t CACHEB0 : 1; /*!< [15..15] This bit is 1 if power is supplied to Cache Bank 0 */ + __IOM uint32_t CACHEB2 : 1; /*!< [16..16] This bit is 1 if power is supplied to Cache Bank 2 */ + } MEMPWRSTATUS_b; + } ; + + union { + __IOM uint32_t DEVPWRSTATUS; /*!< (@ 0x00000018) Device Power ON Status */ + + struct { + __IOM uint32_t MCUL : 1; /*!< [0..0] This bit is 1 if power is supplied to MCUL */ + __IOM uint32_t MCUH : 1; /*!< [1..1] This bit is 1 if power is supplied to MCUH */ + __IOM uint32_t HCPA : 1; /*!< [2..2] This bit is 1 if power is supplied to HCPA domain (IO + SLAVE, UART0, UART1, SCARD) */ + __IOM uint32_t HCPB : 1; /*!< [3..3] This bit is 1 if power is supplied to HCPB domain (IO + MASTER 0, 1, 2) */ + __IOM uint32_t HCPC : 1; /*!< [4..4] This bit is 1 if power is supplied to HCPC domain (IO + MASTER4, 5, 6) */ + __IOM uint32_t PWRADC : 1; /*!< [5..5] This bit is 1 if power is supplied to ADC */ + __IOM uint32_t PWRMSPI : 1; /*!< [6..6] This bit is 1 if power is supplied to MSPI */ + __IOM uint32_t PWRPDM : 1; /*!< [7..7] This bit is 1 if power is supplied to PDM */ + __IOM uint32_t BLEL : 1; /*!< [8..8] This bit is 1 if power is supplied to BLEL */ + __IOM uint32_t BLEH : 1; /*!< [9..9] This bit is 1 if power is supplied to BLEH */ + } DEVPWRSTATUS_b; + } ; + + union { + __IOM uint32_t SRAMCTRL; /*!< (@ 0x0000001C) SRAM Control register */ + + struct { + uint32_t : 1; + __IOM uint32_t SRAMCLKGATE : 1; /*!< [1..1] This bit is 1 if clock gating is allowed for individual + system SRAMs */ + __IOM uint32_t SRAMMASTERCLKGATE : 1; /*!< [2..2] This bit is 1 when the master clock gate is enabled (top-level + clock gate for entire SRAM block) */ + uint32_t : 5; + __IOM uint32_t SRAMLIGHTSLEEP : 12; /*!< [19..8] Light Sleep enable for each TCM/SRAM bank. When 1, corresponding + bank will be put into light sleep. For optimal power, banks + should be put into light sleep while the system is active + but the bank has minimal or no accesses. */ + } SRAMCTRL_b; + } ; + + union { + __IOM uint32_t ADCSTATUS; /*!< (@ 0x00000020) Power Status Register for ADC Block */ + + struct { + __IOM uint32_t ADCPWD : 1; /*!< [0..0] This bit indicates that the ADC is powered down */ + __IOM uint32_t BGTPWD : 1; /*!< [1..1] This bit indicates that the ADC Band Gap is powered down */ + __IOM uint32_t VPTATPWD : 1; /*!< [2..2] This bit indicates that the ADC temperature sensor input + buffer is powered down */ + __IOM uint32_t VBATPWD : 1; /*!< [3..3] This bit indicates that the ADC VBAT resistor divider + is powered down */ + __IOM uint32_t REFKEEPPWD : 1; /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down */ + __IOM uint32_t REFBUFPWD : 1; /*!< [5..5] This bit indicates that the ADC REFBUF is powered down */ + } ADCSTATUS_b; + } ; + + union { + __IOM uint32_t MISC; /*!< (@ 0x00000024) Power Optimization Control Bits */ + + struct { + uint32_t : 3; + __IOM uint32_t FORCEMEMVRLPTIMERS : 1; /*!< [3..3] Control Bit to force Mem VR to LP mode in deep sleep + even when hfrc based ctimer or stimer is running. */ + uint32_t : 2; + __IOM uint32_t MEMVRLPBLE : 1; /*!< [6..6] Control Bit to let Mem VR go to lp mode in deep sleep + even when BLEL or BLEH is powered on given none of the + other domains require it. */ + } MISC_b; + } ; + + union { + __IOM uint32_t DEVPWREVENTEN; /*!< (@ 0x00000028) Event enable register to control which DEVPWRSTATUS + bits are routed to event input of CPU. */ + + struct { + __IOM uint32_t MCULEVEN : 1; /*!< [0..0] Control MCUL power-on status event */ + __IOM uint32_t MCUHEVEN : 1; /*!< [1..1] Control MCUH power-on status event */ + __IOM uint32_t HCPAEVEN : 1; /*!< [2..2] Control HCPA power-on status event */ + __IOM uint32_t HCPBEVEN : 1; /*!< [3..3] Control HCPB power-on status event */ + __IOM uint32_t HCPCEVEN : 1; /*!< [4..4] Control HCPC power-on status event */ + __IOM uint32_t ADCEVEN : 1; /*!< [5..5] Control ADC power-on status event */ + __IOM uint32_t MSPIEVEN : 1; /*!< [6..6] Control MSPI power-on status event */ + __IOM uint32_t PDMEVEN : 1; /*!< [7..7] Control PDM power-on status event */ + __IOM uint32_t BLELEVEN : 1; /*!< [8..8] Control BLE power-on status event */ + uint32_t : 20; + __IOM uint32_t BLEFEATUREEVEN : 1; /*!< [29..29] Control BLEFEATURE status event */ + __IOM uint32_t BURSTFEATUREEVEN : 1; /*!< [30..30] Control BURSTFEATURE status event */ + __IOM uint32_t BURSTEVEN : 1; /*!< [31..31] Control BURST status event */ + } DEVPWREVENTEN_b; + } ; + + union { + __IOM uint32_t MEMPWREVENTEN; /*!< (@ 0x0000002C) Event enable register to control which MEMPWRSTATUS + bits are routed to event input of CPU. */ + + struct { + __IOM uint32_t DTCMEN : 3; /*!< [2..0] Enable DTCM power-on status event */ + __IOM uint32_t SRAMEN : 10; /*!< [12..3] Control SRAM power-on status event */ + __IOM uint32_t FLASH0EN : 1; /*!< [13..13] Control Flash power-on status event */ + __IOM uint32_t FLASH1EN : 1; /*!< [14..14] Control Flash power-on status event */ + uint32_t : 15; + __IOM uint32_t CACHEB0EN : 1; /*!< [30..30] Control CACHE BANK 0 power-on status event */ + __IOM uint32_t CACHEB2EN : 1; /*!< [31..31] Control CACHEB2 power-on status event */ + } MEMPWREVENTEN_b; + } ; +} PWRCTRL_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ RSTGEN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MCU Reset Generator (RSTGEN) + */ + +typedef struct { /*!< (@ 0x40000000) RSTGEN Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t BODHREN : 1; /*!< [0..0] Brown out high (2.1v) reset enable. */ + __IOM uint32_t WDREN : 1; /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must + also be configured for WDT reset. This includes enabling + the RESEN bit in WDTCFG register in Watch dog timer block. */ + } CFG_b; + } ; + + union { + __IOM uint32_t SWPOI; /*!< (@ 0x00000004) Software POI Reset */ + + struct { + __IOM uint32_t SWPOIKEY : 8; /*!< [7..0] 0x1B generates a software POI reset. This is a write-only + register. Reading from this register will yield only all + 0s. */ + } SWPOI_b; + } ; + + union { + __IOM uint32_t SWPOR; /*!< (@ 0x00000008) Software POR Reset */ + + struct { + __IOM uint32_t SWPORKEY : 8; /*!< [7..0] 0xD4 generates a software POR reset. */ + } SWPOR_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t TPIURST; /*!< (@ 0x00000014) TPIU reset */ + + struct { + __IOM uint32_t TPIURST : 1; /*!< [0..0] Static reset for the TPIU. Write to '1' to assert reset + to TPIU. Write to '0' to clear the reset. */ + } TPIURST_b; + } ; + __IM uint32_t RESERVED1[122]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) Reset Interrupt register: Enable */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Reset Interrupt register: Status */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Reset Interrupt register: Clear */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Reset Interrupt register: Set */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTSET_b; + } ; + __IM uint32_t RESERVED2[67107708]; + + union { + __IOM uint32_t STAT; /*!< (@ 0x0FFFF000) Status Register (SBL) */ + + struct { + __IOM uint32_t EXRSTAT : 1; /*!< [0..0] Reset was initiated by an External Reset (SBL). */ + __IOM uint32_t PORSTAT : 1; /*!< [1..1] Reset was initiated by a Power-On Reset (SBL). */ + __IOM uint32_t BORSTAT : 1; /*!< [2..2] Reset was initiated by a Brown-Out Reset (SBL). */ + __IOM uint32_t SWRSTAT : 1; /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset (SBL). */ + __IOM uint32_t POIRSTAT : 1; /*!< [4..4] Reset was a initiated by Software POI Reset (SBL). */ + __IOM uint32_t DBGRSTAT : 1; /*!< [5..5] Reset was a initiated by Debugger Reset (SBL). */ + __IOM uint32_t WDRSTAT : 1; /*!< [6..6] Reset was initiated by a Watchdog Timer Reset (SBL). */ + __IOM uint32_t BOUSTAT : 1; /*!< [7..7] An Unregulated Supply Brownout Event occurred (SBL). */ + __IOM uint32_t BOCSTAT : 1; /*!< [8..8] A Core Regulator Brownout Event occurred (SBL). */ + __IOM uint32_t BOFSTAT : 1; /*!< [9..9] A Memory Regulator Brownout Event occurred (SBL). */ + __IOM uint32_t BOBSTAT : 1; /*!< [10..10] A BLE/Burst Regulator Brownout Event occurred (SBL). */ + uint32_t : 19; + __IOM uint32_t FBOOT : 1; /*!< [30..30] Set if current boot was initiated by soft reset and + resulted in Fast Boot (SBL). */ + __IOM uint32_t SBOOT : 1; /*!< [31..31] Set when booting securely (SBL). */ + } STAT_b; + } ; +} RSTGEN_Type; /*!< Size = 268431364 (0xffff004) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real Time Clock (RTC) + */ + +typedef struct { /*!< (@ 0x40004200) RTC Structure */ + __IM uint32_t RESERVED[16]; + + union { + __IOM uint32_t CTRLOW; /*!< (@ 0x00000040) RTC Counters Lower */ + + struct { + __IOM uint32_t CTR100 : 8; /*!< [7..0] 100ths of a second Counter */ + __IOM uint32_t CTRSEC : 7; /*!< [14..8] Seconds Counter */ + uint32_t : 1; + __IOM uint32_t CTRMIN : 7; /*!< [22..16] Minutes Counter */ + uint32_t : 1; + __IOM uint32_t CTRHR : 6; /*!< [29..24] Hours Counter */ + } CTRLOW_b; + } ; + + union { + __IOM uint32_t CTRUP; /*!< (@ 0x00000044) RTC Counters Upper */ + + struct { + __IOM uint32_t CTRDATE : 6; /*!< [5..0] Date Counter */ + uint32_t : 2; + __IOM uint32_t CTRMO : 5; /*!< [12..8] Months Counter */ + uint32_t : 3; + __IOM uint32_t CTRYR : 8; /*!< [23..16] Years Counter */ + __IOM uint32_t CTRWKDY : 3; /*!< [26..24] Weekdays Counter */ + __IOM uint32_t CB : 1; /*!< [27..27] Century */ + __IOM uint32_t CEB : 1; /*!< [28..28] Century enable */ + uint32_t : 2; + __IOM uint32_t CTERR : 1; /*!< [31..31] Counter read error status. Error is triggered when + software reads the lower word of the counters, and fails + to read the upper counter within 1/100 second. This is + because when the lower counter is read, the upper counter + is held off from incrementing until it is read so that + the full time stamp can be read. */ + } CTRUP_b; + } ; + + union { + __IOM uint32_t ALMLOW; /*!< (@ 0x00000048) RTC Alarms Lower */ + + struct { + __IOM uint32_t ALM100 : 8; /*!< [7..0] 100ths of a second Alarm */ + __IOM uint32_t ALMSEC : 7; /*!< [14..8] Seconds Alarm */ + uint32_t : 1; + __IOM uint32_t ALMMIN : 7; /*!< [22..16] Minutes Alarm */ + uint32_t : 1; + __IOM uint32_t ALMHR : 6; /*!< [29..24] Hours Alarm */ + } ALMLOW_b; + } ; + + union { + __IOM uint32_t ALMUP; /*!< (@ 0x0000004C) RTC Alarms Upper */ + + struct { + __IOM uint32_t ALMDATE : 6; /*!< [5..0] Date Alarm */ + uint32_t : 2; + __IOM uint32_t ALMMO : 5; /*!< [12..8] Months Alarm */ + uint32_t : 3; + __IOM uint32_t ALMWKDY : 3; /*!< [18..16] Weekdays Alarm */ + } ALMUP_b; + } ; + + union { + __IOM uint32_t RTCCTL; /*!< (@ 0x00000050) RTC Control Register */ + + struct { + __IOM uint32_t WRTC : 1; /*!< [0..0] Counter write control */ + __IOM uint32_t RPT : 3; /*!< [3..1] Alarm repeat interval */ + __IOM uint32_t RSTOP : 1; /*!< [4..4] RTC input clock control */ + __IOM uint32_t HR1224 : 1; /*!< [5..5] Hours Counter mode */ + } RTCCTL_b; + } ; + __IM uint32_t RESERVED1[43]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000100) RTC Interrupt Register: Enable */ + + struct { + __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000104) RTC Interrupt Register: Status */ + + struct { + __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000108) RTC Interrupt Register: Clear */ + + struct { + __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000010C) RTC Interrupt Register: Set */ + + struct { + __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ + } INTSET_b; + } ; +} RTC_Type; /*!< Size = 272 (0x110) */ + + + +/* =========================================================================================================================== */ +/* ================ SCARD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial ISO7816 (SCARD) + */ + +typedef struct { /*!< (@ 0x40080000) SCARD Structure */ + + union { + __IOM uint32_t SR; /*!< (@ 0x00000000) ISO7816 interrupt status */ + + struct { + __IOM uint32_t FNE : 1; /*!< [0..0] RX FIFO not empty. */ + __IOM uint32_t TBERBF : 1; /*!< [1..1] FIFO empty (transmit) or full (receive). */ + __IOM uint32_t FER : 1; /*!< [2..2] Framing error. */ + __IOM uint32_t OVR : 1; /*!< [3..3] RX FIFO overflow. */ + __IOM uint32_t PE : 1; /*!< [4..4] Parity Error. */ + __IOM uint32_t FT2REND : 1; /*!< [5..5] TX to RX finished. */ + __IOM uint32_t FHF : 1; /*!< [6..6] FIFO Half Full. */ + } SR_b; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000004) ISO7816 interrupt enable */ + + struct { + __IOM uint32_t FNEEN : 1; /*!< [0..0] RX FIFO not empty interrupt enable. */ + __IOM uint32_t TBERBFEN : 1; /*!< [1..1] FIFO empty (transmit) or full (receive) interrupt enable. */ + __IOM uint32_t FEREN : 1; /*!< [2..2] Framing error interrupt enable. */ + __IOM uint32_t OVREN : 1; /*!< [3..3] RX FIFOI overflow interrupt enable. */ + __IOM uint32_t PEEN : 1; /*!< [4..4] Parity Error interrupt enable. */ + __IOM uint32_t FT2RENDEN : 1; /*!< [5..5] TX to RX finished interrupt enable. */ + __IOM uint32_t FHFEN : 1; /*!< [6..6] FIFO Half Full interrupt enable. */ + } IER_b; + } ; + + union { + __IOM uint32_t TCR; /*!< (@ 0x00000008) ISO7816 transmit control */ + + struct { + __IOM uint32_t CONV : 1; /*!< [0..0] Conversion inversion control. */ + __IOM uint32_t SS : 1; /*!< [1..1] Use first byte to configure conversion. */ + __IOM uint32_t LCT : 1; /*!< [2..2] Fast TX to RX. */ + __IOM uint32_t TR : 1; /*!< [3..3] Transmit/receive mode. */ + __IOM uint32_t PROT : 1; /*!< [4..4] PROT control. */ + __IOM uint32_t AUTOCONV : 1; /*!< [5..5] Automatic conversion. */ + __IOM uint32_t FIP : 1; /*!< [6..6] Parity select. */ + __IOM uint32_t DMAMD : 1; /*!< [7..7] DMA direction. */ + } TCR_b; + } ; + + union { + __IOM uint32_t UCR; /*!< (@ 0x0000000C) ISO7816 user control */ + + struct { + __IOM uint32_t CST : 1; /*!< [0..0] Clock control. */ + __IOM uint32_t RIU : 1; /*!< [1..1] ISO7816 reset. This bit is write-only. */ + __IOM uint32_t RSTIN : 1; /*!< [2..2] Reset polarity. */ + __IOM uint32_t RETXEN : 1; /*!< [3..3] Enable TX/RX time configuration. */ + } UCR_b; + } ; + + union { + __IOM uint32_t DR; /*!< (@ 0x00000010) ISO7816 data */ + + struct { + __IOM uint32_t DR : 8; /*!< [7..0] Data register. */ + } DR_b; + } ; + + union { + __IOM uint32_t BPRL; /*!< (@ 0x00000014) ISO7816 baud rate low */ + + struct { + __IOM uint32_t BPRL : 8; /*!< [7..0] Baud rate low */ + } BPRL_b; + } ; + + union { + __IOM uint32_t BPRH; /*!< (@ 0x00000018) ISO7816 baud rate high */ + + struct { + __IOM uint32_t BPRH : 4; /*!< [3..0] Baud rate high */ + } BPRH_b; + } ; + + union { + __IOM uint32_t UCR1; /*!< (@ 0x0000001C) ISO7816 user control 1 */ + + struct { + __IOM uint32_t PR : 1; /*!< [0..0] Query Card Detect. */ + uint32_t : 1; + __IOM uint32_t STSP : 1; /*!< [2..2] ETU counter control. This bit is write-only. */ + __IOM uint32_t T1PAREN : 1; /*!< [3..3] Parity check control. */ + __IOM uint32_t CLKIOV : 1; /*!< [4..4] Output clock level. */ + __IOM uint32_t ENLASTB : 1; /*!< [5..5] Enable last byte function. */ + } UCR1_b; + } ; + + union { + __IOM uint32_t SR1; /*!< (@ 0x00000020) ISO7816 interrupt status 1 */ + + struct { + __IOM uint32_t ECNTOVER : 1; /*!< [0..0] ETU counter overflow. */ + __IOM uint32_t PRL : 1; /*!< [1..1] Card insert/remove. */ + __IOM uint32_t SYNCEND : 1; /*!< [2..2] Write complete synchronization. */ + __IOM uint32_t IDLE : 1; /*!< [3..3] ISO7816 idle. */ + } SR1_b; + } ; + + union { + __IOM uint32_t IER1; /*!< (@ 0x00000024) ISO7816 interrupt enable 1 */ + + struct { + __IOM uint32_t ECNTOVEREN : 1; /*!< [0..0] ETU counter overflow interrupt enable. */ + __IOM uint32_t PRLEN : 1; /*!< [1..1] Card insert/remove interrupt enable. */ + __IOM uint32_t SYNCENDEN : 1; /*!< [2..2] Write complete synchronization interrupt enable. */ + } IER1_b; + } ; + + union { + __IOM uint32_t ECNTL; /*!< (@ 0x00000028) ETU counter low */ + + struct { + __IOM uint32_t ECNTL : 8; /*!< [7..0] ETU counter low register. */ + } ECNTL_b; + } ; + + union { + __IOM uint32_t ECNTH; /*!< (@ 0x0000002C) ETU counter high */ + + struct { + __IOM uint32_t ECNTH : 8; /*!< [7..0] ETU counter high register. */ + } ECNTH_b; + } ; + + union { + __IOM uint32_t GTR; /*!< (@ 0x00000030) ISO7816 guard time configuration */ + + struct { + __IOM uint32_t GTR : 8; /*!< [7..0] Guard time configuration register. */ + } GTR_b; + } ; + + union { + __IOM uint32_t RETXCNT; /*!< (@ 0x00000034) ISO7816 resend count */ + + struct { + __IOM uint32_t RETXCNT : 4; /*!< [3..0] Resend count register. */ + } RETXCNT_b; + } ; + + union { + __IOM uint32_t RETXCNTRMI; /*!< (@ 0x00000038) ISO7816 resent count inquiry */ + + struct { + __IOM uint32_t RETXCNTRMI : 4; /*!< [3..0] Resent count inquiry register. */ + } RETXCNTRMI_b; + } ; + __IM uint32_t RESERVED[49]; + + union { + __IOM uint32_t CLKCTRL; /*!< (@ 0x00000100) Clock Control */ + + struct { + __IOM uint32_t CLKEN : 1; /*!< [0..0] Enable the serial source clock for SCARD. */ + __IOM uint32_t APBCLKEN : 1; /*!< [1..1] Enable the SCARD APB clock to run continuously. */ + } CLKCTRL_b; + } ; +} SCARD_Type; /*!< Size = 260 (0x104) */ + + + +/* =========================================================================================================================== */ +/* ================ SECURITY ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Security Interfaces (SECURITY) + */ + +typedef struct { /*!< (@ 0x40030000) SECURITY Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control Register */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] Function Enable. Software should set the ENABLE bit to + initiate a CRC operation. Hardware will clear the ENABLE + bit upon completion. */ + uint32_t : 3; + __IOM uint32_t FUNCTION : 4; /*!< [7..4] Function Select */ + uint32_t : 23; + __IOM uint32_t CRCERROR : 1; /*!< [31..31] CRC Error Status - Set to 1 if an error occurs during + a CRC operation. Cleared when CTRL register is written + (with any value). Usually indicates an invalid address + range. */ + } CTRL_b; + } ; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t SRCADDR; /*!< (@ 0x00000010) Source Addresss */ + + struct { + __IOM uint32_t ADDR : 32; /*!< [31..0] Source Buffer Address. Address may be byte aligned, + but the length must be a multiple of 4 bits. */ + } SRCADDR_b; + } ; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t LEN; /*!< (@ 0x00000020) Length */ + + struct { + uint32_t : 2; + __IOM uint32_t LEN : 18; /*!< [19..2] Buffer size (bottom two bits assumed to be zero to ensure + a multiple of 4 bytes) */ + } LEN_b; + } ; + __IM uint32_t RESERVED2[3]; + + union { + __IOM uint32_t RESULT; /*!< (@ 0x00000030) CRC Seed/Result Register */ + + struct { + __IOM uint32_t CRC : 32; /*!< [31..0] CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF + before starting a CRC operation (unless the CRC is continued + from a previous operation). */ + } RESULT_b; + } ; + __IM uint32_t RESERVED3[17]; + + union { + __IOM uint32_t LOCKCTRL; /*!< (@ 0x00000078) LOCK Control Register */ + + struct { + __IOM uint32_t SELECT : 8; /*!< [7..0] LOCK Function Select register. */ + } LOCKCTRL_b; + } ; + + union { + __IOM uint32_t LOCKSTAT; /*!< (@ 0x0000007C) LOCK Status Register */ + + struct { + __IOM uint32_t STATUS : 32; /*!< [31..0] LOCK Status register. This register is a bitmask for + which resources are currently unlocked. These bits are + one-hot per resource. */ + } LOCKSTAT_b; + } ; + + union { + __IOM uint32_t KEY0; /*!< (@ 0x00000080) Key0 Register */ + + struct { + __IOM uint32_t KEY0 : 32; /*!< [31..0] Bits [31:0] of the 128-bit key should be written to + this register. To protect key values, the register always + returns 0x00000000. */ + } KEY0_b; + } ; + + union { + __IOM uint32_t KEY1; /*!< (@ 0x00000084) Key1 Register */ + + struct { + __IOM uint32_t KEY1 : 32; /*!< [31..0] Bits [63:32] of the 128-bit key should be written to + this register. To protect key values, the register always + returns 0x00000000. */ + } KEY1_b; + } ; + + union { + __IOM uint32_t KEY2; /*!< (@ 0x00000088) Key2 Register */ + + struct { + __IOM uint32_t KEY2 : 32; /*!< [31..0] Bits [95:64] of the 128-bit key should be written to + this register. To protect key values, the register always + returns 0x00000000. */ + } KEY2_b; + } ; + + union { + __IOM uint32_t KEY3; /*!< (@ 0x0000008C) Key3 Register */ + + struct { + __IOM uint32_t KEY3 : 32; /*!< [31..0] Bits [127:96] of the 128-bit key should be written to + this register. To protect key values, the register always + returns 0x00000000. */ + } KEY3_b; + } ; +} SECURITY_Type; /*!< Size = 144 (0x90) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial UART (UART0) + */ + +typedef struct { /*!< (@ 0x4001C000) UART0 Structure */ + + union { + __IOM uint32_t DR; /*!< (@ 0x00000000) UART Data Register */ + + struct { + __IOM uint32_t DATA : 8; /*!< [7..0] This is the UART data port. */ + __IOM uint32_t FEDATA : 1; /*!< [8..8] This is the framing error indicator. */ + __IOM uint32_t PEDATA : 1; /*!< [9..9] This is the parity error indicator. */ + __IOM uint32_t BEDATA : 1; /*!< [10..10] This is the break error indicator. */ + __IOM uint32_t OEDATA : 1; /*!< [11..11] This is the overrun error indicator. */ + } DR_b; + } ; + + union { + __IOM uint32_t RSR; /*!< (@ 0x00000004) UART Status Register */ + + struct { + __IOM uint32_t FESTAT : 1; /*!< [0..0] This is the framing error indicator. */ + __IOM uint32_t PESTAT : 1; /*!< [1..1] This is the parity error indicator. */ + __IOM uint32_t BESTAT : 1; /*!< [2..2] This is the break error indicator. */ + __IOM uint32_t OESTAT : 1; /*!< [3..3] This is the overrun error indicator. */ + } RSR_b; + } ; + __IM uint32_t RESERVED[4]; + + union { + __IOM uint32_t FR; /*!< (@ 0x00000018) Flag Register */ + + struct { + __IOM uint32_t CTS : 1; /*!< [0..0] This bit holds the clear to send indicator. */ + __IOM uint32_t DSR : 1; /*!< [1..1] This bit holds the data set ready indicator. */ + __IOM uint32_t DCD : 1; /*!< [2..2] This bit holds the data carrier detect indicator. */ + __IOM uint32_t BUSY : 1; /*!< [3..3] This bit holds the busy indicator. */ + __IOM uint32_t RXFE : 1; /*!< [4..4] This bit holds the receive FIFO empty indicator. */ + __IOM uint32_t TXFF : 1; /*!< [5..5] This bit holds the transmit FIFO full indicator. */ + __IOM uint32_t RXFF : 1; /*!< [6..6] This bit holds the receive FIFO full indicator. */ + __IOM uint32_t TXFE : 1; /*!< [7..7] This bit holds the transmit FIFO empty indicator. */ + __IOM uint32_t TXBUSY : 1; /*!< [8..8] This bit holds the transmit BUSY indicator. */ + } FR_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t ILPR; /*!< (@ 0x00000020) IrDA Counter */ + + struct { + __IOM uint32_t ILPDVSR : 8; /*!< [7..0] These bits hold the IrDA counter divisor. */ + } ILPR_b; + } ; + + union { + __IOM uint32_t IBRD; /*!< (@ 0x00000024) Integer Baud Rate Divisor */ + + struct { + __IOM uint32_t DIVINT : 16; /*!< [15..0] These bits hold the baud integer divisor. */ + } IBRD_b; + } ; + + union { + __IOM uint32_t FBRD; /*!< (@ 0x00000028) Fractional Baud Rate Divisor */ + + struct { + __IOM uint32_t DIVFRAC : 6; /*!< [5..0] These bits hold the baud fractional divisor. */ + } FBRD_b; + } ; + + union { + __IOM uint32_t LCRH; /*!< (@ 0x0000002C) Line Control High */ + + struct { + __IOM uint32_t BRK : 1; /*!< [0..0] This bit holds the break set. */ + __IOM uint32_t PEN : 1; /*!< [1..1] This bit holds the parity enable. */ + __IOM uint32_t EPS : 1; /*!< [2..2] This bit holds the even parity select. */ + __IOM uint32_t STP2 : 1; /*!< [3..3] This bit holds the two stop bits select. */ + __IOM uint32_t FEN : 1; /*!< [4..4] This bit holds the FIFO enable. */ + __IOM uint32_t WLEN : 2; /*!< [6..5] These bits hold the write length. */ + __IOM uint32_t SPS : 1; /*!< [7..7] This bit holds the stick parity select. */ + } LCRH_b; + } ; + + union { + __IOM uint32_t CR; /*!< (@ 0x00000030) Control Register */ + + struct { + __IOM uint32_t UARTEN : 1; /*!< [0..0] This bit is the UART enable. */ + __IOM uint32_t SIREN : 1; /*!< [1..1] This bit is the SIR ENDEC enable. */ + __IOM uint32_t SIRLP : 1; /*!< [2..2] This bit is the SIR low power select. */ + __IOM uint32_t CLKEN : 1; /*!< [3..3] This bit is the UART clock enable. */ + __IOM uint32_t CLKSEL : 3; /*!< [6..4] This bitfield is the UART clock select. */ + __IOM uint32_t LBE : 1; /*!< [7..7] This bit is the loopback enable. */ + __IOM uint32_t TXE : 1; /*!< [8..8] This bit is the transmit enable. */ + __IOM uint32_t RXE : 1; /*!< [9..9] This bit is the receive enable. */ + __IOM uint32_t DTR : 1; /*!< [10..10] This bit enables data transmit ready. */ + __IOM uint32_t RTS : 1; /*!< [11..11] This bit enables request to send. */ + __IOM uint32_t OUT1 : 1; /*!< [12..12] This bit holds modem Out1. */ + __IOM uint32_t OUT2 : 1; /*!< [13..13] This bit holds modem Out2. */ + __IOM uint32_t RTSEN : 1; /*!< [14..14] This bit enables RTS hardware flow control. */ + __IOM uint32_t CTSEN : 1; /*!< [15..15] This bit enables CTS hardware flow control. */ + } CR_b; + } ; + + union { + __IOM uint32_t IFLS; /*!< (@ 0x00000034) FIFO Interrupt Level Select */ + + struct { + __IOM uint32_t TXIFLSEL : 3; /*!< [2..0] These bits hold the transmit FIFO interrupt level. */ + __IOM uint32_t RXIFLSEL : 3; /*!< [5..3] These bits hold the receive FIFO interrupt level. */ + } IFLS_b; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000038) Interrupt Enable */ + + struct { + __IOM uint32_t TXCMPMIM : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt enable. */ + __IOM uint32_t CTSMIM : 1; /*!< [1..1] This bit holds the modem CTS interrupt enable. */ + __IOM uint32_t DCDMIM : 1; /*!< [2..2] This bit holds the modem DCD interrupt enable. */ + __IOM uint32_t DSRMIM : 1; /*!< [3..3] This bit holds the modem DSR interrupt enable. */ + __IOM uint32_t RXIM : 1; /*!< [4..4] This bit holds the receive interrupt enable. */ + __IOM uint32_t TXIM : 1; /*!< [5..5] This bit holds the transmit interrupt enable. */ + __IOM uint32_t RTIM : 1; /*!< [6..6] This bit holds the receive timeout interrupt enable. */ + __IOM uint32_t FEIM : 1; /*!< [7..7] This bit holds the framing error interrupt enable. */ + __IOM uint32_t PEIM : 1; /*!< [8..8] This bit holds the parity error interrupt enable. */ + __IOM uint32_t BEIM : 1; /*!< [9..9] This bit holds the break error interrupt enable. */ + __IOM uint32_t OEIM : 1; /*!< [10..10] This bit holds the overflow interrupt enable. */ + } IER_b; + } ; + + union { + __IOM uint32_t IES; /*!< (@ 0x0000003C) Interrupt Status */ + + struct { + __IOM uint32_t TXCMPMRIS : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt status. */ + __IOM uint32_t CTSMRIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status. */ + __IOM uint32_t DCDMRIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status. */ + __IOM uint32_t DSRMRIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status. */ + __IOM uint32_t RXRIS : 1; /*!< [4..4] This bit holds the receive interrupt status. */ + __IOM uint32_t TXRIS : 1; /*!< [5..5] This bit holds the transmit interrupt status. */ + __IOM uint32_t RTRIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status. */ + __IOM uint32_t FERIS : 1; /*!< [7..7] This bit holds the framing error interrupt status. */ + __IOM uint32_t PERIS : 1; /*!< [8..8] This bit holds the parity error interrupt status. */ + __IOM uint32_t BERIS : 1; /*!< [9..9] This bit holds the break error interrupt status. */ + __IOM uint32_t OERIS : 1; /*!< [10..10] This bit holds the overflow interrupt status. */ + } IES_b; + } ; + + union { + __IOM uint32_t MIS; /*!< (@ 0x00000040) Masked Interrupt Status */ + + struct { + __IOM uint32_t TXCMPMMIS : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt status masked. */ + __IOM uint32_t CTSMMIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status masked. */ + __IOM uint32_t DCDMMIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status masked. */ + __IOM uint32_t DSRMMIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status masked. */ + __IOM uint32_t RXMIS : 1; /*!< [4..4] This bit holds the receive interrupt status masked. */ + __IOM uint32_t TXMIS : 1; /*!< [5..5] This bit holds the transmit interrupt status masked. */ + __IOM uint32_t RTMIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status masked. */ + __IOM uint32_t FEMIS : 1; /*!< [7..7] This bit holds the framing error interrupt status masked. */ + __IOM uint32_t PEMIS : 1; /*!< [8..8] This bit holds the parity error interrupt status masked. */ + __IOM uint32_t BEMIS : 1; /*!< [9..9] This bit holds the break error interrupt status masked. */ + __IOM uint32_t OEMIS : 1; /*!< [10..10] This bit holds the overflow interrupt status masked. */ + } MIS_b; + } ; + + union { + __IOM uint32_t IEC; /*!< (@ 0x00000044) Interrupt Clear */ + + struct { + __IOM uint32_t TXCMPMIC : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt clear. */ + __IOM uint32_t CTSMIC : 1; /*!< [1..1] This bit holds the modem CTS interrupt clear. */ + __IOM uint32_t DCDMIC : 1; /*!< [2..2] This bit holds the modem DCD interrupt clear. */ + __IOM uint32_t DSRMIC : 1; /*!< [3..3] This bit holds the modem DSR interrupt clear. */ + __IOM uint32_t RXIC : 1; /*!< [4..4] This bit holds the receive interrupt clear. */ + __IOM uint32_t TXIC : 1; /*!< [5..5] This bit holds the transmit interrupt clear. */ + __IOM uint32_t RTIC : 1; /*!< [6..6] This bit holds the receive timeout interrupt clear. */ + __IOM uint32_t FEIC : 1; /*!< [7..7] This bit holds the framing error interrupt clear. */ + __IOM uint32_t PEIC : 1; /*!< [8..8] This bit holds the parity error interrupt clear. */ + __IOM uint32_t BEIC : 1; /*!< [9..9] This bit holds the break error interrupt clear. */ + __IOM uint32_t OEIC : 1; /*!< [10..10] This bit holds the overflow interrupt clear. */ + } IEC_b; + } ; +} UART0_Type; /*!< Size = 72 (0x48) */ + + + +/* =========================================================================================================================== */ +/* ================ VCOMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Voltage Comparator (VCOMP) + */ + +typedef struct { /*!< (@ 0x4000C000) VCOMP Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t PSEL : 2; /*!< [1..0] This bitfield selects the positive input to the comparator. */ + uint32_t : 6; + __IOM uint32_t NSEL : 2; /*!< [9..8] This bitfield selects the negative input to the comparator. */ + uint32_t : 6; + __IOM uint32_t LVLSEL : 4; /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this + bitfield selects the voltage level for the negative input + to the comparator. */ + } CFG_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) Status Register */ + + struct { + __IOM uint32_t CMPOUT : 1; /*!< [0..0] This bit is 1 if the positive input of the comparator + is greater than the negative input. */ + __IOM uint32_t PWDSTAT : 1; /*!< [1..1] This bit indicates the power down state of the voltage + comparator. */ + } STAT_b; + } ; + + union { + __IOM uint32_t PWDKEY; /*!< (@ 0x00000008) Key Register for Powering Down the Voltage Comparator */ + + struct { + __IOM uint32_t PWDKEY : 32; /*!< [31..0] Key register value. */ + } PWDKEY_b; + } ; + __IM uint32_t RESERVED[125]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) Voltage Comparator Interrupt registers: Enable */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Voltage Comparator Interrupt registers: Status */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Voltage Comparator Interrupt registers: Clear */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Voltage Comparator Interrupt registers: Set */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTSET_b; + } ; +} VCOMP_Type; /*!< Size = 528 (0x210) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40024000) WDT Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t WDTEN : 1; /*!< [0..0] This bitfield enables the WDT. */ + __IOM uint32_t INTEN : 1; /*!< [1..1] This bitfield enables the WDT interrupt. Note : This + bit must be set before the interrupt status bit will reflect + a watchdog timer expiration. The IER interrupt register + must also be enabled for a WDT interrupt to be sent to + the NVIC. */ + __IOM uint32_t RESEN : 1; /*!< [2..2] This bitfield enables the WDT reset. This needs to be + set together with the WDREN bit in REG_RSTGEN_CFG register + (in reset gen) to trigger the reset. */ + uint32_t : 5; + __IOM uint32_t RESVAL : 8; /*!< [15..8] This bitfield is the compare value for counter bits + 7:0 to generate a watchdog reset. This will cause a software + reset. */ + __IOM uint32_t INTVAL : 8; /*!< [23..16] This bitfield is the compare value for counter bits + 7:0 to generate a watchdog interrupt. */ + __IOM uint32_t CLKSEL : 3; /*!< [26..24] Select the frequency for the WDT. All values not enumerated + below are undefined. */ + } CFG_b; + } ; + + union { + __IOM uint32_t RSTRT; /*!< (@ 0x00000004) Restart the watchdog timer. */ + + struct { + __IOM uint32_t RSTRT : 8; /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer. + This is a write only register. Reading this register will + only provide all 0. */ + } RSTRT_b; + } ; + + union { + __IOM uint32_t LOCK; /*!< (@ 0x00000008) Locks the WDT */ + + struct { + __IOM uint32_t LOCK : 8; /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the + WDTCFG reg cannot be written and WDTEN is set. */ + } LOCK_b; + } ; + + union { + __IOM uint32_t COUNT; /*!< (@ 0x0000000C) Current Counter Value for WDT */ + + struct { + __IOM uint32_t COUNT : 8; /*!< [7..0] Read-Only current value of the WDT counter */ + } COUNT_b; + } ; + __IM uint32_t RESERVED[124]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) WDT Interrupt register: Enable */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) WDT Interrupt register: Status */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) WDT Interrupt register: Clear */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) WDT Interrupt register: Set */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTSET_b; + } ; +} WDT_Type; /*!< Size = 528 (0x210) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define ADC_BASE 0x50010000UL +#define APBDMA_BASE 0x40011000UL +#define BLEIF_BASE 0x5000C000UL +#define CACHECTRL_BASE 0x40018000UL +#define CLKGEN_BASE 0x40004000UL +#define CTIMER_BASE 0x40008000UL +#define GPIO_BASE 0x40010000UL +#define IOM0_BASE 0x50004000UL +#define IOM1_BASE 0x50005000UL +#define IOM2_BASE 0x50006000UL +#define IOM3_BASE 0x50007000UL +#define IOM4_BASE 0x50008000UL +#define IOM5_BASE 0x50009000UL +#define IOSLAVE_BASE 0x50000000UL +#define MCUCTRL_BASE 0x40020000UL +#define MSPI_BASE 0x50014000UL +#define PDM_BASE 0x50011000UL +#define PWRCTRL_BASE 0x40021000UL +#define RSTGEN_BASE 0x40000000UL +#define RTC_BASE 0x40004200UL +#define SCARD_BASE 0x40080000UL +#define SECURITY_BASE 0x40030000UL +#define UART0_BASE 0x4001C000UL +#define UART1_BASE 0x4001D000UL +#define VCOMP_BASE 0x4000C000UL +#define WDT_BASE 0x40024000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define ADC ((ADC_Type*) ADC_BASE) +#define APBDMA ((APBDMA_Type*) APBDMA_BASE) +#define BLEIF ((BLEIF_Type*) BLEIF_BASE) +#define CACHECTRL ((CACHECTRL_Type*) CACHECTRL_BASE) +#define CLKGEN ((CLKGEN_Type*) CLKGEN_BASE) +#define CTIMER ((CTIMER_Type*) CTIMER_BASE) +#define GPIO ((GPIO_Type*) GPIO_BASE) +#define IOM0 ((IOM0_Type*) IOM0_BASE) +#define IOM1 ((IOM0_Type*) IOM1_BASE) +#define IOM2 ((IOM0_Type*) IOM2_BASE) +#define IOM3 ((IOM0_Type*) IOM3_BASE) +#define IOM4 ((IOM0_Type*) IOM4_BASE) +#define IOM5 ((IOM0_Type*) IOM5_BASE) +#define IOSLAVE ((IOSLAVE_Type*) IOSLAVE_BASE) +#define MCUCTRL ((MCUCTRL_Type*) MCUCTRL_BASE) +#define MSPI ((MSPI_Type*) MSPI_BASE) +#define PDM ((PDM_Type*) PDM_BASE) +#define PWRCTRL ((PWRCTRL_Type*) PWRCTRL_BASE) +#define RSTGEN ((RSTGEN_Type*) RSTGEN_BASE) +#define RTC ((RTC_Type*) RTC_BASE) +#define SCARD ((SCARD_Type*) SCARD_BASE) +#define SECURITY ((SECURITY_Type*) SECURITY_BASE) +#define UART0 ((UART0_Type*) UART0_BASE) +#define UART1 ((UART0_Type*) UART1_BASE) +#define VCOMP ((VCOMP_Type*) VCOMP_BASE) +#define WDT ((WDT_Type*) WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define ADC_CFG_CLKSEL_Pos (24UL) /*!< CLKSEL (Bit 24) */ +#define ADC_CFG_CLKSEL_Msk (0x3000000UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ +#define ADC_CFG_TRIGPOL_Pos (19UL) /*!< TRIGPOL (Bit 19) */ +#define ADC_CFG_TRIGPOL_Msk (0x80000UL) /*!< TRIGPOL (Bitfield-Mask: 0x01) */ +#define ADC_CFG_TRIGSEL_Pos (16UL) /*!< TRIGSEL (Bit 16) */ +#define ADC_CFG_TRIGSEL_Msk (0x70000UL) /*!< TRIGSEL (Bitfield-Mask: 0x07) */ +#define ADC_CFG_DFIFORDEN_Pos (12UL) /*!< DFIFORDEN (Bit 12) */ +#define ADC_CFG_DFIFORDEN_Msk (0x1000UL) /*!< DFIFORDEN (Bitfield-Mask: 0x01) */ +#define ADC_CFG_REFSEL_Pos (8UL) /*!< REFSEL (Bit 8) */ +#define ADC_CFG_REFSEL_Msk (0x300UL) /*!< REFSEL (Bitfield-Mask: 0x03) */ +#define ADC_CFG_CKMODE_Pos (4UL) /*!< CKMODE (Bit 4) */ +#define ADC_CFG_CKMODE_Msk (0x10UL) /*!< CKMODE (Bitfield-Mask: 0x01) */ +#define ADC_CFG_LPMODE_Pos (3UL) /*!< LPMODE (Bit 3) */ +#define ADC_CFG_LPMODE_Msk (0x8UL) /*!< LPMODE (Bitfield-Mask: 0x01) */ +#define ADC_CFG_RPTEN_Pos (2UL) /*!< RPTEN (Bit 2) */ +#define ADC_CFG_RPTEN_Msk (0x4UL) /*!< RPTEN (Bitfield-Mask: 0x01) */ +#define ADC_CFG_ADCEN_Pos (0UL) /*!< ADCEN (Bit 0) */ +#define ADC_CFG_ADCEN_Msk (0x1UL) /*!< ADCEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define ADC_STAT_PWDSTAT_Pos (0UL) /*!< PWDSTAT (Bit 0) */ +#define ADC_STAT_PWDSTAT_Msk (0x1UL) /*!< PWDSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== SWT ========================================================== */ +#define ADC_SWT_SWT_Pos (0UL) /*!< SWT (Bit 0) */ +#define ADC_SWT_SWT_Msk (0xffUL) /*!< SWT (Bitfield-Mask: 0xff) */ +/* ======================================================== SL0CFG ========================================================= */ +#define ADC_SL0CFG_ADSEL0_Pos (24UL) /*!< ADSEL0 (Bit 24) */ +#define ADC_SL0CFG_ADSEL0_Msk (0x7000000UL) /*!< ADSEL0 (Bitfield-Mask: 0x07) */ +#define ADC_SL0CFG_PRMODE0_Pos (16UL) /*!< PRMODE0 (Bit 16) */ +#define ADC_SL0CFG_PRMODE0_Msk (0x30000UL) /*!< PRMODE0 (Bitfield-Mask: 0x03) */ +#define ADC_SL0CFG_CHSEL0_Pos (8UL) /*!< CHSEL0 (Bit 8) */ +#define ADC_SL0CFG_CHSEL0_Msk (0xf00UL) /*!< CHSEL0 (Bitfield-Mask: 0x0f) */ +#define ADC_SL0CFG_WCEN0_Pos (1UL) /*!< WCEN0 (Bit 1) */ +#define ADC_SL0CFG_WCEN0_Msk (0x2UL) /*!< WCEN0 (Bitfield-Mask: 0x01) */ +#define ADC_SL0CFG_SLEN0_Pos (0UL) /*!< SLEN0 (Bit 0) */ +#define ADC_SL0CFG_SLEN0_Msk (0x1UL) /*!< SLEN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL1CFG ========================================================= */ +#define ADC_SL1CFG_ADSEL1_Pos (24UL) /*!< ADSEL1 (Bit 24) */ +#define ADC_SL1CFG_ADSEL1_Msk (0x7000000UL) /*!< ADSEL1 (Bitfield-Mask: 0x07) */ +#define ADC_SL1CFG_PRMODE1_Pos (16UL) /*!< PRMODE1 (Bit 16) */ +#define ADC_SL1CFG_PRMODE1_Msk (0x30000UL) /*!< PRMODE1 (Bitfield-Mask: 0x03) */ +#define ADC_SL1CFG_CHSEL1_Pos (8UL) /*!< CHSEL1 (Bit 8) */ +#define ADC_SL1CFG_CHSEL1_Msk (0xf00UL) /*!< CHSEL1 (Bitfield-Mask: 0x0f) */ +#define ADC_SL1CFG_WCEN1_Pos (1UL) /*!< WCEN1 (Bit 1) */ +#define ADC_SL1CFG_WCEN1_Msk (0x2UL) /*!< WCEN1 (Bitfield-Mask: 0x01) */ +#define ADC_SL1CFG_SLEN1_Pos (0UL) /*!< SLEN1 (Bit 0) */ +#define ADC_SL1CFG_SLEN1_Msk (0x1UL) /*!< SLEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL2CFG ========================================================= */ +#define ADC_SL2CFG_ADSEL2_Pos (24UL) /*!< ADSEL2 (Bit 24) */ +#define ADC_SL2CFG_ADSEL2_Msk (0x7000000UL) /*!< ADSEL2 (Bitfield-Mask: 0x07) */ +#define ADC_SL2CFG_PRMODE2_Pos (16UL) /*!< PRMODE2 (Bit 16) */ +#define ADC_SL2CFG_PRMODE2_Msk (0x30000UL) /*!< PRMODE2 (Bitfield-Mask: 0x03) */ +#define ADC_SL2CFG_CHSEL2_Pos (8UL) /*!< CHSEL2 (Bit 8) */ +#define ADC_SL2CFG_CHSEL2_Msk (0xf00UL) /*!< CHSEL2 (Bitfield-Mask: 0x0f) */ +#define ADC_SL2CFG_WCEN2_Pos (1UL) /*!< WCEN2 (Bit 1) */ +#define ADC_SL2CFG_WCEN2_Msk (0x2UL) /*!< WCEN2 (Bitfield-Mask: 0x01) */ +#define ADC_SL2CFG_SLEN2_Pos (0UL) /*!< SLEN2 (Bit 0) */ +#define ADC_SL2CFG_SLEN2_Msk (0x1UL) /*!< SLEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL3CFG ========================================================= */ +#define ADC_SL3CFG_ADSEL3_Pos (24UL) /*!< ADSEL3 (Bit 24) */ +#define ADC_SL3CFG_ADSEL3_Msk (0x7000000UL) /*!< ADSEL3 (Bitfield-Mask: 0x07) */ +#define ADC_SL3CFG_PRMODE3_Pos (16UL) /*!< PRMODE3 (Bit 16) */ +#define ADC_SL3CFG_PRMODE3_Msk (0x30000UL) /*!< PRMODE3 (Bitfield-Mask: 0x03) */ +#define ADC_SL3CFG_CHSEL3_Pos (8UL) /*!< CHSEL3 (Bit 8) */ +#define ADC_SL3CFG_CHSEL3_Msk (0xf00UL) /*!< CHSEL3 (Bitfield-Mask: 0x0f) */ +#define ADC_SL3CFG_WCEN3_Pos (1UL) /*!< WCEN3 (Bit 1) */ +#define ADC_SL3CFG_WCEN3_Msk (0x2UL) /*!< WCEN3 (Bitfield-Mask: 0x01) */ +#define ADC_SL3CFG_SLEN3_Pos (0UL) /*!< SLEN3 (Bit 0) */ +#define ADC_SL3CFG_SLEN3_Msk (0x1UL) /*!< SLEN3 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL4CFG ========================================================= */ +#define ADC_SL4CFG_ADSEL4_Pos (24UL) /*!< ADSEL4 (Bit 24) */ +#define ADC_SL4CFG_ADSEL4_Msk (0x7000000UL) /*!< ADSEL4 (Bitfield-Mask: 0x07) */ +#define ADC_SL4CFG_PRMODE4_Pos (16UL) /*!< PRMODE4 (Bit 16) */ +#define ADC_SL4CFG_PRMODE4_Msk (0x30000UL) /*!< PRMODE4 (Bitfield-Mask: 0x03) */ +#define ADC_SL4CFG_CHSEL4_Pos (8UL) /*!< CHSEL4 (Bit 8) */ +#define ADC_SL4CFG_CHSEL4_Msk (0xf00UL) /*!< CHSEL4 (Bitfield-Mask: 0x0f) */ +#define ADC_SL4CFG_WCEN4_Pos (1UL) /*!< WCEN4 (Bit 1) */ +#define ADC_SL4CFG_WCEN4_Msk (0x2UL) /*!< WCEN4 (Bitfield-Mask: 0x01) */ +#define ADC_SL4CFG_SLEN4_Pos (0UL) /*!< SLEN4 (Bit 0) */ +#define ADC_SL4CFG_SLEN4_Msk (0x1UL) /*!< SLEN4 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL5CFG ========================================================= */ +#define ADC_SL5CFG_ADSEL5_Pos (24UL) /*!< ADSEL5 (Bit 24) */ +#define ADC_SL5CFG_ADSEL5_Msk (0x7000000UL) /*!< ADSEL5 (Bitfield-Mask: 0x07) */ +#define ADC_SL5CFG_PRMODE5_Pos (16UL) /*!< PRMODE5 (Bit 16) */ +#define ADC_SL5CFG_PRMODE5_Msk (0x30000UL) /*!< PRMODE5 (Bitfield-Mask: 0x03) */ +#define ADC_SL5CFG_CHSEL5_Pos (8UL) /*!< CHSEL5 (Bit 8) */ +#define ADC_SL5CFG_CHSEL5_Msk (0xf00UL) /*!< CHSEL5 (Bitfield-Mask: 0x0f) */ +#define ADC_SL5CFG_WCEN5_Pos (1UL) /*!< WCEN5 (Bit 1) */ +#define ADC_SL5CFG_WCEN5_Msk (0x2UL) /*!< WCEN5 (Bitfield-Mask: 0x01) */ +#define ADC_SL5CFG_SLEN5_Pos (0UL) /*!< SLEN5 (Bit 0) */ +#define ADC_SL5CFG_SLEN5_Msk (0x1UL) /*!< SLEN5 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL6CFG ========================================================= */ +#define ADC_SL6CFG_ADSEL6_Pos (24UL) /*!< ADSEL6 (Bit 24) */ +#define ADC_SL6CFG_ADSEL6_Msk (0x7000000UL) /*!< ADSEL6 (Bitfield-Mask: 0x07) */ +#define ADC_SL6CFG_PRMODE6_Pos (16UL) /*!< PRMODE6 (Bit 16) */ +#define ADC_SL6CFG_PRMODE6_Msk (0x30000UL) /*!< PRMODE6 (Bitfield-Mask: 0x03) */ +#define ADC_SL6CFG_CHSEL6_Pos (8UL) /*!< CHSEL6 (Bit 8) */ +#define ADC_SL6CFG_CHSEL6_Msk (0xf00UL) /*!< CHSEL6 (Bitfield-Mask: 0x0f) */ +#define ADC_SL6CFG_WCEN6_Pos (1UL) /*!< WCEN6 (Bit 1) */ +#define ADC_SL6CFG_WCEN6_Msk (0x2UL) /*!< WCEN6 (Bitfield-Mask: 0x01) */ +#define ADC_SL6CFG_SLEN6_Pos (0UL) /*!< SLEN6 (Bit 0) */ +#define ADC_SL6CFG_SLEN6_Msk (0x1UL) /*!< SLEN6 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL7CFG ========================================================= */ +#define ADC_SL7CFG_ADSEL7_Pos (24UL) /*!< ADSEL7 (Bit 24) */ +#define ADC_SL7CFG_ADSEL7_Msk (0x7000000UL) /*!< ADSEL7 (Bitfield-Mask: 0x07) */ +#define ADC_SL7CFG_PRMODE7_Pos (16UL) /*!< PRMODE7 (Bit 16) */ +#define ADC_SL7CFG_PRMODE7_Msk (0x30000UL) /*!< PRMODE7 (Bitfield-Mask: 0x03) */ +#define ADC_SL7CFG_CHSEL7_Pos (8UL) /*!< CHSEL7 (Bit 8) */ +#define ADC_SL7CFG_CHSEL7_Msk (0xf00UL) /*!< CHSEL7 (Bitfield-Mask: 0x0f) */ +#define ADC_SL7CFG_WCEN7_Pos (1UL) /*!< WCEN7 (Bit 1) */ +#define ADC_SL7CFG_WCEN7_Msk (0x2UL) /*!< WCEN7 (Bitfield-Mask: 0x01) */ +#define ADC_SL7CFG_SLEN7_Pos (0UL) /*!< SLEN7 (Bit 0) */ +#define ADC_SL7CFG_SLEN7_Msk (0x1UL) /*!< SLEN7 (Bitfield-Mask: 0x01) */ +/* ========================================================= WULIM ========================================================= */ +#define ADC_WULIM_ULIM_Pos (0UL) /*!< ULIM (Bit 0) */ +#define ADC_WULIM_ULIM_Msk (0xfffffUL) /*!< ULIM (Bitfield-Mask: 0xfffff) */ +/* ========================================================= WLLIM ========================================================= */ +#define ADC_WLLIM_LLIM_Pos (0UL) /*!< LLIM (Bit 0) */ +#define ADC_WLLIM_LLIM_Msk (0xfffffUL) /*!< LLIM (Bitfield-Mask: 0xfffff) */ +/* ======================================================== SCWLIM ========================================================= */ +#define ADC_SCWLIM_SCWLIMEN_Pos (0UL) /*!< SCWLIMEN (Bit 0) */ +#define ADC_SCWLIM_SCWLIMEN_Msk (0x1UL) /*!< SCWLIMEN (Bitfield-Mask: 0x01) */ +/* ========================================================= FIFO ========================================================== */ +#define ADC_FIFO_RSVD_Pos (31UL) /*!< RSVD (Bit 31) */ +#define ADC_FIFO_RSVD_Msk (0x80000000UL) /*!< RSVD (Bitfield-Mask: 0x01) */ +#define ADC_FIFO_SLOTNUM_Pos (28UL) /*!< SLOTNUM (Bit 28) */ +#define ADC_FIFO_SLOTNUM_Msk (0x70000000UL) /*!< SLOTNUM (Bitfield-Mask: 0x07) */ +#define ADC_FIFO_COUNT_Pos (20UL) /*!< COUNT (Bit 20) */ +#define ADC_FIFO_COUNT_Msk (0xff00000UL) /*!< COUNT (Bitfield-Mask: 0xff) */ +#define ADC_FIFO_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define ADC_FIFO_DATA_Msk (0xfffffUL) /*!< DATA (Bitfield-Mask: 0xfffff) */ +/* ======================================================== FIFOPR ========================================================= */ +#define ADC_FIFOPR_RSVDPR_Pos (31UL) /*!< RSVDPR (Bit 31) */ +#define ADC_FIFOPR_RSVDPR_Msk (0x80000000UL) /*!< RSVDPR (Bitfield-Mask: 0x01) */ +#define ADC_FIFOPR_SLOTNUMPR_Pos (28UL) /*!< SLOTNUMPR (Bit 28) */ +#define ADC_FIFOPR_SLOTNUMPR_Msk (0x70000000UL) /*!< SLOTNUMPR (Bitfield-Mask: 0x07) */ +#define ADC_FIFOPR_COUNT_Pos (20UL) /*!< COUNT (Bit 20) */ +#define ADC_FIFOPR_COUNT_Msk (0xff00000UL) /*!< COUNT (Bitfield-Mask: 0xff) */ +#define ADC_FIFOPR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define ADC_FIFOPR_DATA_Msk (0xfffffUL) /*!< DATA (Bitfield-Mask: 0xfffff) */ +/* ========================================================= INTEN ========================================================= */ +#define ADC_INTEN_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define ADC_INTEN_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define ADC_INTEN_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTEN_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTEN_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTEN_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTEN_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTEN_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTEN_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define ADC_INTSTAT_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define ADC_INTSTAT_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define ADC_INTSTAT_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTSTAT_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTSTAT_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTSTAT_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTSTAT_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTSTAT_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTSTAT_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define ADC_INTCLR_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define ADC_INTCLR_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define ADC_INTCLR_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTCLR_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTCLR_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTCLR_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTCLR_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTCLR_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTCLR_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define ADC_INTSET_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define ADC_INTSET_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define ADC_INTSET_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTSET_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTSET_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTSET_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTSET_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTSET_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTSET_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================= DMATRIGEN ======================================================= */ +#define ADC_DMATRIGEN_DFIFOFULL_Pos (1UL) /*!< DFIFOFULL (Bit 1) */ +#define ADC_DMATRIGEN_DFIFOFULL_Msk (0x2UL) /*!< DFIFOFULL (Bitfield-Mask: 0x01) */ +#define ADC_DMATRIGEN_DFIFO75_Pos (0UL) /*!< DFIFO75 (Bit 0) */ +#define ADC_DMATRIGEN_DFIFO75_Msk (0x1UL) /*!< DFIFO75 (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +#define ADC_DMATRIGSTAT_DFULLSTAT_Pos (1UL) /*!< DFULLSTAT (Bit 1) */ +#define ADC_DMATRIGSTAT_DFULLSTAT_Msk (0x2UL) /*!< DFULLSTAT (Bitfield-Mask: 0x01) */ +#define ADC_DMATRIGSTAT_D75STAT_Pos (0UL) /*!< D75STAT (Bit 0) */ +#define ADC_DMATRIGSTAT_D75STAT_Msk (0x1UL) /*!< D75STAT (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACFG ========================================================= */ +#define ADC_DMACFG_DPWROFF_Pos (18UL) /*!< DPWROFF (Bit 18) */ +#define ADC_DMACFG_DPWROFF_Msk (0x40000UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMAMSK_Pos (17UL) /*!< DMAMSK (Bit 17) */ +#define ADC_DMACFG_DMAMSK_Msk (0x20000UL) /*!< DMAMSK (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMAHONSTAT_Pos (16UL) /*!< DMAHONSTAT (Bit 16) */ +#define ADC_DMACFG_DMAHONSTAT_Msk (0x10000UL) /*!< DMAHONSTAT (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMADYNPRI_Pos (9UL) /*!< DMADYNPRI (Bit 9) */ +#define ADC_DMACFG_DMADYNPRI_Msk (0x200UL) /*!< DMADYNPRI (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */ +#define ADC_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMADIR_Pos (2UL) /*!< DMADIR (Bit 2) */ +#define ADC_DMACFG_DMADIR_Msk (0x4UL) /*!< DMADIR (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */ +#define ADC_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +#define ADC_DMATOTCOUNT_TOTCOUNT_Pos (2UL) /*!< TOTCOUNT (Bit 2) */ +#define ADC_DMATOTCOUNT_TOTCOUNT_Msk (0x3fffcUL) /*!< TOTCOUNT (Bitfield-Mask: 0xffff) */ +/* ====================================================== DMATARGADDR ====================================================== */ +#define ADC_DMATARGADDR_UTARGADDR_Pos (19UL) /*!< UTARGADDR (Bit 19) */ +#define ADC_DMATARGADDR_UTARGADDR_Msk (0xfff80000UL) /*!< UTARGADDR (Bitfield-Mask: 0x1fff) */ +#define ADC_DMATARGADDR_LTARGADDR_Pos (0UL) /*!< LTARGADDR (Bit 0) */ +#define ADC_DMATARGADDR_LTARGADDR_Msk (0x7ffffUL) /*!< LTARGADDR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== DMASTAT ======================================================== */ +#define ADC_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */ +#define ADC_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */ +#define ADC_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */ +#define ADC_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */ +#define ADC_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */ +#define ADC_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ APBDMA ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BBVALUE ======================================================== */ +#define APBDMA_BBVALUE_PIN_Pos (16UL) /*!< PIN (Bit 16) */ +#define APBDMA_BBVALUE_PIN_Msk (0xff0000UL) /*!< PIN (Bitfield-Mask: 0xff) */ +#define APBDMA_BBVALUE_DATAOUT_Pos (0UL) /*!< DATAOUT (Bit 0) */ +#define APBDMA_BBVALUE_DATAOUT_Msk (0xffUL) /*!< DATAOUT (Bitfield-Mask: 0xff) */ +/* ====================================================== BBSETCLEAR ======================================================= */ +#define APBDMA_BBSETCLEAR_CLEAR_Pos (16UL) /*!< CLEAR (Bit 16) */ +#define APBDMA_BBSETCLEAR_CLEAR_Msk (0xff0000UL) /*!< CLEAR (Bitfield-Mask: 0xff) */ +#define APBDMA_BBSETCLEAR_SET_Pos (0UL) /*!< SET (Bit 0) */ +#define APBDMA_BBSETCLEAR_SET_Msk (0xffUL) /*!< SET (Bitfield-Mask: 0xff) */ +/* ======================================================== BBINPUT ======================================================== */ +#define APBDMA_BBINPUT_DATAIN_Pos (0UL) /*!< DATAIN (Bit 0) */ +#define APBDMA_BBINPUT_DATAIN_Msk (0xffUL) /*!< DATAIN (Bitfield-Mask: 0xff) */ +/* ======================================================= DEBUGDATA ======================================================= */ +#define APBDMA_DEBUGDATA_DEBUGDATA_Pos (0UL) /*!< DEBUGDATA (Bit 0) */ +#define APBDMA_DEBUGDATA_DEBUGDATA_Msk (0xffffffffUL) /*!< DEBUGDATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DEBUG ========================================================= */ +#define APBDMA_DEBUG_DEBUGEN_Pos (0UL) /*!< DEBUGEN (Bit 0) */ +#define APBDMA_DEBUG_DEBUGEN_Msk (0xfUL) /*!< DEBUGEN (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ BLEIF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FIFO ========================================================== */ +#define BLEIF_FIFO_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */ +#define BLEIF_FIFO_FIFO_Msk (0xffffffffUL) /*!< FIFO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FIFOPTR ======================================================== */ +#define BLEIF_FIFOPTR_FIFO1REM_Pos (24UL) /*!< FIFO1REM (Bit 24) */ +#define BLEIF_FIFOPTR_FIFO1REM_Msk (0xff000000UL) /*!< FIFO1REM (Bitfield-Mask: 0xff) */ +#define BLEIF_FIFOPTR_FIFO1SIZ_Pos (16UL) /*!< FIFO1SIZ (Bit 16) */ +#define BLEIF_FIFOPTR_FIFO1SIZ_Msk (0xff0000UL) /*!< FIFO1SIZ (Bitfield-Mask: 0xff) */ +#define BLEIF_FIFOPTR_FIFO0REM_Pos (8UL) /*!< FIFO0REM (Bit 8) */ +#define BLEIF_FIFOPTR_FIFO0REM_Msk (0xff00UL) /*!< FIFO0REM (Bitfield-Mask: 0xff) */ +#define BLEIF_FIFOPTR_FIFO0SIZ_Pos (0UL) /*!< FIFO0SIZ (Bit 0) */ +#define BLEIF_FIFOPTR_FIFO0SIZ_Msk (0xffUL) /*!< FIFO0SIZ (Bitfield-Mask: 0xff) */ +/* ======================================================== FIFOTHR ======================================================== */ +#define BLEIF_FIFOTHR_FIFOWTHR_Pos (8UL) /*!< FIFOWTHR (Bit 8) */ +#define BLEIF_FIFOTHR_FIFOWTHR_Msk (0x3f00UL) /*!< FIFOWTHR (Bitfield-Mask: 0x3f) */ +#define BLEIF_FIFOTHR_FIFORTHR_Pos (0UL) /*!< FIFORTHR (Bit 0) */ +#define BLEIF_FIFOTHR_FIFORTHR_Msk (0x3fUL) /*!< FIFORTHR (Bitfield-Mask: 0x3f) */ +/* ======================================================== FIFOPOP ======================================================== */ +#define BLEIF_FIFOPOP_FIFODOUT_Pos (0UL) /*!< FIFODOUT (Bit 0) */ +#define BLEIF_FIFOPOP_FIFODOUT_Msk (0xffffffffUL) /*!< FIFODOUT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FIFOPUSH ======================================================== */ +#define BLEIF_FIFOPUSH_FIFODIN_Pos (0UL) /*!< FIFODIN (Bit 0) */ +#define BLEIF_FIFOPUSH_FIFODIN_Msk (0xffffffffUL) /*!< FIFODIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FIFOCTRL ======================================================== */ +#define BLEIF_FIFOCTRL_FIFORSTN_Pos (1UL) /*!< FIFORSTN (Bit 1) */ +#define BLEIF_FIFOCTRL_FIFORSTN_Msk (0x2UL) /*!< FIFORSTN (Bitfield-Mask: 0x01) */ +#define BLEIF_FIFOCTRL_POPWR_Pos (0UL) /*!< POPWR (Bit 0) */ +#define BLEIF_FIFOCTRL_POPWR_Msk (0x1UL) /*!< POPWR (Bitfield-Mask: 0x01) */ +/* ======================================================== FIFOLOC ======================================================== */ +#define BLEIF_FIFOLOC_FIFORPTR_Pos (8UL) /*!< FIFORPTR (Bit 8) */ +#define BLEIF_FIFOLOC_FIFORPTR_Msk (0xf00UL) /*!< FIFORPTR (Bitfield-Mask: 0x0f) */ +#define BLEIF_FIFOLOC_FIFOWPTR_Pos (0UL) /*!< FIFOWPTR (Bit 0) */ +#define BLEIF_FIFOLOC_FIFOWPTR_Msk (0xfUL) /*!< FIFOWPTR (Bitfield-Mask: 0x0f) */ +/* ======================================================== CLKCFG ========================================================= */ +#define BLEIF_CLKCFG_DIV3_Pos (12UL) /*!< DIV3 (Bit 12) */ +#define BLEIF_CLKCFG_DIV3_Msk (0x1000UL) /*!< DIV3 (Bitfield-Mask: 0x01) */ +#define BLEIF_CLKCFG_CLK32KEN_Pos (11UL) /*!< CLK32KEN (Bit 11) */ +#define BLEIF_CLKCFG_CLK32KEN_Msk (0x800UL) /*!< CLK32KEN (Bitfield-Mask: 0x01) */ +#define BLEIF_CLKCFG_FSEL_Pos (8UL) /*!< FSEL (Bit 8) */ +#define BLEIF_CLKCFG_FSEL_Msk (0x700UL) /*!< FSEL (Bitfield-Mask: 0x07) */ +#define BLEIF_CLKCFG_IOCLKEN_Pos (0UL) /*!< IOCLKEN (Bit 0) */ +#define BLEIF_CLKCFG_IOCLKEN_Msk (0x1UL) /*!< IOCLKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CMD ========================================================== */ +#define BLEIF_CMD_OFFSETLO_Pos (24UL) /*!< OFFSETLO (Bit 24) */ +#define BLEIF_CMD_OFFSETLO_Msk (0xff000000UL) /*!< OFFSETLO (Bitfield-Mask: 0xff) */ +#define BLEIF_CMD_CMDSEL_Pos (20UL) /*!< CMDSEL (Bit 20) */ +#define BLEIF_CMD_CMDSEL_Msk (0x300000UL) /*!< CMDSEL (Bitfield-Mask: 0x03) */ +#define BLEIF_CMD_TSIZE_Pos (8UL) /*!< TSIZE (Bit 8) */ +#define BLEIF_CMD_TSIZE_Msk (0xfff00UL) /*!< TSIZE (Bitfield-Mask: 0xfff) */ +#define BLEIF_CMD_CONT_Pos (7UL) /*!< CONT (Bit 7) */ +#define BLEIF_CMD_CONT_Msk (0x80UL) /*!< CONT (Bitfield-Mask: 0x01) */ +#define BLEIF_CMD_OFFSETCNT_Pos (5UL) /*!< OFFSETCNT (Bit 5) */ +#define BLEIF_CMD_OFFSETCNT_Msk (0x60UL) /*!< OFFSETCNT (Bitfield-Mask: 0x03) */ +#define BLEIF_CMD_CMD_Pos (0UL) /*!< CMD (Bit 0) */ +#define BLEIF_CMD_CMD_Msk (0x1fUL) /*!< CMD (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMDRPT ========================================================= */ +#define BLEIF_CMDRPT_CMDRPT_Pos (0UL) /*!< CMDRPT (Bit 0) */ +#define BLEIF_CMDRPT_CMDRPT_Msk (0x1fUL) /*!< CMDRPT (Bitfield-Mask: 0x1f) */ +/* ======================================================= OFFSETHI ======================================================== */ +#define BLEIF_OFFSETHI_OFFSETHI_Pos (0UL) /*!< OFFSETHI (Bit 0) */ +#define BLEIF_OFFSETHI_OFFSETHI_Msk (0xffffUL) /*!< OFFSETHI (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMDSTAT ======================================================== */ +#define BLEIF_CMDSTAT_CTSIZE_Pos (8UL) /*!< CTSIZE (Bit 8) */ +#define BLEIF_CMDSTAT_CTSIZE_Msk (0xfff00UL) /*!< CTSIZE (Bitfield-Mask: 0xfff) */ +#define BLEIF_CMDSTAT_CMDSTAT_Pos (5UL) /*!< CMDSTAT (Bit 5) */ +#define BLEIF_CMDSTAT_CMDSTAT_Msk (0xe0UL) /*!< CMDSTAT (Bitfield-Mask: 0x07) */ +#define BLEIF_CMDSTAT_CCMD_Pos (0UL) /*!< CCMD (Bit 0) */ +#define BLEIF_CMDSTAT_CCMD_Msk (0x1fUL) /*!< CCMD (Bitfield-Mask: 0x1f) */ +/* ========================================================= INTEN ========================================================= */ +#define BLEIF_INTEN_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */ +#define BLEIF_INTEN_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */ +#define BLEIF_INTEN_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */ +#define BLEIF_INTEN_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */ +#define BLEIF_INTEN_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */ +#define BLEIF_INTEN_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */ +#define BLEIF_INTEN_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_DERR_Pos (10UL) /*!< DERR (Bit 10) */ +#define BLEIF_INTEN_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */ +#define BLEIF_INTEN_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */ +#define BLEIF_INTEN_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */ +#define BLEIF_INTEN_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define BLEIF_INTEN_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define BLEIF_INTEN_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */ +#define BLEIF_INTEN_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define BLEIF_INTEN_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define BLEIF_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define BLEIF_INTEN_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define BLEIF_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define BLEIF_INTSTAT_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */ +#define BLEIF_INTSTAT_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */ +#define BLEIF_INTSTAT_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */ +#define BLEIF_INTSTAT_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */ +#define BLEIF_INTSTAT_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */ +#define BLEIF_INTSTAT_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */ +#define BLEIF_INTSTAT_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_DERR_Pos (10UL) /*!< DERR (Bit 10) */ +#define BLEIF_INTSTAT_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */ +#define BLEIF_INTSTAT_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */ +#define BLEIF_INTSTAT_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */ +#define BLEIF_INTSTAT_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define BLEIF_INTSTAT_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define BLEIF_INTSTAT_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */ +#define BLEIF_INTSTAT_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define BLEIF_INTSTAT_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define BLEIF_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define BLEIF_INTSTAT_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define BLEIF_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define BLEIF_INTCLR_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */ +#define BLEIF_INTCLR_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */ +#define BLEIF_INTCLR_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */ +#define BLEIF_INTCLR_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */ +#define BLEIF_INTCLR_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */ +#define BLEIF_INTCLR_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */ +#define BLEIF_INTCLR_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_DERR_Pos (10UL) /*!< DERR (Bit 10) */ +#define BLEIF_INTCLR_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */ +#define BLEIF_INTCLR_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */ +#define BLEIF_INTCLR_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */ +#define BLEIF_INTCLR_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define BLEIF_INTCLR_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define BLEIF_INTCLR_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */ +#define BLEIF_INTCLR_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define BLEIF_INTCLR_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define BLEIF_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define BLEIF_INTCLR_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define BLEIF_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define BLEIF_INTSET_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */ +#define BLEIF_INTSET_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */ +#define BLEIF_INTSET_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */ +#define BLEIF_INTSET_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */ +#define BLEIF_INTSET_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */ +#define BLEIF_INTSET_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */ +#define BLEIF_INTSET_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_DERR_Pos (10UL) /*!< DERR (Bit 10) */ +#define BLEIF_INTSET_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */ +#define BLEIF_INTSET_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */ +#define BLEIF_INTSET_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */ +#define BLEIF_INTSET_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define BLEIF_INTSET_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define BLEIF_INTSET_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */ +#define BLEIF_INTSET_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define BLEIF_INTSET_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define BLEIF_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define BLEIF_INTSET_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define BLEIF_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================= DMATRIGEN ======================================================= */ +#define BLEIF_DMATRIGEN_DTHREN_Pos (1UL) /*!< DTHREN (Bit 1) */ +#define BLEIF_DMATRIGEN_DTHREN_Msk (0x2UL) /*!< DTHREN (Bitfield-Mask: 0x01) */ +#define BLEIF_DMATRIGEN_DCMDCMPEN_Pos (0UL) /*!< DCMDCMPEN (Bit 0) */ +#define BLEIF_DMATRIGEN_DCMDCMPEN_Msk (0x1UL) /*!< DCMDCMPEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +#define BLEIF_DMATRIGSTAT_DTOTCMP_Pos (2UL) /*!< DTOTCMP (Bit 2) */ +#define BLEIF_DMATRIGSTAT_DTOTCMP_Msk (0x4UL) /*!< DTOTCMP (Bitfield-Mask: 0x01) */ +#define BLEIF_DMATRIGSTAT_DTHR_Pos (1UL) /*!< DTHR (Bit 1) */ +#define BLEIF_DMATRIGSTAT_DTHR_Msk (0x2UL) /*!< DTHR (Bitfield-Mask: 0x01) */ +#define BLEIF_DMATRIGSTAT_DCMDCMP_Pos (0UL) /*!< DCMDCMP (Bit 0) */ +#define BLEIF_DMATRIGSTAT_DCMDCMP_Msk (0x1UL) /*!< DCMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACFG ========================================================= */ +#define BLEIF_DMACFG_DPWROFF_Pos (9UL) /*!< DPWROFF (Bit 9) */ +#define BLEIF_DMACFG_DPWROFF_Msk (0x200UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */ +#define BLEIF_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */ +#define BLEIF_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */ +#define BLEIF_DMACFG_DMADIR_Pos (1UL) /*!< DMADIR (Bit 1) */ +#define BLEIF_DMACFG_DMADIR_Msk (0x2UL) /*!< DMADIR (Bitfield-Mask: 0x01) */ +#define BLEIF_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */ +#define BLEIF_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +#define BLEIF_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */ +#define BLEIF_DMATOTCOUNT_TOTCOUNT_Msk (0xfffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xfff) */ +/* ====================================================== DMATARGADDR ====================================================== */ +#define BLEIF_DMATARGADDR_TARGADDR28_Pos (28UL) /*!< TARGADDR28 (Bit 28) */ +#define BLEIF_DMATARGADDR_TARGADDR28_Msk (0x10000000UL) /*!< TARGADDR28 (Bitfield-Mask: 0x01) */ +#define BLEIF_DMATARGADDR_TARGADDR_Pos (0UL) /*!< TARGADDR (Bit 0) */ +#define BLEIF_DMATARGADDR_TARGADDR_Msk (0xfffffUL) /*!< TARGADDR (Bitfield-Mask: 0xfffff) */ +/* ======================================================== DMASTAT ======================================================== */ +#define BLEIF_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */ +#define BLEIF_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */ +#define BLEIF_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */ +#define BLEIF_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */ +#define BLEIF_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */ +#define BLEIF_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */ +/* ========================================================= CQCFG ========================================================= */ +#define BLEIF_CQCFG_CQPRI_Pos (1UL) /*!< CQPRI (Bit 1) */ +#define BLEIF_CQCFG_CQPRI_Msk (0x2UL) /*!< CQPRI (Bitfield-Mask: 0x01) */ +#define BLEIF_CQCFG_CQEN_Pos (0UL) /*!< CQEN (Bit 0) */ +#define BLEIF_CQCFG_CQEN_Msk (0x1UL) /*!< CQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CQADDR ========================================================= */ +#define BLEIF_CQADDR_CQADDR28_Pos (28UL) /*!< CQADDR28 (Bit 28) */ +#define BLEIF_CQADDR_CQADDR28_Msk (0x10000000UL) /*!< CQADDR28 (Bitfield-Mask: 0x01) */ +#define BLEIF_CQADDR_CQADDR_Pos (2UL) /*!< CQADDR (Bit 2) */ +#define BLEIF_CQADDR_CQADDR_Msk (0xffffcUL) /*!< CQADDR (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== CQSTAT ========================================================= */ +#define BLEIF_CQSTAT_CQERR_Pos (2UL) /*!< CQERR (Bit 2) */ +#define BLEIF_CQSTAT_CQERR_Msk (0x4UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define BLEIF_CQSTAT_CQPAUSED_Pos (1UL) /*!< CQPAUSED (Bit 1) */ +#define BLEIF_CQSTAT_CQPAUSED_Msk (0x2UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define BLEIF_CQSTAT_CQTIP_Pos (0UL) /*!< CQTIP (Bit 0) */ +#define BLEIF_CQSTAT_CQTIP_Msk (0x1UL) /*!< CQTIP (Bitfield-Mask: 0x01) */ +/* ======================================================== CQFLAGS ======================================================== */ +#define BLEIF_CQFLAGS_CQIRQMASK_Pos (16UL) /*!< CQIRQMASK (Bit 16) */ +#define BLEIF_CQFLAGS_CQIRQMASK_Msk (0xffff0000UL) /*!< CQIRQMASK (Bitfield-Mask: 0xffff) */ +#define BLEIF_CQFLAGS_CQFLAGS_Pos (0UL) /*!< CQFLAGS (Bit 0) */ +#define BLEIF_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< CQFLAGS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CQSETCLEAR ======================================================= */ +#define BLEIF_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< CQFCLR (Bit 16) */ +#define BLEIF_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< CQFCLR (Bitfield-Mask: 0xff) */ +#define BLEIF_CQSETCLEAR_CQFTGL_Pos (8UL) /*!< CQFTGL (Bit 8) */ +#define BLEIF_CQSETCLEAR_CQFTGL_Msk (0xff00UL) /*!< CQFTGL (Bitfield-Mask: 0xff) */ +#define BLEIF_CQSETCLEAR_CQFSET_Pos (0UL) /*!< CQFSET (Bit 0) */ +#define BLEIF_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< CQFSET (Bitfield-Mask: 0xff) */ +/* ======================================================= CQPAUSEEN ======================================================= */ +#define BLEIF_CQPAUSEEN_CQPEN_Pos (0UL) /*!< CQPEN (Bit 0) */ +#define BLEIF_CQPAUSEEN_CQPEN_Msk (0xffffUL) /*!< CQPEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= CQCURIDX ======================================================== */ +#define BLEIF_CQCURIDX_CQCURIDX_Pos (0UL) /*!< CQCURIDX (Bit 0) */ +#define BLEIF_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< CQCURIDX (Bitfield-Mask: 0xff) */ +/* ======================================================= CQENDIDX ======================================================== */ +#define BLEIF_CQENDIDX_CQENDIDX_Pos (0UL) /*!< CQENDIDX (Bit 0) */ +#define BLEIF_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< CQENDIDX (Bitfield-Mask: 0xff) */ +/* ======================================================== STATUS ========================================================= */ +#define BLEIF_STATUS_IDLEST_Pos (2UL) /*!< IDLEST (Bit 2) */ +#define BLEIF_STATUS_IDLEST_Msk (0x4UL) /*!< IDLEST (Bitfield-Mask: 0x01) */ +#define BLEIF_STATUS_CMDACT_Pos (1UL) /*!< CMDACT (Bit 1) */ +#define BLEIF_STATUS_CMDACT_Msk (0x2UL) /*!< CMDACT (Bitfield-Mask: 0x01) */ +#define BLEIF_STATUS_ERR_Pos (0UL) /*!< ERR (Bit 0) */ +#define BLEIF_STATUS_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== MSPICFG ======================================================== */ +#define BLEIF_MSPICFG_MSPIRST_Pos (30UL) /*!< MSPIRST (Bit 30) */ +#define BLEIF_MSPICFG_MSPIRST_Msk (0x40000000UL) /*!< MSPIRST (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_DOUTDLY_Pos (27UL) /*!< DOUTDLY (Bit 27) */ +#define BLEIF_MSPICFG_DOUTDLY_Msk (0x38000000UL) /*!< DOUTDLY (Bitfield-Mask: 0x07) */ +#define BLEIF_MSPICFG_DINDLY_Pos (24UL) /*!< DINDLY (Bit 24) */ +#define BLEIF_MSPICFG_DINDLY_Msk (0x7000000UL) /*!< DINDLY (Bitfield-Mask: 0x07) */ +#define BLEIF_MSPICFG_SPILSB_Pos (23UL) /*!< SPILSB (Bit 23) */ +#define BLEIF_MSPICFG_SPILSB_Msk (0x800000UL) /*!< SPILSB (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_RDFCPOL_Pos (22UL) /*!< RDFCPOL (Bit 22) */ +#define BLEIF_MSPICFG_RDFCPOL_Msk (0x400000UL) /*!< RDFCPOL (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_WTFCPOL_Pos (21UL) /*!< WTFCPOL (Bit 21) */ +#define BLEIF_MSPICFG_WTFCPOL_Msk (0x200000UL) /*!< WTFCPOL (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_RDFC_Pos (17UL) /*!< RDFC (Bit 17) */ +#define BLEIF_MSPICFG_RDFC_Msk (0x20000UL) /*!< RDFC (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_WTFC_Pos (16UL) /*!< WTFC (Bit 16) */ +#define BLEIF_MSPICFG_WTFC_Msk (0x10000UL) /*!< WTFC (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_FULLDUP_Pos (2UL) /*!< FULLDUP (Bit 2) */ +#define BLEIF_MSPICFG_FULLDUP_Msk (0x4UL) /*!< FULLDUP (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_SPHA_Pos (1UL) /*!< SPHA (Bit 1) */ +#define BLEIF_MSPICFG_SPHA_Msk (0x2UL) /*!< SPHA (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_SPOL_Pos (0UL) /*!< SPOL (Bit 0) */ +#define BLEIF_MSPICFG_SPOL_Msk (0x1UL) /*!< SPOL (Bitfield-Mask: 0x01) */ +/* ======================================================== BLECFG ========================================================= */ +#define BLEIF_BLECFG_SPIISOCTL_Pos (14UL) /*!< SPIISOCTL (Bit 14) */ +#define BLEIF_BLECFG_SPIISOCTL_Msk (0xc000UL) /*!< SPIISOCTL (Bitfield-Mask: 0x03) */ +#define BLEIF_BLECFG_PWRISOCTL_Pos (12UL) /*!< PWRISOCTL (Bit 12) */ +#define BLEIF_BLECFG_PWRISOCTL_Msk (0x3000UL) /*!< PWRISOCTL (Bitfield-Mask: 0x03) */ +#define BLEIF_BLECFG_STAYASLEEP_Pos (11UL) /*!< STAYASLEEP (Bit 11) */ +#define BLEIF_BLECFG_STAYASLEEP_Msk (0x800UL) /*!< STAYASLEEP (Bitfield-Mask: 0x01) */ +#define BLEIF_BLECFG_FRCCLK_Pos (10UL) /*!< FRCCLK (Bit 10) */ +#define BLEIF_BLECFG_FRCCLK_Msk (0x400UL) /*!< FRCCLK (Bitfield-Mask: 0x01) */ +#define BLEIF_BLECFG_MCUFRCSLP_Pos (9UL) /*!< MCUFRCSLP (Bit 9) */ +#define BLEIF_BLECFG_MCUFRCSLP_Msk (0x200UL) /*!< MCUFRCSLP (Bitfield-Mask: 0x01) */ +#define BLEIF_BLECFG_WT4ACTOFF_Pos (8UL) /*!< WT4ACTOFF (Bit 8) */ +#define BLEIF_BLECFG_WT4ACTOFF_Msk (0x100UL) /*!< WT4ACTOFF (Bitfield-Mask: 0x01) */ +#define BLEIF_BLECFG_BLEHREQCTL_Pos (6UL) /*!< BLEHREQCTL (Bit 6) */ +#define BLEIF_BLECFG_BLEHREQCTL_Msk (0xc0UL) /*!< BLEHREQCTL (Bitfield-Mask: 0x03) */ +#define BLEIF_BLECFG_DCDCFLGCTL_Pos (4UL) /*!< DCDCFLGCTL (Bit 4) */ +#define BLEIF_BLECFG_DCDCFLGCTL_Msk (0x30UL) /*!< DCDCFLGCTL (Bitfield-Mask: 0x03) */ +#define BLEIF_BLECFG_WAKEUPCTL_Pos (2UL) /*!< WAKEUPCTL (Bit 2) */ +#define BLEIF_BLECFG_WAKEUPCTL_Msk (0xcUL) /*!< WAKEUPCTL (Bitfield-Mask: 0x03) */ +#define BLEIF_BLECFG_BLERSTN_Pos (1UL) /*!< BLERSTN (Bit 1) */ +#define BLEIF_BLECFG_BLERSTN_Msk (0x2UL) /*!< BLERSTN (Bitfield-Mask: 0x01) */ +#define BLEIF_BLECFG_PWRSMEN_Pos (0UL) /*!< PWRSMEN (Bit 0) */ +#define BLEIF_BLECFG_PWRSMEN_Msk (0x1UL) /*!< PWRSMEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PWRCMD ========================================================= */ +#define BLEIF_PWRCMD_RESTART_Pos (1UL) /*!< RESTART (Bit 1) */ +#define BLEIF_PWRCMD_RESTART_Msk (0x2UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define BLEIF_PWRCMD_WAKEREQ_Pos (0UL) /*!< WAKEREQ (Bit 0) */ +#define BLEIF_PWRCMD_WAKEREQ_Msk (0x1UL) /*!< WAKEREQ (Bitfield-Mask: 0x01) */ +/* ======================================================== BSTATUS ======================================================== */ +#define BLEIF_BSTATUS_BLEHREQ_Pos (12UL) /*!< BLEHREQ (Bit 12) */ +#define BLEIF_BSTATUS_BLEHREQ_Msk (0x1000UL) /*!< BLEHREQ (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_BLEHACK_Pos (11UL) /*!< BLEHACK (Bit 11) */ +#define BLEIF_BSTATUS_BLEHACK_Msk (0x800UL) /*!< BLEHACK (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_PWRST_Pos (8UL) /*!< PWRST (Bit 8) */ +#define BLEIF_BSTATUS_PWRST_Msk (0x700UL) /*!< PWRST (Bitfield-Mask: 0x07) */ +#define BLEIF_BSTATUS_BLEIRQ_Pos (7UL) /*!< BLEIRQ (Bit 7) */ +#define BLEIF_BSTATUS_BLEIRQ_Msk (0x80UL) /*!< BLEIRQ (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_WAKEUP_Pos (6UL) /*!< WAKEUP (Bit 6) */ +#define BLEIF_BSTATUS_WAKEUP_Msk (0x40UL) /*!< WAKEUP (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_DCDCFLAG_Pos (5UL) /*!< DCDCFLAG (Bit 5) */ +#define BLEIF_BSTATUS_DCDCFLAG_Msk (0x20UL) /*!< DCDCFLAG (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_DCDCREQ_Pos (4UL) /*!< DCDCREQ (Bit 4) */ +#define BLEIF_BSTATUS_DCDCREQ_Msk (0x10UL) /*!< DCDCREQ (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_SPISTATUS_Pos (3UL) /*!< SPISTATUS (Bit 3) */ +#define BLEIF_BSTATUS_SPISTATUS_Msk (0x8UL) /*!< SPISTATUS (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_B2MSTATE_Pos (0UL) /*!< B2MSTATE (Bit 0) */ +#define BLEIF_BSTATUS_B2MSTATE_Msk (0x7UL) /*!< B2MSTATE (Bitfield-Mask: 0x07) */ +/* ======================================================== BLEDBG ========================================================= */ +#define BLEIF_BLEDBG_DBGDATA_Pos (3UL) /*!< DBGDATA (Bit 3) */ +#define BLEIF_BLEDBG_DBGDATA_Msk (0xfffffff8UL) /*!< DBGDATA (Bitfield-Mask: 0x1fffffff) */ +#define BLEIF_BLEDBG_APBCLKON_Pos (2UL) /*!< APBCLKON (Bit 2) */ +#define BLEIF_BLEDBG_APBCLKON_Msk (0x4UL) /*!< APBCLKON (Bitfield-Mask: 0x01) */ +#define BLEIF_BLEDBG_IOCLKON_Pos (1UL) /*!< IOCLKON (Bit 1) */ +#define BLEIF_BLEDBG_IOCLKON_Msk (0x2UL) /*!< IOCLKON (Bitfield-Mask: 0x01) */ +#define BLEIF_BLEDBG_DBGEN_Pos (0UL) /*!< DBGEN (Bit 0) */ +#define BLEIF_BLEDBG_DBGEN_Msk (0x1UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CACHECTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CACHECFG ======================================================== */ +#define CACHECTRL_CACHECFG_ENABLE_MONITOR_Pos (24UL) /*!< ENABLE_MONITOR (Bit 24) */ +#define CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk (0x1000000UL) /*!< ENABLE_MONITOR (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_DATA_CLKGATE_Pos (20UL) /*!< DATA_CLKGATE (Bit 20) */ +#define CACHECTRL_CACHECFG_DATA_CLKGATE_Msk (0x100000UL) /*!< DATA_CLKGATE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_CACHE_LS_Pos (11UL) /*!< CACHE_LS (Bit 11) */ +#define CACHECTRL_CACHECFG_CACHE_LS_Msk (0x800UL) /*!< CACHE_LS (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_CACHE_CLKGATE_Pos (10UL) /*!< CACHE_CLKGATE (Bit 10) */ +#define CACHECTRL_CACHECFG_CACHE_CLKGATE_Msk (0x400UL) /*!< CACHE_CLKGATE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_DCACHE_ENABLE_Pos (9UL) /*!< DCACHE_ENABLE (Bit 9) */ +#define CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk (0x200UL) /*!< DCACHE_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_ICACHE_ENABLE_Pos (8UL) /*!< ICACHE_ENABLE (Bit 8) */ +#define CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk (0x100UL) /*!< ICACHE_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_CONFIG_Pos (4UL) /*!< CONFIG (Bit 4) */ +#define CACHECTRL_CACHECFG_CONFIG_Msk (0xf0UL) /*!< CONFIG (Bitfield-Mask: 0x0f) */ +#define CACHECTRL_CACHECFG_ENABLE_NC1_Pos (3UL) /*!< ENABLE_NC1 (Bit 3) */ +#define CACHECTRL_CACHECFG_ENABLE_NC1_Msk (0x8UL) /*!< ENABLE_NC1 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_ENABLE_NC0_Pos (2UL) /*!< ENABLE_NC0 (Bit 2) */ +#define CACHECTRL_CACHECFG_ENABLE_NC0_Msk (0x4UL) /*!< ENABLE_NC0 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_LRU_Pos (1UL) /*!< LRU (Bit 1) */ +#define CACHECTRL_CACHECFG_LRU_Msk (0x2UL) /*!< LRU (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define CACHECTRL_CACHECFG_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= FLASHCFG ======================================================== */ +#define CACHECTRL_FLASHCFG_LPMMODE_Pos (12UL) /*!< LPMMODE (Bit 12) */ +#define CACHECTRL_FLASHCFG_LPMMODE_Msk (0x3000UL) /*!< LPMMODE (Bitfield-Mask: 0x03) */ +#define CACHECTRL_FLASHCFG_LPM_RD_WAIT_Pos (8UL) /*!< LPM_RD_WAIT (Bit 8) */ +#define CACHECTRL_FLASHCFG_LPM_RD_WAIT_Msk (0xf00UL) /*!< LPM_RD_WAIT (Bitfield-Mask: 0x0f) */ +#define CACHECTRL_FLASHCFG_SEDELAY_Pos (4UL) /*!< SEDELAY (Bit 4) */ +#define CACHECTRL_FLASHCFG_SEDELAY_Msk (0x70UL) /*!< SEDELAY (Bitfield-Mask: 0x07) */ +#define CACHECTRL_FLASHCFG_RD_WAIT_Pos (0UL) /*!< RD_WAIT (Bit 0) */ +#define CACHECTRL_FLASHCFG_RD_WAIT_Msk (0xfUL) /*!< RD_WAIT (Bitfield-Mask: 0x0f) */ +/* ========================================================= CTRL ========================================================== */ +#define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Pos (10UL) /*!< FLASH1_SLM_ENABLE (Bit 10) */ +#define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk (0x400UL) /*!< FLASH1_SLM_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Pos (9UL) /*!< FLASH1_SLM_DISABLE (Bit 9) */ +#define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk (0x200UL) /*!< FLASH1_SLM_DISABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Pos (8UL) /*!< FLASH1_SLM_STATUS (Bit 8) */ +#define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Msk (0x100UL) /*!< FLASH1_SLM_STATUS (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Pos (6UL) /*!< FLASH0_SLM_ENABLE (Bit 6) */ +#define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk (0x40UL) /*!< FLASH0_SLM_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Pos (5UL) /*!< FLASH0_SLM_DISABLE (Bit 5) */ +#define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk (0x20UL) /*!< FLASH0_SLM_DISABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Pos (4UL) /*!< FLASH0_SLM_STATUS (Bit 4) */ +#define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Msk (0x10UL) /*!< FLASH0_SLM_STATUS (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_CACHE_READY_Pos (2UL) /*!< CACHE_READY (Bit 2) */ +#define CACHECTRL_CTRL_CACHE_READY_Msk (0x4UL) /*!< CACHE_READY (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_RESET_STAT_Pos (1UL) /*!< RESET_STAT (Bit 1) */ +#define CACHECTRL_CTRL_RESET_STAT_Msk (0x2UL) /*!< RESET_STAT (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_INVALIDATE_Pos (0UL) /*!< INVALIDATE (Bit 0) */ +#define CACHECTRL_CTRL_INVALIDATE_Msk (0x1UL) /*!< INVALIDATE (Bitfield-Mask: 0x01) */ +/* ======================================================= NCR0START ======================================================= */ +#define CACHECTRL_NCR0START_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR0START_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== NCR0END ======================================================== */ +#define CACHECTRL_NCR0END_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR0END_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= NCR1START ======================================================= */ +#define CACHECTRL_NCR1START_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR1START_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== NCR1END ======================================================== */ +#define CACHECTRL_NCR1END_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR1END_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= DMON0 ========================================================= */ +#define CACHECTRL_DMON0_DACCESS_COUNT_Pos (0UL) /*!< DACCESS_COUNT (Bit 0) */ +#define CACHECTRL_DMON0_DACCESS_COUNT_Msk (0xffffffffUL) /*!< DACCESS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMON1 ========================================================= */ +#define CACHECTRL_DMON1_DLOOKUP_COUNT_Pos (0UL) /*!< DLOOKUP_COUNT (Bit 0) */ +#define CACHECTRL_DMON1_DLOOKUP_COUNT_Msk (0xffffffffUL) /*!< DLOOKUP_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMON2 ========================================================= */ +#define CACHECTRL_DMON2_DHIT_COUNT_Pos (0UL) /*!< DHIT_COUNT (Bit 0) */ +#define CACHECTRL_DMON2_DHIT_COUNT_Msk (0xffffffffUL) /*!< DHIT_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMON3 ========================================================= */ +#define CACHECTRL_DMON3_DLINE_COUNT_Pos (0UL) /*!< DLINE_COUNT (Bit 0) */ +#define CACHECTRL_DMON3_DLINE_COUNT_Msk (0xffffffffUL) /*!< DLINE_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON0 ========================================================= */ +#define CACHECTRL_IMON0_IACCESS_COUNT_Pos (0UL) /*!< IACCESS_COUNT (Bit 0) */ +#define CACHECTRL_IMON0_IACCESS_COUNT_Msk (0xffffffffUL) /*!< IACCESS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON1 ========================================================= */ +#define CACHECTRL_IMON1_ILOOKUP_COUNT_Pos (0UL) /*!< ILOOKUP_COUNT (Bit 0) */ +#define CACHECTRL_IMON1_ILOOKUP_COUNT_Msk (0xffffffffUL) /*!< ILOOKUP_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON2 ========================================================= */ +#define CACHECTRL_IMON2_IHIT_COUNT_Pos (0UL) /*!< IHIT_COUNT (Bit 0) */ +#define CACHECTRL_IMON2_IHIT_COUNT_Msk (0xffffffffUL) /*!< IHIT_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON3 ========================================================= */ +#define CACHECTRL_IMON3_ILINE_COUNT_Pos (0UL) /*!< ILINE_COUNT (Bit 0) */ +#define CACHECTRL_IMON3_ILINE_COUNT_Msk (0xffffffffUL) /*!< ILINE_COUNT (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ CLKGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CALXT ========================================================= */ +#define CLKGEN_CALXT_CALXT_Pos (0UL) /*!< CALXT (Bit 0) */ +#define CLKGEN_CALXT_CALXT_Msk (0x7ffUL) /*!< CALXT (Bitfield-Mask: 0x7ff) */ +/* ========================================================= CALRC ========================================================= */ +#define CLKGEN_CALRC_CALRC_Pos (0UL) /*!< CALRC (Bit 0) */ +#define CLKGEN_CALRC_CALRC_Msk (0x3ffffUL) /*!< CALRC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== ACALCTR ======================================================== */ +#define CLKGEN_ACALCTR_ACALCTR_Pos (0UL) /*!< ACALCTR (Bit 0) */ +#define CLKGEN_ACALCTR_ACALCTR_Msk (0xffffffUL) /*!< ACALCTR (Bitfield-Mask: 0xffffff) */ +/* ========================================================= OCTRL ========================================================= */ +#define CLKGEN_OCTRL_ACAL_Pos (8UL) /*!< ACAL (Bit 8) */ +#define CLKGEN_OCTRL_ACAL_Msk (0x700UL) /*!< ACAL (Bitfield-Mask: 0x07) */ +#define CLKGEN_OCTRL_OSEL_Pos (7UL) /*!< OSEL (Bit 7) */ +#define CLKGEN_OCTRL_OSEL_Msk (0x80UL) /*!< OSEL (Bitfield-Mask: 0x01) */ +#define CLKGEN_OCTRL_FOS_Pos (6UL) /*!< FOS (Bit 6) */ +#define CLKGEN_OCTRL_FOS_Msk (0x40UL) /*!< FOS (Bitfield-Mask: 0x01) */ +#define CLKGEN_OCTRL_STOPRC_Pos (1UL) /*!< STOPRC (Bit 1) */ +#define CLKGEN_OCTRL_STOPRC_Msk (0x2UL) /*!< STOPRC (Bitfield-Mask: 0x01) */ +#define CLKGEN_OCTRL_STOPXT_Pos (0UL) /*!< STOPXT (Bit 0) */ +#define CLKGEN_OCTRL_STOPXT_Msk (0x1UL) /*!< STOPXT (Bitfield-Mask: 0x01) */ +/* ======================================================== CLKOUT ========================================================= */ +#define CLKGEN_CLKOUT_CKEN_Pos (7UL) /*!< CKEN (Bit 7) */ +#define CLKGEN_CLKOUT_CKEN_Msk (0x80UL) /*!< CKEN (Bitfield-Mask: 0x01) */ +#define CLKGEN_CLKOUT_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ +#define CLKGEN_CLKOUT_CKSEL_Msk (0x3fUL) /*!< CKSEL (Bitfield-Mask: 0x3f) */ +/* ======================================================== CLKKEY ========================================================= */ +#define CLKGEN_CLKKEY_CLKKEY_Pos (0UL) /*!< CLKKEY (Bit 0) */ +#define CLKGEN_CLKKEY_CLKKEY_Msk (0xffffffffUL) /*!< CLKKEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CCTRL ========================================================= */ +#define CLKGEN_CCTRL_CORESEL_Pos (0UL) /*!< CORESEL (Bit 0) */ +#define CLKGEN_CCTRL_CORESEL_Msk (0x1UL) /*!< CORESEL (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ +#define CLKGEN_STATUS_OSCF_Pos (1UL) /*!< OSCF (Bit 1) */ +#define CLKGEN_STATUS_OSCF_Msk (0x2UL) /*!< OSCF (Bitfield-Mask: 0x01) */ +#define CLKGEN_STATUS_OMODE_Pos (0UL) /*!< OMODE (Bit 0) */ +#define CLKGEN_STATUS_OMODE_Msk (0x1UL) /*!< OMODE (Bitfield-Mask: 0x01) */ +/* ========================================================= HFADJ ========================================================= */ +#define CLKGEN_HFADJ_HFADJGAIN_Pos (21UL) /*!< HFADJGAIN (Bit 21) */ +#define CLKGEN_HFADJ_HFADJGAIN_Msk (0xe00000UL) /*!< HFADJGAIN (Bitfield-Mask: 0x07) */ +#define CLKGEN_HFADJ_HFWARMUP_Pos (20UL) /*!< HFWARMUP (Bit 20) */ +#define CLKGEN_HFADJ_HFWARMUP_Msk (0x100000UL) /*!< HFWARMUP (Bitfield-Mask: 0x01) */ +#define CLKGEN_HFADJ_HFXTADJ_Pos (8UL) /*!< HFXTADJ (Bit 8) */ +#define CLKGEN_HFADJ_HFXTADJ_Msk (0xfff00UL) /*!< HFXTADJ (Bitfield-Mask: 0xfff) */ +#define CLKGEN_HFADJ_HFADJCK_Pos (1UL) /*!< HFADJCK (Bit 1) */ +#define CLKGEN_HFADJ_HFADJCK_Msk (0xeUL) /*!< HFADJCK (Bitfield-Mask: 0x07) */ +#define CLKGEN_HFADJ_HFADJEN_Pos (0UL) /*!< HFADJEN (Bit 0) */ +#define CLKGEN_HFADJ_HFADJEN_Msk (0x1UL) /*!< HFADJEN (Bitfield-Mask: 0x01) */ +/* ====================================================== CLOCKENSTAT ====================================================== */ +#define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Pos (0UL) /*!< CLOCKENSTAT (Bit 0) */ +#define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Msk (0xffffffffUL) /*!< CLOCKENSTAT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CLOCKEN2STAT ====================================================== */ +#define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Pos (0UL) /*!< CLOCKEN2STAT (Bit 0) */ +#define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Msk (0xffffffffUL) /*!< CLOCKEN2STAT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CLOCKEN3STAT ====================================================== */ +#define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Pos (0UL) /*!< CLOCKEN3STAT (Bit 0) */ +#define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Msk (0xffffffffUL) /*!< CLOCKEN3STAT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FREQCTRL ======================================================== */ +#define CLKGEN_FREQCTRL_BURSTSTATUS_Pos (2UL) /*!< BURSTSTATUS (Bit 2) */ +#define CLKGEN_FREQCTRL_BURSTSTATUS_Msk (0x4UL) /*!< BURSTSTATUS (Bitfield-Mask: 0x01) */ +#define CLKGEN_FREQCTRL_BURSTACK_Pos (1UL) /*!< BURSTACK (Bit 1) */ +#define CLKGEN_FREQCTRL_BURSTACK_Msk (0x2UL) /*!< BURSTACK (Bitfield-Mask: 0x01) */ +#define CLKGEN_FREQCTRL_BURSTREQ_Pos (0UL) /*!< BURSTREQ (Bit 0) */ +#define CLKGEN_FREQCTRL_BURSTREQ_Msk (0x1UL) /*!< BURSTREQ (Bitfield-Mask: 0x01) */ +/* ===================================================== BLEBUCKTONADJ ===================================================== */ +#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Pos (27UL) /*!< ZEROLENDETECTEN (Bit 27) */ +#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Msk (0x8000000UL) /*!< ZEROLENDETECTEN (Bitfield-Mask: 0x01) */ +#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Pos (23UL) /*!< ZEROLENDETECTTRIM (Bit 23) */ +#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Msk (0x7800000UL) /*!< ZEROLENDETECTTRIM (Bitfield-Mask: 0x0f) */ +#define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Pos (22UL) /*!< TONADJUSTEN (Bit 22) */ +#define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Msk (0x400000UL) /*!< TONADJUSTEN (Bitfield-Mask: 0x01) */ +#define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Pos (20UL) /*!< TONADJUSTPERIOD (Bit 20) */ +#define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Msk (0x300000UL) /*!< TONADJUSTPERIOD (Bitfield-Mask: 0x03) */ +#define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Pos (10UL) /*!< TONHIGHTHRESHOLD (Bit 10) */ +#define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Msk (0xffc00UL) /*!< TONHIGHTHRESHOLD (Bitfield-Mask: 0x3ff) */ +#define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Pos (0UL) /*!< TONLOWTHRESHOLD (Bit 0) */ +#define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Msk (0x3ffUL) /*!< TONLOWTHRESHOLD (Bitfield-Mask: 0x3ff) */ +/* ======================================================= INTRPTEN ======================================================== */ +#define CLKGEN_INTRPTEN_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTRPTEN_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTEN_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTRPTEN_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTEN_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTRPTEN_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ====================================================== INTRPTSTAT ======================================================= */ +#define CLKGEN_INTRPTSTAT_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTRPTSTAT_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTSTAT_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTRPTSTAT_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTSTAT_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTRPTSTAT_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ======================================================= INTRPTCLR ======================================================= */ +#define CLKGEN_INTRPTCLR_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTRPTCLR_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTCLR_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTRPTCLR_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTCLR_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTRPTCLR_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ======================================================= INTRPTSET ======================================================= */ +#define CLKGEN_INTRPTSET_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTRPTSET_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTSET_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTRPTSET_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTSET_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTRPTSET_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CTIMER ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TMR0 ========================================================== */ +#define CTIMER_TMR0_CTTMRB0_Pos (16UL) /*!< CTTMRB0 (Bit 16) */ +#define CTIMER_TMR0_CTTMRB0_Msk (0xffff0000UL) /*!< CTTMRB0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR0_CTTMRA0_Pos (0UL) /*!< CTTMRA0 (Bit 0) */ +#define CTIMER_TMR0_CTTMRA0_Msk (0xffffUL) /*!< CTTMRA0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA0 ========================================================= */ +#define CTIMER_CMPRA0_CMPR1A0_Pos (16UL) /*!< CMPR1A0 (Bit 16) */ +#define CTIMER_CMPRA0_CMPR1A0_Msk (0xffff0000UL) /*!< CMPR1A0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA0_CMPR0A0_Pos (0UL) /*!< CMPR0A0 (Bit 0) */ +#define CTIMER_CMPRA0_CMPR0A0_Msk (0xffffUL) /*!< CMPR0A0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB0 ========================================================= */ +#define CTIMER_CMPRB0_CMPR1B0_Pos (16UL) /*!< CMPR1B0 (Bit 16) */ +#define CTIMER_CMPRB0_CMPR1B0_Msk (0xffff0000UL) /*!< CMPR1B0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB0_CMPR0B0_Pos (0UL) /*!< CMPR0B0 (Bit 0) */ +#define CTIMER_CMPRB0_CMPR0B0_Msk (0xffffUL) /*!< CMPR0B0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL0 ========================================================= */ +#define CTIMER_CTRL0_CTLINK0_Pos (31UL) /*!< CTLINK0 (Bit 31) */ +#define CTIMER_CTRL0_CTLINK0_Msk (0x80000000UL) /*!< CTLINK0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0POL_Pos (28UL) /*!< TMRB0POL (Bit 28) */ +#define CTIMER_CTRL0_TMRB0POL_Msk (0x10000000UL) /*!< TMRB0POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0CLR_Pos (27UL) /*!< TMRB0CLR (Bit 27) */ +#define CTIMER_CTRL0_TMRB0CLR_Msk (0x8000000UL) /*!< TMRB0CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0IE1_Pos (26UL) /*!< TMRB0IE1 (Bit 26) */ +#define CTIMER_CTRL0_TMRB0IE1_Msk (0x4000000UL) /*!< TMRB0IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0IE0_Pos (25UL) /*!< TMRB0IE0 (Bit 25) */ +#define CTIMER_CTRL0_TMRB0IE0_Msk (0x2000000UL) /*!< TMRB0IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0FN_Pos (22UL) /*!< TMRB0FN (Bit 22) */ +#define CTIMER_CTRL0_TMRB0FN_Msk (0x1c00000UL) /*!< TMRB0FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL0_TMRB0CLK_Pos (17UL) /*!< TMRB0CLK (Bit 17) */ +#define CTIMER_CTRL0_TMRB0CLK_Msk (0x3e0000UL) /*!< TMRB0CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL0_TMRB0EN_Pos (16UL) /*!< TMRB0EN (Bit 16) */ +#define CTIMER_CTRL0_TMRB0EN_Msk (0x10000UL) /*!< TMRB0EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0POL_Pos (12UL) /*!< TMRA0POL (Bit 12) */ +#define CTIMER_CTRL0_TMRA0POL_Msk (0x1000UL) /*!< TMRA0POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0CLR_Pos (11UL) /*!< TMRA0CLR (Bit 11) */ +#define CTIMER_CTRL0_TMRA0CLR_Msk (0x800UL) /*!< TMRA0CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0IE1_Pos (10UL) /*!< TMRA0IE1 (Bit 10) */ +#define CTIMER_CTRL0_TMRA0IE1_Msk (0x400UL) /*!< TMRA0IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0IE0_Pos (9UL) /*!< TMRA0IE0 (Bit 9) */ +#define CTIMER_CTRL0_TMRA0IE0_Msk (0x200UL) /*!< TMRA0IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0FN_Pos (6UL) /*!< TMRA0FN (Bit 6) */ +#define CTIMER_CTRL0_TMRA0FN_Msk (0x1c0UL) /*!< TMRA0FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL0_TMRA0CLK_Pos (1UL) /*!< TMRA0CLK (Bit 1) */ +#define CTIMER_CTRL0_TMRA0CLK_Msk (0x3eUL) /*!< TMRA0CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL0_TMRA0EN_Pos (0UL) /*!< TMRA0EN (Bit 0) */ +#define CTIMER_CTRL0_TMRA0EN_Msk (0x1UL) /*!< TMRA0EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA0 ======================================================= */ +#define CTIMER_CMPRAUXA0_CMPR3A0_Pos (16UL) /*!< CMPR3A0 (Bit 16) */ +#define CTIMER_CMPRAUXA0_CMPR3A0_Msk (0xffff0000UL) /*!< CMPR3A0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA0_CMPR2A0_Pos (0UL) /*!< CMPR2A0 (Bit 0) */ +#define CTIMER_CMPRAUXA0_CMPR2A0_Msk (0xffffUL) /*!< CMPR2A0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB0 ======================================================= */ +#define CTIMER_CMPRAUXB0_CMPR3B0_Pos (16UL) /*!< CMPR3B0 (Bit 16) */ +#define CTIMER_CMPRAUXB0_CMPR3B0_Msk (0xffff0000UL) /*!< CMPR3B0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB0_CMPR2B0_Pos (0UL) /*!< CMPR2B0 (Bit 0) */ +#define CTIMER_CMPRAUXB0_CMPR2B0_Msk (0xffffUL) /*!< CMPR2B0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX0 ========================================================== */ +#define CTIMER_AUX0_TMRB0EN23_Pos (30UL) /*!< TMRB0EN23 (Bit 30) */ +#define CTIMER_AUX0_TMRB0EN23_Msk (0x40000000UL) /*!< TMRB0EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRB0POL23_Pos (29UL) /*!< TMRB0POL23 (Bit 29) */ +#define CTIMER_AUX0_TMRB0POL23_Msk (0x20000000UL) /*!< TMRB0POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRB0TINV_Pos (28UL) /*!< TMRB0TINV (Bit 28) */ +#define CTIMER_AUX0_TMRB0TINV_Msk (0x10000000UL) /*!< TMRB0TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRB0NOSYNC_Pos (27UL) /*!< TMRB0NOSYNC (Bit 27) */ +#define CTIMER_AUX0_TMRB0NOSYNC_Msk (0x8000000UL) /*!< TMRB0NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRB0TRIG_Pos (23UL) /*!< TMRB0TRIG (Bit 23) */ +#define CTIMER_AUX0_TMRB0TRIG_Msk (0x7800000UL) /*!< TMRB0TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX0_TMRB0LMT_Pos (16UL) /*!< TMRB0LMT (Bit 16) */ +#define CTIMER_AUX0_TMRB0LMT_Msk (0x3f0000UL) /*!< TMRB0LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX0_TMRA0EN23_Pos (14UL) /*!< TMRA0EN23 (Bit 14) */ +#define CTIMER_AUX0_TMRA0EN23_Msk (0x4000UL) /*!< TMRA0EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRA0POL23_Pos (13UL) /*!< TMRA0POL23 (Bit 13) */ +#define CTIMER_AUX0_TMRA0POL23_Msk (0x2000UL) /*!< TMRA0POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRA0TINV_Pos (12UL) /*!< TMRA0TINV (Bit 12) */ +#define CTIMER_AUX0_TMRA0TINV_Msk (0x1000UL) /*!< TMRA0TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRA0NOSYNC_Pos (11UL) /*!< TMRA0NOSYNC (Bit 11) */ +#define CTIMER_AUX0_TMRA0NOSYNC_Msk (0x800UL) /*!< TMRA0NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRA0TRIG_Pos (7UL) /*!< TMRA0TRIG (Bit 7) */ +#define CTIMER_AUX0_TMRA0TRIG_Msk (0x780UL) /*!< TMRA0TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX0_TMRA0LMT_Pos (0UL) /*!< TMRA0LMT (Bit 0) */ +#define CTIMER_AUX0_TMRA0LMT_Msk (0x7fUL) /*!< TMRA0LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR1 ========================================================== */ +#define CTIMER_TMR1_CTTMRB1_Pos (16UL) /*!< CTTMRB1 (Bit 16) */ +#define CTIMER_TMR1_CTTMRB1_Msk (0xffff0000UL) /*!< CTTMRB1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR1_CTTMRA1_Pos (0UL) /*!< CTTMRA1 (Bit 0) */ +#define CTIMER_TMR1_CTTMRA1_Msk (0xffffUL) /*!< CTTMRA1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA1 ========================================================= */ +#define CTIMER_CMPRA1_CMPR1A1_Pos (16UL) /*!< CMPR1A1 (Bit 16) */ +#define CTIMER_CMPRA1_CMPR1A1_Msk (0xffff0000UL) /*!< CMPR1A1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA1_CMPR0A1_Pos (0UL) /*!< CMPR0A1 (Bit 0) */ +#define CTIMER_CMPRA1_CMPR0A1_Msk (0xffffUL) /*!< CMPR0A1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB1 ========================================================= */ +#define CTIMER_CMPRB1_CMPR1B1_Pos (16UL) /*!< CMPR1B1 (Bit 16) */ +#define CTIMER_CMPRB1_CMPR1B1_Msk (0xffff0000UL) /*!< CMPR1B1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB1_CMPR0B1_Pos (0UL) /*!< CMPR0B1 (Bit 0) */ +#define CTIMER_CMPRB1_CMPR0B1_Msk (0xffffUL) /*!< CMPR0B1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL1 ========================================================= */ +#define CTIMER_CTRL1_CTLINK1_Pos (31UL) /*!< CTLINK1 (Bit 31) */ +#define CTIMER_CTRL1_CTLINK1_Msk (0x80000000UL) /*!< CTLINK1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1POL_Pos (28UL) /*!< TMRB1POL (Bit 28) */ +#define CTIMER_CTRL1_TMRB1POL_Msk (0x10000000UL) /*!< TMRB1POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1CLR_Pos (27UL) /*!< TMRB1CLR (Bit 27) */ +#define CTIMER_CTRL1_TMRB1CLR_Msk (0x8000000UL) /*!< TMRB1CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1IE1_Pos (26UL) /*!< TMRB1IE1 (Bit 26) */ +#define CTIMER_CTRL1_TMRB1IE1_Msk (0x4000000UL) /*!< TMRB1IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1IE0_Pos (25UL) /*!< TMRB1IE0 (Bit 25) */ +#define CTIMER_CTRL1_TMRB1IE0_Msk (0x2000000UL) /*!< TMRB1IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1FN_Pos (22UL) /*!< TMRB1FN (Bit 22) */ +#define CTIMER_CTRL1_TMRB1FN_Msk (0x1c00000UL) /*!< TMRB1FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL1_TMRB1CLK_Pos (17UL) /*!< TMRB1CLK (Bit 17) */ +#define CTIMER_CTRL1_TMRB1CLK_Msk (0x3e0000UL) /*!< TMRB1CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL1_TMRB1EN_Pos (16UL) /*!< TMRB1EN (Bit 16) */ +#define CTIMER_CTRL1_TMRB1EN_Msk (0x10000UL) /*!< TMRB1EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1POL_Pos (12UL) /*!< TMRA1POL (Bit 12) */ +#define CTIMER_CTRL1_TMRA1POL_Msk (0x1000UL) /*!< TMRA1POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1CLR_Pos (11UL) /*!< TMRA1CLR (Bit 11) */ +#define CTIMER_CTRL1_TMRA1CLR_Msk (0x800UL) /*!< TMRA1CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1IE1_Pos (10UL) /*!< TMRA1IE1 (Bit 10) */ +#define CTIMER_CTRL1_TMRA1IE1_Msk (0x400UL) /*!< TMRA1IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1IE0_Pos (9UL) /*!< TMRA1IE0 (Bit 9) */ +#define CTIMER_CTRL1_TMRA1IE0_Msk (0x200UL) /*!< TMRA1IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1FN_Pos (6UL) /*!< TMRA1FN (Bit 6) */ +#define CTIMER_CTRL1_TMRA1FN_Msk (0x1c0UL) /*!< TMRA1FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL1_TMRA1CLK_Pos (1UL) /*!< TMRA1CLK (Bit 1) */ +#define CTIMER_CTRL1_TMRA1CLK_Msk (0x3eUL) /*!< TMRA1CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL1_TMRA1EN_Pos (0UL) /*!< TMRA1EN (Bit 0) */ +#define CTIMER_CTRL1_TMRA1EN_Msk (0x1UL) /*!< TMRA1EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA1 ======================================================= */ +#define CTIMER_CMPRAUXA1_CMPR3A1_Pos (16UL) /*!< CMPR3A1 (Bit 16) */ +#define CTIMER_CMPRAUXA1_CMPR3A1_Msk (0xffff0000UL) /*!< CMPR3A1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA1_CMPR2A1_Pos (0UL) /*!< CMPR2A1 (Bit 0) */ +#define CTIMER_CMPRAUXA1_CMPR2A1_Msk (0xffffUL) /*!< CMPR2A1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB1 ======================================================= */ +#define CTIMER_CMPRAUXB1_CMPR3B1_Pos (16UL) /*!< CMPR3B1 (Bit 16) */ +#define CTIMER_CMPRAUXB1_CMPR3B1_Msk (0xffff0000UL) /*!< CMPR3B1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB1_CMPR2B1_Pos (0UL) /*!< CMPR2B1 (Bit 0) */ +#define CTIMER_CMPRAUXB1_CMPR2B1_Msk (0xffffUL) /*!< CMPR2B1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX1 ========================================================== */ +#define CTIMER_AUX1_TMRB1EN23_Pos (30UL) /*!< TMRB1EN23 (Bit 30) */ +#define CTIMER_AUX1_TMRB1EN23_Msk (0x40000000UL) /*!< TMRB1EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRB1POL23_Pos (29UL) /*!< TMRB1POL23 (Bit 29) */ +#define CTIMER_AUX1_TMRB1POL23_Msk (0x20000000UL) /*!< TMRB1POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRB1TINV_Pos (28UL) /*!< TMRB1TINV (Bit 28) */ +#define CTIMER_AUX1_TMRB1TINV_Msk (0x10000000UL) /*!< TMRB1TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRB1NOSYNC_Pos (27UL) /*!< TMRB1NOSYNC (Bit 27) */ +#define CTIMER_AUX1_TMRB1NOSYNC_Msk (0x8000000UL) /*!< TMRB1NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRB1TRIG_Pos (23UL) /*!< TMRB1TRIG (Bit 23) */ +#define CTIMER_AUX1_TMRB1TRIG_Msk (0x7800000UL) /*!< TMRB1TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX1_TMRB1LMT_Pos (16UL) /*!< TMRB1LMT (Bit 16) */ +#define CTIMER_AUX1_TMRB1LMT_Msk (0x3f0000UL) /*!< TMRB1LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX1_TMRA1EN23_Pos (14UL) /*!< TMRA1EN23 (Bit 14) */ +#define CTIMER_AUX1_TMRA1EN23_Msk (0x4000UL) /*!< TMRA1EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRA1POL23_Pos (13UL) /*!< TMRA1POL23 (Bit 13) */ +#define CTIMER_AUX1_TMRA1POL23_Msk (0x2000UL) /*!< TMRA1POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRA1TINV_Pos (12UL) /*!< TMRA1TINV (Bit 12) */ +#define CTIMER_AUX1_TMRA1TINV_Msk (0x1000UL) /*!< TMRA1TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRA1NOSYNC_Pos (11UL) /*!< TMRA1NOSYNC (Bit 11) */ +#define CTIMER_AUX1_TMRA1NOSYNC_Msk (0x800UL) /*!< TMRA1NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRA1TRIG_Pos (7UL) /*!< TMRA1TRIG (Bit 7) */ +#define CTIMER_AUX1_TMRA1TRIG_Msk (0x780UL) /*!< TMRA1TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX1_TMRA1LMT_Pos (0UL) /*!< TMRA1LMT (Bit 0) */ +#define CTIMER_AUX1_TMRA1LMT_Msk (0x7fUL) /*!< TMRA1LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR2 ========================================================== */ +#define CTIMER_TMR2_CTTMRB2_Pos (16UL) /*!< CTTMRB2 (Bit 16) */ +#define CTIMER_TMR2_CTTMRB2_Msk (0xffff0000UL) /*!< CTTMRB2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR2_CTTMRA2_Pos (0UL) /*!< CTTMRA2 (Bit 0) */ +#define CTIMER_TMR2_CTTMRA2_Msk (0xffffUL) /*!< CTTMRA2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA2 ========================================================= */ +#define CTIMER_CMPRA2_CMPR1A2_Pos (16UL) /*!< CMPR1A2 (Bit 16) */ +#define CTIMER_CMPRA2_CMPR1A2_Msk (0xffff0000UL) /*!< CMPR1A2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA2_CMPR0A2_Pos (0UL) /*!< CMPR0A2 (Bit 0) */ +#define CTIMER_CMPRA2_CMPR0A2_Msk (0xffffUL) /*!< CMPR0A2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB2 ========================================================= */ +#define CTIMER_CMPRB2_CMPR1B2_Pos (16UL) /*!< CMPR1B2 (Bit 16) */ +#define CTIMER_CMPRB2_CMPR1B2_Msk (0xffff0000UL) /*!< CMPR1B2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB2_CMPR0B2_Pos (0UL) /*!< CMPR0B2 (Bit 0) */ +#define CTIMER_CMPRB2_CMPR0B2_Msk (0xffffUL) /*!< CMPR0B2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL2 ========================================================= */ +#define CTIMER_CTRL2_CTLINK2_Pos (31UL) /*!< CTLINK2 (Bit 31) */ +#define CTIMER_CTRL2_CTLINK2_Msk (0x80000000UL) /*!< CTLINK2 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2POL_Pos (28UL) /*!< TMRB2POL (Bit 28) */ +#define CTIMER_CTRL2_TMRB2POL_Msk (0x10000000UL) /*!< TMRB2POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2CLR_Pos (27UL) /*!< TMRB2CLR (Bit 27) */ +#define CTIMER_CTRL2_TMRB2CLR_Msk (0x8000000UL) /*!< TMRB2CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2IE1_Pos (26UL) /*!< TMRB2IE1 (Bit 26) */ +#define CTIMER_CTRL2_TMRB2IE1_Msk (0x4000000UL) /*!< TMRB2IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2IE0_Pos (25UL) /*!< TMRB2IE0 (Bit 25) */ +#define CTIMER_CTRL2_TMRB2IE0_Msk (0x2000000UL) /*!< TMRB2IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2FN_Pos (22UL) /*!< TMRB2FN (Bit 22) */ +#define CTIMER_CTRL2_TMRB2FN_Msk (0x1c00000UL) /*!< TMRB2FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL2_TMRB2CLK_Pos (17UL) /*!< TMRB2CLK (Bit 17) */ +#define CTIMER_CTRL2_TMRB2CLK_Msk (0x3e0000UL) /*!< TMRB2CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL2_TMRB2EN_Pos (16UL) /*!< TMRB2EN (Bit 16) */ +#define CTIMER_CTRL2_TMRB2EN_Msk (0x10000UL) /*!< TMRB2EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2POL_Pos (12UL) /*!< TMRA2POL (Bit 12) */ +#define CTIMER_CTRL2_TMRA2POL_Msk (0x1000UL) /*!< TMRA2POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2CLR_Pos (11UL) /*!< TMRA2CLR (Bit 11) */ +#define CTIMER_CTRL2_TMRA2CLR_Msk (0x800UL) /*!< TMRA2CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2IE1_Pos (10UL) /*!< TMRA2IE1 (Bit 10) */ +#define CTIMER_CTRL2_TMRA2IE1_Msk (0x400UL) /*!< TMRA2IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2IE0_Pos (9UL) /*!< TMRA2IE0 (Bit 9) */ +#define CTIMER_CTRL2_TMRA2IE0_Msk (0x200UL) /*!< TMRA2IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2FN_Pos (6UL) /*!< TMRA2FN (Bit 6) */ +#define CTIMER_CTRL2_TMRA2FN_Msk (0x1c0UL) /*!< TMRA2FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL2_TMRA2CLK_Pos (1UL) /*!< TMRA2CLK (Bit 1) */ +#define CTIMER_CTRL2_TMRA2CLK_Msk (0x3eUL) /*!< TMRA2CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL2_TMRA2EN_Pos (0UL) /*!< TMRA2EN (Bit 0) */ +#define CTIMER_CTRL2_TMRA2EN_Msk (0x1UL) /*!< TMRA2EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA2 ======================================================= */ +#define CTIMER_CMPRAUXA2_CMPR3A2_Pos (16UL) /*!< CMPR3A2 (Bit 16) */ +#define CTIMER_CMPRAUXA2_CMPR3A2_Msk (0xffff0000UL) /*!< CMPR3A2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA2_CMPR2A2_Pos (0UL) /*!< CMPR2A2 (Bit 0) */ +#define CTIMER_CMPRAUXA2_CMPR2A2_Msk (0xffffUL) /*!< CMPR2A2 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB2 ======================================================= */ +#define CTIMER_CMPRAUXB2_CMPR3B2_Pos (16UL) /*!< CMPR3B2 (Bit 16) */ +#define CTIMER_CMPRAUXB2_CMPR3B2_Msk (0xffff0000UL) /*!< CMPR3B2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB2_CMPR2B2_Pos (0UL) /*!< CMPR2B2 (Bit 0) */ +#define CTIMER_CMPRAUXB2_CMPR2B2_Msk (0xffffUL) /*!< CMPR2B2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX2 ========================================================== */ +#define CTIMER_AUX2_TMRB2EN23_Pos (30UL) /*!< TMRB2EN23 (Bit 30) */ +#define CTIMER_AUX2_TMRB2EN23_Msk (0x40000000UL) /*!< TMRB2EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRB2POL23_Pos (29UL) /*!< TMRB2POL23 (Bit 29) */ +#define CTIMER_AUX2_TMRB2POL23_Msk (0x20000000UL) /*!< TMRB2POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRB2TINV_Pos (28UL) /*!< TMRB2TINV (Bit 28) */ +#define CTIMER_AUX2_TMRB2TINV_Msk (0x10000000UL) /*!< TMRB2TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRB2NOSYNC_Pos (27UL) /*!< TMRB2NOSYNC (Bit 27) */ +#define CTIMER_AUX2_TMRB2NOSYNC_Msk (0x8000000UL) /*!< TMRB2NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRB2TRIG_Pos (23UL) /*!< TMRB2TRIG (Bit 23) */ +#define CTIMER_AUX2_TMRB2TRIG_Msk (0x7800000UL) /*!< TMRB2TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX2_TMRB2LMT_Pos (16UL) /*!< TMRB2LMT (Bit 16) */ +#define CTIMER_AUX2_TMRB2LMT_Msk (0x3f0000UL) /*!< TMRB2LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX2_TMRA2EN23_Pos (14UL) /*!< TMRA2EN23 (Bit 14) */ +#define CTIMER_AUX2_TMRA2EN23_Msk (0x4000UL) /*!< TMRA2EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRA2POL23_Pos (13UL) /*!< TMRA2POL23 (Bit 13) */ +#define CTIMER_AUX2_TMRA2POL23_Msk (0x2000UL) /*!< TMRA2POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRA2TINV_Pos (12UL) /*!< TMRA2TINV (Bit 12) */ +#define CTIMER_AUX2_TMRA2TINV_Msk (0x1000UL) /*!< TMRA2TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRA2NOSYNC_Pos (11UL) /*!< TMRA2NOSYNC (Bit 11) */ +#define CTIMER_AUX2_TMRA2NOSYNC_Msk (0x800UL) /*!< TMRA2NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRA2TRIG_Pos (7UL) /*!< TMRA2TRIG (Bit 7) */ +#define CTIMER_AUX2_TMRA2TRIG_Msk (0x780UL) /*!< TMRA2TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX2_TMRA2LMT_Pos (0UL) /*!< TMRA2LMT (Bit 0) */ +#define CTIMER_AUX2_TMRA2LMT_Msk (0x7fUL) /*!< TMRA2LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR3 ========================================================== */ +#define CTIMER_TMR3_CTTMRB3_Pos (16UL) /*!< CTTMRB3 (Bit 16) */ +#define CTIMER_TMR3_CTTMRB3_Msk (0xffff0000UL) /*!< CTTMRB3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR3_CTTMRA3_Pos (0UL) /*!< CTTMRA3 (Bit 0) */ +#define CTIMER_TMR3_CTTMRA3_Msk (0xffffUL) /*!< CTTMRA3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA3 ========================================================= */ +#define CTIMER_CMPRA3_CMPR1A3_Pos (16UL) /*!< CMPR1A3 (Bit 16) */ +#define CTIMER_CMPRA3_CMPR1A3_Msk (0xffff0000UL) /*!< CMPR1A3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA3_CMPR0A3_Pos (0UL) /*!< CMPR0A3 (Bit 0) */ +#define CTIMER_CMPRA3_CMPR0A3_Msk (0xffffUL) /*!< CMPR0A3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB3 ========================================================= */ +#define CTIMER_CMPRB3_CMPR1B3_Pos (16UL) /*!< CMPR1B3 (Bit 16) */ +#define CTIMER_CMPRB3_CMPR1B3_Msk (0xffff0000UL) /*!< CMPR1B3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB3_CMPR0B3_Pos (0UL) /*!< CMPR0B3 (Bit 0) */ +#define CTIMER_CMPRB3_CMPR0B3_Msk (0xffffUL) /*!< CMPR0B3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL3 ========================================================= */ +#define CTIMER_CTRL3_CTLINK3_Pos (31UL) /*!< CTLINK3 (Bit 31) */ +#define CTIMER_CTRL3_CTLINK3_Msk (0x80000000UL) /*!< CTLINK3 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3POL_Pos (28UL) /*!< TMRB3POL (Bit 28) */ +#define CTIMER_CTRL3_TMRB3POL_Msk (0x10000000UL) /*!< TMRB3POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3CLR_Pos (27UL) /*!< TMRB3CLR (Bit 27) */ +#define CTIMER_CTRL3_TMRB3CLR_Msk (0x8000000UL) /*!< TMRB3CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3IE1_Pos (26UL) /*!< TMRB3IE1 (Bit 26) */ +#define CTIMER_CTRL3_TMRB3IE1_Msk (0x4000000UL) /*!< TMRB3IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3IE0_Pos (25UL) /*!< TMRB3IE0 (Bit 25) */ +#define CTIMER_CTRL3_TMRB3IE0_Msk (0x2000000UL) /*!< TMRB3IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3FN_Pos (22UL) /*!< TMRB3FN (Bit 22) */ +#define CTIMER_CTRL3_TMRB3FN_Msk (0x1c00000UL) /*!< TMRB3FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL3_TMRB3CLK_Pos (17UL) /*!< TMRB3CLK (Bit 17) */ +#define CTIMER_CTRL3_TMRB3CLK_Msk (0x3e0000UL) /*!< TMRB3CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL3_TMRB3EN_Pos (16UL) /*!< TMRB3EN (Bit 16) */ +#define CTIMER_CTRL3_TMRB3EN_Msk (0x10000UL) /*!< TMRB3EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_ADCEN_Pos (15UL) /*!< ADCEN (Bit 15) */ +#define CTIMER_CTRL3_ADCEN_Msk (0x8000UL) /*!< ADCEN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3POL_Pos (12UL) /*!< TMRA3POL (Bit 12) */ +#define CTIMER_CTRL3_TMRA3POL_Msk (0x1000UL) /*!< TMRA3POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3CLR_Pos (11UL) /*!< TMRA3CLR (Bit 11) */ +#define CTIMER_CTRL3_TMRA3CLR_Msk (0x800UL) /*!< TMRA3CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3IE1_Pos (10UL) /*!< TMRA3IE1 (Bit 10) */ +#define CTIMER_CTRL3_TMRA3IE1_Msk (0x400UL) /*!< TMRA3IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3IE0_Pos (9UL) /*!< TMRA3IE0 (Bit 9) */ +#define CTIMER_CTRL3_TMRA3IE0_Msk (0x200UL) /*!< TMRA3IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3FN_Pos (6UL) /*!< TMRA3FN (Bit 6) */ +#define CTIMER_CTRL3_TMRA3FN_Msk (0x1c0UL) /*!< TMRA3FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL3_TMRA3CLK_Pos (1UL) /*!< TMRA3CLK (Bit 1) */ +#define CTIMER_CTRL3_TMRA3CLK_Msk (0x3eUL) /*!< TMRA3CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL3_TMRA3EN_Pos (0UL) /*!< TMRA3EN (Bit 0) */ +#define CTIMER_CTRL3_TMRA3EN_Msk (0x1UL) /*!< TMRA3EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA3 ======================================================= */ +#define CTIMER_CMPRAUXA3_CMPR3A3_Pos (16UL) /*!< CMPR3A3 (Bit 16) */ +#define CTIMER_CMPRAUXA3_CMPR3A3_Msk (0xffff0000UL) /*!< CMPR3A3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA3_CMPR2A3_Pos (0UL) /*!< CMPR2A3 (Bit 0) */ +#define CTIMER_CMPRAUXA3_CMPR2A3_Msk (0xffffUL) /*!< CMPR2A3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB3 ======================================================= */ +#define CTIMER_CMPRAUXB3_CMPR3B3_Pos (16UL) /*!< CMPR3B3 (Bit 16) */ +#define CTIMER_CMPRAUXB3_CMPR3B3_Msk (0xffff0000UL) /*!< CMPR3B3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB3_CMPR2B3_Pos (0UL) /*!< CMPR2B3 (Bit 0) */ +#define CTIMER_CMPRAUXB3_CMPR2B3_Msk (0xffffUL) /*!< CMPR2B3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX3 ========================================================== */ +#define CTIMER_AUX3_TMRB3EN23_Pos (30UL) /*!< TMRB3EN23 (Bit 30) */ +#define CTIMER_AUX3_TMRB3EN23_Msk (0x40000000UL) /*!< TMRB3EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRB3POL23_Pos (29UL) /*!< TMRB3POL23 (Bit 29) */ +#define CTIMER_AUX3_TMRB3POL23_Msk (0x20000000UL) /*!< TMRB3POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRB3TINV_Pos (28UL) /*!< TMRB3TINV (Bit 28) */ +#define CTIMER_AUX3_TMRB3TINV_Msk (0x10000000UL) /*!< TMRB3TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRB3NOSYNC_Pos (27UL) /*!< TMRB3NOSYNC (Bit 27) */ +#define CTIMER_AUX3_TMRB3NOSYNC_Msk (0x8000000UL) /*!< TMRB3NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRB3TRIG_Pos (23UL) /*!< TMRB3TRIG (Bit 23) */ +#define CTIMER_AUX3_TMRB3TRIG_Msk (0x7800000UL) /*!< TMRB3TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX3_TMRB3LMT_Pos (16UL) /*!< TMRB3LMT (Bit 16) */ +#define CTIMER_AUX3_TMRB3LMT_Msk (0x3f0000UL) /*!< TMRB3LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX3_TMRA3EN23_Pos (14UL) /*!< TMRA3EN23 (Bit 14) */ +#define CTIMER_AUX3_TMRA3EN23_Msk (0x4000UL) /*!< TMRA3EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRA3POL23_Pos (13UL) /*!< TMRA3POL23 (Bit 13) */ +#define CTIMER_AUX3_TMRA3POL23_Msk (0x2000UL) /*!< TMRA3POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRA3TINV_Pos (12UL) /*!< TMRA3TINV (Bit 12) */ +#define CTIMER_AUX3_TMRA3TINV_Msk (0x1000UL) /*!< TMRA3TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRA3NOSYNC_Pos (11UL) /*!< TMRA3NOSYNC (Bit 11) */ +#define CTIMER_AUX3_TMRA3NOSYNC_Msk (0x800UL) /*!< TMRA3NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRA3TRIG_Pos (7UL) /*!< TMRA3TRIG (Bit 7) */ +#define CTIMER_AUX3_TMRA3TRIG_Msk (0x780UL) /*!< TMRA3TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX3_TMRA3LMT_Pos (0UL) /*!< TMRA3LMT (Bit 0) */ +#define CTIMER_AUX3_TMRA3LMT_Msk (0x7fUL) /*!< TMRA3LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR4 ========================================================== */ +#define CTIMER_TMR4_CTTMRB4_Pos (16UL) /*!< CTTMRB4 (Bit 16) */ +#define CTIMER_TMR4_CTTMRB4_Msk (0xffff0000UL) /*!< CTTMRB4 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR4_CTTMRA4_Pos (0UL) /*!< CTTMRA4 (Bit 0) */ +#define CTIMER_TMR4_CTTMRA4_Msk (0xffffUL) /*!< CTTMRA4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA4 ========================================================= */ +#define CTIMER_CMPRA4_CMPR1A4_Pos (16UL) /*!< CMPR1A4 (Bit 16) */ +#define CTIMER_CMPRA4_CMPR1A4_Msk (0xffff0000UL) /*!< CMPR1A4 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA4_CMPR0A4_Pos (0UL) /*!< CMPR0A4 (Bit 0) */ +#define CTIMER_CMPRA4_CMPR0A4_Msk (0xffffUL) /*!< CMPR0A4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB4 ========================================================= */ +#define CTIMER_CMPRB4_CMPR1B4_Pos (16UL) /*!< CMPR1B4 (Bit 16) */ +#define CTIMER_CMPRB4_CMPR1B4_Msk (0xffff0000UL) /*!< CMPR1B4 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB4_CMPR0B4_Pos (0UL) /*!< CMPR0B4 (Bit 0) */ +#define CTIMER_CMPRB4_CMPR0B4_Msk (0xffffUL) /*!< CMPR0B4 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL4 ========================================================= */ +#define CTIMER_CTRL4_CTLINK4_Pos (31UL) /*!< CTLINK4 (Bit 31) */ +#define CTIMER_CTRL4_CTLINK4_Msk (0x80000000UL) /*!< CTLINK4 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRB4POL_Pos (28UL) /*!< TMRB4POL (Bit 28) */ +#define CTIMER_CTRL4_TMRB4POL_Msk (0x10000000UL) /*!< TMRB4POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRB4CLR_Pos (27UL) /*!< TMRB4CLR (Bit 27) */ +#define CTIMER_CTRL4_TMRB4CLR_Msk (0x8000000UL) /*!< TMRB4CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRB4IE1_Pos (26UL) /*!< TMRB4IE1 (Bit 26) */ +#define CTIMER_CTRL4_TMRB4IE1_Msk (0x4000000UL) /*!< TMRB4IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRB4IE0_Pos (25UL) /*!< TMRB4IE0 (Bit 25) */ +#define CTIMER_CTRL4_TMRB4IE0_Msk (0x2000000UL) /*!< TMRB4IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRB4FN_Pos (22UL) /*!< TMRB4FN (Bit 22) */ +#define CTIMER_CTRL4_TMRB4FN_Msk (0x1c00000UL) /*!< TMRB4FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL4_TMRB4CLK_Pos (17UL) /*!< TMRB4CLK (Bit 17) */ +#define CTIMER_CTRL4_TMRB4CLK_Msk (0x3e0000UL) /*!< TMRB4CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL4_TMRB4EN_Pos (16UL) /*!< TMRB4EN (Bit 16) */ +#define CTIMER_CTRL4_TMRB4EN_Msk (0x10000UL) /*!< TMRB4EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRA4POL_Pos (12UL) /*!< TMRA4POL (Bit 12) */ +#define CTIMER_CTRL4_TMRA4POL_Msk (0x1000UL) /*!< TMRA4POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRA4CLR_Pos (11UL) /*!< TMRA4CLR (Bit 11) */ +#define CTIMER_CTRL4_TMRA4CLR_Msk (0x800UL) /*!< TMRA4CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRA4IE1_Pos (10UL) /*!< TMRA4IE1 (Bit 10) */ +#define CTIMER_CTRL4_TMRA4IE1_Msk (0x400UL) /*!< TMRA4IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRA4IE0_Pos (9UL) /*!< TMRA4IE0 (Bit 9) */ +#define CTIMER_CTRL4_TMRA4IE0_Msk (0x200UL) /*!< TMRA4IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRA4FN_Pos (6UL) /*!< TMRA4FN (Bit 6) */ +#define CTIMER_CTRL4_TMRA4FN_Msk (0x1c0UL) /*!< TMRA4FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL4_TMRA4CLK_Pos (1UL) /*!< TMRA4CLK (Bit 1) */ +#define CTIMER_CTRL4_TMRA4CLK_Msk (0x3eUL) /*!< TMRA4CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL4_TMRA4EN_Pos (0UL) /*!< TMRA4EN (Bit 0) */ +#define CTIMER_CTRL4_TMRA4EN_Msk (0x1UL) /*!< TMRA4EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA4 ======================================================= */ +#define CTIMER_CMPRAUXA4_CMPR3A4_Pos (16UL) /*!< CMPR3A4 (Bit 16) */ +#define CTIMER_CMPRAUXA4_CMPR3A4_Msk (0xffff0000UL) /*!< CMPR3A4 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA4_CMPR2A4_Pos (0UL) /*!< CMPR2A4 (Bit 0) */ +#define CTIMER_CMPRAUXA4_CMPR2A4_Msk (0xffffUL) /*!< CMPR2A4 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB4 ======================================================= */ +#define CTIMER_CMPRAUXB4_CMPR3B4_Pos (16UL) /*!< CMPR3B4 (Bit 16) */ +#define CTIMER_CMPRAUXB4_CMPR3B4_Msk (0xffff0000UL) /*!< CMPR3B4 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB4_CMPR2B4_Pos (0UL) /*!< CMPR2B4 (Bit 0) */ +#define CTIMER_CMPRAUXB4_CMPR2B4_Msk (0xffffUL) /*!< CMPR2B4 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX4 ========================================================== */ +#define CTIMER_AUX4_TMRB4EN23_Pos (30UL) /*!< TMRB4EN23 (Bit 30) */ +#define CTIMER_AUX4_TMRB4EN23_Msk (0x40000000UL) /*!< TMRB4EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRB4POL23_Pos (29UL) /*!< TMRB4POL23 (Bit 29) */ +#define CTIMER_AUX4_TMRB4POL23_Msk (0x20000000UL) /*!< TMRB4POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRB4TINV_Pos (28UL) /*!< TMRB4TINV (Bit 28) */ +#define CTIMER_AUX4_TMRB4TINV_Msk (0x10000000UL) /*!< TMRB4TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRB4NOSYNC_Pos (27UL) /*!< TMRB4NOSYNC (Bit 27) */ +#define CTIMER_AUX4_TMRB4NOSYNC_Msk (0x8000000UL) /*!< TMRB4NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRB4TRIG_Pos (23UL) /*!< TMRB4TRIG (Bit 23) */ +#define CTIMER_AUX4_TMRB4TRIG_Msk (0x7800000UL) /*!< TMRB4TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX4_TMRB4LMT_Pos (16UL) /*!< TMRB4LMT (Bit 16) */ +#define CTIMER_AUX4_TMRB4LMT_Msk (0x3f0000UL) /*!< TMRB4LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX4_TMRA4EN23_Pos (14UL) /*!< TMRA4EN23 (Bit 14) */ +#define CTIMER_AUX4_TMRA4EN23_Msk (0x4000UL) /*!< TMRA4EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRA4POL23_Pos (13UL) /*!< TMRA4POL23 (Bit 13) */ +#define CTIMER_AUX4_TMRA4POL23_Msk (0x2000UL) /*!< TMRA4POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRA4TINV_Pos (12UL) /*!< TMRA4TINV (Bit 12) */ +#define CTIMER_AUX4_TMRA4TINV_Msk (0x1000UL) /*!< TMRA4TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRA4NOSYNC_Pos (11UL) /*!< TMRA4NOSYNC (Bit 11) */ +#define CTIMER_AUX4_TMRA4NOSYNC_Msk (0x800UL) /*!< TMRA4NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRA4TRIG_Pos (7UL) /*!< TMRA4TRIG (Bit 7) */ +#define CTIMER_AUX4_TMRA4TRIG_Msk (0x780UL) /*!< TMRA4TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX4_TMRA4LMT_Pos (0UL) /*!< TMRA4LMT (Bit 0) */ +#define CTIMER_AUX4_TMRA4LMT_Msk (0x7fUL) /*!< TMRA4LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR5 ========================================================== */ +#define CTIMER_TMR5_CTTMRB5_Pos (16UL) /*!< CTTMRB5 (Bit 16) */ +#define CTIMER_TMR5_CTTMRB5_Msk (0xffff0000UL) /*!< CTTMRB5 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR5_CTTMRA5_Pos (0UL) /*!< CTTMRA5 (Bit 0) */ +#define CTIMER_TMR5_CTTMRA5_Msk (0xffffUL) /*!< CTTMRA5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA5 ========================================================= */ +#define CTIMER_CMPRA5_CMPR1A5_Pos (16UL) /*!< CMPR1A5 (Bit 16) */ +#define CTIMER_CMPRA5_CMPR1A5_Msk (0xffff0000UL) /*!< CMPR1A5 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA5_CMPR0A5_Pos (0UL) /*!< CMPR0A5 (Bit 0) */ +#define CTIMER_CMPRA5_CMPR0A5_Msk (0xffffUL) /*!< CMPR0A5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB5 ========================================================= */ +#define CTIMER_CMPRB5_CMPR1B5_Pos (16UL) /*!< CMPR1B5 (Bit 16) */ +#define CTIMER_CMPRB5_CMPR1B5_Msk (0xffff0000UL) /*!< CMPR1B5 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB5_CMPR0B5_Pos (0UL) /*!< CMPR0B5 (Bit 0) */ +#define CTIMER_CMPRB5_CMPR0B5_Msk (0xffffUL) /*!< CMPR0B5 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL5 ========================================================= */ +#define CTIMER_CTRL5_CTLINK5_Pos (31UL) /*!< CTLINK5 (Bit 31) */ +#define CTIMER_CTRL5_CTLINK5_Msk (0x80000000UL) /*!< CTLINK5 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRB5POL_Pos (28UL) /*!< TMRB5POL (Bit 28) */ +#define CTIMER_CTRL5_TMRB5POL_Msk (0x10000000UL) /*!< TMRB5POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRB5CLR_Pos (27UL) /*!< TMRB5CLR (Bit 27) */ +#define CTIMER_CTRL5_TMRB5CLR_Msk (0x8000000UL) /*!< TMRB5CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRB5IE1_Pos (26UL) /*!< TMRB5IE1 (Bit 26) */ +#define CTIMER_CTRL5_TMRB5IE1_Msk (0x4000000UL) /*!< TMRB5IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRB5IE0_Pos (25UL) /*!< TMRB5IE0 (Bit 25) */ +#define CTIMER_CTRL5_TMRB5IE0_Msk (0x2000000UL) /*!< TMRB5IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRB5FN_Pos (22UL) /*!< TMRB5FN (Bit 22) */ +#define CTIMER_CTRL5_TMRB5FN_Msk (0x1c00000UL) /*!< TMRB5FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL5_TMRB5CLK_Pos (17UL) /*!< TMRB5CLK (Bit 17) */ +#define CTIMER_CTRL5_TMRB5CLK_Msk (0x3e0000UL) /*!< TMRB5CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL5_TMRB5EN_Pos (16UL) /*!< TMRB5EN (Bit 16) */ +#define CTIMER_CTRL5_TMRB5EN_Msk (0x10000UL) /*!< TMRB5EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRA5POL_Pos (12UL) /*!< TMRA5POL (Bit 12) */ +#define CTIMER_CTRL5_TMRA5POL_Msk (0x1000UL) /*!< TMRA5POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRA5CLR_Pos (11UL) /*!< TMRA5CLR (Bit 11) */ +#define CTIMER_CTRL5_TMRA5CLR_Msk (0x800UL) /*!< TMRA5CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRA5IE1_Pos (10UL) /*!< TMRA5IE1 (Bit 10) */ +#define CTIMER_CTRL5_TMRA5IE1_Msk (0x400UL) /*!< TMRA5IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRA5IE0_Pos (9UL) /*!< TMRA5IE0 (Bit 9) */ +#define CTIMER_CTRL5_TMRA5IE0_Msk (0x200UL) /*!< TMRA5IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRA5FN_Pos (6UL) /*!< TMRA5FN (Bit 6) */ +#define CTIMER_CTRL5_TMRA5FN_Msk (0x1c0UL) /*!< TMRA5FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL5_TMRA5CLK_Pos (1UL) /*!< TMRA5CLK (Bit 1) */ +#define CTIMER_CTRL5_TMRA5CLK_Msk (0x3eUL) /*!< TMRA5CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL5_TMRA5EN_Pos (0UL) /*!< TMRA5EN (Bit 0) */ +#define CTIMER_CTRL5_TMRA5EN_Msk (0x1UL) /*!< TMRA5EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA5 ======================================================= */ +#define CTIMER_CMPRAUXA5_CMPR3A5_Pos (16UL) /*!< CMPR3A5 (Bit 16) */ +#define CTIMER_CMPRAUXA5_CMPR3A5_Msk (0xffff0000UL) /*!< CMPR3A5 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA5_CMPR2A5_Pos (0UL) /*!< CMPR2A5 (Bit 0) */ +#define CTIMER_CMPRAUXA5_CMPR2A5_Msk (0xffffUL) /*!< CMPR2A5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB5 ======================================================= */ +#define CTIMER_CMPRAUXB5_CMPR3B5_Pos (16UL) /*!< CMPR3B5 (Bit 16) */ +#define CTIMER_CMPRAUXB5_CMPR3B5_Msk (0xffff0000UL) /*!< CMPR3B5 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB5_CMPR2B5_Pos (0UL) /*!< CMPR2B5 (Bit 0) */ +#define CTIMER_CMPRAUXB5_CMPR2B5_Msk (0xffffUL) /*!< CMPR2B5 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX5 ========================================================== */ +#define CTIMER_AUX5_TMRB5EN23_Pos (30UL) /*!< TMRB5EN23 (Bit 30) */ +#define CTIMER_AUX5_TMRB5EN23_Msk (0x40000000UL) /*!< TMRB5EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRB5POL23_Pos (29UL) /*!< TMRB5POL23 (Bit 29) */ +#define CTIMER_AUX5_TMRB5POL23_Msk (0x20000000UL) /*!< TMRB5POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRB5TINV_Pos (28UL) /*!< TMRB5TINV (Bit 28) */ +#define CTIMER_AUX5_TMRB5TINV_Msk (0x10000000UL) /*!< TMRB5TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRB5NOSYNC_Pos (27UL) /*!< TMRB5NOSYNC (Bit 27) */ +#define CTIMER_AUX5_TMRB5NOSYNC_Msk (0x8000000UL) /*!< TMRB5NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRB5TRIG_Pos (23UL) /*!< TMRB5TRIG (Bit 23) */ +#define CTIMER_AUX5_TMRB5TRIG_Msk (0x7800000UL) /*!< TMRB5TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX5_TMRB5LMT_Pos (16UL) /*!< TMRB5LMT (Bit 16) */ +#define CTIMER_AUX5_TMRB5LMT_Msk (0x3f0000UL) /*!< TMRB5LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX5_TMRA5EN23_Pos (14UL) /*!< TMRA5EN23 (Bit 14) */ +#define CTIMER_AUX5_TMRA5EN23_Msk (0x4000UL) /*!< TMRA5EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRA5POL23_Pos (13UL) /*!< TMRA5POL23 (Bit 13) */ +#define CTIMER_AUX5_TMRA5POL23_Msk (0x2000UL) /*!< TMRA5POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRA5TINV_Pos (12UL) /*!< TMRA5TINV (Bit 12) */ +#define CTIMER_AUX5_TMRA5TINV_Msk (0x1000UL) /*!< TMRA5TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRA5NOSYNC_Pos (11UL) /*!< TMRA5NOSYNC (Bit 11) */ +#define CTIMER_AUX5_TMRA5NOSYNC_Msk (0x800UL) /*!< TMRA5NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRA5TRIG_Pos (7UL) /*!< TMRA5TRIG (Bit 7) */ +#define CTIMER_AUX5_TMRA5TRIG_Msk (0x780UL) /*!< TMRA5TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX5_TMRA5LMT_Pos (0UL) /*!< TMRA5LMT (Bit 0) */ +#define CTIMER_AUX5_TMRA5LMT_Msk (0x7fUL) /*!< TMRA5LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR6 ========================================================== */ +#define CTIMER_TMR6_CTTMRB6_Pos (16UL) /*!< CTTMRB6 (Bit 16) */ +#define CTIMER_TMR6_CTTMRB6_Msk (0xffff0000UL) /*!< CTTMRB6 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR6_CTTMRA6_Pos (0UL) /*!< CTTMRA6 (Bit 0) */ +#define CTIMER_TMR6_CTTMRA6_Msk (0xffffUL) /*!< CTTMRA6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA6 ========================================================= */ +#define CTIMER_CMPRA6_CMPR1A6_Pos (16UL) /*!< CMPR1A6 (Bit 16) */ +#define CTIMER_CMPRA6_CMPR1A6_Msk (0xffff0000UL) /*!< CMPR1A6 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA6_CMPR0A6_Pos (0UL) /*!< CMPR0A6 (Bit 0) */ +#define CTIMER_CMPRA6_CMPR0A6_Msk (0xffffUL) /*!< CMPR0A6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB6 ========================================================= */ +#define CTIMER_CMPRB6_CMPR1B6_Pos (16UL) /*!< CMPR1B6 (Bit 16) */ +#define CTIMER_CMPRB6_CMPR1B6_Msk (0xffff0000UL) /*!< CMPR1B6 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB6_CMPR0B6_Pos (0UL) /*!< CMPR0B6 (Bit 0) */ +#define CTIMER_CMPRB6_CMPR0B6_Msk (0xffffUL) /*!< CMPR0B6 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL6 ========================================================= */ +#define CTIMER_CTRL6_CTLINK6_Pos (31UL) /*!< CTLINK6 (Bit 31) */ +#define CTIMER_CTRL6_CTLINK6_Msk (0x80000000UL) /*!< CTLINK6 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRB6POL_Pos (28UL) /*!< TMRB6POL (Bit 28) */ +#define CTIMER_CTRL6_TMRB6POL_Msk (0x10000000UL) /*!< TMRB6POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRB6CLR_Pos (27UL) /*!< TMRB6CLR (Bit 27) */ +#define CTIMER_CTRL6_TMRB6CLR_Msk (0x8000000UL) /*!< TMRB6CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRB6IE1_Pos (26UL) /*!< TMRB6IE1 (Bit 26) */ +#define CTIMER_CTRL6_TMRB6IE1_Msk (0x4000000UL) /*!< TMRB6IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRB6IE0_Pos (25UL) /*!< TMRB6IE0 (Bit 25) */ +#define CTIMER_CTRL6_TMRB6IE0_Msk (0x2000000UL) /*!< TMRB6IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRB6FN_Pos (22UL) /*!< TMRB6FN (Bit 22) */ +#define CTIMER_CTRL6_TMRB6FN_Msk (0x1c00000UL) /*!< TMRB6FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL6_TMRB6CLK_Pos (17UL) /*!< TMRB6CLK (Bit 17) */ +#define CTIMER_CTRL6_TMRB6CLK_Msk (0x3e0000UL) /*!< TMRB6CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL6_TMRB6EN_Pos (16UL) /*!< TMRB6EN (Bit 16) */ +#define CTIMER_CTRL6_TMRB6EN_Msk (0x10000UL) /*!< TMRB6EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRA6POL_Pos (12UL) /*!< TMRA6POL (Bit 12) */ +#define CTIMER_CTRL6_TMRA6POL_Msk (0x1000UL) /*!< TMRA6POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRA6CLR_Pos (11UL) /*!< TMRA6CLR (Bit 11) */ +#define CTIMER_CTRL6_TMRA6CLR_Msk (0x800UL) /*!< TMRA6CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRA6IE1_Pos (10UL) /*!< TMRA6IE1 (Bit 10) */ +#define CTIMER_CTRL6_TMRA6IE1_Msk (0x400UL) /*!< TMRA6IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRA6IE0_Pos (9UL) /*!< TMRA6IE0 (Bit 9) */ +#define CTIMER_CTRL6_TMRA6IE0_Msk (0x200UL) /*!< TMRA6IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRA6FN_Pos (6UL) /*!< TMRA6FN (Bit 6) */ +#define CTIMER_CTRL6_TMRA6FN_Msk (0x1c0UL) /*!< TMRA6FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL6_TMRA6CLK_Pos (1UL) /*!< TMRA6CLK (Bit 1) */ +#define CTIMER_CTRL6_TMRA6CLK_Msk (0x3eUL) /*!< TMRA6CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL6_TMRA6EN_Pos (0UL) /*!< TMRA6EN (Bit 0) */ +#define CTIMER_CTRL6_TMRA6EN_Msk (0x1UL) /*!< TMRA6EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA6 ======================================================= */ +#define CTIMER_CMPRAUXA6_CMPR3A6_Pos (16UL) /*!< CMPR3A6 (Bit 16) */ +#define CTIMER_CMPRAUXA6_CMPR3A6_Msk (0xffff0000UL) /*!< CMPR3A6 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA6_CMPR2A6_Pos (0UL) /*!< CMPR2A6 (Bit 0) */ +#define CTIMER_CMPRAUXA6_CMPR2A6_Msk (0xffffUL) /*!< CMPR2A6 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB6 ======================================================= */ +#define CTIMER_CMPRAUXB6_CMPR3B6_Pos (16UL) /*!< CMPR3B6 (Bit 16) */ +#define CTIMER_CMPRAUXB6_CMPR3B6_Msk (0xffff0000UL) /*!< CMPR3B6 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB6_CMPR2B6_Pos (0UL) /*!< CMPR2B6 (Bit 0) */ +#define CTIMER_CMPRAUXB6_CMPR2B6_Msk (0xffffUL) /*!< CMPR2B6 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX6 ========================================================== */ +#define CTIMER_AUX6_TMRB6EN23_Pos (30UL) /*!< TMRB6EN23 (Bit 30) */ +#define CTIMER_AUX6_TMRB6EN23_Msk (0x40000000UL) /*!< TMRB6EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRB6POL23_Pos (29UL) /*!< TMRB6POL23 (Bit 29) */ +#define CTIMER_AUX6_TMRB6POL23_Msk (0x20000000UL) /*!< TMRB6POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRB6TINV_Pos (28UL) /*!< TMRB6TINV (Bit 28) */ +#define CTIMER_AUX6_TMRB6TINV_Msk (0x10000000UL) /*!< TMRB6TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRB6NOSYNC_Pos (27UL) /*!< TMRB6NOSYNC (Bit 27) */ +#define CTIMER_AUX6_TMRB6NOSYNC_Msk (0x8000000UL) /*!< TMRB6NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRB6TRIG_Pos (23UL) /*!< TMRB6TRIG (Bit 23) */ +#define CTIMER_AUX6_TMRB6TRIG_Msk (0x7800000UL) /*!< TMRB6TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX6_TMRB6LMT_Pos (16UL) /*!< TMRB6LMT (Bit 16) */ +#define CTIMER_AUX6_TMRB6LMT_Msk (0x3f0000UL) /*!< TMRB6LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX6_TMRA6EN23_Pos (14UL) /*!< TMRA6EN23 (Bit 14) */ +#define CTIMER_AUX6_TMRA6EN23_Msk (0x4000UL) /*!< TMRA6EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRA6POL23_Pos (13UL) /*!< TMRA6POL23 (Bit 13) */ +#define CTIMER_AUX6_TMRA6POL23_Msk (0x2000UL) /*!< TMRA6POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRA6TINV_Pos (12UL) /*!< TMRA6TINV (Bit 12) */ +#define CTIMER_AUX6_TMRA6TINV_Msk (0x1000UL) /*!< TMRA6TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRA6NOSYNC_Pos (11UL) /*!< TMRA6NOSYNC (Bit 11) */ +#define CTIMER_AUX6_TMRA6NOSYNC_Msk (0x800UL) /*!< TMRA6NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRA6TRIG_Pos (7UL) /*!< TMRA6TRIG (Bit 7) */ +#define CTIMER_AUX6_TMRA6TRIG_Msk (0x780UL) /*!< TMRA6TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX6_TMRA6LMT_Pos (0UL) /*!< TMRA6LMT (Bit 0) */ +#define CTIMER_AUX6_TMRA6LMT_Msk (0x7fUL) /*!< TMRA6LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR7 ========================================================== */ +#define CTIMER_TMR7_CTTMRB7_Pos (16UL) /*!< CTTMRB7 (Bit 16) */ +#define CTIMER_TMR7_CTTMRB7_Msk (0xffff0000UL) /*!< CTTMRB7 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR7_CTTMRA7_Pos (0UL) /*!< CTTMRA7 (Bit 0) */ +#define CTIMER_TMR7_CTTMRA7_Msk (0xffffUL) /*!< CTTMRA7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA7 ========================================================= */ +#define CTIMER_CMPRA7_CMPR1A7_Pos (16UL) /*!< CMPR1A7 (Bit 16) */ +#define CTIMER_CMPRA7_CMPR1A7_Msk (0xffff0000UL) /*!< CMPR1A7 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA7_CMPR0A7_Pos (0UL) /*!< CMPR0A7 (Bit 0) */ +#define CTIMER_CMPRA7_CMPR0A7_Msk (0xffffUL) /*!< CMPR0A7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB7 ========================================================= */ +#define CTIMER_CMPRB7_CMPR1B7_Pos (16UL) /*!< CMPR1B7 (Bit 16) */ +#define CTIMER_CMPRB7_CMPR1B7_Msk (0xffff0000UL) /*!< CMPR1B7 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB7_CMPR0B7_Pos (0UL) /*!< CMPR0B7 (Bit 0) */ +#define CTIMER_CMPRB7_CMPR0B7_Msk (0xffffUL) /*!< CMPR0B7 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL7 ========================================================= */ +#define CTIMER_CTRL7_CTLINK7_Pos (31UL) /*!< CTLINK7 (Bit 31) */ +#define CTIMER_CTRL7_CTLINK7_Msk (0x80000000UL) /*!< CTLINK7 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRB7POL_Pos (28UL) /*!< TMRB7POL (Bit 28) */ +#define CTIMER_CTRL7_TMRB7POL_Msk (0x10000000UL) /*!< TMRB7POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRB7CLR_Pos (27UL) /*!< TMRB7CLR (Bit 27) */ +#define CTIMER_CTRL7_TMRB7CLR_Msk (0x8000000UL) /*!< TMRB7CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRB7IE1_Pos (26UL) /*!< TMRB7IE1 (Bit 26) */ +#define CTIMER_CTRL7_TMRB7IE1_Msk (0x4000000UL) /*!< TMRB7IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRB7IE0_Pos (25UL) /*!< TMRB7IE0 (Bit 25) */ +#define CTIMER_CTRL7_TMRB7IE0_Msk (0x2000000UL) /*!< TMRB7IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRB7FN_Pos (22UL) /*!< TMRB7FN (Bit 22) */ +#define CTIMER_CTRL7_TMRB7FN_Msk (0x1c00000UL) /*!< TMRB7FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL7_TMRB7CLK_Pos (17UL) /*!< TMRB7CLK (Bit 17) */ +#define CTIMER_CTRL7_TMRB7CLK_Msk (0x3e0000UL) /*!< TMRB7CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL7_TMRB7EN_Pos (16UL) /*!< TMRB7EN (Bit 16) */ +#define CTIMER_CTRL7_TMRB7EN_Msk (0x10000UL) /*!< TMRB7EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRA7POL_Pos (12UL) /*!< TMRA7POL (Bit 12) */ +#define CTIMER_CTRL7_TMRA7POL_Msk (0x1000UL) /*!< TMRA7POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRA7CLR_Pos (11UL) /*!< TMRA7CLR (Bit 11) */ +#define CTIMER_CTRL7_TMRA7CLR_Msk (0x800UL) /*!< TMRA7CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRA7IE1_Pos (10UL) /*!< TMRA7IE1 (Bit 10) */ +#define CTIMER_CTRL7_TMRA7IE1_Msk (0x400UL) /*!< TMRA7IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRA7IE0_Pos (9UL) /*!< TMRA7IE0 (Bit 9) */ +#define CTIMER_CTRL7_TMRA7IE0_Msk (0x200UL) /*!< TMRA7IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRA7FN_Pos (6UL) /*!< TMRA7FN (Bit 6) */ +#define CTIMER_CTRL7_TMRA7FN_Msk (0x1c0UL) /*!< TMRA7FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL7_TMRA7CLK_Pos (1UL) /*!< TMRA7CLK (Bit 1) */ +#define CTIMER_CTRL7_TMRA7CLK_Msk (0x3eUL) /*!< TMRA7CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL7_TMRA7EN_Pos (0UL) /*!< TMRA7EN (Bit 0) */ +#define CTIMER_CTRL7_TMRA7EN_Msk (0x1UL) /*!< TMRA7EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA7 ======================================================= */ +#define CTIMER_CMPRAUXA7_CMPR3A7_Pos (16UL) /*!< CMPR3A7 (Bit 16) */ +#define CTIMER_CMPRAUXA7_CMPR3A7_Msk (0xffff0000UL) /*!< CMPR3A7 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA7_CMPR2A7_Pos (0UL) /*!< CMPR2A7 (Bit 0) */ +#define CTIMER_CMPRAUXA7_CMPR2A7_Msk (0xffffUL) /*!< CMPR2A7 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB7 ======================================================= */ +#define CTIMER_CMPRAUXB7_CMPR3B7_Pos (16UL) /*!< CMPR3B7 (Bit 16) */ +#define CTIMER_CMPRAUXB7_CMPR3B7_Msk (0xffff0000UL) /*!< CMPR3B7 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB7_CMPR2B7_Pos (0UL) /*!< CMPR2B7 (Bit 0) */ +#define CTIMER_CMPRAUXB7_CMPR2B7_Msk (0xffffUL) /*!< CMPR2B7 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX7 ========================================================== */ +#define CTIMER_AUX7_TMRB7EN23_Pos (30UL) /*!< TMRB7EN23 (Bit 30) */ +#define CTIMER_AUX7_TMRB7EN23_Msk (0x40000000UL) /*!< TMRB7EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRB7POL23_Pos (29UL) /*!< TMRB7POL23 (Bit 29) */ +#define CTIMER_AUX7_TMRB7POL23_Msk (0x20000000UL) /*!< TMRB7POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRB7TINV_Pos (28UL) /*!< TMRB7TINV (Bit 28) */ +#define CTIMER_AUX7_TMRB7TINV_Msk (0x10000000UL) /*!< TMRB7TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRB7NOSYNC_Pos (27UL) /*!< TMRB7NOSYNC (Bit 27) */ +#define CTIMER_AUX7_TMRB7NOSYNC_Msk (0x8000000UL) /*!< TMRB7NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRB7TRIG_Pos (23UL) /*!< TMRB7TRIG (Bit 23) */ +#define CTIMER_AUX7_TMRB7TRIG_Msk (0x7800000UL) /*!< TMRB7TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX7_TMRB7LMT_Pos (16UL) /*!< TMRB7LMT (Bit 16) */ +#define CTIMER_AUX7_TMRB7LMT_Msk (0x3f0000UL) /*!< TMRB7LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX7_TMRA7EN23_Pos (14UL) /*!< TMRA7EN23 (Bit 14) */ +#define CTIMER_AUX7_TMRA7EN23_Msk (0x4000UL) /*!< TMRA7EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRA7POL23_Pos (13UL) /*!< TMRA7POL23 (Bit 13) */ +#define CTIMER_AUX7_TMRA7POL23_Msk (0x2000UL) /*!< TMRA7POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRA7TINV_Pos (12UL) /*!< TMRA7TINV (Bit 12) */ +#define CTIMER_AUX7_TMRA7TINV_Msk (0x1000UL) /*!< TMRA7TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRA7NOSYNC_Pos (11UL) /*!< TMRA7NOSYNC (Bit 11) */ +#define CTIMER_AUX7_TMRA7NOSYNC_Msk (0x800UL) /*!< TMRA7NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRA7TRIG_Pos (7UL) /*!< TMRA7TRIG (Bit 7) */ +#define CTIMER_AUX7_TMRA7TRIG_Msk (0x780UL) /*!< TMRA7TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX7_TMRA7LMT_Pos (0UL) /*!< TMRA7LMT (Bit 0) */ +#define CTIMER_AUX7_TMRA7LMT_Msk (0x7fUL) /*!< TMRA7LMT (Bitfield-Mask: 0x7f) */ +/* ======================================================== GLOBEN ========================================================= */ +#define CTIMER_GLOBEN_ENB7_Pos (15UL) /*!< ENB7 (Bit 15) */ +#define CTIMER_GLOBEN_ENB7_Msk (0x8000UL) /*!< ENB7 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA7_Pos (14UL) /*!< ENA7 (Bit 14) */ +#define CTIMER_GLOBEN_ENA7_Msk (0x4000UL) /*!< ENA7 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB6_Pos (13UL) /*!< ENB6 (Bit 13) */ +#define CTIMER_GLOBEN_ENB6_Msk (0x2000UL) /*!< ENB6 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA6_Pos (12UL) /*!< ENA6 (Bit 12) */ +#define CTIMER_GLOBEN_ENA6_Msk (0x1000UL) /*!< ENA6 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB5_Pos (11UL) /*!< ENB5 (Bit 11) */ +#define CTIMER_GLOBEN_ENB5_Msk (0x800UL) /*!< ENB5 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA5_Pos (10UL) /*!< ENA5 (Bit 10) */ +#define CTIMER_GLOBEN_ENA5_Msk (0x400UL) /*!< ENA5 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB4_Pos (9UL) /*!< ENB4 (Bit 9) */ +#define CTIMER_GLOBEN_ENB4_Msk (0x200UL) /*!< ENB4 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA4_Pos (8UL) /*!< ENA4 (Bit 8) */ +#define CTIMER_GLOBEN_ENA4_Msk (0x100UL) /*!< ENA4 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB3_Pos (7UL) /*!< ENB3 (Bit 7) */ +#define CTIMER_GLOBEN_ENB3_Msk (0x80UL) /*!< ENB3 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA3_Pos (6UL) /*!< ENA3 (Bit 6) */ +#define CTIMER_GLOBEN_ENA3_Msk (0x40UL) /*!< ENA3 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB2_Pos (5UL) /*!< ENB2 (Bit 5) */ +#define CTIMER_GLOBEN_ENB2_Msk (0x20UL) /*!< ENB2 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA2_Pos (4UL) /*!< ENA2 (Bit 4) */ +#define CTIMER_GLOBEN_ENA2_Msk (0x10UL) /*!< ENA2 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB1_Pos (3UL) /*!< ENB1 (Bit 3) */ +#define CTIMER_GLOBEN_ENB1_Msk (0x8UL) /*!< ENB1 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA1_Pos (2UL) /*!< ENA1 (Bit 2) */ +#define CTIMER_GLOBEN_ENA1_Msk (0x4UL) /*!< ENA1 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB0_Pos (1UL) /*!< ENB0 (Bit 1) */ +#define CTIMER_GLOBEN_ENB0_Msk (0x2UL) /*!< ENB0 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA0_Pos (0UL) /*!< ENA0 (Bit 0) */ +#define CTIMER_GLOBEN_ENA0_Msk (0x1UL) /*!< ENA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== OUTCFG0 ======================================================== */ +#define CTIMER_OUTCFG0_CFG9_Pos (28UL) /*!< CFG9 (Bit 28) */ +#define CTIMER_OUTCFG0_CFG9_Msk (0x70000000UL) /*!< CFG9 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG8_Pos (25UL) /*!< CFG8 (Bit 25) */ +#define CTIMER_OUTCFG0_CFG8_Msk (0xe000000UL) /*!< CFG8 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG7_Pos (22UL) /*!< CFG7 (Bit 22) */ +#define CTIMER_OUTCFG0_CFG7_Msk (0x1c00000UL) /*!< CFG7 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG6_Pos (19UL) /*!< CFG6 (Bit 19) */ +#define CTIMER_OUTCFG0_CFG6_Msk (0x380000UL) /*!< CFG6 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG5_Pos (16UL) /*!< CFG5 (Bit 16) */ +#define CTIMER_OUTCFG0_CFG5_Msk (0x70000UL) /*!< CFG5 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG4_Pos (12UL) /*!< CFG4 (Bit 12) */ +#define CTIMER_OUTCFG0_CFG4_Msk (0x7000UL) /*!< CFG4 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG3_Pos (9UL) /*!< CFG3 (Bit 9) */ +#define CTIMER_OUTCFG0_CFG3_Msk (0xe00UL) /*!< CFG3 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG2_Pos (6UL) /*!< CFG2 (Bit 6) */ +#define CTIMER_OUTCFG0_CFG2_Msk (0x1c0UL) /*!< CFG2 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG1_Pos (3UL) /*!< CFG1 (Bit 3) */ +#define CTIMER_OUTCFG0_CFG1_Msk (0x38UL) /*!< CFG1 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG0_Pos (0UL) /*!< CFG0 (Bit 0) */ +#define CTIMER_OUTCFG0_CFG0_Msk (0x7UL) /*!< CFG0 (Bitfield-Mask: 0x07) */ +/* ======================================================== OUTCFG1 ======================================================== */ +#define CTIMER_OUTCFG1_CFG19_Pos (28UL) /*!< CFG19 (Bit 28) */ +#define CTIMER_OUTCFG1_CFG19_Msk (0x70000000UL) /*!< CFG19 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG18_Pos (25UL) /*!< CFG18 (Bit 25) */ +#define CTIMER_OUTCFG1_CFG18_Msk (0xe000000UL) /*!< CFG18 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG17_Pos (22UL) /*!< CFG17 (Bit 22) */ +#define CTIMER_OUTCFG1_CFG17_Msk (0x1c00000UL) /*!< CFG17 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG16_Pos (19UL) /*!< CFG16 (Bit 19) */ +#define CTIMER_OUTCFG1_CFG16_Msk (0x380000UL) /*!< CFG16 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG15_Pos (16UL) /*!< CFG15 (Bit 16) */ +#define CTIMER_OUTCFG1_CFG15_Msk (0x70000UL) /*!< CFG15 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG14_Pos (12UL) /*!< CFG14 (Bit 12) */ +#define CTIMER_OUTCFG1_CFG14_Msk (0x7000UL) /*!< CFG14 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG13_Pos (9UL) /*!< CFG13 (Bit 9) */ +#define CTIMER_OUTCFG1_CFG13_Msk (0xe00UL) /*!< CFG13 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG12_Pos (6UL) /*!< CFG12 (Bit 6) */ +#define CTIMER_OUTCFG1_CFG12_Msk (0x1c0UL) /*!< CFG12 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG11_Pos (3UL) /*!< CFG11 (Bit 3) */ +#define CTIMER_OUTCFG1_CFG11_Msk (0x38UL) /*!< CFG11 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG10_Pos (0UL) /*!< CFG10 (Bit 0) */ +#define CTIMER_OUTCFG1_CFG10_Msk (0x7UL) /*!< CFG10 (Bitfield-Mask: 0x07) */ +/* ======================================================== OUTCFG2 ======================================================== */ +#define CTIMER_OUTCFG2_CFG29_Pos (28UL) /*!< CFG29 (Bit 28) */ +#define CTIMER_OUTCFG2_CFG29_Msk (0x70000000UL) /*!< CFG29 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG28_Pos (25UL) /*!< CFG28 (Bit 25) */ +#define CTIMER_OUTCFG2_CFG28_Msk (0xe000000UL) /*!< CFG28 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG27_Pos (22UL) /*!< CFG27 (Bit 22) */ +#define CTIMER_OUTCFG2_CFG27_Msk (0x1c00000UL) /*!< CFG27 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG26_Pos (19UL) /*!< CFG26 (Bit 19) */ +#define CTIMER_OUTCFG2_CFG26_Msk (0x380000UL) /*!< CFG26 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG25_Pos (16UL) /*!< CFG25 (Bit 16) */ +#define CTIMER_OUTCFG2_CFG25_Msk (0x70000UL) /*!< CFG25 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG24_Pos (12UL) /*!< CFG24 (Bit 12) */ +#define CTIMER_OUTCFG2_CFG24_Msk (0x7000UL) /*!< CFG24 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG23_Pos (9UL) /*!< CFG23 (Bit 9) */ +#define CTIMER_OUTCFG2_CFG23_Msk (0xe00UL) /*!< CFG23 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG22_Pos (6UL) /*!< CFG22 (Bit 6) */ +#define CTIMER_OUTCFG2_CFG22_Msk (0x1c0UL) /*!< CFG22 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG21_Pos (3UL) /*!< CFG21 (Bit 3) */ +#define CTIMER_OUTCFG2_CFG21_Msk (0x38UL) /*!< CFG21 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG20_Pos (0UL) /*!< CFG20 (Bit 0) */ +#define CTIMER_OUTCFG2_CFG20_Msk (0x7UL) /*!< CFG20 (Bitfield-Mask: 0x07) */ +/* ======================================================== OUTCFG3 ======================================================== */ +#define CTIMER_OUTCFG3_CFG31_Pos (3UL) /*!< CFG31 (Bit 3) */ +#define CTIMER_OUTCFG3_CFG31_Msk (0x38UL) /*!< CFG31 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG3_CFG30_Pos (0UL) /*!< CFG30 (Bit 0) */ +#define CTIMER_OUTCFG3_CFG30_Msk (0x7UL) /*!< CFG30 (Bitfield-Mask: 0x07) */ +/* ========================================================= INCFG ========================================================= */ +#define CTIMER_INCFG_CFGB7_Pos (15UL) /*!< CFGB7 (Bit 15) */ +#define CTIMER_INCFG_CFGB7_Msk (0x8000UL) /*!< CFGB7 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA7_Pos (14UL) /*!< CFGA7 (Bit 14) */ +#define CTIMER_INCFG_CFGA7_Msk (0x4000UL) /*!< CFGA7 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB6_Pos (13UL) /*!< CFGB6 (Bit 13) */ +#define CTIMER_INCFG_CFGB6_Msk (0x2000UL) /*!< CFGB6 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA6_Pos (12UL) /*!< CFGA6 (Bit 12) */ +#define CTIMER_INCFG_CFGA6_Msk (0x1000UL) /*!< CFGA6 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB5_Pos (11UL) /*!< CFGB5 (Bit 11) */ +#define CTIMER_INCFG_CFGB5_Msk (0x800UL) /*!< CFGB5 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA5_Pos (10UL) /*!< CFGA5 (Bit 10) */ +#define CTIMER_INCFG_CFGA5_Msk (0x400UL) /*!< CFGA5 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB4_Pos (9UL) /*!< CFGB4 (Bit 9) */ +#define CTIMER_INCFG_CFGB4_Msk (0x200UL) /*!< CFGB4 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA4_Pos (8UL) /*!< CFGA4 (Bit 8) */ +#define CTIMER_INCFG_CFGA4_Msk (0x100UL) /*!< CFGA4 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB3_Pos (7UL) /*!< CFGB3 (Bit 7) */ +#define CTIMER_INCFG_CFGB3_Msk (0x80UL) /*!< CFGB3 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA3_Pos (6UL) /*!< CFGA3 (Bit 6) */ +#define CTIMER_INCFG_CFGA3_Msk (0x40UL) /*!< CFGA3 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB2_Pos (5UL) /*!< CFGB2 (Bit 5) */ +#define CTIMER_INCFG_CFGB2_Msk (0x20UL) /*!< CFGB2 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA2_Pos (4UL) /*!< CFGA2 (Bit 4) */ +#define CTIMER_INCFG_CFGA2_Msk (0x10UL) /*!< CFGA2 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB1_Pos (3UL) /*!< CFGB1 (Bit 3) */ +#define CTIMER_INCFG_CFGB1_Msk (0x8UL) /*!< CFGB1 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA1_Pos (2UL) /*!< CFGA1 (Bit 2) */ +#define CTIMER_INCFG_CFGA1_Msk (0x4UL) /*!< CFGA1 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB0_Pos (1UL) /*!< CFGB0 (Bit 1) */ +#define CTIMER_INCFG_CFGB0_Msk (0x2UL) /*!< CFGB0 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA0_Pos (0UL) /*!< CFGA0 (Bit 0) */ +#define CTIMER_INCFG_CFGA0_Msk (0x1UL) /*!< CFGA0 (Bitfield-Mask: 0x01) */ +/* ========================================================= STCFG ========================================================= */ +#define CTIMER_STCFG_FREEZE_Pos (31UL) /*!< FREEZE (Bit 31) */ +#define CTIMER_STCFG_FREEZE_Msk (0x80000000UL) /*!< FREEZE (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_CLEAR_Pos (30UL) /*!< CLEAR (Bit 30) */ +#define CTIMER_STCFG_CLEAR_Msk (0x40000000UL) /*!< CLEAR (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_H_EN_Pos (15UL) /*!< COMPARE_H_EN (Bit 15) */ +#define CTIMER_STCFG_COMPARE_H_EN_Msk (0x8000UL) /*!< COMPARE_H_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_G_EN_Pos (14UL) /*!< COMPARE_G_EN (Bit 14) */ +#define CTIMER_STCFG_COMPARE_G_EN_Msk (0x4000UL) /*!< COMPARE_G_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_F_EN_Pos (13UL) /*!< COMPARE_F_EN (Bit 13) */ +#define CTIMER_STCFG_COMPARE_F_EN_Msk (0x2000UL) /*!< COMPARE_F_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_E_EN_Pos (12UL) /*!< COMPARE_E_EN (Bit 12) */ +#define CTIMER_STCFG_COMPARE_E_EN_Msk (0x1000UL) /*!< COMPARE_E_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_D_EN_Pos (11UL) /*!< COMPARE_D_EN (Bit 11) */ +#define CTIMER_STCFG_COMPARE_D_EN_Msk (0x800UL) /*!< COMPARE_D_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_C_EN_Pos (10UL) /*!< COMPARE_C_EN (Bit 10) */ +#define CTIMER_STCFG_COMPARE_C_EN_Msk (0x400UL) /*!< COMPARE_C_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_B_EN_Pos (9UL) /*!< COMPARE_B_EN (Bit 9) */ +#define CTIMER_STCFG_COMPARE_B_EN_Msk (0x200UL) /*!< COMPARE_B_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_A_EN_Pos (8UL) /*!< COMPARE_A_EN (Bit 8) */ +#define CTIMER_STCFG_COMPARE_A_EN_Msk (0x100UL) /*!< COMPARE_A_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ +#define CTIMER_STCFG_CLKSEL_Msk (0xfUL) /*!< CLKSEL (Bitfield-Mask: 0x0f) */ +/* ========================================================= STTMR ========================================================= */ +#define CTIMER_STTMR_STTMR_Pos (0UL) /*!< STTMR (Bit 0) */ +#define CTIMER_STTMR_STTMR_Msk (0xffffffffUL) /*!< STTMR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CAPTURECONTROL ===================================================== */ +#define CTIMER_CAPTURECONTROL_CAPTURE3_Pos (3UL) /*!< CAPTURE3 (Bit 3) */ +#define CTIMER_CAPTURECONTROL_CAPTURE3_Msk (0x8UL) /*!< CAPTURE3 (Bitfield-Mask: 0x01) */ +#define CTIMER_CAPTURECONTROL_CAPTURE2_Pos (2UL) /*!< CAPTURE2 (Bit 2) */ +#define CTIMER_CAPTURECONTROL_CAPTURE2_Msk (0x4UL) /*!< CAPTURE2 (Bitfield-Mask: 0x01) */ +#define CTIMER_CAPTURECONTROL_CAPTURE1_Pos (1UL) /*!< CAPTURE1 (Bit 1) */ +#define CTIMER_CAPTURECONTROL_CAPTURE1_Msk (0x2UL) /*!< CAPTURE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CAPTURECONTROL_CAPTURE0_Pos (0UL) /*!< CAPTURE0 (Bit 0) */ +#define CTIMER_CAPTURECONTROL_CAPTURE0_Msk (0x1UL) /*!< CAPTURE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SCMPR0 ========================================================= */ +#define CTIMER_SCMPR0_SCMPR0_Pos (0UL) /*!< SCMPR0 (Bit 0) */ +#define CTIMER_SCMPR0_SCMPR0_Msk (0xffffffffUL) /*!< SCMPR0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR1 ========================================================= */ +#define CTIMER_SCMPR1_SCMPR1_Pos (0UL) /*!< SCMPR1 (Bit 0) */ +#define CTIMER_SCMPR1_SCMPR1_Msk (0xffffffffUL) /*!< SCMPR1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR2 ========================================================= */ +#define CTIMER_SCMPR2_SCMPR2_Pos (0UL) /*!< SCMPR2 (Bit 0) */ +#define CTIMER_SCMPR2_SCMPR2_Msk (0xffffffffUL) /*!< SCMPR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR3 ========================================================= */ +#define CTIMER_SCMPR3_SCMPR3_Pos (0UL) /*!< SCMPR3 (Bit 0) */ +#define CTIMER_SCMPR3_SCMPR3_Msk (0xffffffffUL) /*!< SCMPR3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR4 ========================================================= */ +#define CTIMER_SCMPR4_SCMPR4_Pos (0UL) /*!< SCMPR4 (Bit 0) */ +#define CTIMER_SCMPR4_SCMPR4_Msk (0xffffffffUL) /*!< SCMPR4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR5 ========================================================= */ +#define CTIMER_SCMPR5_SCMPR5_Pos (0UL) /*!< SCMPR5 (Bit 0) */ +#define CTIMER_SCMPR5_SCMPR5_Msk (0xffffffffUL) /*!< SCMPR5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR6 ========================================================= */ +#define CTIMER_SCMPR6_SCMPR6_Pos (0UL) /*!< SCMPR6 (Bit 0) */ +#define CTIMER_SCMPR6_SCMPR6_Msk (0xffffffffUL) /*!< SCMPR6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR7 ========================================================= */ +#define CTIMER_SCMPR7_SCMPR7_Pos (0UL) /*!< SCMPR7 (Bit 0) */ +#define CTIMER_SCMPR7_SCMPR7_Msk (0xffffffffUL) /*!< SCMPR7 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT0 ========================================================= */ +#define CTIMER_SCAPT0_SCAPT0_Pos (0UL) /*!< SCAPT0 (Bit 0) */ +#define CTIMER_SCAPT0_SCAPT0_Msk (0xffffffffUL) /*!< SCAPT0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT1 ========================================================= */ +#define CTIMER_SCAPT1_SCAPT1_Pos (0UL) /*!< SCAPT1 (Bit 0) */ +#define CTIMER_SCAPT1_SCAPT1_Msk (0xffffffffUL) /*!< SCAPT1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT2 ========================================================= */ +#define CTIMER_SCAPT2_SCAPT2_Pos (0UL) /*!< SCAPT2 (Bit 0) */ +#define CTIMER_SCAPT2_SCAPT2_Msk (0xffffffffUL) /*!< SCAPT2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT3 ========================================================= */ +#define CTIMER_SCAPT3_SCAPT3_Pos (0UL) /*!< SCAPT3 (Bit 0) */ +#define CTIMER_SCAPT3_SCAPT3_Msk (0xffffffffUL) /*!< SCAPT3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR0 ========================================================= */ +#define CTIMER_SNVR0_SNVR0_Pos (0UL) /*!< SNVR0 (Bit 0) */ +#define CTIMER_SNVR0_SNVR0_Msk (0xffffffffUL) /*!< SNVR0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR1 ========================================================= */ +#define CTIMER_SNVR1_SNVR1_Pos (0UL) /*!< SNVR1 (Bit 0) */ +#define CTIMER_SNVR1_SNVR1_Msk (0xffffffffUL) /*!< SNVR1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR2 ========================================================= */ +#define CTIMER_SNVR2_SNVR2_Pos (0UL) /*!< SNVR2 (Bit 0) */ +#define CTIMER_SNVR2_SNVR2_Msk (0xffffffffUL) /*!< SNVR2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR3 ========================================================= */ +#define CTIMER_SNVR3_SNVR3_Pos (0UL) /*!< SNVR3 (Bit 0) */ +#define CTIMER_SNVR3_SNVR3_Msk (0xffffffffUL) /*!< SNVR3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTEN ========================================================= */ +#define CTIMER_INTEN_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */ +#define CTIMER_INTEN_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */ +#define CTIMER_INTEN_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */ +#define CTIMER_INTEN_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */ +#define CTIMER_INTEN_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */ +#define CTIMER_INTEN_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */ +#define CTIMER_INTEN_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */ +#define CTIMER_INTEN_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */ +#define CTIMER_INTEN_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */ +#define CTIMER_INTEN_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */ +#define CTIMER_INTEN_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */ +#define CTIMER_INTEN_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */ +#define CTIMER_INTEN_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */ +#define CTIMER_INTEN_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */ +#define CTIMER_INTEN_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */ +#define CTIMER_INTEN_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */ +#define CTIMER_INTEN_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */ +#define CTIMER_INTEN_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */ +#define CTIMER_INTEN_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */ +#define CTIMER_INTEN_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */ +#define CTIMER_INTEN_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */ +#define CTIMER_INTEN_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */ +#define CTIMER_INTEN_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */ +#define CTIMER_INTEN_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */ +#define CTIMER_INTEN_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTEN_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTEN_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTEN_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTEN_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTEN_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTEN_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTEN_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTEN_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define CTIMER_INTSTAT_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */ +#define CTIMER_INTSTAT_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */ +#define CTIMER_INTSTAT_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */ +#define CTIMER_INTSTAT_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */ +#define CTIMER_INTSTAT_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */ +#define CTIMER_INTSTAT_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */ +#define CTIMER_INTSTAT_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */ +#define CTIMER_INTSTAT_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */ +#define CTIMER_INTSTAT_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */ +#define CTIMER_INTSTAT_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */ +#define CTIMER_INTSTAT_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */ +#define CTIMER_INTSTAT_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */ +#define CTIMER_INTSTAT_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */ +#define CTIMER_INTSTAT_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */ +#define CTIMER_INTSTAT_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */ +#define CTIMER_INTSTAT_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */ +#define CTIMER_INTSTAT_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */ +#define CTIMER_INTSTAT_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */ +#define CTIMER_INTSTAT_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */ +#define CTIMER_INTSTAT_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */ +#define CTIMER_INTSTAT_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */ +#define CTIMER_INTSTAT_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */ +#define CTIMER_INTSTAT_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */ +#define CTIMER_INTSTAT_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */ +#define CTIMER_INTSTAT_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTSTAT_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTSTAT_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTSTAT_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTSTAT_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTSTAT_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTSTAT_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTSTAT_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTSTAT_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define CTIMER_INTCLR_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */ +#define CTIMER_INTCLR_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */ +#define CTIMER_INTCLR_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */ +#define CTIMER_INTCLR_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */ +#define CTIMER_INTCLR_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */ +#define CTIMER_INTCLR_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */ +#define CTIMER_INTCLR_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */ +#define CTIMER_INTCLR_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */ +#define CTIMER_INTCLR_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */ +#define CTIMER_INTCLR_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */ +#define CTIMER_INTCLR_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */ +#define CTIMER_INTCLR_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */ +#define CTIMER_INTCLR_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */ +#define CTIMER_INTCLR_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */ +#define CTIMER_INTCLR_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */ +#define CTIMER_INTCLR_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */ +#define CTIMER_INTCLR_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */ +#define CTIMER_INTCLR_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */ +#define CTIMER_INTCLR_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */ +#define CTIMER_INTCLR_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */ +#define CTIMER_INTCLR_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */ +#define CTIMER_INTCLR_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */ +#define CTIMER_INTCLR_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */ +#define CTIMER_INTCLR_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */ +#define CTIMER_INTCLR_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTCLR_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTCLR_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTCLR_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTCLR_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTCLR_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTCLR_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTCLR_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTCLR_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define CTIMER_INTSET_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */ +#define CTIMER_INTSET_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */ +#define CTIMER_INTSET_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */ +#define CTIMER_INTSET_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */ +#define CTIMER_INTSET_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */ +#define CTIMER_INTSET_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */ +#define CTIMER_INTSET_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */ +#define CTIMER_INTSET_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */ +#define CTIMER_INTSET_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */ +#define CTIMER_INTSET_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */ +#define CTIMER_INTSET_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */ +#define CTIMER_INTSET_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */ +#define CTIMER_INTSET_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */ +#define CTIMER_INTSET_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */ +#define CTIMER_INTSET_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */ +#define CTIMER_INTSET_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */ +#define CTIMER_INTSET_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */ +#define CTIMER_INTSET_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */ +#define CTIMER_INTSET_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */ +#define CTIMER_INTSET_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */ +#define CTIMER_INTSET_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */ +#define CTIMER_INTSET_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */ +#define CTIMER_INTSET_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */ +#define CTIMER_INTSET_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */ +#define CTIMER_INTSET_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTSET_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTSET_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTSET_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTSET_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTSET_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTSET_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTSET_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTSET_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================= STMINTEN ======================================================== */ +#define CTIMER_STMINTEN_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTEN_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTEN_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTEN_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTEN_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTEN_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTEN_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTEN_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTEN_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTEN_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTEN_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTEN_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTEN_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTEN_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ +/* ====================================================== STMINTSTAT ======================================================= */ +#define CTIMER_STMINTSTAT_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTSTAT_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTSTAT_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTSTAT_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTSTAT_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTSTAT_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTSTAT_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTSTAT_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTSTAT_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTSTAT_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTSTAT_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTSTAT_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTSTAT_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTSTAT_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ +/* ======================================================= STMINTCLR ======================================================= */ +#define CTIMER_STMINTCLR_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTCLR_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTCLR_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTCLR_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTCLR_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTCLR_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTCLR_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTCLR_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTCLR_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTCLR_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTCLR_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTCLR_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTCLR_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTCLR_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ +/* ======================================================= STMINTSET ======================================================= */ +#define CTIMER_STMINTSET_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTSET_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTSET_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTSET_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTSET_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTSET_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTSET_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTSET_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTSET_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTSET_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTSET_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTSET_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTSET_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTSET_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PADREGA ======================================================== */ +#define GPIO_PADREGA_PAD3PWRUP_Pos (30UL) /*!< PAD3PWRUP (Bit 30) */ +#define GPIO_PADREGA_PAD3PWRUP_Msk (0x40000000UL) /*!< PAD3PWRUP (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD3FNCSEL_Pos (27UL) /*!< PAD3FNCSEL (Bit 27) */ +#define GPIO_PADREGA_PAD3FNCSEL_Msk (0x38000000UL) /*!< PAD3FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD3STRNG_Pos (26UL) /*!< PAD3STRNG (Bit 26) */ +#define GPIO_PADREGA_PAD3STRNG_Msk (0x4000000UL) /*!< PAD3STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD3INPEN_Pos (25UL) /*!< PAD3INPEN (Bit 25) */ +#define GPIO_PADREGA_PAD3INPEN_Msk (0x2000000UL) /*!< PAD3INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD3PULL_Pos (24UL) /*!< PAD3PULL (Bit 24) */ +#define GPIO_PADREGA_PAD3PULL_Msk (0x1000000UL) /*!< PAD3PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD2FNCSEL_Pos (19UL) /*!< PAD2FNCSEL (Bit 19) */ +#define GPIO_PADREGA_PAD2FNCSEL_Msk (0x380000UL) /*!< PAD2FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD2STRNG_Pos (18UL) /*!< PAD2STRNG (Bit 18) */ +#define GPIO_PADREGA_PAD2STRNG_Msk (0x40000UL) /*!< PAD2STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD2INPEN_Pos (17UL) /*!< PAD2INPEN (Bit 17) */ +#define GPIO_PADREGA_PAD2INPEN_Msk (0x20000UL) /*!< PAD2INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD2PULL_Pos (16UL) /*!< PAD2PULL (Bit 16) */ +#define GPIO_PADREGA_PAD2PULL_Msk (0x10000UL) /*!< PAD2PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD1RSEL_Pos (14UL) /*!< PAD1RSEL (Bit 14) */ +#define GPIO_PADREGA_PAD1RSEL_Msk (0xc000UL) /*!< PAD1RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGA_PAD1FNCSEL_Pos (11UL) /*!< PAD1FNCSEL (Bit 11) */ +#define GPIO_PADREGA_PAD1FNCSEL_Msk (0x3800UL) /*!< PAD1FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD1STRNG_Pos (10UL) /*!< PAD1STRNG (Bit 10) */ +#define GPIO_PADREGA_PAD1STRNG_Msk (0x400UL) /*!< PAD1STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD1INPEN_Pos (9UL) /*!< PAD1INPEN (Bit 9) */ +#define GPIO_PADREGA_PAD1INPEN_Msk (0x200UL) /*!< PAD1INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD1PULL_Pos (8UL) /*!< PAD1PULL (Bit 8) */ +#define GPIO_PADREGA_PAD1PULL_Msk (0x100UL) /*!< PAD1PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD0RSEL_Pos (6UL) /*!< PAD0RSEL (Bit 6) */ +#define GPIO_PADREGA_PAD0RSEL_Msk (0xc0UL) /*!< PAD0RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGA_PAD0FNCSEL_Pos (3UL) /*!< PAD0FNCSEL (Bit 3) */ +#define GPIO_PADREGA_PAD0FNCSEL_Msk (0x38UL) /*!< PAD0FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD0STRNG_Pos (2UL) /*!< PAD0STRNG (Bit 2) */ +#define GPIO_PADREGA_PAD0STRNG_Msk (0x4UL) /*!< PAD0STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD0INPEN_Pos (1UL) /*!< PAD0INPEN (Bit 1) */ +#define GPIO_PADREGA_PAD0INPEN_Msk (0x2UL) /*!< PAD0INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD0PULL_Pos (0UL) /*!< PAD0PULL (Bit 0) */ +#define GPIO_PADREGA_PAD0PULL_Msk (0x1UL) /*!< PAD0PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGB ======================================================== */ +#define GPIO_PADREGB_PAD7FNCSEL_Pos (27UL) /*!< PAD7FNCSEL (Bit 27) */ +#define GPIO_PADREGB_PAD7FNCSEL_Msk (0x38000000UL) /*!< PAD7FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD7STRNG_Pos (26UL) /*!< PAD7STRNG (Bit 26) */ +#define GPIO_PADREGB_PAD7STRNG_Msk (0x4000000UL) /*!< PAD7STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD7INPEN_Pos (25UL) /*!< PAD7INPEN (Bit 25) */ +#define GPIO_PADREGB_PAD7INPEN_Msk (0x2000000UL) /*!< PAD7INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD7PULL_Pos (24UL) /*!< PAD7PULL (Bit 24) */ +#define GPIO_PADREGB_PAD7PULL_Msk (0x1000000UL) /*!< PAD7PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD6RSEL_Pos (22UL) /*!< PAD6RSEL (Bit 22) */ +#define GPIO_PADREGB_PAD6RSEL_Msk (0xc00000UL) /*!< PAD6RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGB_PAD6FNCSEL_Pos (19UL) /*!< PAD6FNCSEL (Bit 19) */ +#define GPIO_PADREGB_PAD6FNCSEL_Msk (0x380000UL) /*!< PAD6FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD6STRNG_Pos (18UL) /*!< PAD6STRNG (Bit 18) */ +#define GPIO_PADREGB_PAD6STRNG_Msk (0x40000UL) /*!< PAD6STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD6INPEN_Pos (17UL) /*!< PAD6INPEN (Bit 17) */ +#define GPIO_PADREGB_PAD6INPEN_Msk (0x20000UL) /*!< PAD6INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD6PULL_Pos (16UL) /*!< PAD6PULL (Bit 16) */ +#define GPIO_PADREGB_PAD6PULL_Msk (0x10000UL) /*!< PAD6PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD5RSEL_Pos (14UL) /*!< PAD5RSEL (Bit 14) */ +#define GPIO_PADREGB_PAD5RSEL_Msk (0xc000UL) /*!< PAD5RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGB_PAD5FNCSEL_Pos (11UL) /*!< PAD5FNCSEL (Bit 11) */ +#define GPIO_PADREGB_PAD5FNCSEL_Msk (0x3800UL) /*!< PAD5FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD5STRNG_Pos (10UL) /*!< PAD5STRNG (Bit 10) */ +#define GPIO_PADREGB_PAD5STRNG_Msk (0x400UL) /*!< PAD5STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD5INPEN_Pos (9UL) /*!< PAD5INPEN (Bit 9) */ +#define GPIO_PADREGB_PAD5INPEN_Msk (0x200UL) /*!< PAD5INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD5PULL_Pos (8UL) /*!< PAD5PULL (Bit 8) */ +#define GPIO_PADREGB_PAD5PULL_Msk (0x100UL) /*!< PAD5PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD4FNCSEL_Pos (3UL) /*!< PAD4FNCSEL (Bit 3) */ +#define GPIO_PADREGB_PAD4FNCSEL_Msk (0x38UL) /*!< PAD4FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD4STRNG_Pos (2UL) /*!< PAD4STRNG (Bit 2) */ +#define GPIO_PADREGB_PAD4STRNG_Msk (0x4UL) /*!< PAD4STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD4INPEN_Pos (1UL) /*!< PAD4INPEN (Bit 1) */ +#define GPIO_PADREGB_PAD4INPEN_Msk (0x2UL) /*!< PAD4INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD4PULL_Pos (0UL) /*!< PAD4PULL (Bit 0) */ +#define GPIO_PADREGB_PAD4PULL_Msk (0x1UL) /*!< PAD4PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGC ======================================================== */ +#define GPIO_PADREGC_PAD11FNCSEL_Pos (27UL) /*!< PAD11FNCSEL (Bit 27) */ +#define GPIO_PADREGC_PAD11FNCSEL_Msk (0x38000000UL) /*!< PAD11FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD11STRNG_Pos (26UL) /*!< PAD11STRNG (Bit 26) */ +#define GPIO_PADREGC_PAD11STRNG_Msk (0x4000000UL) /*!< PAD11STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD11INPEN_Pos (25UL) /*!< PAD11INPEN (Bit 25) */ +#define GPIO_PADREGC_PAD11INPEN_Msk (0x2000000UL) /*!< PAD11INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD11PULL_Pos (24UL) /*!< PAD11PULL (Bit 24) */ +#define GPIO_PADREGC_PAD11PULL_Msk (0x1000000UL) /*!< PAD11PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD10FNCSEL_Pos (19UL) /*!< PAD10FNCSEL (Bit 19) */ +#define GPIO_PADREGC_PAD10FNCSEL_Msk (0x380000UL) /*!< PAD10FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD10STRNG_Pos (18UL) /*!< PAD10STRNG (Bit 18) */ +#define GPIO_PADREGC_PAD10STRNG_Msk (0x40000UL) /*!< PAD10STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD10INPEN_Pos (17UL) /*!< PAD10INPEN (Bit 17) */ +#define GPIO_PADREGC_PAD10INPEN_Msk (0x20000UL) /*!< PAD10INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD10PULL_Pos (16UL) /*!< PAD10PULL (Bit 16) */ +#define GPIO_PADREGC_PAD10PULL_Msk (0x10000UL) /*!< PAD10PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD9RSEL_Pos (14UL) /*!< PAD9RSEL (Bit 14) */ +#define GPIO_PADREGC_PAD9RSEL_Msk (0xc000UL) /*!< PAD9RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGC_PAD9FNCSEL_Pos (11UL) /*!< PAD9FNCSEL (Bit 11) */ +#define GPIO_PADREGC_PAD9FNCSEL_Msk (0x3800UL) /*!< PAD9FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD9STRNG_Pos (10UL) /*!< PAD9STRNG (Bit 10) */ +#define GPIO_PADREGC_PAD9STRNG_Msk (0x400UL) /*!< PAD9STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD9INPEN_Pos (9UL) /*!< PAD9INPEN (Bit 9) */ +#define GPIO_PADREGC_PAD9INPEN_Msk (0x200UL) /*!< PAD9INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD9PULL_Pos (8UL) /*!< PAD9PULL (Bit 8) */ +#define GPIO_PADREGC_PAD9PULL_Msk (0x100UL) /*!< PAD9PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD8RSEL_Pos (6UL) /*!< PAD8RSEL (Bit 6) */ +#define GPIO_PADREGC_PAD8RSEL_Msk (0xc0UL) /*!< PAD8RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGC_PAD8FNCSEL_Pos (3UL) /*!< PAD8FNCSEL (Bit 3) */ +#define GPIO_PADREGC_PAD8FNCSEL_Msk (0x38UL) /*!< PAD8FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD8STRNG_Pos (2UL) /*!< PAD8STRNG (Bit 2) */ +#define GPIO_PADREGC_PAD8STRNG_Msk (0x4UL) /*!< PAD8STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD8INPEN_Pos (1UL) /*!< PAD8INPEN (Bit 1) */ +#define GPIO_PADREGC_PAD8INPEN_Msk (0x2UL) /*!< PAD8INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD8PULL_Pos (0UL) /*!< PAD8PULL (Bit 0) */ +#define GPIO_PADREGC_PAD8PULL_Msk (0x1UL) /*!< PAD8PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGD ======================================================== */ +#define GPIO_PADREGD_PAD15FNCSEL_Pos (27UL) /*!< PAD15FNCSEL (Bit 27) */ +#define GPIO_PADREGD_PAD15FNCSEL_Msk (0x38000000UL) /*!< PAD15FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD15STRNG_Pos (26UL) /*!< PAD15STRNG (Bit 26) */ +#define GPIO_PADREGD_PAD15STRNG_Msk (0x4000000UL) /*!< PAD15STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD15INPEN_Pos (25UL) /*!< PAD15INPEN (Bit 25) */ +#define GPIO_PADREGD_PAD15INPEN_Msk (0x2000000UL) /*!< PAD15INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD15PULL_Pos (24UL) /*!< PAD15PULL (Bit 24) */ +#define GPIO_PADREGD_PAD15PULL_Msk (0x1000000UL) /*!< PAD15PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD14FNCSEL_Pos (19UL) /*!< PAD14FNCSEL (Bit 19) */ +#define GPIO_PADREGD_PAD14FNCSEL_Msk (0x380000UL) /*!< PAD14FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD14STRNG_Pos (18UL) /*!< PAD14STRNG (Bit 18) */ +#define GPIO_PADREGD_PAD14STRNG_Msk (0x40000UL) /*!< PAD14STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD14INPEN_Pos (17UL) /*!< PAD14INPEN (Bit 17) */ +#define GPIO_PADREGD_PAD14INPEN_Msk (0x20000UL) /*!< PAD14INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD14PULL_Pos (16UL) /*!< PAD14PULL (Bit 16) */ +#define GPIO_PADREGD_PAD14PULL_Msk (0x10000UL) /*!< PAD14PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD13FNCSEL_Pos (11UL) /*!< PAD13FNCSEL (Bit 11) */ +#define GPIO_PADREGD_PAD13FNCSEL_Msk (0x3800UL) /*!< PAD13FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD13STRNG_Pos (10UL) /*!< PAD13STRNG (Bit 10) */ +#define GPIO_PADREGD_PAD13STRNG_Msk (0x400UL) /*!< PAD13STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD13INPEN_Pos (9UL) /*!< PAD13INPEN (Bit 9) */ +#define GPIO_PADREGD_PAD13INPEN_Msk (0x200UL) /*!< PAD13INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD13PULL_Pos (8UL) /*!< PAD13PULL (Bit 8) */ +#define GPIO_PADREGD_PAD13PULL_Msk (0x100UL) /*!< PAD13PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD12FNCSEL_Pos (3UL) /*!< PAD12FNCSEL (Bit 3) */ +#define GPIO_PADREGD_PAD12FNCSEL_Msk (0x38UL) /*!< PAD12FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD12STRNG_Pos (2UL) /*!< PAD12STRNG (Bit 2) */ +#define GPIO_PADREGD_PAD12STRNG_Msk (0x4UL) /*!< PAD12STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD12INPEN_Pos (1UL) /*!< PAD12INPEN (Bit 1) */ +#define GPIO_PADREGD_PAD12INPEN_Msk (0x2UL) /*!< PAD12INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD12PULL_Pos (0UL) /*!< PAD12PULL (Bit 0) */ +#define GPIO_PADREGD_PAD12PULL_Msk (0x1UL) /*!< PAD12PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGE ======================================================== */ +#define GPIO_PADREGE_PAD19FNCSEL_Pos (27UL) /*!< PAD19FNCSEL (Bit 27) */ +#define GPIO_PADREGE_PAD19FNCSEL_Msk (0x38000000UL) /*!< PAD19FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD19STRNG_Pos (26UL) /*!< PAD19STRNG (Bit 26) */ +#define GPIO_PADREGE_PAD19STRNG_Msk (0x4000000UL) /*!< PAD19STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD19INPEN_Pos (25UL) /*!< PAD19INPEN (Bit 25) */ +#define GPIO_PADREGE_PAD19INPEN_Msk (0x2000000UL) /*!< PAD19INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD19PULL_Pos (24UL) /*!< PAD19PULL (Bit 24) */ +#define GPIO_PADREGE_PAD19PULL_Msk (0x1000000UL) /*!< PAD19PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD18FNCSEL_Pos (19UL) /*!< PAD18FNCSEL (Bit 19) */ +#define GPIO_PADREGE_PAD18FNCSEL_Msk (0x380000UL) /*!< PAD18FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD18STRNG_Pos (18UL) /*!< PAD18STRNG (Bit 18) */ +#define GPIO_PADREGE_PAD18STRNG_Msk (0x40000UL) /*!< PAD18STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD18INPEN_Pos (17UL) /*!< PAD18INPEN (Bit 17) */ +#define GPIO_PADREGE_PAD18INPEN_Msk (0x20000UL) /*!< PAD18INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD18PULL_Pos (16UL) /*!< PAD18PULL (Bit 16) */ +#define GPIO_PADREGE_PAD18PULL_Msk (0x10000UL) /*!< PAD18PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD17FNCSEL_Pos (11UL) /*!< PAD17FNCSEL (Bit 11) */ +#define GPIO_PADREGE_PAD17FNCSEL_Msk (0x3800UL) /*!< PAD17FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD17STRNG_Pos (10UL) /*!< PAD17STRNG (Bit 10) */ +#define GPIO_PADREGE_PAD17STRNG_Msk (0x400UL) /*!< PAD17STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD17INPEN_Pos (9UL) /*!< PAD17INPEN (Bit 9) */ +#define GPIO_PADREGE_PAD17INPEN_Msk (0x200UL) /*!< PAD17INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD17PULL_Pos (8UL) /*!< PAD17PULL (Bit 8) */ +#define GPIO_PADREGE_PAD17PULL_Msk (0x100UL) /*!< PAD17PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD16FNCSEL_Pos (3UL) /*!< PAD16FNCSEL (Bit 3) */ +#define GPIO_PADREGE_PAD16FNCSEL_Msk (0x38UL) /*!< PAD16FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD16STRNG_Pos (2UL) /*!< PAD16STRNG (Bit 2) */ +#define GPIO_PADREGE_PAD16STRNG_Msk (0x4UL) /*!< PAD16STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD16INPEN_Pos (1UL) /*!< PAD16INPEN (Bit 1) */ +#define GPIO_PADREGE_PAD16INPEN_Msk (0x2UL) /*!< PAD16INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD16PULL_Pos (0UL) /*!< PAD16PULL (Bit 0) */ +#define GPIO_PADREGE_PAD16PULL_Msk (0x1UL) /*!< PAD16PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGF ======================================================== */ +#define GPIO_PADREGF_PAD23FNCSEL_Pos (27UL) /*!< PAD23FNCSEL (Bit 27) */ +#define GPIO_PADREGF_PAD23FNCSEL_Msk (0x38000000UL) /*!< PAD23FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD23STRNG_Pos (26UL) /*!< PAD23STRNG (Bit 26) */ +#define GPIO_PADREGF_PAD23STRNG_Msk (0x4000000UL) /*!< PAD23STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD23INPEN_Pos (25UL) /*!< PAD23INPEN (Bit 25) */ +#define GPIO_PADREGF_PAD23INPEN_Msk (0x2000000UL) /*!< PAD23INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD23PULL_Pos (24UL) /*!< PAD23PULL (Bit 24) */ +#define GPIO_PADREGF_PAD23PULL_Msk (0x1000000UL) /*!< PAD23PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD22FNCSEL_Pos (19UL) /*!< PAD22FNCSEL (Bit 19) */ +#define GPIO_PADREGF_PAD22FNCSEL_Msk (0x380000UL) /*!< PAD22FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD22STRNG_Pos (18UL) /*!< PAD22STRNG (Bit 18) */ +#define GPIO_PADREGF_PAD22STRNG_Msk (0x40000UL) /*!< PAD22STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD22INPEN_Pos (17UL) /*!< PAD22INPEN (Bit 17) */ +#define GPIO_PADREGF_PAD22INPEN_Msk (0x20000UL) /*!< PAD22INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD22PULL_Pos (16UL) /*!< PAD22PULL (Bit 16) */ +#define GPIO_PADREGF_PAD22PULL_Msk (0x10000UL) /*!< PAD22PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD21FNCSEL_Pos (11UL) /*!< PAD21FNCSEL (Bit 11) */ +#define GPIO_PADREGF_PAD21FNCSEL_Msk (0x3800UL) /*!< PAD21FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD21STRNG_Pos (10UL) /*!< PAD21STRNG (Bit 10) */ +#define GPIO_PADREGF_PAD21STRNG_Msk (0x400UL) /*!< PAD21STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD21INPEN_Pos (9UL) /*!< PAD21INPEN (Bit 9) */ +#define GPIO_PADREGF_PAD21INPEN_Msk (0x200UL) /*!< PAD21INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD21PULL_Pos (8UL) /*!< PAD21PULL (Bit 8) */ +#define GPIO_PADREGF_PAD21PULL_Msk (0x100UL) /*!< PAD21PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD20FNCSEL_Pos (3UL) /*!< PAD20FNCSEL (Bit 3) */ +#define GPIO_PADREGF_PAD20FNCSEL_Msk (0x38UL) /*!< PAD20FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD20STRNG_Pos (2UL) /*!< PAD20STRNG (Bit 2) */ +#define GPIO_PADREGF_PAD20STRNG_Msk (0x4UL) /*!< PAD20STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD20INPEN_Pos (1UL) /*!< PAD20INPEN (Bit 1) */ +#define GPIO_PADREGF_PAD20INPEN_Msk (0x2UL) /*!< PAD20INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD20PULL_Pos (0UL) /*!< PAD20PULL (Bit 0) */ +#define GPIO_PADREGF_PAD20PULL_Msk (0x1UL) /*!< PAD20PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGG ======================================================== */ +#define GPIO_PADREGG_PAD27RSEL_Pos (30UL) /*!< PAD27RSEL (Bit 30) */ +#define GPIO_PADREGG_PAD27RSEL_Msk (0xc0000000UL) /*!< PAD27RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGG_PAD27FNCSEL_Pos (27UL) /*!< PAD27FNCSEL (Bit 27) */ +#define GPIO_PADREGG_PAD27FNCSEL_Msk (0x38000000UL) /*!< PAD27FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD27STRNG_Pos (26UL) /*!< PAD27STRNG (Bit 26) */ +#define GPIO_PADREGG_PAD27STRNG_Msk (0x4000000UL) /*!< PAD27STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD27INPEN_Pos (25UL) /*!< PAD27INPEN (Bit 25) */ +#define GPIO_PADREGG_PAD27INPEN_Msk (0x2000000UL) /*!< PAD27INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD27PULL_Pos (24UL) /*!< PAD27PULL (Bit 24) */ +#define GPIO_PADREGG_PAD27PULL_Msk (0x1000000UL) /*!< PAD27PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD26FNCSEL_Pos (19UL) /*!< PAD26FNCSEL (Bit 19) */ +#define GPIO_PADREGG_PAD26FNCSEL_Msk (0x380000UL) /*!< PAD26FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD26STRNG_Pos (18UL) /*!< PAD26STRNG (Bit 18) */ +#define GPIO_PADREGG_PAD26STRNG_Msk (0x40000UL) /*!< PAD26STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD26INPEN_Pos (17UL) /*!< PAD26INPEN (Bit 17) */ +#define GPIO_PADREGG_PAD26INPEN_Msk (0x20000UL) /*!< PAD26INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD26PULL_Pos (16UL) /*!< PAD26PULL (Bit 16) */ +#define GPIO_PADREGG_PAD26PULL_Msk (0x10000UL) /*!< PAD26PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD25RSEL_Pos (14UL) /*!< PAD25RSEL (Bit 14) */ +#define GPIO_PADREGG_PAD25RSEL_Msk (0xc000UL) /*!< PAD25RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGG_PAD25FNCSEL_Pos (11UL) /*!< PAD25FNCSEL (Bit 11) */ +#define GPIO_PADREGG_PAD25FNCSEL_Msk (0x3800UL) /*!< PAD25FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD25STRNG_Pos (10UL) /*!< PAD25STRNG (Bit 10) */ +#define GPIO_PADREGG_PAD25STRNG_Msk (0x400UL) /*!< PAD25STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD25INPEN_Pos (9UL) /*!< PAD25INPEN (Bit 9) */ +#define GPIO_PADREGG_PAD25INPEN_Msk (0x200UL) /*!< PAD25INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD25PULL_Pos (8UL) /*!< PAD25PULL (Bit 8) */ +#define GPIO_PADREGG_PAD25PULL_Msk (0x100UL) /*!< PAD25PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD24FNCSEL_Pos (3UL) /*!< PAD24FNCSEL (Bit 3) */ +#define GPIO_PADREGG_PAD24FNCSEL_Msk (0x38UL) /*!< PAD24FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD24STRNG_Pos (2UL) /*!< PAD24STRNG (Bit 2) */ +#define GPIO_PADREGG_PAD24STRNG_Msk (0x4UL) /*!< PAD24STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD24INPEN_Pos (1UL) /*!< PAD24INPEN (Bit 1) */ +#define GPIO_PADREGG_PAD24INPEN_Msk (0x2UL) /*!< PAD24INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD24PULL_Pos (0UL) /*!< PAD24PULL (Bit 0) */ +#define GPIO_PADREGG_PAD24PULL_Msk (0x1UL) /*!< PAD24PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGH ======================================================== */ +#define GPIO_PADREGH_PAD31FNCSEL_Pos (27UL) /*!< PAD31FNCSEL (Bit 27) */ +#define GPIO_PADREGH_PAD31FNCSEL_Msk (0x38000000UL) /*!< PAD31FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD31STRNG_Pos (26UL) /*!< PAD31STRNG (Bit 26) */ +#define GPIO_PADREGH_PAD31STRNG_Msk (0x4000000UL) /*!< PAD31STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD31INPEN_Pos (25UL) /*!< PAD31INPEN (Bit 25) */ +#define GPIO_PADREGH_PAD31INPEN_Msk (0x2000000UL) /*!< PAD31INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD31PULL_Pos (24UL) /*!< PAD31PULL (Bit 24) */ +#define GPIO_PADREGH_PAD31PULL_Msk (0x1000000UL) /*!< PAD31PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD30FNCSEL_Pos (19UL) /*!< PAD30FNCSEL (Bit 19) */ +#define GPIO_PADREGH_PAD30FNCSEL_Msk (0x380000UL) /*!< PAD30FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD30STRNG_Pos (18UL) /*!< PAD30STRNG (Bit 18) */ +#define GPIO_PADREGH_PAD30STRNG_Msk (0x40000UL) /*!< PAD30STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD30INPEN_Pos (17UL) /*!< PAD30INPEN (Bit 17) */ +#define GPIO_PADREGH_PAD30INPEN_Msk (0x20000UL) /*!< PAD30INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD30PULL_Pos (16UL) /*!< PAD30PULL (Bit 16) */ +#define GPIO_PADREGH_PAD30PULL_Msk (0x10000UL) /*!< PAD30PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD29FNCSEL_Pos (11UL) /*!< PAD29FNCSEL (Bit 11) */ +#define GPIO_PADREGH_PAD29FNCSEL_Msk (0x3800UL) /*!< PAD29FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD29STRNG_Pos (10UL) /*!< PAD29STRNG (Bit 10) */ +#define GPIO_PADREGH_PAD29STRNG_Msk (0x400UL) /*!< PAD29STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD29INPEN_Pos (9UL) /*!< PAD29INPEN (Bit 9) */ +#define GPIO_PADREGH_PAD29INPEN_Msk (0x200UL) /*!< PAD29INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD29PULL_Pos (8UL) /*!< PAD29PULL (Bit 8) */ +#define GPIO_PADREGH_PAD29PULL_Msk (0x100UL) /*!< PAD29PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD28FNCSEL_Pos (3UL) /*!< PAD28FNCSEL (Bit 3) */ +#define GPIO_PADREGH_PAD28FNCSEL_Msk (0x38UL) /*!< PAD28FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD28STRNG_Pos (2UL) /*!< PAD28STRNG (Bit 2) */ +#define GPIO_PADREGH_PAD28STRNG_Msk (0x4UL) /*!< PAD28STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD28INPEN_Pos (1UL) /*!< PAD28INPEN (Bit 1) */ +#define GPIO_PADREGH_PAD28INPEN_Msk (0x2UL) /*!< PAD28INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD28PULL_Pos (0UL) /*!< PAD28PULL (Bit 0) */ +#define GPIO_PADREGH_PAD28PULL_Msk (0x1UL) /*!< PAD28PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGI ======================================================== */ +#define GPIO_PADREGI_PAD35FNCSEL_Pos (27UL) /*!< PAD35FNCSEL (Bit 27) */ +#define GPIO_PADREGI_PAD35FNCSEL_Msk (0x38000000UL) /*!< PAD35FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD35STRNG_Pos (26UL) /*!< PAD35STRNG (Bit 26) */ +#define GPIO_PADREGI_PAD35STRNG_Msk (0x4000000UL) /*!< PAD35STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD35INPEN_Pos (25UL) /*!< PAD35INPEN (Bit 25) */ +#define GPIO_PADREGI_PAD35INPEN_Msk (0x2000000UL) /*!< PAD35INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD35PULL_Pos (24UL) /*!< PAD35PULL (Bit 24) */ +#define GPIO_PADREGI_PAD35PULL_Msk (0x1000000UL) /*!< PAD35PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD34FNCSEL_Pos (19UL) /*!< PAD34FNCSEL (Bit 19) */ +#define GPIO_PADREGI_PAD34FNCSEL_Msk (0x380000UL) /*!< PAD34FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD34STRNG_Pos (18UL) /*!< PAD34STRNG (Bit 18) */ +#define GPIO_PADREGI_PAD34STRNG_Msk (0x40000UL) /*!< PAD34STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD34INPEN_Pos (17UL) /*!< PAD34INPEN (Bit 17) */ +#define GPIO_PADREGI_PAD34INPEN_Msk (0x20000UL) /*!< PAD34INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD34PULL_Pos (16UL) /*!< PAD34PULL (Bit 16) */ +#define GPIO_PADREGI_PAD34PULL_Msk (0x10000UL) /*!< PAD34PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD33FNCSEL_Pos (11UL) /*!< PAD33FNCSEL (Bit 11) */ +#define GPIO_PADREGI_PAD33FNCSEL_Msk (0x3800UL) /*!< PAD33FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD33STRNG_Pos (10UL) /*!< PAD33STRNG (Bit 10) */ +#define GPIO_PADREGI_PAD33STRNG_Msk (0x400UL) /*!< PAD33STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD33INPEN_Pos (9UL) /*!< PAD33INPEN (Bit 9) */ +#define GPIO_PADREGI_PAD33INPEN_Msk (0x200UL) /*!< PAD33INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD33PULL_Pos (8UL) /*!< PAD33PULL (Bit 8) */ +#define GPIO_PADREGI_PAD33PULL_Msk (0x100UL) /*!< PAD33PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD32FNCSEL_Pos (3UL) /*!< PAD32FNCSEL (Bit 3) */ +#define GPIO_PADREGI_PAD32FNCSEL_Msk (0x38UL) /*!< PAD32FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD32STRNG_Pos (2UL) /*!< PAD32STRNG (Bit 2) */ +#define GPIO_PADREGI_PAD32STRNG_Msk (0x4UL) /*!< PAD32STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD32INPEN_Pos (1UL) /*!< PAD32INPEN (Bit 1) */ +#define GPIO_PADREGI_PAD32INPEN_Msk (0x2UL) /*!< PAD32INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD32PULL_Pos (0UL) /*!< PAD32PULL (Bit 0) */ +#define GPIO_PADREGI_PAD32PULL_Msk (0x1UL) /*!< PAD32PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGJ ======================================================== */ +#define GPIO_PADREGJ_PAD39RSEL_Pos (30UL) /*!< PAD39RSEL (Bit 30) */ +#define GPIO_PADREGJ_PAD39RSEL_Msk (0xc0000000UL) /*!< PAD39RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGJ_PAD39FNCSEL_Pos (27UL) /*!< PAD39FNCSEL (Bit 27) */ +#define GPIO_PADREGJ_PAD39FNCSEL_Msk (0x38000000UL) /*!< PAD39FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD39STRNG_Pos (26UL) /*!< PAD39STRNG (Bit 26) */ +#define GPIO_PADREGJ_PAD39STRNG_Msk (0x4000000UL) /*!< PAD39STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD39INPEN_Pos (25UL) /*!< PAD39INPEN (Bit 25) */ +#define GPIO_PADREGJ_PAD39INPEN_Msk (0x2000000UL) /*!< PAD39INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD39PULL_Pos (24UL) /*!< PAD39PULL (Bit 24) */ +#define GPIO_PADREGJ_PAD39PULL_Msk (0x1000000UL) /*!< PAD39PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD38FNCSEL_Pos (19UL) /*!< PAD38FNCSEL (Bit 19) */ +#define GPIO_PADREGJ_PAD38FNCSEL_Msk (0x380000UL) /*!< PAD38FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD38STRNG_Pos (18UL) /*!< PAD38STRNG (Bit 18) */ +#define GPIO_PADREGJ_PAD38STRNG_Msk (0x40000UL) /*!< PAD38STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD38INPEN_Pos (17UL) /*!< PAD38INPEN (Bit 17) */ +#define GPIO_PADREGJ_PAD38INPEN_Msk (0x20000UL) /*!< PAD38INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD38PULL_Pos (16UL) /*!< PAD38PULL (Bit 16) */ +#define GPIO_PADREGJ_PAD38PULL_Msk (0x10000UL) /*!< PAD38PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37PWRDN_Pos (15UL) /*!< PAD37PWRDN (Bit 15) */ +#define GPIO_PADREGJ_PAD37PWRDN_Msk (0x8000UL) /*!< PAD37PWRDN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37FNCSEL_Pos (11UL) /*!< PAD37FNCSEL (Bit 11) */ +#define GPIO_PADREGJ_PAD37FNCSEL_Msk (0x3800UL) /*!< PAD37FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD37STRNG_Pos (10UL) /*!< PAD37STRNG (Bit 10) */ +#define GPIO_PADREGJ_PAD37STRNG_Msk (0x400UL) /*!< PAD37STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37INPEN_Pos (9UL) /*!< PAD37INPEN (Bit 9) */ +#define GPIO_PADREGJ_PAD37INPEN_Msk (0x200UL) /*!< PAD37INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37PULL_Pos (8UL) /*!< PAD37PULL (Bit 8) */ +#define GPIO_PADREGJ_PAD37PULL_Msk (0x100UL) /*!< PAD37PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36PWRUP_Pos (6UL) /*!< PAD36PWRUP (Bit 6) */ +#define GPIO_PADREGJ_PAD36PWRUP_Msk (0x40UL) /*!< PAD36PWRUP (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36FNCSEL_Pos (3UL) /*!< PAD36FNCSEL (Bit 3) */ +#define GPIO_PADREGJ_PAD36FNCSEL_Msk (0x38UL) /*!< PAD36FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD36STRNG_Pos (2UL) /*!< PAD36STRNG (Bit 2) */ +#define GPIO_PADREGJ_PAD36STRNG_Msk (0x4UL) /*!< PAD36STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36INPEN_Pos (1UL) /*!< PAD36INPEN (Bit 1) */ +#define GPIO_PADREGJ_PAD36INPEN_Msk (0x2UL) /*!< PAD36INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36PULL_Pos (0UL) /*!< PAD36PULL (Bit 0) */ +#define GPIO_PADREGJ_PAD36PULL_Msk (0x1UL) /*!< PAD36PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGK ======================================================== */ +#define GPIO_PADREGK_PAD43RSEL_Pos (30UL) /*!< PAD43RSEL (Bit 30) */ +#define GPIO_PADREGK_PAD43RSEL_Msk (0xc0000000UL) /*!< PAD43RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGK_PAD43FNCSEL_Pos (27UL) /*!< PAD43FNCSEL (Bit 27) */ +#define GPIO_PADREGK_PAD43FNCSEL_Msk (0x38000000UL) /*!< PAD43FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD43STRNG_Pos (26UL) /*!< PAD43STRNG (Bit 26) */ +#define GPIO_PADREGK_PAD43STRNG_Msk (0x4000000UL) /*!< PAD43STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD43INPEN_Pos (25UL) /*!< PAD43INPEN (Bit 25) */ +#define GPIO_PADREGK_PAD43INPEN_Msk (0x2000000UL) /*!< PAD43INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD43PULL_Pos (24UL) /*!< PAD43PULL (Bit 24) */ +#define GPIO_PADREGK_PAD43PULL_Msk (0x1000000UL) /*!< PAD43PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD42RSEL_Pos (22UL) /*!< PAD42RSEL (Bit 22) */ +#define GPIO_PADREGK_PAD42RSEL_Msk (0xc00000UL) /*!< PAD42RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGK_PAD42FNCSEL_Pos (19UL) /*!< PAD42FNCSEL (Bit 19) */ +#define GPIO_PADREGK_PAD42FNCSEL_Msk (0x380000UL) /*!< PAD42FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD42STRNG_Pos (18UL) /*!< PAD42STRNG (Bit 18) */ +#define GPIO_PADREGK_PAD42STRNG_Msk (0x40000UL) /*!< PAD42STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD42INPEN_Pos (17UL) /*!< PAD42INPEN (Bit 17) */ +#define GPIO_PADREGK_PAD42INPEN_Msk (0x20000UL) /*!< PAD42INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD42PULL_Pos (16UL) /*!< PAD42PULL (Bit 16) */ +#define GPIO_PADREGK_PAD42PULL_Msk (0x10000UL) /*!< PAD42PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41PWRDN_Pos (15UL) /*!< PAD41PWRDN (Bit 15) */ +#define GPIO_PADREGK_PAD41PWRDN_Msk (0x8000UL) /*!< PAD41PWRDN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41FNCSEL_Pos (11UL) /*!< PAD41FNCSEL (Bit 11) */ +#define GPIO_PADREGK_PAD41FNCSEL_Msk (0x3800UL) /*!< PAD41FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD41STRNG_Pos (10UL) /*!< PAD41STRNG (Bit 10) */ +#define GPIO_PADREGK_PAD41STRNG_Msk (0x400UL) /*!< PAD41STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41INPEN_Pos (9UL) /*!< PAD41INPEN (Bit 9) */ +#define GPIO_PADREGK_PAD41INPEN_Msk (0x200UL) /*!< PAD41INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41PULL_Pos (8UL) /*!< PAD41PULL (Bit 8) */ +#define GPIO_PADREGK_PAD41PULL_Msk (0x100UL) /*!< PAD41PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD40RSEL_Pos (6UL) /*!< PAD40RSEL (Bit 6) */ +#define GPIO_PADREGK_PAD40RSEL_Msk (0xc0UL) /*!< PAD40RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGK_PAD40FNCSEL_Pos (3UL) /*!< PAD40FNCSEL (Bit 3) */ +#define GPIO_PADREGK_PAD40FNCSEL_Msk (0x38UL) /*!< PAD40FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD40STRNG_Pos (2UL) /*!< PAD40STRNG (Bit 2) */ +#define GPIO_PADREGK_PAD40STRNG_Msk (0x4UL) /*!< PAD40STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD40INPEN_Pos (1UL) /*!< PAD40INPEN (Bit 1) */ +#define GPIO_PADREGK_PAD40INPEN_Msk (0x2UL) /*!< PAD40INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD40PULL_Pos (0UL) /*!< PAD40PULL (Bit 0) */ +#define GPIO_PADREGK_PAD40PULL_Msk (0x1UL) /*!< PAD40PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGL ======================================================== */ +#define GPIO_PADREGL_PAD47FNCSEL_Pos (27UL) /*!< PAD47FNCSEL (Bit 27) */ +#define GPIO_PADREGL_PAD47FNCSEL_Msk (0x38000000UL) /*!< PAD47FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD47STRNG_Pos (26UL) /*!< PAD47STRNG (Bit 26) */ +#define GPIO_PADREGL_PAD47STRNG_Msk (0x4000000UL) /*!< PAD47STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD47INPEN_Pos (25UL) /*!< PAD47INPEN (Bit 25) */ +#define GPIO_PADREGL_PAD47INPEN_Msk (0x2000000UL) /*!< PAD47INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD47PULL_Pos (24UL) /*!< PAD47PULL (Bit 24) */ +#define GPIO_PADREGL_PAD47PULL_Msk (0x1000000UL) /*!< PAD47PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD46FNCSEL_Pos (19UL) /*!< PAD46FNCSEL (Bit 19) */ +#define GPIO_PADREGL_PAD46FNCSEL_Msk (0x380000UL) /*!< PAD46FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD46STRNG_Pos (18UL) /*!< PAD46STRNG (Bit 18) */ +#define GPIO_PADREGL_PAD46STRNG_Msk (0x40000UL) /*!< PAD46STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD46INPEN_Pos (17UL) /*!< PAD46INPEN (Bit 17) */ +#define GPIO_PADREGL_PAD46INPEN_Msk (0x20000UL) /*!< PAD46INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD46PULL_Pos (16UL) /*!< PAD46PULL (Bit 16) */ +#define GPIO_PADREGL_PAD46PULL_Msk (0x10000UL) /*!< PAD46PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD45FNCSEL_Pos (11UL) /*!< PAD45FNCSEL (Bit 11) */ +#define GPIO_PADREGL_PAD45FNCSEL_Msk (0x3800UL) /*!< PAD45FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD45STRNG_Pos (10UL) /*!< PAD45STRNG (Bit 10) */ +#define GPIO_PADREGL_PAD45STRNG_Msk (0x400UL) /*!< PAD45STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD45INPEN_Pos (9UL) /*!< PAD45INPEN (Bit 9) */ +#define GPIO_PADREGL_PAD45INPEN_Msk (0x200UL) /*!< PAD45INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD45PULL_Pos (8UL) /*!< PAD45PULL (Bit 8) */ +#define GPIO_PADREGL_PAD45PULL_Msk (0x100UL) /*!< PAD45PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD44FNCSEL_Pos (3UL) /*!< PAD44FNCSEL (Bit 3) */ +#define GPIO_PADREGL_PAD44FNCSEL_Msk (0x38UL) /*!< PAD44FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD44STRNG_Pos (2UL) /*!< PAD44STRNG (Bit 2) */ +#define GPIO_PADREGL_PAD44STRNG_Msk (0x4UL) /*!< PAD44STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD44INPEN_Pos (1UL) /*!< PAD44INPEN (Bit 1) */ +#define GPIO_PADREGL_PAD44INPEN_Msk (0x2UL) /*!< PAD44INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD44PULL_Pos (0UL) /*!< PAD44PULL (Bit 0) */ +#define GPIO_PADREGL_PAD44PULL_Msk (0x1UL) /*!< PAD44PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGM ======================================================== */ +#define GPIO_PADREGM_PAD49RSEL_Pos (14UL) /*!< PAD49RSEL (Bit 14) */ +#define GPIO_PADREGM_PAD49RSEL_Msk (0xc000UL) /*!< PAD49RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGM_PAD49FNCSEL_Pos (11UL) /*!< PAD49FNCSEL (Bit 11) */ +#define GPIO_PADREGM_PAD49FNCSEL_Msk (0x3800UL) /*!< PAD49FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGM_PAD49STRNG_Pos (10UL) /*!< PAD49STRNG (Bit 10) */ +#define GPIO_PADREGM_PAD49STRNG_Msk (0x400UL) /*!< PAD49STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD49INPEN_Pos (9UL) /*!< PAD49INPEN (Bit 9) */ +#define GPIO_PADREGM_PAD49INPEN_Msk (0x200UL) /*!< PAD49INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD49PULL_Pos (8UL) /*!< PAD49PULL (Bit 8) */ +#define GPIO_PADREGM_PAD49PULL_Msk (0x100UL) /*!< PAD49PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD48RSEL_Pos (6UL) /*!< PAD48RSEL (Bit 6) */ +#define GPIO_PADREGM_PAD48RSEL_Msk (0xc0UL) /*!< PAD48RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGM_PAD48FNCSEL_Pos (3UL) /*!< PAD48FNCSEL (Bit 3) */ +#define GPIO_PADREGM_PAD48FNCSEL_Msk (0x38UL) /*!< PAD48FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGM_PAD48STRNG_Pos (2UL) /*!< PAD48STRNG (Bit 2) */ +#define GPIO_PADREGM_PAD48STRNG_Msk (0x4UL) /*!< PAD48STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD48INPEN_Pos (1UL) /*!< PAD48INPEN (Bit 1) */ +#define GPIO_PADREGM_PAD48INPEN_Msk (0x2UL) /*!< PAD48INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD48PULL_Pos (0UL) /*!< PAD48PULL (Bit 0) */ +#define GPIO_PADREGM_PAD48PULL_Msk (0x1UL) /*!< PAD48PULL (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGA ========================================================== */ +#define GPIO_CFGA_GPIO7INTD_Pos (31UL) /*!< GPIO7INTD (Bit 31) */ +#define GPIO_CFGA_GPIO7INTD_Msk (0x80000000UL) /*!< GPIO7INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO7OUTCFG_Pos (29UL) /*!< GPIO7OUTCFG (Bit 29) */ +#define GPIO_CFGA_GPIO7OUTCFG_Msk (0x60000000UL) /*!< GPIO7OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO7INCFG_Pos (28UL) /*!< GPIO7INCFG (Bit 28) */ +#define GPIO_CFGA_GPIO7INCFG_Msk (0x10000000UL) /*!< GPIO7INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO6INTD_Pos (27UL) /*!< GPIO6INTD (Bit 27) */ +#define GPIO_CFGA_GPIO6INTD_Msk (0x8000000UL) /*!< GPIO6INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO6OUTCFG_Pos (25UL) /*!< GPIO6OUTCFG (Bit 25) */ +#define GPIO_CFGA_GPIO6OUTCFG_Msk (0x6000000UL) /*!< GPIO6OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO6INCFG_Pos (24UL) /*!< GPIO6INCFG (Bit 24) */ +#define GPIO_CFGA_GPIO6INCFG_Msk (0x1000000UL) /*!< GPIO6INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO5INTD_Pos (23UL) /*!< GPIO5INTD (Bit 23) */ +#define GPIO_CFGA_GPIO5INTD_Msk (0x800000UL) /*!< GPIO5INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO5OUTCFG_Pos (21UL) /*!< GPIO5OUTCFG (Bit 21) */ +#define GPIO_CFGA_GPIO5OUTCFG_Msk (0x600000UL) /*!< GPIO5OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO5INCFG_Pos (20UL) /*!< GPIO5INCFG (Bit 20) */ +#define GPIO_CFGA_GPIO5INCFG_Msk (0x100000UL) /*!< GPIO5INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO4INTD_Pos (19UL) /*!< GPIO4INTD (Bit 19) */ +#define GPIO_CFGA_GPIO4INTD_Msk (0x80000UL) /*!< GPIO4INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO4OUTCFG_Pos (17UL) /*!< GPIO4OUTCFG (Bit 17) */ +#define GPIO_CFGA_GPIO4OUTCFG_Msk (0x60000UL) /*!< GPIO4OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO4INCFG_Pos (16UL) /*!< GPIO4INCFG (Bit 16) */ +#define GPIO_CFGA_GPIO4INCFG_Msk (0x10000UL) /*!< GPIO4INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO3INTD_Pos (15UL) /*!< GPIO3INTD (Bit 15) */ +#define GPIO_CFGA_GPIO3INTD_Msk (0x8000UL) /*!< GPIO3INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO3OUTCFG_Pos (13UL) /*!< GPIO3OUTCFG (Bit 13) */ +#define GPIO_CFGA_GPIO3OUTCFG_Msk (0x6000UL) /*!< GPIO3OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO3INCFG_Pos (12UL) /*!< GPIO3INCFG (Bit 12) */ +#define GPIO_CFGA_GPIO3INCFG_Msk (0x1000UL) /*!< GPIO3INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO2INTD_Pos (11UL) /*!< GPIO2INTD (Bit 11) */ +#define GPIO_CFGA_GPIO2INTD_Msk (0x800UL) /*!< GPIO2INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO2OUTCFG_Pos (9UL) /*!< GPIO2OUTCFG (Bit 9) */ +#define GPIO_CFGA_GPIO2OUTCFG_Msk (0x600UL) /*!< GPIO2OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO2INCFG_Pos (8UL) /*!< GPIO2INCFG (Bit 8) */ +#define GPIO_CFGA_GPIO2INCFG_Msk (0x100UL) /*!< GPIO2INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO1INTD_Pos (7UL) /*!< GPIO1INTD (Bit 7) */ +#define GPIO_CFGA_GPIO1INTD_Msk (0x80UL) /*!< GPIO1INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO1OUTCFG_Pos (5UL) /*!< GPIO1OUTCFG (Bit 5) */ +#define GPIO_CFGA_GPIO1OUTCFG_Msk (0x60UL) /*!< GPIO1OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO1INCFG_Pos (4UL) /*!< GPIO1INCFG (Bit 4) */ +#define GPIO_CFGA_GPIO1INCFG_Msk (0x10UL) /*!< GPIO1INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO0INTD_Pos (3UL) /*!< GPIO0INTD (Bit 3) */ +#define GPIO_CFGA_GPIO0INTD_Msk (0x8UL) /*!< GPIO0INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO0OUTCFG_Pos (1UL) /*!< GPIO0OUTCFG (Bit 1) */ +#define GPIO_CFGA_GPIO0OUTCFG_Msk (0x6UL) /*!< GPIO0OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO0INCFG_Pos (0UL) /*!< GPIO0INCFG (Bit 0) */ +#define GPIO_CFGA_GPIO0INCFG_Msk (0x1UL) /*!< GPIO0INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGB ========================================================== */ +#define GPIO_CFGB_GPIO15INTD_Pos (31UL) /*!< GPIO15INTD (Bit 31) */ +#define GPIO_CFGB_GPIO15INTD_Msk (0x80000000UL) /*!< GPIO15INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO15OUTCFG_Pos (29UL) /*!< GPIO15OUTCFG (Bit 29) */ +#define GPIO_CFGB_GPIO15OUTCFG_Msk (0x60000000UL) /*!< GPIO15OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO15INCFG_Pos (28UL) /*!< GPIO15INCFG (Bit 28) */ +#define GPIO_CFGB_GPIO15INCFG_Msk (0x10000000UL) /*!< GPIO15INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO14INTD_Pos (27UL) /*!< GPIO14INTD (Bit 27) */ +#define GPIO_CFGB_GPIO14INTD_Msk (0x8000000UL) /*!< GPIO14INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO14OUTCFG_Pos (25UL) /*!< GPIO14OUTCFG (Bit 25) */ +#define GPIO_CFGB_GPIO14OUTCFG_Msk (0x6000000UL) /*!< GPIO14OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO14INCFG_Pos (24UL) /*!< GPIO14INCFG (Bit 24) */ +#define GPIO_CFGB_GPIO14INCFG_Msk (0x1000000UL) /*!< GPIO14INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO13INTD_Pos (23UL) /*!< GPIO13INTD (Bit 23) */ +#define GPIO_CFGB_GPIO13INTD_Msk (0x800000UL) /*!< GPIO13INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO13OUTCFG_Pos (21UL) /*!< GPIO13OUTCFG (Bit 21) */ +#define GPIO_CFGB_GPIO13OUTCFG_Msk (0x600000UL) /*!< GPIO13OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO13INCFG_Pos (20UL) /*!< GPIO13INCFG (Bit 20) */ +#define GPIO_CFGB_GPIO13INCFG_Msk (0x100000UL) /*!< GPIO13INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO12INTD_Pos (19UL) /*!< GPIO12INTD (Bit 19) */ +#define GPIO_CFGB_GPIO12INTD_Msk (0x80000UL) /*!< GPIO12INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO12OUTCFG_Pos (17UL) /*!< GPIO12OUTCFG (Bit 17) */ +#define GPIO_CFGB_GPIO12OUTCFG_Msk (0x60000UL) /*!< GPIO12OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO12INCFG_Pos (16UL) /*!< GPIO12INCFG (Bit 16) */ +#define GPIO_CFGB_GPIO12INCFG_Msk (0x10000UL) /*!< GPIO12INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO11INTD_Pos (15UL) /*!< GPIO11INTD (Bit 15) */ +#define GPIO_CFGB_GPIO11INTD_Msk (0x8000UL) /*!< GPIO11INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO11OUTCFG_Pos (13UL) /*!< GPIO11OUTCFG (Bit 13) */ +#define GPIO_CFGB_GPIO11OUTCFG_Msk (0x6000UL) /*!< GPIO11OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO11INCFG_Pos (12UL) /*!< GPIO11INCFG (Bit 12) */ +#define GPIO_CFGB_GPIO11INCFG_Msk (0x1000UL) /*!< GPIO11INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO10INTD_Pos (11UL) /*!< GPIO10INTD (Bit 11) */ +#define GPIO_CFGB_GPIO10INTD_Msk (0x800UL) /*!< GPIO10INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO10OUTCFG_Pos (9UL) /*!< GPIO10OUTCFG (Bit 9) */ +#define GPIO_CFGB_GPIO10OUTCFG_Msk (0x600UL) /*!< GPIO10OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO10INCFG_Pos (8UL) /*!< GPIO10INCFG (Bit 8) */ +#define GPIO_CFGB_GPIO10INCFG_Msk (0x100UL) /*!< GPIO10INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO9INTD_Pos (7UL) /*!< GPIO9INTD (Bit 7) */ +#define GPIO_CFGB_GPIO9INTD_Msk (0x80UL) /*!< GPIO9INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO9OUTCFG_Pos (5UL) /*!< GPIO9OUTCFG (Bit 5) */ +#define GPIO_CFGB_GPIO9OUTCFG_Msk (0x60UL) /*!< GPIO9OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO9INCFG_Pos (4UL) /*!< GPIO9INCFG (Bit 4) */ +#define GPIO_CFGB_GPIO9INCFG_Msk (0x10UL) /*!< GPIO9INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO8INTD_Pos (3UL) /*!< GPIO8INTD (Bit 3) */ +#define GPIO_CFGB_GPIO8INTD_Msk (0x8UL) /*!< GPIO8INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO8OUTCFG_Pos (1UL) /*!< GPIO8OUTCFG (Bit 1) */ +#define GPIO_CFGB_GPIO8OUTCFG_Msk (0x6UL) /*!< GPIO8OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO8INCFG_Pos (0UL) /*!< GPIO8INCFG (Bit 0) */ +#define GPIO_CFGB_GPIO8INCFG_Msk (0x1UL) /*!< GPIO8INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGC ========================================================== */ +#define GPIO_CFGC_GPIO23INTD_Pos (31UL) /*!< GPIO23INTD (Bit 31) */ +#define GPIO_CFGC_GPIO23INTD_Msk (0x80000000UL) /*!< GPIO23INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO23OUTCFG_Pos (29UL) /*!< GPIO23OUTCFG (Bit 29) */ +#define GPIO_CFGC_GPIO23OUTCFG_Msk (0x60000000UL) /*!< GPIO23OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO23INCFG_Pos (28UL) /*!< GPIO23INCFG (Bit 28) */ +#define GPIO_CFGC_GPIO23INCFG_Msk (0x10000000UL) /*!< GPIO23INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO22INTD_Pos (27UL) /*!< GPIO22INTD (Bit 27) */ +#define GPIO_CFGC_GPIO22INTD_Msk (0x8000000UL) /*!< GPIO22INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO22OUTCFG_Pos (25UL) /*!< GPIO22OUTCFG (Bit 25) */ +#define GPIO_CFGC_GPIO22OUTCFG_Msk (0x6000000UL) /*!< GPIO22OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO22INCFG_Pos (24UL) /*!< GPIO22INCFG (Bit 24) */ +#define GPIO_CFGC_GPIO22INCFG_Msk (0x1000000UL) /*!< GPIO22INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO21INTD_Pos (23UL) /*!< GPIO21INTD (Bit 23) */ +#define GPIO_CFGC_GPIO21INTD_Msk (0x800000UL) /*!< GPIO21INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO21OUTCFG_Pos (21UL) /*!< GPIO21OUTCFG (Bit 21) */ +#define GPIO_CFGC_GPIO21OUTCFG_Msk (0x600000UL) /*!< GPIO21OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO21INCFG_Pos (20UL) /*!< GPIO21INCFG (Bit 20) */ +#define GPIO_CFGC_GPIO21INCFG_Msk (0x100000UL) /*!< GPIO21INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO20INTD_Pos (19UL) /*!< GPIO20INTD (Bit 19) */ +#define GPIO_CFGC_GPIO20INTD_Msk (0x80000UL) /*!< GPIO20INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO20OUTCFG_Pos (17UL) /*!< GPIO20OUTCFG (Bit 17) */ +#define GPIO_CFGC_GPIO20OUTCFG_Msk (0x60000UL) /*!< GPIO20OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO20INCFG_Pos (16UL) /*!< GPIO20INCFG (Bit 16) */ +#define GPIO_CFGC_GPIO20INCFG_Msk (0x10000UL) /*!< GPIO20INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO19INTD_Pos (15UL) /*!< GPIO19INTD (Bit 15) */ +#define GPIO_CFGC_GPIO19INTD_Msk (0x8000UL) /*!< GPIO19INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO19OUTCFG_Pos (13UL) /*!< GPIO19OUTCFG (Bit 13) */ +#define GPIO_CFGC_GPIO19OUTCFG_Msk (0x6000UL) /*!< GPIO19OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO19INCFG_Pos (12UL) /*!< GPIO19INCFG (Bit 12) */ +#define GPIO_CFGC_GPIO19INCFG_Msk (0x1000UL) /*!< GPIO19INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO18INTD_Pos (11UL) /*!< GPIO18INTD (Bit 11) */ +#define GPIO_CFGC_GPIO18INTD_Msk (0x800UL) /*!< GPIO18INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO18OUTCFG_Pos (9UL) /*!< GPIO18OUTCFG (Bit 9) */ +#define GPIO_CFGC_GPIO18OUTCFG_Msk (0x600UL) /*!< GPIO18OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO18INCFG_Pos (8UL) /*!< GPIO18INCFG (Bit 8) */ +#define GPIO_CFGC_GPIO18INCFG_Msk (0x100UL) /*!< GPIO18INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO17INTD_Pos (7UL) /*!< GPIO17INTD (Bit 7) */ +#define GPIO_CFGC_GPIO17INTD_Msk (0x80UL) /*!< GPIO17INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO17OUTCFG_Pos (5UL) /*!< GPIO17OUTCFG (Bit 5) */ +#define GPIO_CFGC_GPIO17OUTCFG_Msk (0x60UL) /*!< GPIO17OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO17INCFG_Pos (4UL) /*!< GPIO17INCFG (Bit 4) */ +#define GPIO_CFGC_GPIO17INCFG_Msk (0x10UL) /*!< GPIO17INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO16INTD_Pos (3UL) /*!< GPIO16INTD (Bit 3) */ +#define GPIO_CFGC_GPIO16INTD_Msk (0x8UL) /*!< GPIO16INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO16OUTCFG_Pos (1UL) /*!< GPIO16OUTCFG (Bit 1) */ +#define GPIO_CFGC_GPIO16OUTCFG_Msk (0x6UL) /*!< GPIO16OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO16INCFG_Pos (0UL) /*!< GPIO16INCFG (Bit 0) */ +#define GPIO_CFGC_GPIO16INCFG_Msk (0x1UL) /*!< GPIO16INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGD ========================================================== */ +#define GPIO_CFGD_GPIO31INTD_Pos (31UL) /*!< GPIO31INTD (Bit 31) */ +#define GPIO_CFGD_GPIO31INTD_Msk (0x80000000UL) /*!< GPIO31INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO31OUTCFG_Pos (29UL) /*!< GPIO31OUTCFG (Bit 29) */ +#define GPIO_CFGD_GPIO31OUTCFG_Msk (0x60000000UL) /*!< GPIO31OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO31INCFG_Pos (28UL) /*!< GPIO31INCFG (Bit 28) */ +#define GPIO_CFGD_GPIO31INCFG_Msk (0x10000000UL) /*!< GPIO31INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO30INTD_Pos (27UL) /*!< GPIO30INTD (Bit 27) */ +#define GPIO_CFGD_GPIO30INTD_Msk (0x8000000UL) /*!< GPIO30INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO30OUTCFG_Pos (25UL) /*!< GPIO30OUTCFG (Bit 25) */ +#define GPIO_CFGD_GPIO30OUTCFG_Msk (0x6000000UL) /*!< GPIO30OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO30INCFG_Pos (24UL) /*!< GPIO30INCFG (Bit 24) */ +#define GPIO_CFGD_GPIO30INCFG_Msk (0x1000000UL) /*!< GPIO30INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO29INTD_Pos (23UL) /*!< GPIO29INTD (Bit 23) */ +#define GPIO_CFGD_GPIO29INTD_Msk (0x800000UL) /*!< GPIO29INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO29OUTCFG_Pos (21UL) /*!< GPIO29OUTCFG (Bit 21) */ +#define GPIO_CFGD_GPIO29OUTCFG_Msk (0x600000UL) /*!< GPIO29OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO29INCFG_Pos (20UL) /*!< GPIO29INCFG (Bit 20) */ +#define GPIO_CFGD_GPIO29INCFG_Msk (0x100000UL) /*!< GPIO29INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO28INTD_Pos (19UL) /*!< GPIO28INTD (Bit 19) */ +#define GPIO_CFGD_GPIO28INTD_Msk (0x80000UL) /*!< GPIO28INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO28OUTCFG_Pos (17UL) /*!< GPIO28OUTCFG (Bit 17) */ +#define GPIO_CFGD_GPIO28OUTCFG_Msk (0x60000UL) /*!< GPIO28OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO28INCFG_Pos (16UL) /*!< GPIO28INCFG (Bit 16) */ +#define GPIO_CFGD_GPIO28INCFG_Msk (0x10000UL) /*!< GPIO28INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO27INTD_Pos (15UL) /*!< GPIO27INTD (Bit 15) */ +#define GPIO_CFGD_GPIO27INTD_Msk (0x8000UL) /*!< GPIO27INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO27OUTCFG_Pos (13UL) /*!< GPIO27OUTCFG (Bit 13) */ +#define GPIO_CFGD_GPIO27OUTCFG_Msk (0x6000UL) /*!< GPIO27OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO27INCFG_Pos (12UL) /*!< GPIO27INCFG (Bit 12) */ +#define GPIO_CFGD_GPIO27INCFG_Msk (0x1000UL) /*!< GPIO27INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO26INTD_Pos (11UL) /*!< GPIO26INTD (Bit 11) */ +#define GPIO_CFGD_GPIO26INTD_Msk (0x800UL) /*!< GPIO26INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO26OUTCFG_Pos (9UL) /*!< GPIO26OUTCFG (Bit 9) */ +#define GPIO_CFGD_GPIO26OUTCFG_Msk (0x600UL) /*!< GPIO26OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO26INCFG_Pos (8UL) /*!< GPIO26INCFG (Bit 8) */ +#define GPIO_CFGD_GPIO26INCFG_Msk (0x100UL) /*!< GPIO26INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO25INTD_Pos (7UL) /*!< GPIO25INTD (Bit 7) */ +#define GPIO_CFGD_GPIO25INTD_Msk (0x80UL) /*!< GPIO25INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO25OUTCFG_Pos (5UL) /*!< GPIO25OUTCFG (Bit 5) */ +#define GPIO_CFGD_GPIO25OUTCFG_Msk (0x60UL) /*!< GPIO25OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO25INCFG_Pos (4UL) /*!< GPIO25INCFG (Bit 4) */ +#define GPIO_CFGD_GPIO25INCFG_Msk (0x10UL) /*!< GPIO25INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO24INTD_Pos (3UL) /*!< GPIO24INTD (Bit 3) */ +#define GPIO_CFGD_GPIO24INTD_Msk (0x8UL) /*!< GPIO24INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO24OUTCFG_Pos (1UL) /*!< GPIO24OUTCFG (Bit 1) */ +#define GPIO_CFGD_GPIO24OUTCFG_Msk (0x6UL) /*!< GPIO24OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO24INCFG_Pos (0UL) /*!< GPIO24INCFG (Bit 0) */ +#define GPIO_CFGD_GPIO24INCFG_Msk (0x1UL) /*!< GPIO24INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGE ========================================================== */ +#define GPIO_CFGE_GPIO39INTD_Pos (31UL) /*!< GPIO39INTD (Bit 31) */ +#define GPIO_CFGE_GPIO39INTD_Msk (0x80000000UL) /*!< GPIO39INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO39OUTCFG_Pos (29UL) /*!< GPIO39OUTCFG (Bit 29) */ +#define GPIO_CFGE_GPIO39OUTCFG_Msk (0x60000000UL) /*!< GPIO39OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO39INCFG_Pos (28UL) /*!< GPIO39INCFG (Bit 28) */ +#define GPIO_CFGE_GPIO39INCFG_Msk (0x10000000UL) /*!< GPIO39INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO38INTD_Pos (27UL) /*!< GPIO38INTD (Bit 27) */ +#define GPIO_CFGE_GPIO38INTD_Msk (0x8000000UL) /*!< GPIO38INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO38OUTCFG_Pos (25UL) /*!< GPIO38OUTCFG (Bit 25) */ +#define GPIO_CFGE_GPIO38OUTCFG_Msk (0x6000000UL) /*!< GPIO38OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO38INCFG_Pos (24UL) /*!< GPIO38INCFG (Bit 24) */ +#define GPIO_CFGE_GPIO38INCFG_Msk (0x1000000UL) /*!< GPIO38INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO37INTD_Pos (23UL) /*!< GPIO37INTD (Bit 23) */ +#define GPIO_CFGE_GPIO37INTD_Msk (0x800000UL) /*!< GPIO37INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO37OUTCFG_Pos (21UL) /*!< GPIO37OUTCFG (Bit 21) */ +#define GPIO_CFGE_GPIO37OUTCFG_Msk (0x600000UL) /*!< GPIO37OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO37INCFG_Pos (20UL) /*!< GPIO37INCFG (Bit 20) */ +#define GPIO_CFGE_GPIO37INCFG_Msk (0x100000UL) /*!< GPIO37INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO36INTD_Pos (19UL) /*!< GPIO36INTD (Bit 19) */ +#define GPIO_CFGE_GPIO36INTD_Msk (0x80000UL) /*!< GPIO36INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO36OUTCFG_Pos (17UL) /*!< GPIO36OUTCFG (Bit 17) */ +#define GPIO_CFGE_GPIO36OUTCFG_Msk (0x60000UL) /*!< GPIO36OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO36INCFG_Pos (16UL) /*!< GPIO36INCFG (Bit 16) */ +#define GPIO_CFGE_GPIO36INCFG_Msk (0x10000UL) /*!< GPIO36INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO35INTD_Pos (15UL) /*!< GPIO35INTD (Bit 15) */ +#define GPIO_CFGE_GPIO35INTD_Msk (0x8000UL) /*!< GPIO35INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO35OUTCFG_Pos (13UL) /*!< GPIO35OUTCFG (Bit 13) */ +#define GPIO_CFGE_GPIO35OUTCFG_Msk (0x6000UL) /*!< GPIO35OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO35INCFG_Pos (12UL) /*!< GPIO35INCFG (Bit 12) */ +#define GPIO_CFGE_GPIO35INCFG_Msk (0x1000UL) /*!< GPIO35INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO34INTD_Pos (11UL) /*!< GPIO34INTD (Bit 11) */ +#define GPIO_CFGE_GPIO34INTD_Msk (0x800UL) /*!< GPIO34INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO34OUTCFG_Pos (9UL) /*!< GPIO34OUTCFG (Bit 9) */ +#define GPIO_CFGE_GPIO34OUTCFG_Msk (0x600UL) /*!< GPIO34OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO34INCFG_Pos (8UL) /*!< GPIO34INCFG (Bit 8) */ +#define GPIO_CFGE_GPIO34INCFG_Msk (0x100UL) /*!< GPIO34INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO33INTD_Pos (7UL) /*!< GPIO33INTD (Bit 7) */ +#define GPIO_CFGE_GPIO33INTD_Msk (0x80UL) /*!< GPIO33INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO33OUTCFG_Pos (5UL) /*!< GPIO33OUTCFG (Bit 5) */ +#define GPIO_CFGE_GPIO33OUTCFG_Msk (0x60UL) /*!< GPIO33OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO33INCFG_Pos (4UL) /*!< GPIO33INCFG (Bit 4) */ +#define GPIO_CFGE_GPIO33INCFG_Msk (0x10UL) /*!< GPIO33INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO32INTD_Pos (3UL) /*!< GPIO32INTD (Bit 3) */ +#define GPIO_CFGE_GPIO32INTD_Msk (0x8UL) /*!< GPIO32INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO32OUTCFG_Pos (1UL) /*!< GPIO32OUTCFG (Bit 1) */ +#define GPIO_CFGE_GPIO32OUTCFG_Msk (0x6UL) /*!< GPIO32OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO32INCFG_Pos (0UL) /*!< GPIO32INCFG (Bit 0) */ +#define GPIO_CFGE_GPIO32INCFG_Msk (0x1UL) /*!< GPIO32INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGF ========================================================== */ +#define GPIO_CFGF_GPIO47INTD_Pos (31UL) /*!< GPIO47INTD (Bit 31) */ +#define GPIO_CFGF_GPIO47INTD_Msk (0x80000000UL) /*!< GPIO47INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO47OUTCFG_Pos (29UL) /*!< GPIO47OUTCFG (Bit 29) */ +#define GPIO_CFGF_GPIO47OUTCFG_Msk (0x60000000UL) /*!< GPIO47OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO47INCFG_Pos (28UL) /*!< GPIO47INCFG (Bit 28) */ +#define GPIO_CFGF_GPIO47INCFG_Msk (0x10000000UL) /*!< GPIO47INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO46INTD_Pos (27UL) /*!< GPIO46INTD (Bit 27) */ +#define GPIO_CFGF_GPIO46INTD_Msk (0x8000000UL) /*!< GPIO46INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO46OUTCFG_Pos (25UL) /*!< GPIO46OUTCFG (Bit 25) */ +#define GPIO_CFGF_GPIO46OUTCFG_Msk (0x6000000UL) /*!< GPIO46OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO46INCFG_Pos (24UL) /*!< GPIO46INCFG (Bit 24) */ +#define GPIO_CFGF_GPIO46INCFG_Msk (0x1000000UL) /*!< GPIO46INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO45INTD_Pos (23UL) /*!< GPIO45INTD (Bit 23) */ +#define GPIO_CFGF_GPIO45INTD_Msk (0x800000UL) /*!< GPIO45INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO45OUTCFG_Pos (21UL) /*!< GPIO45OUTCFG (Bit 21) */ +#define GPIO_CFGF_GPIO45OUTCFG_Msk (0x600000UL) /*!< GPIO45OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO45INCFG_Pos (20UL) /*!< GPIO45INCFG (Bit 20) */ +#define GPIO_CFGF_GPIO45INCFG_Msk (0x100000UL) /*!< GPIO45INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO44INTD_Pos (19UL) /*!< GPIO44INTD (Bit 19) */ +#define GPIO_CFGF_GPIO44INTD_Msk (0x80000UL) /*!< GPIO44INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO44OUTCFG_Pos (17UL) /*!< GPIO44OUTCFG (Bit 17) */ +#define GPIO_CFGF_GPIO44OUTCFG_Msk (0x60000UL) /*!< GPIO44OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO44INCFG_Pos (16UL) /*!< GPIO44INCFG (Bit 16) */ +#define GPIO_CFGF_GPIO44INCFG_Msk (0x10000UL) /*!< GPIO44INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO43INTD_Pos (15UL) /*!< GPIO43INTD (Bit 15) */ +#define GPIO_CFGF_GPIO43INTD_Msk (0x8000UL) /*!< GPIO43INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO43OUTCFG_Pos (13UL) /*!< GPIO43OUTCFG (Bit 13) */ +#define GPIO_CFGF_GPIO43OUTCFG_Msk (0x6000UL) /*!< GPIO43OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO43INCFG_Pos (12UL) /*!< GPIO43INCFG (Bit 12) */ +#define GPIO_CFGF_GPIO43INCFG_Msk (0x1000UL) /*!< GPIO43INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO42INTD_Pos (11UL) /*!< GPIO42INTD (Bit 11) */ +#define GPIO_CFGF_GPIO42INTD_Msk (0x800UL) /*!< GPIO42INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO42OUTCFG_Pos (9UL) /*!< GPIO42OUTCFG (Bit 9) */ +#define GPIO_CFGF_GPIO42OUTCFG_Msk (0x600UL) /*!< GPIO42OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO42INCFG_Pos (8UL) /*!< GPIO42INCFG (Bit 8) */ +#define GPIO_CFGF_GPIO42INCFG_Msk (0x100UL) /*!< GPIO42INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO41INTD_Pos (7UL) /*!< GPIO41INTD (Bit 7) */ +#define GPIO_CFGF_GPIO41INTD_Msk (0x80UL) /*!< GPIO41INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO41OUTCFG_Pos (5UL) /*!< GPIO41OUTCFG (Bit 5) */ +#define GPIO_CFGF_GPIO41OUTCFG_Msk (0x60UL) /*!< GPIO41OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO41INCFG_Pos (4UL) /*!< GPIO41INCFG (Bit 4) */ +#define GPIO_CFGF_GPIO41INCFG_Msk (0x10UL) /*!< GPIO41INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO40INTD_Pos (3UL) /*!< GPIO40INTD (Bit 3) */ +#define GPIO_CFGF_GPIO40INTD_Msk (0x8UL) /*!< GPIO40INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO40OUTCFG_Pos (1UL) /*!< GPIO40OUTCFG (Bit 1) */ +#define GPIO_CFGF_GPIO40OUTCFG_Msk (0x6UL) /*!< GPIO40OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO40INCFG_Pos (0UL) /*!< GPIO40INCFG (Bit 0) */ +#define GPIO_CFGF_GPIO40INCFG_Msk (0x1UL) /*!< GPIO40INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGG ========================================================== */ +#define GPIO_CFGG_GPIO49INTD_Pos (7UL) /*!< GPIO49INTD (Bit 7) */ +#define GPIO_CFGG_GPIO49INTD_Msk (0x80UL) /*!< GPIO49INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGG_GPIO49OUTCFG_Pos (5UL) /*!< GPIO49OUTCFG (Bit 5) */ +#define GPIO_CFGG_GPIO49OUTCFG_Msk (0x60UL) /*!< GPIO49OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGG_GPIO49INCFG_Pos (4UL) /*!< GPIO49INCFG (Bit 4) */ +#define GPIO_CFGG_GPIO49INCFG_Msk (0x10UL) /*!< GPIO49INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGG_GPIO48INTD_Pos (3UL) /*!< GPIO48INTD (Bit 3) */ +#define GPIO_CFGG_GPIO48INTD_Msk (0x8UL) /*!< GPIO48INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGG_GPIO48OUTCFG_Pos (1UL) /*!< GPIO48OUTCFG (Bit 1) */ +#define GPIO_CFGG_GPIO48OUTCFG_Msk (0x6UL) /*!< GPIO48OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGG_GPIO48INCFG_Pos (0UL) /*!< GPIO48INCFG (Bit 0) */ +#define GPIO_CFGG_GPIO48INCFG_Msk (0x1UL) /*!< GPIO48INCFG (Bitfield-Mask: 0x01) */ +/* ======================================================== PADKEY ========================================================= */ +#define GPIO_PADKEY_PADKEY_Pos (0UL) /*!< PADKEY (Bit 0) */ +#define GPIO_PADKEY_PADKEY_Msk (0xffffffffUL) /*!< PADKEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RDA ========================================================== */ +#define GPIO_RDA_RDA_Pos (0UL) /*!< RDA (Bit 0) */ +#define GPIO_RDA_RDA_Msk (0xffffffffUL) /*!< RDA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RDB ========================================================== */ +#define GPIO_RDB_RDB_Pos (0UL) /*!< RDB (Bit 0) */ +#define GPIO_RDB_RDB_Msk (0x3ffffUL) /*!< RDB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== WTA ========================================================== */ +#define GPIO_WTA_WTA_Pos (0UL) /*!< WTA (Bit 0) */ +#define GPIO_WTA_WTA_Msk (0xffffffffUL) /*!< WTA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== WTB ========================================================== */ +#define GPIO_WTB_WTB_Pos (0UL) /*!< WTB (Bit 0) */ +#define GPIO_WTB_WTB_Msk (0x3ffffUL) /*!< WTB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= WTSA ========================================================== */ +#define GPIO_WTSA_WTSA_Pos (0UL) /*!< WTSA (Bit 0) */ +#define GPIO_WTSA_WTSA_Msk (0xffffffffUL) /*!< WTSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= WTSB ========================================================== */ +#define GPIO_WTSB_WTSB_Pos (0UL) /*!< WTSB (Bit 0) */ +#define GPIO_WTSB_WTSB_Msk (0x3ffffUL) /*!< WTSB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= WTCA ========================================================== */ +#define GPIO_WTCA_WTCA_Pos (0UL) /*!< WTCA (Bit 0) */ +#define GPIO_WTCA_WTCA_Msk (0xffffffffUL) /*!< WTCA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= WTCB ========================================================== */ +#define GPIO_WTCB_WTCB_Pos (0UL) /*!< WTCB (Bit 0) */ +#define GPIO_WTCB_WTCB_Msk (0x3ffffUL) /*!< WTCB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== ENA ========================================================== */ +#define GPIO_ENA_ENA_Pos (0UL) /*!< ENA (Bit 0) */ +#define GPIO_ENA_ENA_Msk (0xffffffffUL) /*!< ENA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== ENB ========================================================== */ +#define GPIO_ENB_ENB_Pos (0UL) /*!< ENB (Bit 0) */ +#define GPIO_ENB_ENB_Msk (0x3ffffUL) /*!< ENB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= ENSA ========================================================== */ +#define GPIO_ENSA_ENSA_Pos (0UL) /*!< ENSA (Bit 0) */ +#define GPIO_ENSA_ENSA_Msk (0xffffffffUL) /*!< ENSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ENSB ========================================================== */ +#define GPIO_ENSB_ENSB_Pos (0UL) /*!< ENSB (Bit 0) */ +#define GPIO_ENSB_ENSB_Msk (0x3ffffUL) /*!< ENSB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= ENCA ========================================================== */ +#define GPIO_ENCA_ENCA_Pos (0UL) /*!< ENCA (Bit 0) */ +#define GPIO_ENCA_ENCA_Msk (0xffffffffUL) /*!< ENCA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ENCB ========================================================== */ +#define GPIO_ENCB_ENCB_Pos (0UL) /*!< ENCB (Bit 0) */ +#define GPIO_ENCB_ENCB_Msk (0x3ffffUL) /*!< ENCB (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== STMRCAP ======================================================== */ +#define GPIO_STMRCAP_STPOL3_Pos (30UL) /*!< STPOL3 (Bit 30) */ +#define GPIO_STMRCAP_STPOL3_Msk (0x40000000UL) /*!< STPOL3 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL3_Pos (24UL) /*!< STSEL3 (Bit 24) */ +#define GPIO_STMRCAP_STSEL3_Msk (0x3f000000UL) /*!< STSEL3 (Bitfield-Mask: 0x3f) */ +#define GPIO_STMRCAP_STPOL2_Pos (22UL) /*!< STPOL2 (Bit 22) */ +#define GPIO_STMRCAP_STPOL2_Msk (0x400000UL) /*!< STPOL2 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL2_Pos (16UL) /*!< STSEL2 (Bit 16) */ +#define GPIO_STMRCAP_STSEL2_Msk (0x3f0000UL) /*!< STSEL2 (Bitfield-Mask: 0x3f) */ +#define GPIO_STMRCAP_STPOL1_Pos (14UL) /*!< STPOL1 (Bit 14) */ +#define GPIO_STMRCAP_STPOL1_Msk (0x4000UL) /*!< STPOL1 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL1_Pos (8UL) /*!< STSEL1 (Bit 8) */ +#define GPIO_STMRCAP_STSEL1_Msk (0x3f00UL) /*!< STSEL1 (Bitfield-Mask: 0x3f) */ +#define GPIO_STMRCAP_STPOL0_Pos (6UL) /*!< STPOL0 (Bit 6) */ +#define GPIO_STMRCAP_STPOL0_Msk (0x40UL) /*!< STPOL0 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL0_Pos (0UL) /*!< STSEL0 (Bit 0) */ +#define GPIO_STMRCAP_STSEL0_Msk (0x3fUL) /*!< STSEL0 (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM0IRQ ======================================================== */ +#define GPIO_IOM0IRQ_IOM0IRQ_Pos (0UL) /*!< IOM0IRQ (Bit 0) */ +#define GPIO_IOM0IRQ_IOM0IRQ_Msk (0x3fUL) /*!< IOM0IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM1IRQ ======================================================== */ +#define GPIO_IOM1IRQ_IOM1IRQ_Pos (0UL) /*!< IOM1IRQ (Bit 0) */ +#define GPIO_IOM1IRQ_IOM1IRQ_Msk (0x3fUL) /*!< IOM1IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM2IRQ ======================================================== */ +#define GPIO_IOM2IRQ_IOM2IRQ_Pos (0UL) /*!< IOM2IRQ (Bit 0) */ +#define GPIO_IOM2IRQ_IOM2IRQ_Msk (0x3fUL) /*!< IOM2IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM3IRQ ======================================================== */ +#define GPIO_IOM3IRQ_IOM3IRQ_Pos (0UL) /*!< IOM3IRQ (Bit 0) */ +#define GPIO_IOM3IRQ_IOM3IRQ_Msk (0x3fUL) /*!< IOM3IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM4IRQ ======================================================== */ +#define GPIO_IOM4IRQ_IOM4IRQ_Pos (0UL) /*!< IOM4IRQ (Bit 0) */ +#define GPIO_IOM4IRQ_IOM4IRQ_Msk (0x3fUL) /*!< IOM4IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM5IRQ ======================================================== */ +#define GPIO_IOM5IRQ_IOM5IRQ_Pos (0UL) /*!< IOM5IRQ (Bit 0) */ +#define GPIO_IOM5IRQ_IOM5IRQ_Msk (0x3fUL) /*!< IOM5IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================= BLEIFIRQ ======================================================== */ +#define GPIO_BLEIFIRQ_BLEIFIRQ_Pos (0UL) /*!< BLEIFIRQ (Bit 0) */ +#define GPIO_BLEIFIRQ_BLEIFIRQ_Msk (0x3fUL) /*!< BLEIFIRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== GPIOOBS ======================================================== */ +#define GPIO_GPIOOBS_OBS_DATA_Pos (0UL) /*!< OBS_DATA (Bit 0) */ +#define GPIO_GPIOOBS_OBS_DATA_Msk (0xffffUL) /*!< OBS_DATA (Bitfield-Mask: 0xffff) */ +/* ====================================================== ALTPADCFGA ======================================================= */ +#define GPIO_ALTPADCFGA_PAD3_SR_Pos (28UL) /*!< PAD3_SR (Bit 28) */ +#define GPIO_ALTPADCFGA_PAD3_SR_Msk (0x10000000UL) /*!< PAD3_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD3_DS1_Pos (24UL) /*!< PAD3_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGA_PAD3_DS1_Msk (0x1000000UL) /*!< PAD3_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD2_SR_Pos (20UL) /*!< PAD2_SR (Bit 20) */ +#define GPIO_ALTPADCFGA_PAD2_SR_Msk (0x100000UL) /*!< PAD2_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD2_DS1_Pos (16UL) /*!< PAD2_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGA_PAD2_DS1_Msk (0x10000UL) /*!< PAD2_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD1_SR_Pos (12UL) /*!< PAD1_SR (Bit 12) */ +#define GPIO_ALTPADCFGA_PAD1_SR_Msk (0x1000UL) /*!< PAD1_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD1_DS1_Pos (8UL) /*!< PAD1_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGA_PAD1_DS1_Msk (0x100UL) /*!< PAD1_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD0_SR_Pos (4UL) /*!< PAD0_SR (Bit 4) */ +#define GPIO_ALTPADCFGA_PAD0_SR_Msk (0x10UL) /*!< PAD0_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD0_DS1_Pos (0UL) /*!< PAD0_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGA_PAD0_DS1_Msk (0x1UL) /*!< PAD0_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGB ======================================================= */ +#define GPIO_ALTPADCFGB_PAD7_SR_Pos (28UL) /*!< PAD7_SR (Bit 28) */ +#define GPIO_ALTPADCFGB_PAD7_SR_Msk (0x10000000UL) /*!< PAD7_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD7_DS1_Pos (24UL) /*!< PAD7_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGB_PAD7_DS1_Msk (0x1000000UL) /*!< PAD7_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD6_SR_Pos (20UL) /*!< PAD6_SR (Bit 20) */ +#define GPIO_ALTPADCFGB_PAD6_SR_Msk (0x100000UL) /*!< PAD6_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD6_DS1_Pos (16UL) /*!< PAD6_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGB_PAD6_DS1_Msk (0x10000UL) /*!< PAD6_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD5_SR_Pos (12UL) /*!< PAD5_SR (Bit 12) */ +#define GPIO_ALTPADCFGB_PAD5_SR_Msk (0x1000UL) /*!< PAD5_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD5_DS1_Pos (8UL) /*!< PAD5_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGB_PAD5_DS1_Msk (0x100UL) /*!< PAD5_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD4_SR_Pos (4UL) /*!< PAD4_SR (Bit 4) */ +#define GPIO_ALTPADCFGB_PAD4_SR_Msk (0x10UL) /*!< PAD4_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD4_DS1_Pos (0UL) /*!< PAD4_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGB_PAD4_DS1_Msk (0x1UL) /*!< PAD4_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGC ======================================================= */ +#define GPIO_ALTPADCFGC_PAD11_SR_Pos (28UL) /*!< PAD11_SR (Bit 28) */ +#define GPIO_ALTPADCFGC_PAD11_SR_Msk (0x10000000UL) /*!< PAD11_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD11_DS1_Pos (24UL) /*!< PAD11_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGC_PAD11_DS1_Msk (0x1000000UL) /*!< PAD11_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD10_SR_Pos (20UL) /*!< PAD10_SR (Bit 20) */ +#define GPIO_ALTPADCFGC_PAD10_SR_Msk (0x100000UL) /*!< PAD10_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD10_DS1_Pos (16UL) /*!< PAD10_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGC_PAD10_DS1_Msk (0x10000UL) /*!< PAD10_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD9_SR_Pos (12UL) /*!< PAD9_SR (Bit 12) */ +#define GPIO_ALTPADCFGC_PAD9_SR_Msk (0x1000UL) /*!< PAD9_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD9_DS1_Pos (8UL) /*!< PAD9_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGC_PAD9_DS1_Msk (0x100UL) /*!< PAD9_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD8_SR_Pos (4UL) /*!< PAD8_SR (Bit 4) */ +#define GPIO_ALTPADCFGC_PAD8_SR_Msk (0x10UL) /*!< PAD8_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD8_DS1_Pos (0UL) /*!< PAD8_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGC_PAD8_DS1_Msk (0x1UL) /*!< PAD8_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGD ======================================================= */ +#define GPIO_ALTPADCFGD_PAD15_SR_Pos (28UL) /*!< PAD15_SR (Bit 28) */ +#define GPIO_ALTPADCFGD_PAD15_SR_Msk (0x10000000UL) /*!< PAD15_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD15_DS1_Pos (24UL) /*!< PAD15_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGD_PAD15_DS1_Msk (0x1000000UL) /*!< PAD15_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD14_SR_Pos (20UL) /*!< PAD14_SR (Bit 20) */ +#define GPIO_ALTPADCFGD_PAD14_SR_Msk (0x100000UL) /*!< PAD14_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD14_DS1_Pos (16UL) /*!< PAD14_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGD_PAD14_DS1_Msk (0x10000UL) /*!< PAD14_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD13_SR_Pos (12UL) /*!< PAD13_SR (Bit 12) */ +#define GPIO_ALTPADCFGD_PAD13_SR_Msk (0x1000UL) /*!< PAD13_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD13_DS1_Pos (8UL) /*!< PAD13_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGD_PAD13_DS1_Msk (0x100UL) /*!< PAD13_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD12_SR_Pos (4UL) /*!< PAD12_SR (Bit 4) */ +#define GPIO_ALTPADCFGD_PAD12_SR_Msk (0x10UL) /*!< PAD12_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD12_DS1_Pos (0UL) /*!< PAD12_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGD_PAD12_DS1_Msk (0x1UL) /*!< PAD12_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGE ======================================================= */ +#define GPIO_ALTPADCFGE_PAD19_SR_Pos (28UL) /*!< PAD19_SR (Bit 28) */ +#define GPIO_ALTPADCFGE_PAD19_SR_Msk (0x10000000UL) /*!< PAD19_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD19_DS1_Pos (24UL) /*!< PAD19_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGE_PAD19_DS1_Msk (0x1000000UL) /*!< PAD19_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD18_SR_Pos (20UL) /*!< PAD18_SR (Bit 20) */ +#define GPIO_ALTPADCFGE_PAD18_SR_Msk (0x100000UL) /*!< PAD18_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD18_DS1_Pos (16UL) /*!< PAD18_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGE_PAD18_DS1_Msk (0x10000UL) /*!< PAD18_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD17_SR_Pos (12UL) /*!< PAD17_SR (Bit 12) */ +#define GPIO_ALTPADCFGE_PAD17_SR_Msk (0x1000UL) /*!< PAD17_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD17_DS1_Pos (8UL) /*!< PAD17_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGE_PAD17_DS1_Msk (0x100UL) /*!< PAD17_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD16_SR_Pos (4UL) /*!< PAD16_SR (Bit 4) */ +#define GPIO_ALTPADCFGE_PAD16_SR_Msk (0x10UL) /*!< PAD16_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD16_DS1_Pos (0UL) /*!< PAD16_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGE_PAD16_DS1_Msk (0x1UL) /*!< PAD16_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGF ======================================================= */ +#define GPIO_ALTPADCFGF_PAD23_SR_Pos (28UL) /*!< PAD23_SR (Bit 28) */ +#define GPIO_ALTPADCFGF_PAD23_SR_Msk (0x10000000UL) /*!< PAD23_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD23_DS1_Pos (24UL) /*!< PAD23_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGF_PAD23_DS1_Msk (0x1000000UL) /*!< PAD23_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD22_SR_Pos (20UL) /*!< PAD22_SR (Bit 20) */ +#define GPIO_ALTPADCFGF_PAD22_SR_Msk (0x100000UL) /*!< PAD22_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD22_DS1_Pos (16UL) /*!< PAD22_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGF_PAD22_DS1_Msk (0x10000UL) /*!< PAD22_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD21_SR_Pos (12UL) /*!< PAD21_SR (Bit 12) */ +#define GPIO_ALTPADCFGF_PAD21_SR_Msk (0x1000UL) /*!< PAD21_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD21_DS1_Pos (8UL) /*!< PAD21_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGF_PAD21_DS1_Msk (0x100UL) /*!< PAD21_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD20_SR_Pos (4UL) /*!< PAD20_SR (Bit 4) */ +#define GPIO_ALTPADCFGF_PAD20_SR_Msk (0x10UL) /*!< PAD20_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD20_DS1_Pos (0UL) /*!< PAD20_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGF_PAD20_DS1_Msk (0x1UL) /*!< PAD20_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGG ======================================================= */ +#define GPIO_ALTPADCFGG_PAD27_SR_Pos (28UL) /*!< PAD27_SR (Bit 28) */ +#define GPIO_ALTPADCFGG_PAD27_SR_Msk (0x10000000UL) /*!< PAD27_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD27_DS1_Pos (24UL) /*!< PAD27_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGG_PAD27_DS1_Msk (0x1000000UL) /*!< PAD27_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD26_SR_Pos (20UL) /*!< PAD26_SR (Bit 20) */ +#define GPIO_ALTPADCFGG_PAD26_SR_Msk (0x100000UL) /*!< PAD26_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD26_DS1_Pos (16UL) /*!< PAD26_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGG_PAD26_DS1_Msk (0x10000UL) /*!< PAD26_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD25_SR_Pos (12UL) /*!< PAD25_SR (Bit 12) */ +#define GPIO_ALTPADCFGG_PAD25_SR_Msk (0x1000UL) /*!< PAD25_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD25_DS1_Pos (8UL) /*!< PAD25_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGG_PAD25_DS1_Msk (0x100UL) /*!< PAD25_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD24_SR_Pos (4UL) /*!< PAD24_SR (Bit 4) */ +#define GPIO_ALTPADCFGG_PAD24_SR_Msk (0x10UL) /*!< PAD24_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD24_DS1_Pos (0UL) /*!< PAD24_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGG_PAD24_DS1_Msk (0x1UL) /*!< PAD24_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGH ======================================================= */ +#define GPIO_ALTPADCFGH_PAD31_SR_Pos (28UL) /*!< PAD31_SR (Bit 28) */ +#define GPIO_ALTPADCFGH_PAD31_SR_Msk (0x10000000UL) /*!< PAD31_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD31_DS1_Pos (24UL) /*!< PAD31_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGH_PAD31_DS1_Msk (0x1000000UL) /*!< PAD31_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD30_SR_Pos (20UL) /*!< PAD30_SR (Bit 20) */ +#define GPIO_ALTPADCFGH_PAD30_SR_Msk (0x100000UL) /*!< PAD30_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD30_DS1_Pos (16UL) /*!< PAD30_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGH_PAD30_DS1_Msk (0x10000UL) /*!< PAD30_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD29_SR_Pos (12UL) /*!< PAD29_SR (Bit 12) */ +#define GPIO_ALTPADCFGH_PAD29_SR_Msk (0x1000UL) /*!< PAD29_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD29_DS1_Pos (8UL) /*!< PAD29_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGH_PAD29_DS1_Msk (0x100UL) /*!< PAD29_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD28_SR_Pos (4UL) /*!< PAD28_SR (Bit 4) */ +#define GPIO_ALTPADCFGH_PAD28_SR_Msk (0x10UL) /*!< PAD28_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD28_DS1_Pos (0UL) /*!< PAD28_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGH_PAD28_DS1_Msk (0x1UL) /*!< PAD28_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGI ======================================================= */ +#define GPIO_ALTPADCFGI_PAD35_SR_Pos (28UL) /*!< PAD35_SR (Bit 28) */ +#define GPIO_ALTPADCFGI_PAD35_SR_Msk (0x10000000UL) /*!< PAD35_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD35_DS1_Pos (24UL) /*!< PAD35_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGI_PAD35_DS1_Msk (0x1000000UL) /*!< PAD35_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD34_SR_Pos (20UL) /*!< PAD34_SR (Bit 20) */ +#define GPIO_ALTPADCFGI_PAD34_SR_Msk (0x100000UL) /*!< PAD34_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD34_DS1_Pos (16UL) /*!< PAD34_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGI_PAD34_DS1_Msk (0x10000UL) /*!< PAD34_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD33_SR_Pos (12UL) /*!< PAD33_SR (Bit 12) */ +#define GPIO_ALTPADCFGI_PAD33_SR_Msk (0x1000UL) /*!< PAD33_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD33_DS1_Pos (8UL) /*!< PAD33_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGI_PAD33_DS1_Msk (0x100UL) /*!< PAD33_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD32_SR_Pos (4UL) /*!< PAD32_SR (Bit 4) */ +#define GPIO_ALTPADCFGI_PAD32_SR_Msk (0x10UL) /*!< PAD32_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD32_DS1_Pos (0UL) /*!< PAD32_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGI_PAD32_DS1_Msk (0x1UL) /*!< PAD32_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGJ ======================================================= */ +#define GPIO_ALTPADCFGJ_PAD39_SR_Pos (28UL) /*!< PAD39_SR (Bit 28) */ +#define GPIO_ALTPADCFGJ_PAD39_SR_Msk (0x10000000UL) /*!< PAD39_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD39_DS1_Pos (24UL) /*!< PAD39_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGJ_PAD39_DS1_Msk (0x1000000UL) /*!< PAD39_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD38_SR_Pos (20UL) /*!< PAD38_SR (Bit 20) */ +#define GPIO_ALTPADCFGJ_PAD38_SR_Msk (0x100000UL) /*!< PAD38_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD38_DS1_Pos (16UL) /*!< PAD38_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGJ_PAD38_DS1_Msk (0x10000UL) /*!< PAD38_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD37_SR_Pos (12UL) /*!< PAD37_SR (Bit 12) */ +#define GPIO_ALTPADCFGJ_PAD37_SR_Msk (0x1000UL) /*!< PAD37_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD37_DS1_Pos (8UL) /*!< PAD37_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGJ_PAD37_DS1_Msk (0x100UL) /*!< PAD37_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD36_SR_Pos (4UL) /*!< PAD36_SR (Bit 4) */ +#define GPIO_ALTPADCFGJ_PAD36_SR_Msk (0x10UL) /*!< PAD36_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD36_DS1_Pos (0UL) /*!< PAD36_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGJ_PAD36_DS1_Msk (0x1UL) /*!< PAD36_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGK ======================================================= */ +#define GPIO_ALTPADCFGK_PAD43_SR_Pos (28UL) /*!< PAD43_SR (Bit 28) */ +#define GPIO_ALTPADCFGK_PAD43_SR_Msk (0x10000000UL) /*!< PAD43_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD43_DS1_Pos (24UL) /*!< PAD43_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGK_PAD43_DS1_Msk (0x1000000UL) /*!< PAD43_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD42_SR_Pos (20UL) /*!< PAD42_SR (Bit 20) */ +#define GPIO_ALTPADCFGK_PAD42_SR_Msk (0x100000UL) /*!< PAD42_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD42_DS1_Pos (16UL) /*!< PAD42_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGK_PAD42_DS1_Msk (0x10000UL) /*!< PAD42_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD41_SR_Pos (12UL) /*!< PAD41_SR (Bit 12) */ +#define GPIO_ALTPADCFGK_PAD41_SR_Msk (0x1000UL) /*!< PAD41_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD41_DS1_Pos (8UL) /*!< PAD41_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGK_PAD41_DS1_Msk (0x100UL) /*!< PAD41_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD40_SR_Pos (4UL) /*!< PAD40_SR (Bit 4) */ +#define GPIO_ALTPADCFGK_PAD40_SR_Msk (0x10UL) /*!< PAD40_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD40_DS1_Pos (0UL) /*!< PAD40_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGK_PAD40_DS1_Msk (0x1UL) /*!< PAD40_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGL ======================================================= */ +#define GPIO_ALTPADCFGL_PAD47_SR_Pos (28UL) /*!< PAD47_SR (Bit 28) */ +#define GPIO_ALTPADCFGL_PAD47_SR_Msk (0x10000000UL) /*!< PAD47_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD47_DS1_Pos (24UL) /*!< PAD47_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGL_PAD47_DS1_Msk (0x1000000UL) /*!< PAD47_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD46_SR_Pos (20UL) /*!< PAD46_SR (Bit 20) */ +#define GPIO_ALTPADCFGL_PAD46_SR_Msk (0x100000UL) /*!< PAD46_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD46_DS1_Pos (16UL) /*!< PAD46_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGL_PAD46_DS1_Msk (0x10000UL) /*!< PAD46_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD45_SR_Pos (12UL) /*!< PAD45_SR (Bit 12) */ +#define GPIO_ALTPADCFGL_PAD45_SR_Msk (0x1000UL) /*!< PAD45_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD45_DS1_Pos (8UL) /*!< PAD45_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGL_PAD45_DS1_Msk (0x100UL) /*!< PAD45_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD44_SR_Pos (4UL) /*!< PAD44_SR (Bit 4) */ +#define GPIO_ALTPADCFGL_PAD44_SR_Msk (0x10UL) /*!< PAD44_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD44_DS1_Pos (0UL) /*!< PAD44_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGL_PAD44_DS1_Msk (0x1UL) /*!< PAD44_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGM ======================================================= */ +#define GPIO_ALTPADCFGM_PAD49_SR_Pos (12UL) /*!< PAD49_SR (Bit 12) */ +#define GPIO_ALTPADCFGM_PAD49_SR_Msk (0x1000UL) /*!< PAD49_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGM_PAD49_DS1_Pos (8UL) /*!< PAD49_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGM_PAD49_DS1_Msk (0x100UL) /*!< PAD49_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGM_PAD48_SR_Pos (4UL) /*!< PAD48_SR (Bit 4) */ +#define GPIO_ALTPADCFGM_PAD48_SR_Msk (0x10UL) /*!< PAD48_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGM_PAD48_DS1_Pos (0UL) /*!< PAD48_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGM_PAD48_DS1_Msk (0x1UL) /*!< PAD48_DS1 (Bitfield-Mask: 0x01) */ +/* ========================================================= SCDET ========================================================= */ +#define GPIO_SCDET_SCDET_Pos (0UL) /*!< SCDET (Bit 0) */ +#define GPIO_SCDET_SCDET_Msk (0x3fUL) /*!< SCDET (Bitfield-Mask: 0x3f) */ +/* ======================================================== CTENCFG ======================================================== */ +#define GPIO_CTENCFG_EN31_Pos (31UL) /*!< EN31 (Bit 31) */ +#define GPIO_CTENCFG_EN31_Msk (0x80000000UL) /*!< EN31 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN30_Pos (30UL) /*!< EN30 (Bit 30) */ +#define GPIO_CTENCFG_EN30_Msk (0x40000000UL) /*!< EN30 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN29_Pos (29UL) /*!< EN29 (Bit 29) */ +#define GPIO_CTENCFG_EN29_Msk (0x20000000UL) /*!< EN29 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN28_Pos (28UL) /*!< EN28 (Bit 28) */ +#define GPIO_CTENCFG_EN28_Msk (0x10000000UL) /*!< EN28 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN27_Pos (27UL) /*!< EN27 (Bit 27) */ +#define GPIO_CTENCFG_EN27_Msk (0x8000000UL) /*!< EN27 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN26_Pos (26UL) /*!< EN26 (Bit 26) */ +#define GPIO_CTENCFG_EN26_Msk (0x4000000UL) /*!< EN26 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN25_Pos (25UL) /*!< EN25 (Bit 25) */ +#define GPIO_CTENCFG_EN25_Msk (0x2000000UL) /*!< EN25 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN24_Pos (24UL) /*!< EN24 (Bit 24) */ +#define GPIO_CTENCFG_EN24_Msk (0x1000000UL) /*!< EN24 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN23_Pos (23UL) /*!< EN23 (Bit 23) */ +#define GPIO_CTENCFG_EN23_Msk (0x800000UL) /*!< EN23 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN22_Pos (22UL) /*!< EN22 (Bit 22) */ +#define GPIO_CTENCFG_EN22_Msk (0x400000UL) /*!< EN22 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN21_Pos (21UL) /*!< EN21 (Bit 21) */ +#define GPIO_CTENCFG_EN21_Msk (0x200000UL) /*!< EN21 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN20_Pos (20UL) /*!< EN20 (Bit 20) */ +#define GPIO_CTENCFG_EN20_Msk (0x100000UL) /*!< EN20 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN19_Pos (19UL) /*!< EN19 (Bit 19) */ +#define GPIO_CTENCFG_EN19_Msk (0x80000UL) /*!< EN19 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN18_Pos (18UL) /*!< EN18 (Bit 18) */ +#define GPIO_CTENCFG_EN18_Msk (0x40000UL) /*!< EN18 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN17_Pos (17UL) /*!< EN17 (Bit 17) */ +#define GPIO_CTENCFG_EN17_Msk (0x20000UL) /*!< EN17 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN16_Pos (16UL) /*!< EN16 (Bit 16) */ +#define GPIO_CTENCFG_EN16_Msk (0x10000UL) /*!< EN16 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN15_Pos (15UL) /*!< EN15 (Bit 15) */ +#define GPIO_CTENCFG_EN15_Msk (0x8000UL) /*!< EN15 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN14_Pos (14UL) /*!< EN14 (Bit 14) */ +#define GPIO_CTENCFG_EN14_Msk (0x4000UL) /*!< EN14 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN13_Pos (13UL) /*!< EN13 (Bit 13) */ +#define GPIO_CTENCFG_EN13_Msk (0x2000UL) /*!< EN13 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN12_Pos (12UL) /*!< EN12 (Bit 12) */ +#define GPIO_CTENCFG_EN12_Msk (0x1000UL) /*!< EN12 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN11_Pos (11UL) /*!< EN11 (Bit 11) */ +#define GPIO_CTENCFG_EN11_Msk (0x800UL) /*!< EN11 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN10_Pos (10UL) /*!< EN10 (Bit 10) */ +#define GPIO_CTENCFG_EN10_Msk (0x400UL) /*!< EN10 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN9_Pos (9UL) /*!< EN9 (Bit 9) */ +#define GPIO_CTENCFG_EN9_Msk (0x200UL) /*!< EN9 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN8_Pos (8UL) /*!< EN8 (Bit 8) */ +#define GPIO_CTENCFG_EN8_Msk (0x100UL) /*!< EN8 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN7_Pos (7UL) /*!< EN7 (Bit 7) */ +#define GPIO_CTENCFG_EN7_Msk (0x80UL) /*!< EN7 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN6_Pos (6UL) /*!< EN6 (Bit 6) */ +#define GPIO_CTENCFG_EN6_Msk (0x40UL) /*!< EN6 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN5_Pos (5UL) /*!< EN5 (Bit 5) */ +#define GPIO_CTENCFG_EN5_Msk (0x20UL) /*!< EN5 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN4_Pos (4UL) /*!< EN4 (Bit 4) */ +#define GPIO_CTENCFG_EN4_Msk (0x10UL) /*!< EN4 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN3_Pos (3UL) /*!< EN3 (Bit 3) */ +#define GPIO_CTENCFG_EN3_Msk (0x8UL) /*!< EN3 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN2_Pos (2UL) /*!< EN2 (Bit 2) */ +#define GPIO_CTENCFG_EN2_Msk (0x4UL) /*!< EN2 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN1_Pos (1UL) /*!< EN1 (Bit 1) */ +#define GPIO_CTENCFG_EN1_Msk (0x2UL) /*!< EN1 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN0_Pos (0UL) /*!< EN0 (Bit 0) */ +#define GPIO_CTENCFG_EN0_Msk (0x1UL) /*!< EN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT0EN ========================================================= */ +#define GPIO_INT0EN_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0EN_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0EN_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0EN_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0EN_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0EN_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0EN_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0EN_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0EN_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0EN_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0EN_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0EN_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0EN_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0EN_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0EN_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0EN_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0EN_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0EN_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0EN_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0EN_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0EN_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0EN_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0EN_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0EN_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0EN_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0EN_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0EN_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0EN_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0EN_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0EN_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0EN_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0EN_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0EN_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================= INT0STAT ======================================================== */ +#define GPIO_INT0STAT_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0STAT_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0STAT_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0STAT_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0STAT_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0STAT_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0STAT_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0STAT_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0STAT_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0STAT_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0STAT_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0STAT_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0STAT_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0STAT_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0STAT_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0STAT_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0STAT_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0STAT_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0STAT_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0STAT_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0STAT_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0STAT_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0STAT_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0STAT_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0STAT_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0STAT_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0STAT_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0STAT_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0STAT_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0STAT_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0STAT_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0STAT_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0STAT_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT0CLR ======================================================== */ +#define GPIO_INT0CLR_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0CLR_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0CLR_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0CLR_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0CLR_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0CLR_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0CLR_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0CLR_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0CLR_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0CLR_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0CLR_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0CLR_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0CLR_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0CLR_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0CLR_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0CLR_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0CLR_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0CLR_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0CLR_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0CLR_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0CLR_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0CLR_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0CLR_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0CLR_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0CLR_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0CLR_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0CLR_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0CLR_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0CLR_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0CLR_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0CLR_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0CLR_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0CLR_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT0SET ======================================================== */ +#define GPIO_INT0SET_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0SET_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0SET_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0SET_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0SET_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0SET_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0SET_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0SET_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0SET_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0SET_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0SET_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0SET_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0SET_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0SET_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0SET_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0SET_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0SET_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0SET_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0SET_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0SET_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0SET_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0SET_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0SET_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0SET_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0SET_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0SET_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0SET_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0SET_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0SET_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0SET_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0SET_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0SET_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0SET_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT1EN ========================================================= */ +#define GPIO_INT1EN_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1EN_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1EN_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1EN_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1EN_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1EN_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1EN_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1EN_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1EN_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1EN_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1EN_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1EN_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1EN_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1EN_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1EN_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1EN_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1EN_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1EN_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1EN_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ======================================================= INT1STAT ======================================================== */ +#define GPIO_INT1STAT_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1STAT_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1STAT_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1STAT_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1STAT_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1STAT_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1STAT_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1STAT_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1STAT_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1STAT_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1STAT_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1STAT_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1STAT_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1STAT_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1STAT_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1STAT_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1STAT_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1STAT_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1STAT_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT1CLR ======================================================== */ +#define GPIO_INT1CLR_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1CLR_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1CLR_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1CLR_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1CLR_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1CLR_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1CLR_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1CLR_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1CLR_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1CLR_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1CLR_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1CLR_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1CLR_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1CLR_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1CLR_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1CLR_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1CLR_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1CLR_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1CLR_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT1SET ======================================================== */ +#define GPIO_INT1SET_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1SET_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1SET_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1SET_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1SET_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1SET_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1SET_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1SET_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1SET_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1SET_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1SET_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1SET_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1SET_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1SET_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1SET_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1SET_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1SET_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1SET_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1SET_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IOM0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FIFO ========================================================== */ +#define IOM0_FIFO_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */ +#define IOM0_FIFO_FIFO_Msk (0xffffffffUL) /*!< FIFO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FIFOPTR ======================================================== */ +#define IOM0_FIFOPTR_FIFO1REM_Pos (24UL) /*!< FIFO1REM (Bit 24) */ +#define IOM0_FIFOPTR_FIFO1REM_Msk (0xff000000UL) /*!< FIFO1REM (Bitfield-Mask: 0xff) */ +#define IOM0_FIFOPTR_FIFO1SIZ_Pos (16UL) /*!< FIFO1SIZ (Bit 16) */ +#define IOM0_FIFOPTR_FIFO1SIZ_Msk (0xff0000UL) /*!< FIFO1SIZ (Bitfield-Mask: 0xff) */ +#define IOM0_FIFOPTR_FIFO0REM_Pos (8UL) /*!< FIFO0REM (Bit 8) */ +#define IOM0_FIFOPTR_FIFO0REM_Msk (0xff00UL) /*!< FIFO0REM (Bitfield-Mask: 0xff) */ +#define IOM0_FIFOPTR_FIFO0SIZ_Pos (0UL) /*!< FIFO0SIZ (Bit 0) */ +#define IOM0_FIFOPTR_FIFO0SIZ_Msk (0xffUL) /*!< FIFO0SIZ (Bitfield-Mask: 0xff) */ +/* ======================================================== FIFOTHR ======================================================== */ +#define IOM0_FIFOTHR_FIFOWTHR_Pos (8UL) /*!< FIFOWTHR (Bit 8) */ +#define IOM0_FIFOTHR_FIFOWTHR_Msk (0x3f00UL) /*!< FIFOWTHR (Bitfield-Mask: 0x3f) */ +#define IOM0_FIFOTHR_FIFORTHR_Pos (0UL) /*!< FIFORTHR (Bit 0) */ +#define IOM0_FIFOTHR_FIFORTHR_Msk (0x3fUL) /*!< FIFORTHR (Bitfield-Mask: 0x3f) */ +/* ======================================================== FIFOPOP ======================================================== */ +#define IOM0_FIFOPOP_FIFODOUT_Pos (0UL) /*!< FIFODOUT (Bit 0) */ +#define IOM0_FIFOPOP_FIFODOUT_Msk (0xffffffffUL) /*!< FIFODOUT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FIFOPUSH ======================================================== */ +#define IOM0_FIFOPUSH_FIFODIN_Pos (0UL) /*!< FIFODIN (Bit 0) */ +#define IOM0_FIFOPUSH_FIFODIN_Msk (0xffffffffUL) /*!< FIFODIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FIFOCTRL ======================================================== */ +#define IOM0_FIFOCTRL_FIFORSTN_Pos (1UL) /*!< FIFORSTN (Bit 1) */ +#define IOM0_FIFOCTRL_FIFORSTN_Msk (0x2UL) /*!< FIFORSTN (Bitfield-Mask: 0x01) */ +#define IOM0_FIFOCTRL_POPWR_Pos (0UL) /*!< POPWR (Bit 0) */ +#define IOM0_FIFOCTRL_POPWR_Msk (0x1UL) /*!< POPWR (Bitfield-Mask: 0x01) */ +/* ======================================================== FIFOLOC ======================================================== */ +#define IOM0_FIFOLOC_FIFORPTR_Pos (8UL) /*!< FIFORPTR (Bit 8) */ +#define IOM0_FIFOLOC_FIFORPTR_Msk (0xf00UL) /*!< FIFORPTR (Bitfield-Mask: 0x0f) */ +#define IOM0_FIFOLOC_FIFOWPTR_Pos (0UL) /*!< FIFOWPTR (Bit 0) */ +#define IOM0_FIFOLOC_FIFOWPTR_Msk (0xfUL) /*!< FIFOWPTR (Bitfield-Mask: 0x0f) */ +/* ========================================================= INTEN ========================================================= */ +#define IOM0_INTEN_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */ +#define IOM0_INTEN_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */ +#define IOM0_INTEN_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */ +#define IOM0_INTEN_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_DERR_Pos (11UL) /*!< DERR (Bit 11) */ +#define IOM0_INTEN_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */ +#define IOM0_INTEN_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_ARB_Pos (9UL) /*!< ARB (Bit 9) */ +#define IOM0_INTEN_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_STOP_Pos (8UL) /*!< STOP (Bit 8) */ +#define IOM0_INTEN_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_START_Pos (7UL) /*!< START (Bit 7) */ +#define IOM0_INTEN_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define IOM0_INTEN_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define IOM0_INTEN_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOM0_INTEN_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOM0_INTEN_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOM0_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOM0_INTEN_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOM0_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define IOM0_INTSTAT_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */ +#define IOM0_INTSTAT_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */ +#define IOM0_INTSTAT_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */ +#define IOM0_INTSTAT_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_DERR_Pos (11UL) /*!< DERR (Bit 11) */ +#define IOM0_INTSTAT_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */ +#define IOM0_INTSTAT_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_ARB_Pos (9UL) /*!< ARB (Bit 9) */ +#define IOM0_INTSTAT_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_STOP_Pos (8UL) /*!< STOP (Bit 8) */ +#define IOM0_INTSTAT_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_START_Pos (7UL) /*!< START (Bit 7) */ +#define IOM0_INTSTAT_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define IOM0_INTSTAT_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define IOM0_INTSTAT_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOM0_INTSTAT_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOM0_INTSTAT_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOM0_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOM0_INTSTAT_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOM0_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define IOM0_INTCLR_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */ +#define IOM0_INTCLR_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */ +#define IOM0_INTCLR_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */ +#define IOM0_INTCLR_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_DERR_Pos (11UL) /*!< DERR (Bit 11) */ +#define IOM0_INTCLR_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */ +#define IOM0_INTCLR_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_ARB_Pos (9UL) /*!< ARB (Bit 9) */ +#define IOM0_INTCLR_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_STOP_Pos (8UL) /*!< STOP (Bit 8) */ +#define IOM0_INTCLR_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_START_Pos (7UL) /*!< START (Bit 7) */ +#define IOM0_INTCLR_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define IOM0_INTCLR_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define IOM0_INTCLR_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOM0_INTCLR_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOM0_INTCLR_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOM0_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOM0_INTCLR_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOM0_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define IOM0_INTSET_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */ +#define IOM0_INTSET_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */ +#define IOM0_INTSET_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */ +#define IOM0_INTSET_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_DERR_Pos (11UL) /*!< DERR (Bit 11) */ +#define IOM0_INTSET_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */ +#define IOM0_INTSET_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_ARB_Pos (9UL) /*!< ARB (Bit 9) */ +#define IOM0_INTSET_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_STOP_Pos (8UL) /*!< STOP (Bit 8) */ +#define IOM0_INTSET_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_START_Pos (7UL) /*!< START (Bit 7) */ +#define IOM0_INTSET_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define IOM0_INTSET_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define IOM0_INTSET_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOM0_INTSET_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOM0_INTSET_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOM0_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOM0_INTSET_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOM0_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== CLKCFG ========================================================= */ +#define IOM0_CLKCFG_TOTPER_Pos (24UL) /*!< TOTPER (Bit 24) */ +#define IOM0_CLKCFG_TOTPER_Msk (0xff000000UL) /*!< TOTPER (Bitfield-Mask: 0xff) */ +#define IOM0_CLKCFG_LOWPER_Pos (16UL) /*!< LOWPER (Bit 16) */ +#define IOM0_CLKCFG_LOWPER_Msk (0xff0000UL) /*!< LOWPER (Bitfield-Mask: 0xff) */ +#define IOM0_CLKCFG_DIVEN_Pos (12UL) /*!< DIVEN (Bit 12) */ +#define IOM0_CLKCFG_DIVEN_Msk (0x1000UL) /*!< DIVEN (Bitfield-Mask: 0x01) */ +#define IOM0_CLKCFG_DIV3_Pos (11UL) /*!< DIV3 (Bit 11) */ +#define IOM0_CLKCFG_DIV3_Msk (0x800UL) /*!< DIV3 (Bitfield-Mask: 0x01) */ +#define IOM0_CLKCFG_FSEL_Pos (8UL) /*!< FSEL (Bit 8) */ +#define IOM0_CLKCFG_FSEL_Msk (0x700UL) /*!< FSEL (Bitfield-Mask: 0x07) */ +#define IOM0_CLKCFG_IOCLKEN_Pos (0UL) /*!< IOCLKEN (Bit 0) */ +#define IOM0_CLKCFG_IOCLKEN_Msk (0x1UL) /*!< IOCLKEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SUBMODCTRL ======================================================= */ +#define IOM0_SUBMODCTRL_SMOD1TYPE_Pos (5UL) /*!< SMOD1TYPE (Bit 5) */ +#define IOM0_SUBMODCTRL_SMOD1TYPE_Msk (0xe0UL) /*!< SMOD1TYPE (Bitfield-Mask: 0x07) */ +#define IOM0_SUBMODCTRL_SMOD1EN_Pos (4UL) /*!< SMOD1EN (Bit 4) */ +#define IOM0_SUBMODCTRL_SMOD1EN_Msk (0x10UL) /*!< SMOD1EN (Bitfield-Mask: 0x01) */ +#define IOM0_SUBMODCTRL_SMOD0TYPE_Pos (1UL) /*!< SMOD0TYPE (Bit 1) */ +#define IOM0_SUBMODCTRL_SMOD0TYPE_Msk (0xeUL) /*!< SMOD0TYPE (Bitfield-Mask: 0x07) */ +#define IOM0_SUBMODCTRL_SMOD0EN_Pos (0UL) /*!< SMOD0EN (Bit 0) */ +#define IOM0_SUBMODCTRL_SMOD0EN_Msk (0x1UL) /*!< SMOD0EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CMD ========================================================== */ +#define IOM0_CMD_OFFSETLO_Pos (24UL) /*!< OFFSETLO (Bit 24) */ +#define IOM0_CMD_OFFSETLO_Msk (0xff000000UL) /*!< OFFSETLO (Bitfield-Mask: 0xff) */ +#define IOM0_CMD_CMDSEL_Pos (20UL) /*!< CMDSEL (Bit 20) */ +#define IOM0_CMD_CMDSEL_Msk (0x300000UL) /*!< CMDSEL (Bitfield-Mask: 0x03) */ +#define IOM0_CMD_TSIZE_Pos (8UL) /*!< TSIZE (Bit 8) */ +#define IOM0_CMD_TSIZE_Msk (0xfff00UL) /*!< TSIZE (Bitfield-Mask: 0xfff) */ +#define IOM0_CMD_CONT_Pos (7UL) /*!< CONT (Bit 7) */ +#define IOM0_CMD_CONT_Msk (0x80UL) /*!< CONT (Bitfield-Mask: 0x01) */ +#define IOM0_CMD_OFFSETCNT_Pos (5UL) /*!< OFFSETCNT (Bit 5) */ +#define IOM0_CMD_OFFSETCNT_Msk (0x60UL) /*!< OFFSETCNT (Bitfield-Mask: 0x03) */ +#define IOM0_CMD_CMD_Pos (0UL) /*!< CMD (Bit 0) */ +#define IOM0_CMD_CMD_Msk (0x1fUL) /*!< CMD (Bitfield-Mask: 0x1f) */ +/* ========================================================== DCX ========================================================== */ +#define IOM0_DCX_DCXEN_Pos (4UL) /*!< DCXEN (Bit 4) */ +#define IOM0_DCX_DCXEN_Msk (0x10UL) /*!< DCXEN (Bitfield-Mask: 0x01) */ +#define IOM0_DCX_CE3OUT_Pos (3UL) /*!< CE3OUT (Bit 3) */ +#define IOM0_DCX_CE3OUT_Msk (0x8UL) /*!< CE3OUT (Bitfield-Mask: 0x01) */ +#define IOM0_DCX_CE2OUT_Pos (2UL) /*!< CE2OUT (Bit 2) */ +#define IOM0_DCX_CE2OUT_Msk (0x4UL) /*!< CE2OUT (Bitfield-Mask: 0x01) */ +#define IOM0_DCX_CE1OUT_Pos (1UL) /*!< CE1OUT (Bit 1) */ +#define IOM0_DCX_CE1OUT_Msk (0x2UL) /*!< CE1OUT (Bitfield-Mask: 0x01) */ +#define IOM0_DCX_CE0OUT_Pos (0UL) /*!< CE0OUT (Bit 0) */ +#define IOM0_DCX_CE0OUT_Msk (0x1UL) /*!< CE0OUT (Bitfield-Mask: 0x01) */ +/* ======================================================= OFFSETHI ======================================================== */ +#define IOM0_OFFSETHI_OFFSETHI_Pos (0UL) /*!< OFFSETHI (Bit 0) */ +#define IOM0_OFFSETHI_OFFSETHI_Msk (0xffffUL) /*!< OFFSETHI (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMDSTAT ======================================================== */ +#define IOM0_CMDSTAT_CTSIZE_Pos (8UL) /*!< CTSIZE (Bit 8) */ +#define IOM0_CMDSTAT_CTSIZE_Msk (0xfff00UL) /*!< CTSIZE (Bitfield-Mask: 0xfff) */ +#define IOM0_CMDSTAT_CMDSTAT_Pos (5UL) /*!< CMDSTAT (Bit 5) */ +#define IOM0_CMDSTAT_CMDSTAT_Msk (0xe0UL) /*!< CMDSTAT (Bitfield-Mask: 0x07) */ +#define IOM0_CMDSTAT_CCMD_Pos (0UL) /*!< CCMD (Bit 0) */ +#define IOM0_CMDSTAT_CCMD_Msk (0x1fUL) /*!< CCMD (Bitfield-Mask: 0x1f) */ +/* ======================================================= DMATRIGEN ======================================================= */ +#define IOM0_DMATRIGEN_DTHREN_Pos (1UL) /*!< DTHREN (Bit 1) */ +#define IOM0_DMATRIGEN_DTHREN_Msk (0x2UL) /*!< DTHREN (Bitfield-Mask: 0x01) */ +#define IOM0_DMATRIGEN_DCMDCMPEN_Pos (0UL) /*!< DCMDCMPEN (Bit 0) */ +#define IOM0_DMATRIGEN_DCMDCMPEN_Msk (0x1UL) /*!< DCMDCMPEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +#define IOM0_DMATRIGSTAT_DTOTCMP_Pos (2UL) /*!< DTOTCMP (Bit 2) */ +#define IOM0_DMATRIGSTAT_DTOTCMP_Msk (0x4UL) /*!< DTOTCMP (Bitfield-Mask: 0x01) */ +#define IOM0_DMATRIGSTAT_DTHR_Pos (1UL) /*!< DTHR (Bit 1) */ +#define IOM0_DMATRIGSTAT_DTHR_Msk (0x2UL) /*!< DTHR (Bitfield-Mask: 0x01) */ +#define IOM0_DMATRIGSTAT_DCMDCMP_Pos (0UL) /*!< DCMDCMP (Bit 0) */ +#define IOM0_DMATRIGSTAT_DCMDCMP_Msk (0x1UL) /*!< DCMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACFG ========================================================= */ +#define IOM0_DMACFG_DPWROFF_Pos (9UL) /*!< DPWROFF (Bit 9) */ +#define IOM0_DMACFG_DPWROFF_Msk (0x200UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */ +#define IOM0_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */ +#define IOM0_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */ +#define IOM0_DMACFG_DMADIR_Pos (1UL) /*!< DMADIR (Bit 1) */ +#define IOM0_DMACFG_DMADIR_Msk (0x2UL) /*!< DMADIR (Bitfield-Mask: 0x01) */ +#define IOM0_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */ +#define IOM0_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +#define IOM0_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */ +#define IOM0_DMATOTCOUNT_TOTCOUNT_Msk (0xfffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xfff) */ +/* ====================================================== DMATARGADDR ====================================================== */ +#define IOM0_DMATARGADDR_TARGADDR28_Pos (28UL) /*!< TARGADDR28 (Bit 28) */ +#define IOM0_DMATARGADDR_TARGADDR28_Msk (0x10000000UL) /*!< TARGADDR28 (Bitfield-Mask: 0x01) */ +#define IOM0_DMATARGADDR_TARGADDR_Pos (0UL) /*!< TARGADDR (Bit 0) */ +#define IOM0_DMATARGADDR_TARGADDR_Msk (0xfffffUL) /*!< TARGADDR (Bitfield-Mask: 0xfffff) */ +/* ======================================================== DMASTAT ======================================================== */ +#define IOM0_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */ +#define IOM0_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */ +#define IOM0_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */ +#define IOM0_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */ +#define IOM0_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */ +#define IOM0_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */ +/* ========================================================= CQCFG ========================================================= */ +#define IOM0_CQCFG_CQPRI_Pos (1UL) /*!< CQPRI (Bit 1) */ +#define IOM0_CQCFG_CQPRI_Msk (0x2UL) /*!< CQPRI (Bitfield-Mask: 0x01) */ +#define IOM0_CQCFG_CQEN_Pos (0UL) /*!< CQEN (Bit 0) */ +#define IOM0_CQCFG_CQEN_Msk (0x1UL) /*!< CQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CQADDR ========================================================= */ +#define IOM0_CQADDR_CQADDR28_Pos (28UL) /*!< CQADDR28 (Bit 28) */ +#define IOM0_CQADDR_CQADDR28_Msk (0x10000000UL) /*!< CQADDR28 (Bitfield-Mask: 0x01) */ +#define IOM0_CQADDR_CQADDR_Pos (2UL) /*!< CQADDR (Bit 2) */ +#define IOM0_CQADDR_CQADDR_Msk (0xffffcUL) /*!< CQADDR (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== CQSTAT ========================================================= */ +#define IOM0_CQSTAT_CQERR_Pos (2UL) /*!< CQERR (Bit 2) */ +#define IOM0_CQSTAT_CQERR_Msk (0x4UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define IOM0_CQSTAT_CQPAUSED_Pos (1UL) /*!< CQPAUSED (Bit 1) */ +#define IOM0_CQSTAT_CQPAUSED_Msk (0x2UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define IOM0_CQSTAT_CQTIP_Pos (0UL) /*!< CQTIP (Bit 0) */ +#define IOM0_CQSTAT_CQTIP_Msk (0x1UL) /*!< CQTIP (Bitfield-Mask: 0x01) */ +/* ======================================================== CQFLAGS ======================================================== */ +#define IOM0_CQFLAGS_CQIRQMASK_Pos (16UL) /*!< CQIRQMASK (Bit 16) */ +#define IOM0_CQFLAGS_CQIRQMASK_Msk (0xffff0000UL) /*!< CQIRQMASK (Bitfield-Mask: 0xffff) */ +#define IOM0_CQFLAGS_CQFLAGS_Pos (0UL) /*!< CQFLAGS (Bit 0) */ +#define IOM0_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< CQFLAGS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CQSETCLEAR ======================================================= */ +#define IOM0_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< CQFCLR (Bit 16) */ +#define IOM0_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< CQFCLR (Bitfield-Mask: 0xff) */ +#define IOM0_CQSETCLEAR_CQFTGL_Pos (8UL) /*!< CQFTGL (Bit 8) */ +#define IOM0_CQSETCLEAR_CQFTGL_Msk (0xff00UL) /*!< CQFTGL (Bitfield-Mask: 0xff) */ +#define IOM0_CQSETCLEAR_CQFSET_Pos (0UL) /*!< CQFSET (Bit 0) */ +#define IOM0_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< CQFSET (Bitfield-Mask: 0xff) */ +/* ======================================================= CQPAUSEEN ======================================================= */ +#define IOM0_CQPAUSEEN_CQPEN_Pos (0UL) /*!< CQPEN (Bit 0) */ +#define IOM0_CQPAUSEEN_CQPEN_Msk (0xffffUL) /*!< CQPEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= CQCURIDX ======================================================== */ +#define IOM0_CQCURIDX_CQCURIDX_Pos (0UL) /*!< CQCURIDX (Bit 0) */ +#define IOM0_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< CQCURIDX (Bitfield-Mask: 0xff) */ +/* ======================================================= CQENDIDX ======================================================== */ +#define IOM0_CQENDIDX_CQENDIDX_Pos (0UL) /*!< CQENDIDX (Bit 0) */ +#define IOM0_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< CQENDIDX (Bitfield-Mask: 0xff) */ +/* ======================================================== STATUS ========================================================= */ +#define IOM0_STATUS_IDLEST_Pos (2UL) /*!< IDLEST (Bit 2) */ +#define IOM0_STATUS_IDLEST_Msk (0x4UL) /*!< IDLEST (Bitfield-Mask: 0x01) */ +#define IOM0_STATUS_CMDACT_Pos (1UL) /*!< CMDACT (Bit 1) */ +#define IOM0_STATUS_CMDACT_Msk (0x2UL) /*!< CMDACT (Bitfield-Mask: 0x01) */ +#define IOM0_STATUS_ERR_Pos (0UL) /*!< ERR (Bit 0) */ +#define IOM0_STATUS_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== MSPICFG ======================================================== */ +#define IOM0_MSPICFG_MSPIRST_Pos (30UL) /*!< MSPIRST (Bit 30) */ +#define IOM0_MSPICFG_MSPIRST_Msk (0x40000000UL) /*!< MSPIRST (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_DOUTDLY_Pos (27UL) /*!< DOUTDLY (Bit 27) */ +#define IOM0_MSPICFG_DOUTDLY_Msk (0x38000000UL) /*!< DOUTDLY (Bitfield-Mask: 0x07) */ +#define IOM0_MSPICFG_DINDLY_Pos (24UL) /*!< DINDLY (Bit 24) */ +#define IOM0_MSPICFG_DINDLY_Msk (0x7000000UL) /*!< DINDLY (Bitfield-Mask: 0x07) */ +#define IOM0_MSPICFG_SPILSB_Pos (23UL) /*!< SPILSB (Bit 23) */ +#define IOM0_MSPICFG_SPILSB_Msk (0x800000UL) /*!< SPILSB (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_RDFCPOL_Pos (22UL) /*!< RDFCPOL (Bit 22) */ +#define IOM0_MSPICFG_RDFCPOL_Msk (0x400000UL) /*!< RDFCPOL (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_WTFCPOL_Pos (21UL) /*!< WTFCPOL (Bit 21) */ +#define IOM0_MSPICFG_WTFCPOL_Msk (0x200000UL) /*!< WTFCPOL (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_WTFCIRQ_Pos (20UL) /*!< WTFCIRQ (Bit 20) */ +#define IOM0_MSPICFG_WTFCIRQ_Msk (0x100000UL) /*!< WTFCIRQ (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_MOSIINV_Pos (18UL) /*!< MOSIINV (Bit 18) */ +#define IOM0_MSPICFG_MOSIINV_Msk (0x40000UL) /*!< MOSIINV (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_RDFC_Pos (17UL) /*!< RDFC (Bit 17) */ +#define IOM0_MSPICFG_RDFC_Msk (0x20000UL) /*!< RDFC (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_WTFC_Pos (16UL) /*!< WTFC (Bit 16) */ +#define IOM0_MSPICFG_WTFC_Msk (0x10000UL) /*!< WTFC (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_FULLDUP_Pos (2UL) /*!< FULLDUP (Bit 2) */ +#define IOM0_MSPICFG_FULLDUP_Msk (0x4UL) /*!< FULLDUP (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_SPHA_Pos (1UL) /*!< SPHA (Bit 1) */ +#define IOM0_MSPICFG_SPHA_Msk (0x2UL) /*!< SPHA (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_SPOL_Pos (0UL) /*!< SPOL (Bit 0) */ +#define IOM0_MSPICFG_SPOL_Msk (0x1UL) /*!< SPOL (Bitfield-Mask: 0x01) */ +/* ======================================================== MI2CCFG ======================================================== */ +#define IOM0_MI2CCFG_STRDIS_Pos (24UL) /*!< STRDIS (Bit 24) */ +#define IOM0_MI2CCFG_STRDIS_Msk (0x1000000UL) /*!< STRDIS (Bitfield-Mask: 0x01) */ +#define IOM0_MI2CCFG_SMPCNT_Pos (16UL) /*!< SMPCNT (Bit 16) */ +#define IOM0_MI2CCFG_SMPCNT_Msk (0xff0000UL) /*!< SMPCNT (Bitfield-Mask: 0xff) */ +#define IOM0_MI2CCFG_SDAENDLY_Pos (12UL) /*!< SDAENDLY (Bit 12) */ +#define IOM0_MI2CCFG_SDAENDLY_Msk (0xf000UL) /*!< SDAENDLY (Bitfield-Mask: 0x0f) */ +#define IOM0_MI2CCFG_SCLENDLY_Pos (8UL) /*!< SCLENDLY (Bit 8) */ +#define IOM0_MI2CCFG_SCLENDLY_Msk (0xf00UL) /*!< SCLENDLY (Bitfield-Mask: 0x0f) */ +#define IOM0_MI2CCFG_MI2CRST_Pos (6UL) /*!< MI2CRST (Bit 6) */ +#define IOM0_MI2CCFG_MI2CRST_Msk (0x40UL) /*!< MI2CRST (Bitfield-Mask: 0x01) */ +#define IOM0_MI2CCFG_SDADLY_Pos (4UL) /*!< SDADLY (Bit 4) */ +#define IOM0_MI2CCFG_SDADLY_Msk (0x30UL) /*!< SDADLY (Bitfield-Mask: 0x03) */ +#define IOM0_MI2CCFG_ARBEN_Pos (2UL) /*!< ARBEN (Bit 2) */ +#define IOM0_MI2CCFG_ARBEN_Msk (0x4UL) /*!< ARBEN (Bitfield-Mask: 0x01) */ +#define IOM0_MI2CCFG_I2CLSB_Pos (1UL) /*!< I2CLSB (Bit 1) */ +#define IOM0_MI2CCFG_I2CLSB_Msk (0x2UL) /*!< I2CLSB (Bitfield-Mask: 0x01) */ +#define IOM0_MI2CCFG_ADDRSZ_Pos (0UL) /*!< ADDRSZ (Bit 0) */ +#define IOM0_MI2CCFG_ADDRSZ_Msk (0x1UL) /*!< ADDRSZ (Bitfield-Mask: 0x01) */ +/* ======================================================== DEVCFG ========================================================= */ +#define IOM0_DEVCFG_DEVADDR_Pos (0UL) /*!< DEVADDR (Bit 0) */ +#define IOM0_DEVCFG_DEVADDR_Msk (0x3ffUL) /*!< DEVADDR (Bitfield-Mask: 0x3ff) */ +/* ======================================================== IOMDBG ========================================================= */ +#define IOM0_IOMDBG_DBGDATA_Pos (3UL) /*!< DBGDATA (Bit 3) */ +#define IOM0_IOMDBG_DBGDATA_Msk (0xfffffff8UL) /*!< DBGDATA (Bitfield-Mask: 0x1fffffff) */ +#define IOM0_IOMDBG_APBCLKON_Pos (2UL) /*!< APBCLKON (Bit 2) */ +#define IOM0_IOMDBG_APBCLKON_Msk (0x4UL) /*!< APBCLKON (Bitfield-Mask: 0x01) */ +#define IOM0_IOMDBG_IOCLKON_Pos (1UL) /*!< IOCLKON (Bit 1) */ +#define IOM0_IOMDBG_IOCLKON_Msk (0x2UL) /*!< IOCLKON (Bitfield-Mask: 0x01) */ +#define IOM0_IOMDBG_DBGEN_Pos (0UL) /*!< DBGEN (Bit 0) */ +#define IOM0_IOMDBG_DBGEN_Msk (0x1UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IOSLAVE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FIFOPTR ======================================================== */ +#define IOSLAVE_FIFOPTR_FIFOSIZ_Pos (8UL) /*!< FIFOSIZ (Bit 8) */ +#define IOSLAVE_FIFOPTR_FIFOSIZ_Msk (0xff00UL) /*!< FIFOSIZ (Bitfield-Mask: 0xff) */ +#define IOSLAVE_FIFOPTR_FIFOPTR_Pos (0UL) /*!< FIFOPTR (Bit 0) */ +#define IOSLAVE_FIFOPTR_FIFOPTR_Msk (0xffUL) /*!< FIFOPTR (Bitfield-Mask: 0xff) */ +/* ======================================================== FIFOCFG ======================================================== */ +#define IOSLAVE_FIFOCFG_ROBASE_Pos (24UL) /*!< ROBASE (Bit 24) */ +#define IOSLAVE_FIFOCFG_ROBASE_Msk (0x3f000000UL) /*!< ROBASE (Bitfield-Mask: 0x3f) */ +#define IOSLAVE_FIFOCFG_FIFOMAX_Pos (8UL) /*!< FIFOMAX (Bit 8) */ +#define IOSLAVE_FIFOCFG_FIFOMAX_Msk (0x3f00UL) /*!< FIFOMAX (Bitfield-Mask: 0x3f) */ +#define IOSLAVE_FIFOCFG_FIFOBASE_Pos (0UL) /*!< FIFOBASE (Bit 0) */ +#define IOSLAVE_FIFOCFG_FIFOBASE_Msk (0x1fUL) /*!< FIFOBASE (Bitfield-Mask: 0x1f) */ +/* ======================================================== FIFOTHR ======================================================== */ +#define IOSLAVE_FIFOTHR_FIFOTHR_Pos (0UL) /*!< FIFOTHR (Bit 0) */ +#define IOSLAVE_FIFOTHR_FIFOTHR_Msk (0xffUL) /*!< FIFOTHR (Bitfield-Mask: 0xff) */ +/* ========================================================= FUPD ========================================================== */ +#define IOSLAVE_FUPD_IOREAD_Pos (1UL) /*!< IOREAD (Bit 1) */ +#define IOSLAVE_FUPD_IOREAD_Msk (0x2UL) /*!< IOREAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_FUPD_FIFOUPD_Pos (0UL) /*!< FIFOUPD (Bit 0) */ +#define IOSLAVE_FUPD_FIFOUPD_Msk (0x1UL) /*!< FIFOUPD (Bitfield-Mask: 0x01) */ +/* ======================================================== FIFOCTR ======================================================== */ +#define IOSLAVE_FIFOCTR_FIFOCTR_Pos (0UL) /*!< FIFOCTR (Bit 0) */ +#define IOSLAVE_FIFOCTR_FIFOCTR_Msk (0x3ffUL) /*!< FIFOCTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FIFOINC ======================================================== */ +#define IOSLAVE_FIFOINC_FIFOINC_Pos (0UL) /*!< FIFOINC (Bit 0) */ +#define IOSLAVE_FIFOINC_FIFOINC_Msk (0x3ffUL) /*!< FIFOINC (Bitfield-Mask: 0x3ff) */ +/* ========================================================== CFG ========================================================== */ +#define IOSLAVE_CFG_IFCEN_Pos (31UL) /*!< IFCEN (Bit 31) */ +#define IOSLAVE_CFG_IFCEN_Msk (0x80000000UL) /*!< IFCEN (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_I2CADDR_Pos (8UL) /*!< I2CADDR (Bit 8) */ +#define IOSLAVE_CFG_I2CADDR_Msk (0xfff00UL) /*!< I2CADDR (Bitfield-Mask: 0xfff) */ +#define IOSLAVE_CFG_STARTRD_Pos (4UL) /*!< STARTRD (Bit 4) */ +#define IOSLAVE_CFG_STARTRD_Msk (0x10UL) /*!< STARTRD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_LSB_Pos (2UL) /*!< LSB (Bit 2) */ +#define IOSLAVE_CFG_LSB_Msk (0x4UL) /*!< LSB (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_SPOL_Pos (1UL) /*!< SPOL (Bit 1) */ +#define IOSLAVE_CFG_SPOL_Msk (0x2UL) /*!< SPOL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_IFCSEL_Pos (0UL) /*!< IFCSEL (Bit 0) */ +#define IOSLAVE_CFG_IFCSEL_Msk (0x1UL) /*!< IFCSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= PRENC ========================================================= */ +#define IOSLAVE_PRENC_PRENC_Pos (0UL) /*!< PRENC (Bit 0) */ +#define IOSLAVE_PRENC_PRENC_Msk (0x1fUL) /*!< PRENC (Bitfield-Mask: 0x1f) */ +/* ======================================================= IOINTCTL ======================================================== */ +#define IOSLAVE_IOINTCTL_IOINTSET_Pos (24UL) /*!< IOINTSET (Bit 24) */ +#define IOSLAVE_IOINTCTL_IOINTSET_Msk (0xff000000UL) /*!< IOINTSET (Bitfield-Mask: 0xff) */ +#define IOSLAVE_IOINTCTL_IOINTCLR_Pos (16UL) /*!< IOINTCLR (Bit 16) */ +#define IOSLAVE_IOINTCTL_IOINTCLR_Msk (0x10000UL) /*!< IOINTCLR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_IOINTCTL_IOINT_Pos (8UL) /*!< IOINT (Bit 8) */ +#define IOSLAVE_IOINTCTL_IOINT_Msk (0xff00UL) /*!< IOINT (Bitfield-Mask: 0xff) */ +#define IOSLAVE_IOINTCTL_IOINTEN_Pos (0UL) /*!< IOINTEN (Bit 0) */ +#define IOSLAVE_IOINTCTL_IOINTEN_Msk (0xffUL) /*!< IOINTEN (Bitfield-Mask: 0xff) */ +/* ======================================================== GENADD ========================================================= */ +#define IOSLAVE_GENADD_GADATA_Pos (0UL) /*!< GADATA (Bit 0) */ +#define IOSLAVE_GENADD_GADATA_Msk (0xffUL) /*!< GADATA (Bitfield-Mask: 0xff) */ +/* ========================================================= INTEN ========================================================= */ +#define IOSLAVE_INTEN_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTEN_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTEN_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTEN_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTEN_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTEN_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTEN_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTEN_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTEN_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTEN_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define IOSLAVE_INTSTAT_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTSTAT_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTSTAT_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTSTAT_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTSTAT_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTSTAT_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTSTAT_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTSTAT_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTSTAT_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTSTAT_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define IOSLAVE_INTCLR_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTCLR_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTCLR_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTCLR_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTCLR_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTCLR_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTCLR_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTCLR_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTCLR_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTCLR_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define IOSLAVE_INTSET_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTSET_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTSET_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTSET_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTSET_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTSET_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTSET_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTSET_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTSET_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTSET_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ====================================================== REGACCINTEN ====================================================== */ +#define IOSLAVE_REGACCINTEN_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTEN_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== REGACCINTSTAT ===================================================== */ +#define IOSLAVE_REGACCINTSTAT_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTSTAT_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== REGACCINTCLR ====================================================== */ +#define IOSLAVE_REGACCINTCLR_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTCLR_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== REGACCINTSET ====================================================== */ +#define IOSLAVE_REGACCINTSET_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTSET_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ MCUCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CHIPPN ========================================================= */ +#define MCUCTRL_CHIPPN_PARTNUM_Pos (0UL) /*!< PARTNUM (Bit 0) */ +#define MCUCTRL_CHIPPN_PARTNUM_Msk (0xffffffffUL) /*!< PARTNUM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHIPID0 ======================================================== */ +#define MCUCTRL_CHIPID0_CHIPID0_Pos (0UL) /*!< CHIPID0 (Bit 0) */ +#define MCUCTRL_CHIPID0_CHIPID0_Msk (0xffffffffUL) /*!< CHIPID0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHIPID1 ======================================================== */ +#define MCUCTRL_CHIPID1_CHIPID1_Pos (0UL) /*!< CHIPID1 (Bit 0) */ +#define MCUCTRL_CHIPID1_CHIPID1_Msk (0xffffffffUL) /*!< CHIPID1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHIPREV ======================================================== */ +#define MCUCTRL_CHIPREV_SIPART_Pos (8UL) /*!< SIPART (Bit 8) */ +#define MCUCTRL_CHIPREV_SIPART_Msk (0xfff00UL) /*!< SIPART (Bitfield-Mask: 0xfff) */ +#define MCUCTRL_CHIPREV_REVMAJ_Pos (4UL) /*!< REVMAJ (Bit 4) */ +#define MCUCTRL_CHIPREV_REVMAJ_Msk (0xf0UL) /*!< REVMAJ (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_CHIPREV_REVMIN_Pos (0UL) /*!< REVMIN (Bit 0) */ +#define MCUCTRL_CHIPREV_REVMIN_Msk (0xfUL) /*!< REVMIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= VENDORID ======================================================== */ +#define MCUCTRL_VENDORID_VENDORID_Pos (0UL) /*!< VENDORID (Bit 0) */ +#define MCUCTRL_VENDORID_VENDORID_Msk (0xffffffffUL) /*!< VENDORID (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== SKU ========================================================== */ +#define MCUCTRL_SKU_SECBOOT_Pos (2UL) /*!< SECBOOT (Bit 2) */ +#define MCUCTRL_SKU_SECBOOT_Msk (0x4UL) /*!< SECBOOT (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SKU_ALLOWBLE_Pos (1UL) /*!< ALLOWBLE (Bit 1) */ +#define MCUCTRL_SKU_ALLOWBLE_Msk (0x2UL) /*!< ALLOWBLE (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SKU_ALLOWBURST_Pos (0UL) /*!< ALLOWBURST (Bit 0) */ +#define MCUCTRL_SKU_ALLOWBURST_Msk (0x1UL) /*!< ALLOWBURST (Bitfield-Mask: 0x01) */ +/* ===================================================== FEATUREENABLE ===================================================== */ +#define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Pos (6UL) /*!< BURSTAVAIL (Bit 6) */ +#define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Msk (0x40UL) /*!< BURSTAVAIL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FEATUREENABLE_BURSTACK_Pos (5UL) /*!< BURSTACK (Bit 5) */ +#define MCUCTRL_FEATUREENABLE_BURSTACK_Msk (0x20UL) /*!< BURSTACK (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FEATUREENABLE_BURSTREQ_Pos (4UL) /*!< BURSTREQ (Bit 4) */ +#define MCUCTRL_FEATUREENABLE_BURSTREQ_Msk (0x10UL) /*!< BURSTREQ (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FEATUREENABLE_BLEAVAIL_Pos (2UL) /*!< BLEAVAIL (Bit 2) */ +#define MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk (0x4UL) /*!< BLEAVAIL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FEATUREENABLE_BLEACK_Pos (1UL) /*!< BLEACK (Bit 1) */ +#define MCUCTRL_FEATUREENABLE_BLEACK_Msk (0x2UL) /*!< BLEACK (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FEATUREENABLE_BLEREQ_Pos (0UL) /*!< BLEREQ (Bit 0) */ +#define MCUCTRL_FEATUREENABLE_BLEREQ_Msk (0x1UL) /*!< BLEREQ (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGGER ======================================================== */ +#define MCUCTRL_DEBUGGER_LOCKOUT_Pos (0UL) /*!< LOCKOUT (Bit 0) */ +#define MCUCTRL_DEBUGGER_LOCKOUT_Msk (0x1UL) /*!< LOCKOUT (Bitfield-Mask: 0x01) */ +/* ======================================================== BODCTRL ======================================================== */ +#define MCUCTRL_BODCTRL_BODHVREFSEL_Pos (5UL) /*!< BODHVREFSEL (Bit 5) */ +#define MCUCTRL_BODCTRL_BODHVREFSEL_Msk (0x20UL) /*!< BODHVREFSEL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODCTRL_BODLVREFSEL_Pos (4UL) /*!< BODLVREFSEL (Bit 4) */ +#define MCUCTRL_BODCTRL_BODLVREFSEL_Msk (0x10UL) /*!< BODLVREFSEL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODCTRL_BODFPWD_Pos (3UL) /*!< BODFPWD (Bit 3) */ +#define MCUCTRL_BODCTRL_BODFPWD_Msk (0x8UL) /*!< BODFPWD (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODCTRL_BODCPWD_Pos (2UL) /*!< BODCPWD (Bit 2) */ +#define MCUCTRL_BODCTRL_BODCPWD_Msk (0x4UL) /*!< BODCPWD (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODCTRL_BODHPWD_Pos (1UL) /*!< BODHPWD (Bit 1) */ +#define MCUCTRL_BODCTRL_BODHPWD_Msk (0x2UL) /*!< BODHPWD (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODCTRL_BODLPWD_Pos (0UL) /*!< BODLPWD (Bit 0) */ +#define MCUCTRL_BODCTRL_BODLPWD_Msk (0x1UL) /*!< BODLPWD (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCPWRDLY ======================================================= */ +#define MCUCTRL_ADCPWRDLY_ADCPWR1_Pos (8UL) /*!< ADCPWR1 (Bit 8) */ +#define MCUCTRL_ADCPWRDLY_ADCPWR1_Msk (0xff00UL) /*!< ADCPWR1 (Bitfield-Mask: 0xff) */ +#define MCUCTRL_ADCPWRDLY_ADCPWR0_Pos (0UL) /*!< ADCPWR0 (Bit 0) */ +#define MCUCTRL_ADCPWRDLY_ADCPWR0_Msk (0xffUL) /*!< ADCPWR0 (Bitfield-Mask: 0xff) */ +/* ======================================================== ADCCAL ========================================================= */ +#define MCUCTRL_ADCCAL_ADCCALIBRATED_Pos (1UL) /*!< ADCCALIBRATED (Bit 1) */ +#define MCUCTRL_ADCCAL_ADCCALIBRATED_Msk (0x2UL) /*!< ADCCALIBRATED (Bitfield-Mask: 0x01) */ +#define MCUCTRL_ADCCAL_CALONPWRUP_Pos (0UL) /*!< CALONPWRUP (Bit 0) */ +#define MCUCTRL_ADCCAL_CALONPWRUP_Msk (0x1UL) /*!< CALONPWRUP (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCBATTLOAD ====================================================== */ +#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Pos (0UL) /*!< BATTLOAD (Bit 0) */ +#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Msk (0x1UL) /*!< BATTLOAD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCTRIM ======================================================== */ +#define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Pos (11UL) /*!< ADCRFBUFIBTRIM (Bit 11) */ +#define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Msk (0x1800UL) /*!< ADCRFBUFIBTRIM (Bitfield-Mask: 0x03) */ +#define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Pos (6UL) /*!< ADCREFBUFTRIM (Bit 6) */ +#define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Msk (0x7c0UL) /*!< ADCREFBUFTRIM (Bitfield-Mask: 0x1f) */ +#define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Pos (0UL) /*!< ADCREFKEEPIBTRIM (Bit 0) */ +#define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Msk (0x3UL) /*!< ADCREFKEEPIBTRIM (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCREFCOMP ======================================================= */ +#define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Pos (16UL) /*!< ADCRFCMPEN (Bit 16) */ +#define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Msk (0x10000UL) /*!< ADCRFCMPEN (Bitfield-Mask: 0x01) */ +#define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Pos (8UL) /*!< ADCREFKEEPTRIM (Bit 8) */ +#define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Msk (0x1f00UL) /*!< ADCREFKEEPTRIM (Bitfield-Mask: 0x1f) */ +#define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Pos (0UL) /*!< ADC_REFCOMP_OUT (Bit 0) */ +#define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Msk (0x1UL) /*!< ADC_REFCOMP_OUT (Bitfield-Mask: 0x01) */ +/* ======================================================= XTALCTRL ======================================================== */ +#define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Pos (8UL) /*!< XTALICOMPTRIM (Bit 8) */ +#define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Msk (0x300UL) /*!< XTALICOMPTRIM (Bitfield-Mask: 0x03) */ +#define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Pos (6UL) /*!< XTALIBUFTRIM (Bit 6) */ +#define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Msk (0xc0UL) /*!< XTALIBUFTRIM (Bitfield-Mask: 0x03) */ +#define MCUCTRL_XTALCTRL_PWDBODXTAL_Pos (5UL) /*!< PWDBODXTAL (Bit 5) */ +#define MCUCTRL_XTALCTRL_PWDBODXTAL_Msk (0x20UL) /*!< PWDBODXTAL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Pos (4UL) /*!< PDNBCMPRXTAL (Bit 4) */ +#define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk (0x10UL) /*!< PDNBCMPRXTAL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Pos (3UL) /*!< PDNBCOREXTAL (Bit 3) */ +#define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk (0x8UL) /*!< PDNBCOREXTAL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Pos (2UL) /*!< BYPCMPRXTAL (Bit 2) */ +#define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk (0x4UL) /*!< BYPCMPRXTAL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Pos (1UL) /*!< FDBKDSBLXTAL (Bit 1) */ +#define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk (0x2UL) /*!< FDBKDSBLXTAL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_XTALCTRL_XTALSWE_Pos (0UL) /*!< XTALSWE (Bit 0) */ +#define MCUCTRL_XTALCTRL_XTALSWE_Msk (0x1UL) /*!< XTALSWE (Bitfield-Mask: 0x01) */ +/* ====================================================== XTALGENCTRL ====================================================== */ +#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Pos (8UL) /*!< XTALKSBIASTRIM (Bit 8) */ +#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Msk (0x3f00UL) /*!< XTALKSBIASTRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Pos (2UL) /*!< XTALBIASTRIM (Bit 2) */ +#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Msk (0xfcUL) /*!< XTALBIASTRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_XTALGENCTRL_ACWARMUP_Pos (0UL) /*!< ACWARMUP (Bit 0) */ +#define MCUCTRL_XTALGENCTRL_ACWARMUP_Msk (0x3UL) /*!< ACWARMUP (Bitfield-Mask: 0x03) */ +/* ======================================================= MISCCTRL ======================================================== */ +#define MCUCTRL_MISCCTRL_BLE_RESETN_Pos (5UL) /*!< BLE_RESETN (Bit 5) */ +#define MCUCTRL_MISCCTRL_BLE_RESETN_Msk (0x20UL) /*!< BLE_RESETN (Bitfield-Mask: 0x01) */ +#define MCUCTRL_MISCCTRL_RESERVED_RW_0_Pos (0UL) /*!< RESERVED_RW_0 (Bit 0) */ +#define MCUCTRL_MISCCTRL_RESERVED_RW_0_Msk (0x1fUL) /*!< RESERVED_RW_0 (Bitfield-Mask: 0x1f) */ +/* ====================================================== BOOTLOADER ======================================================= */ +#define MCUCTRL_BOOTLOADER_SECBOOTONRST_Pos (30UL) /*!< SECBOOTONRST (Bit 30) */ +#define MCUCTRL_BOOTLOADER_SECBOOTONRST_Msk (0xc0000000UL) /*!< SECBOOTONRST (Bitfield-Mask: 0x03) */ +#define MCUCTRL_BOOTLOADER_SECBOOT_Pos (28UL) /*!< SECBOOT (Bit 28) */ +#define MCUCTRL_BOOTLOADER_SECBOOT_Msk (0x30000000UL) /*!< SECBOOT (Bitfield-Mask: 0x03) */ +#define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Pos (26UL) /*!< SECBOOTFEATURE (Bit 26) */ +#define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Msk (0xc000000UL) /*!< SECBOOTFEATURE (Bitfield-Mask: 0x03) */ +#define MCUCTRL_BOOTLOADER_PROTLOCK_Pos (2UL) /*!< PROTLOCK (Bit 2) */ +#define MCUCTRL_BOOTLOADER_PROTLOCK_Msk (0x4UL) /*!< PROTLOCK (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BOOTLOADER_SBLOCK_Pos (1UL) /*!< SBLOCK (Bit 1) */ +#define MCUCTRL_BOOTLOADER_SBLOCK_Msk (0x2UL) /*!< SBLOCK (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Pos (0UL) /*!< BOOTLOADERLOW (Bit 0) */ +#define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Msk (0x1UL) /*!< BOOTLOADERLOW (Bitfield-Mask: 0x01) */ +/* ====================================================== SHADOWVALID ====================================================== */ +#define MCUCTRL_SHADOWVALID_INFO0_VALID_Pos (2UL) /*!< INFO0_VALID (Bit 2) */ +#define MCUCTRL_SHADOWVALID_INFO0_VALID_Msk (0x4UL) /*!< INFO0_VALID (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SHADOWVALID_BLDSLEEP_Pos (1UL) /*!< BLDSLEEP (Bit 1) */ +#define MCUCTRL_SHADOWVALID_BLDSLEEP_Msk (0x2UL) /*!< BLDSLEEP (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SHADOWVALID_VALID_Pos (0UL) /*!< VALID (Bit 0) */ +#define MCUCTRL_SHADOWVALID_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ +/* ======================================================= SCRATCH0 ======================================================== */ +#define MCUCTRL_SCRATCH0_SCRATCH0_Pos (0UL) /*!< SCRATCH0 (Bit 0) */ +#define MCUCTRL_SCRATCH0_SCRATCH0_Msk (0xffffffffUL) /*!< SCRATCH0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH1 ======================================================== */ +#define MCUCTRL_SCRATCH1_SCRATCH1_Pos (0UL) /*!< SCRATCH1 (Bit 0) */ +#define MCUCTRL_SCRATCH1_SCRATCH1_Msk (0xffffffffUL) /*!< SCRATCH1 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== ICODEFAULTADDR ===================================================== */ +#define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Pos (0UL) /*!< ICODEFAULTADDR (Bit 0) */ +#define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Msk (0xffffffffUL) /*!< ICODEFAULTADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DCODEFAULTADDR ===================================================== */ +#define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Pos (0UL) /*!< DCODEFAULTADDR (Bit 0) */ +#define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Msk (0xffffffffUL) /*!< DCODEFAULTADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SYSFAULTADDR ====================================================== */ +#define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Pos (0UL) /*!< SYSFAULTADDR (Bit 0) */ +#define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Msk (0xffffffffUL) /*!< SYSFAULTADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FAULTSTATUS ====================================================== */ +#define MCUCTRL_FAULTSTATUS_SYSFAULT_Pos (2UL) /*!< SYSFAULT (Bit 2) */ +#define MCUCTRL_FAULTSTATUS_SYSFAULT_Msk (0x4UL) /*!< SYSFAULT (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FAULTSTATUS_DCODEFAULT_Pos (1UL) /*!< DCODEFAULT (Bit 1) */ +#define MCUCTRL_FAULTSTATUS_DCODEFAULT_Msk (0x2UL) /*!< DCODEFAULT (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FAULTSTATUS_ICODEFAULT_Pos (0UL) /*!< ICODEFAULT (Bit 0) */ +#define MCUCTRL_FAULTSTATUS_ICODEFAULT_Msk (0x1UL) /*!< ICODEFAULT (Bitfield-Mask: 0x01) */ +/* ==================================================== FAULTCAPTUREEN ===================================================== */ +#define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Pos (0UL) /*!< FAULTCAPTUREEN (Bit 0) */ +#define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Msk (0x1UL) /*!< FAULTCAPTUREEN (Bitfield-Mask: 0x01) */ +/* ========================================================= DBGR1 ========================================================= */ +#define MCUCTRL_DBGR1_ONETO8_Pos (0UL) /*!< ONETO8 (Bit 0) */ +#define MCUCTRL_DBGR1_ONETO8_Msk (0xffffffffUL) /*!< ONETO8 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBGR2 ========================================================= */ +#define MCUCTRL_DBGR2_COOLCODE_Pos (0UL) /*!< COOLCODE (Bit 0) */ +#define MCUCTRL_DBGR2_COOLCODE_Msk (0xffffffffUL) /*!< COOLCODE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMUENABLE ======================================================= */ +#define MCUCTRL_PMUENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define MCUCTRL_PMUENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= TPIUCTRL ======================================================== */ +#define MCUCTRL_TPIUCTRL_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ +#define MCUCTRL_TPIUCTRL_CLKSEL_Msk (0x700UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */ +#define MCUCTRL_TPIUCTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define MCUCTRL_TPIUCTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ====================================================== OTAPOINTER ======================================================= */ +#define MCUCTRL_OTAPOINTER_OTAPOINTER_Pos (2UL) /*!< OTAPOINTER (Bit 2) */ +#define MCUCTRL_OTAPOINTER_OTAPOINTER_Msk (0xfffffffcUL) /*!< OTAPOINTER (Bitfield-Mask: 0x3fffffff) */ +#define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Pos (1UL) /*!< OTASBLUPDATE (Bit 1) */ +#define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Msk (0x2UL) /*!< OTASBLUPDATE (Bitfield-Mask: 0x01) */ +#define MCUCTRL_OTAPOINTER_OTAVALID_Pos (0UL) /*!< OTAVALID (Bit 0) */ +#define MCUCTRL_OTAPOINTER_OTAVALID_Msk (0x1UL) /*!< OTAVALID (Bitfield-Mask: 0x01) */ +/* ====================================================== APBDMACTRL ======================================================= */ +#define MCUCTRL_APBDMACTRL_HYSTERESIS_Pos (8UL) /*!< HYSTERESIS (Bit 8) */ +#define MCUCTRL_APBDMACTRL_HYSTERESIS_Msk (0xff00UL) /*!< HYSTERESIS (Bitfield-Mask: 0xff) */ +#define MCUCTRL_APBDMACTRL_DECODEABORT_Pos (1UL) /*!< DECODEABORT (Bit 1) */ +#define MCUCTRL_APBDMACTRL_DECODEABORT_Msk (0x2UL) /*!< DECODEABORT (Bitfield-Mask: 0x01) */ +#define MCUCTRL_APBDMACTRL_DMA_ENABLE_Pos (0UL) /*!< DMA_ENABLE (Bit 0) */ +#define MCUCTRL_APBDMACTRL_DMA_ENABLE_Msk (0x1UL) /*!< DMA_ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMMODE ======================================================== */ +#define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Pos (5UL) /*!< DPREFETCH_CACHE (Bit 5) */ +#define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk (0x20UL) /*!< DPREFETCH_CACHE (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SRAMMODE_DPREFETCH_Pos (4UL) /*!< DPREFETCH (Bit 4) */ +#define MCUCTRL_SRAMMODE_DPREFETCH_Msk (0x10UL) /*!< DPREFETCH (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Pos (1UL) /*!< IPREFETCH_CACHE (Bit 1) */ +#define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk (0x2UL) /*!< IPREFETCH_CACHE (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SRAMMODE_IPREFETCH_Pos (0UL) /*!< IPREFETCH (Bit 0) */ +#define MCUCTRL_SRAMMODE_IPREFETCH_Msk (0x1UL) /*!< IPREFETCH (Bitfield-Mask: 0x01) */ +/* ====================================================== KEXTCLKSEL ======================================================= */ +#define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Pos (0UL) /*!< KEXTCLKSEL (Bit 0) */ +#define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Msk (0xffffffffUL) /*!< KEXTCLKSEL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SIMOBUCK2 ======================================================= */ +#define MCUCTRL_SIMOBUCK2_RESERVED_RW_24_Pos (24UL) /*!< RESERVED_RW_24 (Bit 24) */ +#define MCUCTRL_SIMOBUCK2_RESERVED_RW_24_Msk (0xff000000UL) /*!< RESERVED_RW_24 (Bitfield-Mask: 0xff) */ +#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPLOWTONTRIM_Pos (20UL) /*!< SIMOBUCKCORELPLOWTONTRIM (Bit 20) */ +#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPLOWTONTRIM_Msk (0xf00000UL) /*!< SIMOBUCKCORELPLOWTONTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPHIGHTONTRIM_Pos (16UL) /*!< SIMOBUCKCORELPHIGHTONTRIM (Bit 16) */ +#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPHIGHTONTRIM_Msk (0xf0000UL) /*!< SIMOBUCKCORELPHIGHTONTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK2_RESERVED_RW_0_Pos (0UL) /*!< RESERVED_RW_0 (Bit 0) */ +#define MCUCTRL_SIMOBUCK2_RESERVED_RW_0_Msk (0xffffUL) /*!< RESERVED_RW_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SIMOBUCK3 ======================================================= */ +#define MCUCTRL_SIMOBUCK3_RESERVED_RW_31_Pos (31UL) /*!< RESERVED_RW_31 (Bit 31) */ +#define MCUCTRL_SIMOBUCK3_RESERVED_RW_31_Msk (0x80000000UL) /*!< RESERVED_RW_31 (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTONTRIM_Pos (27UL) /*!< SIMOBUCKMEMLPHIGHTONTRIM (Bit 27) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTONTRIM_Msk (0x78000000UL) /*!< SIMOBUCKMEMLPHIGHTONTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK3_RESERVED_RW_16_Pos (16UL) /*!< RESERVED_RW_16 (Bit 16) */ +#define MCUCTRL_SIMOBUCK3_RESERVED_RW_16_Msk (0x7ff0000UL) /*!< RESERVED_RW_16 (Bitfield-Mask: 0x7ff) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPLOWTOFFTRIM_Pos (12UL) /*!< SIMOBUCKMEMLPLOWTOFFTRIM (Bit 12) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPLOWTOFFTRIM_Msk (0xf000UL) /*!< SIMOBUCKMEMLPLOWTOFFTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTOFFTRIM_Pos (8UL) /*!< SIMOBUCKMEMLPHIGHTOFFTRIM (Bit 8) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTOFFTRIM_Msk (0xf00UL) /*!< SIMOBUCKMEMLPHIGHTOFFTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPLOWTOFFTRIM_Pos (4UL) /*!< SIMOBUCKCORELPLOWTOFFTRIM (Bit 4) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPLOWTOFFTRIM_Msk (0xf0UL) /*!< SIMOBUCKCORELPLOWTOFFTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPHIGHTOFFTRIM_Pos (0UL) /*!< SIMOBUCKCORELPHIGHTOFFTRIM (Bit 0) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPHIGHTOFFTRIM_Msk (0xfUL) /*!< SIMOBUCKCORELPHIGHTOFFTRIM (Bitfield-Mask: 0x0f) */ +/* ======================================================= SIMOBUCK4 ======================================================= */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2TIMEOUTEN_Pos (24UL) /*!< SIMOBUCKCOMP2TIMEOUTEN (Bit 24) */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2TIMEOUTEN_Msk (0x1000000UL) /*!< SIMOBUCKCOMP2TIMEOUTEN (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Pos (21UL) /*!< SIMOBUCKCLKDIVSEL (Bit 21) */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Msk (0x600000UL) /*!< SIMOBUCKCLKDIVSEL (Bitfield-Mask: 0x03) */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKMEMLPLOWTONTRIM_Pos (0UL) /*!< SIMOBUCKMEMLPLOWTONTRIM (Bit 0) */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKMEMLPLOWTONTRIM_Msk (0xfUL) /*!< SIMOBUCKMEMLPLOWTONTRIM (Bitfield-Mask: 0x0f) */ +/* ======================================================= BLEBUCK2 ======================================================== */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Pos (12UL) /*!< BLEBUCKTOND2ATRIM (Bit 12) */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Msk (0x3f000UL) /*!< BLEBUCKTOND2ATRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Pos (6UL) /*!< BLEBUCKTONHITRIM (Bit 6) */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Msk (0xfc0UL) /*!< BLEBUCKTONHITRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Pos (0UL) /*!< BLEBUCKTONLOWTRIM (Bit 0) */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Msk (0x3fUL) /*!< BLEBUCKTONLOWTRIM (Bitfield-Mask: 0x3f) */ +/* ====================================================== FLASHWPROT0 ====================================================== */ +#define MCUCTRL_FLASHWPROT0_FW0BITS_Pos (0UL) /*!< FW0BITS (Bit 0) */ +#define MCUCTRL_FLASHWPROT0_FW0BITS_Msk (0xffffffffUL) /*!< FW0BITS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FLASHWPROT1 ====================================================== */ +#define MCUCTRL_FLASHWPROT1_FW1BITS_Pos (0UL) /*!< FW1BITS (Bit 0) */ +#define MCUCTRL_FLASHWPROT1_FW1BITS_Msk (0xffffffffUL) /*!< FW1BITS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FLASHRPROT0 ====================================================== */ +#define MCUCTRL_FLASHRPROT0_FR0BITS_Pos (0UL) /*!< FR0BITS (Bit 0) */ +#define MCUCTRL_FLASHRPROT0_FR0BITS_Msk (0xffffffffUL) /*!< FR0BITS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FLASHRPROT1 ====================================================== */ +#define MCUCTRL_FLASHRPROT1_FR1BITS_Pos (0UL) /*!< FR1BITS (Bit 0) */ +#define MCUCTRL_FLASHRPROT1_FR1BITS_Msk (0xffffffffUL) /*!< FR1BITS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= DMASRAMWRITEPROTECT0 ================================================== */ +#define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Pos (0UL) /*!< DMA_WPROT0 (Bit 0) */ +#define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Msk (0xffffffffUL) /*!< DMA_WPROT0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= DMASRAMWRITEPROTECT1 ================================================== */ +#define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Pos (0UL) /*!< DMA_WPROT1 (Bit 0) */ +#define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Msk (0xffffUL) /*!< DMA_WPROT1 (Bitfield-Mask: 0xffff) */ +/* ================================================== DMASRAMREADPROTECT0 ================================================== */ +#define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Pos (0UL) /*!< DMA_RPROT0 (Bit 0) */ +#define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Msk (0xffffffffUL) /*!< DMA_RPROT0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== DMASRAMREADPROTECT1 ================================================== */ +#define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Pos (0UL) /*!< DMA_RPROT1 (Bit 0) */ +#define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Msk (0xffffUL) /*!< DMA_RPROT1 (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ MSPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define MSPI_CTRL_XFERBYTES_Pos (16UL) /*!< XFERBYTES (Bit 16) */ +#define MSPI_CTRL_XFERBYTES_Msk (0xffff0000UL) /*!< XFERBYTES (Bitfield-Mask: 0xffff) */ +#define MSPI_CTRL_PIOSCRAMBLE_Pos (11UL) /*!< PIOSCRAMBLE (Bit 11) */ +#define MSPI_CTRL_PIOSCRAMBLE_Msk (0x800UL) /*!< PIOSCRAMBLE (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_TXRX_Pos (10UL) /*!< TXRX (Bit 10) */ +#define MSPI_CTRL_TXRX_Msk (0x400UL) /*!< TXRX (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_SENDI_Pos (9UL) /*!< SENDI (Bit 9) */ +#define MSPI_CTRL_SENDI_Msk (0x200UL) /*!< SENDI (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_SENDA_Pos (8UL) /*!< SENDA (Bit 8) */ +#define MSPI_CTRL_SENDA_Msk (0x100UL) /*!< SENDA (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_ENTURN_Pos (7UL) /*!< ENTURN (Bit 7) */ +#define MSPI_CTRL_ENTURN_Msk (0x80UL) /*!< ENTURN (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_BIGENDIAN_Pos (6UL) /*!< BIGENDIAN (Bit 6) */ +#define MSPI_CTRL_BIGENDIAN_Msk (0x40UL) /*!< BIGENDIAN (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_QUADCMD_Pos (3UL) /*!< QUADCMD (Bit 3) */ +#define MSPI_CTRL_QUADCMD_Msk (0x8UL) /*!< QUADCMD (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_BUSY_Pos (2UL) /*!< BUSY (Bit 2) */ +#define MSPI_CTRL_BUSY_Msk (0x4UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_STATUS_Pos (1UL) /*!< STATUS (Bit 1) */ +#define MSPI_CTRL_STATUS_Msk (0x2UL) /*!< STATUS (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_START_Pos (0UL) /*!< START (Bit 0) */ +#define MSPI_CTRL_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================== CFG ========================================================== */ +#define MSPI_CFG_CPOL_Pos (17UL) /*!< CPOL (Bit 17) */ +#define MSPI_CFG_CPOL_Msk (0x20000UL) /*!< CPOL (Bitfield-Mask: 0x01) */ +#define MSPI_CFG_CPHA_Pos (16UL) /*!< CPHA (Bit 16) */ +#define MSPI_CFG_CPHA_Msk (0x10000UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +#define MSPI_CFG_TURNAROUND_Pos (8UL) /*!< TURNAROUND (Bit 8) */ +#define MSPI_CFG_TURNAROUND_Msk (0x3f00UL) /*!< TURNAROUND (Bitfield-Mask: 0x3f) */ +#define MSPI_CFG_SEPIO_Pos (7UL) /*!< SEPIO (Bit 7) */ +#define MSPI_CFG_SEPIO_Msk (0x80UL) /*!< SEPIO (Bitfield-Mask: 0x01) */ +#define MSPI_CFG_ISIZE_Pos (6UL) /*!< ISIZE (Bit 6) */ +#define MSPI_CFG_ISIZE_Msk (0x40UL) /*!< ISIZE (Bitfield-Mask: 0x01) */ +#define MSPI_CFG_ASIZE_Pos (4UL) /*!< ASIZE (Bit 4) */ +#define MSPI_CFG_ASIZE_Msk (0x30UL) /*!< ASIZE (Bitfield-Mask: 0x03) */ +#define MSPI_CFG_DEVCFG_Pos (0UL) /*!< DEVCFG (Bit 0) */ +#define MSPI_CFG_DEVCFG_Msk (0xfUL) /*!< DEVCFG (Bitfield-Mask: 0x0f) */ +/* ========================================================= ADDR ========================================================== */ +#define MSPI_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define MSPI_ADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INSTR ========================================================= */ +#define MSPI_INSTR_INSTR_Pos (0UL) /*!< INSTR (Bit 0) */ +#define MSPI_INSTR_INSTR_Msk (0xffffUL) /*!< INSTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== TXFIFO ========================================================= */ +#define MSPI_TXFIFO_TXFIFO_Pos (0UL) /*!< TXFIFO (Bit 0) */ +#define MSPI_TXFIFO_TXFIFO_Msk (0xffffffffUL) /*!< TXFIFO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== RXFIFO ========================================================= */ +#define MSPI_RXFIFO_RXFIFO_Pos (0UL) /*!< RXFIFO (Bit 0) */ +#define MSPI_RXFIFO_RXFIFO_Msk (0xffffffffUL) /*!< RXFIFO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TXENTRIES ======================================================= */ +#define MSPI_TXENTRIES_TXENTRIES_Pos (0UL) /*!< TXENTRIES (Bit 0) */ +#define MSPI_TXENTRIES_TXENTRIES_Msk (0x1fUL) /*!< TXENTRIES (Bitfield-Mask: 0x1f) */ +/* ======================================================= RXENTRIES ======================================================= */ +#define MSPI_RXENTRIES_RXENTRIES_Pos (0UL) /*!< RXENTRIES (Bit 0) */ +#define MSPI_RXENTRIES_RXENTRIES_Msk (0x1fUL) /*!< RXENTRIES (Bitfield-Mask: 0x1f) */ +/* ======================================================= THRESHOLD ======================================================= */ +#define MSPI_THRESHOLD_RXTHRESH_Pos (8UL) /*!< RXTHRESH (Bit 8) */ +#define MSPI_THRESHOLD_RXTHRESH_Msk (0x1f00UL) /*!< RXTHRESH (Bitfield-Mask: 0x1f) */ +#define MSPI_THRESHOLD_TXTHRESH_Pos (0UL) /*!< TXTHRESH (Bit 0) */ +#define MSPI_THRESHOLD_TXTHRESH_Msk (0x1fUL) /*!< TXTHRESH (Bitfield-Mask: 0x1f) */ +/* ======================================================== MSPICFG ======================================================== */ +#define MSPI_MSPICFG_PRSTN_Pos (31UL) /*!< PRSTN (Bit 31) */ +#define MSPI_MSPICFG_PRSTN_Msk (0x80000000UL) /*!< PRSTN (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_IPRSTN_Pos (30UL) /*!< IPRSTN (Bit 30) */ +#define MSPI_MSPICFG_IPRSTN_Msk (0x40000000UL) /*!< IPRSTN (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_FIFORESET_Pos (29UL) /*!< FIFORESET (Bit 29) */ +#define MSPI_MSPICFG_FIFORESET_Msk (0x20000000UL) /*!< FIFORESET (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_CLKDIV_Pos (8UL) /*!< CLKDIV (Bit 8) */ +#define MSPI_MSPICFG_CLKDIV_Msk (0x3f00UL) /*!< CLKDIV (Bitfield-Mask: 0x3f) */ +#define MSPI_MSPICFG_IOMSEL_Pos (4UL) /*!< IOMSEL (Bit 4) */ +#define MSPI_MSPICFG_IOMSEL_Msk (0x70UL) /*!< IOMSEL (Bitfield-Mask: 0x07) */ +#define MSPI_MSPICFG_TXNEG_Pos (3UL) /*!< TXNEG (Bit 3) */ +#define MSPI_MSPICFG_TXNEG_Msk (0x8UL) /*!< TXNEG (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_RXNEG_Pos (2UL) /*!< RXNEG (Bit 2) */ +#define MSPI_MSPICFG_RXNEG_Msk (0x4UL) /*!< RXNEG (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_RXCAP_Pos (1UL) /*!< RXCAP (Bit 1) */ +#define MSPI_MSPICFG_RXCAP_Msk (0x2UL) /*!< RXCAP (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_APBCLK_Pos (0UL) /*!< APBCLK (Bit 0) */ +#define MSPI_MSPICFG_APBCLK_Msk (0x1UL) /*!< APBCLK (Bitfield-Mask: 0x01) */ +/* ======================================================== PADCFG ========================================================= */ +#define MSPI_PADCFG_REVCS_Pos (21UL) /*!< REVCS (Bit 21) */ +#define MSPI_PADCFG_REVCS_Msk (0x200000UL) /*!< REVCS (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_IN3_Pos (20UL) /*!< IN3 (Bit 20) */ +#define MSPI_PADCFG_IN3_Msk (0x100000UL) /*!< IN3 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_IN2_Pos (19UL) /*!< IN2 (Bit 19) */ +#define MSPI_PADCFG_IN2_Msk (0x80000UL) /*!< IN2 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_IN1_Pos (18UL) /*!< IN1 (Bit 18) */ +#define MSPI_PADCFG_IN1_Msk (0x40000UL) /*!< IN1 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_IN0_Pos (16UL) /*!< IN0 (Bit 16) */ +#define MSPI_PADCFG_IN0_Msk (0x30000UL) /*!< IN0 (Bitfield-Mask: 0x03) */ +#define MSPI_PADCFG_OUT7_Pos (4UL) /*!< OUT7 (Bit 4) */ +#define MSPI_PADCFG_OUT7_Msk (0x10UL) /*!< OUT7 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_OUT6_Pos (3UL) /*!< OUT6 (Bit 3) */ +#define MSPI_PADCFG_OUT6_Msk (0x8UL) /*!< OUT6 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_OUT5_Pos (2UL) /*!< OUT5 (Bit 2) */ +#define MSPI_PADCFG_OUT5_Msk (0x4UL) /*!< OUT5 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_OUT4_Pos (1UL) /*!< OUT4 (Bit 1) */ +#define MSPI_PADCFG_OUT4_Msk (0x2UL) /*!< OUT4 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_OUT3_Pos (0UL) /*!< OUT3 (Bit 0) */ +#define MSPI_PADCFG_OUT3_Msk (0x1UL) /*!< OUT3 (Bitfield-Mask: 0x01) */ +/* ======================================================= PADOUTEN ======================================================== */ +#define MSPI_PADOUTEN_OUTEN_Pos (0UL) /*!< OUTEN (Bit 0) */ +#define MSPI_PADOUTEN_OUTEN_Msk (0x1ffUL) /*!< OUTEN (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FLASH ========================================================= */ +#define MSPI_FLASH_READINSTR_Pos (24UL) /*!< READINSTR (Bit 24) */ +#define MSPI_FLASH_READINSTR_Msk (0xff000000UL) /*!< READINSTR (Bitfield-Mask: 0xff) */ +#define MSPI_FLASH_WRITEINSTR_Pos (16UL) /*!< WRITEINSTR (Bit 16) */ +#define MSPI_FLASH_WRITEINSTR_Msk (0xff0000UL) /*!< WRITEINSTR (Bitfield-Mask: 0xff) */ +#define MSPI_FLASH_XIPMIXED_Pos (8UL) /*!< XIPMIXED (Bit 8) */ +#define MSPI_FLASH_XIPMIXED_Msk (0x700UL) /*!< XIPMIXED (Bitfield-Mask: 0x07) */ +#define MSPI_FLASH_XIPSENDI_Pos (7UL) /*!< XIPSENDI (Bit 7) */ +#define MSPI_FLASH_XIPSENDI_Msk (0x80UL) /*!< XIPSENDI (Bitfield-Mask: 0x01) */ +#define MSPI_FLASH_XIPSENDA_Pos (6UL) /*!< XIPSENDA (Bit 6) */ +#define MSPI_FLASH_XIPSENDA_Msk (0x40UL) /*!< XIPSENDA (Bitfield-Mask: 0x01) */ +#define MSPI_FLASH_XIPENTURN_Pos (5UL) /*!< XIPENTURN (Bit 5) */ +#define MSPI_FLASH_XIPENTURN_Msk (0x20UL) /*!< XIPENTURN (Bitfield-Mask: 0x01) */ +#define MSPI_FLASH_XIPBIGENDIAN_Pos (4UL) /*!< XIPBIGENDIAN (Bit 4) */ +#define MSPI_FLASH_XIPBIGENDIAN_Msk (0x10UL) /*!< XIPBIGENDIAN (Bitfield-Mask: 0x01) */ +#define MSPI_FLASH_XIPACK_Pos (2UL) /*!< XIPACK (Bit 2) */ +#define MSPI_FLASH_XIPACK_Msk (0xcUL) /*!< XIPACK (Bitfield-Mask: 0x03) */ +#define MSPI_FLASH_XIPEN_Pos (0UL) /*!< XIPEN (Bit 0) */ +#define MSPI_FLASH_XIPEN_Msk (0x1UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SCRAMBLING ======================================================= */ +#define MSPI_SCRAMBLING_SCRENABLE_Pos (31UL) /*!< SCRENABLE (Bit 31) */ +#define MSPI_SCRAMBLING_SCRENABLE_Msk (0x80000000UL) /*!< SCRENABLE (Bitfield-Mask: 0x01) */ +#define MSPI_SCRAMBLING_SCREND_Pos (16UL) /*!< SCREND (Bit 16) */ +#define MSPI_SCRAMBLING_SCREND_Msk (0x3ff0000UL) /*!< SCREND (Bitfield-Mask: 0x3ff) */ +#define MSPI_SCRAMBLING_SCRSTART_Pos (0UL) /*!< SCRSTART (Bit 0) */ +#define MSPI_SCRAMBLING_SCRSTART_Msk (0x3ffUL) /*!< SCRSTART (Bitfield-Mask: 0x3ff) */ +/* ========================================================= INTEN ========================================================= */ +#define MSPI_INTEN_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */ +#define MSPI_INTEN_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */ +#define MSPI_INTEN_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */ +#define MSPI_INTEN_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */ +#define MSPI_INTEN_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */ +#define MSPI_INTEN_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define MSPI_INTEN_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define MSPI_INTEN_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_RXF_Pos (5UL) /*!< RXF (Bit 5) */ +#define MSPI_INTEN_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_RXO_Pos (4UL) /*!< RXO (Bit 4) */ +#define MSPI_INTEN_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_RXU_Pos (3UL) /*!< RXU (Bit 3) */ +#define MSPI_INTEN_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_TXO_Pos (2UL) /*!< TXO (Bit 2) */ +#define MSPI_INTEN_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_TXE_Pos (1UL) /*!< TXE (Bit 1) */ +#define MSPI_INTEN_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define MSPI_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define MSPI_INTSTAT_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */ +#define MSPI_INTSTAT_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */ +#define MSPI_INTSTAT_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */ +#define MSPI_INTSTAT_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */ +#define MSPI_INTSTAT_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */ +#define MSPI_INTSTAT_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define MSPI_INTSTAT_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define MSPI_INTSTAT_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_RXF_Pos (5UL) /*!< RXF (Bit 5) */ +#define MSPI_INTSTAT_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_RXO_Pos (4UL) /*!< RXO (Bit 4) */ +#define MSPI_INTSTAT_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_RXU_Pos (3UL) /*!< RXU (Bit 3) */ +#define MSPI_INTSTAT_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_TXO_Pos (2UL) /*!< TXO (Bit 2) */ +#define MSPI_INTSTAT_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_TXE_Pos (1UL) /*!< TXE (Bit 1) */ +#define MSPI_INTSTAT_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define MSPI_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define MSPI_INTCLR_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */ +#define MSPI_INTCLR_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */ +#define MSPI_INTCLR_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */ +#define MSPI_INTCLR_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */ +#define MSPI_INTCLR_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */ +#define MSPI_INTCLR_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define MSPI_INTCLR_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define MSPI_INTCLR_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_RXF_Pos (5UL) /*!< RXF (Bit 5) */ +#define MSPI_INTCLR_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_RXO_Pos (4UL) /*!< RXO (Bit 4) */ +#define MSPI_INTCLR_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_RXU_Pos (3UL) /*!< RXU (Bit 3) */ +#define MSPI_INTCLR_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_TXO_Pos (2UL) /*!< TXO (Bit 2) */ +#define MSPI_INTCLR_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_TXE_Pos (1UL) /*!< TXE (Bit 1) */ +#define MSPI_INTCLR_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define MSPI_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define MSPI_INTSET_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */ +#define MSPI_INTSET_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */ +#define MSPI_INTSET_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */ +#define MSPI_INTSET_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */ +#define MSPI_INTSET_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */ +#define MSPI_INTSET_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define MSPI_INTSET_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define MSPI_INTSET_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_RXF_Pos (5UL) /*!< RXF (Bit 5) */ +#define MSPI_INTSET_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_RXO_Pos (4UL) /*!< RXO (Bit 4) */ +#define MSPI_INTSET_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_RXU_Pos (3UL) /*!< RXU (Bit 3) */ +#define MSPI_INTSET_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_TXO_Pos (2UL) /*!< TXO (Bit 2) */ +#define MSPI_INTSET_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_TXE_Pos (1UL) /*!< TXE (Bit 1) */ +#define MSPI_INTSET_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define MSPI_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACFG ========================================================= */ +#define MSPI_DMACFG_DMAPWROFF_Pos (18UL) /*!< DMAPWROFF (Bit 18) */ +#define MSPI_DMACFG_DMAPWROFF_Msk (0x40000UL) /*!< DMAPWROFF (Bitfield-Mask: 0x01) */ +#define MSPI_DMACFG_DMAPRI_Pos (3UL) /*!< DMAPRI (Bit 3) */ +#define MSPI_DMACFG_DMAPRI_Msk (0x18UL) /*!< DMAPRI (Bitfield-Mask: 0x03) */ +#define MSPI_DMACFG_DMADIR_Pos (2UL) /*!< DMADIR (Bit 2) */ +#define MSPI_DMACFG_DMADIR_Msk (0x4UL) /*!< DMADIR (Bitfield-Mask: 0x01) */ +#define MSPI_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */ +#define MSPI_DMACFG_DMAEN_Msk (0x3UL) /*!< DMAEN (Bitfield-Mask: 0x03) */ +/* ======================================================== DMASTAT ======================================================== */ +#define MSPI_DMASTAT_SCRERR_Pos (3UL) /*!< SCRERR (Bit 3) */ +#define MSPI_DMASTAT_SCRERR_Msk (0x8UL) /*!< SCRERR (Bitfield-Mask: 0x01) */ +#define MSPI_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */ +#define MSPI_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */ +#define MSPI_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */ +#define MSPI_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */ +#define MSPI_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */ +#define MSPI_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATARGADDR ====================================================== */ +#define MSPI_DMATARGADDR_TARGADDR_Pos (0UL) /*!< TARGADDR (Bit 0) */ +#define MSPI_DMATARGADDR_TARGADDR_Msk (0xffffffffUL) /*!< TARGADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DMADEVADDR ======================================================= */ +#define MSPI_DMADEVADDR_DEVADDR_Pos (0UL) /*!< DEVADDR (Bit 0) */ +#define MSPI_DMADEVADDR_DEVADDR_Msk (0xffffffffUL) /*!< DEVADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +#define MSPI_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */ +#define MSPI_DMATOTCOUNT_TOTCOUNT_Msk (0xffffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= DMABCOUNT ======================================================= */ +#define MSPI_DMABCOUNT_BCOUNT_Pos (0UL) /*!< BCOUNT (Bit 0) */ +#define MSPI_DMABCOUNT_BCOUNT_Msk (0xffUL) /*!< BCOUNT (Bitfield-Mask: 0xff) */ +/* ======================================================= DMATHRESH ======================================================= */ +#define MSPI_DMATHRESH_DMATHRESH_Pos (0UL) /*!< DMATHRESH (Bit 0) */ +#define MSPI_DMATHRESH_DMATHRESH_Msk (0xfUL) /*!< DMATHRESH (Bitfield-Mask: 0x0f) */ +/* ========================================================= CQCFG ========================================================= */ +#define MSPI_CQCFG_CQAUTOCLEARMASK_Pos (3UL) /*!< CQAUTOCLEARMASK (Bit 3) */ +#define MSPI_CQCFG_CQAUTOCLEARMASK_Msk (0x8UL) /*!< CQAUTOCLEARMASK (Bitfield-Mask: 0x01) */ +#define MSPI_CQCFG_CQPWROFF_Pos (2UL) /*!< CQPWROFF (Bit 2) */ +#define MSPI_CQCFG_CQPWROFF_Msk (0x4UL) /*!< CQPWROFF (Bitfield-Mask: 0x01) */ +#define MSPI_CQCFG_CQPRI_Pos (1UL) /*!< CQPRI (Bit 1) */ +#define MSPI_CQCFG_CQPRI_Msk (0x2UL) /*!< CQPRI (Bitfield-Mask: 0x01) */ +#define MSPI_CQCFG_CQEN_Pos (0UL) /*!< CQEN (Bit 0) */ +#define MSPI_CQCFG_CQEN_Msk (0x1UL) /*!< CQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CQADDR ========================================================= */ +#define MSPI_CQADDR_CQADDR_Pos (0UL) /*!< CQADDR (Bit 0) */ +#define MSPI_CQADDR_CQADDR_Msk (0x1fffffffUL) /*!< CQADDR (Bitfield-Mask: 0x1fffffff) */ +/* ======================================================== CQSTAT ========================================================= */ +#define MSPI_CQSTAT_CQPAUSED_Pos (3UL) /*!< CQPAUSED (Bit 3) */ +#define MSPI_CQSTAT_CQPAUSED_Msk (0x8UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define MSPI_CQSTAT_CQERR_Pos (2UL) /*!< CQERR (Bit 2) */ +#define MSPI_CQSTAT_CQERR_Msk (0x4UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define MSPI_CQSTAT_CQCPL_Pos (1UL) /*!< CQCPL (Bit 1) */ +#define MSPI_CQSTAT_CQCPL_Msk (0x2UL) /*!< CQCPL (Bitfield-Mask: 0x01) */ +#define MSPI_CQSTAT_CQTIP_Pos (0UL) /*!< CQTIP (Bit 0) */ +#define MSPI_CQSTAT_CQTIP_Msk (0x1UL) /*!< CQTIP (Bitfield-Mask: 0x01) */ +/* ======================================================== CQFLAGS ======================================================== */ +#define MSPI_CQFLAGS_CQFLAGS_Pos (0UL) /*!< CQFLAGS (Bit 0) */ +#define MSPI_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< CQFLAGS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CQSETCLEAR ======================================================= */ +#define MSPI_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< CQFCLR (Bit 16) */ +#define MSPI_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< CQFCLR (Bitfield-Mask: 0xff) */ +#define MSPI_CQSETCLEAR_CQFTOGGLE_Pos (8UL) /*!< CQFTOGGLE (Bit 8) */ +#define MSPI_CQSETCLEAR_CQFTOGGLE_Msk (0xff00UL) /*!< CQFTOGGLE (Bitfield-Mask: 0xff) */ +#define MSPI_CQSETCLEAR_CQFSET_Pos (0UL) /*!< CQFSET (Bit 0) */ +#define MSPI_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< CQFSET (Bitfield-Mask: 0xff) */ +/* ======================================================== CQPAUSE ======================================================== */ +#define MSPI_CQPAUSE_CQMASK_Pos (0UL) /*!< CQMASK (Bit 0) */ +#define MSPI_CQPAUSE_CQMASK_Msk (0xffffUL) /*!< CQMASK (Bitfield-Mask: 0xffff) */ +/* ======================================================= CQCURIDX ======================================================== */ +#define MSPI_CQCURIDX_CQCURIDX_Pos (0UL) /*!< CQCURIDX (Bit 0) */ +#define MSPI_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< CQCURIDX (Bitfield-Mask: 0xff) */ +/* ======================================================= CQENDIDX ======================================================== */ +#define MSPI_CQENDIDX_CQENDIDX_Pos (0UL) /*!< CQENDIDX (Bit 0) */ +#define MSPI_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< CQENDIDX (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PCFG ========================================================== */ +#define PDM_PCFG_LRSWAP_Pos (31UL) /*!< LRSWAP (Bit 31) */ +#define PDM_PCFG_LRSWAP_Msk (0x80000000UL) /*!< LRSWAP (Bitfield-Mask: 0x01) */ +#define PDM_PCFG_PGARIGHT_Pos (26UL) /*!< PGARIGHT (Bit 26) */ +#define PDM_PCFG_PGARIGHT_Msk (0x7c000000UL) /*!< PGARIGHT (Bitfield-Mask: 0x1f) */ +#define PDM_PCFG_PGALEFT_Pos (21UL) /*!< PGALEFT (Bit 21) */ +#define PDM_PCFG_PGALEFT_Msk (0x3e00000UL) /*!< PGALEFT (Bitfield-Mask: 0x1f) */ +#define PDM_PCFG_MCLKDIV_Pos (17UL) /*!< MCLKDIV (Bit 17) */ +#define PDM_PCFG_MCLKDIV_Msk (0x60000UL) /*!< MCLKDIV (Bitfield-Mask: 0x03) */ +#define PDM_PCFG_SINCRATE_Pos (10UL) /*!< SINCRATE (Bit 10) */ +#define PDM_PCFG_SINCRATE_Msk (0x1fc00UL) /*!< SINCRATE (Bitfield-Mask: 0x7f) */ +#define PDM_PCFG_ADCHPD_Pos (9UL) /*!< ADCHPD (Bit 9) */ +#define PDM_PCFG_ADCHPD_Msk (0x200UL) /*!< ADCHPD (Bitfield-Mask: 0x01) */ +#define PDM_PCFG_HPCUTOFF_Pos (5UL) /*!< HPCUTOFF (Bit 5) */ +#define PDM_PCFG_HPCUTOFF_Msk (0x1e0UL) /*!< HPCUTOFF (Bitfield-Mask: 0x0f) */ +#define PDM_PCFG_CYCLES_Pos (2UL) /*!< CYCLES (Bit 2) */ +#define PDM_PCFG_CYCLES_Msk (0x1cUL) /*!< CYCLES (Bitfield-Mask: 0x07) */ +#define PDM_PCFG_SOFTMUTE_Pos (1UL) /*!< SOFTMUTE (Bit 1) */ +#define PDM_PCFG_SOFTMUTE_Msk (0x2UL) /*!< SOFTMUTE (Bitfield-Mask: 0x01) */ +#define PDM_PCFG_PDMCOREEN_Pos (0UL) /*!< PDMCOREEN (Bit 0) */ +#define PDM_PCFG_PDMCOREEN_Msk (0x1UL) /*!< PDMCOREEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VCFG ========================================================== */ +#define PDM_VCFG_IOCLKEN_Pos (31UL) /*!< IOCLKEN (Bit 31) */ +#define PDM_VCFG_IOCLKEN_Msk (0x80000000UL) /*!< IOCLKEN (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_RSTB_Pos (30UL) /*!< RSTB (Bit 30) */ +#define PDM_VCFG_RSTB_Msk (0x40000000UL) /*!< RSTB (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_PDMCLKSEL_Pos (27UL) /*!< PDMCLKSEL (Bit 27) */ +#define PDM_VCFG_PDMCLKSEL_Msk (0x38000000UL) /*!< PDMCLKSEL (Bitfield-Mask: 0x07) */ +#define PDM_VCFG_PDMCLKEN_Pos (26UL) /*!< PDMCLKEN (Bit 26) */ +#define PDM_VCFG_PDMCLKEN_Msk (0x4000000UL) /*!< PDMCLKEN (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_I2SEN_Pos (20UL) /*!< I2SEN (Bit 20) */ +#define PDM_VCFG_I2SEN_Msk (0x100000UL) /*!< I2SEN (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_BCLKINV_Pos (19UL) /*!< BCLKINV (Bit 19) */ +#define PDM_VCFG_BCLKINV_Msk (0x80000UL) /*!< BCLKINV (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_DMICKDEL_Pos (17UL) /*!< DMICKDEL (Bit 17) */ +#define PDM_VCFG_DMICKDEL_Msk (0x20000UL) /*!< DMICKDEL (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_SELAP_Pos (16UL) /*!< SELAP (Bit 16) */ +#define PDM_VCFG_SELAP_Msk (0x10000UL) /*!< SELAP (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_PCMPACK_Pos (8UL) /*!< PCMPACK (Bit 8) */ +#define PDM_VCFG_PCMPACK_Msk (0x100UL) /*!< PCMPACK (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_CHSET_Pos (3UL) /*!< CHSET (Bit 3) */ +#define PDM_VCFG_CHSET_Msk (0x18UL) /*!< CHSET (Bitfield-Mask: 0x03) */ +/* ======================================================= VOICESTAT ======================================================= */ +#define PDM_VOICESTAT_FIFOCNT_Pos (0UL) /*!< FIFOCNT (Bit 0) */ +#define PDM_VOICESTAT_FIFOCNT_Msk (0x3fUL) /*!< FIFOCNT (Bitfield-Mask: 0x3f) */ +/* ======================================================= FIFOREAD ======================================================== */ +#define PDM_FIFOREAD_FIFOREAD_Pos (0UL) /*!< FIFOREAD (Bit 0) */ +#define PDM_FIFOREAD_FIFOREAD_Msk (0xffffffffUL) /*!< FIFOREAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FIFOFLUSH ======================================================= */ +#define PDM_FIFOFLUSH_FIFOFLUSH_Pos (0UL) /*!< FIFOFLUSH (Bit 0) */ +#define PDM_FIFOFLUSH_FIFOFLUSH_Msk (0x1UL) /*!< FIFOFLUSH (Bitfield-Mask: 0x01) */ +/* ======================================================== FIFOTHR ======================================================== */ +#define PDM_FIFOTHR_FIFOTHR_Pos (0UL) /*!< FIFOTHR (Bit 0) */ +#define PDM_FIFOTHR_FIFOTHR_Msk (0x1fUL) /*!< FIFOTHR (Bitfield-Mask: 0x1f) */ +/* ========================================================= INTEN ========================================================= */ +#define PDM_INTEN_DERR_Pos (4UL) /*!< DERR (Bit 4) */ +#define PDM_INTEN_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define PDM_INTEN_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */ +#define PDM_INTEN_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define PDM_INTEN_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTEN_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTEN_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTEN_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTEN_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTEN_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define PDM_INTSTAT_DERR_Pos (4UL) /*!< DERR (Bit 4) */ +#define PDM_INTSTAT_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define PDM_INTSTAT_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */ +#define PDM_INTSTAT_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define PDM_INTSTAT_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTSTAT_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTSTAT_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTSTAT_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTSTAT_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTSTAT_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define PDM_INTCLR_DERR_Pos (4UL) /*!< DERR (Bit 4) */ +#define PDM_INTCLR_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define PDM_INTCLR_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */ +#define PDM_INTCLR_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define PDM_INTCLR_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTCLR_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTCLR_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTCLR_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTCLR_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTCLR_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define PDM_INTSET_DERR_Pos (4UL) /*!< DERR (Bit 4) */ +#define PDM_INTSET_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define PDM_INTSET_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */ +#define PDM_INTSET_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define PDM_INTSET_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTSET_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTSET_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTSET_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTSET_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTSET_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================= DMATRIGEN ======================================================= */ +#define PDM_DMATRIGEN_DTHR90_Pos (1UL) /*!< DTHR90 (Bit 1) */ +#define PDM_DMATRIGEN_DTHR90_Msk (0x2UL) /*!< DTHR90 (Bitfield-Mask: 0x01) */ +#define PDM_DMATRIGEN_DTHR_Pos (0UL) /*!< DTHR (Bit 0) */ +#define PDM_DMATRIGEN_DTHR_Msk (0x1UL) /*!< DTHR (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +#define PDM_DMATRIGSTAT_DTHR90STAT_Pos (1UL) /*!< DTHR90STAT (Bit 1) */ +#define PDM_DMATRIGSTAT_DTHR90STAT_Msk (0x2UL) /*!< DTHR90STAT (Bitfield-Mask: 0x01) */ +#define PDM_DMATRIGSTAT_DTHRSTAT_Pos (0UL) /*!< DTHRSTAT (Bit 0) */ +#define PDM_DMATRIGSTAT_DTHRSTAT_Msk (0x1UL) /*!< DTHRSTAT (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACFG ========================================================= */ +#define PDM_DMACFG_DPWROFF_Pos (10UL) /*!< DPWROFF (Bit 10) */ +#define PDM_DMACFG_DPWROFF_Msk (0x400UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */ +#define PDM_DMACFG_DAUTOHIP_Pos (9UL) /*!< DAUTOHIP (Bit 9) */ +#define PDM_DMACFG_DAUTOHIP_Msk (0x200UL) /*!< DAUTOHIP (Bitfield-Mask: 0x01) */ +#define PDM_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */ +#define PDM_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */ +#define PDM_DMACFG_DMADIR_Pos (2UL) /*!< DMADIR (Bit 2) */ +#define PDM_DMACFG_DMADIR_Msk (0x4UL) /*!< DMADIR (Bitfield-Mask: 0x01) */ +#define PDM_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */ +#define PDM_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +#define PDM_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */ +#define PDM_DMATOTCOUNT_TOTCOUNT_Msk (0xfffffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xfffff) */ +/* ====================================================== DMATARGADDR ====================================================== */ +#define PDM_DMATARGADDR_UTARGADDR_Pos (20UL) /*!< UTARGADDR (Bit 20) */ +#define PDM_DMATARGADDR_UTARGADDR_Msk (0xfff00000UL) /*!< UTARGADDR (Bitfield-Mask: 0xfff) */ +#define PDM_DMATARGADDR_LTARGADDR_Pos (0UL) /*!< LTARGADDR (Bit 0) */ +#define PDM_DMATARGADDR_LTARGADDR_Msk (0xfffffUL) /*!< LTARGADDR (Bitfield-Mask: 0xfffff) */ +/* ======================================================== DMASTAT ======================================================== */ +#define PDM_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */ +#define PDM_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */ +#define PDM_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */ +#define PDM_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */ +#define PDM_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */ +#define PDM_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ PWRCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SUPPLYSRC ======================================================= */ +#define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Pos (0UL) /*!< BLEBUCKEN (Bit 0) */ +#define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Msk (0x1UL) /*!< BLEBUCKEN (Bitfield-Mask: 0x01) */ +/* ===================================================== SUPPLYSTATUS ====================================================== */ +#define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Pos (1UL) /*!< BLEBUCKON (Bit 1) */ +#define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Msk (0x2UL) /*!< BLEBUCKON (Bitfield-Mask: 0x01) */ +#define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Pos (0UL) /*!< SIMOBUCKON (Bit 0) */ +#define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Msk (0x1UL) /*!< SIMOBUCKON (Bitfield-Mask: 0x01) */ +/* ======================================================= DEVPWREN ======================================================== */ +#define PWRCTRL_DEVPWREN_PWRBLEL_Pos (13UL) /*!< PWRBLEL (Bit 13) */ +#define PWRCTRL_DEVPWREN_PWRBLEL_Msk (0x2000UL) /*!< PWRBLEL (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRPDM_Pos (12UL) /*!< PWRPDM (Bit 12) */ +#define PWRCTRL_DEVPWREN_PWRPDM_Msk (0x1000UL) /*!< PWRPDM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRMSPI_Pos (11UL) /*!< PWRMSPI (Bit 11) */ +#define PWRCTRL_DEVPWREN_PWRMSPI_Msk (0x800UL) /*!< PWRMSPI (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRSCARD_Pos (10UL) /*!< PWRSCARD (Bit 10) */ +#define PWRCTRL_DEVPWREN_PWRSCARD_Msk (0x400UL) /*!< PWRSCARD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRADC_Pos (9UL) /*!< PWRADC (Bit 9) */ +#define PWRCTRL_DEVPWREN_PWRADC_Msk (0x200UL) /*!< PWRADC (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRUART1_Pos (8UL) /*!< PWRUART1 (Bit 8) */ +#define PWRCTRL_DEVPWREN_PWRUART1_Msk (0x100UL) /*!< PWRUART1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRUART0_Pos (7UL) /*!< PWRUART0 (Bit 7) */ +#define PWRCTRL_DEVPWREN_PWRUART0_Msk (0x80UL) /*!< PWRUART0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM5_Pos (6UL) /*!< PWRIOM5 (Bit 6) */ +#define PWRCTRL_DEVPWREN_PWRIOM5_Msk (0x40UL) /*!< PWRIOM5 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM4_Pos (5UL) /*!< PWRIOM4 (Bit 5) */ +#define PWRCTRL_DEVPWREN_PWRIOM4_Msk (0x20UL) /*!< PWRIOM4 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM3_Pos (4UL) /*!< PWRIOM3 (Bit 4) */ +#define PWRCTRL_DEVPWREN_PWRIOM3_Msk (0x10UL) /*!< PWRIOM3 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM2_Pos (3UL) /*!< PWRIOM2 (Bit 3) */ +#define PWRCTRL_DEVPWREN_PWRIOM2_Msk (0x8UL) /*!< PWRIOM2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM1_Pos (2UL) /*!< PWRIOM1 (Bit 2) */ +#define PWRCTRL_DEVPWREN_PWRIOM1_Msk (0x4UL) /*!< PWRIOM1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM0_Pos (1UL) /*!< PWRIOM0 (Bit 1) */ +#define PWRCTRL_DEVPWREN_PWRIOM0_Msk (0x2UL) /*!< PWRIOM0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOS_Pos (0UL) /*!< PWRIOS (Bit 0) */ +#define PWRCTRL_DEVPWREN_PWRIOS_Msk (0x1UL) /*!< PWRIOS (Bitfield-Mask: 0x01) */ +/* ===================================================== MEMPWDINSLEEP ===================================================== */ +#define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Pos (31UL) /*!< CACHEPWDSLP (Bit 31) */ +#define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk (0x80000000UL) /*!< CACHEPWDSLP (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Pos (14UL) /*!< FLASH1PWDSLP (Bit 14) */ +#define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk (0x4000UL) /*!< FLASH1PWDSLP (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Pos (13UL) /*!< FLASH0PWDSLP (Bit 13) */ +#define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk (0x2000UL) /*!< FLASH0PWDSLP (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Pos (3UL) /*!< SRAMPWDSLP (Bit 3) */ +#define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Msk (0x1ff8UL) /*!< SRAMPWDSLP (Bitfield-Mask: 0x3ff) */ +#define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Pos (0UL) /*!< DTCMPWDSLP (Bit 0) */ +#define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Msk (0x7UL) /*!< DTCMPWDSLP (Bitfield-Mask: 0x07) */ +/* ======================================================= MEMPWREN ======================================================== */ +#define PWRCTRL_MEMPWREN_CACHEB2_Pos (31UL) /*!< CACHEB2 (Bit 31) */ +#define PWRCTRL_MEMPWREN_CACHEB2_Msk (0x80000000UL) /*!< CACHEB2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREN_CACHEB0_Pos (30UL) /*!< CACHEB0 (Bit 30) */ +#define PWRCTRL_MEMPWREN_CACHEB0_Msk (0x40000000UL) /*!< CACHEB0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREN_FLASH1_Pos (14UL) /*!< FLASH1 (Bit 14) */ +#define PWRCTRL_MEMPWREN_FLASH1_Msk (0x4000UL) /*!< FLASH1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREN_FLASH0_Pos (13UL) /*!< FLASH0 (Bit 13) */ +#define PWRCTRL_MEMPWREN_FLASH0_Msk (0x2000UL) /*!< FLASH0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREN_SRAM_Pos (3UL) /*!< SRAM (Bit 3) */ +#define PWRCTRL_MEMPWREN_SRAM_Msk (0x1ff8UL) /*!< SRAM (Bitfield-Mask: 0x3ff) */ +#define PWRCTRL_MEMPWREN_DTCM_Pos (0UL) /*!< DTCM (Bit 0) */ +#define PWRCTRL_MEMPWREN_DTCM_Msk (0x7UL) /*!< DTCM (Bitfield-Mask: 0x07) */ +/* ===================================================== MEMPWRSTATUS ====================================================== */ +#define PWRCTRL_MEMPWRSTATUS_CACHEB2_Pos (16UL) /*!< CACHEB2 (Bit 16) */ +#define PWRCTRL_MEMPWRSTATUS_CACHEB2_Msk (0x10000UL) /*!< CACHEB2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_CACHEB0_Pos (15UL) /*!< CACHEB0 (Bit 15) */ +#define PWRCTRL_MEMPWRSTATUS_CACHEB0_Msk (0x8000UL) /*!< CACHEB0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_FLASH1_Pos (14UL) /*!< FLASH1 (Bit 14) */ +#define PWRCTRL_MEMPWRSTATUS_FLASH1_Msk (0x4000UL) /*!< FLASH1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_FLASH0_Pos (13UL) /*!< FLASH0 (Bit 13) */ +#define PWRCTRL_MEMPWRSTATUS_FLASH0_Msk (0x2000UL) /*!< FLASH0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM9_Pos (12UL) /*!< SRAM9 (Bit 12) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM9_Msk (0x1000UL) /*!< SRAM9 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM8_Pos (11UL) /*!< SRAM8 (Bit 11) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM8_Msk (0x800UL) /*!< SRAM8 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM7_Pos (10UL) /*!< SRAM7 (Bit 10) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM7_Msk (0x400UL) /*!< SRAM7 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM6_Pos (9UL) /*!< SRAM6 (Bit 9) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM6_Msk (0x200UL) /*!< SRAM6 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM5_Pos (8UL) /*!< SRAM5 (Bit 8) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM5_Msk (0x100UL) /*!< SRAM5 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM4_Pos (7UL) /*!< SRAM4 (Bit 7) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM4_Msk (0x80UL) /*!< SRAM4 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM3_Pos (6UL) /*!< SRAM3 (Bit 6) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM3_Msk (0x40UL) /*!< SRAM3 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM2_Pos (5UL) /*!< SRAM2 (Bit 5) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM2_Msk (0x20UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM1_Pos (4UL) /*!< SRAM1 (Bit 4) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM1_Msk (0x10UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM0_Pos (3UL) /*!< SRAM0 (Bit 3) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM0_Msk (0x8UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM1_Pos (2UL) /*!< DTCM1 (Bit 2) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM1_Msk (0x4UL) /*!< DTCM1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM01_Pos (1UL) /*!< DTCM01 (Bit 1) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM01_Msk (0x2UL) /*!< DTCM01 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM00_Pos (0UL) /*!< DTCM00 (Bit 0) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM00_Msk (0x1UL) /*!< DTCM00 (Bitfield-Mask: 0x01) */ +/* ===================================================== DEVPWRSTATUS ====================================================== */ +#define PWRCTRL_DEVPWRSTATUS_BLEH_Pos (9UL) /*!< BLEH (Bit 9) */ +#define PWRCTRL_DEVPWRSTATUS_BLEH_Msk (0x200UL) /*!< BLEH (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_BLEL_Pos (8UL) /*!< BLEL (Bit 8) */ +#define PWRCTRL_DEVPWRSTATUS_BLEL_Msk (0x100UL) /*!< BLEL (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_PWRPDM_Pos (7UL) /*!< PWRPDM (Bit 7) */ +#define PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk (0x80UL) /*!< PWRPDM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Pos (6UL) /*!< PWRMSPI (Bit 6) */ +#define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk (0x40UL) /*!< PWRMSPI (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_PWRADC_Pos (5UL) /*!< PWRADC (Bit 5) */ +#define PWRCTRL_DEVPWRSTATUS_PWRADC_Msk (0x20UL) /*!< PWRADC (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_HCPC_Pos (4UL) /*!< HCPC (Bit 4) */ +#define PWRCTRL_DEVPWRSTATUS_HCPC_Msk (0x10UL) /*!< HCPC (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_HCPB_Pos (3UL) /*!< HCPB (Bit 3) */ +#define PWRCTRL_DEVPWRSTATUS_HCPB_Msk (0x8UL) /*!< HCPB (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_HCPA_Pos (2UL) /*!< HCPA (Bit 2) */ +#define PWRCTRL_DEVPWRSTATUS_HCPA_Msk (0x4UL) /*!< HCPA (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_MCUH_Pos (1UL) /*!< MCUH (Bit 1) */ +#define PWRCTRL_DEVPWRSTATUS_MCUH_Msk (0x2UL) /*!< MCUH (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_MCUL_Pos (0UL) /*!< MCUL (Bit 0) */ +#define PWRCTRL_DEVPWRSTATUS_MCUL_Msk (0x1UL) /*!< MCUL (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMCTRL ======================================================== */ +#define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Pos (8UL) /*!< SRAMLIGHTSLEEP (Bit 8) */ +#define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Msk (0xfff00UL) /*!< SRAMLIGHTSLEEP (Bitfield-Mask: 0xfff) */ +#define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Pos (2UL) /*!< SRAMMASTERCLKGATE (Bit 2) */ +#define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Msk (0x4UL) /*!< SRAMMASTERCLKGATE (Bitfield-Mask: 0x01) */ +#define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Pos (1UL) /*!< SRAMCLKGATE (Bit 1) */ +#define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Msk (0x2UL) /*!< SRAMCLKGATE (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCSTATUS ======================================================= */ +#define PWRCTRL_ADCSTATUS_REFBUFPWD_Pos (5UL) /*!< REFBUFPWD (Bit 5) */ +#define PWRCTRL_ADCSTATUS_REFBUFPWD_Msk (0x20UL) /*!< REFBUFPWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_REFKEEPPWD_Pos (4UL) /*!< REFKEEPPWD (Bit 4) */ +#define PWRCTRL_ADCSTATUS_REFKEEPPWD_Msk (0x10UL) /*!< REFKEEPPWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_VBATPWD_Pos (3UL) /*!< VBATPWD (Bit 3) */ +#define PWRCTRL_ADCSTATUS_VBATPWD_Msk (0x8UL) /*!< VBATPWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_VPTATPWD_Pos (2UL) /*!< VPTATPWD (Bit 2) */ +#define PWRCTRL_ADCSTATUS_VPTATPWD_Msk (0x4UL) /*!< VPTATPWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_BGTPWD_Pos (1UL) /*!< BGTPWD (Bit 1) */ +#define PWRCTRL_ADCSTATUS_BGTPWD_Msk (0x2UL) /*!< BGTPWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_ADCPWD_Pos (0UL) /*!< ADCPWD (Bit 0) */ +#define PWRCTRL_ADCSTATUS_ADCPWD_Msk (0x1UL) /*!< ADCPWD (Bitfield-Mask: 0x01) */ +/* ========================================================= MISC ========================================================== */ +#define PWRCTRL_MISC_MEMVRLPBLE_Pos (6UL) /*!< MEMVRLPBLE (Bit 6) */ +#define PWRCTRL_MISC_MEMVRLPBLE_Msk (0x40UL) /*!< MEMVRLPBLE (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Pos (3UL) /*!< FORCEMEMVRLPTIMERS (Bit 3) */ +#define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Msk (0x8UL) /*!< FORCEMEMVRLPTIMERS (Bitfield-Mask: 0x01) */ +/* ===================================================== DEVPWREVENTEN ===================================================== */ +#define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Pos (31UL) /*!< BURSTEVEN (Bit 31) */ +#define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Msk (0x80000000UL) /*!< BURSTEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Pos (30UL) /*!< BURSTFEATUREEVEN (Bit 30) */ +#define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Msk (0x40000000UL) /*!< BURSTFEATUREEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Pos (29UL) /*!< BLEFEATUREEVEN (Bit 29) */ +#define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Msk (0x20000000UL) /*!< BLEFEATUREEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Pos (8UL) /*!< BLELEVEN (Bit 8) */ +#define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Msk (0x100UL) /*!< BLELEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Pos (7UL) /*!< PDMEVEN (Bit 7) */ +#define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Msk (0x80UL) /*!< PDMEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Pos (6UL) /*!< MSPIEVEN (Bit 6) */ +#define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Msk (0x40UL) /*!< MSPIEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Pos (5UL) /*!< ADCEVEN (Bit 5) */ +#define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Msk (0x20UL) /*!< ADCEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Pos (4UL) /*!< HCPCEVEN (Bit 4) */ +#define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Msk (0x10UL) /*!< HCPCEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Pos (3UL) /*!< HCPBEVEN (Bit 3) */ +#define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Msk (0x8UL) /*!< HCPBEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Pos (2UL) /*!< HCPAEVEN (Bit 2) */ +#define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Msk (0x4UL) /*!< HCPAEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Pos (1UL) /*!< MCUHEVEN (Bit 1) */ +#define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Msk (0x2UL) /*!< MCUHEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Pos (0UL) /*!< MCULEVEN (Bit 0) */ +#define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Msk (0x1UL) /*!< MCULEVEN (Bitfield-Mask: 0x01) */ +/* ===================================================== MEMPWREVENTEN ===================================================== */ +#define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Pos (31UL) /*!< CACHEB2EN (Bit 31) */ +#define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Msk (0x80000000UL) /*!< CACHEB2EN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Pos (30UL) /*!< CACHEB0EN (Bit 30) */ +#define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Msk (0x40000000UL) /*!< CACHEB0EN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Pos (14UL) /*!< FLASH1EN (Bit 14) */ +#define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Msk (0x4000UL) /*!< FLASH1EN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Pos (13UL) /*!< FLASH0EN (Bit 13) */ +#define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Msk (0x2000UL) /*!< FLASH0EN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREVENTEN_SRAMEN_Pos (3UL) /*!< SRAMEN (Bit 3) */ +#define PWRCTRL_MEMPWREVENTEN_SRAMEN_Msk (0x1ff8UL) /*!< SRAMEN (Bitfield-Mask: 0x3ff) */ +#define PWRCTRL_MEMPWREVENTEN_DTCMEN_Pos (0UL) /*!< DTCMEN (Bit 0) */ +#define PWRCTRL_MEMPWREVENTEN_DTCMEN_Msk (0x7UL) /*!< DTCMEN (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ RSTGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define RSTGEN_CFG_WDREN_Pos (1UL) /*!< WDREN (Bit 1) */ +#define RSTGEN_CFG_WDREN_Msk (0x2UL) /*!< WDREN (Bitfield-Mask: 0x01) */ +#define RSTGEN_CFG_BODHREN_Pos (0UL) /*!< BODHREN (Bit 0) */ +#define RSTGEN_CFG_BODHREN_Msk (0x1UL) /*!< BODHREN (Bitfield-Mask: 0x01) */ +/* ========================================================= SWPOI ========================================================= */ +#define RSTGEN_SWPOI_SWPOIKEY_Pos (0UL) /*!< SWPOIKEY (Bit 0) */ +#define RSTGEN_SWPOI_SWPOIKEY_Msk (0xffUL) /*!< SWPOIKEY (Bitfield-Mask: 0xff) */ +/* ========================================================= SWPOR ========================================================= */ +#define RSTGEN_SWPOR_SWPORKEY_Pos (0UL) /*!< SWPORKEY (Bit 0) */ +#define RSTGEN_SWPOR_SWPORKEY_Msk (0xffUL) /*!< SWPORKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== TPIURST ======================================================== */ +#define RSTGEN_TPIURST_TPIURST_Pos (0UL) /*!< TPIURST (Bit 0) */ +#define RSTGEN_TPIURST_TPIURST_Msk (0x1UL) /*!< TPIURST (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ +#define RSTGEN_INTEN_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTEN_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define RSTGEN_INTSTAT_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTSTAT_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define RSTGEN_INTCLR_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTCLR_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define RSTGEN_INTSET_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTSET_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define RSTGEN_STAT_SBOOT_Pos (31UL) /*!< SBOOT (Bit 31) */ +#define RSTGEN_STAT_SBOOT_Msk (0x80000000UL) /*!< SBOOT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_FBOOT_Pos (30UL) /*!< FBOOT (Bit 30) */ +#define RSTGEN_STAT_FBOOT_Msk (0x40000000UL) /*!< FBOOT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BOBSTAT_Pos (10UL) /*!< BOBSTAT (Bit 10) */ +#define RSTGEN_STAT_BOBSTAT_Msk (0x400UL) /*!< BOBSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BOFSTAT_Pos (9UL) /*!< BOFSTAT (Bit 9) */ +#define RSTGEN_STAT_BOFSTAT_Msk (0x200UL) /*!< BOFSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BOCSTAT_Pos (8UL) /*!< BOCSTAT (Bit 8) */ +#define RSTGEN_STAT_BOCSTAT_Msk (0x100UL) /*!< BOCSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BOUSTAT_Pos (7UL) /*!< BOUSTAT (Bit 7) */ +#define RSTGEN_STAT_BOUSTAT_Msk (0x80UL) /*!< BOUSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_WDRSTAT_Pos (6UL) /*!< WDRSTAT (Bit 6) */ +#define RSTGEN_STAT_WDRSTAT_Msk (0x40UL) /*!< WDRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_DBGRSTAT_Pos (5UL) /*!< DBGRSTAT (Bit 5) */ +#define RSTGEN_STAT_DBGRSTAT_Msk (0x20UL) /*!< DBGRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_POIRSTAT_Pos (4UL) /*!< POIRSTAT (Bit 4) */ +#define RSTGEN_STAT_POIRSTAT_Msk (0x10UL) /*!< POIRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_SWRSTAT_Pos (3UL) /*!< SWRSTAT (Bit 3) */ +#define RSTGEN_STAT_SWRSTAT_Msk (0x8UL) /*!< SWRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BORSTAT_Pos (2UL) /*!< BORSTAT (Bit 2) */ +#define RSTGEN_STAT_BORSTAT_Msk (0x4UL) /*!< BORSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_PORSTAT_Pos (1UL) /*!< PORSTAT (Bit 1) */ +#define RSTGEN_STAT_PORSTAT_Msk (0x2UL) /*!< PORSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_EXRSTAT_Pos (0UL) /*!< EXRSTAT (Bit 0) */ +#define RSTGEN_STAT_EXRSTAT_Msk (0x1UL) /*!< EXRSTAT (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTRLOW ========================================================= */ +#define RTC_CTRLOW_CTRHR_Pos (24UL) /*!< CTRHR (Bit 24) */ +#define RTC_CTRLOW_CTRHR_Msk (0x3f000000UL) /*!< CTRHR (Bitfield-Mask: 0x3f) */ +#define RTC_CTRLOW_CTRMIN_Pos (16UL) /*!< CTRMIN (Bit 16) */ +#define RTC_CTRLOW_CTRMIN_Msk (0x7f0000UL) /*!< CTRMIN (Bitfield-Mask: 0x7f) */ +#define RTC_CTRLOW_CTRSEC_Pos (8UL) /*!< CTRSEC (Bit 8) */ +#define RTC_CTRLOW_CTRSEC_Msk (0x7f00UL) /*!< CTRSEC (Bitfield-Mask: 0x7f) */ +#define RTC_CTRLOW_CTR100_Pos (0UL) /*!< CTR100 (Bit 0) */ +#define RTC_CTRLOW_CTR100_Msk (0xffUL) /*!< CTR100 (Bitfield-Mask: 0xff) */ +/* ========================================================= CTRUP ========================================================= */ +#define RTC_CTRUP_CTERR_Pos (31UL) /*!< CTERR (Bit 31) */ +#define RTC_CTRUP_CTERR_Msk (0x80000000UL) /*!< CTERR (Bitfield-Mask: 0x01) */ +#define RTC_CTRUP_CEB_Pos (28UL) /*!< CEB (Bit 28) */ +#define RTC_CTRUP_CEB_Msk (0x10000000UL) /*!< CEB (Bitfield-Mask: 0x01) */ +#define RTC_CTRUP_CB_Pos (27UL) /*!< CB (Bit 27) */ +#define RTC_CTRUP_CB_Msk (0x8000000UL) /*!< CB (Bitfield-Mask: 0x01) */ +#define RTC_CTRUP_CTRWKDY_Pos (24UL) /*!< CTRWKDY (Bit 24) */ +#define RTC_CTRUP_CTRWKDY_Msk (0x7000000UL) /*!< CTRWKDY (Bitfield-Mask: 0x07) */ +#define RTC_CTRUP_CTRYR_Pos (16UL) /*!< CTRYR (Bit 16) */ +#define RTC_CTRUP_CTRYR_Msk (0xff0000UL) /*!< CTRYR (Bitfield-Mask: 0xff) */ +#define RTC_CTRUP_CTRMO_Pos (8UL) /*!< CTRMO (Bit 8) */ +#define RTC_CTRUP_CTRMO_Msk (0x1f00UL) /*!< CTRMO (Bitfield-Mask: 0x1f) */ +#define RTC_CTRUP_CTRDATE_Pos (0UL) /*!< CTRDATE (Bit 0) */ +#define RTC_CTRUP_CTRDATE_Msk (0x3fUL) /*!< CTRDATE (Bitfield-Mask: 0x3f) */ +/* ======================================================== ALMLOW ========================================================= */ +#define RTC_ALMLOW_ALMHR_Pos (24UL) /*!< ALMHR (Bit 24) */ +#define RTC_ALMLOW_ALMHR_Msk (0x3f000000UL) /*!< ALMHR (Bitfield-Mask: 0x3f) */ +#define RTC_ALMLOW_ALMMIN_Pos (16UL) /*!< ALMMIN (Bit 16) */ +#define RTC_ALMLOW_ALMMIN_Msk (0x7f0000UL) /*!< ALMMIN (Bitfield-Mask: 0x7f) */ +#define RTC_ALMLOW_ALMSEC_Pos (8UL) /*!< ALMSEC (Bit 8) */ +#define RTC_ALMLOW_ALMSEC_Msk (0x7f00UL) /*!< ALMSEC (Bitfield-Mask: 0x7f) */ +#define RTC_ALMLOW_ALM100_Pos (0UL) /*!< ALM100 (Bit 0) */ +#define RTC_ALMLOW_ALM100_Msk (0xffUL) /*!< ALM100 (Bitfield-Mask: 0xff) */ +/* ========================================================= ALMUP ========================================================= */ +#define RTC_ALMUP_ALMWKDY_Pos (16UL) /*!< ALMWKDY (Bit 16) */ +#define RTC_ALMUP_ALMWKDY_Msk (0x70000UL) /*!< ALMWKDY (Bitfield-Mask: 0x07) */ +#define RTC_ALMUP_ALMMO_Pos (8UL) /*!< ALMMO (Bit 8) */ +#define RTC_ALMUP_ALMMO_Msk (0x1f00UL) /*!< ALMMO (Bitfield-Mask: 0x1f) */ +#define RTC_ALMUP_ALMDATE_Pos (0UL) /*!< ALMDATE (Bit 0) */ +#define RTC_ALMUP_ALMDATE_Msk (0x3fUL) /*!< ALMDATE (Bitfield-Mask: 0x3f) */ +/* ======================================================== RTCCTL ========================================================= */ +#define RTC_RTCCTL_HR1224_Pos (5UL) /*!< HR1224 (Bit 5) */ +#define RTC_RTCCTL_HR1224_Msk (0x20UL) /*!< HR1224 (Bitfield-Mask: 0x01) */ +#define RTC_RTCCTL_RSTOP_Pos (4UL) /*!< RSTOP (Bit 4) */ +#define RTC_RTCCTL_RSTOP_Msk (0x10UL) /*!< RSTOP (Bitfield-Mask: 0x01) */ +#define RTC_RTCCTL_RPT_Pos (1UL) /*!< RPT (Bit 1) */ +#define RTC_RTCCTL_RPT_Msk (0xeUL) /*!< RPT (Bitfield-Mask: 0x07) */ +#define RTC_RTCCTL_WRTC_Pos (0UL) /*!< WRTC (Bit 0) */ +#define RTC_RTCCTL_WRTC_Msk (0x1UL) /*!< WRTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ +#define RTC_INTEN_ALM_Pos (0UL) /*!< ALM (Bit 0) */ +#define RTC_INTEN_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define RTC_INTSTAT_ALM_Pos (0UL) /*!< ALM (Bit 0) */ +#define RTC_INTSTAT_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define RTC_INTCLR_ALM_Pos (0UL) /*!< ALM (Bit 0) */ +#define RTC_INTCLR_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define RTC_INTSET_ALM_Pos (0UL) /*!< ALM (Bit 0) */ +#define RTC_INTSET_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SCARD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SR =========================================================== */ +#define SCARD_SR_FHF_Pos (6UL) /*!< FHF (Bit 6) */ +#define SCARD_SR_FHF_Msk (0x40UL) /*!< FHF (Bitfield-Mask: 0x01) */ +#define SCARD_SR_FT2REND_Pos (5UL) /*!< FT2REND (Bit 5) */ +#define SCARD_SR_FT2REND_Msk (0x20UL) /*!< FT2REND (Bitfield-Mask: 0x01) */ +#define SCARD_SR_PE_Pos (4UL) /*!< PE (Bit 4) */ +#define SCARD_SR_PE_Msk (0x10UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define SCARD_SR_OVR_Pos (3UL) /*!< OVR (Bit 3) */ +#define SCARD_SR_OVR_Msk (0x8UL) /*!< OVR (Bitfield-Mask: 0x01) */ +#define SCARD_SR_FER_Pos (2UL) /*!< FER (Bit 2) */ +#define SCARD_SR_FER_Msk (0x4UL) /*!< FER (Bitfield-Mask: 0x01) */ +#define SCARD_SR_TBERBF_Pos (1UL) /*!< TBERBF (Bit 1) */ +#define SCARD_SR_TBERBF_Msk (0x2UL) /*!< TBERBF (Bitfield-Mask: 0x01) */ +#define SCARD_SR_FNE_Pos (0UL) /*!< FNE (Bit 0) */ +#define SCARD_SR_FNE_Msk (0x1UL) /*!< FNE (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define SCARD_IER_FHFEN_Pos (6UL) /*!< FHFEN (Bit 6) */ +#define SCARD_IER_FHFEN_Msk (0x40UL) /*!< FHFEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_FT2RENDEN_Pos (5UL) /*!< FT2RENDEN (Bit 5) */ +#define SCARD_IER_FT2RENDEN_Msk (0x20UL) /*!< FT2RENDEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_PEEN_Pos (4UL) /*!< PEEN (Bit 4) */ +#define SCARD_IER_PEEN_Msk (0x10UL) /*!< PEEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_OVREN_Pos (3UL) /*!< OVREN (Bit 3) */ +#define SCARD_IER_OVREN_Msk (0x8UL) /*!< OVREN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_FEREN_Pos (2UL) /*!< FEREN (Bit 2) */ +#define SCARD_IER_FEREN_Msk (0x4UL) /*!< FEREN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_TBERBFEN_Pos (1UL) /*!< TBERBFEN (Bit 1) */ +#define SCARD_IER_TBERBFEN_Msk (0x2UL) /*!< TBERBFEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_FNEEN_Pos (0UL) /*!< FNEEN (Bit 0) */ +#define SCARD_IER_FNEEN_Msk (0x1UL) /*!< FNEEN (Bitfield-Mask: 0x01) */ +/* ========================================================== TCR ========================================================== */ +#define SCARD_TCR_DMAMD_Pos (7UL) /*!< DMAMD (Bit 7) */ +#define SCARD_TCR_DMAMD_Msk (0x80UL) /*!< DMAMD (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_FIP_Pos (6UL) /*!< FIP (Bit 6) */ +#define SCARD_TCR_FIP_Msk (0x40UL) /*!< FIP (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_AUTOCONV_Pos (5UL) /*!< AUTOCONV (Bit 5) */ +#define SCARD_TCR_AUTOCONV_Msk (0x20UL) /*!< AUTOCONV (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_PROT_Pos (4UL) /*!< PROT (Bit 4) */ +#define SCARD_TCR_PROT_Msk (0x10UL) /*!< PROT (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_TR_Pos (3UL) /*!< TR (Bit 3) */ +#define SCARD_TCR_TR_Msk (0x8UL) /*!< TR (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_LCT_Pos (2UL) /*!< LCT (Bit 2) */ +#define SCARD_TCR_LCT_Msk (0x4UL) /*!< LCT (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_SS_Pos (1UL) /*!< SS (Bit 1) */ +#define SCARD_TCR_SS_Msk (0x2UL) /*!< SS (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_CONV_Pos (0UL) /*!< CONV (Bit 0) */ +#define SCARD_TCR_CONV_Msk (0x1UL) /*!< CONV (Bitfield-Mask: 0x01) */ +/* ========================================================== UCR ========================================================== */ +#define SCARD_UCR_RETXEN_Pos (3UL) /*!< RETXEN (Bit 3) */ +#define SCARD_UCR_RETXEN_Msk (0x8UL) /*!< RETXEN (Bitfield-Mask: 0x01) */ +#define SCARD_UCR_RSTIN_Pos (2UL) /*!< RSTIN (Bit 2) */ +#define SCARD_UCR_RSTIN_Msk (0x4UL) /*!< RSTIN (Bitfield-Mask: 0x01) */ +#define SCARD_UCR_RIU_Pos (1UL) /*!< RIU (Bit 1) */ +#define SCARD_UCR_RIU_Msk (0x2UL) /*!< RIU (Bitfield-Mask: 0x01) */ +#define SCARD_UCR_CST_Pos (0UL) /*!< CST (Bit 0) */ +#define SCARD_UCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define SCARD_DR_DR_Pos (0UL) /*!< DR (Bit 0) */ +#define SCARD_DR_DR_Msk (0xffUL) /*!< DR (Bitfield-Mask: 0xff) */ +/* ========================================================= BPRL ========================================================== */ +#define SCARD_BPRL_BPRL_Pos (0UL) /*!< BPRL (Bit 0) */ +#define SCARD_BPRL_BPRL_Msk (0xffUL) /*!< BPRL (Bitfield-Mask: 0xff) */ +/* ========================================================= BPRH ========================================================== */ +#define SCARD_BPRH_BPRH_Pos (0UL) /*!< BPRH (Bit 0) */ +#define SCARD_BPRH_BPRH_Msk (0xfUL) /*!< BPRH (Bitfield-Mask: 0x0f) */ +/* ========================================================= UCR1 ========================================================== */ +#define SCARD_UCR1_ENLASTB_Pos (5UL) /*!< ENLASTB (Bit 5) */ +#define SCARD_UCR1_ENLASTB_Msk (0x20UL) /*!< ENLASTB (Bitfield-Mask: 0x01) */ +#define SCARD_UCR1_CLKIOV_Pos (4UL) /*!< CLKIOV (Bit 4) */ +#define SCARD_UCR1_CLKIOV_Msk (0x10UL) /*!< CLKIOV (Bitfield-Mask: 0x01) */ +#define SCARD_UCR1_T1PAREN_Pos (3UL) /*!< T1PAREN (Bit 3) */ +#define SCARD_UCR1_T1PAREN_Msk (0x8UL) /*!< T1PAREN (Bitfield-Mask: 0x01) */ +#define SCARD_UCR1_STSP_Pos (2UL) /*!< STSP (Bit 2) */ +#define SCARD_UCR1_STSP_Msk (0x4UL) /*!< STSP (Bitfield-Mask: 0x01) */ +#define SCARD_UCR1_PR_Pos (0UL) /*!< PR (Bit 0) */ +#define SCARD_UCR1_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ +/* ========================================================== SR1 ========================================================== */ +#define SCARD_SR1_IDLE_Pos (3UL) /*!< IDLE (Bit 3) */ +#define SCARD_SR1_IDLE_Msk (0x8UL) /*!< IDLE (Bitfield-Mask: 0x01) */ +#define SCARD_SR1_SYNCEND_Pos (2UL) /*!< SYNCEND (Bit 2) */ +#define SCARD_SR1_SYNCEND_Msk (0x4UL) /*!< SYNCEND (Bitfield-Mask: 0x01) */ +#define SCARD_SR1_PRL_Pos (1UL) /*!< PRL (Bit 1) */ +#define SCARD_SR1_PRL_Msk (0x2UL) /*!< PRL (Bitfield-Mask: 0x01) */ +#define SCARD_SR1_ECNTOVER_Pos (0UL) /*!< ECNTOVER (Bit 0) */ +#define SCARD_SR1_ECNTOVER_Msk (0x1UL) /*!< ECNTOVER (Bitfield-Mask: 0x01) */ +/* ========================================================= IER1 ========================================================== */ +#define SCARD_IER1_SYNCENDEN_Pos (2UL) /*!< SYNCENDEN (Bit 2) */ +#define SCARD_IER1_SYNCENDEN_Msk (0x4UL) /*!< SYNCENDEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER1_PRLEN_Pos (1UL) /*!< PRLEN (Bit 1) */ +#define SCARD_IER1_PRLEN_Msk (0x2UL) /*!< PRLEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER1_ECNTOVEREN_Pos (0UL) /*!< ECNTOVEREN (Bit 0) */ +#define SCARD_IER1_ECNTOVEREN_Msk (0x1UL) /*!< ECNTOVEREN (Bitfield-Mask: 0x01) */ +/* ========================================================= ECNTL ========================================================= */ +#define SCARD_ECNTL_ECNTL_Pos (0UL) /*!< ECNTL (Bit 0) */ +#define SCARD_ECNTL_ECNTL_Msk (0xffUL) /*!< ECNTL (Bitfield-Mask: 0xff) */ +/* ========================================================= ECNTH ========================================================= */ +#define SCARD_ECNTH_ECNTH_Pos (0UL) /*!< ECNTH (Bit 0) */ +#define SCARD_ECNTH_ECNTH_Msk (0xffUL) /*!< ECNTH (Bitfield-Mask: 0xff) */ +/* ========================================================== GTR ========================================================== */ +#define SCARD_GTR_GTR_Pos (0UL) /*!< GTR (Bit 0) */ +#define SCARD_GTR_GTR_Msk (0xffUL) /*!< GTR (Bitfield-Mask: 0xff) */ +/* ======================================================== RETXCNT ======================================================== */ +#define SCARD_RETXCNT_RETXCNT_Pos (0UL) /*!< RETXCNT (Bit 0) */ +#define SCARD_RETXCNT_RETXCNT_Msk (0xfUL) /*!< RETXCNT (Bitfield-Mask: 0x0f) */ +/* ====================================================== RETXCNTRMI ======================================================= */ +#define SCARD_RETXCNTRMI_RETXCNTRMI_Pos (0UL) /*!< RETXCNTRMI (Bit 0) */ +#define SCARD_RETXCNTRMI_RETXCNTRMI_Msk (0xfUL) /*!< RETXCNTRMI (Bitfield-Mask: 0x0f) */ +/* ======================================================== CLKCTRL ======================================================== */ +#define SCARD_CLKCTRL_APBCLKEN_Pos (1UL) /*!< APBCLKEN (Bit 1) */ +#define SCARD_CLKCTRL_APBCLKEN_Msk (0x2UL) /*!< APBCLKEN (Bitfield-Mask: 0x01) */ +#define SCARD_CLKCTRL_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */ +#define SCARD_CLKCTRL_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SECURITY ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define SECURITY_CTRL_CRCERROR_Pos (31UL) /*!< CRCERROR (Bit 31) */ +#define SECURITY_CTRL_CRCERROR_Msk (0x80000000UL) /*!< CRCERROR (Bitfield-Mask: 0x01) */ +#define SECURITY_CTRL_FUNCTION_Pos (4UL) /*!< FUNCTION (Bit 4) */ +#define SECURITY_CTRL_FUNCTION_Msk (0xf0UL) /*!< FUNCTION (Bitfield-Mask: 0x0f) */ +#define SECURITY_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define SECURITY_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== SRCADDR ======================================================== */ +#define SECURITY_SRCADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define SECURITY_SRCADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== LEN ========================================================== */ +#define SECURITY_LEN_LEN_Pos (2UL) /*!< LEN (Bit 2) */ +#define SECURITY_LEN_LEN_Msk (0xffffcUL) /*!< LEN (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== RESULT ========================================================= */ +#define SECURITY_RESULT_CRC_Pos (0UL) /*!< CRC (Bit 0) */ +#define SECURITY_RESULT_CRC_Msk (0xffffffffUL) /*!< CRC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LOCKCTRL ======================================================== */ +#define SECURITY_LOCKCTRL_SELECT_Pos (0UL) /*!< SELECT (Bit 0) */ +#define SECURITY_LOCKCTRL_SELECT_Msk (0xffUL) /*!< SELECT (Bitfield-Mask: 0xff) */ +/* ======================================================= LOCKSTAT ======================================================== */ +#define SECURITY_LOCKSTAT_STATUS_Pos (0UL) /*!< STATUS (Bit 0) */ +#define SECURITY_LOCKSTAT_STATUS_Msk (0xffffffffUL) /*!< STATUS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= KEY0 ========================================================== */ +#define SECURITY_KEY0_KEY0_Pos (0UL) /*!< KEY0 (Bit 0) */ +#define SECURITY_KEY0_KEY0_Msk (0xffffffffUL) /*!< KEY0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= KEY1 ========================================================== */ +#define SECURITY_KEY1_KEY1_Pos (0UL) /*!< KEY1 (Bit 0) */ +#define SECURITY_KEY1_KEY1_Msk (0xffffffffUL) /*!< KEY1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= KEY2 ========================================================== */ +#define SECURITY_KEY2_KEY2_Pos (0UL) /*!< KEY2 (Bit 0) */ +#define SECURITY_KEY2_KEY2_Msk (0xffffffffUL) /*!< KEY2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= KEY3 ========================================================== */ +#define SECURITY_KEY3_KEY3_Pos (0UL) /*!< KEY3 (Bit 0) */ +#define SECURITY_KEY3_KEY3_Msk (0xffffffffUL) /*!< KEY3 (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DR =========================================================== */ +#define UART0_DR_OEDATA_Pos (11UL) /*!< OEDATA (Bit 11) */ +#define UART0_DR_OEDATA_Msk (0x800UL) /*!< OEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_BEDATA_Pos (10UL) /*!< BEDATA (Bit 10) */ +#define UART0_DR_BEDATA_Msk (0x400UL) /*!< BEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_PEDATA_Pos (9UL) /*!< PEDATA (Bit 9) */ +#define UART0_DR_PEDATA_Msk (0x200UL) /*!< PEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_FEDATA_Pos (8UL) /*!< FEDATA (Bit 8) */ +#define UART0_DR_FEDATA_Msk (0x100UL) /*!< FEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define UART0_DR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== RSR ========================================================== */ +#define UART0_RSR_OESTAT_Pos (3UL) /*!< OESTAT (Bit 3) */ +#define UART0_RSR_OESTAT_Msk (0x8UL) /*!< OESTAT (Bitfield-Mask: 0x01) */ +#define UART0_RSR_BESTAT_Pos (2UL) /*!< BESTAT (Bit 2) */ +#define UART0_RSR_BESTAT_Msk (0x4UL) /*!< BESTAT (Bitfield-Mask: 0x01) */ +#define UART0_RSR_PESTAT_Pos (1UL) /*!< PESTAT (Bit 1) */ +#define UART0_RSR_PESTAT_Msk (0x2UL) /*!< PESTAT (Bitfield-Mask: 0x01) */ +#define UART0_RSR_FESTAT_Pos (0UL) /*!< FESTAT (Bit 0) */ +#define UART0_RSR_FESTAT_Msk (0x1UL) /*!< FESTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== FR =========================================================== */ +#define UART0_FR_TXBUSY_Pos (8UL) /*!< TXBUSY (Bit 8) */ +#define UART0_FR_TXBUSY_Msk (0x100UL) /*!< TXBUSY (Bitfield-Mask: 0x01) */ +#define UART0_FR_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ +#define UART0_FR_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ +#define UART0_FR_RXFF_Pos (6UL) /*!< RXFF (Bit 6) */ +#define UART0_FR_RXFF_Msk (0x40UL) /*!< RXFF (Bitfield-Mask: 0x01) */ +#define UART0_FR_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */ +#define UART0_FR_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */ +#define UART0_FR_RXFE_Pos (4UL) /*!< RXFE (Bit 4) */ +#define UART0_FR_RXFE_Msk (0x10UL) /*!< RXFE (Bitfield-Mask: 0x01) */ +#define UART0_FR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */ +#define UART0_FR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define UART0_FR_DCD_Pos (2UL) /*!< DCD (Bit 2) */ +#define UART0_FR_DCD_Msk (0x4UL) /*!< DCD (Bitfield-Mask: 0x01) */ +#define UART0_FR_DSR_Pos (1UL) /*!< DSR (Bit 1) */ +#define UART0_FR_DSR_Msk (0x2UL) /*!< DSR (Bitfield-Mask: 0x01) */ +#define UART0_FR_CTS_Pos (0UL) /*!< CTS (Bit 0) */ +#define UART0_FR_CTS_Msk (0x1UL) /*!< CTS (Bitfield-Mask: 0x01) */ +/* ========================================================= ILPR ========================================================== */ +#define UART0_ILPR_ILPDVSR_Pos (0UL) /*!< ILPDVSR (Bit 0) */ +#define UART0_ILPR_ILPDVSR_Msk (0xffUL) /*!< ILPDVSR (Bitfield-Mask: 0xff) */ +/* ========================================================= IBRD ========================================================== */ +#define UART0_IBRD_DIVINT_Pos (0UL) /*!< DIVINT (Bit 0) */ +#define UART0_IBRD_DIVINT_Msk (0xffffUL) /*!< DIVINT (Bitfield-Mask: 0xffff) */ +/* ========================================================= FBRD ========================================================== */ +#define UART0_FBRD_DIVFRAC_Pos (0UL) /*!< DIVFRAC (Bit 0) */ +#define UART0_FBRD_DIVFRAC_Msk (0x3fUL) /*!< DIVFRAC (Bitfield-Mask: 0x3f) */ +/* ========================================================= LCRH ========================================================== */ +#define UART0_LCRH_SPS_Pos (7UL) /*!< SPS (Bit 7) */ +#define UART0_LCRH_SPS_Msk (0x80UL) /*!< SPS (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_WLEN_Pos (5UL) /*!< WLEN (Bit 5) */ +#define UART0_LCRH_WLEN_Msk (0x60UL) /*!< WLEN (Bitfield-Mask: 0x03) */ +#define UART0_LCRH_FEN_Pos (4UL) /*!< FEN (Bit 4) */ +#define UART0_LCRH_FEN_Msk (0x10UL) /*!< FEN (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_STP2_Pos (3UL) /*!< STP2 (Bit 3) */ +#define UART0_LCRH_STP2_Msk (0x8UL) /*!< STP2 (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_EPS_Pos (2UL) /*!< EPS (Bit 2) */ +#define UART0_LCRH_EPS_Msk (0x4UL) /*!< EPS (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_PEN_Pos (1UL) /*!< PEN (Bit 1) */ +#define UART0_LCRH_PEN_Msk (0x2UL) /*!< PEN (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_BRK_Pos (0UL) /*!< BRK (Bit 0) */ +#define UART0_LCRH_BRK_Msk (0x1UL) /*!< BRK (Bitfield-Mask: 0x01) */ +/* ========================================================== CR =========================================================== */ +#define UART0_CR_CTSEN_Pos (15UL) /*!< CTSEN (Bit 15) */ +#define UART0_CR_CTSEN_Msk (0x8000UL) /*!< CTSEN (Bitfield-Mask: 0x01) */ +#define UART0_CR_RTSEN_Pos (14UL) /*!< RTSEN (Bit 14) */ +#define UART0_CR_RTSEN_Msk (0x4000UL) /*!< RTSEN (Bitfield-Mask: 0x01) */ +#define UART0_CR_OUT2_Pos (13UL) /*!< OUT2 (Bit 13) */ +#define UART0_CR_OUT2_Msk (0x2000UL) /*!< OUT2 (Bitfield-Mask: 0x01) */ +#define UART0_CR_OUT1_Pos (12UL) /*!< OUT1 (Bit 12) */ +#define UART0_CR_OUT1_Msk (0x1000UL) /*!< OUT1 (Bitfield-Mask: 0x01) */ +#define UART0_CR_RTS_Pos (11UL) /*!< RTS (Bit 11) */ +#define UART0_CR_RTS_Msk (0x800UL) /*!< RTS (Bitfield-Mask: 0x01) */ +#define UART0_CR_DTR_Pos (10UL) /*!< DTR (Bit 10) */ +#define UART0_CR_DTR_Msk (0x400UL) /*!< DTR (Bitfield-Mask: 0x01) */ +#define UART0_CR_RXE_Pos (9UL) /*!< RXE (Bit 9) */ +#define UART0_CR_RXE_Msk (0x200UL) /*!< RXE (Bitfield-Mask: 0x01) */ +#define UART0_CR_TXE_Pos (8UL) /*!< TXE (Bit 8) */ +#define UART0_CR_TXE_Msk (0x100UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define UART0_CR_LBE_Pos (7UL) /*!< LBE (Bit 7) */ +#define UART0_CR_LBE_Msk (0x80UL) /*!< LBE (Bitfield-Mask: 0x01) */ +#define UART0_CR_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ +#define UART0_CR_CLKSEL_Msk (0x70UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */ +#define UART0_CR_CLKEN_Pos (3UL) /*!< CLKEN (Bit 3) */ +#define UART0_CR_CLKEN_Msk (0x8UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ +#define UART0_CR_SIRLP_Pos (2UL) /*!< SIRLP (Bit 2) */ +#define UART0_CR_SIRLP_Msk (0x4UL) /*!< SIRLP (Bitfield-Mask: 0x01) */ +#define UART0_CR_SIREN_Pos (1UL) /*!< SIREN (Bit 1) */ +#define UART0_CR_SIREN_Msk (0x2UL) /*!< SIREN (Bitfield-Mask: 0x01) */ +#define UART0_CR_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */ +#define UART0_CR_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IFLS ========================================================== */ +#define UART0_IFLS_RXIFLSEL_Pos (3UL) /*!< RXIFLSEL (Bit 3) */ +#define UART0_IFLS_RXIFLSEL_Msk (0x38UL) /*!< RXIFLSEL (Bitfield-Mask: 0x07) */ +#define UART0_IFLS_TXIFLSEL_Pos (0UL) /*!< TXIFLSEL (Bit 0) */ +#define UART0_IFLS_TXIFLSEL_Msk (0x7UL) /*!< TXIFLSEL (Bitfield-Mask: 0x07) */ +/* ========================================================== IER ========================================================== */ +#define UART0_IER_OEIM_Pos (10UL) /*!< OEIM (Bit 10) */ +#define UART0_IER_OEIM_Msk (0x400UL) /*!< OEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_BEIM_Pos (9UL) /*!< BEIM (Bit 9) */ +#define UART0_IER_BEIM_Msk (0x200UL) /*!< BEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_PEIM_Pos (8UL) /*!< PEIM (Bit 8) */ +#define UART0_IER_PEIM_Msk (0x100UL) /*!< PEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_FEIM_Pos (7UL) /*!< FEIM (Bit 7) */ +#define UART0_IER_FEIM_Msk (0x80UL) /*!< FEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_RTIM_Pos (6UL) /*!< RTIM (Bit 6) */ +#define UART0_IER_RTIM_Msk (0x40UL) /*!< RTIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_TXIM_Pos (5UL) /*!< TXIM (Bit 5) */ +#define UART0_IER_TXIM_Msk (0x20UL) /*!< TXIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_RXIM_Pos (4UL) /*!< RXIM (Bit 4) */ +#define UART0_IER_RXIM_Msk (0x10UL) /*!< RXIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_DSRMIM_Pos (3UL) /*!< DSRMIM (Bit 3) */ +#define UART0_IER_DSRMIM_Msk (0x8UL) /*!< DSRMIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_DCDMIM_Pos (2UL) /*!< DCDMIM (Bit 2) */ +#define UART0_IER_DCDMIM_Msk (0x4UL) /*!< DCDMIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_CTSMIM_Pos (1UL) /*!< CTSMIM (Bit 1) */ +#define UART0_IER_CTSMIM_Msk (0x2UL) /*!< CTSMIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_TXCMPMIM_Pos (0UL) /*!< TXCMPMIM (Bit 0) */ +#define UART0_IER_TXCMPMIM_Msk (0x1UL) /*!< TXCMPMIM (Bitfield-Mask: 0x01) */ +/* ========================================================== IES ========================================================== */ +#define UART0_IES_OERIS_Pos (10UL) /*!< OERIS (Bit 10) */ +#define UART0_IES_OERIS_Msk (0x400UL) /*!< OERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_BERIS_Pos (9UL) /*!< BERIS (Bit 9) */ +#define UART0_IES_BERIS_Msk (0x200UL) /*!< BERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_PERIS_Pos (8UL) /*!< PERIS (Bit 8) */ +#define UART0_IES_PERIS_Msk (0x100UL) /*!< PERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_FERIS_Pos (7UL) /*!< FERIS (Bit 7) */ +#define UART0_IES_FERIS_Msk (0x80UL) /*!< FERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_RTRIS_Pos (6UL) /*!< RTRIS (Bit 6) */ +#define UART0_IES_RTRIS_Msk (0x40UL) /*!< RTRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_TXRIS_Pos (5UL) /*!< TXRIS (Bit 5) */ +#define UART0_IES_TXRIS_Msk (0x20UL) /*!< TXRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_RXRIS_Pos (4UL) /*!< RXRIS (Bit 4) */ +#define UART0_IES_RXRIS_Msk (0x10UL) /*!< RXRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_DSRMRIS_Pos (3UL) /*!< DSRMRIS (Bit 3) */ +#define UART0_IES_DSRMRIS_Msk (0x8UL) /*!< DSRMRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_DCDMRIS_Pos (2UL) /*!< DCDMRIS (Bit 2) */ +#define UART0_IES_DCDMRIS_Msk (0x4UL) /*!< DCDMRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_CTSMRIS_Pos (1UL) /*!< CTSMRIS (Bit 1) */ +#define UART0_IES_CTSMRIS_Msk (0x2UL) /*!< CTSMRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_TXCMPMRIS_Pos (0UL) /*!< TXCMPMRIS (Bit 0) */ +#define UART0_IES_TXCMPMRIS_Msk (0x1UL) /*!< TXCMPMRIS (Bitfield-Mask: 0x01) */ +/* ========================================================== MIS ========================================================== */ +#define UART0_MIS_OEMIS_Pos (10UL) /*!< OEMIS (Bit 10) */ +#define UART0_MIS_OEMIS_Msk (0x400UL) /*!< OEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_BEMIS_Pos (9UL) /*!< BEMIS (Bit 9) */ +#define UART0_MIS_BEMIS_Msk (0x200UL) /*!< BEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_PEMIS_Pos (8UL) /*!< PEMIS (Bit 8) */ +#define UART0_MIS_PEMIS_Msk (0x100UL) /*!< PEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_FEMIS_Pos (7UL) /*!< FEMIS (Bit 7) */ +#define UART0_MIS_FEMIS_Msk (0x80UL) /*!< FEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_RTMIS_Pos (6UL) /*!< RTMIS (Bit 6) */ +#define UART0_MIS_RTMIS_Msk (0x40UL) /*!< RTMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_TXMIS_Pos (5UL) /*!< TXMIS (Bit 5) */ +#define UART0_MIS_TXMIS_Msk (0x20UL) /*!< TXMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_RXMIS_Pos (4UL) /*!< RXMIS (Bit 4) */ +#define UART0_MIS_RXMIS_Msk (0x10UL) /*!< RXMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_DSRMMIS_Pos (3UL) /*!< DSRMMIS (Bit 3) */ +#define UART0_MIS_DSRMMIS_Msk (0x8UL) /*!< DSRMMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_DCDMMIS_Pos (2UL) /*!< DCDMMIS (Bit 2) */ +#define UART0_MIS_DCDMMIS_Msk (0x4UL) /*!< DCDMMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_CTSMMIS_Pos (1UL) /*!< CTSMMIS (Bit 1) */ +#define UART0_MIS_CTSMMIS_Msk (0x2UL) /*!< CTSMMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_TXCMPMMIS_Pos (0UL) /*!< TXCMPMMIS (Bit 0) */ +#define UART0_MIS_TXCMPMMIS_Msk (0x1UL) /*!< TXCMPMMIS (Bitfield-Mask: 0x01) */ +/* ========================================================== IEC ========================================================== */ +#define UART0_IEC_OEIC_Pos (10UL) /*!< OEIC (Bit 10) */ +#define UART0_IEC_OEIC_Msk (0x400UL) /*!< OEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_BEIC_Pos (9UL) /*!< BEIC (Bit 9) */ +#define UART0_IEC_BEIC_Msk (0x200UL) /*!< BEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_PEIC_Pos (8UL) /*!< PEIC (Bit 8) */ +#define UART0_IEC_PEIC_Msk (0x100UL) /*!< PEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_FEIC_Pos (7UL) /*!< FEIC (Bit 7) */ +#define UART0_IEC_FEIC_Msk (0x80UL) /*!< FEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_RTIC_Pos (6UL) /*!< RTIC (Bit 6) */ +#define UART0_IEC_RTIC_Msk (0x40UL) /*!< RTIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_TXIC_Pos (5UL) /*!< TXIC (Bit 5) */ +#define UART0_IEC_TXIC_Msk (0x20UL) /*!< TXIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_RXIC_Pos (4UL) /*!< RXIC (Bit 4) */ +#define UART0_IEC_RXIC_Msk (0x10UL) /*!< RXIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_DSRMIC_Pos (3UL) /*!< DSRMIC (Bit 3) */ +#define UART0_IEC_DSRMIC_Msk (0x8UL) /*!< DSRMIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_DCDMIC_Pos (2UL) /*!< DCDMIC (Bit 2) */ +#define UART0_IEC_DCDMIC_Msk (0x4UL) /*!< DCDMIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_CTSMIC_Pos (1UL) /*!< CTSMIC (Bit 1) */ +#define UART0_IEC_CTSMIC_Msk (0x2UL) /*!< CTSMIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_TXCMPMIC_Pos (0UL) /*!< TXCMPMIC (Bit 0) */ +#define UART0_IEC_TXCMPMIC_Msk (0x1UL) /*!< TXCMPMIC (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ VCOMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define VCOMP_CFG_LVLSEL_Pos (16UL) /*!< LVLSEL (Bit 16) */ +#define VCOMP_CFG_LVLSEL_Msk (0xf0000UL) /*!< LVLSEL (Bitfield-Mask: 0x0f) */ +#define VCOMP_CFG_NSEL_Pos (8UL) /*!< NSEL (Bit 8) */ +#define VCOMP_CFG_NSEL_Msk (0x300UL) /*!< NSEL (Bitfield-Mask: 0x03) */ +#define VCOMP_CFG_PSEL_Pos (0UL) /*!< PSEL (Bit 0) */ +#define VCOMP_CFG_PSEL_Msk (0x3UL) /*!< PSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= STAT ========================================================== */ +#define VCOMP_STAT_PWDSTAT_Pos (1UL) /*!< PWDSTAT (Bit 1) */ +#define VCOMP_STAT_PWDSTAT_Msk (0x2UL) /*!< PWDSTAT (Bitfield-Mask: 0x01) */ +#define VCOMP_STAT_CMPOUT_Pos (0UL) /*!< CMPOUT (Bit 0) */ +#define VCOMP_STAT_CMPOUT_Msk (0x1UL) /*!< CMPOUT (Bitfield-Mask: 0x01) */ +/* ======================================================== PWDKEY ========================================================= */ +#define VCOMP_PWDKEY_PWDKEY_Pos (0UL) /*!< PWDKEY (Bit 0) */ +#define VCOMP_PWDKEY_PWDKEY_Msk (0xffffffffUL) /*!< PWDKEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTEN ========================================================= */ +#define VCOMP_INTEN_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTEN_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTEN_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTEN_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define VCOMP_INTSTAT_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTSTAT_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTSTAT_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTSTAT_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define VCOMP_INTCLR_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTCLR_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTCLR_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTCLR_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define VCOMP_INTSET_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTSET_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTSET_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTSET_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define WDT_CFG_CLKSEL_Pos (24UL) /*!< CLKSEL (Bit 24) */ +#define WDT_CFG_CLKSEL_Msk (0x7000000UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */ +#define WDT_CFG_INTVAL_Pos (16UL) /*!< INTVAL (Bit 16) */ +#define WDT_CFG_INTVAL_Msk (0xff0000UL) /*!< INTVAL (Bitfield-Mask: 0xff) */ +#define WDT_CFG_RESVAL_Pos (8UL) /*!< RESVAL (Bit 8) */ +#define WDT_CFG_RESVAL_Msk (0xff00UL) /*!< RESVAL (Bitfield-Mask: 0xff) */ +#define WDT_CFG_RESEN_Pos (2UL) /*!< RESEN (Bit 2) */ +#define WDT_CFG_RESEN_Msk (0x4UL) /*!< RESEN (Bitfield-Mask: 0x01) */ +#define WDT_CFG_INTEN_Pos (1UL) /*!< INTEN (Bit 1) */ +#define WDT_CFG_INTEN_Msk (0x2UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +#define WDT_CFG_WDTEN_Pos (0UL) /*!< WDTEN (Bit 0) */ +#define WDT_CFG_WDTEN_Msk (0x1UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTRT ========================================================= */ +#define WDT_RSTRT_RSTRT_Pos (0UL) /*!< RSTRT (Bit 0) */ +#define WDT_RSTRT_RSTRT_Msk (0xffUL) /*!< RSTRT (Bitfield-Mask: 0xff) */ +/* ========================================================= LOCK ========================================================== */ +#define WDT_LOCK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ +#define WDT_LOCK_LOCK_Msk (0xffUL) /*!< LOCK (Bitfield-Mask: 0xff) */ +/* ========================================================= COUNT ========================================================= */ +#define WDT_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define WDT_COUNT_COUNT_Msk (0xffUL) /*!< COUNT (Bitfield-Mask: 0xff) */ +/* ========================================================= INTEN ========================================================= */ +#define WDT_INTEN_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTEN_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define WDT_INTSTAT_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTSTAT_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define WDT_INTCLR_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTCLR_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define WDT_INTSET_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTSET_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Enumerated Values Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup EnumValue_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* ================================================ ADC CFG CLKSEL [24..25] ================================================ */ +typedef enum { /*!< ADC_CFG_CLKSEL */ + ADC_CFG_CLKSEL_OFF = 0, /*!< OFF : Off mode. The HFRC or HFRC_DIV2 clock must be selected + for the ADC to function. The ADC controller + automatically shuts off the clock in it's + low power modes. When setting ADCEN to '0', + the CLKSEL should remain set to one of the + two clock selects for proper power down + sequencing. */ + ADC_CFG_CLKSEL_HFRC = 1, /*!< HFRC : HFRC Core Clock divided by (CORESEL+1) */ + ADC_CFG_CLKSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : HFRC Core Clock / 2 further divided by (CORESEL+1) */ +} ADC_CFG_CLKSEL_Enum; + +/* =============================================== ADC CFG TRIGPOL [19..19] ================================================ */ +typedef enum { /*!< ADC_CFG_TRIGPOL */ + ADC_CFG_TRIGPOL_RISING_EDGE = 0, /*!< RISING_EDGE : Trigger on rising edge. */ + ADC_CFG_TRIGPOL_FALLING_EDGE = 1, /*!< FALLING_EDGE : Trigger on falling edge. */ +} ADC_CFG_TRIGPOL_Enum; + +/* =============================================== ADC CFG TRIGSEL [16..18] ================================================ */ +typedef enum { /*!< ADC_CFG_TRIGSEL */ + ADC_CFG_TRIGSEL_EXT0 = 0, /*!< EXT0 : Off chip External Trigger0 (ADC_ET0) */ + ADC_CFG_TRIGSEL_EXT1 = 1, /*!< EXT1 : Off chip External Trigger1 (ADC_ET1) */ + ADC_CFG_TRIGSEL_EXT2 = 2, /*!< EXT2 : Off chip External Trigger2 (ADC_ET2) */ + ADC_CFG_TRIGSEL_EXT3 = 3, /*!< EXT3 : Off chip External Trigger3 (ADC_ET3) */ + ADC_CFG_TRIGSEL_VCOMP = 4, /*!< VCOMP : Voltage Comparator Output */ + ADC_CFG_TRIGSEL_SWT = 7, /*!< SWT : Software Trigger */ +} ADC_CFG_TRIGSEL_Enum; + +/* ============================================== ADC CFG DFIFORDEN [12..12] =============================================== */ +typedef enum { /*!< ADC_CFG_DFIFORDEN */ + ADC_CFG_DFIFORDEN_DIS = 0, /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register + will not POP an entry off the FIFO. */ + ADC_CFG_DFIFORDEN_EN = 1, /*!< EN : Reads to the FIFOPR registger will automatically pop an + entry off the FIFO. */ +} ADC_CFG_DFIFORDEN_Enum; + +/* ================================================= ADC CFG REFSEL [8..9] ================================================= */ +typedef enum { /*!< ADC_CFG_REFSEL */ + ADC_CFG_REFSEL_INT2P0 = 0, /*!< INT2P0 : Internal 2.0V Bandgap Reference Voltage */ + ADC_CFG_REFSEL_INT1P5 = 1, /*!< INT1P5 : Internal 1.5V Bandgap Reference Voltage */ + ADC_CFG_REFSEL_EXT2P0 = 2, /*!< EXT2P0 : Off Chip 2.0V Reference */ + ADC_CFG_REFSEL_EXT1P5 = 3, /*!< EXT1P5 : Off Chip 1.5V Reference */ +} ADC_CFG_REFSEL_Enum; + +/* ================================================= ADC CFG CKMODE [4..4] ================================================= */ +typedef enum { /*!< ADC_CFG_CKMODE */ + ADC_CFG_CKMODE_LPCKMODE = 0, /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set + LPCKMODE to 0x1 while configuring the ADC. */ + ADC_CFG_CKMODE_LLCKMODE = 1, /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk + will remain on while in functioning in LPMODE0. */ +} ADC_CFG_CKMODE_Enum; + +/* ================================================= ADC CFG LPMODE [3..3] ================================================= */ +typedef enum { /*!< ADC_CFG_LPMODE */ + ADC_CFG_LPMODE_MODE0 = 0, /*!< MODE0 : Low Power Mode 0. Leaves the ADC fully powered between + scans with minimum latency between a trigger event and + sample data collection. */ + ADC_CFG_LPMODE_MODE1 = 1, /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks + associated with the ADC until the next trigger event. Between + scans, the reference buffer requires up to 50us of delay + from a scan trigger event before the conversion will commence + while operating in this mode. */ +} ADC_CFG_LPMODE_Enum; + +/* ================================================= ADC CFG RPTEN [2..2] ================================================== */ +typedef enum { /*!< ADC_CFG_RPTEN */ + ADC_CFG_RPTEN_SINGLE_SCAN = 0, /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single + scan upon each trigger event. */ + ADC_CFG_RPTEN_REPEATING_SCAN = 1, /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete + it's first scan upon the initial trigger event and all + subsequent scans will occur at regular intervals defined + by the configuration programmed for the CTTMRA3 internal + timer until the timer is disabled or the ADC is disabled. + When disabling the ADC (setting ADCEN to '0'), the RPTEN + bit should be cleared. */ +} ADC_CFG_RPTEN_Enum; + +/* ================================================= ADC CFG ADCEN [0..0] ================================================== */ +typedef enum { /*!< ADC_CFG_ADCEN */ + ADC_CFG_ADCEN_DIS = 0, /*!< DIS : Disable the ADC module. */ + ADC_CFG_ADCEN_EN = 1, /*!< EN : Enable the ADC module. */ +} ADC_CFG_ADCEN_Enum; + +/* ========================================================= STAT ========================================================== */ +/* ================================================ ADC STAT PWDSTAT [0..0] ================================================ */ +typedef enum { /*!< ADC_STAT_PWDSTAT */ + ADC_STAT_PWDSTAT_ON = 0, /*!< ON : Powered on. */ + ADC_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : ADC Low Power Mode 1. */ +} ADC_STAT_PWDSTAT_Enum; + +/* ========================================================== SWT ========================================================== */ +/* ================================================== ADC SWT SWT [0..7] =================================================== */ +typedef enum { /*!< ADC_SWT_SWT */ + ADC_SWT_SWT_GEN_SW_TRIGGER = 55, /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger. */ +} ADC_SWT_SWT_Enum; + +/* ======================================================== SL0CFG ========================================================= */ +/* ============================================== ADC SL0CFG ADSEL0 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL0CFG_ADSEL0 */ + ADC_SL0CFG_ADSEL0_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL0CFG_ADSEL0_Enum; + +/* ============================================== ADC SL0CFG PRMODE0 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL0CFG_PRMODE0 */ + ADC_SL0CFG_PRMODE0_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL0CFG_PRMODE0_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL0CFG_PRMODE0_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL0CFG_PRMODE0_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL0CFG_PRMODE0_Enum; + +/* =============================================== ADC SL0CFG CHSEL0 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL0CFG_CHSEL0 */ + ADC_SL0CFG_CHSEL0_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL0CFG_CHSEL0_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL0CFG_CHSEL0_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL0CFG_CHSEL0_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL0CFG_CHSEL0_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL0CFG_CHSEL0_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL0CFG_CHSEL0_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL0CFG_CHSEL0_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL0CFG_CHSEL0_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL0CFG_CHSEL0_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL0CFG_CHSEL0_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL0CFG_CHSEL0_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL0CFG_CHSEL0_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL0CFG_CHSEL0_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL0CFG_CHSEL0_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL0CFG_CHSEL0_Enum; + +/* ================================================ ADC SL0CFG WCEN0 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL0CFG_WCEN0 */ + ADC_SL0CFG_WCEN0_WCEN = 1, /*!< WCEN : Enable the window compare for slot 0. */ +} ADC_SL0CFG_WCEN0_Enum; + +/* ================================================ ADC SL0CFG SLEN0 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL0CFG_SLEN0 */ + ADC_SL0CFG_SLEN0_SLEN = 1, /*!< SLEN : Enable slot 0 for ADC conversions. */ +} ADC_SL0CFG_SLEN0_Enum; + +/* ======================================================== SL1CFG ========================================================= */ +/* ============================================== ADC SL1CFG ADSEL1 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL1CFG_ADSEL1 */ + ADC_SL1CFG_ADSEL1_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL1CFG_ADSEL1_Enum; + +/* ============================================== ADC SL1CFG PRMODE1 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL1CFG_PRMODE1 */ + ADC_SL1CFG_PRMODE1_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL1CFG_PRMODE1_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL1CFG_PRMODE1_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL1CFG_PRMODE1_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL1CFG_PRMODE1_Enum; + +/* =============================================== ADC SL1CFG CHSEL1 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL1CFG_CHSEL1 */ + ADC_SL1CFG_CHSEL1_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL1CFG_CHSEL1_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL1CFG_CHSEL1_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL1CFG_CHSEL1_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL1CFG_CHSEL1_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL1CFG_CHSEL1_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL1CFG_CHSEL1_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL1CFG_CHSEL1_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL1CFG_CHSEL1_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL1CFG_CHSEL1_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL1CFG_CHSEL1_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL1CFG_CHSEL1_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL1CFG_CHSEL1_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL1CFG_CHSEL1_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL1CFG_CHSEL1_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL1CFG_CHSEL1_Enum; + +/* ================================================ ADC SL1CFG WCEN1 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL1CFG_WCEN1 */ + ADC_SL1CFG_WCEN1_WCEN = 1, /*!< WCEN : Enable the window compare for slot 1. */ +} ADC_SL1CFG_WCEN1_Enum; + +/* ================================================ ADC SL1CFG SLEN1 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL1CFG_SLEN1 */ + ADC_SL1CFG_SLEN1_SLEN = 1, /*!< SLEN : Enable slot 1 for ADC conversions. */ +} ADC_SL1CFG_SLEN1_Enum; + +/* ======================================================== SL2CFG ========================================================= */ +/* ============================================== ADC SL2CFG ADSEL2 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL2CFG_ADSEL2 */ + ADC_SL2CFG_ADSEL2_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL2CFG_ADSEL2_Enum; + +/* ============================================== ADC SL2CFG PRMODE2 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL2CFG_PRMODE2 */ + ADC_SL2CFG_PRMODE2_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL2CFG_PRMODE2_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL2CFG_PRMODE2_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL2CFG_PRMODE2_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL2CFG_PRMODE2_Enum; + +/* =============================================== ADC SL2CFG CHSEL2 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL2CFG_CHSEL2 */ + ADC_SL2CFG_CHSEL2_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL2CFG_CHSEL2_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL2CFG_CHSEL2_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL2CFG_CHSEL2_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL2CFG_CHSEL2_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL2CFG_CHSEL2_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL2CFG_CHSEL2_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL2CFG_CHSEL2_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL2CFG_CHSEL2_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL2CFG_CHSEL2_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL2CFG_CHSEL2_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL2CFG_CHSEL2_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL2CFG_CHSEL2_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL2CFG_CHSEL2_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL2CFG_CHSEL2_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL2CFG_CHSEL2_Enum; + +/* ================================================ ADC SL2CFG WCEN2 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL2CFG_WCEN2 */ + ADC_SL2CFG_WCEN2_WCEN = 1, /*!< WCEN : Enable the window compare for slot 2. */ +} ADC_SL2CFG_WCEN2_Enum; + +/* ================================================ ADC SL2CFG SLEN2 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL2CFG_SLEN2 */ + ADC_SL2CFG_SLEN2_SLEN = 1, /*!< SLEN : Enable slot 2 for ADC conversions. */ +} ADC_SL2CFG_SLEN2_Enum; + +/* ======================================================== SL3CFG ========================================================= */ +/* ============================================== ADC SL3CFG ADSEL3 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL3CFG_ADSEL3 */ + ADC_SL3CFG_ADSEL3_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL3CFG_ADSEL3_Enum; + +/* ============================================== ADC SL3CFG PRMODE3 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL3CFG_PRMODE3 */ + ADC_SL3CFG_PRMODE3_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL3CFG_PRMODE3_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL3CFG_PRMODE3_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL3CFG_PRMODE3_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL3CFG_PRMODE3_Enum; + +/* =============================================== ADC SL3CFG CHSEL3 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL3CFG_CHSEL3 */ + ADC_SL3CFG_CHSEL3_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL3CFG_CHSEL3_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL3CFG_CHSEL3_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL3CFG_CHSEL3_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL3CFG_CHSEL3_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL3CFG_CHSEL3_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL3CFG_CHSEL3_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL3CFG_CHSEL3_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL3CFG_CHSEL3_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL3CFG_CHSEL3_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL3CFG_CHSEL3_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL3CFG_CHSEL3_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL3CFG_CHSEL3_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL3CFG_CHSEL3_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL3CFG_CHSEL3_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL3CFG_CHSEL3_Enum; + +/* ================================================ ADC SL3CFG WCEN3 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL3CFG_WCEN3 */ + ADC_SL3CFG_WCEN3_WCEN = 1, /*!< WCEN : Enable the window compare for slot 3. */ +} ADC_SL3CFG_WCEN3_Enum; + +/* ================================================ ADC SL3CFG SLEN3 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL3CFG_SLEN3 */ + ADC_SL3CFG_SLEN3_SLEN = 1, /*!< SLEN : Enable slot 3 for ADC conversions. */ +} ADC_SL3CFG_SLEN3_Enum; + +/* ======================================================== SL4CFG ========================================================= */ +/* ============================================== ADC SL4CFG ADSEL4 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL4CFG_ADSEL4 */ + ADC_SL4CFG_ADSEL4_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL4CFG_ADSEL4_Enum; + +/* ============================================== ADC SL4CFG PRMODE4 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL4CFG_PRMODE4 */ + ADC_SL4CFG_PRMODE4_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL4CFG_PRMODE4_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL4CFG_PRMODE4_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL4CFG_PRMODE4_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL4CFG_PRMODE4_Enum; + +/* =============================================== ADC SL4CFG CHSEL4 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL4CFG_CHSEL4 */ + ADC_SL4CFG_CHSEL4_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL4CFG_CHSEL4_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL4CFG_CHSEL4_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL4CFG_CHSEL4_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL4CFG_CHSEL4_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL4CFG_CHSEL4_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL4CFG_CHSEL4_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL4CFG_CHSEL4_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL4CFG_CHSEL4_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL4CFG_CHSEL4_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL4CFG_CHSEL4_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL4CFG_CHSEL4_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL4CFG_CHSEL4_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL4CFG_CHSEL4_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL4CFG_CHSEL4_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL4CFG_CHSEL4_Enum; + +/* ================================================ ADC SL4CFG WCEN4 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL4CFG_WCEN4 */ + ADC_SL4CFG_WCEN4_WCEN = 1, /*!< WCEN : Enable the window compare for slot 4. */ +} ADC_SL4CFG_WCEN4_Enum; + +/* ================================================ ADC SL4CFG SLEN4 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL4CFG_SLEN4 */ + ADC_SL4CFG_SLEN4_SLEN = 1, /*!< SLEN : Enable slot 4 for ADC conversions. */ +} ADC_SL4CFG_SLEN4_Enum; + +/* ======================================================== SL5CFG ========================================================= */ +/* ============================================== ADC SL5CFG ADSEL5 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL5CFG_ADSEL5 */ + ADC_SL5CFG_ADSEL5_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL5CFG_ADSEL5_Enum; + +/* ============================================== ADC SL5CFG PRMODE5 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL5CFG_PRMODE5 */ + ADC_SL5CFG_PRMODE5_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL5CFG_PRMODE5_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL5CFG_PRMODE5_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL5CFG_PRMODE5_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL5CFG_PRMODE5_Enum; + +/* =============================================== ADC SL5CFG CHSEL5 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL5CFG_CHSEL5 */ + ADC_SL5CFG_CHSEL5_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL5CFG_CHSEL5_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL5CFG_CHSEL5_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL5CFG_CHSEL5_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL5CFG_CHSEL5_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL5CFG_CHSEL5_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL5CFG_CHSEL5_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL5CFG_CHSEL5_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL5CFG_CHSEL5_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL5CFG_CHSEL5_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL5CFG_CHSEL5_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL5CFG_CHSEL5_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL5CFG_CHSEL5_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL5CFG_CHSEL5_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL5CFG_CHSEL5_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL5CFG_CHSEL5_Enum; + +/* ================================================ ADC SL5CFG WCEN5 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL5CFG_WCEN5 */ + ADC_SL5CFG_WCEN5_WCEN = 1, /*!< WCEN : Enable the window compare for slot 5. */ +} ADC_SL5CFG_WCEN5_Enum; + +/* ================================================ ADC SL5CFG SLEN5 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL5CFG_SLEN5 */ + ADC_SL5CFG_SLEN5_SLEN = 1, /*!< SLEN : Enable slot 5 for ADC conversions. */ +} ADC_SL5CFG_SLEN5_Enum; + +/* ======================================================== SL6CFG ========================================================= */ +/* ============================================== ADC SL6CFG ADSEL6 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL6CFG_ADSEL6 */ + ADC_SL6CFG_ADSEL6_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL6CFG_ADSEL6_Enum; + +/* ============================================== ADC SL6CFG PRMODE6 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL6CFG_PRMODE6 */ + ADC_SL6CFG_PRMODE6_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL6CFG_PRMODE6_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL6CFG_PRMODE6_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL6CFG_PRMODE6_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL6CFG_PRMODE6_Enum; + +/* =============================================== ADC SL6CFG CHSEL6 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL6CFG_CHSEL6 */ + ADC_SL6CFG_CHSEL6_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL6CFG_CHSEL6_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL6CFG_CHSEL6_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL6CFG_CHSEL6_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL6CFG_CHSEL6_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL6CFG_CHSEL6_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL6CFG_CHSEL6_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL6CFG_CHSEL6_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL6CFG_CHSEL6_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL6CFG_CHSEL6_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL6CFG_CHSEL6_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL6CFG_CHSEL6_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL6CFG_CHSEL6_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL6CFG_CHSEL6_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL6CFG_CHSEL6_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL6CFG_CHSEL6_Enum; + +/* ================================================ ADC SL6CFG WCEN6 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL6CFG_WCEN6 */ + ADC_SL6CFG_WCEN6_WCEN = 1, /*!< WCEN : Enable the window compare for slot 6. */ +} ADC_SL6CFG_WCEN6_Enum; + +/* ================================================ ADC SL6CFG SLEN6 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL6CFG_SLEN6 */ + ADC_SL6CFG_SLEN6_SLEN = 1, /*!< SLEN : Enable slot 6 for ADC conversions. */ +} ADC_SL6CFG_SLEN6_Enum; + +/* ======================================================== SL7CFG ========================================================= */ +/* ============================================== ADC SL7CFG ADSEL7 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL7CFG_ADSEL7 */ + ADC_SL7CFG_ADSEL7_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL7CFG_ADSEL7_Enum; + +/* ============================================== ADC SL7CFG PRMODE7 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL7CFG_PRMODE7 */ + ADC_SL7CFG_PRMODE7_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL7CFG_PRMODE7_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL7CFG_PRMODE7_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL7CFG_PRMODE7_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL7CFG_PRMODE7_Enum; + +/* =============================================== ADC SL7CFG CHSEL7 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL7CFG_CHSEL7 */ + ADC_SL7CFG_CHSEL7_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL7CFG_CHSEL7_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL7CFG_CHSEL7_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL7CFG_CHSEL7_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL7CFG_CHSEL7_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL7CFG_CHSEL7_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL7CFG_CHSEL7_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL7CFG_CHSEL7_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL7CFG_CHSEL7_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL7CFG_CHSEL7_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL7CFG_CHSEL7_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL7CFG_CHSEL7_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL7CFG_CHSEL7_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL7CFG_CHSEL7_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL7CFG_CHSEL7_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL7CFG_CHSEL7_Enum; + +/* ================================================ ADC SL7CFG WCEN7 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL7CFG_WCEN7 */ + ADC_SL7CFG_WCEN7_WCEN = 1, /*!< WCEN : Enable the window compare for slot 7. */ +} ADC_SL7CFG_WCEN7_Enum; + +/* ================================================ ADC SL7CFG SLEN7 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL7CFG_SLEN7 */ + ADC_SL7CFG_SLEN7_SLEN = 1, /*!< SLEN : Enable slot 7 for ADC conversions. */ +} ADC_SL7CFG_SLEN7_Enum; + +/* ========================================================= WULIM ========================================================= */ +/* ========================================================= WLLIM ========================================================= */ +/* ======================================================== SCWLIM ========================================================= */ +/* ========================================================= FIFO ========================================================== */ +/* ======================================================== FIFOPR ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ================================================= ADC INTEN DERR [7..7] ================================================= */ +typedef enum { /*!< ADC_INTEN_DERR */ + ADC_INTEN_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ +} ADC_INTEN_DERR_Enum; + +/* ================================================= ADC INTEN DCMP [6..6] ================================================= */ +typedef enum { /*!< ADC_INTEN_DCMP */ + ADC_INTEN_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ +} ADC_INTEN_DCMP_Enum; + +/* ================================================ ADC INTEN WCINC [5..5] ================================================= */ +typedef enum { /*!< ADC_INTEN_WCINC */ + ADC_INTEN_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTEN_WCINC_Enum; + +/* ================================================ ADC INTEN WCEXC [4..4] ================================================= */ +typedef enum { /*!< ADC_INTEN_WCEXC */ + ADC_INTEN_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTEN_WCEXC_Enum; + +/* =============================================== ADC INTEN FIFOOVR2 [3..3] =============================================== */ +typedef enum { /*!< ADC_INTEN_FIFOOVR2 */ + ADC_INTEN_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTEN_FIFOOVR2_Enum; + +/* =============================================== ADC INTEN FIFOOVR1 [2..2] =============================================== */ +typedef enum { /*!< ADC_INTEN_FIFOOVR1 */ + ADC_INTEN_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTEN_FIFOOVR1_Enum; + +/* ================================================ ADC INTEN SCNCMP [1..1] ================================================ */ +typedef enum { /*!< ADC_INTEN_SCNCMP */ + ADC_INTEN_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTEN_SCNCMP_Enum; + +/* ================================================ ADC INTEN CNVCMP [0..0] ================================================ */ +typedef enum { /*!< ADC_INTEN_CNVCMP */ + ADC_INTEN_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTEN_CNVCMP_Enum; + +/* ======================================================== INTSTAT ======================================================== */ +/* ================================================ ADC INTSTAT DERR [7..7] ================================================ */ +typedef enum { /*!< ADC_INTSTAT_DERR */ + ADC_INTSTAT_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ +} ADC_INTSTAT_DERR_Enum; + +/* ================================================ ADC INTSTAT DCMP [6..6] ================================================ */ +typedef enum { /*!< ADC_INTSTAT_DCMP */ + ADC_INTSTAT_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ +} ADC_INTSTAT_DCMP_Enum; + +/* =============================================== ADC INTSTAT WCINC [5..5] ================================================ */ +typedef enum { /*!< ADC_INTSTAT_WCINC */ + ADC_INTSTAT_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTSTAT_WCINC_Enum; + +/* =============================================== ADC INTSTAT WCEXC [4..4] ================================================ */ +typedef enum { /*!< ADC_INTSTAT_WCEXC */ + ADC_INTSTAT_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTSTAT_WCEXC_Enum; + +/* ============================================== ADC INTSTAT FIFOOVR2 [3..3] ============================================== */ +typedef enum { /*!< ADC_INTSTAT_FIFOOVR2 */ + ADC_INTSTAT_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTSTAT_FIFOOVR2_Enum; + +/* ============================================== ADC INTSTAT FIFOOVR1 [2..2] ============================================== */ +typedef enum { /*!< ADC_INTSTAT_FIFOOVR1 */ + ADC_INTSTAT_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTSTAT_FIFOOVR1_Enum; + +/* =============================================== ADC INTSTAT SCNCMP [1..1] =============================================== */ +typedef enum { /*!< ADC_INTSTAT_SCNCMP */ + ADC_INTSTAT_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTSTAT_SCNCMP_Enum; + +/* =============================================== ADC INTSTAT CNVCMP [0..0] =============================================== */ +typedef enum { /*!< ADC_INTSTAT_CNVCMP */ + ADC_INTSTAT_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTSTAT_CNVCMP_Enum; + +/* ======================================================== INTCLR ========================================================= */ +/* ================================================ ADC INTCLR DERR [7..7] ================================================= */ +typedef enum { /*!< ADC_INTCLR_DERR */ + ADC_INTCLR_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ +} ADC_INTCLR_DERR_Enum; + +/* ================================================ ADC INTCLR DCMP [6..6] ================================================= */ +typedef enum { /*!< ADC_INTCLR_DCMP */ + ADC_INTCLR_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ +} ADC_INTCLR_DCMP_Enum; + +/* ================================================ ADC INTCLR WCINC [5..5] ================================================ */ +typedef enum { /*!< ADC_INTCLR_WCINC */ + ADC_INTCLR_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTCLR_WCINC_Enum; + +/* ================================================ ADC INTCLR WCEXC [4..4] ================================================ */ +typedef enum { /*!< ADC_INTCLR_WCEXC */ + ADC_INTCLR_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTCLR_WCEXC_Enum; + +/* ============================================== ADC INTCLR FIFOOVR2 [3..3] =============================================== */ +typedef enum { /*!< ADC_INTCLR_FIFOOVR2 */ + ADC_INTCLR_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTCLR_FIFOOVR2_Enum; + +/* ============================================== ADC INTCLR FIFOOVR1 [2..2] =============================================== */ +typedef enum { /*!< ADC_INTCLR_FIFOOVR1 */ + ADC_INTCLR_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTCLR_FIFOOVR1_Enum; + +/* =============================================== ADC INTCLR SCNCMP [1..1] ================================================ */ +typedef enum { /*!< ADC_INTCLR_SCNCMP */ + ADC_INTCLR_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTCLR_SCNCMP_Enum; + +/* =============================================== ADC INTCLR CNVCMP [0..0] ================================================ */ +typedef enum { /*!< ADC_INTCLR_CNVCMP */ + ADC_INTCLR_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTCLR_CNVCMP_Enum; + +/* ======================================================== INTSET ========================================================= */ +/* ================================================ ADC INTSET DERR [7..7] ================================================= */ +typedef enum { /*!< ADC_INTSET_DERR */ + ADC_INTSET_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ +} ADC_INTSET_DERR_Enum; + +/* ================================================ ADC INTSET DCMP [6..6] ================================================= */ +typedef enum { /*!< ADC_INTSET_DCMP */ + ADC_INTSET_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ +} ADC_INTSET_DCMP_Enum; + +/* ================================================ ADC INTSET WCINC [5..5] ================================================ */ +typedef enum { /*!< ADC_INTSET_WCINC */ + ADC_INTSET_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTSET_WCINC_Enum; + +/* ================================================ ADC INTSET WCEXC [4..4] ================================================ */ +typedef enum { /*!< ADC_INTSET_WCEXC */ + ADC_INTSET_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTSET_WCEXC_Enum; + +/* ============================================== ADC INTSET FIFOOVR2 [3..3] =============================================== */ +typedef enum { /*!< ADC_INTSET_FIFOOVR2 */ + ADC_INTSET_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTSET_FIFOOVR2_Enum; + +/* ============================================== ADC INTSET FIFOOVR1 [2..2] =============================================== */ +typedef enum { /*!< ADC_INTSET_FIFOOVR1 */ + ADC_INTSET_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTSET_FIFOOVR1_Enum; + +/* =============================================== ADC INTSET SCNCMP [1..1] ================================================ */ +typedef enum { /*!< ADC_INTSET_SCNCMP */ + ADC_INTSET_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTSET_SCNCMP_Enum; + +/* =============================================== ADC INTSET CNVCMP [0..0] ================================================ */ +typedef enum { /*!< ADC_INTSET_CNVCMP */ + ADC_INTSET_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTSET_CNVCMP_Enum; + +/* ======================================================= DMATRIGEN ======================================================= */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +/* ======================================================== DMACFG ========================================================= */ +/* ============================================== ADC DMACFG DMAMSK [17..17] =============================================== */ +typedef enum { /*!< ADC_DMACFG_DMAMSK */ + ADC_DMACFG_DMAMSK_DIS = 0, /*!< DIS : FIFO Contents are copied directly to memory without modification. */ + ADC_DMACFG_DMAMSK_EN = 1, /*!< EN : Only the FIFODATA contents are copied to memory on DMA + transfers. The SLOTNUM and FIFOCNT contents are cleared + to zero. */ +} ADC_DMACFG_DMAMSK_Enum; + +/* ============================================ ADC DMACFG DMAHONSTAT [16..16] ============================================= */ +typedef enum { /*!< ADC_DMACFG_DMAHONSTAT */ + ADC_DMACFG_DMAHONSTAT_DIS = 0, /*!< DIS : ADC conversions will continue regardless of DMA status + register */ + ADC_DMACFG_DMAHONSTAT_EN = 1, /*!< EN : ADC conversions will not progress if DMAERR or DMACPL bits + in DMA status register are set. */ +} ADC_DMACFG_DMAHONSTAT_Enum; + +/* ============================================== ADC DMACFG DMADYNPRI [9..9] ============================================== */ +typedef enum { /*!< ADC_DMACFG_DMADYNPRI */ + ADC_DMACFG_DMADYNPRI_DIS = 0, /*!< DIS : Disable dynamic priority (use DMAPRI setting only) */ + ADC_DMACFG_DMADYNPRI_EN = 1, /*!< EN : Enable dynamic priority */ +} ADC_DMACFG_DMADYNPRI_Enum; + +/* =============================================== ADC DMACFG DMAPRI [8..8] ================================================ */ +typedef enum { /*!< ADC_DMACFG_DMAPRI */ + ADC_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + ADC_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} ADC_DMACFG_DMAPRI_Enum; + +/* =============================================== ADC DMACFG DMADIR [2..2] ================================================ */ +typedef enum { /*!< ADC_DMACFG_DMADIR */ + ADC_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction */ + ADC_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction */ +} ADC_DMACFG_DMADIR_Enum; + +/* ================================================ ADC DMACFG DMAEN [0..0] ================================================ */ +typedef enum { /*!< ADC_DMACFG_DMAEN */ + ADC_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ + ADC_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ +} ADC_DMACFG_DMAEN_Enum; + +/* ====================================================== DMATOTCOUNT ====================================================== */ +/* ====================================================== DMATARGADDR ====================================================== */ +/* ======================================================== DMASTAT ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ APBDMA ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BBVALUE ======================================================== */ +/* ====================================================== BBSETCLEAR ======================================================= */ +/* ======================================================== BBINPUT ======================================================== */ +/* ======================================================= DEBUGDATA ======================================================= */ +/* ========================================================= DEBUG ========================================================= */ +/* ============================================== APBDMA DEBUG DEBUGEN [0..3] ============================================== */ +typedef enum { /*!< APBDMA_DEBUG_DEBUGEN */ + APBDMA_DEBUG_DEBUGEN_OFF = 0, /*!< OFF : Debug Disabled */ + APBDMA_DEBUG_DEBUGEN_ARB = 1, /*!< ARB : Debug Arb values */ +} APBDMA_DEBUG_DEBUGEN_Enum; + + + +/* =========================================================================================================================== */ +/* ================ BLEIF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FIFO ========================================================== */ +/* ======================================================== FIFOPTR ======================================================== */ +/* ======================================================== FIFOTHR ======================================================== */ +/* ======================================================== FIFOPOP ======================================================== */ +/* ======================================================= FIFOPUSH ======================================================== */ +/* ======================================================= FIFOCTRL ======================================================== */ +/* ======================================================== FIFOLOC ======================================================== */ +/* ======================================================== CLKCFG ========================================================= */ +/* =============================================== BLEIF CLKCFG FSEL [8..10] =============================================== */ +typedef enum { /*!< BLEIF_CLKCFG_FSEL */ + BLEIF_CLKCFG_FSEL_MIN_PWR = 0, /*!< MIN_PWR : Selects the minimum power clock. This setting should + be used whenever the IOM is not active. */ + BLEIF_CLKCFG_FSEL_HFRC = 1, /*!< HFRC : Selects the HFRC as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV8 = 4, /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV16 = 5, /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV32 = 6, /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV64 = 7, /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock. */ +} BLEIF_CLKCFG_FSEL_Enum; + +/* ========================================================== CMD ========================================================== */ +/* ================================================= BLEIF CMD CMD [0..4] ================================================== */ +typedef enum { /*!< BLEIF_CMD_CMD */ + BLEIF_CMD_CMD_WRITE = 1, /*!< WRITE : Write command using count of offset bytes specified + in the OFFSETCNT field */ + BLEIF_CMD_CMD_READ = 2, /*!< READ : Read command using count of offset bytes specified in + the OFFSETCNT field */ +} BLEIF_CMD_CMD_Enum; + +/* ======================================================== CMDRPT ========================================================= */ +/* ======================================================= OFFSETHI ======================================================== */ +/* ======================================================== CMDSTAT ======================================================== */ +/* ============================================= BLEIF CMDSTAT CMDSTAT [5..7] ============================================== */ +typedef enum { /*!< BLEIF_CMDSTAT_CMDSTAT */ + BLEIF_CMDSTAT_CMDSTAT_ERR = 1, /*!< ERR : Error encountered with command */ + BLEIF_CMDSTAT_CMDSTAT_ACTIVE = 2, /*!< ACTIVE : Actively processing command */ + BLEIF_CMDSTAT_CMDSTAT_IDLE = 4, /*!< IDLE : Idle state, no active command, no error */ + BLEIF_CMDSTAT_CMDSTAT_WAIT = 6, /*!< WAIT : Command in progress, but waiting on data from host */ +} BLEIF_CMDSTAT_CMDSTAT_Enum; + +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================= DMATRIGEN ======================================================= */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +/* ======================================================== DMACFG ========================================================= */ +/* ============================================== BLEIF DMACFG DPWROFF [9..9] ============================================== */ +typedef enum { /*!< BLEIF_DMACFG_DPWROFF */ + BLEIF_DMACFG_DPWROFF_DIS = 0, /*!< DIS : Power off disabled */ + BLEIF_DMACFG_DPWROFF_EN = 1, /*!< EN : Power off enabled */ +} BLEIF_DMACFG_DPWROFF_Enum; + +/* ============================================== BLEIF DMACFG DMAPRI [8..8] =============================================== */ +typedef enum { /*!< BLEIF_DMACFG_DMAPRI */ + BLEIF_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + BLEIF_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} BLEIF_DMACFG_DMAPRI_Enum; + +/* ============================================== BLEIF DMACFG DMADIR [1..1] =============================================== */ +typedef enum { /*!< BLEIF_DMACFG_DMADIR */ + BLEIF_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when + doing IOM read operations, ie reading data from external + devices. */ + BLEIF_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. To be set when doing + IOM write operations, ie writing data to external devices. */ +} BLEIF_DMACFG_DMADIR_Enum; + +/* =============================================== BLEIF DMACFG DMAEN [0..0] =============================================== */ +typedef enum { /*!< BLEIF_DMACFG_DMAEN */ + BLEIF_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ + BLEIF_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ +} BLEIF_DMACFG_DMAEN_Enum; + +/* ====================================================== DMATOTCOUNT ====================================================== */ +/* ====================================================== DMATARGADDR ====================================================== */ +/* ======================================================== DMASTAT ======================================================== */ +/* ========================================================= CQCFG ========================================================= */ +/* =============================================== BLEIF CQCFG CQPRI [1..1] ================================================ */ +typedef enum { /*!< BLEIF_CQCFG_CQPRI */ + BLEIF_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + BLEIF_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} BLEIF_CQCFG_CQPRI_Enum; + +/* ================================================ BLEIF CQCFG CQEN [0..0] ================================================ */ +typedef enum { /*!< BLEIF_CQCFG_CQEN */ + BLEIF_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */ + BLEIF_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */ +} BLEIF_CQCFG_CQEN_Enum; + +/* ======================================================== CQADDR ========================================================= */ +/* ======================================================== CQSTAT ========================================================= */ +/* ======================================================== CQFLAGS ======================================================== */ +/* ====================================================== CQSETCLEAR ======================================================= */ +/* ======================================================= CQPAUSEEN ======================================================= */ +/* ============================================= BLEIF CQPAUSEEN CQPEN [0..15] ============================================= */ +typedef enum { /*!< BLEIF_CQPAUSEEN_CQPEN */ + BLEIF_CQPAUSEEN_CQPEN_CNTEQ = 32768, /*!< CNTEQ : Pauses command queue processing when HWCNT matches SWCNT */ + BLEIF_CQPAUSEEN_CQPEN_BLEXOREN = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with + SWFLAG4 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_IOMXOREN = 8192, /*!< IOMXOREN : Pause command queue when input IOM bit XORed with + SWFLAG3 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_GPIOXOREN = 4096, /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed + with SWFLAG2 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_MSPI1XNOREN = 2048, /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed + with SWFLAG1 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_MSPI0XNOREN = 1024, /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed + with SWFLAG0 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_MSPI1XOREN = 512, /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed + with SWFLAG1 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_MSPI0XOREN = 256, /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed + with SWFLAG0 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN7 = 128, /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7 + is '1'. */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN6 = 64, /*!< SWFLAGEN6 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN5 = 32, /*!< SWFLAGEN5 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN4 = 16, /*!< SWFLAGEN4 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN3 = 8, /*!< SWFLAGEN3 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN2 = 4, /*!< SWFLAGEN2 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN1 = 2, /*!< SWFLAGEN1 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLGEN0 = 1, /*!< SWFLGEN0 : Pause the command queue when software flag bit 7 + is '1' */ +} BLEIF_CQPAUSEEN_CQPEN_Enum; + +/* ======================================================= CQCURIDX ======================================================== */ +/* ======================================================= CQENDIDX ======================================================== */ +/* ======================================================== STATUS ========================================================= */ +/* ============================================== BLEIF STATUS IDLEST [2..2] =============================================== */ +typedef enum { /*!< BLEIF_STATUS_IDLEST */ + BLEIF_STATUS_IDLEST_IDLE = 1, /*!< IDLE : The I/O state machine is in the idle state. */ +} BLEIF_STATUS_IDLEST_Enum; + +/* ============================================== BLEIF STATUS CMDACT [1..1] =============================================== */ +typedef enum { /*!< BLEIF_STATUS_CMDACT */ + BLEIF_STATUS_CMDACT_ACTIVE = 1, /*!< ACTIVE : An I/O command is active. Indicates the active module + has an active command and is processing this. De-asserted + when the command is completed. */ +} BLEIF_STATUS_CMDACT_Enum; + +/* ================================================ BLEIF STATUS ERR [0..0] ================================================ */ +typedef enum { /*!< BLEIF_STATUS_ERR */ + BLEIF_STATUS_ERR_ERROR = 1, /*!< ERROR : Bit has been deprecated and will always return 0. */ +} BLEIF_STATUS_ERR_Enum; + +/* ======================================================== MSPICFG ======================================================== */ +/* ============================================= BLEIF MSPICFG SPILSB [23..23] ============================================= */ +typedef enum { /*!< BLEIF_MSPICFG_SPILSB */ + BLEIF_MSPICFG_SPILSB_MSB = 0, /*!< MSB : Send and receive MSB bit first */ + BLEIF_MSPICFG_SPILSB_LSB = 1, /*!< LSB : Send and receive LSB bit first */ +} BLEIF_MSPICFG_SPILSB_Enum; + +/* ============================================ BLEIF MSPICFG RDFCPOL [22..22] ============================================= */ +typedef enum { /*!< BLEIF_MSPICFG_RDFCPOL */ + BLEIF_MSPICFG_RDFCPOL_NORMAL = 0, /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow + control and new read spi transactions will not be started + until the signal goes low.(default) */ + BLEIF_MSPICFG_RDFCPOL_INVERTED = 1, /*!< INVERTED : SPI_STATUS signal from BLE Core low(0) creates flow + control and new read spi transactions will not be started + until the signal goes high. */ +} BLEIF_MSPICFG_RDFCPOL_Enum; + +/* ============================================ BLEIF MSPICFG WTFCPOL [21..21] ============================================= */ +typedef enum { /*!< BLEIF_MSPICFG_WTFCPOL */ + BLEIF_MSPICFG_WTFCPOL_NORMAL = 0, /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow + control and new write spi transactions will not be started + until the signal goes low.(default) */ + BLEIF_MSPICFG_WTFCPOL_INVERTED = 1, /*!< INVERTED : SPI_STATUS signal from BLE Core high(1) creates low(0) + control and new write spi transactions will not be started + until the signal goes high. */ +} BLEIF_MSPICFG_WTFCPOL_Enum; + +/* ============================================== BLEIF MSPICFG RDFC [17..17] ============================================== */ +typedef enum { /*!< BLEIF_MSPICFG_RDFC */ + BLEIF_MSPICFG_RDFC_DIS = 0, /*!< DIS : Read mode flow control disabled. */ + BLEIF_MSPICFG_RDFC_EN = 1, /*!< EN : Read mode flow control enabled. */ +} BLEIF_MSPICFG_RDFC_Enum; + +/* ============================================== BLEIF MSPICFG WTFC [16..16] ============================================== */ +typedef enum { /*!< BLEIF_MSPICFG_WTFC */ + BLEIF_MSPICFG_WTFC_DIS = 0, /*!< DIS : Write mode flow control disabled. */ + BLEIF_MSPICFG_WTFC_EN = 1, /*!< EN : Write mode flow control enabled. */ +} BLEIF_MSPICFG_WTFC_Enum; + +/* =============================================== BLEIF MSPICFG SPHA [1..1] =============================================== */ +typedef enum { /*!< BLEIF_MSPICFG_SPHA */ + BLEIF_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0, /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge, + rising or falling dependant on the value of SPOL */ + BLEIF_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1, /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock + edge, rising of falling dependant on the value of SPOL */ +} BLEIF_MSPICFG_SPHA_Enum; + +/* =============================================== BLEIF MSPICFG SPOL [0..0] =============================================== */ +typedef enum { /*!< BLEIF_MSPICFG_SPOL */ + BLEIF_MSPICFG_SPOL_CLK_BASE_0 = 0, /*!< CLK_BASE_0 : The initial value of the clock is 0. */ + BLEIF_MSPICFG_SPOL_CLK_BASE_1 = 1, /*!< CLK_BASE_1 : The initial value of the clock is 1. */ +} BLEIF_MSPICFG_SPOL_Enum; + +/* ======================================================== BLECFG ========================================================= */ +/* ============================================ BLEIF BLECFG SPIISOCTL [14..15] ============================================ */ +typedef enum { /*!< BLEIF_BLECFG_SPIISOCTL */ + BLEIF_BLECFG_SPIISOCTL_ON = 3, /*!< ON : SPI signals from BLE Core to/from MCU Core are isolated. */ + BLEIF_BLECFG_SPIISOCTL_OFF = 2, /*!< OFF : SPI signals from BLE Core to/from MCU Core are not isolated. */ + BLEIF_BLECFG_SPIISOCTL_AUTO = 0, /*!< AUTO : SPI signals from BLE Core to/from MCU Core are automatically + isolated by the logic */ +} BLEIF_BLECFG_SPIISOCTL_Enum; + +/* ============================================ BLEIF BLECFG PWRISOCTL [12..13] ============================================ */ +typedef enum { /*!< BLEIF_BLECFG_PWRISOCTL */ + BLEIF_BLECFG_PWRISOCTL_ON = 3, /*!< ON : BLEH power signal isolation to on (isolated). */ + BLEIF_BLECFG_PWRISOCTL_OFF = 2, /*!< OFF : BLEH power signal isolation to off (not isolated). */ + BLEIF_BLECFG_PWRISOCTL_AUTO = 0, /*!< AUTO : BLEH Power signal isolation is controlled automatically + through the interface logic */ +} BLEIF_BLECFG_PWRISOCTL_Enum; + +/* ============================================ BLEIF BLECFG BLEHREQCTL [6..7] ============================================= */ +typedef enum { /*!< BLEIF_BLECFG_BLEHREQCTL */ + BLEIF_BLECFG_BLEHREQCTL_ON = 3, /*!< ON : BLEH Power-on reg signal is set to on (1). */ + BLEIF_BLECFG_BLEHREQCTL_OFF = 2, /*!< OFF : BLEH Power-on signal is set to off (0). */ + BLEIF_BLECFG_BLEHREQCTL_AUTO = 0, /*!< AUTO : BLEH Power-on signal is controlled by the PWRSM logic + and automatically controlled */ +} BLEIF_BLECFG_BLEHREQCTL_Enum; + +/* ============================================ BLEIF BLECFG DCDCFLGCTL [4..5] ============================================= */ +typedef enum { /*!< BLEIF_BLECFG_DCDCFLGCTL */ + BLEIF_BLECFG_DCDCFLGCTL_ON = 3, /*!< ON : DCDC Flag signal is set to on (1). */ + BLEIF_BLECFG_DCDCFLGCTL_OFF = 2, /*!< OFF : DCDC Flag signal is set to off (0). */ + BLEIF_BLECFG_DCDCFLGCTL_AUTO = 0, /*!< AUTO : DCDC Flag signal is controlled by the PWRSM logic and + automatically controlled */ +} BLEIF_BLECFG_DCDCFLGCTL_Enum; + +/* ============================================= BLEIF BLECFG WAKEUPCTL [2..3] ============================================= */ +typedef enum { /*!< BLEIF_BLECFG_WAKEUPCTL */ + BLEIF_BLECFG_WAKEUPCTL_ON = 3, /*!< ON : Wake signal is set to on (1). */ + BLEIF_BLECFG_WAKEUPCTL_OFF = 2, /*!< OFF : Wake signal is set to off (0). */ + BLEIF_BLECFG_WAKEUPCTL_AUTO = 0, /*!< AUTO : Wake signal is controlled by the PWRSM logic and automatically + controlled */ +} BLEIF_BLECFG_WAKEUPCTL_Enum; + +/* ============================================== BLEIF BLECFG BLERSTN [1..1] ============================================== */ +typedef enum { /*!< BLEIF_BLECFG_BLERSTN */ + BLEIF_BLECFG_BLERSTN_ACTIVE = 1, /*!< ACTIVE : The reset signal is active (0) */ + BLEIF_BLECFG_BLERSTN_INACTIVE = 0, /*!< INACTIVE : The reset signal is inactive (1) */ +} BLEIF_BLECFG_BLERSTN_Enum; + +/* ============================================== BLEIF BLECFG PWRSMEN [0..0] ============================================== */ +typedef enum { /*!< BLEIF_BLECFG_PWRSMEN */ + BLEIF_BLECFG_PWRSMEN_ON = 1, /*!< ON : Internal power state machine is enabled and will sequence + the BLEH power domain as indicated in the design document. + Overrides for the power signals are not enabled. */ + BLEIF_BLECFG_PWRSMEN_OFF = 0, /*!< OFF : Internal power state machine is disabled and will not + sequence the BLEH power domain. The values of the overrides + will be used to drive the output sequencing signals */ +} BLEIF_BLECFG_PWRSMEN_Enum; + +/* ======================================================== PWRCMD ========================================================= */ +/* ======================================================== BSTATUS ======================================================== */ +/* ============================================== BLEIF BSTATUS PWRST [8..10] ============================================== */ +typedef enum { /*!< BLEIF_BSTATUS_PWRST */ + BLEIF_BSTATUS_PWRST_OFF = 0, /*!< OFF : Internal power state machine is disabled and will not + sequence the BLEH power domain. The values of the overrides + will be used to drive the output sequencing signals */ + BLEIF_BSTATUS_PWRST_INIT = 1, /*!< INIT : Initialization state. BLEH not powered */ + BLEIF_BSTATUS_PWRST_PWRON = 2, /*!< PWRON : Waiting for the powerup of the BLEH */ + BLEIF_BSTATUS_PWRST_ACTIVE = 3, /*!< ACTIVE : The BLE Core is powered and active */ + BLEIF_BSTATUS_PWRST_SLEEP = 6, /*!< SLEEP : The BLE Core has entered sleep mode and the power request + is inactive */ + BLEIF_BSTATUS_PWRST_SHUTDOWN = 4, /*!< SHUTDOWN : The BLE Core is in shutdown mode */ +} BLEIF_BSTATUS_PWRST_Enum; + +/* ============================================= BLEIF BSTATUS B2MSTATE [0..2] ============================================= */ +typedef enum { /*!< BLEIF_BSTATUS_B2MSTATE */ + BLEIF_BSTATUS_B2MSTATE_RESET = 0, /*!< RESET : Reset State */ + BLEIF_BSTATUS_B2MSTATE_Sleep = 1, /*!< Sleep : Sleep state. */ + BLEIF_BSTATUS_B2MSTATE_Standby = 2, /*!< Standby : Standby State */ + BLEIF_BSTATUS_B2MSTATE_Idle = 3, /*!< Idle : Idle state */ + BLEIF_BSTATUS_B2MSTATE_Active = 4, /*!< Active : Active state. */ +} BLEIF_BSTATUS_B2MSTATE_Enum; + +/* ======================================================== BLEDBG ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ CACHECTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CACHECFG ======================================================== */ +/* =========================================== CACHECTRL CACHECFG CONFIG [4..7] ============================================ */ +typedef enum { /*!< CACHECTRL_CACHECFG_CONFIG */ + CACHECTRL_CACHECFG_CONFIG_W1_128B_512E = 4, /*!< W1_128B_512E : Direct mapped, 128-bit linesize, 512 entries + (4 SRAMs active) */ + CACHECTRL_CACHECFG_CONFIG_W2_128B_512E = 5, /*!< W2_128B_512E : Two-way set associative, 128-bit linesize, 512 + entries (8 SRAMs active) */ + CACHECTRL_CACHECFG_CONFIG_W1_128B_1024E = 8, /*!< W1_128B_1024E : Direct mapped, 128-bit linesize, 1024 entries + (8 SRAMs active) */ +} CACHECTRL_CACHECFG_CONFIG_Enum; + +/* ======================================================= FLASHCFG ======================================================== */ +/* ========================================== CACHECTRL FLASHCFG LPMMODE [12..13] ========================================== */ +typedef enum { /*!< CACHECTRL_FLASHCFG_LPMMODE */ + CACHECTRL_FLASHCFG_LPMMODE_NEVER = 0, /*!< NEVER : High power mode (LPM not used). */ + CACHECTRL_FLASHCFG_LPMMODE_STANDBY = 1, /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations, + but asserted while flash IDLE. */ + CACHECTRL_FLASHCFG_LPMMODE_ALWAYS = 2, /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT + must be programmed to accomodate longer read access times. */ +} CACHECTRL_FLASHCFG_LPMMODE_Enum; + +/* ========================================================= CTRL ========================================================== */ +/* =========================================== CACHECTRL CTRL RESET_STAT [1..1] ============================================ */ +typedef enum { /*!< CACHECTRL_CTRL_RESET_STAT */ + CACHECTRL_CTRL_RESET_STAT_CLEAR = 1, /*!< CLEAR : Clear Cache Stats */ +} CACHECTRL_CTRL_RESET_STAT_Enum; + +/* ======================================================= NCR0START ======================================================= */ +/* ======================================================== NCR0END ======================================================== */ +/* ======================================================= NCR1START ======================================================= */ +/* ======================================================== NCR1END ======================================================== */ +/* ========================================================= DMON0 ========================================================= */ +/* ========================================================= DMON1 ========================================================= */ +/* ========================================================= DMON2 ========================================================= */ +/* ========================================================= DMON3 ========================================================= */ +/* ========================================================= IMON0 ========================================================= */ +/* ========================================================= IMON1 ========================================================= */ +/* ========================================================= IMON2 ========================================================= */ +/* ========================================================= IMON3 ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ CLKGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CALXT ========================================================= */ +/* ========================================================= CALRC ========================================================= */ +/* ======================================================== ACALCTR ======================================================== */ +/* ========================================================= OCTRL ========================================================= */ +/* =============================================== CLKGEN OCTRL ACAL [8..10] =============================================== */ +typedef enum { /*!< CLKGEN_OCTRL_ACAL */ + CLKGEN_OCTRL_ACAL_DIS = 0, /*!< DIS : Disable Autocalibration */ + CLKGEN_OCTRL_ACAL_1024SEC = 2, /*!< 1024SEC : Autocalibrate every 1024 seconds. Once autocalibration + is done, an interrupt will be triggered at the end of 1024 + seconds. */ + CLKGEN_OCTRL_ACAL_512SEC = 3, /*!< 512SEC : Autocalibrate every 512 seconds. Once autocalibration + is done, an interrupt will be trigged at the end of 512 + seconds. */ + CLKGEN_OCTRL_ACAL_XTFREQ = 6, /*!< XTFREQ : Frequency measurement using XT. The XT clock is normally + considered much more accurate than the LFRC clock source. */ + CLKGEN_OCTRL_ACAL_EXTFREQ = 7, /*!< EXTFREQ : Frequency measurement using external clock. */ +} CLKGEN_OCTRL_ACAL_Enum; + +/* =============================================== CLKGEN OCTRL OSEL [7..7] ================================================ */ +typedef enum { /*!< CLKGEN_OCTRL_OSEL */ + CLKGEN_OCTRL_OSEL_RTC_XT = 0, /*!< RTC_XT : RTC uses the XT */ + CLKGEN_OCTRL_OSEL_RTC_LFRC = 1, /*!< RTC_LFRC : RTC uses the LFRC */ +} CLKGEN_OCTRL_OSEL_Enum; + +/* ================================================ CLKGEN OCTRL FOS [6..6] ================================================ */ +typedef enum { /*!< CLKGEN_OCTRL_FOS */ + CLKGEN_OCTRL_FOS_DIS = 0, /*!< DIS : Disable the oscillator switch on failure function. */ + CLKGEN_OCTRL_FOS_EN = 1, /*!< EN : Enable the oscillator switch on failure function. */ +} CLKGEN_OCTRL_FOS_Enum; + +/* ============================================== CLKGEN OCTRL STOPRC [1..1] =============================================== */ +typedef enum { /*!< CLKGEN_OCTRL_STOPRC */ + CLKGEN_OCTRL_STOPRC_EN = 0, /*!< EN : Enable the LFRC Oscillator to drive the RTC */ + CLKGEN_OCTRL_STOPRC_STOP = 1, /*!< STOP : Stop the LFRC Oscillator when driving the RTC */ +} CLKGEN_OCTRL_STOPRC_Enum; + +/* ============================================== CLKGEN OCTRL STOPXT [0..0] =============================================== */ +typedef enum { /*!< CLKGEN_OCTRL_STOPXT */ + CLKGEN_OCTRL_STOPXT_EN = 0, /*!< EN : Enable the XT Oscillator to drive the RTC */ + CLKGEN_OCTRL_STOPXT_STOP = 1, /*!< STOP : Stop the XT Oscillator when driving the RTC */ +} CLKGEN_OCTRL_STOPXT_Enum; + +/* ======================================================== CLKOUT ========================================================= */ +/* =============================================== CLKGEN CLKOUT CKEN [7..7] =============================================== */ +typedef enum { /*!< CLKGEN_CLKOUT_CKEN */ + CLKGEN_CLKOUT_CKEN_DIS = 0, /*!< DIS : Disable CLKOUT */ + CLKGEN_CLKOUT_CKEN_EN = 1, /*!< EN : Enable CLKOUT */ +} CLKGEN_CLKOUT_CKEN_Enum; + +/* ============================================== CLKGEN CLKOUT CKSEL [0..5] =============================================== */ +typedef enum { /*!< CLKGEN_CLKOUT_CKSEL */ + CLKGEN_CLKOUT_CKSEL_LFRC = 0, /*!< LFRC : LFRC */ + CLKGEN_CLKOUT_CKSEL_XT_DIV2 = 1, /*!< XT_DIV2 : XT / 2 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV4 = 2, /*!< XT_DIV4 : XT / 4 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV8 = 3, /*!< XT_DIV8 : XT / 8 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV16 = 4, /*!< XT_DIV16 : XT / 16 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV32 = 5, /*!< XT_DIV32 : XT / 32 */ + CLKGEN_CLKOUT_CKSEL_RTC_1Hz = 16, /*!< RTC_1Hz : 1 Hz as selected in RTC */ + CLKGEN_CLKOUT_CKSEL_XT_DIV2M = 22, /*!< XT_DIV2M : XT / 2^21 */ + CLKGEN_CLKOUT_CKSEL_XT = 23, /*!< XT : XT */ + CLKGEN_CLKOUT_CKSEL_CG_100Hz = 24, /*!< CG_100Hz : 100 Hz as selected in CLKGEN */ + CLKGEN_CLKOUT_CKSEL_HFRC = 25, /*!< HFRC : HFRC */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 = 26, /*!< HFRC_DIV4 : HFRC / 4 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 = 27, /*!< HFRC_DIV8 : HFRC / 8 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV16 = 28, /*!< HFRC_DIV16 : HFRC / 16 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 = 29, /*!< HFRC_DIV64 : HFRC / 64 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 = 30, /*!< HFRC_DIV128 : HFRC / 128 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 = 31, /*!< HFRC_DIV256 : HFRC / 256 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV512 = 32, /*!< HFRC_DIV512 : HFRC / 512 */ + CLKGEN_CLKOUT_CKSEL_FLASH_CLK = 34, /*!< FLASH_CLK : Flash Clock */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 = 35, /*!< LFRC_DIV2 : LFRC / 2 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 = 36, /*!< LFRC_DIV32 : LFRC / 32 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 = 37, /*!< LFRC_DIV512 : LFRC / 512 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K = 38, /*!< LFRC_DIV32K : LFRC / 32768 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV256 = 39, /*!< XT_DIV256 : XT / 256 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV8K = 40, /*!< XT_DIV8K : XT / 8192 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV64K = 41, /*!< XT_DIV64K : XT / 2^16 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 = 42, /*!< ULFRC_DIV16 : Uncal LFRC / 16 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 = 43, /*!< ULFRC_DIV128 : Uncal LFRC / 128 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz = 44, /*!< ULFRC_1Hz : Uncal LFRC / 1024 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K = 45, /*!< ULFRC_DIV4K : Uncal LFRC / 4096 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M = 46, /*!< ULFRC_DIV1M : Uncal LFRC / 2^20 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K = 47, /*!< HFRC_DIV64K : HFRC / 2^16 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M = 48, /*!< HFRC_DIV16M : HFRC / 2^24 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV1M = 49, /*!< LFRC_DIV1M : LFRC / 2^20 */ + CLKGEN_CLKOUT_CKSEL_HFRCNE = 50, /*!< HFRCNE : HFRC (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 = 51, /*!< HFRCNE_DIV8 : HFRC / 8 (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_XTNE = 53, /*!< XTNE : XT (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 = 54, /*!< XTNE_DIV16 : XT / 16 (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 = 55, /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_LFRCNE = 57, /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values */ +} CLKGEN_CLKOUT_CKSEL_Enum; + +/* ======================================================== CLKKEY ========================================================= */ +/* ============================================= CLKGEN CLKKEY CLKKEY [0..31] ============================================== */ +typedef enum { /*!< CLKGEN_CLKKEY_CLKKEY */ + CLKGEN_CLKKEY_CLKKEY_Key = 71, /*!< Key : Key */ +} CLKGEN_CLKKEY_CLKKEY_Enum; + +/* ========================================================= CCTRL ========================================================= */ +/* ============================================== CLKGEN CCTRL CORESEL [0..0] ============================================== */ +typedef enum { /*!< CLKGEN_CCTRL_CORESEL */ + CLKGEN_CCTRL_CORESEL_HFRC = 0, /*!< HFRC : Core Clock is HFRC */ + CLKGEN_CCTRL_CORESEL_HFRC_DIV2 = 1, /*!< HFRC_DIV2 : Core Clock is HFRC / 2 */ +} CLKGEN_CCTRL_CORESEL_Enum; + +/* ======================================================== STATUS ========================================================= */ +/* ========================================================= HFADJ ========================================================= */ +/* ============================================ CLKGEN HFADJ HFADJGAIN [21..23] ============================================ */ +typedef enum { /*!< CLKGEN_HFADJ_HFADJGAIN */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1 = 0, /*!< Gain_of_1 : HF Adjust with Gain of 1 */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2 = 1, /*!< Gain_of_1_in_2 : HF Adjust with Gain of 0.5 */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_4 = 2, /*!< Gain_of_1_in_4 : HF Adjust with Gain of 0.25 */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_8 = 3, /*!< Gain_of_1_in_8 : HF Adjust with Gain of 0.125 */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_16 = 4, /*!< Gain_of_1_in_16 : HF Adjust with Gain of 0.0625 */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_32 = 5, /*!< Gain_of_1_in_32 : HF Adjust with Gain of 0.03125 */ +} CLKGEN_HFADJ_HFADJGAIN_Enum; + +/* ============================================ CLKGEN HFADJ HFWARMUP [20..20] ============================================= */ +typedef enum { /*!< CLKGEN_HFADJ_HFWARMUP */ + CLKGEN_HFADJ_HFWARMUP_1SEC = 0, /*!< 1SEC : Autoadjust XT warmup period = 1-2 seconds */ + CLKGEN_HFADJ_HFWARMUP_2SEC = 1, /*!< 2SEC : Autoadjust XT warmup period = 2-4 seconds */ +} CLKGEN_HFADJ_HFWARMUP_Enum; + +/* ============================================== CLKGEN HFADJ HFADJCK [1..3] ============================================== */ +typedef enum { /*!< CLKGEN_HFADJ_HFADJCK */ + CLKGEN_HFADJ_HFADJCK_4SEC = 0, /*!< 4SEC : Autoadjust repeat period = 4 seconds */ + CLKGEN_HFADJ_HFADJCK_16SEC = 1, /*!< 16SEC : Autoadjust repeat period = 16 seconds */ + CLKGEN_HFADJ_HFADJCK_32SEC = 2, /*!< 32SEC : Autoadjust repeat period = 32 seconds */ + CLKGEN_HFADJ_HFADJCK_64SEC = 3, /*!< 64SEC : Autoadjust repeat period = 64 seconds */ + CLKGEN_HFADJ_HFADJCK_128SEC = 4, /*!< 128SEC : Autoadjust repeat period = 128 seconds */ + CLKGEN_HFADJ_HFADJCK_256SEC = 5, /*!< 256SEC : Autoadjust repeat period = 256 seconds */ + CLKGEN_HFADJ_HFADJCK_512SEC = 6, /*!< 512SEC : Autoadjust repeat period = 512 seconds */ + CLKGEN_HFADJ_HFADJCK_1024SEC = 7, /*!< 1024SEC : Autoadjust repeat period = 1024 seconds */ +} CLKGEN_HFADJ_HFADJCK_Enum; + +/* ============================================== CLKGEN HFADJ HFADJEN [0..0] ============================================== */ +typedef enum { /*!< CLKGEN_HFADJ_HFADJEN */ + CLKGEN_HFADJ_HFADJEN_DIS = 0, /*!< DIS : Disable the HFRC adjustment */ + CLKGEN_HFADJ_HFADJEN_EN = 1, /*!< EN : Enable the HFRC adjustment */ +} CLKGEN_HFADJ_HFADJEN_Enum; + +/* ====================================================== CLOCKENSTAT ====================================================== */ +/* ======================================== CLKGEN CLOCKENSTAT CLOCKENSTAT [0..31] ========================================= */ +typedef enum { /*!< CLKGEN_CLOCKENSTAT_CLOCKENSTAT */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_ADC_CLKEN = 1, /*!< ADC_CLKEN : Clock enable for the ADC. */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_ACTIVITY_CLKEN = 2,/*!< APBDMA_ACTIVITY_CLKEN : Clock enable for the APBDMA ACTIVITY */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOH_CLKEN = 4,/*!< APBDMA_AOH_CLKEN : Clock enable for the APBDMA AOH DOMAIN */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOL_CLKEN = 8,/*!< APBDMA_AOL_CLKEN : Clock enable for the APBDMA AOL DOMAIN */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_APB_CLKEN = 16,/*!< APBDMA_APB_CLKEN : Clock enable for the APBDMA_APB */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_BLEL_CLKEN = 32,/*!< APBDMA_BLEL_CLKEN : Clock enable for the APBDMA_BLEL */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPA_CLKEN = 64,/*!< APBDMA_HCPA_CLKEN : Clock enable for the APBDMA_HCPA */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPB_CLKEN = 128,/*!< APBDMA_HCPB_CLKEN : Clock enable for the APBDMA_HCPB */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPC_CLKEN = 256,/*!< APBDMA_HCPC_CLKEN : Clock enable for the APBDMA_HCPC */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_MSPI_CLKEN = 512,/*!< APBDMA_MSPI_CLKEN : Clock enable for the APBDMA_MSPI */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_PDM_CLKEN = 1024,/*!< APBDMA_PDM_CLKEN : Clock enable for the APBDMA_PDM */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK_CLKEN = 2048,/*!< BLEIF_CLK_CLKEN : Clock enable for the BLEIF */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK32K_CLKEN = 4096,/*!< BLEIF_CLK32K_CLKEN : Clock enable for the BLEIF 32khZ CLOCK */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER_CLKEN = 8192,/*!< CTIMER_CLKEN : Clock enable for the CTIMER BLOCK */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0A_CLKEN = 16384,/*!< CTIMER0A_CLKEN : Clock enable for the CTIMER0A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0B_CLKEN = 32768,/*!< CTIMER0B_CLKEN : Clock enable for the CTIMER0B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1A_CLKEN = 65536,/*!< CTIMER1A_CLKEN : Clock enable for the CTIMER1A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1B_CLKEN = 131072,/*!< CTIMER1B_CLKEN : Clock enable for the CTIMER1B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2A_CLKEN = 262144,/*!< CTIMER2A_CLKEN : Clock enable for the CTIMER2A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2B_CLKEN = 524288,/*!< CTIMER2B_CLKEN : Clock enable for the CTIMER2B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3A_CLKEN = 1048576,/*!< CTIMER3A_CLKEN : Clock enable for the CTIMER3A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3B_CLKEN = 2097152,/*!< CTIMER3B_CLKEN : Clock enable for the CTIMER3B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4A_CLKEN = 4194304,/*!< CTIMER4A_CLKEN : Clock enable for the CTIMER4A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4B_CLKEN = 8388608,/*!< CTIMER4B_CLKEN : Clock enable for the CTIMER4B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5A_CLKEN = 16777216,/*!< CTIMER5A_CLKEN : Clock enable for the CTIMER5A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5B_CLKEN = 33554432,/*!< CTIMER5B_CLKEN : Clock enable for the CTIMER5B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6A_CLKEN = 67108864,/*!< CTIMER6A_CLKEN : Clock enable for the CTIMER6A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6B_CLKEN = 134217728,/*!< CTIMER6B_CLKEN : Clock enable for the CTIMER6B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7A_CLKEN = 268435456,/*!< CTIMER7A_CLKEN : Clock enable for the CTIMER7A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7B_CLKEN = 536870912,/*!< CTIMER7B_CLKEN : Clock enable for the CTIMER7B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_DAP_CLKEN = 1073741824,/*!< DAP_CLKEN : Clock enable for the DAP */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_IOMSTRIFC0_CLKEN = -2147483648,/*!< IOMSTRIFC0_CLKEN : Clock enable for the IOMSTRIFC0 */ +} CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Enum; + +/* ===================================================== CLOCKEN2STAT ====================================================== */ +/* ======================================= CLKGEN CLOCKEN2STAT CLOCKEN2STAT [0..31] ======================================== */ +typedef enum { /*!< CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC1_CLKEN = 1,/*!< IOMSTRIFC1_CLKEN : Clock enable for the IO MASTER 1 IFC INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC2_CLKEN = 2,/*!< IOMSTRIFC2_CLKEN : Clock enable for the IO MASTER 2 IFC INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC3_CLKEN = 4,/*!< IOMSTRIFC3_CLKEN : Clock enable for the IO MASTER 3 IFC INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC4_CLKEN = 8,/*!< IOMSTRIFC4_CLKEN : Clock enable for the IO MASTER 4 IFC INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC5_CLKEN = 16,/*!< IOMSTRIFC5_CLKEN : Clock enable for the IO MASTER 5 IFC INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDM_CLKEN = 32,/*!< PDM_CLKEN : Clock enable for the PDM */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDMIFC_CLKEN = 64,/*!< PDMIFC_CLKEN : Clock enable for the PDM INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_CLKEN = 128,/*!< PWRCTRL_CLKEN : Clock enable for the PWRCTRL */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_COUNT_CLKEN = 256,/*!< PWRCTRL_COUNT_CLKEN : Clock enable for the PWRCTRL counter */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_RSTGEN_CLKEN = 512,/*!< RSTGEN_CLKEN : Clock enable for the RSTGEN */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_CLKEN = 1024,/*!< SCARD_CLKEN : Clock enable for the SCARD */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_ALTAPB_CLKEN = 2048,/*!< SCARD_ALTAPB_CLKEN : Clock enable for the SCARD ALTAPB */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_STIMER_CNT_CLKEN = 4096,/*!< STIMER_CNT_CLKEN : Clock enable for the STIMER_CNT_CLKEN */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_TPIU_CLKEN = 8192,/*!< TPIU_CLKEN : Clock enable for the TPIU_CLKEN */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART0HF_CLKEN = 16384,/*!< UART0HF_CLKEN : Clock enable for the UART0 HF */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART1HF_CLKEN = 32768,/*!< UART1HF_CLKEN : Clock enable for the UART1 HF */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_XT_32KHZ_EN = 1073741824,/*!< XT_32KHZ_EN : Clock enable for the XT 32KHZ */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_FORCEHFRC = -2147483648,/*!< FORCEHFRC : HFRC is forced on Status. */ +} CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Enum; + +/* ===================================================== CLOCKEN3STAT ====================================================== */ +/* ======================================= CLKGEN CLOCKEN3STAT CLOCKEN3STAT [0..31] ======================================== */ +typedef enum { /*!< CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DAP_enabled = 131072,/*!< DAP_enabled : DAP clock is enabled [17] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_VCOMP_enabled = 262144,/*!< VCOMP_enabled : VCOMP powerdown indicator [18] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_XTAL_enabled = 16777216,/*!< XTAL_enabled : XTAL is enabled [24] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_enabled = 33554432,/*!< HFRC_enabled : HFRC is enabled [25] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFADJEN = 67108864,/*!< HFADJEN : HFRC Adjust enabled [26] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_en_out = 134217728,/*!< HFRC_en_out : HFRC Enabled out [27] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RTC_XT = 268435456,/*!< RTC_XT : RTC use XT [28] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_xtal_en = 536870912,/*!< clkout_xtal_en : XTAL clkout enabled [29] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_hfrc_en = 1073741824,/*!< clkout_hfrc_en : HFRC clkout enabled [30] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_flashclk_en = -2147483648,/*!< flashclk_en : Flash clk is enabled [31] */ +} CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Enum; + +/* ======================================================= FREQCTRL ======================================================== */ +/* ============================================ CLKGEN FREQCTRL BURSTREQ [0..0] ============================================ */ +typedef enum { /*!< CLKGEN_FREQCTRL_BURSTREQ */ + CLKGEN_FREQCTRL_BURSTREQ_DIS = 0, /*!< DIS : Frequency for ARM core stays at 48MHz */ + CLKGEN_FREQCTRL_BURSTREQ_EN = 1, /*!< EN : Frequency for ARM core is increased to 96MHz */ +} CLKGEN_FREQCTRL_BURSTREQ_Enum; + +/* ===================================================== BLEBUCKTONADJ ===================================================== */ +/* ===================================== CLKGEN BLEBUCKTONADJ ZEROLENDETECTEN [27..27] ===================================== */ +typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_DIS = 0, /*!< DIS : Disable Zero Length Detect */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_EN = 1, /*!< EN : Enable Zero Length Detect */ +} CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Enum; + +/* ==================================== CLKGEN BLEBUCKTONADJ ZEROLENDETECTTRIM [23..26] ==================================== */ +typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetF = 15,/*!< SetF : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 81us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetE = 14,/*!< SetE : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 75.6us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetD = 13,/*!< SetD : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 70.2us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetC = 12,/*!< SetC : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 64.8us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetB = 11,/*!< SetB : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 59.4us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetA = 10,/*!< SetA : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 54.0us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set9 = 9,/*!< Set9 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 48.6us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set8 = 8,/*!< Set8 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 43.2us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set7 = 7,/*!< Set7 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 37.8us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set6 = 6,/*!< Set6 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 32.4us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set5 = 5,/*!< Set5 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 27.0us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set4 = 4,/*!< Set4 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 21.6us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set3 = 3,/*!< Set3 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 16.2us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set2 = 2,/*!< Set2 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 10.8us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set1 = 1,/*!< Set1 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 5.4us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set0 = 0,/*!< Set0 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 2.0us (10 percent margin of error) or more */ +} CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Enum; + +/* ======================================= CLKGEN BLEBUCKTONADJ TONADJUSTEN [22..22] ======================================= */ +typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTEN */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_DIS = 0, /*!< DIS : Disable Adjust for BLE BUCK TON trim */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_EN = 1, /*!< EN : Enable Adjust for BLE BUCK TON trim */ +} CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Enum; + +/* ===================================== CLKGEN BLEBUCKTONADJ TONADJUSTPERIOD [20..21] ===================================== */ +typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_3KHz = 3,/*!< HFRC_3KHz : Adjust done for every 1 3KHz period */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_12KHz = 2,/*!< HFRC_12KHz : Adjust done for every 1 12KHz period */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_47KHz = 1,/*!< HFRC_47KHz : Adjust done for every 1 47KHz period */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_94KHz = 0,/*!< HFRC_94KHz : Adjust done for every 1 94KHz period */ +} CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Enum; + +/* ======================================================= INTRPTEN ======================================================== */ +/* ====================================================== INTRPTSTAT ======================================================= */ +/* ======================================================= INTRPTCLR ======================================================= */ +/* ======================================================= INTRPTSET ======================================================= */ + + +/* =========================================================================================================================== */ +/* ================ CTIMER ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TMR0 ========================================================== */ +/* ======================================================== CMPRA0 ========================================================= */ +/* ======================================================== CMPRB0 ========================================================= */ +/* ========================================================= CTRL0 ========================================================= */ +/* ============================================= CTIMER CTRL0 CTLINK0 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_CTLINK0 */ + CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL0_CTLINK0_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A0/B0 timers into a single 32-bit timer. */ +} CTIMER_CTRL0_CTLINK0_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0POL */ + CTIMER_CTRL0_TMRB0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB0 pin is the same as the + timer output. */ + CTIMER_CTRL0_TMRB0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB0 pin is the inverse of + the timer output. */ +} CTIMER_CTRL0_TMRB0POL_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0CLR */ + CTIMER_CTRL0_TMRB0CLR_RUN = 0, /*!< RUN : Allow counter/timer B0 to run */ + CTIMER_CTRL0_TMRB0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B0 at 0x0000. */ +} CTIMER_CTRL0_TMRB0CLR_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0IE1 */ + CTIMER_CTRL0_TMRB0IE1_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL0_TMRB0IE1_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL0_TMRB0IE1_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0IE0 */ + CTIMER_CTRL0_TMRB0IE0_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL0_TMRB0IE0_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL0_TMRB0IE0_Enum; + +/* ============================================= CTIMER CTRL0 TMRB0FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0FN */ + CTIMER_CTRL0_TMRB0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B0, stop. */ + CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B0, restart. */ + CTIMER_CTRL0_TMRB0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B0, assert, + count to CMPR1B0, deassert, stop. */ + CTIMER_CTRL0_TMRB0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B0, assert, count + to CMPR1B0, deassert, restart. */ + CTIMER_CTRL0_TMRB0FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL0_TMRB0FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL0_TMRB0FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL0_TMRB0FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL0_TMRB0FN_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0CLK */ + CTIMER_CTRL0_TMRB0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL0_TMRB0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL0_TMRB0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL0_TMRB0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL0_TMRB0CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL0_TMRB0CLK_CTMRA0 = 20, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB1 = 21, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRA1 = 22, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL0_TMRB0CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL0_TMRB0CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL0_TMRB0CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL0_TMRB0CLK_Enum; + +/* ============================================= CTIMER CTRL0 TMRB0EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0EN */ + CTIMER_CTRL0_TMRB0EN_DIS = 0, /*!< DIS : Counter/Timer B0 Disable. */ + CTIMER_CTRL0_TMRB0EN_EN = 1, /*!< EN : Counter/Timer B0 Enable. */ +} CTIMER_CTRL0_TMRB0EN_Enum; + +/* ============================================ CTIMER CTRL0 TMRA0POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0POL */ + CTIMER_CTRL0_TMRA0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA0 pin is the same as the + timer output. */ + CTIMER_CTRL0_TMRA0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA0 pin is the inverse of + the timer output. */ +} CTIMER_CTRL0_TMRA0POL_Enum; + +/* ============================================ CTIMER CTRL0 TMRA0CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0CLR */ + CTIMER_CTRL0_TMRA0CLR_RUN = 0, /*!< RUN : Allow counter/timer A0 to run */ + CTIMER_CTRL0_TMRA0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A0 at 0x0000. */ +} CTIMER_CTRL0_TMRA0CLR_Enum; + +/* ============================================ CTIMER CTRL0 TMRA0IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0IE1 */ + CTIMER_CTRL0_TMRA0IE1_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL0_TMRA0IE1_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL0_TMRA0IE1_Enum; + +/* ============================================= CTIMER CTRL0 TMRA0IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0IE0 */ + CTIMER_CTRL0_TMRA0IE0_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL0_TMRA0IE0_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL0_TMRA0IE0_Enum; + +/* ============================================== CTIMER CTRL0 TMRA0FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0FN */ + CTIMER_CTRL0_TMRA0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A0, stop. */ + CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A0, restart. */ + CTIMER_CTRL0_TMRA0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A0, assert, + count to CMPR1A0, deassert, stop. */ + CTIMER_CTRL0_TMRA0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A0, assert, count + to CMPR1A0, deassert, restart. */ + CTIMER_CTRL0_TMRA0FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL0_TMRA0FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL0_TMRA0FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL0_TMRA0FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL0_TMRA0FN_Enum; + +/* ============================================= CTIMER CTRL0 TMRA0CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0CLK */ + CTIMER_CTRL0_TMRA0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL0_TMRA0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL0_TMRA0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL0_TMRA0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL0_TMRA0CLK_CTMRB0 = 20, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL0_TMRA0CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL0_TMRA0CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL0_TMRA0CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL0_TMRA0CLK_Enum; + +/* ============================================== CTIMER CTRL0 TMRA0EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0EN */ + CTIMER_CTRL0_TMRA0EN_DIS = 0, /*!< DIS : Counter/Timer A0 Disable. */ + CTIMER_CTRL0_TMRA0EN_EN = 1, /*!< EN : Counter/Timer A0 Enable. */ +} CTIMER_CTRL0_TMRA0EN_Enum; + +/* ======================================================= CMPRAUXA0 ======================================================= */ +/* ======================================================= CMPRAUXB0 ======================================================= */ +/* ========================================================= AUX0 ========================================================== */ +/* ============================================ CTIMER AUX0 TMRB0EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRB0EN23 */ + CTIMER_AUX0_TMRB0EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX0_TMRB0EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX0_TMRB0EN23_Enum; + +/* ============================================ CTIMER AUX0 TMRB0POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX0_TMRB0POL23 */ + CTIMER_AUX0_TMRB0POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX0_TMRB0POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX0_TMRB0POL23_Enum; + +/* ============================================ CTIMER AUX0 TMRB0TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRB0TINV */ + CTIMER_AUX0_TMRB0TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX0_TMRB0TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX0_TMRB0TINV_Enum; + +/* =========================================== CTIMER AUX0 TMRB0NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX0_TMRB0NOSYNC */ + CTIMER_AUX0_TMRB0NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX0_TMRB0NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX0_TMRB0NOSYNC_Enum; + +/* ============================================ CTIMER AUX0 TMRB0TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRB0TRIG */ + CTIMER_AUX0_TMRB0TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX0_TMRB0TRIG_A0OUT = 1, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ + CTIMER_AUX0_TMRB0TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX0_TMRB0TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX0_TMRB0TRIG_B2OUT = 4, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX0_TMRB0TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ + CTIMER_AUX0_TMRB0TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX0_TMRB0TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX0_TMRB0TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX0_TMRB0TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX0_TMRB0TRIG_B7OUT2 = 10, /*!< B7OUT2 : Trigger source is CTIMERB7 OUT2. */ + CTIMER_AUX0_TMRB0TRIG_A2OUT2 = 11, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX0_TMRB0TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX0_TMRB0TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX0_TMRB0TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ + CTIMER_AUX0_TMRB0TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ +} CTIMER_AUX0_TMRB0TRIG_Enum; + +/* ============================================ CTIMER AUX0 TMRA0EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRA0EN23 */ + CTIMER_AUX0_TMRA0EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX0_TMRA0EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX0_TMRA0EN23_Enum; + +/* ============================================ CTIMER AUX0 TMRA0POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX0_TMRA0POL23 */ + CTIMER_AUX0_TMRA0POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX0_TMRA0POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX0_TMRA0POL23_Enum; + +/* ============================================ CTIMER AUX0 TMRA0TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRA0TINV */ + CTIMER_AUX0_TMRA0TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX0_TMRA0TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX0_TMRA0TINV_Enum; + +/* =========================================== CTIMER AUX0 TMRA0NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX0_TMRA0NOSYNC */ + CTIMER_AUX0_TMRA0NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX0_TMRA0NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX0_TMRA0NOSYNC_Enum; + +/* ============================================= CTIMER AUX0 TMRA0TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRA0TRIG */ + CTIMER_AUX0_TMRA0TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX0_TMRA0TRIG_B0OUT = 1, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ + CTIMER_AUX0_TMRA0TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX0_TMRA0TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX0_TMRA0TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX0_TMRA0TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX0_TMRA0TRIG_A5OUT = 6, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ + CTIMER_AUX0_TMRA0TRIG_B5OUT = 7, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ + CTIMER_AUX0_TMRA0TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX0_TMRA0TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX0_TMRA0TRIG_B6OUT2 = 10, /*!< B6OUT2 : Trigger source is CTIMERB6 OUT2. */ + CTIMER_AUX0_TMRA0TRIG_A2OUT2 = 11, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX0_TMRA0TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX0_TMRA0TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX0_TMRA0TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX0_TMRA0TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX0_TMRA0TRIG_Enum; + +/* ========================================================= TMR1 ========================================================== */ +/* ======================================================== CMPRA1 ========================================================= */ +/* ======================================================== CMPRB1 ========================================================= */ +/* ========================================================= CTRL1 ========================================================= */ +/* ============================================= CTIMER CTRL1 CTLINK1 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_CTLINK1 */ + CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A1/B1 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL1_CTLINK1_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A1/B1 timers into a single 32-bit timer. */ +} CTIMER_CTRL1_CTLINK1_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1POL */ + CTIMER_CTRL1_TMRB1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB1 pin is the same as the + timer output. */ + CTIMER_CTRL1_TMRB1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB1 pin is the inverse of + the timer output. */ +} CTIMER_CTRL1_TMRB1POL_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1CLR */ + CTIMER_CTRL1_TMRB1CLR_RUN = 0, /*!< RUN : Allow counter/timer B1 to run */ + CTIMER_CTRL1_TMRB1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B1 at 0x0000. */ +} CTIMER_CTRL1_TMRB1CLR_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1IE1 */ + CTIMER_CTRL1_TMRB1IE1_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL1_TMRB1IE1_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL1_TMRB1IE1_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1IE0 */ + CTIMER_CTRL1_TMRB1IE0_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL1_TMRB1IE0_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL1_TMRB1IE0_Enum; + +/* ============================================= CTIMER CTRL1 TMRB1FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1FN */ + CTIMER_CTRL1_TMRB1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B1, stop. */ + CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B1, restart. */ + CTIMER_CTRL1_TMRB1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B1, assert, + count to CMPR1B1, deassert, stop. */ + CTIMER_CTRL1_TMRB1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B1, assert, count + to CMPR1B1, deassert, restart. */ + CTIMER_CTRL1_TMRB1FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL1_TMRB1FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL1_TMRB1FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL1_TMRB1FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL1_TMRB1FN_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1CLK */ + CTIMER_CTRL1_TMRB1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL1_TMRB1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL1_TMRB1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL1_TMRB1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL1_TMRB1CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL1_TMRB1CLK_CTMRA1 = 20, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL1_TMRB1CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL1_TMRB1CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL1_TMRB1CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL1_TMRB1CLK_Enum; + +/* ============================================= CTIMER CTRL1 TMRB1EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1EN */ + CTIMER_CTRL1_TMRB1EN_DIS = 0, /*!< DIS : Counter/Timer B1 Disable. */ + CTIMER_CTRL1_TMRB1EN_EN = 1, /*!< EN : Counter/Timer B1 Enable. */ +} CTIMER_CTRL1_TMRB1EN_Enum; + +/* ============================================ CTIMER CTRL1 TMRA1POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1POL */ + CTIMER_CTRL1_TMRA1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA1 pin is the same as the + timer output. */ + CTIMER_CTRL1_TMRA1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA1 pin is the inverse of + the timer output. */ +} CTIMER_CTRL1_TMRA1POL_Enum; + +/* ============================================ CTIMER CTRL1 TMRA1CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1CLR */ + CTIMER_CTRL1_TMRA1CLR_RUN = 0, /*!< RUN : Allow counter/timer A1 to run */ + CTIMER_CTRL1_TMRA1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A1 at 0x0000. */ +} CTIMER_CTRL1_TMRA1CLR_Enum; + +/* ============================================ CTIMER CTRL1 TMRA1IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1IE1 */ + CTIMER_CTRL1_TMRA1IE1_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL1_TMRA1IE1_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL1_TMRA1IE1_Enum; + +/* ============================================= CTIMER CTRL1 TMRA1IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1IE0 */ + CTIMER_CTRL1_TMRA1IE0_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL1_TMRA1IE0_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL1_TMRA1IE0_Enum; + +/* ============================================== CTIMER CTRL1 TMRA1FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1FN */ + CTIMER_CTRL1_TMRA1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A1, stop. */ + CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A1, restart. */ + CTIMER_CTRL1_TMRA1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A1, assert, + count to CMPR1A1, deassert, stop. */ + CTIMER_CTRL1_TMRA1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A1, assert, count + to CMPR1A1, deassert, restart. */ + CTIMER_CTRL1_TMRA1FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL1_TMRA1FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL1_TMRA1FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL1_TMRA1FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL1_TMRA1FN_Enum; + +/* ============================================= CTIMER CTRL1 TMRA1CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1CLK */ + CTIMER_CTRL1_TMRA1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL1_TMRA1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL1_TMRA1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL1_TMRA1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL1_TMRA1CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL1_TMRA1CLK_CTMRB1 = 20, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL1_TMRA1CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL1_TMRA1CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL1_TMRA1CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL1_TMRA1CLK_Enum; + +/* ============================================== CTIMER CTRL1 TMRA1EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1EN */ + CTIMER_CTRL1_TMRA1EN_DIS = 0, /*!< DIS : Counter/Timer A1 Disable. */ + CTIMER_CTRL1_TMRA1EN_EN = 1, /*!< EN : Counter/Timer A1 Enable. */ +} CTIMER_CTRL1_TMRA1EN_Enum; + +/* ======================================================= CMPRAUXA1 ======================================================= */ +/* ======================================================= CMPRAUXB1 ======================================================= */ +/* ========================================================= AUX1 ========================================================== */ +/* ============================================ CTIMER AUX1 TMRB1EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRB1EN23 */ + CTIMER_AUX1_TMRB1EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX1_TMRB1EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX1_TMRB1EN23_Enum; + +/* ============================================ CTIMER AUX1 TMRB1POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX1_TMRB1POL23 */ + CTIMER_AUX1_TMRB1POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX1_TMRB1POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX1_TMRB1POL23_Enum; + +/* ============================================ CTIMER AUX1 TMRB1TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRB1TINV */ + CTIMER_AUX1_TMRB1TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX1_TMRB1TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX1_TMRB1TINV_Enum; + +/* =========================================== CTIMER AUX1 TMRB1NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX1_TMRB1NOSYNC */ + CTIMER_AUX1_TMRB1NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX1_TMRB1NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX1_TMRB1NOSYNC_Enum; + +/* ============================================ CTIMER AUX1 TMRB1TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRB1TRIG */ + CTIMER_AUX1_TMRB1TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX1_TMRB1TRIG_A1OUT = 1, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX1_TMRB1TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX1_TMRB1TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX1_TMRB1TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ + CTIMER_AUX1_TMRB1TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ + CTIMER_AUX1_TMRB1TRIG_A0OUT = 6, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ + CTIMER_AUX1_TMRB1TRIG_B0OUT = 7, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ + CTIMER_AUX1_TMRB1TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX1_TMRB1TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX1_TMRB1TRIG_A4OUT2 = 10, /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2. */ + CTIMER_AUX1_TMRB1TRIG_B4OUT2 = 11, /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2. */ + CTIMER_AUX1_TMRB1TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX1_TMRB1TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX1_TMRB1TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ + CTIMER_AUX1_TMRB1TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ +} CTIMER_AUX1_TMRB1TRIG_Enum; + +/* ============================================ CTIMER AUX1 TMRA1EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRA1EN23 */ + CTIMER_AUX1_TMRA1EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX1_TMRA1EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX1_TMRA1EN23_Enum; + +/* ============================================ CTIMER AUX1 TMRA1POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX1_TMRA1POL23 */ + CTIMER_AUX1_TMRA1POL23_NORMAL = 0, /*!< NORMAL : Upper output normal polarity */ + CTIMER_AUX1_TMRA1POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX1_TMRA1POL23_Enum; + +/* ============================================ CTIMER AUX1 TMRA1TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRA1TINV */ + CTIMER_AUX1_TMRA1TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX1_TMRA1TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX1_TMRA1TINV_Enum; + +/* =========================================== CTIMER AUX1 TMRA1NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX1_TMRA1NOSYNC */ + CTIMER_AUX1_TMRA1NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX1_TMRA1NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX1_TMRA1NOSYNC_Enum; + +/* ============================================= CTIMER AUX1 TMRA1TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRA1TRIG */ + CTIMER_AUX1_TMRA1TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX1_TMRA1TRIG_B1OUT = 1, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX1_TMRA1TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX1_TMRA1TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX1_TMRA1TRIG_A0OUT = 4, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ + CTIMER_AUX1_TMRA1TRIG_B0OUT = 5, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ + CTIMER_AUX1_TMRA1TRIG_A5OUT = 6, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ + CTIMER_AUX1_TMRA1TRIG_B5OUT = 7, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ + CTIMER_AUX1_TMRA1TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX1_TMRA1TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX1_TMRA1TRIG_A4OUT2 = 10, /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2. */ + CTIMER_AUX1_TMRA1TRIG_B4OUT2 = 11, /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2. */ + CTIMER_AUX1_TMRA1TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX1_TMRA1TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX1_TMRA1TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ + CTIMER_AUX1_TMRA1TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ +} CTIMER_AUX1_TMRA1TRIG_Enum; + +/* ========================================================= TMR2 ========================================================== */ +/* ======================================================== CMPRA2 ========================================================= */ +/* ======================================================== CMPRB2 ========================================================= */ +/* ========================================================= CTRL2 ========================================================= */ +/* ============================================= CTIMER CTRL2 CTLINK2 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_CTLINK2 */ + CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A2/B2 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL2_CTLINK2_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A2/B2 timers into a single 32-bit timer. */ +} CTIMER_CTRL2_CTLINK2_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2POL */ + CTIMER_CTRL2_TMRB2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB2 pin is the same as the + timer output. */ + CTIMER_CTRL2_TMRB2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB2 pin is the inverse of + the timer output. */ +} CTIMER_CTRL2_TMRB2POL_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2CLR */ + CTIMER_CTRL2_TMRB2CLR_RUN = 0, /*!< RUN : Allow counter/timer B2 to run */ + CTIMER_CTRL2_TMRB2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B2 at 0x0000. */ +} CTIMER_CTRL2_TMRB2CLR_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2IE1 */ + CTIMER_CTRL2_TMRB2IE1_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL2_TMRB2IE1_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL2_TMRB2IE1_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2IE0 */ + CTIMER_CTRL2_TMRB2IE0_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL2_TMRB2IE0_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL2_TMRB2IE0_Enum; + +/* ============================================= CTIMER CTRL2 TMRB2FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2FN */ + CTIMER_CTRL2_TMRB2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B2, stop. */ + CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B2, restart. */ + CTIMER_CTRL2_TMRB2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B2, assert, + count to CMPR1B2, deassert, stop. */ + CTIMER_CTRL2_TMRB2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B2, assert, count + to CMPR1B2, deassert, restart. */ + CTIMER_CTRL2_TMRB2FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL2_TMRB2FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL2_TMRB2FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL2_TMRB2FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL2_TMRB2FN_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2CLK */ + CTIMER_CTRL2_TMRB2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL2_TMRB2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL2_TMRB2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL2_TMRB2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL2_TMRB2CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL2_TMRB2CLK_CTMRA2 = 20, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB3 = 21, /*!< CTMRB3 : Clock source is CTIMERA3 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRA3 = 22, /*!< CTMRA3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL2_TMRB2CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL2_TMRB2CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL2_TMRB2CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL2_TMRB2CLK_Enum; + +/* ============================================= CTIMER CTRL2 TMRB2EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2EN */ + CTIMER_CTRL2_TMRB2EN_DIS = 0, /*!< DIS : Counter/Timer B2 Disable. */ + CTIMER_CTRL2_TMRB2EN_EN = 1, /*!< EN : Counter/Timer B2 Enable. */ +} CTIMER_CTRL2_TMRB2EN_Enum; + +/* ============================================ CTIMER CTRL2 TMRA2POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2POL */ + CTIMER_CTRL2_TMRA2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA2 pin is the same as the + timer output. */ + CTIMER_CTRL2_TMRA2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA2 pin is the inverse of + the timer output. */ +} CTIMER_CTRL2_TMRA2POL_Enum; + +/* ============================================ CTIMER CTRL2 TMRA2CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2CLR */ + CTIMER_CTRL2_TMRA2CLR_RUN = 0, /*!< RUN : Allow counter/timer A2 to run */ + CTIMER_CTRL2_TMRA2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A2 at 0x0000. */ +} CTIMER_CTRL2_TMRA2CLR_Enum; + +/* ============================================ CTIMER CTRL2 TMRA2IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2IE1 */ + CTIMER_CTRL2_TMRA2IE1_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL2_TMRA2IE1_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL2_TMRA2IE1_Enum; + +/* ============================================= CTIMER CTRL2 TMRA2IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2IE0 */ + CTIMER_CTRL2_TMRA2IE0_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL2_TMRA2IE0_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL2_TMRA2IE0_Enum; + +/* ============================================== CTIMER CTRL2 TMRA2FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2FN */ + CTIMER_CTRL2_TMRA2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A2, stop. */ + CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A2, restart. */ + CTIMER_CTRL2_TMRA2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A2, assert, + count to CMPR1A2, deassert, stop. */ + CTIMER_CTRL2_TMRA2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A2, assert, count + to CMPR1A2, deassert, restart. */ + CTIMER_CTRL2_TMRA2FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL2_TMRA2FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL2_TMRA2FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL2_TMRA2FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL2_TMRA2FN_Enum; + +/* ============================================= CTIMER CTRL2 TMRA2CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2CLK */ + CTIMER_CTRL2_TMRA2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL2_TMRA2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL2_TMRA2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL2_TMRA2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL2_TMRA2CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL2_TMRA2CLK_CTMRB2 = 20, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB3 = 21, /*!< CTMRB3 : Clock source is CTIMERA3 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRA3 = 22, /*!< CTMRA3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL2_TMRA2CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL2_TMRA2CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL2_TMRA2CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL2_TMRA2CLK_Enum; + +/* ============================================== CTIMER CTRL2 TMRA2EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2EN */ + CTIMER_CTRL2_TMRA2EN_DIS = 0, /*!< DIS : Counter/Timer A2 Disable. */ + CTIMER_CTRL2_TMRA2EN_EN = 1, /*!< EN : Counter/Timer A2 Enable. */ +} CTIMER_CTRL2_TMRA2EN_Enum; + +/* ======================================================= CMPRAUXA2 ======================================================= */ +/* ======================================================= CMPRAUXB2 ======================================================= */ +/* ========================================================= AUX2 ========================================================== */ +/* ============================================ CTIMER AUX2 TMRB2EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRB2EN23 */ + CTIMER_AUX2_TMRB2EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX2_TMRB2EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX2_TMRB2EN23_Enum; + +/* ============================================ CTIMER AUX2 TMRB2POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX2_TMRB2POL23 */ + CTIMER_AUX2_TMRB2POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX2_TMRB2POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX2_TMRB2POL23_Enum; + +/* ============================================ CTIMER AUX2 TMRB2TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRB2TINV */ + CTIMER_AUX2_TMRB2TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX2_TMRB2TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX2_TMRB2TINV_Enum; + +/* =========================================== CTIMER AUX2 TMRB2NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX2_TMRB2NOSYNC */ + CTIMER_AUX2_TMRB2NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX2_TMRB2NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX2_TMRB2NOSYNC_Enum; + +/* ============================================ CTIMER AUX2 TMRB2TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRB2TRIG */ + CTIMER_AUX2_TMRB2TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX2_TMRB2TRIG_A2OUT = 1, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX2_TMRB2TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX2_TMRB2TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX2_TMRB2TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX2_TMRB2TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX2_TMRB2TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX2_TMRB2TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX2_TMRB2TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX2_TMRB2TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX2_TMRB2TRIG_A5OUT2 = 10, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ + CTIMER_AUX2_TMRB2TRIG_B5OUT2 = 11, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ + CTIMER_AUX2_TMRB2TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX2_TMRB2TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX2_TMRB2TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX2_TMRB2TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX2_TMRB2TRIG_Enum; + +/* ============================================ CTIMER AUX2 TMRA2EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRA2EN23 */ + CTIMER_AUX2_TMRA2EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX2_TMRA2EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX2_TMRA2EN23_Enum; + +/* ============================================ CTIMER AUX2 TMRA2POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX2_TMRA2POL23 */ + CTIMER_AUX2_TMRA2POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX2_TMRA2POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX2_TMRA2POL23_Enum; + +/* ============================================ CTIMER AUX2 TMRA2TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRA2TINV */ + CTIMER_AUX2_TMRA2TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX2_TMRA2TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX2_TMRA2TINV_Enum; + +/* =========================================== CTIMER AUX2 TMRA2NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX2_TMRA2NOSYNC */ + CTIMER_AUX2_TMRA2NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX2_TMRA2NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX2_TMRA2NOSYNC_Enum; + +/* ============================================= CTIMER AUX2 TMRA2TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRA2TRIG */ + CTIMER_AUX2_TMRA2TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX2_TMRA2TRIG_B2OUT = 1, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX2_TMRA2TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX2_TMRA2TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX2_TMRA2TRIG_A0OUT = 4, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ + CTIMER_AUX2_TMRA2TRIG_B0OUT = 5, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ + CTIMER_AUX2_TMRA2TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX2_TMRA2TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX2_TMRA2TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX2_TMRA2TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX2_TMRA2TRIG_A5OUT2 = 10, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ + CTIMER_AUX2_TMRA2TRIG_B5OUT2 = 11, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ + CTIMER_AUX2_TMRA2TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX2_TMRA2TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX2_TMRA2TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX2_TMRA2TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX2_TMRA2TRIG_Enum; + +/* ========================================================= TMR3 ========================================================== */ +/* ======================================================== CMPRA3 ========================================================= */ +/* ======================================================== CMPRB3 ========================================================= */ +/* ========================================================= CTRL3 ========================================================= */ +/* ============================================= CTIMER CTRL3 CTLINK3 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_CTLINK3 */ + CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A3/B3 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL3_CTLINK3_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A3/B3 timers into a single 32-bit timer. */ +} CTIMER_CTRL3_CTLINK3_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3POL */ + CTIMER_CTRL3_TMRB3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB3 pin is the same as the + timer output. */ + CTIMER_CTRL3_TMRB3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB3 pin is the inverse of + the timer output. */ +} CTIMER_CTRL3_TMRB3POL_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3CLR */ + CTIMER_CTRL3_TMRB3CLR_RUN = 0, /*!< RUN : Allow counter/timer B3 to run */ + CTIMER_CTRL3_TMRB3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B3 at 0x0000. */ +} CTIMER_CTRL3_TMRB3CLR_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3IE1 */ + CTIMER_CTRL3_TMRB3IE1_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL3_TMRB3IE1_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL3_TMRB3IE1_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3IE0 */ + CTIMER_CTRL3_TMRB3IE0_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL3_TMRB3IE0_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL3_TMRB3IE0_Enum; + +/* ============================================= CTIMER CTRL3 TMRB3FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3FN */ + CTIMER_CTRL3_TMRB3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B3, stop. */ + CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B3, restart. */ + CTIMER_CTRL3_TMRB3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B3, assert, + count to CMPR1B3, deassert, stop. */ + CTIMER_CTRL3_TMRB3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B3, assert, count + to CMPR1B3, deassert, restart. */ + CTIMER_CTRL3_TMRB3FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL3_TMRB3FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL3_TMRB3FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL3_TMRB3FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL3_TMRB3FN_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3CLK */ + CTIMER_CTRL3_TMRB3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL3_TMRB3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL3_TMRB3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL3_TMRB3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL3_TMRB3CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL3_TMRB3CLK_CTMRA3 = 20, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL3_TMRB3CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL3_TMRB3CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL3_TMRB3CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL3_TMRB3CLK_Enum; + +/* ============================================= CTIMER CTRL3 TMRB3EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3EN */ + CTIMER_CTRL3_TMRB3EN_DIS = 0, /*!< DIS : Counter/Timer B3 Disable. */ + CTIMER_CTRL3_TMRB3EN_EN = 1, /*!< EN : Counter/Timer B3 Enable. */ +} CTIMER_CTRL3_TMRB3EN_Enum; + +/* ============================================ CTIMER CTRL3 TMRA3POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3POL */ + CTIMER_CTRL3_TMRA3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA3 pin is the same as the + timer output. */ + CTIMER_CTRL3_TMRA3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA3 pin is the inverse of + the timer output. */ +} CTIMER_CTRL3_TMRA3POL_Enum; + +/* ============================================ CTIMER CTRL3 TMRA3CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3CLR */ + CTIMER_CTRL3_TMRA3CLR_RUN = 0, /*!< RUN : Allow counter/timer A3 to run */ + CTIMER_CTRL3_TMRA3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A3 at 0x0000. */ +} CTIMER_CTRL3_TMRA3CLR_Enum; + +/* ============================================ CTIMER CTRL3 TMRA3IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3IE1 */ + CTIMER_CTRL3_TMRA3IE1_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL3_TMRA3IE1_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL3_TMRA3IE1_Enum; + +/* ============================================= CTIMER CTRL3 TMRA3IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3IE0 */ + CTIMER_CTRL3_TMRA3IE0_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL3_TMRA3IE0_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL3_TMRA3IE0_Enum; + +/* ============================================== CTIMER CTRL3 TMRA3FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3FN */ + CTIMER_CTRL3_TMRA3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A3, stop. */ + CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A3, restart. */ + CTIMER_CTRL3_TMRA3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A3, assert, + count to CMPR1A3, deassert, stop. */ + CTIMER_CTRL3_TMRA3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A3, assert, count + to CMPR1A3, deassert, restart. */ + CTIMER_CTRL3_TMRA3FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL3_TMRA3FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL3_TMRA3FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL3_TMRA3FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL3_TMRA3FN_Enum; + +/* ============================================= CTIMER CTRL3 TMRA3CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3CLK */ + CTIMER_CTRL3_TMRA3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL3_TMRA3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL3_TMRA3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL3_TMRA3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL3_TMRA3CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL3_TMRA3CLK_CTMRB3 = 20, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL3_TMRA3CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL3_TMRA3CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL3_TMRA3CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL3_TMRA3CLK_Enum; + +/* ============================================== CTIMER CTRL3 TMRA3EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3EN */ + CTIMER_CTRL3_TMRA3EN_DIS = 0, /*!< DIS : Counter/Timer A3 Disable. */ + CTIMER_CTRL3_TMRA3EN_EN = 1, /*!< EN : Counter/Timer A3 Enable. */ +} CTIMER_CTRL3_TMRA3EN_Enum; + +/* ======================================================= CMPRAUXA3 ======================================================= */ +/* ======================================================= CMPRAUXB3 ======================================================= */ +/* ========================================================= AUX3 ========================================================== */ +/* ============================================ CTIMER AUX3 TMRB3EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRB3EN23 */ + CTIMER_AUX3_TMRB3EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX3_TMRB3EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX3_TMRB3EN23_Enum; + +/* ============================================ CTIMER AUX3 TMRB3POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX3_TMRB3POL23 */ + CTIMER_AUX3_TMRB3POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX3_TMRB3POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX3_TMRB3POL23_Enum; + +/* ============================================ CTIMER AUX3 TMRB3TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRB3TINV */ + CTIMER_AUX3_TMRB3TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX3_TMRB3TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX3_TMRB3TINV_Enum; + +/* =========================================== CTIMER AUX3 TMRB3NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX3_TMRB3NOSYNC */ + CTIMER_AUX3_TMRB3NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX3_TMRB3NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX3_TMRB3NOSYNC_Enum; + +/* ============================================ CTIMER AUX3 TMRB3TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRB3TRIG */ + CTIMER_AUX3_TMRB3TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX3_TMRB3TRIG_A3OUT = 1, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX3_TMRB3TRIG_B2OUT = 2, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX3_TMRB3TRIG_A2OUT = 3, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX3_TMRB3TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX3_TMRB3TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX3_TMRB3TRIG_A6OUT = 6, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ + CTIMER_AUX3_TMRB3TRIG_B6OUT = 7, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ + CTIMER_AUX3_TMRB3TRIG_B5OUT2 = 8, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ + CTIMER_AUX3_TMRB3TRIG_A5OUT2 = 9, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ + CTIMER_AUX3_TMRB3TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ + CTIMER_AUX3_TMRB3TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ + CTIMER_AUX3_TMRB3TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX3_TMRB3TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX3_TMRB3TRIG_B2OUT2DUAL = 14, /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge. */ + CTIMER_AUX3_TMRB3TRIG_A2OUT2DUAL = 15, /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge. */ +} CTIMER_AUX3_TMRB3TRIG_Enum; + +/* ============================================ CTIMER AUX3 TMRA3EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRA3EN23 */ + CTIMER_AUX3_TMRA3EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX3_TMRA3EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX3_TMRA3EN23_Enum; + +/* ============================================ CTIMER AUX3 TMRA3POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX3_TMRA3POL23 */ + CTIMER_AUX3_TMRA3POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX3_TMRA3POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX3_TMRA3POL23_Enum; + +/* ============================================ CTIMER AUX3 TMRA3TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRA3TINV */ + CTIMER_AUX3_TMRA3TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX3_TMRA3TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX3_TMRA3TINV_Enum; + +/* =========================================== CTIMER AUX3 TMRA3NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX3_TMRA3NOSYNC */ + CTIMER_AUX3_TMRA3NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX3_TMRA3NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX3_TMRA3NOSYNC_Enum; + +/* ============================================= CTIMER AUX3 TMRA3TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRA3TRIG */ + CTIMER_AUX3_TMRA3TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX3_TMRA3TRIG_B3OUT = 1, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX3_TMRA3TRIG_B2OUT = 2, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX3_TMRA3TRIG_A2OUT = 3, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX3_TMRA3TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX3_TMRA3TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX3_TMRA3TRIG_A7OUT = 6, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */ + CTIMER_AUX3_TMRA3TRIG_B7OUT = 7, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */ + CTIMER_AUX3_TMRA3TRIG_B5OUT2 = 8, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ + CTIMER_AUX3_TMRA3TRIG_A5OUT2 = 9, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ + CTIMER_AUX3_TMRA3TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ + CTIMER_AUX3_TMRA3TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ + CTIMER_AUX3_TMRA3TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX3_TMRA3TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX3_TMRA3TRIG_B2OUT2DUAL = 14, /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge. */ + CTIMER_AUX3_TMRA3TRIG_A2OUT2DUAL = 15, /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge. */ +} CTIMER_AUX3_TMRA3TRIG_Enum; + +/* ========================================================= TMR4 ========================================================== */ +/* ======================================================== CMPRA4 ========================================================= */ +/* ======================================================== CMPRB4 ========================================================= */ +/* ========================================================= CTRL4 ========================================================= */ +/* ============================================= CTIMER CTRL4 CTLINK4 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_CTLINK4 */ + CTIMER_CTRL4_CTLINK4_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A4/B4 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL4_CTLINK4_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A4/B4 timers into a single 32-bit timer. */ +} CTIMER_CTRL4_CTLINK4_Enum; + +/* ============================================ CTIMER CTRL4 TMRB4POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4POL */ + CTIMER_CTRL4_TMRB4POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB4 pin is the same as the + timer output. */ + CTIMER_CTRL4_TMRB4POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB4 pin is the inverse of + the timer output. */ +} CTIMER_CTRL4_TMRB4POL_Enum; + +/* ============================================ CTIMER CTRL4 TMRB4CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4CLR */ + CTIMER_CTRL4_TMRB4CLR_RUN = 0, /*!< RUN : Allow counter/timer B4 to run */ + CTIMER_CTRL4_TMRB4CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B4 at 0x0000. */ +} CTIMER_CTRL4_TMRB4CLR_Enum; + +/* ============================================ CTIMER CTRL4 TMRB4IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4IE1 */ + CTIMER_CTRL4_TMRB4IE1_DIS = 0, /*!< DIS : Disable counter/timer B4 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL4_TMRB4IE1_EN = 1, /*!< EN : Enable counter/timer B4 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL4_TMRB4IE1_Enum; + +/* ============================================ CTIMER CTRL4 TMRB4IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4IE0 */ + CTIMER_CTRL4_TMRB4IE0_DIS = 0, /*!< DIS : Disable counter/timer B4 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL4_TMRB4IE0_EN = 1, /*!< EN : Enable counter/timer B4 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL4_TMRB4IE0_Enum; + +/* ============================================= CTIMER CTRL4 TMRB4FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4FN */ + CTIMER_CTRL4_TMRB4FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B4, stop. */ + CTIMER_CTRL4_TMRB4FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B4, restart. */ + CTIMER_CTRL4_TMRB4FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B4, assert, + count to CMPR1B4, deassert, stop. */ + CTIMER_CTRL4_TMRB4FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B4, assert, count + to CMPR1B4, deassert, restart. */ + CTIMER_CTRL4_TMRB4FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL4_TMRB4FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL4_TMRB4FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL4_TMRB4FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL4_TMRB4FN_Enum; + +/* ============================================ CTIMER CTRL4 TMRB4CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4CLK */ + CTIMER_CTRL4_TMRB4CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL4_TMRB4CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL4_TMRB4CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL4_TMRB4CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL4_TMRB4CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL4_TMRB4CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL4_TMRB4CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL4_TMRB4CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL4_TMRB4CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL4_TMRB4CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL4_TMRB4CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL4_TMRB4CLK_CTMRA4 = 20, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRA5 = 23, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB5 = 24, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL4_TMRB4CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL4_TMRB4CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL4_TMRB4CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL4_TMRB4CLK_Enum; + +/* ============================================= CTIMER CTRL4 TMRB4EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4EN */ + CTIMER_CTRL4_TMRB4EN_DIS = 0, /*!< DIS : Counter/Timer B4 Disable. */ + CTIMER_CTRL4_TMRB4EN_EN = 1, /*!< EN : Counter/Timer B4 Enable. */ +} CTIMER_CTRL4_TMRB4EN_Enum; + +/* ============================================ CTIMER CTRL4 TMRA4POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4POL */ + CTIMER_CTRL4_TMRA4POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA4 pin is the same as the + timer output. */ + CTIMER_CTRL4_TMRA4POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA4 pin is the inverse of + the timer output. */ +} CTIMER_CTRL4_TMRA4POL_Enum; + +/* ============================================ CTIMER CTRL4 TMRA4CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4CLR */ + CTIMER_CTRL4_TMRA4CLR_RUN = 0, /*!< RUN : Allow counter/timer A4 to run */ + CTIMER_CTRL4_TMRA4CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A4 at 0x0000. */ +} CTIMER_CTRL4_TMRA4CLR_Enum; + +/* ============================================ CTIMER CTRL4 TMRA4IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4IE1 */ + CTIMER_CTRL4_TMRA4IE1_DIS = 0, /*!< DIS : Disable counter/timer A4 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL4_TMRA4IE1_EN = 1, /*!< EN : Enable counter/timer A4 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL4_TMRA4IE1_Enum; + +/* ============================================= CTIMER CTRL4 TMRA4IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4IE0 */ + CTIMER_CTRL4_TMRA4IE0_DIS = 0, /*!< DIS : Disable counter/timer A4 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL4_TMRA4IE0_EN = 1, /*!< EN : Enable counter/timer A4 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL4_TMRA4IE0_Enum; + +/* ============================================== CTIMER CTRL4 TMRA4FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4FN */ + CTIMER_CTRL4_TMRA4FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A4, stop. */ + CTIMER_CTRL4_TMRA4FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A4, restart. */ + CTIMER_CTRL4_TMRA4FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A4, assert, + count to CMPR1A4, deassert, stop. */ + CTIMER_CTRL4_TMRA4FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A4, assert, count + to CMPR1A4, deassert, restart. */ + CTIMER_CTRL4_TMRA4FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL4_TMRA4FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL4_TMRA4FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL4_TMRA4FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL4_TMRA4FN_Enum; + +/* ============================================= CTIMER CTRL4 TMRA4CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4CLK */ + CTIMER_CTRL4_TMRA4CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL4_TMRA4CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL4_TMRA4CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL4_TMRA4CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL4_TMRA4CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL4_TMRA4CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL4_TMRA4CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL4_TMRA4CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL4_TMRA4CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL4_TMRA4CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL4_TMRA4CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4. (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL4_TMRA4CLK_CTMRB4 = 20, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRA5 = 23, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB5 = 24, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL4_TMRA4CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL4_TMRA4CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL4_TMRA4CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL4_TMRA4CLK_Enum; + +/* ============================================== CTIMER CTRL4 TMRA4EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4EN */ + CTIMER_CTRL4_TMRA4EN_DIS = 0, /*!< DIS : Counter/Timer A4 Disable. */ + CTIMER_CTRL4_TMRA4EN_EN = 1, /*!< EN : Counter/Timer A4 Enable. */ +} CTIMER_CTRL4_TMRA4EN_Enum; + +/* ======================================================= CMPRAUXA4 ======================================================= */ +/* ======================================================= CMPRAUXB4 ======================================================= */ +/* ========================================================= AUX4 ========================================================== */ +/* ============================================ CTIMER AUX4 TMRB4EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRB4EN23 */ + CTIMER_AUX4_TMRB4EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX4_TMRB4EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX4_TMRB4EN23_Enum; + +/* ============================================ CTIMER AUX4 TMRB4POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX4_TMRB4POL23 */ + CTIMER_AUX4_TMRB4POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX4_TMRB4POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX4_TMRB4POL23_Enum; + +/* ============================================ CTIMER AUX4 TMRB4TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRB4TINV */ + CTIMER_AUX4_TMRB4TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX4_TMRB4TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX4_TMRB4TINV_Enum; + +/* =========================================== CTIMER AUX4 TMRB4NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX4_TMRB4NOSYNC */ + CTIMER_AUX4_TMRB4NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX4_TMRB4NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX4_TMRB4NOSYNC_Enum; + +/* ============================================ CTIMER AUX4 TMRB4TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRB4TRIG */ + CTIMER_AUX4_TMRB4TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX4_TMRB4TRIG_A4OUT = 1, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX4_TMRB4TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX4_TMRB4TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX4_TMRB4TRIG_A7OUT = 4, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */ + CTIMER_AUX4_TMRB4TRIG_B7OUT = 5, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */ + CTIMER_AUX4_TMRB4TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX4_TMRB4TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX4_TMRB4TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX4_TMRB4TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX4_TMRB4TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ + CTIMER_AUX4_TMRB4TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ + CTIMER_AUX4_TMRB4TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX4_TMRB4TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX4_TMRB4TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ + CTIMER_AUX4_TMRB4TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ +} CTIMER_AUX4_TMRB4TRIG_Enum; + +/* ============================================ CTIMER AUX4 TMRA4EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRA4EN23 */ + CTIMER_AUX4_TMRA4EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX4_TMRA4EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX4_TMRA4EN23_Enum; + +/* ============================================ CTIMER AUX4 TMRA4POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX4_TMRA4POL23 */ + CTIMER_AUX4_TMRA4POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX4_TMRA4POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX4_TMRA4POL23_Enum; + +/* ============================================ CTIMER AUX4 TMRA4TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRA4TINV */ + CTIMER_AUX4_TMRA4TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX4_TMRA4TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX4_TMRA4TINV_Enum; + +/* =========================================== CTIMER AUX4 TMRA4NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX4_TMRA4NOSYNC */ + CTIMER_AUX4_TMRA4NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX4_TMRA4NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX4_TMRA4NOSYNC_Enum; + +/* ============================================= CTIMER AUX4 TMRA4TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRA4TRIG */ + CTIMER_AUX4_TMRA4TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX4_TMRA4TRIG_STIMER = 1, /*!< STIMER : Trigger source is STimer Interrupt. Only Active When + CTLINK==1 and TMRB4TRIG!=0. TMRB4TRIG selects an STIMER + interrupt */ + CTIMER_AUX4_TMRA4TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX4_TMRA4TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX4_TMRA4TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ + CTIMER_AUX4_TMRA4TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ + CTIMER_AUX4_TMRA4TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX4_TMRA4TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX4_TMRA4TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX4_TMRA4TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX4_TMRA4TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ + CTIMER_AUX4_TMRA4TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ + CTIMER_AUX4_TMRA4TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX4_TMRA4TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX4_TMRA4TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ + CTIMER_AUX4_TMRA4TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ +} CTIMER_AUX4_TMRA4TRIG_Enum; + +/* ========================================================= TMR5 ========================================================== */ +/* ======================================================== CMPRA5 ========================================================= */ +/* ======================================================== CMPRB5 ========================================================= */ +/* ========================================================= CTRL5 ========================================================= */ +/* ============================================= CTIMER CTRL5 CTLINK5 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_CTLINK5 */ + CTIMER_CTRL5_CTLINK5_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A5/B5 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL5_CTLINK5_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A5/B5 timers into a single 32-bit timer. */ +} CTIMER_CTRL5_CTLINK5_Enum; + +/* ============================================ CTIMER CTRL5 TMRB5POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5POL */ + CTIMER_CTRL5_TMRB5POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB5 pin is the same as the + timer output. */ + CTIMER_CTRL5_TMRB5POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB5 pin is the inverse of + the timer output. */ +} CTIMER_CTRL5_TMRB5POL_Enum; + +/* ============================================ CTIMER CTRL5 TMRB5CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5CLR */ + CTIMER_CTRL5_TMRB5CLR_RUN = 0, /*!< RUN : Allow counter/timer B5 to run */ + CTIMER_CTRL5_TMRB5CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B5 at 0x0000. */ +} CTIMER_CTRL5_TMRB5CLR_Enum; + +/* ============================================ CTIMER CTRL5 TMRB5IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5IE1 */ + CTIMER_CTRL5_TMRB5IE1_DIS = 0, /*!< DIS : Disable counter/timer B5 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL5_TMRB5IE1_EN = 1, /*!< EN : Enable counter/timer B5 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL5_TMRB5IE1_Enum; + +/* ============================================ CTIMER CTRL5 TMRB5IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5IE0 */ + CTIMER_CTRL5_TMRB5IE0_DIS = 0, /*!< DIS : Disable counter/timer B5 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL5_TMRB5IE0_EN = 1, /*!< EN : Enable counter/timer B5 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL5_TMRB5IE0_Enum; + +/* ============================================= CTIMER CTRL5 TMRB5FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5FN */ + CTIMER_CTRL5_TMRB5FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B5, stop. */ + CTIMER_CTRL5_TMRB5FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B5, restart. */ + CTIMER_CTRL5_TMRB5FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B5, assert, + count to CMPR1B5, deassert, stop. */ + CTIMER_CTRL5_TMRB5FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B5, assert, count + to CMPR1B5, deassert, restart. */ + CTIMER_CTRL5_TMRB5FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL5_TMRB5FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL5_TMRB5FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL5_TMRB5FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL5_TMRB5FN_Enum; + +/* ============================================ CTIMER CTRL5 TMRB5CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5CLK */ + CTIMER_CTRL5_TMRB5CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL5_TMRB5CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL5_TMRB5CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL5_TMRB5CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL5_TMRB5CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL5_TMRB5CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL5_TMRB5CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL5_TMRB5CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL5_TMRB5CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL5_TMRB5CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL5_TMRB5CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL5_TMRB5CLK_CTMRA5 = 20, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRA6 = 23, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB6 = 24, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL5_TMRB5CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL5_TMRB5CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL5_TMRB5CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL5_TMRB5CLK_Enum; + +/* ============================================= CTIMER CTRL5 TMRB5EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5EN */ + CTIMER_CTRL5_TMRB5EN_DIS = 0, /*!< DIS : Counter/Timer B5 Disable. */ + CTIMER_CTRL5_TMRB5EN_EN = 1, /*!< EN : Counter/Timer B5 Enable. */ +} CTIMER_CTRL5_TMRB5EN_Enum; + +/* ============================================ CTIMER CTRL5 TMRA5POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5POL */ + CTIMER_CTRL5_TMRA5POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA5 pin is the same as the + timer output. */ + CTIMER_CTRL5_TMRA5POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA5 pin is the inverse of + the timer output. */ +} CTIMER_CTRL5_TMRA5POL_Enum; + +/* ============================================ CTIMER CTRL5 TMRA5CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5CLR */ + CTIMER_CTRL5_TMRA5CLR_RUN = 0, /*!< RUN : Allow counter/timer A5 to run */ + CTIMER_CTRL5_TMRA5CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A5 at 0x0000. */ +} CTIMER_CTRL5_TMRA5CLR_Enum; + +/* ============================================ CTIMER CTRL5 TMRA5IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5IE1 */ + CTIMER_CTRL5_TMRA5IE1_DIS = 0, /*!< DIS : Disable counter/timer A5 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL5_TMRA5IE1_EN = 1, /*!< EN : Enable counter/timer A5 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL5_TMRA5IE1_Enum; + +/* ============================================= CTIMER CTRL5 TMRA5IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5IE0 */ + CTIMER_CTRL5_TMRA5IE0_DIS = 0, /*!< DIS : Disable counter/timer A5 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL5_TMRA5IE0_EN = 1, /*!< EN : Enable counter/timer A5 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL5_TMRA5IE0_Enum; + +/* ============================================== CTIMER CTRL5 TMRA5FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5FN */ + CTIMER_CTRL5_TMRA5FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A5, stop. */ + CTIMER_CTRL5_TMRA5FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A5, restart. */ + CTIMER_CTRL5_TMRA5FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A5, assert, + count to CMPR1A5, deassert, stop. */ + CTIMER_CTRL5_TMRA5FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A5, assert, count + to CMPR1A5, deassert, restart. */ + CTIMER_CTRL5_TMRA5FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL5_TMRA5FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL5_TMRA5FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL5_TMRA5FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL5_TMRA5FN_Enum; + +/* ============================================= CTIMER CTRL5 TMRA5CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5CLK */ + CTIMER_CTRL5_TMRA5CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL5_TMRA5CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL5_TMRA5CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL5_TMRA5CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL5_TMRA5CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL5_TMRA5CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL5_TMRA5CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL5_TMRA5CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL5_TMRA5CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL5_TMRA5CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL5_TMRA5CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL5_TMRA5CLK_CTMRB5 = 20, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRA6 = 23, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB6 = 24, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL5_TMRA5CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL5_TMRA5CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL5_TMRA5CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL5_TMRA5CLK_Enum; + +/* ============================================== CTIMER CTRL5 TMRA5EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5EN */ + CTIMER_CTRL5_TMRA5EN_DIS = 0, /*!< DIS : Counter/Timer A5 Disable. */ + CTIMER_CTRL5_TMRA5EN_EN = 1, /*!< EN : Counter/Timer A5 Enable. */ +} CTIMER_CTRL5_TMRA5EN_Enum; + +/* ======================================================= CMPRAUXA5 ======================================================= */ +/* ======================================================= CMPRAUXB5 ======================================================= */ +/* ========================================================= AUX5 ========================================================== */ +/* ============================================ CTIMER AUX5 TMRB5EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRB5EN23 */ + CTIMER_AUX5_TMRB5EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX5_TMRB5EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX5_TMRB5EN23_Enum; + +/* ============================================ CTIMER AUX5 TMRB5POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX5_TMRB5POL23 */ + CTIMER_AUX5_TMRB5POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX5_TMRB5POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX5_TMRB5POL23_Enum; + +/* ============================================ CTIMER AUX5 TMRB5TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRB5TINV */ + CTIMER_AUX5_TMRB5TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX5_TMRB5TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX5_TMRB5TINV_Enum; + +/* =========================================== CTIMER AUX5 TMRB5NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX5_TMRB5NOSYNC */ + CTIMER_AUX5_TMRB5NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX5_TMRB5NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX5_TMRB5NOSYNC_Enum; + +/* ============================================ CTIMER AUX5 TMRB5TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRB5TRIG */ + CTIMER_AUX5_TMRB5TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX5_TMRB5TRIG_A5OUT = 1, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ + CTIMER_AUX5_TMRB5TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX5_TMRB5TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX5_TMRB5TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ + CTIMER_AUX5_TMRB5TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ + CTIMER_AUX5_TMRB5TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX5_TMRB5TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX5_TMRB5TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX5_TMRB5TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX5_TMRB5TRIG_A0OUT2 = 10, /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2. */ + CTIMER_AUX5_TMRB5TRIG_B0OUT2 = 11, /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2. */ + CTIMER_AUX5_TMRB5TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX5_TMRB5TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX5_TMRB5TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX5_TMRB5TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX5_TMRB5TRIG_Enum; + +/* ============================================ CTIMER AUX5 TMRA5EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRA5EN23 */ + CTIMER_AUX5_TMRA5EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX5_TMRA5EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX5_TMRA5EN23_Enum; + +/* ============================================ CTIMER AUX5 TMRA5POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX5_TMRA5POL23 */ + CTIMER_AUX5_TMRA5POL23_NORMAL = 0, /*!< NORMAL : Upper output normal polarity */ + CTIMER_AUX5_TMRA5POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX5_TMRA5POL23_Enum; + +/* ============================================ CTIMER AUX5 TMRA5TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRA5TINV */ + CTIMER_AUX5_TMRA5TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX5_TMRA5TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX5_TMRA5TINV_Enum; + +/* =========================================== CTIMER AUX5 TMRA5NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX5_TMRA5NOSYNC */ + CTIMER_AUX5_TMRA5NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX5_TMRA5NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX5_TMRA5NOSYNC_Enum; + +/* ============================================= CTIMER AUX5 TMRA5TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRA5TRIG */ + CTIMER_AUX5_TMRA5TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX5_TMRA5TRIG_STIMER = 1, /*!< STIMER : Trigger source is STimer Interrupt. Only Active When + CTLINK==1 and TMRB5TRIG!=0. TMRB5TRIG selects an STIMER + interrupt */ + CTIMER_AUX5_TMRA5TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX5_TMRA5TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX5_TMRA5TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX5_TMRA5TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX5_TMRA5TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX5_TMRA5TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX5_TMRA5TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX5_TMRA5TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX5_TMRA5TRIG_A0OUT2 = 10, /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2. */ + CTIMER_AUX5_TMRA5TRIG_B0OUT2 = 11, /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2. */ + CTIMER_AUX5_TMRA5TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX5_TMRA5TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX5_TMRA5TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX5_TMRA5TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX5_TMRA5TRIG_Enum; + +/* ========================================================= TMR6 ========================================================== */ +/* ======================================================== CMPRA6 ========================================================= */ +/* ======================================================== CMPRB6 ========================================================= */ +/* ========================================================= CTRL6 ========================================================= */ +/* ============================================= CTIMER CTRL6 CTLINK6 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_CTLINK6 */ + CTIMER_CTRL6_CTLINK6_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A6/B6 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL6_CTLINK6_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A6/B6 timers into a single 32-bit timer. */ +} CTIMER_CTRL6_CTLINK6_Enum; + +/* ============================================ CTIMER CTRL6 TMRB6POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6POL */ + CTIMER_CTRL6_TMRB6POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB6 pin is the same as the + timer output. */ + CTIMER_CTRL6_TMRB6POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB6 pin is the inverse of + the timer output. */ +} CTIMER_CTRL6_TMRB6POL_Enum; + +/* ============================================ CTIMER CTRL6 TMRB6CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6CLR */ + CTIMER_CTRL6_TMRB6CLR_RUN = 0, /*!< RUN : Allow counter/timer B6 to run */ + CTIMER_CTRL6_TMRB6CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B6 at 0x0000. */ +} CTIMER_CTRL6_TMRB6CLR_Enum; + +/* ============================================ CTIMER CTRL6 TMRB6IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6IE1 */ + CTIMER_CTRL6_TMRB6IE1_DIS = 0, /*!< DIS : Disable counter/timer B6 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL6_TMRB6IE1_EN = 1, /*!< EN : Enable counter/timer B6 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL6_TMRB6IE1_Enum; + +/* ============================================ CTIMER CTRL6 TMRB6IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6IE0 */ + CTIMER_CTRL6_TMRB6IE0_DIS = 0, /*!< DIS : Disable counter/timer B6 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL6_TMRB6IE0_EN = 1, /*!< EN : Enable counter/timer B6 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL6_TMRB6IE0_Enum; + +/* ============================================= CTIMER CTRL6 TMRB6FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6FN */ + CTIMER_CTRL6_TMRB6FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B6, stop. */ + CTIMER_CTRL6_TMRB6FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B6, restart. */ + CTIMER_CTRL6_TMRB6FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B6, assert, + count to CMPR1B6, deassert, stop. */ + CTIMER_CTRL6_TMRB6FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B6, assert, count + to CMPR1B6, deassert, restart. */ + CTIMER_CTRL6_TMRB6FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL6_TMRB6FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL6_TMRB6FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL6_TMRB6FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL6_TMRB6FN_Enum; + +/* ============================================ CTIMER CTRL6 TMRB6CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6CLK */ + CTIMER_CTRL6_TMRB6CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL6_TMRB6CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL6_TMRB6CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL6_TMRB6CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL6_TMRB6CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL6_TMRB6CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL6_TMRB6CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL6_TMRB6CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL6_TMRB6CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL6_TMRB6CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL6_TMRB6CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL6_TMRB6CLK_CTMRA6 = 20, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRA3 = 21, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB3 = 22, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRA7 = 23, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB7 = 24, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB2 = 27, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL6_TMRB6CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL6_TMRB6CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL6_TMRB6CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL6_TMRB6CLK_Enum; + +/* ============================================= CTIMER CTRL6 TMRB6EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6EN */ + CTIMER_CTRL6_TMRB6EN_DIS = 0, /*!< DIS : Counter/Timer B6 Disable. */ + CTIMER_CTRL6_TMRB6EN_EN = 1, /*!< EN : Counter/Timer B6 Enable. */ +} CTIMER_CTRL6_TMRB6EN_Enum; + +/* ============================================ CTIMER CTRL6 TMRA6POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6POL */ + CTIMER_CTRL6_TMRA6POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA6 pin is the same as the + timer output. */ + CTIMER_CTRL6_TMRA6POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA6 pin is the inverse of + the timer output. */ +} CTIMER_CTRL6_TMRA6POL_Enum; + +/* ============================================ CTIMER CTRL6 TMRA6CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6CLR */ + CTIMER_CTRL6_TMRA6CLR_RUN = 0, /*!< RUN : Allow counter/timer A6 to run */ + CTIMER_CTRL6_TMRA6CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A6 at 0x0000. */ +} CTIMER_CTRL6_TMRA6CLR_Enum; + +/* ============================================ CTIMER CTRL6 TMRA6IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6IE1 */ + CTIMER_CTRL6_TMRA6IE1_DIS = 0, /*!< DIS : Disable counter/timer A6 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL6_TMRA6IE1_EN = 1, /*!< EN : Enable counter/timer A6 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL6_TMRA6IE1_Enum; + +/* ============================================= CTIMER CTRL6 TMRA6IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6IE0 */ + CTIMER_CTRL6_TMRA6IE0_DIS = 0, /*!< DIS : Disable counter/timer A6 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL6_TMRA6IE0_EN = 1, /*!< EN : Enable counter/timer A6 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL6_TMRA6IE0_Enum; + +/* ============================================== CTIMER CTRL6 TMRA6FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6FN */ + CTIMER_CTRL6_TMRA6FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A6, stop. */ + CTIMER_CTRL6_TMRA6FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A6, restart. */ + CTIMER_CTRL6_TMRA6FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A6, assert, + count to CMPR1A6, deassert, stop. */ + CTIMER_CTRL6_TMRA6FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A6, assert, count + to CMPR1A6, deassert, restart. */ + CTIMER_CTRL6_TMRA6FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL6_TMRA6FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL6_TMRA6FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL6_TMRA6FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL6_TMRA6FN_Enum; + +/* ============================================= CTIMER CTRL6 TMRA6CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6CLK */ + CTIMER_CTRL6_TMRA6CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL6_TMRA6CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL6_TMRA6CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL6_TMRA6CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL6_TMRA6CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL6_TMRA6CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL6_TMRA6CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL6_TMRA6CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL6_TMRA6CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL6_TMRA6CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL6_TMRA6CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL6_TMRA6CLK_CTMRB6 = 20, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRA3 = 21, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB3 = 22, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRA7 = 23, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB7 = 24, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB2 = 27, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL6_TMRA6CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL6_TMRA6CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL6_TMRA6CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL6_TMRA6CLK_Enum; + +/* ============================================== CTIMER CTRL6 TMRA6EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6EN */ + CTIMER_CTRL6_TMRA6EN_DIS = 0, /*!< DIS : Counter/Timer A6 Disable. */ + CTIMER_CTRL6_TMRA6EN_EN = 1, /*!< EN : Counter/Timer A6 Enable. */ +} CTIMER_CTRL6_TMRA6EN_Enum; + +/* ======================================================= CMPRAUXA6 ======================================================= */ +/* ======================================================= CMPRAUXB6 ======================================================= */ +/* ========================================================= AUX6 ========================================================== */ +/* ============================================ CTIMER AUX6 TMRB6EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRB6EN23 */ + CTIMER_AUX6_TMRB6EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX6_TMRB6EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX6_TMRB6EN23_Enum; + +/* ============================================ CTIMER AUX6 TMRB6POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX6_TMRB6POL23 */ + CTIMER_AUX6_TMRB6POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX6_TMRB6POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX6_TMRB6POL23_Enum; + +/* ============================================ CTIMER AUX6 TMRB6TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRB6TINV */ + CTIMER_AUX6_TMRB6TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX6_TMRB6TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX6_TMRB6TINV_Enum; + +/* =========================================== CTIMER AUX6 TMRB6NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX6_TMRB6NOSYNC */ + CTIMER_AUX6_TMRB6NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX6_TMRB6NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX6_TMRB6NOSYNC_Enum; + +/* ============================================ CTIMER AUX6 TMRB6TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRB6TRIG */ + CTIMER_AUX6_TMRB6TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX6_TMRB6TRIG_A6OUT = 1, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ + CTIMER_AUX6_TMRB6TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX6_TMRB6TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX6_TMRB6TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX6_TMRB6TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX6_TMRB6TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX6_TMRB6TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX6_TMRB6TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX6_TMRB6TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX6_TMRB6TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX6_TMRB6TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */ + CTIMER_AUX6_TMRB6TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX6_TMRB6TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX6_TMRB6TRIG_B0OUT2DUAL = 14, /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge. */ + CTIMER_AUX6_TMRB6TRIG_A0OUT2DUAL = 15, /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge. */ +} CTIMER_AUX6_TMRB6TRIG_Enum; + +/* ============================================ CTIMER AUX6 TMRA6EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRA6EN23 */ + CTIMER_AUX6_TMRA6EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX6_TMRA6EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX6_TMRA6EN23_Enum; + +/* ============================================ CTIMER AUX6 TMRA6POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX6_TMRA6POL23 */ + CTIMER_AUX6_TMRA6POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX6_TMRA6POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX6_TMRA6POL23_Enum; + +/* ============================================ CTIMER AUX6 TMRA6TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRA6TINV */ + CTIMER_AUX6_TMRA6TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX6_TMRA6TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX6_TMRA6TINV_Enum; + +/* =========================================== CTIMER AUX6 TMRA6NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX6_TMRA6NOSYNC */ + CTIMER_AUX6_TMRA6NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX6_TMRA6NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX6_TMRA6NOSYNC_Enum; + +/* ============================================= CTIMER AUX6 TMRA6TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRA6TRIG */ + CTIMER_AUX6_TMRA6TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX6_TMRA6TRIG_B6OUT = 1, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ + CTIMER_AUX6_TMRA6TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX6_TMRA6TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX6_TMRA6TRIG_A5OUT = 4, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ + CTIMER_AUX6_TMRA6TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ + CTIMER_AUX6_TMRA6TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX6_TMRA6TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX6_TMRA6TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX6_TMRA6TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX6_TMRA6TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX6_TMRA6TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERBb OUT2. */ + CTIMER_AUX6_TMRA6TRIG_A5OUT2DUAL = 12, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ + CTIMER_AUX6_TMRA6TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX6_TMRA6TRIG_B0OUT2DUAL = 14, /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge. */ + CTIMER_AUX6_TMRA6TRIG_A0OUT2DUAL = 15, /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge. */ +} CTIMER_AUX6_TMRA6TRIG_Enum; + +/* ========================================================= TMR7 ========================================================== */ +/* ======================================================== CMPRA7 ========================================================= */ +/* ======================================================== CMPRB7 ========================================================= */ +/* ========================================================= CTRL7 ========================================================= */ +/* ============================================= CTIMER CTRL7 CTLINK7 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_CTLINK7 */ + CTIMER_CTRL7_CTLINK7_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A7/B7 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL7_CTLINK7_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A7/B7 timers into a single 32-bit timer. */ +} CTIMER_CTRL7_CTLINK7_Enum; + +/* ============================================ CTIMER CTRL7 TMRB7POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7POL */ + CTIMER_CTRL7_TMRB7POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB7 pin is the same as the + timer output. */ + CTIMER_CTRL7_TMRB7POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB7 pin is the inverse of + the timer output. */ +} CTIMER_CTRL7_TMRB7POL_Enum; + +/* ============================================ CTIMER CTRL7 TMRB7CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7CLR */ + CTIMER_CTRL7_TMRB7CLR_RUN = 0, /*!< RUN : Allow counter/timer B7 to run */ + CTIMER_CTRL7_TMRB7CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B7 at 0x0000. */ +} CTIMER_CTRL7_TMRB7CLR_Enum; + +/* ============================================ CTIMER CTRL7 TMRB7IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7IE1 */ + CTIMER_CTRL7_TMRB7IE1_DIS = 0, /*!< DIS : Disable counter/timer B7 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL7_TMRB7IE1_EN = 1, /*!< EN : Enable counter/timer B7 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL7_TMRB7IE1_Enum; + +/* ============================================ CTIMER CTRL7 TMRB7IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7IE0 */ + CTIMER_CTRL7_TMRB7IE0_DIS = 0, /*!< DIS : Disable counter/timer B7 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL7_TMRB7IE0_EN = 1, /*!< EN : Enable counter/timer B7 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL7_TMRB7IE0_Enum; + +/* ============================================= CTIMER CTRL7 TMRB7FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7FN */ + CTIMER_CTRL7_TMRB7FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B7, stop. */ + CTIMER_CTRL7_TMRB7FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B7, restart. */ + CTIMER_CTRL7_TMRB7FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B7, assert, + count to CMPR1B7, deassert, stop. */ + CTIMER_CTRL7_TMRB7FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B7, assert, count + to CMPR1B7, deassert, restart. */ + CTIMER_CTRL7_TMRB7FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL7_TMRB7FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL7_TMRB7FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL7_TMRB7FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL7_TMRB7FN_Enum; + +/* ============================================ CTIMER CTRL7 TMRB7CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7CLK */ + CTIMER_CTRL7_TMRB7CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL7_TMRB7CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL7_TMRB7CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL7_TMRB7CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL7_TMRB7CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL7_TMRB7CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL7_TMRB7CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL7_TMRB7CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL7_TMRB7CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL7_TMRB7CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL7_TMRB7CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL7_TMRB7CLK_CTMRA7 = 20, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRA0 = 23, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB0 = 24, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB3 = 26, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB4 = 27, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB5 = 28, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL7_TMRB7CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL7_TMRB7CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL7_TMRB7CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL7_TMRB7CLK_Enum; + +/* ============================================= CTIMER CTRL7 TMRB7EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7EN */ + CTIMER_CTRL7_TMRB7EN_DIS = 0, /*!< DIS : Counter/Timer B7 Disable. */ + CTIMER_CTRL7_TMRB7EN_EN = 1, /*!< EN : Counter/Timer B7 Enable. */ +} CTIMER_CTRL7_TMRB7EN_Enum; + +/* ============================================ CTIMER CTRL7 TMRA7POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7POL */ + CTIMER_CTRL7_TMRA7POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA7 pin is the same as the + timer output. */ + CTIMER_CTRL7_TMRA7POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA7 pin is the inverse of + the timer output. */ +} CTIMER_CTRL7_TMRA7POL_Enum; + +/* ============================================ CTIMER CTRL7 TMRA7CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7CLR */ + CTIMER_CTRL7_TMRA7CLR_RUN = 0, /*!< RUN : Allow counter/timer A7 to run */ + CTIMER_CTRL7_TMRA7CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A7 at 0x0000. */ +} CTIMER_CTRL7_TMRA7CLR_Enum; + +/* ============================================ CTIMER CTRL7 TMRA7IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7IE1 */ + CTIMER_CTRL7_TMRA7IE1_DIS = 0, /*!< DIS : Disable counter/timer A7 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL7_TMRA7IE1_EN = 1, /*!< EN : Enable counter/timer A7 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL7_TMRA7IE1_Enum; + +/* ============================================= CTIMER CTRL7 TMRA7IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7IE0 */ + CTIMER_CTRL7_TMRA7IE0_DIS = 0, /*!< DIS : Disable counter/timer A7 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL7_TMRA7IE0_EN = 1, /*!< EN : Enable counter/timer A7 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL7_TMRA7IE0_Enum; + +/* ============================================== CTIMER CTRL7 TMRA7FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7FN */ + CTIMER_CTRL7_TMRA7FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A7, stop. */ + CTIMER_CTRL7_TMRA7FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A7, restart. */ + CTIMER_CTRL7_TMRA7FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A7, assert, + count to CMPR1A7, deassert, stop. */ + CTIMER_CTRL7_TMRA7FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A7, assert, count + to CMPR1A7, deassert, restart. */ + CTIMER_CTRL7_TMRA7FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL7_TMRA7FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL7_TMRA7FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL7_TMRA7FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL7_TMRA7FN_Enum; + +/* ============================================= CTIMER CTRL7 TMRA7CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7CLK */ + CTIMER_CTRL7_TMRA7CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL7_TMRA7CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL7_TMRA7CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL7_TMRA7CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL7_TMRA7CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL7_TMRA7CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL7_TMRA7CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL7_TMRA7CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL7_TMRA7CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL7_TMRA7CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL7_TMRA7CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL7_TMRA7CLK_CTMRB7 = 20, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRA0 = 23, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB0 = 24, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB3 = 26, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB4 = 27, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB5 = 28, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL7_TMRA7CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL7_TMRA7CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL7_TMRA7CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL7_TMRA7CLK_Enum; + +/* ============================================== CTIMER CTRL7 TMRA7EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7EN */ + CTIMER_CTRL7_TMRA7EN_DIS = 0, /*!< DIS : Counter/Timer A7 Disable. */ + CTIMER_CTRL7_TMRA7EN_EN = 1, /*!< EN : Counter/Timer A7 Enable. */ +} CTIMER_CTRL7_TMRA7EN_Enum; + +/* ======================================================= CMPRAUXA7 ======================================================= */ +/* ======================================================= CMPRAUXB7 ======================================================= */ +/* ========================================================= AUX7 ========================================================== */ +/* ============================================ CTIMER AUX7 TMRB7EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRB7EN23 */ + CTIMER_AUX7_TMRB7EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX7_TMRB7EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX7_TMRB7EN23_Enum; + +/* ============================================ CTIMER AUX7 TMRB7POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX7_TMRB7POL23 */ + CTIMER_AUX7_TMRB7POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX7_TMRB7POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX7_TMRB7POL23_Enum; + +/* ============================================ CTIMER AUX7 TMRB7TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRB7TINV */ + CTIMER_AUX7_TMRB7TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX7_TMRB7TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX7_TMRB7TINV_Enum; + +/* =========================================== CTIMER AUX7 TMRB7NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX7_TMRB7NOSYNC */ + CTIMER_AUX7_TMRB7NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX7_TMRB7NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX7_TMRB7NOSYNC_Enum; + +/* ============================================ CTIMER AUX7 TMRB7TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRB7TRIG */ + CTIMER_AUX7_TMRB7TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX7_TMRB7TRIG_A7OUT = 1, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */ + CTIMER_AUX7_TMRB7TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX7_TMRB7TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX7_TMRB7TRIG_A5OUT = 4, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ + CTIMER_AUX7_TMRB7TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ + CTIMER_AUX7_TMRB7TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX7_TMRB7TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX7_TMRB7TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX7_TMRB7TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX7_TMRB7TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX7_TMRB7TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */ + CTIMER_AUX7_TMRB7TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX7_TMRB7TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX7_TMRB7TRIG_B1OUT2DUAL = 14, /*!< B1OUT2DUAL : Trigger source is CTIMERB1 OUT2, dual edge. */ + CTIMER_AUX7_TMRB7TRIG_A1OUT2DUAL = 15, /*!< A1OUT2DUAL : Trigger source is CTIMERA1 OUT2, dual edge. */ +} CTIMER_AUX7_TMRB7TRIG_Enum; + +/* ============================================ CTIMER AUX7 TMRA7EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRA7EN23 */ + CTIMER_AUX7_TMRA7EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX7_TMRA7EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX7_TMRA7EN23_Enum; + +/* ============================================ CTIMER AUX7 TMRA7POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX7_TMRA7POL23 */ + CTIMER_AUX7_TMRA7POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX7_TMRA7POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX7_TMRA7POL23_Enum; + +/* ============================================ CTIMER AUX7 TMRA7TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRA7TINV */ + CTIMER_AUX7_TMRA7TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX7_TMRA7TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX7_TMRA7TINV_Enum; + +/* =========================================== CTIMER AUX7 TMRA7NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX7_TMRA7NOSYNC */ + CTIMER_AUX7_TMRA7NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX7_TMRA7NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX7_TMRA7NOSYNC_Enum; + +/* ============================================= CTIMER AUX7 TMRA7TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRA7TRIG */ + CTIMER_AUX7_TMRA7TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX7_TMRA7TRIG_B7OUT = 1, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */ + CTIMER_AUX7_TMRA7TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX7_TMRA7TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX7_TMRA7TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX7_TMRA7TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX7_TMRA7TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX7_TMRA7TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX7_TMRA7TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX7_TMRA7TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX7_TMRA7TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX7_TMRA7TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */ + CTIMER_AUX7_TMRA7TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX7_TMRA7TRIG_A5OUT2DUAL = 13, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ + CTIMER_AUX7_TMRA7TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX7_TMRA7TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX7_TMRA7TRIG_Enum; + +/* ======================================================== GLOBEN ========================================================= */ +/* ============================================== CTIMER GLOBEN ENB7 [15..15] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB7 */ + CTIMER_GLOBEN_ENB7_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB7_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB7_Enum; + +/* ============================================== CTIMER GLOBEN ENA7 [14..14] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA7 */ + CTIMER_GLOBEN_ENA7_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA7_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA7_Enum; + +/* ============================================== CTIMER GLOBEN ENB6 [13..13] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB6 */ + CTIMER_GLOBEN_ENB6_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB6_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB6_Enum; + +/* ============================================== CTIMER GLOBEN ENA6 [12..12] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA6 */ + CTIMER_GLOBEN_ENA6_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA6_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA6_Enum; + +/* ============================================== CTIMER GLOBEN ENB5 [11..11] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB5 */ + CTIMER_GLOBEN_ENB5_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB5_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB5_Enum; + +/* ============================================== CTIMER GLOBEN ENA5 [10..10] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA5 */ + CTIMER_GLOBEN_ENA5_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA5_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA5_Enum; + +/* =============================================== CTIMER GLOBEN ENB4 [9..9] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB4 */ + CTIMER_GLOBEN_ENB4_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB4_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB4_Enum; + +/* =============================================== CTIMER GLOBEN ENA4 [8..8] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA4 */ + CTIMER_GLOBEN_ENA4_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA4_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA4_Enum; + +/* =============================================== CTIMER GLOBEN ENB3 [7..7] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB3 */ + CTIMER_GLOBEN_ENB3_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB3_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB3_Enum; + +/* =============================================== CTIMER GLOBEN ENA3 [6..6] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA3 */ + CTIMER_GLOBEN_ENA3_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA3_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA3_Enum; + +/* =============================================== CTIMER GLOBEN ENB2 [5..5] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB2 */ + CTIMER_GLOBEN_ENB2_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB2_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB2_Enum; + +/* =============================================== CTIMER GLOBEN ENA2 [4..4] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA2 */ + CTIMER_GLOBEN_ENA2_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA2_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA2_Enum; + +/* =============================================== CTIMER GLOBEN ENB1 [3..3] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB1 */ + CTIMER_GLOBEN_ENB1_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB1_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB1_Enum; + +/* =============================================== CTIMER GLOBEN ENA1 [2..2] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA1 */ + CTIMER_GLOBEN_ENA1_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA1_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA1_Enum; + +/* =============================================== CTIMER GLOBEN ENB0 [1..1] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB0 */ + CTIMER_GLOBEN_ENB0_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB0_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB0_Enum; + +/* =============================================== CTIMER GLOBEN ENA0 [0..0] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA0 */ + CTIMER_GLOBEN_ENA0_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA0_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA0_Enum; + +/* ======================================================== OUTCFG0 ======================================================== */ +/* ============================================= CTIMER OUTCFG0 CFG9 [28..30] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG9 */ + CTIMER_OUTCFG0_CFG9_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG9_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG9_B0OUT = 5, /*!< B0OUT : Output is B0OUT. */ + CTIMER_OUTCFG0_CFG9_A4OUT = 4, /*!< A4OUT : Output is A4OUT. */ + CTIMER_OUTCFG0_CFG9_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */ + CTIMER_OUTCFG0_CFG9_A2OUT2 = 2, /*!< A2OUT2 : Output is A2OUT2 */ + CTIMER_OUTCFG0_CFG9_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG9_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG9_Enum; + +/* ============================================= CTIMER OUTCFG0 CFG8 [25..27] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG8 */ + CTIMER_OUTCFG0_CFG8_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG8_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG8_B6OUT = 5, /*!< B6OUT : Output is B6OUT. */ + CTIMER_OUTCFG0_CFG8_A4OUT2 = 4, /*!< A4OUT2 : Output is A4OUT2. */ + CTIMER_OUTCFG0_CFG8_A3OUT2 = 3, /*!< A3OUT2 : Output is A3OUT. */ + CTIMER_OUTCFG0_CFG8_A2OUT = 2, /*!< A2OUT : Output is A2OUT */ + CTIMER_OUTCFG0_CFG8_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG8_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG8_Enum; + +/* ============================================= CTIMER OUTCFG0 CFG7 [22..24] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG7 */ + CTIMER_OUTCFG0_CFG7_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG7_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG7_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG0_CFG7_B5OUT = 4, /*!< B5OUT : Output is B5OUT. */ + CTIMER_OUTCFG0_CFG7_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */ + CTIMER_OUTCFG0_CFG7_B1OUT2 = 2, /*!< B1OUT2 : Output is B1OUT2 */ + CTIMER_OUTCFG0_CFG7_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG7_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG7_Enum; + +/* ============================================= CTIMER OUTCFG0 CFG6 [19..21] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG6 */ + CTIMER_OUTCFG0_CFG6_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG6_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG6_B7OUT = 5, /*!< B7OUT : Output is B7OUT. */ + CTIMER_OUTCFG0_CFG6_B5OUT2 = 4, /*!< B5OUT2 : Output is B5OUT2. */ + CTIMER_OUTCFG0_CFG6_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG0_CFG6_B1OUT = 2, /*!< B1OUT : Output is B1OUT */ + CTIMER_OUTCFG0_CFG6_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG6_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG6_Enum; + +/* ============================================= CTIMER OUTCFG0 CFG5 [16..18] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG5 */ + CTIMER_OUTCFG0_CFG5_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG5_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG5_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG0_CFG5_B6OUT = 4, /*!< B6OUT : Output is A5OUT. */ + CTIMER_OUTCFG0_CFG5_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG0_CFG5_A1OUT2 = 2, /*!< A1OUT2 : Output is A1OUT2 */ + CTIMER_OUTCFG0_CFG5_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG5_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG5_Enum; + +/* ============================================= CTIMER OUTCFG0 CFG4 [12..14] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG4 */ + CTIMER_OUTCFG0_CFG4_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG4_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG4_B5OUT = 5, /*!< B5OUT : Output is B5OUT. */ + CTIMER_OUTCFG0_CFG4_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */ + CTIMER_OUTCFG0_CFG4_A2OUT2 = 3, /*!< A2OUT2 : Output is A2OUT2. */ + CTIMER_OUTCFG0_CFG4_A1OUT = 2, /*!< A1OUT : Output is A1OUT */ + CTIMER_OUTCFG0_CFG4_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG4_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG4_Enum; + +/* ============================================== CTIMER OUTCFG0 CFG3 [9..11] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG3 */ + CTIMER_OUTCFG0_CFG3_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG3_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG3_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG0_CFG3_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG0_CFG3_B0OUT = 3, /*!< B0OUT : Output is B0OUT. */ + CTIMER_OUTCFG0_CFG3_B0OUT2 = 2, /*!< B0OUT2 : Output is B0OUT2 */ + CTIMER_OUTCFG0_CFG3_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG3_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG3_Enum; + +/* ============================================== CTIMER OUTCFG0 CFG2 [6..8] =============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG2 */ + CTIMER_OUTCFG0_CFG2_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG2_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG2_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG0_CFG2_B6OUT2 = 4, /*!< B6OUT2 : Output is B6OUT2. */ + CTIMER_OUTCFG0_CFG2_B1OUT2 = 3, /*!< B1OUT2 : Output is B1OUT2. */ + CTIMER_OUTCFG0_CFG2_B0OUT = 2, /*!< B0OUT : Output is B0OUT */ + CTIMER_OUTCFG0_CFG2_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG2_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG2_Enum; + +/* ============================================== CTIMER OUTCFG0 CFG1 [3..5] =============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG1 */ + CTIMER_OUTCFG0_CFG1_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG1_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG1_B7OUT2 = 5, /*!< B7OUT2 : Output is B7OUT2. */ + CTIMER_OUTCFG0_CFG1_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */ + CTIMER_OUTCFG0_CFG1_A0OUT = 3, /*!< A0OUT : Output is A0OUT. */ + CTIMER_OUTCFG0_CFG1_A0OUT2 = 2, /*!< A0OUT2 : Output is A0OUT2 */ + CTIMER_OUTCFG0_CFG1_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG1_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG1_Enum; + +/* ============================================== CTIMER OUTCFG0 CFG0 [0..2] =============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG0 */ + CTIMER_OUTCFG0_CFG0_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG0_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG0_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG0_CFG0_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */ + CTIMER_OUTCFG0_CFG0_B2OUT2 = 3, /*!< B2OUT2 : Output is B2OUT2. */ + CTIMER_OUTCFG0_CFG0_A0OUT = 2, /*!< A0OUT : Output is A0OUT */ + CTIMER_OUTCFG0_CFG0_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG0_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG0_Enum; + +/* ======================================================== OUTCFG1 ======================================================== */ +/* ============================================= CTIMER OUTCFG1 CFG19 [28..30] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG19 */ + CTIMER_OUTCFG1_CFG19_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG19_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG19_B1OUT2 = 5, /*!< B1OUT2 : Output is B1OUT2. */ + CTIMER_OUTCFG1_CFG19_B4OUT = 4, /*!< B4OUT : Output is B4OUT. */ + CTIMER_OUTCFG1_CFG19_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */ + CTIMER_OUTCFG1_CFG19_B4OUT2 = 2, /*!< B4OUT2 : Output is B4OUT2 */ + CTIMER_OUTCFG1_CFG19_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG19_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG19_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG18 [25..27] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG18 */ + CTIMER_OUTCFG1_CFG18_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG18_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG18_A3OUT2 = 5, /*!< A3OUT2 : Output is A3OUT2. */ + CTIMER_OUTCFG1_CFG18_A0OUT = 4, /*!< A0OUT : Output is A0OUT. */ + CTIMER_OUTCFG1_CFG18_B0OUT = 3, /*!< B0OUT : Output is B0OUT. */ + CTIMER_OUTCFG1_CFG18_B4OUT = 2, /*!< B4OUT : Output is B4OUT */ + CTIMER_OUTCFG1_CFG18_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG18_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG18_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG17 [22..24] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG17 */ + CTIMER_OUTCFG1_CFG17_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG17_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG17_A1OUT2 = 5, /*!< A1OUT2 : Output is A1OUT2. */ + CTIMER_OUTCFG1_CFG17_A4OUT = 4, /*!< A4OUT : Output is A4OUT. */ + CTIMER_OUTCFG1_CFG17_B7OUT = 3, /*!< B7OUT : Output is B7OUT. */ + CTIMER_OUTCFG1_CFG17_A4OUT2 = 2, /*!< A4OUT2 : Output is A4OUT2 */ + CTIMER_OUTCFG1_CFG17_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG17_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG17_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG16 [19..21] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG16 */ + CTIMER_OUTCFG1_CFG16_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG16_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG16_B3OUT2 = 5, /*!< B3OUT2 : Output is B3OUT2. */ + CTIMER_OUTCFG1_CFG16_A0OUT2 = 4, /*!< A0OUT2 : Output is A0OUT2. */ + CTIMER_OUTCFG1_CFG16_A0OUT = 3, /*!< A0OUT : Output is A0OUT. */ + CTIMER_OUTCFG1_CFG16_A4OUT = 2, /*!< A4OUT : Output is A4OUT */ + CTIMER_OUTCFG1_CFG16_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG16_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG16_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG15 [16..18] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG15 */ + CTIMER_OUTCFG1_CFG15_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG15_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG15_A4OUT2 = 5, /*!< A4OUT2 : Output is A4OUT2. */ + CTIMER_OUTCFG1_CFG15_A7OUT = 4, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG1_CFG15_B3OUT = 3, /*!< B3OUT : Output is B3OUT. */ + CTIMER_OUTCFG1_CFG15_B3OUT2 = 2, /*!< B3OUT2 : Output is B3OUT2 */ + CTIMER_OUTCFG1_CFG15_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG15_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG15_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG14 [12..14] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG14 */ + CTIMER_OUTCFG1_CFG14_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG14_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG14_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG1_CFG14_B7OUT2 = 4, /*!< B7OUT2 : Output is B7OUT2. */ + CTIMER_OUTCFG1_CFG14_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */ + CTIMER_OUTCFG1_CFG14_B3OUT = 2, /*!< B3OUT : Output is B3OUT */ + CTIMER_OUTCFG1_CFG14_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG14_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG14_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG13 [9..11] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG13 */ + CTIMER_OUTCFG1_CFG13_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG13_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG13_B4OUT2 = 5, /*!< B4OUT2 : Output is B4OUT2. */ + CTIMER_OUTCFG1_CFG13_A6OUT = 4, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG1_CFG13_A3OUT = 3, /*!< A3OUT : Output is A3OUT. */ + CTIMER_OUTCFG1_CFG13_A3OUT2 = 2, /*!< A3OUT2 : Output is A3OUT2 */ + CTIMER_OUTCFG1_CFG13_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG13_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG13_Enum; + +/* ============================================== CTIMER OUTCFG1 CFG12 [6..8] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG12 */ + CTIMER_OUTCFG1_CFG12_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG12_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG12_B6OUT2 = 5, /*!< B6OUT2 : Output is B6OUT2. */ + CTIMER_OUTCFG1_CFG12_B0OUT2 = 4, /*!< B0OUT2 : Output is B0OUT2. */ + CTIMER_OUTCFG1_CFG12_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */ + CTIMER_OUTCFG1_CFG12_A3OUT = 2, /*!< A3OUT : Output is A3OUT */ + CTIMER_OUTCFG1_CFG12_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG12_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG12_Enum; + +/* ============================================== CTIMER OUTCFG1 CFG11 [3..5] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG11 */ + CTIMER_OUTCFG1_CFG11_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG11_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG11_B5OUT2 = 5, /*!< B5OUT2 : Output is B5OUT2. */ + CTIMER_OUTCFG1_CFG11_B4OUT = 4, /*!< B4OUT : Output is B4OUT. */ + CTIMER_OUTCFG1_CFG11_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */ + CTIMER_OUTCFG1_CFG11_B2OUT2 = 2, /*!< B2OUT2 : Output is B2OUT2 */ + CTIMER_OUTCFG1_CFG11_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG11_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG11_Enum; + +/* ============================================== CTIMER OUTCFG1 CFG10 [0..2] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG10 */ + CTIMER_OUTCFG1_CFG10_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG10_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG10_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG1_CFG10_B4OUT2 = 4, /*!< B4OUT2 : Output is B4OUT2. */ + CTIMER_OUTCFG1_CFG10_B3OUT2 = 3, /*!< B3OUT2 : Output is B3OUT2. */ + CTIMER_OUTCFG1_CFG10_B2OUT = 2, /*!< B2OUT : Output is B2OUT */ + CTIMER_OUTCFG1_CFG10_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG10_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG10_Enum; + +/* ======================================================== OUTCFG2 ======================================================== */ +/* ============================================= CTIMER OUTCFG2 CFG29 [28..30] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG29 */ + CTIMER_OUTCFG2_CFG29_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG29_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG29_A3OUT2 = 5, /*!< A3OUT2 : Output is A3OUT2. */ + CTIMER_OUTCFG2_CFG29_A7OUT = 4, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG2_CFG29_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG29_B5OUT2 = 2, /*!< B5OUT2 : Output is B5OUT2 */ + CTIMER_OUTCFG2_CFG29_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG29_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG29_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG28 [25..27] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG28 */ + CTIMER_OUTCFG2_CFG28_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG28_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG28_B0OUT2 = 5, /*!< B0OUT2 : Output is B0OUT2. */ + CTIMER_OUTCFG2_CFG28_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */ + CTIMER_OUTCFG2_CFG28_A3OUT = 3, /*!< A3OUT : Output is A3OUT. */ + CTIMER_OUTCFG2_CFG28_A7OUT = 2, /*!< A7OUT : Output is A7OUT */ + CTIMER_OUTCFG2_CFG28_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG28_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG28_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG27 [22..24] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG27 */ + CTIMER_OUTCFG2_CFG27_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG27_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG27_B2OUT2 = 5, /*!< B2OUT2 : Output is B2OUT2. */ + CTIMER_OUTCFG2_CFG27_B6OUT = 4, /*!< B6OUT : Output is B6OUT. */ + CTIMER_OUTCFG2_CFG27_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG27_B6OUT2 = 2, /*!< B6OUT2 : Output is B6OUT2 */ + CTIMER_OUTCFG2_CFG27_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG27_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG27_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG26 [19..21] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG26 */ + CTIMER_OUTCFG2_CFG26_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG26_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG26_A1OUT2 = 5, /*!< A1OUT2 : Output is A1OUT2. */ + CTIMER_OUTCFG2_CFG26_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */ + CTIMER_OUTCFG2_CFG26_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */ + CTIMER_OUTCFG2_CFG26_B6OUT = 2, /*!< B6OUT : Output is B6OUT */ + CTIMER_OUTCFG2_CFG26_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG26_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG26_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG25 [16..18] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG25 */ + CTIMER_OUTCFG2_CFG25_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG25_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG25_A2OUT2 = 5, /*!< A2OUT2 : Output is A2OUT2. */ + CTIMER_OUTCFG2_CFG25_A6OUT = 4, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG2_CFG25_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */ + CTIMER_OUTCFG2_CFG25_B4OUT2 = 2, /*!< B4OUT2 : Output is B4OUT2 */ + CTIMER_OUTCFG2_CFG25_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG25_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG25_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG24 [12..14] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG24 */ + CTIMER_OUTCFG2_CFG24_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG24_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG24_B1OUT2 = 5, /*!< B1OUT2 : Output is B1OUT2. */ + CTIMER_OUTCFG2_CFG24_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG24_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */ + CTIMER_OUTCFG2_CFG24_A6OUT = 2, /*!< A6OUT : Output is A6OUT */ + CTIMER_OUTCFG2_CFG24_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG24_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG24_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG23 [9..11] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG23 */ + CTIMER_OUTCFG2_CFG23_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG23_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG23_B0OUT2 = 5, /*!< B0OUT2 : Output is B0OUT2. */ + CTIMER_OUTCFG2_CFG23_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */ + CTIMER_OUTCFG2_CFG23_A7OUT = 3, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG2_CFG23_B5OUT2 = 2, /*!< B5OUT2 : Output is B5OUT2 */ + CTIMER_OUTCFG2_CFG23_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG23_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG23_Enum; + +/* ============================================== CTIMER OUTCFG2 CFG22 [6..8] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG22 */ + CTIMER_OUTCFG2_CFG22_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG22_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG22_A2OUT2 = 5, /*!< A2OUT2 : Output is A2OUT2. */ + CTIMER_OUTCFG2_CFG22_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG22_A6OUT = 3, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG2_CFG22_B5OUT = 2, /*!< B5OUT : Output is B5OUT */ + CTIMER_OUTCFG2_CFG22_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG22_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG22_Enum; + +/* ============================================== CTIMER OUTCFG2 CFG21 [3..5] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG21 */ + CTIMER_OUTCFG2_CFG21_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG21_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG21_A0OUT2 = 5, /*!< A0OUT2 : Output is A0OUT2. */ + CTIMER_OUTCFG2_CFG21_B5OUT = 4, /*!< B5OUT : Output is B5OUT. */ + CTIMER_OUTCFG2_CFG21_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG21_A5OUT2 = 2, /*!< A5OUT2 : Output is A5OUT2 */ + CTIMER_OUTCFG2_CFG21_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG21_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG21_Enum; + +/* ============================================== CTIMER OUTCFG2 CFG20 [0..2] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG20 */ + CTIMER_OUTCFG2_CFG20_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG20_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG20_B2OUT2 = 5, /*!< B2OUT2 : Output is B2OUT2. */ + CTIMER_OUTCFG2_CFG20_A1OUT2 = 4, /*!< A1OUT2 : Output is A1OUT2. */ + CTIMER_OUTCFG2_CFG20_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG20_A5OUT = 2, /*!< A5OUT : Output is A5OUT */ + CTIMER_OUTCFG2_CFG20_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG20_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG20_Enum; + +/* ======================================================== OUTCFG3 ======================================================== */ +/* ============================================== CTIMER OUTCFG3 CFG31 [3..5] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG3_CFG31 */ + CTIMER_OUTCFG3_CFG31_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG3_CFG31_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG3_CFG31_B3OUT2 = 5, /*!< B3OUT2 : Output is B3OUT2. */ + CTIMER_OUTCFG3_CFG31_B7OUT = 4, /*!< B7OUT : Output is B7OUT. */ + CTIMER_OUTCFG3_CFG31_A6OUT = 3, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG3_CFG31_B7OUT2 = 2, /*!< B7OUT2 : Output is B7OUT2 */ + CTIMER_OUTCFG3_CFG31_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG3_CFG31_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG3_CFG31_Enum; + +/* ============================================== CTIMER OUTCFG3 CFG30 [0..2] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG3_CFG30 */ + CTIMER_OUTCFG3_CFG30_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG3_CFG30_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG3_CFG30_A0OUT2 = 5, /*!< A0OUT2 : Output is A0OUT2. */ + CTIMER_OUTCFG3_CFG30_A4OUT2 = 4, /*!< A4OUT2 : Output is A4OUT2. */ + CTIMER_OUTCFG3_CFG30_B3OUT = 3, /*!< B3OUT : Output is B3OUT. */ + CTIMER_OUTCFG3_CFG30_B7OUT = 2, /*!< B7OUT : Output is B7OUT */ + CTIMER_OUTCFG3_CFG30_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG3_CFG30_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG3_CFG30_Enum; + +/* ========================================================= INCFG ========================================================= */ +/* ============================================== CTIMER INCFG CFGB7 [15..15] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB7 */ + CTIMER_INCFG_CFGB7_CT31 = 1, /*!< CT31 : Input is CT31 */ + CTIMER_INCFG_CFGB7_CT30 = 0, /*!< CT30 : Input is CT30 */ +} CTIMER_INCFG_CFGB7_Enum; + +/* ============================================== CTIMER INCFG CFGA7 [14..14] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA7 */ + CTIMER_INCFG_CFGA7_CT29 = 1, /*!< CT29 : Input is CT29 */ + CTIMER_INCFG_CFGA7_CT28 = 0, /*!< CT28 : Input is CT28 */ +} CTIMER_INCFG_CFGA7_Enum; + +/* ============================================== CTIMER INCFG CFGB6 [13..13] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB6 */ + CTIMER_INCFG_CFGB6_CT27 = 1, /*!< CT27 : Input is CT27 */ + CTIMER_INCFG_CFGB6_CT26 = 0, /*!< CT26 : Input is CT26 */ +} CTIMER_INCFG_CFGB6_Enum; + +/* ============================================== CTIMER INCFG CFGA6 [12..12] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA6 */ + CTIMER_INCFG_CFGA6_CT25 = 1, /*!< CT25 : Input is CT25 */ + CTIMER_INCFG_CFGA6_CT24 = 0, /*!< CT24 : Input is CT24 */ +} CTIMER_INCFG_CFGA6_Enum; + +/* ============================================== CTIMER INCFG CFGB5 [11..11] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB5 */ + CTIMER_INCFG_CFGB5_CT23 = 1, /*!< CT23 : Input is CT23 */ + CTIMER_INCFG_CFGB5_CT22 = 0, /*!< CT22 : Input is CT22 */ +} CTIMER_INCFG_CFGB5_Enum; + +/* ============================================== CTIMER INCFG CFGA5 [10..10] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA5 */ + CTIMER_INCFG_CFGA5_CT21 = 1, /*!< CT21 : Input is CT21 */ + CTIMER_INCFG_CFGA5_CT20 = 0, /*!< CT20 : Input is CT20 */ +} CTIMER_INCFG_CFGA5_Enum; + +/* =============================================== CTIMER INCFG CFGB4 [9..9] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB4 */ + CTIMER_INCFG_CFGB4_CT19 = 1, /*!< CT19 : Input is CT19 */ + CTIMER_INCFG_CFGB4_CT18 = 0, /*!< CT18 : Input is CT18 */ +} CTIMER_INCFG_CFGB4_Enum; + +/* =============================================== CTIMER INCFG CFGA4 [8..8] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA4 */ + CTIMER_INCFG_CFGA4_CT17 = 1, /*!< CT17 : Input is CT17 */ + CTIMER_INCFG_CFGA4_CT16 = 0, /*!< CT16 : Input is CT16 */ +} CTIMER_INCFG_CFGA4_Enum; + +/* =============================================== CTIMER INCFG CFGB3 [7..7] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB3 */ + CTIMER_INCFG_CFGB3_CT15 = 1, /*!< CT15 : Input is CT15 */ + CTIMER_INCFG_CFGB3_CT14 = 0, /*!< CT14 : Input is CT14 */ +} CTIMER_INCFG_CFGB3_Enum; + +/* =============================================== CTIMER INCFG CFGA3 [6..6] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA3 */ + CTIMER_INCFG_CFGA3_CT13 = 1, /*!< CT13 : Input is CT13 */ + CTIMER_INCFG_CFGA3_CT12 = 0, /*!< CT12 : Input is CT12 */ +} CTIMER_INCFG_CFGA3_Enum; + +/* =============================================== CTIMER INCFG CFGB2 [5..5] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB2 */ + CTIMER_INCFG_CFGB2_CT11 = 1, /*!< CT11 : Input is CT11 */ + CTIMER_INCFG_CFGB2_CT10 = 0, /*!< CT10 : Input is CT10 */ +} CTIMER_INCFG_CFGB2_Enum; + +/* =============================================== CTIMER INCFG CFGA2 [4..4] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA2 */ + CTIMER_INCFG_CFGA2_CT9 = 1, /*!< CT9 : Input is CT9 */ + CTIMER_INCFG_CFGA2_CT8 = 0, /*!< CT8 : Input is CT8 */ +} CTIMER_INCFG_CFGA2_Enum; + +/* =============================================== CTIMER INCFG CFGB1 [3..3] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB1 */ + CTIMER_INCFG_CFGB1_CT7 = 1, /*!< CT7 : Input is CT7 */ + CTIMER_INCFG_CFGB1_CT6 = 0, /*!< CT6 : Input is CT6 */ +} CTIMER_INCFG_CFGB1_Enum; + +/* =============================================== CTIMER INCFG CFGA1 [2..2] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA1 */ + CTIMER_INCFG_CFGA1_CT5 = 1, /*!< CT5 : Input is CT5 */ + CTIMER_INCFG_CFGA1_CT4 = 0, /*!< CT4 : Input is CT4 */ +} CTIMER_INCFG_CFGA1_Enum; + +/* =============================================== CTIMER INCFG CFGB0 [1..1] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB0 */ + CTIMER_INCFG_CFGB0_CT3 = 1, /*!< CT3 : Input is CT3 */ + CTIMER_INCFG_CFGB0_CT2 = 0, /*!< CT2 : Input is CT2 */ +} CTIMER_INCFG_CFGB0_Enum; + +/* =============================================== CTIMER INCFG CFGA0 [0..0] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA0 */ + CTIMER_INCFG_CFGA0_CT1 = 1, /*!< CT1 : Input is CT1 */ + CTIMER_INCFG_CFGA0_CT0 = 0, /*!< CT0 : Input is CT0 */ +} CTIMER_INCFG_CFGA0_Enum; + +/* ========================================================= STCFG ========================================================= */ +/* ============================================= CTIMER STCFG FREEZE [31..31] ============================================== */ +typedef enum { /*!< CTIMER_STCFG_FREEZE */ + CTIMER_STCFG_FREEZE_THAW = 0, /*!< THAW : Let the COUNTER register run on its input clock. */ + CTIMER_STCFG_FREEZE_FREEZE = 1, /*!< FREEZE : Stop the COUNTER register for loading. */ +} CTIMER_STCFG_FREEZE_Enum; + +/* ============================================== CTIMER STCFG CLEAR [30..30] ============================================== */ +typedef enum { /*!< CTIMER_STCFG_CLEAR */ + CTIMER_STCFG_CLEAR_RUN = 0, /*!< RUN : Let the COUNTER register run on its input clock. */ + CTIMER_STCFG_CLEAR_CLEAR = 1, /*!< CLEAR : Stop the COUNTER register for loading. */ +} CTIMER_STCFG_CLEAR_Enum; + +/* ========================================== CTIMER STCFG COMPARE_H_EN [15..15] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_H_EN */ + CTIMER_STCFG_COMPARE_H_EN_DISABLE = 0, /*!< DISABLE : Compare H disabled. */ + CTIMER_STCFG_COMPARE_H_EN_ENABLE = 1, /*!< ENABLE : Compare H enabled. */ +} CTIMER_STCFG_COMPARE_H_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_G_EN [14..14] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_G_EN */ + CTIMER_STCFG_COMPARE_G_EN_DISABLE = 0, /*!< DISABLE : Compare G disabled. */ + CTIMER_STCFG_COMPARE_G_EN_ENABLE = 1, /*!< ENABLE : Compare G enabled. */ +} CTIMER_STCFG_COMPARE_G_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_F_EN [13..13] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_F_EN */ + CTIMER_STCFG_COMPARE_F_EN_DISABLE = 0, /*!< DISABLE : Compare F disabled. */ + CTIMER_STCFG_COMPARE_F_EN_ENABLE = 1, /*!< ENABLE : Compare F enabled. */ +} CTIMER_STCFG_COMPARE_F_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_E_EN [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_E_EN */ + CTIMER_STCFG_COMPARE_E_EN_DISABLE = 0, /*!< DISABLE : Compare E disabled. */ + CTIMER_STCFG_COMPARE_E_EN_ENABLE = 1, /*!< ENABLE : Compare E enabled. */ +} CTIMER_STCFG_COMPARE_E_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_D_EN [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_D_EN */ + CTIMER_STCFG_COMPARE_D_EN_DISABLE = 0, /*!< DISABLE : Compare D disabled. */ + CTIMER_STCFG_COMPARE_D_EN_ENABLE = 1, /*!< ENABLE : Compare D enabled. */ +} CTIMER_STCFG_COMPARE_D_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_C_EN [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_C_EN */ + CTIMER_STCFG_COMPARE_C_EN_DISABLE = 0, /*!< DISABLE : Compare C disabled. */ + CTIMER_STCFG_COMPARE_C_EN_ENABLE = 1, /*!< ENABLE : Compare C enabled. */ +} CTIMER_STCFG_COMPARE_C_EN_Enum; + +/* =========================================== CTIMER STCFG COMPARE_B_EN [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_B_EN */ + CTIMER_STCFG_COMPARE_B_EN_DISABLE = 0, /*!< DISABLE : Compare B disabled. */ + CTIMER_STCFG_COMPARE_B_EN_ENABLE = 1, /*!< ENABLE : Compare B enabled. */ +} CTIMER_STCFG_COMPARE_B_EN_Enum; + +/* =========================================== CTIMER STCFG COMPARE_A_EN [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_A_EN */ + CTIMER_STCFG_COMPARE_A_EN_DISABLE = 0, /*!< DISABLE : Compare A disabled. */ + CTIMER_STCFG_COMPARE_A_EN_ENABLE = 1, /*!< ENABLE : Compare A enabled. */ +} CTIMER_STCFG_COMPARE_A_EN_Enum; + +/* ============================================== CTIMER STCFG CLKSEL [0..3] =============================================== */ +typedef enum { /*!< CTIMER_STCFG_CLKSEL */ + CTIMER_STCFG_CLKSEL_NOCLK = 0, /*!< NOCLK : No clock enabled. */ + CTIMER_STCFG_CLKSEL_HFRC_DIV16 = 1, /*!< HFRC_DIV16 : 3MHz from the HFRC clock divider. */ + CTIMER_STCFG_CLKSEL_HFRC_DIV256 = 2, /*!< HFRC_DIV256 : 187.5KHz from the HFRC clock divider. */ + CTIMER_STCFG_CLKSEL_XTAL_DIV1 = 3, /*!< XTAL_DIV1 : 32768Hz from the crystal oscillator. */ + CTIMER_STCFG_CLKSEL_XTAL_DIV2 = 4, /*!< XTAL_DIV2 : 16384Hz from the crystal oscillator. */ + CTIMER_STCFG_CLKSEL_XTAL_DIV32 = 5, /*!< XTAL_DIV32 : 1024Hz from the crystal oscillator. */ + CTIMER_STCFG_CLKSEL_LFRC_DIV1 = 6, /*!< LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated). */ + CTIMER_STCFG_CLKSEL_CTIMER0A = 7, /*!< CTIMER0A : Use CTIMER 0 section A as a prescaler for the clock + source. */ + CTIMER_STCFG_CLKSEL_CTIMER0B = 8, /*!< CTIMER0B : Use CTIMER 0 section B (or A and B linked together) + as a prescaler for the clock source. */ +} CTIMER_STCFG_CLKSEL_Enum; + +/* ========================================================= STTMR ========================================================= */ +/* ==================================================== CAPTURECONTROL ===================================================== */ +/* ========================================= CTIMER CAPTURECONTROL CAPTURE3 [3..3] ========================================= */ +typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE3 */ + CTIMER_CAPTURECONTROL_CAPTURE3_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURECONTROL_CAPTURE3_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURECONTROL_CAPTURE3_Enum; + +/* ========================================= CTIMER CAPTURECONTROL CAPTURE2 [2..2] ========================================= */ +typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE2 */ + CTIMER_CAPTURECONTROL_CAPTURE2_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURECONTROL_CAPTURE2_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURECONTROL_CAPTURE2_Enum; + +/* ========================================= CTIMER CAPTURECONTROL CAPTURE1 [1..1] ========================================= */ +typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE1 */ + CTIMER_CAPTURECONTROL_CAPTURE1_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURECONTROL_CAPTURE1_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURECONTROL_CAPTURE1_Enum; + +/* ========================================= CTIMER CAPTURECONTROL CAPTURE0 [0..0] ========================================= */ +typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE0 */ + CTIMER_CAPTURECONTROL_CAPTURE0_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURECONTROL_CAPTURE0_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURECONTROL_CAPTURE0_Enum; + +/* ======================================================== SCMPR0 ========================================================= */ +/* ======================================================== SCMPR1 ========================================================= */ +/* ======================================================== SCMPR2 ========================================================= */ +/* ======================================================== SCMPR3 ========================================================= */ +/* ======================================================== SCMPR4 ========================================================= */ +/* ======================================================== SCMPR5 ========================================================= */ +/* ======================================================== SCMPR6 ========================================================= */ +/* ======================================================== SCMPR7 ========================================================= */ +/* ======================================================== SCAPT0 ========================================================= */ +/* ======================================================== SCAPT1 ========================================================= */ +/* ======================================================== SCAPT2 ========================================================= */ +/* ======================================================== SCAPT3 ========================================================= */ +/* ========================================================= SNVR0 ========================================================= */ +/* ========================================================= SNVR1 ========================================================= */ +/* ========================================================= SNVR2 ========================================================= */ +/* ========================================================= SNVR3 ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================= STMINTEN ======================================================== */ +/* =========================================== CTIMER STMINTEN CAPTURED [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTURED */ + CTIMER_STMINTEN_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTURED_Enum; + +/* =========================================== CTIMER STMINTEN CAPTUREC [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTUREC */ + CTIMER_STMINTEN_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTUREC_Enum; + +/* =========================================== CTIMER STMINTEN CAPTUREB [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTUREB */ + CTIMER_STMINTEN_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTUREB_Enum; + +/* ============================================ CTIMER STMINTEN CAPTUREA [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTUREA */ + CTIMER_STMINTEN_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTUREA_Enum; + +/* ============================================ CTIMER STMINTEN OVERFLOW [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_OVERFLOW */ + CTIMER_STMINTEN_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTEN_OVERFLOW_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREH [7..7] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREH */ + CTIMER_STMINTEN_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREH_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREG [6..6] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREG */ + CTIMER_STMINTEN_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREG_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREF [5..5] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREF */ + CTIMER_STMINTEN_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREF_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREE [4..4] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREE */ + CTIMER_STMINTEN_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREE_Enum; + +/* ============================================ CTIMER STMINTEN COMPARED [3..3] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPARED */ + CTIMER_STMINTEN_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPARED_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREC [2..2] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREC */ + CTIMER_STMINTEN_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREC_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREB [1..1] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREB */ + CTIMER_STMINTEN_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREB_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREA [0..0] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREA */ + CTIMER_STMINTEN_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREA_Enum; + +/* ====================================================== STMINTSTAT ======================================================= */ +/* ========================================== CTIMER STMINTSTAT CAPTURED [12..12] ========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTURED */ + CTIMER_STMINTSTAT_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTURED_Enum; + +/* ========================================== CTIMER STMINTSTAT CAPTUREC [11..11] ========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREC */ + CTIMER_STMINTSTAT_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTUREC_Enum; + +/* ========================================== CTIMER STMINTSTAT CAPTUREB [10..10] ========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREB */ + CTIMER_STMINTSTAT_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTUREB_Enum; + +/* =========================================== CTIMER STMINTSTAT CAPTUREA [9..9] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREA */ + CTIMER_STMINTSTAT_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTUREA_Enum; + +/* =========================================== CTIMER STMINTSTAT OVERFLOW [8..8] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_OVERFLOW */ + CTIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTSTAT_OVERFLOW_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREH [7..7] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREH */ + CTIMER_STMINTSTAT_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREH_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREG [6..6] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREG */ + CTIMER_STMINTSTAT_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREG_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREF [5..5] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREF */ + CTIMER_STMINTSTAT_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREF_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREE [4..4] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREE */ + CTIMER_STMINTSTAT_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREE_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPARED [3..3] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPARED */ + CTIMER_STMINTSTAT_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPARED_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREC [2..2] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREC */ + CTIMER_STMINTSTAT_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREC_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREB [1..1] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREB */ + CTIMER_STMINTSTAT_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREB_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREA [0..0] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREA */ + CTIMER_STMINTSTAT_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREA_Enum; + +/* ======================================================= STMINTCLR ======================================================= */ +/* ========================================== CTIMER STMINTCLR CAPTURED [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTURED */ + CTIMER_STMINTCLR_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTURED_Enum; + +/* ========================================== CTIMER STMINTCLR CAPTUREC [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREC */ + CTIMER_STMINTCLR_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTUREC_Enum; + +/* ========================================== CTIMER STMINTCLR CAPTUREB [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREB */ + CTIMER_STMINTCLR_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTUREB_Enum; + +/* =========================================== CTIMER STMINTCLR CAPTUREA [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREA */ + CTIMER_STMINTCLR_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTUREA_Enum; + +/* =========================================== CTIMER STMINTCLR OVERFLOW [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_OVERFLOW */ + CTIMER_STMINTCLR_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTCLR_OVERFLOW_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREH [7..7] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREH */ + CTIMER_STMINTCLR_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREH_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREG [6..6] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREG */ + CTIMER_STMINTCLR_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREG_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREF [5..5] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREF */ + CTIMER_STMINTCLR_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREF_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREE [4..4] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREE */ + CTIMER_STMINTCLR_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREE_Enum; + +/* =========================================== CTIMER STMINTCLR COMPARED [3..3] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPARED */ + CTIMER_STMINTCLR_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPARED_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREC [2..2] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREC */ + CTIMER_STMINTCLR_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREC_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREB [1..1] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREB */ + CTIMER_STMINTCLR_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREB_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREA [0..0] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREA */ + CTIMER_STMINTCLR_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREA_Enum; + +/* ======================================================= STMINTSET ======================================================= */ +/* ========================================== CTIMER STMINTSET CAPTURED [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTURED */ + CTIMER_STMINTSET_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTURED_Enum; + +/* ========================================== CTIMER STMINTSET CAPTUREC [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTUREC */ + CTIMER_STMINTSET_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTUREC_Enum; + +/* ========================================== CTIMER STMINTSET CAPTUREB [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTUREB */ + CTIMER_STMINTSET_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTUREB_Enum; + +/* =========================================== CTIMER STMINTSET CAPTUREA [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTUREA */ + CTIMER_STMINTSET_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTUREA_Enum; + +/* =========================================== CTIMER STMINTSET OVERFLOW [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_OVERFLOW */ + CTIMER_STMINTSET_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTSET_OVERFLOW_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREH [7..7] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREH */ + CTIMER_STMINTSET_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREH_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREG [6..6] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREG */ + CTIMER_STMINTSET_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREG_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREF [5..5] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREF */ + CTIMER_STMINTSET_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREF_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREE [4..4] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREE */ + CTIMER_STMINTSET_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREE_Enum; + +/* =========================================== CTIMER STMINTSET COMPARED [3..3] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPARED */ + CTIMER_STMINTSET_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPARED_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREC [2..2] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREC */ + CTIMER_STMINTSET_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREC_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREB [1..1] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREB */ + CTIMER_STMINTSET_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREB_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREA [0..0] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREA */ + CTIMER_STMINTSET_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREA_Enum; + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PADREGA ======================================================== */ +/* ============================================ GPIO PADREGA PAD3PWRUP [30..30] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3PWRUP */ + GPIO_PADREGA_PAD3PWRUP_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGA_PAD3PWRUP_EN = 1, /*!< EN : Power switch enabled (switched to VDD) */ +} GPIO_PADREGA_PAD3PWRUP_Enum; + +/* =========================================== GPIO PADREGA PAD3FNCSEL [27..29] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3FNCSEL */ + GPIO_PADREGA_PAD3FNCSEL_UA0RTS = 0, /*!< UA0RTS : Configure as the UART0 RTS output */ + GPIO_PADREGA_PAD3FNCSEL_SLnCE = 1, /*!< SLnCE : Configure as the IOSLAVE SPI nCE signal */ + GPIO_PADREGA_PAD3FNCSEL_NCE3 = 2, /*!< NCE3 : IOM/MSPI nCE group 3 */ + GPIO_PADREGA_PAD3FNCSEL_GPIO3 = 3, /*!< GPIO3 : Configure as GPIO3 */ + GPIO_PADREGA_PAD3FNCSEL_MSPI7 = 5, /*!< MSPI7 : MSPI data connection 7 */ + GPIO_PADREGA_PAD3FNCSEL_TRIG1 = 6, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ + GPIO_PADREGA_PAD3FNCSEL_I2S_WCLK = 7, /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input */ +} GPIO_PADREGA_PAD3FNCSEL_Enum; + +/* ============================================ GPIO PADREGA PAD3STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3STRNG */ + GPIO_PADREGA_PAD3STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD3STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD3STRNG_Enum; + +/* ============================================ GPIO PADREGA PAD3INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3INPEN */ + GPIO_PADREGA_PAD3INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD3INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD3INPEN_Enum; + +/* ============================================ GPIO PADREGA PAD3PULL [24..24] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD3PULL */ + GPIO_PADREGA_PAD3PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD3PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD3PULL_Enum; + +/* =========================================== GPIO PADREGA PAD2FNCSEL [19..21] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD2FNCSEL */ + GPIO_PADREGA_PAD2FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as the UART1 RX input. */ + GPIO_PADREGA_PAD2FNCSEL_SLMISO = 1, /*!< SLMISO : Configure as the IOSLAVE SPI MISO signal. */ + GPIO_PADREGA_PAD2FNCSEL_UART0RX = 2, /*!< UART0RX : Configure as the UART0 RX input. */ + GPIO_PADREGA_PAD2FNCSEL_GPIO2 = 3, /*!< GPIO2 : Configure as GPIO2. */ + GPIO_PADREGA_PAD2FNCSEL_MSPI6 = 5, /*!< MSPI6 : MSPI data connection 6. */ + GPIO_PADREGA_PAD2FNCSEL_NCE2 = 7, /*!< NCE2 : IOM/MSPI nCE group 2 */ +} GPIO_PADREGA_PAD2FNCSEL_Enum; + +/* ============================================ GPIO PADREGA PAD2STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD2STRNG */ + GPIO_PADREGA_PAD2STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD2STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD2STRNG_Enum; + +/* ============================================ GPIO PADREGA PAD2INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD2INPEN */ + GPIO_PADREGA_PAD2INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD2INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD2INPEN_Enum; + +/* ============================================ GPIO PADREGA PAD2PULL [16..16] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD2PULL */ + GPIO_PADREGA_PAD2PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD2PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD2PULL_Enum; + +/* ============================================ GPIO PADREGA PAD1RSEL [14..15] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD1RSEL */ + GPIO_PADREGA_PAD1RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGA_PAD1RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGA_PAD1RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGA_PAD1RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGA_PAD1RSEL_Enum; + +/* =========================================== GPIO PADREGA PAD1FNCSEL [11..13] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD1FNCSEL */ + GPIO_PADREGA_PAD1FNCSEL_SLSDAWIR3 = 0, /*!< SLSDAWIR3 : Configure as the IOSLAVE I2C SDA or SPI WIR3 signal */ + GPIO_PADREGA_PAD1FNCSEL_SLMOSI = 1, /*!< SLMOSI : Configure as the IOSLAVE SPI MOSI signal */ + GPIO_PADREGA_PAD1FNCSEL_UART0TX = 2, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGA_PAD1FNCSEL_GPIO1 = 3, /*!< GPIO1 : Configure as GPIO1 */ + GPIO_PADREGA_PAD1FNCSEL_MSPI5 = 5, /*!< MSPI5 : MSPI data connection 5 */ + GPIO_PADREGA_PAD1FNCSEL_NCE1 = 7, /*!< NCE1 : IOM/MSPI nCE group 1 */ +} GPIO_PADREGA_PAD1FNCSEL_Enum; + +/* ============================================ GPIO PADREGA PAD1STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD1STRNG */ + GPIO_PADREGA_PAD1STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD1STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD1STRNG_Enum; + +/* ============================================= GPIO PADREGA PAD1INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD1INPEN */ + GPIO_PADREGA_PAD1INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD1INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD1INPEN_Enum; + +/* ============================================= GPIO PADREGA PAD1PULL [8..8] ============================================== */ +typedef enum { /*!< GPIO_PADREGA_PAD1PULL */ + GPIO_PADREGA_PAD1PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD1PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD1PULL_Enum; + +/* ============================================= GPIO PADREGA PAD0RSEL [6..7] ============================================== */ +typedef enum { /*!< GPIO_PADREGA_PAD0RSEL */ + GPIO_PADREGA_PAD0RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGA_PAD0RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGA_PAD0RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGA_PAD0RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGA_PAD0RSEL_Enum; + +/* ============================================ GPIO PADREGA PAD0FNCSEL [3..5] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD0FNCSEL */ + GPIO_PADREGA_PAD0FNCSEL_SLSCL = 0, /*!< SLSCL : Configure as the IOSLAVE I2C SCL signal */ + GPIO_PADREGA_PAD0FNCSEL_SLSCK = 1, /*!< SLSCK : Configure as the IOSLAVE SPI SCK signal */ + GPIO_PADREGA_PAD0FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGA_PAD0FNCSEL_GPIO0 = 3, /*!< GPIO0 : Configure as GPIO0 */ + GPIO_PADREGA_PAD0FNCSEL_MSPI4 = 5, /*!< MSPI4 : MSPI data connection 4 */ + GPIO_PADREGA_PAD0FNCSEL_NCE0 = 7, /*!< NCE0 : IOM/MSPI nCE group 0 */ +} GPIO_PADREGA_PAD0FNCSEL_Enum; + +/* ============================================= GPIO PADREGA PAD0STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD0STRNG */ + GPIO_PADREGA_PAD0STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD0STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD0STRNG_Enum; + +/* ============================================= GPIO PADREGA PAD0INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD0INPEN */ + GPIO_PADREGA_PAD0INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD0INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD0INPEN_Enum; + +/* ============================================= GPIO PADREGA PAD0PULL [0..0] ============================================== */ +typedef enum { /*!< GPIO_PADREGA_PAD0PULL */ + GPIO_PADREGA_PAD0PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD0PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD0PULL_Enum; + +/* ======================================================== PADREGB ======================================================== */ +/* =========================================== GPIO PADREGB PAD7FNCSEL [27..29] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD7FNCSEL */ + GPIO_PADREGB_PAD7FNCSEL_NCE7 = 0, /*!< NCE7 : IOM/MSPI nCE group 7 */ + GPIO_PADREGB_PAD7FNCSEL_M0MOSI = 1, /*!< M0MOSI : Configure as the IOMSTR0 SPI MOSI signal */ + GPIO_PADREGB_PAD7FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGB_PAD7FNCSEL_GPIO7 = 3, /*!< GPIO7 : Configure as GPIO7 */ + GPIO_PADREGB_PAD7FNCSEL_TRIG0 = 4, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ + GPIO_PADREGB_PAD7FNCSEL_UART0TX = 5, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGB_PAD7FNCSEL_CT19 = 7, /*!< CT19 : CTIMER connection 19 */ +} GPIO_PADREGB_PAD7FNCSEL_Enum; + +/* ============================================ GPIO PADREGB PAD7STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD7STRNG */ + GPIO_PADREGB_PAD7STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD7STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD7STRNG_Enum; + +/* ============================================ GPIO PADREGB PAD7INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD7INPEN */ + GPIO_PADREGB_PAD7INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD7INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD7INPEN_Enum; + +/* ============================================ GPIO PADREGB PAD7PULL [24..24] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD7PULL */ + GPIO_PADREGB_PAD7PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD7PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD7PULL_Enum; + +/* ============================================ GPIO PADREGB PAD6RSEL [22..23] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD6RSEL */ + GPIO_PADREGB_PAD6RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGB_PAD6RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGB_PAD6RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGB_PAD6RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGB_PAD6RSEL_Enum; + +/* =========================================== GPIO PADREGB PAD6FNCSEL [19..21] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD6FNCSEL */ + GPIO_PADREGB_PAD6FNCSEL_M0SDAWIR3 = 0, /*!< M0SDAWIR3 : Configure as the IOMSTR0 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGB_PAD6FNCSEL_M0MISO = 1, /*!< M0MISO : Configure as the IOMSTR0 SPI MISO signal */ + GPIO_PADREGB_PAD6FNCSEL_UA0CTS = 2, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGB_PAD6FNCSEL_GPIO6 = 3, /*!< GPIO6 : Configure as GPIO6 */ + GPIO_PADREGB_PAD6FNCSEL_CT10 = 5, /*!< CT10 : CTIMER connection 10 */ + GPIO_PADREGB_PAD6FNCSEL_I2S_DAT = 7, /*!< I2S_DAT : Configure as the PDM I2S Data output signal */ +} GPIO_PADREGB_PAD6FNCSEL_Enum; + +/* ============================================ GPIO PADREGB PAD6STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD6STRNG */ + GPIO_PADREGB_PAD6STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD6STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD6STRNG_Enum; + +/* ============================================ GPIO PADREGB PAD6INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD6INPEN */ + GPIO_PADREGB_PAD6INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD6INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD6INPEN_Enum; + +/* ============================================ GPIO PADREGB PAD6PULL [16..16] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD6PULL */ + GPIO_PADREGB_PAD6PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD6PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD6PULL_Enum; + +/* ============================================ GPIO PADREGB PAD5RSEL [14..15] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD5RSEL */ + GPIO_PADREGB_PAD5RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGB_PAD5RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGB_PAD5RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGB_PAD5RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGB_PAD5RSEL_Enum; + +/* =========================================== GPIO PADREGB PAD5FNCSEL [11..13] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD5FNCSEL */ + GPIO_PADREGB_PAD5FNCSEL_M0SCL = 0, /*!< M0SCL : Configure as the IOMSTR0 I2C SCL signal */ + GPIO_PADREGB_PAD5FNCSEL_M0SCK = 1, /*!< M0SCK : Configure as the IOMSTR0 SPI SCK signal */ + GPIO_PADREGB_PAD5FNCSEL_UA0RTS = 2, /*!< UA0RTS : Configure as the UART0 RTS signal output */ + GPIO_PADREGB_PAD5FNCSEL_GPIO5 = 3, /*!< GPIO5 : Configure as GPIO5 */ + GPIO_PADREGB_PAD5FNCSEL_EXTHFA = 5, /*!< EXTHFA : Configure as the External HFA input clock */ + GPIO_PADREGB_PAD5FNCSEL_CT8 = 7, /*!< CT8 : CTIMER connection 8 */ +} GPIO_PADREGB_PAD5FNCSEL_Enum; + +/* ============================================ GPIO PADREGB PAD5STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD5STRNG */ + GPIO_PADREGB_PAD5STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD5STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD5STRNG_Enum; + +/* ============================================= GPIO PADREGB PAD5INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD5INPEN */ + GPIO_PADREGB_PAD5INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD5INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD5INPEN_Enum; + +/* ============================================= GPIO PADREGB PAD5PULL [8..8] ============================================== */ +typedef enum { /*!< GPIO_PADREGB_PAD5PULL */ + GPIO_PADREGB_PAD5PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD5PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD5PULL_Enum; + +/* ============================================ GPIO PADREGB PAD4FNCSEL [3..5] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD4FNCSEL */ + GPIO_PADREGB_PAD4FNCSEL_UA0CTS = 0, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGB_PAD4FNCSEL_SLINT = 1, /*!< SLINT : Configure as the IOSLAVE interrupt out signal */ + GPIO_PADREGB_PAD4FNCSEL_NCE4 = 2, /*!< NCE4 : IOM/SPI nCE group 4 */ + GPIO_PADREGB_PAD4FNCSEL_GPIO4 = 3, /*!< GPIO4 : Configure as GPIO4 */ + GPIO_PADREGB_PAD4FNCSEL_UART0RX = 5, /*!< UART0RX : Configure as the UART0 RX input */ + GPIO_PADREGB_PAD4FNCSEL_CT17 = 6, /*!< CT17 : CTIMER connection 17 */ + GPIO_PADREGB_PAD4FNCSEL_MSPI2 = 7, /*!< MSPI2 : MSPI data connection 2 */ +} GPIO_PADREGB_PAD4FNCSEL_Enum; + +/* ============================================= GPIO PADREGB PAD4STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD4STRNG */ + GPIO_PADREGB_PAD4STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD4STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD4STRNG_Enum; + +/* ============================================= GPIO PADREGB PAD4INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD4INPEN */ + GPIO_PADREGB_PAD4INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD4INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD4INPEN_Enum; + +/* ============================================= GPIO PADREGB PAD4PULL [0..0] ============================================== */ +typedef enum { /*!< GPIO_PADREGB_PAD4PULL */ + GPIO_PADREGB_PAD4PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD4PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD4PULL_Enum; + +/* ======================================================== PADREGC ======================================================== */ +/* =========================================== GPIO PADREGC PAD11FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD11FNCSEL */ + GPIO_PADREGC_PAD11FNCSEL_ADCSE2 = 0, /*!< ADCSE2 : Configure as the analog input for ADC single ended + input 2 */ + GPIO_PADREGC_PAD11FNCSEL_NCE11 = 1, /*!< NCE11 : IOM/MSPI nCE group 11 */ + GPIO_PADREGC_PAD11FNCSEL_CT31 = 2, /*!< CT31 : CTIMER connection 31 */ + GPIO_PADREGC_PAD11FNCSEL_GPIO11 = 3, /*!< GPIO11 : Configure as GPIO11 */ + GPIO_PADREGC_PAD11FNCSEL_SLINT = 4, /*!< SLINT : Configure as the IOSLAVE interrupt out signal */ + GPIO_PADREGC_PAD11FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */ + GPIO_PADREGC_PAD11FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGC_PAD11FNCSEL_PDM_DATA = 7, /*!< PDM_DATA : Configure as the PDM Data input signal */ +} GPIO_PADREGC_PAD11FNCSEL_Enum; + +/* =========================================== GPIO PADREGC PAD11STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD11STRNG */ + GPIO_PADREGC_PAD11STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD11STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD11STRNG_Enum; + +/* =========================================== GPIO PADREGC PAD11INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD11INPEN */ + GPIO_PADREGC_PAD11INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD11INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD11INPEN_Enum; + +/* ============================================ GPIO PADREGC PAD11PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD11PULL */ + GPIO_PADREGC_PAD11PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD11PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD11PULL_Enum; + +/* =========================================== GPIO PADREGC PAD10FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD10FNCSEL */ + GPIO_PADREGC_PAD10FNCSEL_M1MOSI = 1, /*!< M1MOSI : Configure as the IOMSTR1 SPI MOSI signal */ + GPIO_PADREGC_PAD10FNCSEL_NCE10 = 2, /*!< NCE10 : IOM/MSPI nCE group 10 */ + GPIO_PADREGC_PAD10FNCSEL_GPIO10 = 3, /*!< GPIO10 : Configure as GPIO10 */ + GPIO_PADREGC_PAD10FNCSEL_PDMCLK = 4, /*!< PDMCLK : PDM serial clock out */ + GPIO_PADREGC_PAD10FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as the UART1 RTS output signal */ +} GPIO_PADREGC_PAD10FNCSEL_Enum; + +/* =========================================== GPIO PADREGC PAD10STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD10STRNG */ + GPIO_PADREGC_PAD10STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD10STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD10STRNG_Enum; + +/* =========================================== GPIO PADREGC PAD10INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD10INPEN */ + GPIO_PADREGC_PAD10INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD10INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD10INPEN_Enum; + +/* ============================================ GPIO PADREGC PAD10PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD10PULL */ + GPIO_PADREGC_PAD10PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD10PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD10PULL_Enum; + +/* ============================================ GPIO PADREGC PAD9RSEL [14..15] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD9RSEL */ + GPIO_PADREGC_PAD9RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGC_PAD9RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGC_PAD9RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGC_PAD9RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGC_PAD9RSEL_Enum; + +/* =========================================== GPIO PADREGC PAD9FNCSEL [11..13] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD9FNCSEL */ + GPIO_PADREGC_PAD9FNCSEL_M1SDAWIR3 = 0, /*!< M1SDAWIR3 : Configure as the IOMSTR1 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGC_PAD9FNCSEL_M1MISO = 1, /*!< M1MISO : Configure as the IOMSTR1 SPI MISO signal */ + GPIO_PADREGC_PAD9FNCSEL_NCE9 = 2, /*!< NCE9 : IOM/MSPI nCE group 9 */ + GPIO_PADREGC_PAD9FNCSEL_GPIO9 = 3, /*!< GPIO9 : Configure as GPIO9 */ + GPIO_PADREGC_PAD9FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD data I/O connection */ + GPIO_PADREGC_PAD9FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as UART1 RX input signal */ +} GPIO_PADREGC_PAD9FNCSEL_Enum; + +/* ============================================ GPIO PADREGC PAD9STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD9STRNG */ + GPIO_PADREGC_PAD9STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD9STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD9STRNG_Enum; + +/* ============================================= GPIO PADREGC PAD9INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD9INPEN */ + GPIO_PADREGC_PAD9INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD9INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD9INPEN_Enum; + +/* ============================================= GPIO PADREGC PAD9PULL [8..8] ============================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD9PULL */ + GPIO_PADREGC_PAD9PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD9PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD9PULL_Enum; + +/* ============================================= GPIO PADREGC PAD8RSEL [6..7] ============================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD8RSEL */ + GPIO_PADREGC_PAD8RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGC_PAD8RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGC_PAD8RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGC_PAD8RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGC_PAD8RSEL_Enum; + +/* ============================================ GPIO PADREGC PAD8FNCSEL [3..5] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD8FNCSEL */ + GPIO_PADREGC_PAD8FNCSEL_M1SCL = 0, /*!< M1SCL : Configure as the IOMSTR1 I2C SCL signal */ + GPIO_PADREGC_PAD8FNCSEL_M1SCK = 1, /*!< M1SCK : Configure as the IOMSTR1 SPI SCK signal */ + GPIO_PADREGC_PAD8FNCSEL_NCE8 = 2, /*!< NCE8 : IOM/MSPI nCE group 8 */ + GPIO_PADREGC_PAD8FNCSEL_GPIO8 = 3, /*!< GPIO8 : Configure as GPIO8 */ + GPIO_PADREGC_PAD8FNCSEL_SCCLK = 4, /*!< SCCLK : SCARD serial clock output */ + GPIO_PADREGC_PAD8FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output signal */ +} GPIO_PADREGC_PAD8FNCSEL_Enum; + +/* ============================================= GPIO PADREGC PAD8STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD8STRNG */ + GPIO_PADREGC_PAD8STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD8STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD8STRNG_Enum; + +/* ============================================= GPIO PADREGC PAD8INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD8INPEN */ + GPIO_PADREGC_PAD8INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD8INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD8INPEN_Enum; + +/* ============================================= GPIO PADREGC PAD8PULL [0..0] ============================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD8PULL */ + GPIO_PADREGC_PAD8PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD8PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD8PULL_Enum; + +/* ======================================================== PADREGD ======================================================== */ +/* =========================================== GPIO PADREGD PAD15FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGD_PAD15FNCSEL */ + GPIO_PADREGD_PAD15FNCSEL_ADCD1N = 0, /*!< ADCD1N : Configure as the analog ADC differential pair 1 N input + signal */ + GPIO_PADREGD_PAD15FNCSEL_NCE15 = 1, /*!< NCE15 : IOM/MSPI nCE group 15 */ + GPIO_PADREGD_PAD15FNCSEL_UART1RX = 2, /*!< UART1RX : Configure as the UART1 RX signal */ + GPIO_PADREGD_PAD15FNCSEL_GPIO15 = 3, /*!< GPIO15 : Configure as GPIO15 */ + GPIO_PADREGD_PAD15FNCSEL_PDMDATA = 4, /*!< PDMDATA : PDM serial data input */ + GPIO_PADREGD_PAD15FNCSEL_EXTXT = 5, /*!< EXTXT : Configure as the external XTAL oscillator input */ + GPIO_PADREGD_PAD15FNCSEL_SWDIO = 6, /*!< SWDIO : Configure as an alternate port for the SWDIO I/O signal */ + GPIO_PADREGD_PAD15FNCSEL_SWO = 7, /*!< SWO : Configure as an SWO (Serial Wire Trace output) */ +} GPIO_PADREGD_PAD15FNCSEL_Enum; + +/* =========================================== GPIO PADREGD PAD15STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD15STRNG */ + GPIO_PADREGD_PAD15STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD15STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD15STRNG_Enum; + +/* =========================================== GPIO PADREGD PAD15INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD15INPEN */ + GPIO_PADREGD_PAD15INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD15INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD15INPEN_Enum; + +/* ============================================ GPIO PADREGD PAD15PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD15PULL */ + GPIO_PADREGD_PAD15PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD15PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD15PULL_Enum; + +/* =========================================== GPIO PADREGD PAD14FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGD_PAD14FNCSEL */ + GPIO_PADREGD_PAD14FNCSEL_ADCD1P = 0, /*!< ADCD1P : Configure as the analog ADC differential pair 1 P input + signal */ + GPIO_PADREGD_PAD14FNCSEL_NCE14 = 1, /*!< NCE14 : IOM/MSPI nCE group 14 */ + GPIO_PADREGD_PAD14FNCSEL_UART1TX = 2, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGD_PAD14FNCSEL_GPIO14 = 3, /*!< GPIO14 : Configure as GPIO14 */ + GPIO_PADREGD_PAD14FNCSEL_PDMCLK = 4, /*!< PDMCLK : PDM serial clock output */ + GPIO_PADREGD_PAD14FNCSEL_EXTHFS = 5, /*!< EXTHFS : Configure as the External HFRC oscillator input select */ + GPIO_PADREGD_PAD14FNCSEL_SWDCK = 6, /*!< SWDCK : Configure as the alternate input for the SWDCK input + signal */ + GPIO_PADREGD_PAD14FNCSEL_32kHzXT = 7, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */ +} GPIO_PADREGD_PAD14FNCSEL_Enum; + +/* =========================================== GPIO PADREGD PAD14STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD14STRNG */ + GPIO_PADREGD_PAD14STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD14STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD14STRNG_Enum; + +/* =========================================== GPIO PADREGD PAD14INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD14INPEN */ + GPIO_PADREGD_PAD14INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD14INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD14INPEN_Enum; + +/* ============================================ GPIO PADREGD PAD14PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD14PULL */ + GPIO_PADREGD_PAD14PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD14PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD14PULL_Enum; + +/* =========================================== GPIO PADREGD PAD13FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGD_PAD13FNCSEL */ + GPIO_PADREGD_PAD13FNCSEL_ADCD0PSE8 = 0, /*!< ADCD0PSE8 : Configure as the ADC Differential pair 0 P, or Single + Ended input 8 analog input signal. Determination of the + D0P vs SE8 usage is done when the particular channel is + selected within the ADC module */ + GPIO_PADREGD_PAD13FNCSEL_NCE13 = 1, /*!< NCE13 : IOM/MSPI nCE group 13 */ + GPIO_PADREGD_PAD13FNCSEL_CT2 = 2, /*!< CT2 : CTIMER connection 2 */ + GPIO_PADREGD_PAD13FNCSEL_GPIO13 = 3, /*!< GPIO13 : Configure as GPIO13 */ + GPIO_PADREGD_PAD13FNCSEL_I2SBCLK = 4, /*!< I2SBCLK : I2C interface bit clock */ + GPIO_PADREGD_PAD13FNCSEL_EXTHFB = 5, /*!< EXTHFB : Configure as the external HFRC oscillator input */ + GPIO_PADREGD_PAD13FNCSEL_UA0RTS = 6, /*!< UA0RTS : Configure as the UART0 RTS signal output */ + GPIO_PADREGD_PAD13FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input signal */ +} GPIO_PADREGD_PAD13FNCSEL_Enum; + +/* =========================================== GPIO PADREGD PAD13STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD13STRNG */ + GPIO_PADREGD_PAD13STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD13STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD13STRNG_Enum; + +/* ============================================ GPIO PADREGD PAD13INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD13INPEN */ + GPIO_PADREGD_PAD13INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD13INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD13INPEN_Enum; + +/* ============================================= GPIO PADREGD PAD13PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD13PULL */ + GPIO_PADREGD_PAD13PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD13PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD13PULL_Enum; + +/* ============================================ GPIO PADREGD PAD12FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD12FNCSEL */ + GPIO_PADREGD_PAD12FNCSEL_ADCD0NSE9 = 0, /*!< ADCD0NSE9 : Configure as the ADC Differential pair 0 N, or Single + Ended input 9 analog input signal. Determination of the + D0N vs SE9 usage is done when the particular channel is + selected within the ADC module */ + GPIO_PADREGD_PAD12FNCSEL_NCE12 = 1, /*!< NCE12 : IOM/MSPI nCE group 12 */ + GPIO_PADREGD_PAD12FNCSEL_CT0 = 2, /*!< CT0 : CTIMER connection 0 */ + GPIO_PADREGD_PAD12FNCSEL_GPIO12 = 3, /*!< GPIO12 : Configure as GPIO12 */ + GPIO_PADREGD_PAD12FNCSEL_PDMCLK = 5, /*!< PDMCLK : PDM serial clock output */ + GPIO_PADREGD_PAD12FNCSEL_UA0CTS = 6, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGD_PAD12FNCSEL_UART1TX = 7, /*!< UART1TX : Configure as the UART1 TX output signal */ +} GPIO_PADREGD_PAD12FNCSEL_Enum; + +/* ============================================ GPIO PADREGD PAD12STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD12STRNG */ + GPIO_PADREGD_PAD12STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD12STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD12STRNG_Enum; + +/* ============================================ GPIO PADREGD PAD12INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD12INPEN */ + GPIO_PADREGD_PAD12INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD12INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD12INPEN_Enum; + +/* ============================================= GPIO PADREGD PAD12PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD12PULL */ + GPIO_PADREGD_PAD12PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD12PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD12PULL_Enum; + +/* ======================================================== PADREGE ======================================================== */ +/* =========================================== GPIO PADREGE PAD19FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGE_PAD19FNCSEL */ + GPIO_PADREGE_PAD19FNCSEL_CMPRF0 = 0, /*!< CMPRF0 : Configure as the analog comparator reference 0 signal */ + GPIO_PADREGE_PAD19FNCSEL_NCE19 = 1, /*!< NCE19 : IOM/MSPI nCE group 19 */ + GPIO_PADREGE_PAD19FNCSEL_CT6 = 2, /*!< CT6 : CTIMER conenction 6 */ + GPIO_PADREGE_PAD19FNCSEL_GPIO19 = 3, /*!< GPIO19 : Configure as GPIO19 */ + GPIO_PADREGE_PAD19FNCSEL_SCCLK = 4, /*!< SCCLK : SCARD serial clock */ + GPIO_PADREGE_PAD19FNCSEL_ANATEST1 = 5, /*!< ANATEST1 : Configure as the ANATEST1 I/O signal */ + GPIO_PADREGE_PAD19FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */ + GPIO_PADREGE_PAD19FNCSEL_I2SBCLK = 7, /*!< I2SBCLK : Configure as the PDM I2S bit clock input signal */ +} GPIO_PADREGE_PAD19FNCSEL_Enum; + +/* =========================================== GPIO PADREGE PAD19STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD19STRNG */ + GPIO_PADREGE_PAD19STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD19STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD19STRNG_Enum; + +/* =========================================== GPIO PADREGE PAD19INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD19INPEN */ + GPIO_PADREGE_PAD19INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD19INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD19INPEN_Enum; + +/* ============================================ GPIO PADREGE PAD19PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD19PULL */ + GPIO_PADREGE_PAD19PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD19PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD19PULL_Enum; + +/* =========================================== GPIO PADREGE PAD18FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGE_PAD18FNCSEL */ + GPIO_PADREGE_PAD18FNCSEL_CMPIN1 = 0, /*!< CMPIN1 : Configure as the analog comparator input 1 signal */ + GPIO_PADREGE_PAD18FNCSEL_NCE18 = 1, /*!< NCE18 : IOM/MSPI nCE group 18 */ + GPIO_PADREGE_PAD18FNCSEL_CT4 = 2, /*!< CT4 : CTIMER connection 4 */ + GPIO_PADREGE_PAD18FNCSEL_GPIO18 = 3, /*!< GPIO18 : Configure as GPIO18 */ + GPIO_PADREGE_PAD18FNCSEL_UA0RTS = 4, /*!< UA0RTS : Configure as UART0 RTS output signal */ + GPIO_PADREGE_PAD18FNCSEL_ANATEST2 = 5, /*!< ANATEST2 : Configure as ANATEST2 I/O signal */ + GPIO_PADREGE_PAD18FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as UART1 TX output signal */ + GPIO_PADREGE_PAD18FNCSEL_SCCIO = 7, /*!< SCCIO : SCARD data input/output connectin */ +} GPIO_PADREGE_PAD18FNCSEL_Enum; + +/* =========================================== GPIO PADREGE PAD18STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD18STRNG */ + GPIO_PADREGE_PAD18STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD18STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD18STRNG_Enum; + +/* =========================================== GPIO PADREGE PAD18INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD18INPEN */ + GPIO_PADREGE_PAD18INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD18INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD18INPEN_Enum; + +/* ============================================ GPIO PADREGE PAD18PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD18PULL */ + GPIO_PADREGE_PAD18PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD18PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD18PULL_Enum; + +/* =========================================== GPIO PADREGE PAD17FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGE_PAD17FNCSEL */ + GPIO_PADREGE_PAD17FNCSEL_CMPRF1 = 0, /*!< CMPRF1 : Configure as the analog comparator reference signal + 1 input signal */ + GPIO_PADREGE_PAD17FNCSEL_NCE17 = 1, /*!< NCE17 : IOM/MSPI nCE group 17 */ + GPIO_PADREGE_PAD17FNCSEL_TRIG1 = 2, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ + GPIO_PADREGE_PAD17FNCSEL_GPIO17 = 3, /*!< GPIO17 : Configure as GPIO17 */ + GPIO_PADREGE_PAD17FNCSEL_SCCCLK = 4, /*!< SCCCLK : SCARD serial clock output */ + GPIO_PADREGE_PAD17FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as UART0 RX input signal */ + GPIO_PADREGE_PAD17FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */ +} GPIO_PADREGE_PAD17FNCSEL_Enum; + +/* =========================================== GPIO PADREGE PAD17STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD17STRNG */ + GPIO_PADREGE_PAD17STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD17STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD17STRNG_Enum; + +/* ============================================ GPIO PADREGE PAD17INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD17INPEN */ + GPIO_PADREGE_PAD17INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD17INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD17INPEN_Enum; + +/* ============================================= GPIO PADREGE PAD17PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD17PULL */ + GPIO_PADREGE_PAD17PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD17PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD17PULL_Enum; + +/* ============================================ GPIO PADREGE PAD16FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD16FNCSEL */ + GPIO_PADREGE_PAD16FNCSEL_ADCSE0 = 0, /*!< ADCSE0 : Configure as the analog ADC single ended port 0 input + signal */ + GPIO_PADREGE_PAD16FNCSEL_NCE16 = 1, /*!< NCE16 : IOM/MSPI nCE group 16 */ + GPIO_PADREGE_PAD16FNCSEL_TRIG0 = 2, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ + GPIO_PADREGE_PAD16FNCSEL_GPIO16 = 3, /*!< GPIO16 : Configure as GPIO16 */ + GPIO_PADREGE_PAD16FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */ + GPIO_PADREGE_PAD16FNCSEL_CMPIN0 = 5, /*!< CMPIN0 : Configure as comparator input 0 signal */ + GPIO_PADREGE_PAD16FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGE_PAD16FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */ +} GPIO_PADREGE_PAD16FNCSEL_Enum; + +/* ============================================ GPIO PADREGE PAD16STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD16STRNG */ + GPIO_PADREGE_PAD16STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD16STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD16STRNG_Enum; + +/* ============================================ GPIO PADREGE PAD16INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD16INPEN */ + GPIO_PADREGE_PAD16INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD16INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD16INPEN_Enum; + +/* ============================================= GPIO PADREGE PAD16PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD16PULL */ + GPIO_PADREGE_PAD16PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD16PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD16PULL_Enum; + +/* ======================================================== PADREGF ======================================================== */ +/* =========================================== GPIO PADREGF PAD23FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGF_PAD23FNCSEL */ + GPIO_PADREGF_PAD23FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX signal */ + GPIO_PADREGF_PAD23FNCSEL_NCE23 = 1, /*!< NCE23 : IOM/MSPI nCE group 23 */ + GPIO_PADREGF_PAD23FNCSEL_CT14 = 2, /*!< CT14 : CTIMER connection 14 */ + GPIO_PADREGF_PAD23FNCSEL_GPIO23 = 3, /*!< GPIO23 : Configure as GPIO23 */ + GPIO_PADREGF_PAD23FNCSEL_I2SWCLK = 4, /*!< I2SWCLK : I2S word clock input */ + GPIO_PADREGF_PAD23FNCSEL_CMPOUT = 5, /*!< CMPOUT : Configure as voltage comparitor output */ + GPIO_PADREGF_PAD23FNCSEL_MSPI3 = 6, /*!< MSPI3 : MSPI data connection 3 */ + GPIO_PADREGF_PAD23FNCSEL_EXTXT = 7, /*!< EXTXT : External XTAL osacillatgor input */ +} GPIO_PADREGF_PAD23FNCSEL_Enum; + +/* =========================================== GPIO PADREGF PAD23STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD23STRNG */ + GPIO_PADREGF_PAD23STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD23STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD23STRNG_Enum; + +/* =========================================== GPIO PADREGF PAD23INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD23INPEN */ + GPIO_PADREGF_PAD23INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD23INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD23INPEN_Enum; + +/* ============================================ GPIO PADREGF PAD23PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD23PULL */ + GPIO_PADREGF_PAD23PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGF_PAD23PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGF_PAD23PULL_Enum; + +/* =========================================== GPIO PADREGF PAD22FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGF_PAD22FNCSEL */ + GPIO_PADREGF_PAD22FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX signal */ + GPIO_PADREGF_PAD22FNCSEL_NCE22 = 1, /*!< NCE22 : IOM/MSPI nCE group 22 */ + GPIO_PADREGF_PAD22FNCSEL_CT12 = 2, /*!< CT12 : CTIMER connection 12 */ + GPIO_PADREGF_PAD22FNCSEL_GPIO22 = 3, /*!< GPIO22 : Configure as GPIO22 */ + GPIO_PADREGF_PAD22FNCSEL_PDM_CLK = 4, /*!< PDM_CLK : Configure as the PDM CLK output */ + GPIO_PADREGF_PAD22FNCSEL_EXTLF = 5, /*!< EXTLF : External LFRC input */ + GPIO_PADREGF_PAD22FNCSEL_MSPI0 = 6, /*!< MSPI0 : MSPI data connection 0 */ + GPIO_PADREGF_PAD22FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ +} GPIO_PADREGF_PAD22FNCSEL_Enum; + +/* =========================================== GPIO PADREGF PAD22STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD22STRNG */ + GPIO_PADREGF_PAD22STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD22STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD22STRNG_Enum; + +/* =========================================== GPIO PADREGF PAD22INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD22INPEN */ + GPIO_PADREGF_PAD22INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD22INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD22INPEN_Enum; + +/* ============================================ GPIO PADREGF PAD22PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD22PULL */ + GPIO_PADREGF_PAD22PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGF_PAD22PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGF_PAD22PULL_Enum; + +/* =========================================== GPIO PADREGF PAD21FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGF_PAD21FNCSEL */ + GPIO_PADREGF_PAD21FNCSEL_SWDIO = 0, /*!< SWDIO : Configure as the serial wire debug data signal */ + GPIO_PADREGF_PAD21FNCSEL_NCE21 = 1, /*!< NCE21 : IOM/MSPI nCE group 21 */ + GPIO_PADREGF_PAD21FNCSEL_GPIO21 = 3, /*!< GPIO21 : Configure as GPIO21 */ + GPIO_PADREGF_PAD21FNCSEL_UART0RX = 4, /*!< UART0RX : Configure as UART0 RX input signal */ + GPIO_PADREGF_PAD21FNCSEL_UART1RX = 5, /*!< UART1RX : Configure as UART1 RX input signal */ + GPIO_PADREGF_PAD21FNCSEL_I2SBCLK = 6, /*!< I2SBCLK : I2S byte clock input */ + GPIO_PADREGF_PAD21FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */ +} GPIO_PADREGF_PAD21FNCSEL_Enum; + +/* =========================================== GPIO PADREGF PAD21STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD21STRNG */ + GPIO_PADREGF_PAD21STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD21STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD21STRNG_Enum; + +/* ============================================ GPIO PADREGF PAD21INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD21INPEN */ + GPIO_PADREGF_PAD21INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD21INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD21INPEN_Enum; + +/* ============================================= GPIO PADREGF PAD21PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD21PULL */ + GPIO_PADREGF_PAD21PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGF_PAD21PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGF_PAD21PULL_Enum; + +/* ============================================ GPIO PADREGF PAD20FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD20FNCSEL */ + GPIO_PADREGF_PAD20FNCSEL_SWDCK = 0, /*!< SWDCK : Configure as the serial wire debug clock signal */ + GPIO_PADREGF_PAD20FNCSEL_NCE20 = 1, /*!< NCE20 : IOM/MSPI nCE group 20 */ + GPIO_PADREGF_PAD20FNCSEL_GPIO20 = 3, /*!< GPIO20 : Configure as GPIO20 */ + GPIO_PADREGF_PAD20FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGF_PAD20FNCSEL_UART1TX = 5, /*!< UART1TX : Configure as UART1 TX output signal */ + GPIO_PADREGF_PAD20FNCSEL_I2SBCLK = 6, /*!< I2SBCLK : I2S byte clock input */ + GPIO_PADREGF_PAD20FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */ +} GPIO_PADREGF_PAD20FNCSEL_Enum; + +/* ============================================ GPIO PADREGF PAD20STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD20STRNG */ + GPIO_PADREGF_PAD20STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD20STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD20STRNG_Enum; + +/* ============================================ GPIO PADREGF PAD20INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD20INPEN */ + GPIO_PADREGF_PAD20INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD20INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD20INPEN_Enum; + +/* ============================================= GPIO PADREGF PAD20PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD20PULL */ + GPIO_PADREGF_PAD20PULL_DIS = 0, /*!< DIS : Pulldown disabled */ + GPIO_PADREGF_PAD20PULL_EN = 1, /*!< EN : Pulldown enabled */ +} GPIO_PADREGF_PAD20PULL_Enum; + +/* ======================================================== PADREGG ======================================================== */ +/* ============================================ GPIO PADREGG PAD27RSEL [30..31] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27RSEL */ + GPIO_PADREGG_PAD27RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGG_PAD27RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGG_PAD27RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGG_PAD27RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGG_PAD27RSEL_Enum; + +/* =========================================== GPIO PADREGG PAD27FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGG_PAD27FNCSEL */ + GPIO_PADREGG_PAD27FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as UART0 RX input signal */ + GPIO_PADREGG_PAD27FNCSEL_NCE27 = 1, /*!< NCE27 : IOM/MSPI nCE group 27 */ + GPIO_PADREGG_PAD27FNCSEL_CT5 = 2, /*!< CT5 : CTIMER connection 5 */ + GPIO_PADREGG_PAD27FNCSEL_GPIO27 = 3, /*!< GPIO27 : Configure as GPIO27 */ + GPIO_PADREGG_PAD27FNCSEL_M2SCL = 4, /*!< M2SCL : Configure as I2C clock I/O signal from IOMSTR2 */ + GPIO_PADREGG_PAD27FNCSEL_M2SCK = 5, /*!< M2SCK : Configure as SPI clock output signal from IOMSTR2 */ +} GPIO_PADREGG_PAD27FNCSEL_Enum; + +/* =========================================== GPIO PADREGG PAD27STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27STRNG */ + GPIO_PADREGG_PAD27STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD27STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD27STRNG_Enum; + +/* =========================================== GPIO PADREGG PAD27INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27INPEN */ + GPIO_PADREGG_PAD27INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD27INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD27INPEN_Enum; + +/* ============================================ GPIO PADREGG PAD27PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27PULL */ + GPIO_PADREGG_PAD27PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD27PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD27PULL_Enum; + +/* =========================================== GPIO PADREGG PAD26FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGG_PAD26FNCSEL */ + GPIO_PADREGG_PAD26FNCSEL_EXTHF = 0, /*!< EXTHF : Configure as the external HFRC oscillator input */ + GPIO_PADREGG_PAD26FNCSEL_NCE26 = 1, /*!< NCE26 : IOM/MSPI nCE group 26 */ + GPIO_PADREGG_PAD26FNCSEL_CT3 = 2, /*!< CT3 : CTIMER connection 3 */ + GPIO_PADREGG_PAD26FNCSEL_GPIO26 = 3, /*!< GPIO26 : Configure as GPIO26 */ + GPIO_PADREGG_PAD26FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */ + GPIO_PADREGG_PAD26FNCSEL_MSPI1 = 5, /*!< MSPI1 : MSPI data connection 1 */ + GPIO_PADREGG_PAD26FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGG_PAD26FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */ +} GPIO_PADREGG_PAD26FNCSEL_Enum; + +/* =========================================== GPIO PADREGG PAD26STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD26STRNG */ + GPIO_PADREGG_PAD26STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD26STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD26STRNG_Enum; + +/* =========================================== GPIO PADREGG PAD26INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD26INPEN */ + GPIO_PADREGG_PAD26INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD26INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD26INPEN_Enum; + +/* ============================================ GPIO PADREGG PAD26PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD26PULL */ + GPIO_PADREGG_PAD26PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD26PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD26PULL_Enum; + +/* ============================================ GPIO PADREGG PAD25RSEL [14..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD25RSEL */ + GPIO_PADREGG_PAD25RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGG_PAD25RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGG_PAD25RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGG_PAD25RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGG_PAD25RSEL_Enum; + +/* =========================================== GPIO PADREGG PAD25FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGG_PAD25FNCSEL */ + GPIO_PADREGG_PAD25FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as UART1 RX input signal */ + GPIO_PADREGG_PAD25FNCSEL_NCE25 = 1, /*!< NCE25 : IOM/MSPI nCE group 25 */ + GPIO_PADREGG_PAD25FNCSEL_CT1 = 2, /*!< CT1 : CTIMER connection 1 */ + GPIO_PADREGG_PAD25FNCSEL_GPIO25 = 3, /*!< GPIO25 : Configure as GPIO25 */ + GPIO_PADREGG_PAD25FNCSEL_M2SDAWIR3 = 4, /*!< M2SDAWIR3 : Configure as the IOMSTR2 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGG_PAD25FNCSEL_M2MISO = 5, /*!< M2MISO : Configure as the IOMSTR2 SPI MISO input signal */ +} GPIO_PADREGG_PAD25FNCSEL_Enum; + +/* =========================================== GPIO PADREGG PAD25STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD25STRNG */ + GPIO_PADREGG_PAD25STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD25STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD25STRNG_Enum; + +/* ============================================ GPIO PADREGG PAD25INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD25INPEN */ + GPIO_PADREGG_PAD25INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD25INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD25INPEN_Enum; + +/* ============================================= GPIO PADREGG PAD25PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD25PULL */ + GPIO_PADREGG_PAD25PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD25PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD25PULL_Enum; + +/* ============================================ GPIO PADREGG PAD24FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD24FNCSEL */ + GPIO_PADREGG_PAD24FNCSEL_UART1TX = 0, /*!< UART1TX : Configure as UART1 TX output signal */ + GPIO_PADREGG_PAD24FNCSEL_NCE24 = 1, /*!< NCE24 : IOM/MSPI nCE group 24 */ + GPIO_PADREGG_PAD24FNCSEL_MSPI8 = 2, /*!< MSPI8 : MSPI data connection 8 */ + GPIO_PADREGG_PAD24FNCSEL_GPIO24 = 3, /*!< GPIO24 : Configure as GPIO24 */ + GPIO_PADREGG_PAD24FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as UART0 CTS input signal */ + GPIO_PADREGG_PAD24FNCSEL_CT21 = 5, /*!< CT21 : CTIMER connection 21 */ + GPIO_PADREGG_PAD24FNCSEL_32kHzXT = 6, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */ + GPIO_PADREGG_PAD24FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ +} GPIO_PADREGG_PAD24FNCSEL_Enum; + +/* ============================================ GPIO PADREGG PAD24STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD24STRNG */ + GPIO_PADREGG_PAD24STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD24STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD24STRNG_Enum; + +/* ============================================ GPIO PADREGG PAD24INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD24INPEN */ + GPIO_PADREGG_PAD24INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD24INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD24INPEN_Enum; + +/* ============================================= GPIO PADREGG PAD24PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD24PULL */ + GPIO_PADREGG_PAD24PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD24PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD24PULL_Enum; + +/* ======================================================== PADREGH ======================================================== */ +/* =========================================== GPIO PADREGH PAD31FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGH_PAD31FNCSEL */ + GPIO_PADREGH_PAD31FNCSEL_ADCSE3 = 0, /*!< ADCSE3 : Configure as the analog input for ADC single ended + input 3 */ + GPIO_PADREGH_PAD31FNCSEL_NCE31 = 1, /*!< NCE31 : IOM/MSPI nCE group 31 */ + GPIO_PADREGH_PAD31FNCSEL_CT13 = 2, /*!< CT13 : CTIMER connection 13 */ + GPIO_PADREGH_PAD31FNCSEL_GPIO31 = 3, /*!< GPIO31 : Configure as GPIO31 */ + GPIO_PADREGH_PAD31FNCSEL_UART0RX = 4, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGH_PAD31FNCSEL_SCCCLK = 5, /*!< SCCCLK : SCARD serial clock output */ + GPIO_PADREGH_PAD31FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */ +} GPIO_PADREGH_PAD31FNCSEL_Enum; + +/* =========================================== GPIO PADREGH PAD31STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD31STRNG */ + GPIO_PADREGH_PAD31STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD31STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD31STRNG_Enum; + +/* =========================================== GPIO PADREGH PAD31INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD31INPEN */ + GPIO_PADREGH_PAD31INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD31INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD31INPEN_Enum; + +/* ============================================ GPIO PADREGH PAD31PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD31PULL */ + GPIO_PADREGH_PAD31PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD31PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD31PULL_Enum; + +/* =========================================== GPIO PADREGH PAD30FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGH_PAD30FNCSEL */ + GPIO_PADREGH_PAD30FNCSEL_ANATEST1 = 0, /*!< ANATEST1 : Configure as the ANATEST1 I/O signal */ + GPIO_PADREGH_PAD30FNCSEL_NCE30 = 1, /*!< NCE30 : IOM/MSPI nCE group 30 */ + GPIO_PADREGH_PAD30FNCSEL_CT11 = 2, /*!< CT11 : CTIMER connection 11 */ + GPIO_PADREGH_PAD30FNCSEL_GPIO30 = 3, /*!< GPIO30 : Configure as GPIO30 */ + GPIO_PADREGH_PAD30FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGH_PAD30FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as UART1 RTS output signal */ + GPIO_PADREGH_PAD30FNCSEL_I2S_DAT = 7, /*!< I2S_DAT : Configure as the PDM I2S Data output signal */ +} GPIO_PADREGH_PAD30FNCSEL_Enum; + +/* =========================================== GPIO PADREGH PAD30STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD30STRNG */ + GPIO_PADREGH_PAD30STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD30STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD30STRNG_Enum; + +/* =========================================== GPIO PADREGH PAD30INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD30INPEN */ + GPIO_PADREGH_PAD30INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD30INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD30INPEN_Enum; + +/* ============================================ GPIO PADREGH PAD30PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD30PULL */ + GPIO_PADREGH_PAD30PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD30PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD30PULL_Enum; + +/* =========================================== GPIO PADREGH PAD29FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGH_PAD29FNCSEL */ + GPIO_PADREGH_PAD29FNCSEL_ADCSE1 = 0, /*!< ADCSE1 : Configure as the analog input for ADC single ended + input 1 */ + GPIO_PADREGH_PAD29FNCSEL_NCE29 = 1, /*!< NCE29 : IOM/MSPI nCE group 29 */ + GPIO_PADREGH_PAD29FNCSEL_CT9 = 2, /*!< CT9 : CTIMER connection 9 */ + GPIO_PADREGH_PAD29FNCSEL_GPIO29 = 3, /*!< GPIO29 : Configure as GPIO29 */ + GPIO_PADREGH_PAD29FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGH_PAD29FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */ + GPIO_PADREGH_PAD29FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGH_PAD29FNCSEL_PDM_DATA = 7, /*!< PDM_DATA : Configure as PDM DATA input */ +} GPIO_PADREGH_PAD29FNCSEL_Enum; + +/* =========================================== GPIO PADREGH PAD29STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD29STRNG */ + GPIO_PADREGH_PAD29STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD29STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD29STRNG_Enum; + +/* ============================================ GPIO PADREGH PAD29INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD29INPEN */ + GPIO_PADREGH_PAD29INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD29INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD29INPEN_Enum; + +/* ============================================= GPIO PADREGH PAD29PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD29PULL */ + GPIO_PADREGH_PAD29PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD29PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD29PULL_Enum; + +/* ============================================ GPIO PADREGH PAD28FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD28FNCSEL */ + GPIO_PADREGH_PAD28FNCSEL_I2S_WCLK = 0, /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input */ + GPIO_PADREGH_PAD28FNCSEL_NCE28 = 1, /*!< NCE28 : IOM/MSPI nCE group 28 */ + GPIO_PADREGH_PAD28FNCSEL_CT7 = 2, /*!< CT7 : CTIMER connection 7 */ + GPIO_PADREGH_PAD28FNCSEL_GPIO28 = 3, /*!< GPIO28 : Configure as GPIO28 */ + GPIO_PADREGH_PAD28FNCSEL_M2MOSI = 5, /*!< M2MOSI : Configure as the IOMSTR2 SPI MOSI output signal */ + GPIO_PADREGH_PAD28FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as the UART0 TX output signal */ +} GPIO_PADREGH_PAD28FNCSEL_Enum; + +/* ============================================ GPIO PADREGH PAD28STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD28STRNG */ + GPIO_PADREGH_PAD28STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD28STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD28STRNG_Enum; + +/* ============================================ GPIO PADREGH PAD28INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD28INPEN */ + GPIO_PADREGH_PAD28INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD28INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD28INPEN_Enum; + +/* ============================================= GPIO PADREGH PAD28PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD28PULL */ + GPIO_PADREGH_PAD28PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD28PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD28PULL_Enum; + +/* ======================================================== PADREGI ======================================================== */ +/* =========================================== GPIO PADREGI PAD35FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGI_PAD35FNCSEL */ + GPIO_PADREGI_PAD35FNCSEL_ADCSE7 = 0, /*!< ADCSE7 : Configure as the analog input for ADC single ended + input 7 */ + GPIO_PADREGI_PAD35FNCSEL_NCE35 = 1, /*!< NCE35 : IOM/MSPI nCE group 35 */ + GPIO_PADREGI_PAD35FNCSEL_UART1TX = 2, /*!< UART1TX : Configure as the UART1 TX signal */ + GPIO_PADREGI_PAD35FNCSEL_GPIO35 = 3, /*!< GPIO35 : Configure as GPIO35 */ + GPIO_PADREGI_PAD35FNCSEL_I2SDAT = 4, /*!< I2SDAT : I2S serial data output */ + GPIO_PADREGI_PAD35FNCSEL_CT27 = 5, /*!< CT27 : CTIMER connection 27 */ + GPIO_PADREGI_PAD35FNCSEL_UA0RTS = 6, /*!< UA0RTS : Configure as the UART0 RTS output */ +} GPIO_PADREGI_PAD35FNCSEL_Enum; + +/* =========================================== GPIO PADREGI PAD35STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD35STRNG */ + GPIO_PADREGI_PAD35STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD35STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD35STRNG_Enum; + +/* =========================================== GPIO PADREGI PAD35INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD35INPEN */ + GPIO_PADREGI_PAD35INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD35INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD35INPEN_Enum; + +/* ============================================ GPIO PADREGI PAD35PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD35PULL */ + GPIO_PADREGI_PAD35PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD35PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD35PULL_Enum; + +/* =========================================== GPIO PADREGI PAD34FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGI_PAD34FNCSEL */ + GPIO_PADREGI_PAD34FNCSEL_ADCSE6 = 0, /*!< ADCSE6 : Configure as the analog input for ADC single ended + input 6 */ + GPIO_PADREGI_PAD34FNCSEL_NCE34 = 1, /*!< NCE34 : IOM/MSPI nCE group 34 */ + GPIO_PADREGI_PAD34FNCSEL_UA1RTS = 2, /*!< UA1RTS : Configure as the UART1 RTS output */ + GPIO_PADREGI_PAD34FNCSEL_GPIO34 = 3, /*!< GPIO34 : Configure as GPIO34 */ + GPIO_PADREGI_PAD34FNCSEL_CMPRF2 = 4, /*!< CMPRF2 : Configure as the analog comparator reference 2 signal */ + GPIO_PADREGI_PAD34FNCSEL_UA0RTS = 5, /*!< UA0RTS : Configure as the UART0 RTS output */ + GPIO_PADREGI_PAD34FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input */ + GPIO_PADREGI_PAD34FNCSEL_PDMDATA = 7, /*!< PDMDATA : PDM serial data input */ +} GPIO_PADREGI_PAD34FNCSEL_Enum; + +/* =========================================== GPIO PADREGI PAD34STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD34STRNG */ + GPIO_PADREGI_PAD34STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD34STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD34STRNG_Enum; + +/* =========================================== GPIO PADREGI PAD34INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD34INPEN */ + GPIO_PADREGI_PAD34INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD34INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD34INPEN_Enum; + +/* ============================================ GPIO PADREGI PAD34PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD34PULL */ + GPIO_PADREGI_PAD34PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD34PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD34PULL_Enum; + +/* =========================================== GPIO PADREGI PAD33FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGI_PAD33FNCSEL */ + GPIO_PADREGI_PAD33FNCSEL_ADCSE5 = 0, /*!< ADCSE5 : Configure as the analog ADC single ended port 5 input + signal */ + GPIO_PADREGI_PAD33FNCSEL_NCE33 = 1, /*!< NCE33 : IOM/MSPI nCE group 33 */ + GPIO_PADREGI_PAD33FNCSEL_32kHzXT = 2, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */ + GPIO_PADREGI_PAD33FNCSEL_GPIO33 = 3, /*!< GPIO33 : Configure as GPIO33 */ + GPIO_PADREGI_PAD33FNCSEL_UA0CTS = 5, /*!< UA0CTS : Configure as the UART0 CTS input */ + GPIO_PADREGI_PAD33FNCSEL_CT23 = 6, /*!< CT23 : CTIMER connection 23 */ + GPIO_PADREGI_PAD33FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ +} GPIO_PADREGI_PAD33FNCSEL_Enum; + +/* =========================================== GPIO PADREGI PAD33STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD33STRNG */ + GPIO_PADREGI_PAD33STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD33STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD33STRNG_Enum; + +/* ============================================ GPIO PADREGI PAD33INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD33INPEN */ + GPIO_PADREGI_PAD33INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD33INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD33INPEN_Enum; + +/* ============================================= GPIO PADREGI PAD33PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD33PULL */ + GPIO_PADREGI_PAD33PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD33PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD33PULL_Enum; + +/* ============================================ GPIO PADREGI PAD32FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD32FNCSEL */ + GPIO_PADREGI_PAD32FNCSEL_ADCSE4 = 0, /*!< ADCSE4 : Configure as the analog input for ADC single ended + input 4 */ + GPIO_PADREGI_PAD32FNCSEL_NCE32 = 1, /*!< NCE32 : IOM/MSPI nCE group 32 */ + GPIO_PADREGI_PAD32FNCSEL_CT15 = 2, /*!< CT15 : CTIMER connection 15 */ + GPIO_PADREGI_PAD32FNCSEL_GPIO32 = 3, /*!< GPIO32 : Configure as GPIO32 */ + GPIO_PADREGI_PAD32FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD serial data input/output */ + GPIO_PADREGI_PAD32FNCSEL_EXTLF = 5, /*!< EXTLF : External input to the LFRC oscillator */ + GPIO_PADREGI_PAD32FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as the UART1 CTS input */ +} GPIO_PADREGI_PAD32FNCSEL_Enum; + +/* ============================================ GPIO PADREGI PAD32STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD32STRNG */ + GPIO_PADREGI_PAD32STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD32STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD32STRNG_Enum; + +/* ============================================ GPIO PADREGI PAD32INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD32INPEN */ + GPIO_PADREGI_PAD32INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD32INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD32INPEN_Enum; + +/* ============================================= GPIO PADREGI PAD32PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD32PULL */ + GPIO_PADREGI_PAD32PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD32PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD32PULL_Enum; + +/* ======================================================== PADREGJ ======================================================== */ +/* ============================================ GPIO PADREGJ PAD39RSEL [30..31] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39RSEL */ + GPIO_PADREGJ_PAD39RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGJ_PAD39RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGJ_PAD39RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGJ_PAD39RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGJ_PAD39RSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD39FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGJ_PAD39FNCSEL */ + GPIO_PADREGJ_PAD39FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGJ_PAD39FNCSEL_UART1TX = 1, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGJ_PAD39FNCSEL_CT25 = 2, /*!< CT25 : CTIMER connection 25 */ + GPIO_PADREGJ_PAD39FNCSEL_GPIO39 = 3, /*!< GPIO39 : Configure as GPIO39 */ + GPIO_PADREGJ_PAD39FNCSEL_M4SCL = 4, /*!< M4SCL : Configure as the IOMSTR4 I2C SCL signal */ + GPIO_PADREGJ_PAD39FNCSEL_M4SCK = 5, /*!< M4SCK : Configure as the IOMSTR4 SPI SCK signal */ +} GPIO_PADREGJ_PAD39FNCSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD39STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39STRNG */ + GPIO_PADREGJ_PAD39STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD39STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD39STRNG_Enum; + +/* =========================================== GPIO PADREGJ PAD39INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39INPEN */ + GPIO_PADREGJ_PAD39INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD39INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD39INPEN_Enum; + +/* ============================================ GPIO PADREGJ PAD39PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39PULL */ + GPIO_PADREGJ_PAD39PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD39PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD39PULL_Enum; + +/* =========================================== GPIO PADREGJ PAD38FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGJ_PAD38FNCSEL */ + GPIO_PADREGJ_PAD38FNCSEL_TRIG3 = 0, /*!< TRIG3 : Configure as the ADC Trigger 3 signal */ + GPIO_PADREGJ_PAD38FNCSEL_NCE38 = 1, /*!< NCE38 : IOM/MSPI nCE group 38 */ + GPIO_PADREGJ_PAD38FNCSEL_UA0CTS = 2, /*!< UA0CTS : Configure as the UART0 CTS signal */ + GPIO_PADREGJ_PAD38FNCSEL_GPIO38 = 3, /*!< GPIO38 : Configure as GPIO38 */ + GPIO_PADREGJ_PAD38FNCSEL_M3MOSI = 5, /*!< M3MOSI : Configure as the IOMSTR3 SPI MOSI output signal */ + GPIO_PADREGJ_PAD38FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */ +} GPIO_PADREGJ_PAD38FNCSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD38STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD38STRNG */ + GPIO_PADREGJ_PAD38STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD38STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD38STRNG_Enum; + +/* =========================================== GPIO PADREGJ PAD38INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD38INPEN */ + GPIO_PADREGJ_PAD38INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD38INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD38INPEN_Enum; + +/* ============================================ GPIO PADREGJ PAD38PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD38PULL */ + GPIO_PADREGJ_PAD38PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD38PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD38PULL_Enum; + +/* =========================================== GPIO PADREGJ PAD37PWRDN [15..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD37PWRDN */ + GPIO_PADREGJ_PAD37PWRDN_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGJ_PAD37PWRDN_EN = 1, /*!< EN : Power switch enabled (switch to GND) */ +} GPIO_PADREGJ_PAD37PWRDN_Enum; + +/* =========================================== GPIO PADREGJ PAD37FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGJ_PAD37FNCSEL */ + GPIO_PADREGJ_PAD37FNCSEL_TRIG2 = 0, /*!< TRIG2 : Configure as the ADC Trigger 2 signal */ + GPIO_PADREGJ_PAD37FNCSEL_NCE37 = 1, /*!< NCE37 : IOM/MSPI nCE group 37 */ + GPIO_PADREGJ_PAD37FNCSEL_UA0RTS = 2, /*!< UA0RTS : Configure as the UART0 RTS output signal */ + GPIO_PADREGJ_PAD37FNCSEL_GPIO37 = 3, /*!< GPIO37 : Configure as GPIO37 */ + GPIO_PADREGJ_PAD37FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD serial data input/output */ + GPIO_PADREGJ_PAD37FNCSEL_UART1TX = 5, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGJ_PAD37FNCSEL_PDMCLK = 6, /*!< PDMCLK : Configure as the PDM CLK output signal */ + GPIO_PADREGJ_PAD37FNCSEL_CT29 = 7, /*!< CT29 : CTIMER connection 29 */ +} GPIO_PADREGJ_PAD37FNCSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD37STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD37STRNG */ + GPIO_PADREGJ_PAD37STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD37STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD37STRNG_Enum; + +/* ============================================ GPIO PADREGJ PAD37INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD37INPEN */ + GPIO_PADREGJ_PAD37INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD37INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD37INPEN_Enum; + +/* ============================================= GPIO PADREGJ PAD37PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD37PULL */ + GPIO_PADREGJ_PAD37PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD37PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD37PULL_Enum; + +/* ============================================ GPIO PADREGJ PAD36PWRUP [6..6] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36PWRUP */ + GPIO_PADREGJ_PAD36PWRUP_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGJ_PAD36PWRUP_EN = 1, /*!< EN : Power switch enabled (switched to VDD) */ +} GPIO_PADREGJ_PAD36PWRUP_Enum; + +/* ============================================ GPIO PADREGJ PAD36FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD36FNCSEL */ + GPIO_PADREGJ_PAD36FNCSEL_TRIG1 = 0, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ + GPIO_PADREGJ_PAD36FNCSEL_NCE36 = 1, /*!< NCE36 : IOM/MSPI nCE group 36 */ + GPIO_PADREGJ_PAD36FNCSEL_UART1RX = 2, /*!< UART1RX : Configure as the UART1 RX input signal */ + GPIO_PADREGJ_PAD36FNCSEL_GPIO36 = 3, /*!< GPIO36 : Configure as GPIO36 */ + GPIO_PADREGJ_PAD36FNCSEL_32kHzXT = 4, /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal */ + GPIO_PADREGJ_PAD36FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */ + GPIO_PADREGJ_PAD36FNCSEL_UA0CTS = 6, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGJ_PAD36FNCSEL_PDMDATA = 7, /*!< PDMDATA : PDM serial data input */ +} GPIO_PADREGJ_PAD36FNCSEL_Enum; + +/* ============================================ GPIO PADREGJ PAD36STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36STRNG */ + GPIO_PADREGJ_PAD36STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD36STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD36STRNG_Enum; + +/* ============================================ GPIO PADREGJ PAD36INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36INPEN */ + GPIO_PADREGJ_PAD36INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD36INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD36INPEN_Enum; + +/* ============================================= GPIO PADREGJ PAD36PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36PULL */ + GPIO_PADREGJ_PAD36PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD36PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD36PULL_Enum; + +/* ======================================================== PADREGK ======================================================== */ +/* ============================================ GPIO PADREGK PAD43RSEL [30..31] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43RSEL */ + GPIO_PADREGK_PAD43RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGK_PAD43RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGK_PAD43RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGK_PAD43RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGK_PAD43RSEL_Enum; + +/* =========================================== GPIO PADREGK PAD43FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGK_PAD43FNCSEL */ + GPIO_PADREGK_PAD43FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as the UART1 RX input signal */ + GPIO_PADREGK_PAD43FNCSEL_NCE43 = 1, /*!< NCE43 : IOM/MSPI nCE group 43 */ + GPIO_PADREGK_PAD43FNCSEL_CT18 = 2, /*!< CT18 : CTIMER connection 18 */ + GPIO_PADREGK_PAD43FNCSEL_GPIO43 = 3, /*!< GPIO43 : Configure as GPIO43 */ + GPIO_PADREGK_PAD43FNCSEL_M3SDAWIR3 = 4, /*!< M3SDAWIR3 : Configure as the IOMSTR3 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGK_PAD43FNCSEL_M3MISO = 5, /*!< M3MISO : Configure as the IOMSTR3 SPI MISO signal */ +} GPIO_PADREGK_PAD43FNCSEL_Enum; + +/* =========================================== GPIO PADREGK PAD43STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43STRNG */ + GPIO_PADREGK_PAD43STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD43STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD43STRNG_Enum; + +/* =========================================== GPIO PADREGK PAD43INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43INPEN */ + GPIO_PADREGK_PAD43INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD43INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD43INPEN_Enum; + +/* ============================================ GPIO PADREGK PAD43PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43PULL */ + GPIO_PADREGK_PAD43PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD43PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD43PULL_Enum; + +/* ============================================ GPIO PADREGK PAD42RSEL [22..23] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42RSEL */ + GPIO_PADREGK_PAD42RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGK_PAD42RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGK_PAD42RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGK_PAD42RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGK_PAD42RSEL_Enum; + +/* =========================================== GPIO PADREGK PAD42FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGK_PAD42FNCSEL */ + GPIO_PADREGK_PAD42FNCSEL_UART1TX = 0, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGK_PAD42FNCSEL_NCE42 = 1, /*!< NCE42 : IOM/MSPI nCE group 42 */ + GPIO_PADREGK_PAD42FNCSEL_CT16 = 2, /*!< CT16 : CTIMER connection 16 */ + GPIO_PADREGK_PAD42FNCSEL_GPIO42 = 3, /*!< GPIO42 : Configure as GPIO42 */ + GPIO_PADREGK_PAD42FNCSEL_M3SCL = 4, /*!< M3SCL : Configure as the IOMSTR3 I2C SCL clock I/O signal */ + GPIO_PADREGK_PAD42FNCSEL_M3SCK = 5, /*!< M3SCK : Configure as the IOMSTR3 SPI SCK output */ +} GPIO_PADREGK_PAD42FNCSEL_Enum; + +/* =========================================== GPIO PADREGK PAD42STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42STRNG */ + GPIO_PADREGK_PAD42STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD42STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD42STRNG_Enum; + +/* =========================================== GPIO PADREGK PAD42INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42INPEN */ + GPIO_PADREGK_PAD42INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD42INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD42INPEN_Enum; + +/* ============================================ GPIO PADREGK PAD42PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42PULL */ + GPIO_PADREGK_PAD42PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD42PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD42PULL_Enum; + +/* =========================================== GPIO PADREGK PAD41PWRDN [15..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD41PWRDN */ + GPIO_PADREGK_PAD41PWRDN_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGK_PAD41PWRDN_EN = 1, /*!< EN : Power switch enabled (Switch pad to VSS) */ +} GPIO_PADREGK_PAD41PWRDN_Enum; + +/* =========================================== GPIO PADREGK PAD41FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGK_PAD41FNCSEL */ + GPIO_PADREGK_PAD41FNCSEL_NCE41 = 0, /*!< NCE41 : IOM/MSPI nCE group 41 */ + GPIO_PADREGK_PAD41FNCSEL_SWO = 2, /*!< SWO : Configure as the serial wire debug SWO signal */ + GPIO_PADREGK_PAD41FNCSEL_GPIO41 = 3, /*!< GPIO41 : Configure as GPIO41 */ + GPIO_PADREGK_PAD41FNCSEL_I2SWCLK = 4, /*!< I2SWCLK : I2S word clock input */ + GPIO_PADREGK_PAD41FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as the UART1 RTS output signal */ + GPIO_PADREGK_PAD41FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGK_PAD41FNCSEL_UA0RTS = 7, /*!< UA0RTS : Configure as the UART0 RTS output signal */ +} GPIO_PADREGK_PAD41FNCSEL_Enum; + +/* =========================================== GPIO PADREGK PAD41STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD41STRNG */ + GPIO_PADREGK_PAD41STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD41STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD41STRNG_Enum; + +/* ============================================ GPIO PADREGK PAD41INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD41INPEN */ + GPIO_PADREGK_PAD41INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD41INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD41INPEN_Enum; + +/* ============================================= GPIO PADREGK PAD41PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD41PULL */ + GPIO_PADREGK_PAD41PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD41PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD41PULL_Enum; + +/* ============================================= GPIO PADREGK PAD40RSEL [6..7] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40RSEL */ + GPIO_PADREGK_PAD40RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGK_PAD40RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGK_PAD40RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGK_PAD40RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGK_PAD40RSEL_Enum; + +/* ============================================ GPIO PADREGK PAD40FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD40FNCSEL */ + GPIO_PADREGK_PAD40FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGK_PAD40FNCSEL_UART1RX = 1, /*!< UART1RX : Configure as the UART1 RX input signal */ + GPIO_PADREGK_PAD40FNCSEL_TRIG0 = 2, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ + GPIO_PADREGK_PAD40FNCSEL_GPIO40 = 3, /*!< GPIO40 : Configure as GPIO40 */ + GPIO_PADREGK_PAD40FNCSEL_M4SDAWIR3 = 4, /*!< M4SDAWIR3 : Configure as the IOMSTR4 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGK_PAD40FNCSEL_M4MISO = 5, /*!< M4MISO : Configure as the IOMSTR4 SPI MISO input signal */ +} GPIO_PADREGK_PAD40FNCSEL_Enum; + +/* ============================================ GPIO PADREGK PAD40STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40STRNG */ + GPIO_PADREGK_PAD40STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD40STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD40STRNG_Enum; + +/* ============================================ GPIO PADREGK PAD40INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40INPEN */ + GPIO_PADREGK_PAD40INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD40INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD40INPEN_Enum; + +/* ============================================= GPIO PADREGK PAD40PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40PULL */ + GPIO_PADREGK_PAD40PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD40PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD40PULL_Enum; + +/* ======================================================== PADREGL ======================================================== */ +/* =========================================== GPIO PADREGL PAD47FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGL_PAD47FNCSEL */ + GPIO_PADREGL_PAD47FNCSEL_32kHzXT = 0, /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal */ + GPIO_PADREGL_PAD47FNCSEL_NCE47 = 1, /*!< NCE47 : IOM/MSPI nCE group 47 */ + GPIO_PADREGL_PAD47FNCSEL_CT26 = 2, /*!< CT26 : CTIMER connection 26 */ + GPIO_PADREGL_PAD47FNCSEL_GPIO47 = 3, /*!< GPIO47 : Configure as GPIO47 */ + GPIO_PADREGL_PAD47FNCSEL_M5MOSI = 5, /*!< M5MOSI : Configure as the IOMSTR5 SPI MOSI output signal */ + GPIO_PADREGL_PAD47FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */ +} GPIO_PADREGL_PAD47FNCSEL_Enum; + +/* =========================================== GPIO PADREGL PAD47STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD47STRNG */ + GPIO_PADREGL_PAD47STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD47STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD47STRNG_Enum; + +/* =========================================== GPIO PADREGL PAD47INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD47INPEN */ + GPIO_PADREGL_PAD47INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD47INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD47INPEN_Enum; + +/* ============================================ GPIO PADREGL PAD47PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD47PULL */ + GPIO_PADREGL_PAD47PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD47PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD47PULL_Enum; + +/* =========================================== GPIO PADREGL PAD46FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGL_PAD46FNCSEL */ + GPIO_PADREGL_PAD46FNCSEL_32khz_XT = 0, /*!< 32khz_XT : Configure as the 32kHz output clock from the crystal */ + GPIO_PADREGL_PAD46FNCSEL_NCE46 = 1, /*!< NCE46 : IOM/MSPI nCE group 46 */ + GPIO_PADREGL_PAD46FNCSEL_CT24 = 2, /*!< CT24 : CTIMER connection 24 */ + GPIO_PADREGL_PAD46FNCSEL_GPIO46 = 3, /*!< GPIO46 : Configure as GPIO46 */ + GPIO_PADREGL_PAD46FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */ + GPIO_PADREGL_PAD46FNCSEL_PDMCLK = 5, /*!< PDMCLK : PDM serial clock output */ + GPIO_PADREGL_PAD46FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGL_PAD46FNCSEL_SWO = 7, /*!< SWO : Configure as the serial wire debug SWO signal */ +} GPIO_PADREGL_PAD46FNCSEL_Enum; + +/* =========================================== GPIO PADREGL PAD46STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD46STRNG */ + GPIO_PADREGL_PAD46STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD46STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD46STRNG_Enum; + +/* =========================================== GPIO PADREGL PAD46INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD46INPEN */ + GPIO_PADREGL_PAD46INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD46INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD46INPEN_Enum; + +/* ============================================ GPIO PADREGL PAD46PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD46PULL */ + GPIO_PADREGL_PAD46PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD46PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD46PULL_Enum; + +/* =========================================== GPIO PADREGL PAD45FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGL_PAD45FNCSEL */ + GPIO_PADREGL_PAD45FNCSEL_UA1CTS = 0, /*!< UA1CTS : Configure as the UART1 CTS input signal */ + GPIO_PADREGL_PAD45FNCSEL_NCE45 = 1, /*!< NCE45 : IOM/MSPI nCE group 45 */ + GPIO_PADREGL_PAD45FNCSEL_CT22 = 2, /*!< CT22 : CTIMER connection 22 */ + GPIO_PADREGL_PAD45FNCSEL_GPIO45 = 3, /*!< GPIO45 : Configure as GPIO45 */ + GPIO_PADREGL_PAD45FNCSEL_I2SDAT = 4, /*!< I2SDAT : I2S serial data output */ + GPIO_PADREGL_PAD45FNCSEL_PDMDATA = 5, /*!< PDMDATA : PDM serial data input */ + GPIO_PADREGL_PAD45FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the SPI channel 5 nCE signal from IOMSTR5 */ + GPIO_PADREGL_PAD45FNCSEL_SWO = 7, /*!< SWO : Configure as the serial wire debug SWO signal */ +} GPIO_PADREGL_PAD45FNCSEL_Enum; + +/* =========================================== GPIO PADREGL PAD45STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD45STRNG */ + GPIO_PADREGL_PAD45STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD45STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD45STRNG_Enum; + +/* ============================================ GPIO PADREGL PAD45INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD45INPEN */ + GPIO_PADREGL_PAD45INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD45INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD45INPEN_Enum; + +/* ============================================= GPIO PADREGL PAD45PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD45PULL */ + GPIO_PADREGL_PAD45PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD45PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD45PULL_Enum; + +/* ============================================ GPIO PADREGL PAD44FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD44FNCSEL */ + GPIO_PADREGL_PAD44FNCSEL_UA1RTS = 0, /*!< UA1RTS : Configure as the UART1 RTS output signal */ + GPIO_PADREGL_PAD44FNCSEL_NCE44 = 1, /*!< NCE44 : IOM/MSPI nCE group 44 */ + GPIO_PADREGL_PAD44FNCSEL_CT20 = 2, /*!< CT20 : CTIMER connection 20 */ + GPIO_PADREGL_PAD44FNCSEL_GPIO44 = 3, /*!< GPIO44 : Configure as GPIO44 */ + GPIO_PADREGL_PAD44FNCSEL_M4MOSI = 5, /*!< M4MOSI : Configure as the IOMSTR4 SPI MOSI signal */ + GPIO_PADREGL_PAD44FNCSEL_M5nCE6 = 6, /*!< M5nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR5 */ +} GPIO_PADREGL_PAD44FNCSEL_Enum; + +/* ============================================ GPIO PADREGL PAD44STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD44STRNG */ + GPIO_PADREGL_PAD44STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD44STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD44STRNG_Enum; + +/* ============================================ GPIO PADREGL PAD44INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD44INPEN */ + GPIO_PADREGL_PAD44INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD44INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD44INPEN_Enum; + +/* ============================================= GPIO PADREGL PAD44PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD44PULL */ + GPIO_PADREGL_PAD44PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD44PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD44PULL_Enum; + +/* ======================================================== PADREGM ======================================================== */ +/* ============================================ GPIO PADREGM PAD49RSEL [14..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGM_PAD49RSEL */ + GPIO_PADREGM_PAD49RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGM_PAD49RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGM_PAD49RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGM_PAD49RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGM_PAD49RSEL_Enum; + +/* =========================================== GPIO PADREGM PAD49FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGM_PAD49FNCSEL */ + GPIO_PADREGM_PAD49FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGM_PAD49FNCSEL_NCE49 = 1, /*!< NCE49 : IOM/MSPPI nCE group 49 */ + GPIO_PADREGM_PAD49FNCSEL_CT30 = 2, /*!< CT30 : CTIMER connection 30 */ + GPIO_PADREGM_PAD49FNCSEL_GPIO49 = 3, /*!< GPIO49 : Configure as GPIO49 */ + GPIO_PADREGM_PAD49FNCSEL_M5SDAWIR3 = 4, /*!< M5SDAWIR3 : Configure as the IOMSTR5 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGM_PAD49FNCSEL_M5MISO = 5, /*!< M5MISO : Configure as the IOMSTR5 SPI MISO input signal */ +} GPIO_PADREGM_PAD49FNCSEL_Enum; + +/* =========================================== GPIO PADREGM PAD49STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGM_PAD49STRNG */ + GPIO_PADREGM_PAD49STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGM_PAD49STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGM_PAD49STRNG_Enum; + +/* ============================================ GPIO PADREGM PAD49INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD49INPEN */ + GPIO_PADREGM_PAD49INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGM_PAD49INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGM_PAD49INPEN_Enum; + +/* ============================================= GPIO PADREGM PAD49PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD49PULL */ + GPIO_PADREGM_PAD49PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGM_PAD49PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGM_PAD49PULL_Enum; + +/* ============================================= GPIO PADREGM PAD48RSEL [6..7] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48RSEL */ + GPIO_PADREGM_PAD48RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGM_PAD48RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGM_PAD48RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGM_PAD48RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGM_PAD48RSEL_Enum; + +/* ============================================ GPIO PADREGM PAD48FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGM_PAD48FNCSEL */ + GPIO_PADREGM_PAD48FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGM_PAD48FNCSEL_NCE48 = 1, /*!< NCE48 : IOM/MSPI nCE group 48 */ + GPIO_PADREGM_PAD48FNCSEL_CT28 = 2, /*!< CT28 : CTIMER conenction 28 */ + GPIO_PADREGM_PAD48FNCSEL_GPIO48 = 3, /*!< GPIO48 : Configure as GPIO48 */ + GPIO_PADREGM_PAD48FNCSEL_M5SCL = 4, /*!< M5SCL : Configure as the IOMSTR5 I2C SCL clock I/O signal */ + GPIO_PADREGM_PAD48FNCSEL_M5SCK = 5, /*!< M5SCK : Configure as the IOMSTR5 SPI SCK output */ +} GPIO_PADREGM_PAD48FNCSEL_Enum; + +/* ============================================ GPIO PADREGM PAD48STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48STRNG */ + GPIO_PADREGM_PAD48STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGM_PAD48STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGM_PAD48STRNG_Enum; + +/* ============================================ GPIO PADREGM PAD48INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48INPEN */ + GPIO_PADREGM_PAD48INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGM_PAD48INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGM_PAD48INPEN_Enum; + +/* ============================================= GPIO PADREGM PAD48PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48PULL */ + GPIO_PADREGM_PAD48PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGM_PAD48PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGM_PAD48PULL_Enum; + +/* ========================================================= CFGA ========================================================== */ +/* ============================================= GPIO CFGA GPIO7INTD [31..31] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO7INTD */ + GPIO_CFGA_GPIO7INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x0 - nCE polarity active low */ + GPIO_CFGA_GPIO7INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x0 - nCE polarity active high */ +} GPIO_CFGA_GPIO7INTD_Enum; + +/* ============================================ GPIO CFGA GPIO7OUTCFG [29..30] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO7OUTCFG */ + GPIO_CFGA_GPIO7OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO7OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO7OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO7OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO7OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO7INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO7INCFG */ + GPIO_CFGA_GPIO7INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO7INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO7INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO6INTD [27..27] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO6INTD */ + GPIO_CFGA_GPIO6INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */ + GPIO_CFGA_GPIO6INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high + to low GPIO transition */ +} GPIO_CFGA_GPIO6INTD_Enum; + +/* ============================================ GPIO CFGA GPIO6OUTCFG [25..26] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO6OUTCFG */ + GPIO_CFGA_GPIO6OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO6OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO6OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO6OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO6OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO6INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO6INCFG */ + GPIO_CFGA_GPIO6INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO6INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO6INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO5INTD [23..23] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO5INTD */ + GPIO_CFGA_GPIO5INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */ + GPIO_CFGA_GPIO5INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high + to low GPIO transition */ +} GPIO_CFGA_GPIO5INTD_Enum; + +/* ============================================ GPIO CFGA GPIO5OUTCFG [21..22] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO5OUTCFG */ + GPIO_CFGA_GPIO5OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO5OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO5OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO5OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO5OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO5INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO5INCFG */ + GPIO_CFGA_GPIO5INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO5INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO5INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO4INTD [19..19] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO4INTD */ + GPIO_CFGA_GPIO4INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */ + GPIO_CFGA_GPIO4INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */ +} GPIO_CFGA_GPIO4INTD_Enum; + +/* ============================================ GPIO CFGA GPIO4OUTCFG [17..18] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO4OUTCFG */ + GPIO_CFGA_GPIO4OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO4OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO4OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO4OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO4OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO4INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO4INCFG */ + GPIO_CFGA_GPIO4INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO4INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO4INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO3INTD [15..15] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO3INTD */ + GPIO_CFGA_GPIO3INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */ + GPIO_CFGA_GPIO3INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */ +} GPIO_CFGA_GPIO3INTD_Enum; + +/* ============================================ GPIO CFGA GPIO3OUTCFG [13..14] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO3OUTCFG */ + GPIO_CFGA_GPIO3OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO3OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO3OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO3OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO3OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO3INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO3INCFG */ + GPIO_CFGA_GPIO3INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO3INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO3INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO2INTD [11..11] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO2INTD */ + GPIO_CFGA_GPIO2INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low */ + GPIO_CFGA_GPIO2INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high */ +} GPIO_CFGA_GPIO2INTD_Enum; + +/* ============================================= GPIO CFGA GPIO2OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO2OUTCFG */ + GPIO_CFGA_GPIO2OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO2OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO2OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO2OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO2OUTCFG_Enum; + +/* ============================================== GPIO CFGA GPIO2INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO2INCFG */ + GPIO_CFGA_GPIO2INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO2INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO2INCFG_Enum; + +/* ============================================== GPIO CFGA GPIO1INTD [7..7] =============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO1INTD */ + GPIO_CFGA_GPIO1INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low */ + GPIO_CFGA_GPIO1INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high */ +} GPIO_CFGA_GPIO1INTD_Enum; + +/* ============================================= GPIO CFGA GPIO1OUTCFG [5..6] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO1OUTCFG */ + GPIO_CFGA_GPIO1OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO1OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO1OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO1OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO1OUTCFG_Enum; + +/* ============================================== GPIO CFGA GPIO1INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO1INCFG */ + GPIO_CFGA_GPIO1INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO1INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO1INCFG_Enum; + +/* ============================================== GPIO CFGA GPIO0INTD [3..3] =============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO0INTD */ + GPIO_CFGA_GPIO0INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low */ + GPIO_CFGA_GPIO0INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high */ +} GPIO_CFGA_GPIO0INTD_Enum; + +/* ============================================= GPIO CFGA GPIO0OUTCFG [1..2] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO0OUTCFG */ + GPIO_CFGA_GPIO0OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO0OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO0OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO0OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO0OUTCFG_Enum; + +/* ============================================== GPIO CFGA GPIO0INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO0INCFG */ + GPIO_CFGA_GPIO0INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO0INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO0INCFG_Enum; + +/* ========================================================= CFGB ========================================================== */ +/* ============================================= GPIO CFGB GPIO15INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO15INTD */ + GPIO_CFGB_GPIO15INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGB_GPIO15INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGB_GPIO15INTD_Enum; + +/* ============================================ GPIO CFGB GPIO15OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO15OUTCFG */ + GPIO_CFGB_GPIO15OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO15OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO15OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO15OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO15OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO15INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO15INCFG */ + GPIO_CFGB_GPIO15INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO15INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO15INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO14INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO14INTD */ + GPIO_CFGB_GPIO14INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGB_GPIO14INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGB_GPIO14INTD_Enum; + +/* ============================================ GPIO CFGB GPIO14OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO14OUTCFG */ + GPIO_CFGB_GPIO14OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO14OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO14OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO14OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO14OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO14INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO14INCFG */ + GPIO_CFGB_GPIO14INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO14INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO14INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO13INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO13INTD */ + GPIO_CFGB_GPIO13INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGB_GPIO13INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGB_GPIO13INTD_Enum; + +/* ============================================ GPIO CFGB GPIO13OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO13OUTCFG */ + GPIO_CFGB_GPIO13OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO13OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO13OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO13OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO13OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO13INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO13INCFG */ + GPIO_CFGB_GPIO13INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO13INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO13INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO12INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO12INTD */ + GPIO_CFGB_GPIO12INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGB_GPIO12INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGB_GPIO12INTD_Enum; + +/* ============================================ GPIO CFGB GPIO12OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO12OUTCFG */ + GPIO_CFGB_GPIO12OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO12OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO12OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO12OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO12OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO12INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO12INCFG */ + GPIO_CFGB_GPIO12INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO12INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO12INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO11INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO11INTD */ + GPIO_CFGB_GPIO11INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGB_GPIO11INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGB_GPIO11INTD_Enum; + +/* ============================================ GPIO CFGB GPIO11OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO11OUTCFG */ + GPIO_CFGB_GPIO11OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO11OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO11OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO11OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO11OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO11INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO11INCFG */ + GPIO_CFGB_GPIO11INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO11INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO11INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO10INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO10INTD */ + GPIO_CFGB_GPIO10INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */ + GPIO_CFGB_GPIO10INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */ +} GPIO_CFGB_GPIO10INTD_Enum; + +/* ============================================ GPIO CFGB GPIO10OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO10OUTCFG */ + GPIO_CFGB_GPIO10OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO10OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO10OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO10OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO10OUTCFG_Enum; + +/* ============================================= GPIO CFGB GPIO10INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO10INCFG */ + GPIO_CFGB_GPIO10INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO10INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO10INCFG_Enum; + +/* ============================================== GPIO CFGB GPIO9INTD [7..7] =============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO9INTD */ + GPIO_CFGB_GPIO9INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */ + GPIO_CFGB_GPIO9INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */ +} GPIO_CFGB_GPIO9INTD_Enum; + +/* ============================================= GPIO CFGB GPIO9OUTCFG [5..6] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO9OUTCFG */ + GPIO_CFGB_GPIO9OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO9OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO9OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO9OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO9OUTCFG_Enum; + +/* ============================================== GPIO CFGB GPIO9INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO9INCFG */ + GPIO_CFGB_GPIO9INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO9INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO9INCFG_Enum; + +/* ============================================== GPIO CFGB GPIO8INTD [3..3] =============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO8INTD */ + GPIO_CFGB_GPIO8INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */ + GPIO_CFGB_GPIO8INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */ +} GPIO_CFGB_GPIO8INTD_Enum; + +/* ============================================= GPIO CFGB GPIO8OUTCFG [1..2] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO8OUTCFG */ + GPIO_CFGB_GPIO8OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO8OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO8OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO8OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO8OUTCFG_Enum; + +/* ============================================== GPIO CFGB GPIO8INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO8INCFG */ + GPIO_CFGB_GPIO8INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO8INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO8INCFG_Enum; + +/* ========================================================= CFGC ========================================================== */ +/* ============================================= GPIO CFGC GPIO23INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO23INTD */ + GPIO_CFGC_GPIO23INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO23INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO23INTD_Enum; + +/* ============================================ GPIO CFGC GPIO23OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO23OUTCFG */ + GPIO_CFGC_GPIO23OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO23OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO23OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO23OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO23OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO23INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO23INCFG */ + GPIO_CFGC_GPIO23INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO23INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO23INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO22INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO22INTD */ + GPIO_CFGC_GPIO22INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO22INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO22INTD_Enum; + +/* ============================================ GPIO CFGC GPIO22OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO22OUTCFG */ + GPIO_CFGC_GPIO22OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO22OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO22OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO22OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO22OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO22INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO22INCFG */ + GPIO_CFGC_GPIO22INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO22INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO22INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO21INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO21INTD */ + GPIO_CFGC_GPIO21INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO21INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO21INTD_Enum; + +/* ============================================ GPIO CFGC GPIO21OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO21OUTCFG */ + GPIO_CFGC_GPIO21OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO21OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO21OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO21OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO21OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO21INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO21INCFG */ + GPIO_CFGC_GPIO21INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO21INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO21INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO20INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO20INTD */ + GPIO_CFGC_GPIO20INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO20INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO20INTD_Enum; + +/* ============================================ GPIO CFGC GPIO20OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO20OUTCFG */ + GPIO_CFGC_GPIO20OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO20OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO20OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO20OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO20OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO20INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO20INCFG */ + GPIO_CFGC_GPIO20INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO20INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO20INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO19INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO19INTD */ + GPIO_CFGC_GPIO19INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO19INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO19INTD_Enum; + +/* ============================================ GPIO CFGC GPIO19OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO19OUTCFG */ + GPIO_CFGC_GPIO19OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO19OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO19OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO19OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO19OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO19INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO19INCFG */ + GPIO_CFGC_GPIO19INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO19INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO19INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO18INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO18INTD */ + GPIO_CFGC_GPIO18INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO18INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO18INTD_Enum; + +/* ============================================ GPIO CFGC GPIO18OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO18OUTCFG */ + GPIO_CFGC_GPIO18OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO18OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO18OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO18OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO18OUTCFG_Enum; + +/* ============================================= GPIO CFGC GPIO18INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO18INCFG */ + GPIO_CFGC_GPIO18INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO18INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO18INCFG_Enum; + +/* ============================================== GPIO CFGC GPIO17INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO17INTD */ + GPIO_CFGC_GPIO17INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO17INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO17INTD_Enum; + +/* ============================================= GPIO CFGC GPIO17OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO17OUTCFG */ + GPIO_CFGC_GPIO17OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO17OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO17OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO17OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO17OUTCFG_Enum; + +/* ============================================= GPIO CFGC GPIO17INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO17INCFG */ + GPIO_CFGC_GPIO17INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO17INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO17INCFG_Enum; + +/* ============================================== GPIO CFGC GPIO16INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO16INTD */ + GPIO_CFGC_GPIO16INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO16INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO16INTD_Enum; + +/* ============================================= GPIO CFGC GPIO16OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO16OUTCFG */ + GPIO_CFGC_GPIO16OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO16OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO16OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO16OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO16OUTCFG_Enum; + +/* ============================================= GPIO CFGC GPIO16INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO16INCFG */ + GPIO_CFGC_GPIO16INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO16INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO16INCFG_Enum; + +/* ========================================================= CFGD ========================================================== */ +/* ============================================= GPIO CFGD GPIO31INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO31INTD */ + GPIO_CFGD_GPIO31INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO31INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO31INTD_Enum; + +/* ============================================ GPIO CFGD GPIO31OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO31OUTCFG */ + GPIO_CFGD_GPIO31OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO31OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO31OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO31OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO31OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO31INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO31INCFG */ + GPIO_CFGD_GPIO31INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO31INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO31INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO30INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO30INTD */ + GPIO_CFGD_GPIO30INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO30INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO30INTD_Enum; + +/* ============================================ GPIO CFGD GPIO30OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO30OUTCFG */ + GPIO_CFGD_GPIO30OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO30OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO30OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO30OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO30OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO30INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO30INCFG */ + GPIO_CFGD_GPIO30INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO30INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO30INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO29INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO29INTD */ + GPIO_CFGD_GPIO29INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO29INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO29INTD_Enum; + +/* ============================================ GPIO CFGD GPIO29OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO29OUTCFG */ + GPIO_CFGD_GPIO29OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO29OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO29OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO29OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO29OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO29INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO29INCFG */ + GPIO_CFGD_GPIO29INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO29INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO29INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO28INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO28INTD */ + GPIO_CFGD_GPIO28INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO28INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO28INTD_Enum; + +/* ============================================ GPIO CFGD GPIO28OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO28OUTCFG */ + GPIO_CFGD_GPIO28OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO28OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO28OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO28OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO28OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO28INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO28INCFG */ + GPIO_CFGD_GPIO28INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO28INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO28INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO27INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO27INTD */ + GPIO_CFGD_GPIO27INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO27INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO27INTD_Enum; + +/* ============================================ GPIO CFGD GPIO27OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO27OUTCFG */ + GPIO_CFGD_GPIO27OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO27OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO27OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO27OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO27OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO27INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO27INCFG */ + GPIO_CFGD_GPIO27INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO27INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO27INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO26INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO26INTD */ + GPIO_CFGD_GPIO26INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO26INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO26INTD_Enum; + +/* ============================================ GPIO CFGD GPIO26OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO26OUTCFG */ + GPIO_CFGD_GPIO26OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO26OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO26OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO26OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO26OUTCFG_Enum; + +/* ============================================= GPIO CFGD GPIO26INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO26INCFG */ + GPIO_CFGD_GPIO26INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO26INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO26INCFG_Enum; + +/* ============================================== GPIO CFGD GPIO25INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO25INTD */ + GPIO_CFGD_GPIO25INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO25INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO25INTD_Enum; + +/* ============================================= GPIO CFGD GPIO25OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO25OUTCFG */ + GPIO_CFGD_GPIO25OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO25OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO25OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO25OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO25OUTCFG_Enum; + +/* ============================================= GPIO CFGD GPIO25INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO25INCFG */ + GPIO_CFGD_GPIO25INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO25INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO25INCFG_Enum; + +/* ============================================== GPIO CFGD GPIO24INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO24INTD */ + GPIO_CFGD_GPIO24INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO24INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO24INTD_Enum; + +/* ============================================= GPIO CFGD GPIO24OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO24OUTCFG */ + GPIO_CFGD_GPIO24OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO24OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO24OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO24OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO24OUTCFG_Enum; + +/* ============================================= GPIO CFGD GPIO24INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO24INCFG */ + GPIO_CFGD_GPIO24INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO24INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO24INCFG_Enum; + +/* ========================================================= CFGE ========================================================== */ +/* ============================================= GPIO CFGE GPIO39INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO39INTD */ + GPIO_CFGE_GPIO39INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */ + GPIO_CFGE_GPIO39INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high + to low GPIO transition */ +} GPIO_CFGE_GPIO39INTD_Enum; + +/* ============================================ GPIO CFGE GPIO39OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO39OUTCFG */ + GPIO_CFGE_GPIO39OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO39OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO39OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO39OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO39OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO39INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO39INCFG */ + GPIO_CFGE_GPIO39INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO39INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO39INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO38INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO38INTD */ + GPIO_CFGE_GPIO38INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO38INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO38INTD_Enum; + +/* ============================================ GPIO CFGE GPIO38OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO38OUTCFG */ + GPIO_CFGE_GPIO38OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO38OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO38OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO38OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO38OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO38INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO38INCFG */ + GPIO_CFGE_GPIO38INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO38INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO38INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO37INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO37INTD */ + GPIO_CFGE_GPIO37INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO37INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO37INTD_Enum; + +/* ============================================ GPIO CFGE GPIO37OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO37OUTCFG */ + GPIO_CFGE_GPIO37OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO37OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO37OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO37OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO37OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO37INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO37INCFG */ + GPIO_CFGE_GPIO37INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO37INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO37INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO36INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO36INTD */ + GPIO_CFGE_GPIO36INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO36INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO36INTD_Enum; + +/* ============================================ GPIO CFGE GPIO36OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO36OUTCFG */ + GPIO_CFGE_GPIO36OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO36OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO36OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO36OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO36OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO36INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO36INCFG */ + GPIO_CFGE_GPIO36INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO36INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO36INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO35INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO35INTD */ + GPIO_CFGE_GPIO35INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO35INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO35INTD_Enum; + +/* ============================================ GPIO CFGE GPIO35OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO35OUTCFG */ + GPIO_CFGE_GPIO35OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO35OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO35OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO35OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO35OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO35INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO35INCFG */ + GPIO_CFGE_GPIO35INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO35INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO35INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO34INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO34INTD */ + GPIO_CFGE_GPIO34INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO34INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO34INTD_Enum; + +/* ============================================ GPIO CFGE GPIO34OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO34OUTCFG */ + GPIO_CFGE_GPIO34OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO34OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO34OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO34OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO34OUTCFG_Enum; + +/* ============================================= GPIO CFGE GPIO34INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO34INCFG */ + GPIO_CFGE_GPIO34INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO34INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO34INCFG_Enum; + +/* ============================================== GPIO CFGE GPIO33INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO33INTD */ + GPIO_CFGE_GPIO33INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO33INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO33INTD_Enum; + +/* ============================================= GPIO CFGE GPIO33OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO33OUTCFG */ + GPIO_CFGE_GPIO33OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO33OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO33OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO33OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO33OUTCFG_Enum; + +/* ============================================= GPIO CFGE GPIO33INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO33INCFG */ + GPIO_CFGE_GPIO33INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO33INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO33INCFG_Enum; + +/* ============================================== GPIO CFGE GPIO32INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO32INTD */ + GPIO_CFGE_GPIO32INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO32INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO32INTD_Enum; + +/* ============================================= GPIO CFGE GPIO32OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO32OUTCFG */ + GPIO_CFGE_GPIO32OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO32OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO32OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO32OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO32OUTCFG_Enum; + +/* ============================================= GPIO CFGE GPIO32INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO32INCFG */ + GPIO_CFGE_GPIO32INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO32INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO32INCFG_Enum; + +/* ========================================================= CFGF ========================================================== */ +/* ============================================= GPIO CFGF GPIO47INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO47INTD */ + GPIO_CFGF_GPIO47INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO47INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO47INTD_Enum; + +/* ============================================ GPIO CFGF GPIO47OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO47OUTCFG */ + GPIO_CFGF_GPIO47OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO47OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO47OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO47OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO47OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO47INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO47INCFG */ + GPIO_CFGF_GPIO47INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO47INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO47INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO46INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO46INTD */ + GPIO_CFGF_GPIO46INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO46INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO46INTD_Enum; + +/* ============================================ GPIO CFGF GPIO46OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO46OUTCFG */ + GPIO_CFGF_GPIO46OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO46OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO46OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO46OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO46OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO46INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO46INCFG */ + GPIO_CFGF_GPIO46INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO46INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO46INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO45INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO45INTD */ + GPIO_CFGF_GPIO45INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO45INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO45INTD_Enum; + +/* ============================================ GPIO CFGF GPIO45OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO45OUTCFG */ + GPIO_CFGF_GPIO45OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO45OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO45OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO45OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO45OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO45INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO45INCFG */ + GPIO_CFGF_GPIO45INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO45INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO45INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO44INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO44INTD */ + GPIO_CFGF_GPIO44INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO44INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO44INTD_Enum; + +/* ============================================ GPIO CFGF GPIO44OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO44OUTCFG */ + GPIO_CFGF_GPIO44OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO44OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO44OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO44OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO44OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO44INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO44INCFG */ + GPIO_CFGF_GPIO44INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO44INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO44INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO43INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO43INTD */ + GPIO_CFGF_GPIO43INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO43INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO43INTD_Enum; + +/* ============================================ GPIO CFGF GPIO43OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO43OUTCFG */ + GPIO_CFGF_GPIO43OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO43OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO43OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO43OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO43OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO43INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO43INCFG */ + GPIO_CFGF_GPIO43INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO43INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO43INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO42INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO42INTD */ + GPIO_CFGF_GPIO42INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO42INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO42INTD_Enum; + +/* ============================================ GPIO CFGF GPIO42OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO42OUTCFG */ + GPIO_CFGF_GPIO42OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO42OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO42OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO42OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO42OUTCFG_Enum; + +/* ============================================= GPIO CFGF GPIO42INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO42INCFG */ + GPIO_CFGF_GPIO42INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO42INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO42INCFG_Enum; + +/* ============================================== GPIO CFGF GPIO41INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO41INTD */ + GPIO_CFGF_GPIO41INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x0 - nCE polarity active low */ + GPIO_CFGF_GPIO41INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x0 - nCE polarity active high */ +} GPIO_CFGF_GPIO41INTD_Enum; + +/* ============================================= GPIO CFGF GPIO41OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO41OUTCFG */ + GPIO_CFGF_GPIO41OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO41OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO41OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO41OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO41OUTCFG_Enum; + +/* ============================================= GPIO CFGF GPIO41INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO41INCFG */ + GPIO_CFGF_GPIO41INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO41INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO41INCFG_Enum; + +/* ============================================== GPIO CFGF GPIO40INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO40INTD */ + GPIO_CFGF_GPIO40INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */ + GPIO_CFGF_GPIO40INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high + to low GPIO transition */ +} GPIO_CFGF_GPIO40INTD_Enum; + +/* ============================================= GPIO CFGF GPIO40OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO40OUTCFG */ + GPIO_CFGF_GPIO40OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO40OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO40OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO40OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO40OUTCFG_Enum; + +/* ============================================= GPIO CFGF GPIO40INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO40INCFG */ + GPIO_CFGF_GPIO40INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO40INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO40INCFG_Enum; + +/* ========================================================= CFGG ========================================================== */ +/* ============================================== GPIO CFGG GPIO49INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO49INTD */ + GPIO_CFGG_GPIO49INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGG_GPIO49INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGG_GPIO49INTD_Enum; + +/* ============================================= GPIO CFGG GPIO49OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGG_GPIO49OUTCFG */ + GPIO_CFGG_GPIO49OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGG_GPIO49OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGG_GPIO49OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGG_GPIO49OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGG_GPIO49OUTCFG_Enum; + +/* ============================================= GPIO CFGG GPIO49INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO49INCFG */ + GPIO_CFGG_GPIO49INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGG_GPIO49INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGG_GPIO49INCFG_Enum; + +/* ============================================== GPIO CFGG GPIO48INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO48INTD */ + GPIO_CFGG_GPIO48INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGG_GPIO48INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGG_GPIO48INTD_Enum; + +/* ============================================= GPIO CFGG GPIO48OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGG_GPIO48OUTCFG */ + GPIO_CFGG_GPIO48OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGG_GPIO48OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGG_GPIO48OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGG_GPIO48OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGG_GPIO48OUTCFG_Enum; + +/* ============================================= GPIO CFGG GPIO48INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO48INCFG */ + GPIO_CFGG_GPIO48INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGG_GPIO48INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGG_GPIO48INCFG_Enum; + +/* ======================================================== PADKEY ========================================================= */ +/* ============================================== GPIO PADKEY PADKEY [0..31] =============================================== */ +typedef enum { /*!< GPIO_PADKEY_PADKEY */ + GPIO_PADKEY_PADKEY_Key = 115, /*!< Key : Key */ +} GPIO_PADKEY_PADKEY_Enum; + +/* ========================================================== RDA ========================================================== */ +/* ========================================================== RDB ========================================================== */ +/* ========================================================== WTA ========================================================== */ +/* ========================================================== WTB ========================================================== */ +/* ========================================================= WTSA ========================================================== */ +/* ========================================================= WTSB ========================================================== */ +/* ========================================================= WTCA ========================================================== */ +/* ========================================================= WTCB ========================================================== */ +/* ========================================================== ENA ========================================================== */ +/* ========================================================== ENB ========================================================== */ +/* ========================================================= ENSA ========================================================== */ +/* ========================================================= ENSB ========================================================== */ +/* ========================================================= ENCA ========================================================== */ +/* ========================================================= ENCB ========================================================== */ +/* ======================================================== STMRCAP ======================================================== */ +/* ============================================= GPIO STMRCAP STPOL3 [30..30] ============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL3 */ + GPIO_STMRCAP_STPOL3_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL3_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL3_Enum; + +/* ============================================= GPIO STMRCAP STPOL2 [22..22] ============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL2 */ + GPIO_STMRCAP_STPOL2_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL2_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL2_Enum; + +/* ============================================= GPIO STMRCAP STPOL1 [14..14] ============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL1 */ + GPIO_STMRCAP_STPOL1_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL1_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL1_Enum; + +/* ============================================== GPIO STMRCAP STPOL0 [6..6] =============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL0 */ + GPIO_STMRCAP_STPOL0_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL0_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL0_Enum; + +/* ======================================================== IOM0IRQ ======================================================== */ +/* ======================================================== IOM1IRQ ======================================================== */ +/* ======================================================== IOM2IRQ ======================================================== */ +/* ======================================================== IOM3IRQ ======================================================== */ +/* ======================================================== IOM4IRQ ======================================================== */ +/* ======================================================== IOM5IRQ ======================================================== */ +/* ======================================================= BLEIFIRQ ======================================================== */ +/* ======================================================== GPIOOBS ======================================================== */ +/* ====================================================== ALTPADCFGA ======================================================= */ +/* =========================================== GPIO ALTPADCFGA PAD3_SR [28..28] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD3_SR */ + GPIO_ALTPADCFGA_PAD3_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD3_SR_Enum; + +/* =========================================== GPIO ALTPADCFGA PAD2_SR [20..20] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD2_SR */ + GPIO_ALTPADCFGA_PAD2_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD2_SR_Enum; + +/* =========================================== GPIO ALTPADCFGA PAD1_SR [12..12] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD1_SR */ + GPIO_ALTPADCFGA_PAD1_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD1_SR_Enum; + +/* ============================================ GPIO ALTPADCFGA PAD0_SR [4..4] ============================================= */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD0_SR */ + GPIO_ALTPADCFGA_PAD0_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD0_SR_Enum; + +/* ====================================================== ALTPADCFGB ======================================================= */ +/* =========================================== GPIO ALTPADCFGB PAD7_SR [28..28] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD7_SR */ + GPIO_ALTPADCFGB_PAD7_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD7_SR_Enum; + +/* =========================================== GPIO ALTPADCFGB PAD6_SR [20..20] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD6_SR */ + GPIO_ALTPADCFGB_PAD6_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD6_SR_Enum; + +/* =========================================== GPIO ALTPADCFGB PAD5_SR [12..12] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD5_SR */ + GPIO_ALTPADCFGB_PAD5_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD5_SR_Enum; + +/* ============================================ GPIO ALTPADCFGB PAD4_SR [4..4] ============================================= */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD4_SR */ + GPIO_ALTPADCFGB_PAD4_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD4_SR_Enum; + +/* ====================================================== ALTPADCFGC ======================================================= */ +/* =========================================== GPIO ALTPADCFGC PAD11_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD11_SR */ + GPIO_ALTPADCFGC_PAD11_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD11_SR_Enum; + +/* =========================================== GPIO ALTPADCFGC PAD10_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD10_SR */ + GPIO_ALTPADCFGC_PAD10_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD10_SR_Enum; + +/* =========================================== GPIO ALTPADCFGC PAD9_SR [12..12] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD9_SR */ + GPIO_ALTPADCFGC_PAD9_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD9_SR_Enum; + +/* ============================================ GPIO ALTPADCFGC PAD8_SR [4..4] ============================================= */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD8_SR */ + GPIO_ALTPADCFGC_PAD8_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD8_SR_Enum; + +/* ====================================================== ALTPADCFGD ======================================================= */ +/* =========================================== GPIO ALTPADCFGD PAD15_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD15_SR */ + GPIO_ALTPADCFGD_PAD15_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD15_SR_Enum; + +/* =========================================== GPIO ALTPADCFGD PAD14_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD14_SR */ + GPIO_ALTPADCFGD_PAD14_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD14_SR_Enum; + +/* =========================================== GPIO ALTPADCFGD PAD13_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD13_SR */ + GPIO_ALTPADCFGD_PAD13_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD13_SR_Enum; + +/* ============================================ GPIO ALTPADCFGD PAD12_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD12_SR */ + GPIO_ALTPADCFGD_PAD12_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD12_SR_Enum; + +/* ====================================================== ALTPADCFGE ======================================================= */ +/* =========================================== GPIO ALTPADCFGE PAD19_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD19_SR */ + GPIO_ALTPADCFGE_PAD19_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD19_SR_Enum; + +/* =========================================== GPIO ALTPADCFGE PAD18_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD18_SR */ + GPIO_ALTPADCFGE_PAD18_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD18_SR_Enum; + +/* =========================================== GPIO ALTPADCFGE PAD17_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD17_SR */ + GPIO_ALTPADCFGE_PAD17_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD17_SR_Enum; + +/* ============================================ GPIO ALTPADCFGE PAD16_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD16_SR */ + GPIO_ALTPADCFGE_PAD16_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD16_SR_Enum; + +/* ====================================================== ALTPADCFGF ======================================================= */ +/* =========================================== GPIO ALTPADCFGF PAD23_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD23_SR */ + GPIO_ALTPADCFGF_PAD23_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD23_SR_Enum; + +/* =========================================== GPIO ALTPADCFGF PAD22_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD22_SR */ + GPIO_ALTPADCFGF_PAD22_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD22_SR_Enum; + +/* =========================================== GPIO ALTPADCFGF PAD21_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD21_SR */ + GPIO_ALTPADCFGF_PAD21_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD21_SR_Enum; + +/* ============================================ GPIO ALTPADCFGF PAD20_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD20_SR */ + GPIO_ALTPADCFGF_PAD20_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD20_SR_Enum; + +/* ====================================================== ALTPADCFGG ======================================================= */ +/* =========================================== GPIO ALTPADCFGG PAD27_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD27_SR */ + GPIO_ALTPADCFGG_PAD27_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD27_SR_Enum; + +/* =========================================== GPIO ALTPADCFGG PAD26_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD26_SR */ + GPIO_ALTPADCFGG_PAD26_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD26_SR_Enum; + +/* =========================================== GPIO ALTPADCFGG PAD25_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD25_SR */ + GPIO_ALTPADCFGG_PAD25_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD25_SR_Enum; + +/* ============================================ GPIO ALTPADCFGG PAD24_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD24_SR */ + GPIO_ALTPADCFGG_PAD24_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD24_SR_Enum; + +/* ====================================================== ALTPADCFGH ======================================================= */ +/* =========================================== GPIO ALTPADCFGH PAD31_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD31_SR */ + GPIO_ALTPADCFGH_PAD31_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD31_SR_Enum; + +/* =========================================== GPIO ALTPADCFGH PAD30_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD30_SR */ + GPIO_ALTPADCFGH_PAD30_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD30_SR_Enum; + +/* =========================================== GPIO ALTPADCFGH PAD29_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD29_SR */ + GPIO_ALTPADCFGH_PAD29_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD29_SR_Enum; + +/* ============================================ GPIO ALTPADCFGH PAD28_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD28_SR */ + GPIO_ALTPADCFGH_PAD28_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD28_SR_Enum; + +/* ====================================================== ALTPADCFGI ======================================================= */ +/* =========================================== GPIO ALTPADCFGI PAD35_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD35_SR */ + GPIO_ALTPADCFGI_PAD35_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD35_SR_Enum; + +/* =========================================== GPIO ALTPADCFGI PAD34_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD34_SR */ + GPIO_ALTPADCFGI_PAD34_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD34_SR_Enum; + +/* =========================================== GPIO ALTPADCFGI PAD33_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD33_SR */ + GPIO_ALTPADCFGI_PAD33_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD33_SR_Enum; + +/* ============================================ GPIO ALTPADCFGI PAD32_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD32_SR */ + GPIO_ALTPADCFGI_PAD32_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD32_SR_Enum; + +/* ====================================================== ALTPADCFGJ ======================================================= */ +/* =========================================== GPIO ALTPADCFGJ PAD39_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD39_SR */ + GPIO_ALTPADCFGJ_PAD39_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD39_SR_Enum; + +/* =========================================== GPIO ALTPADCFGJ PAD38_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD38_SR */ + GPIO_ALTPADCFGJ_PAD38_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD38_SR_Enum; + +/* =========================================== GPIO ALTPADCFGJ PAD37_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD37_SR */ + GPIO_ALTPADCFGJ_PAD37_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD37_SR_Enum; + +/* ============================================ GPIO ALTPADCFGJ PAD36_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD36_SR */ + GPIO_ALTPADCFGJ_PAD36_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD36_SR_Enum; + +/* ====================================================== ALTPADCFGK ======================================================= */ +/* =========================================== GPIO ALTPADCFGK PAD43_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD43_SR */ + GPIO_ALTPADCFGK_PAD43_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD43_SR_Enum; + +/* =========================================== GPIO ALTPADCFGK PAD42_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD42_SR */ + GPIO_ALTPADCFGK_PAD42_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD42_SR_Enum; + +/* =========================================== GPIO ALTPADCFGK PAD41_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD41_SR */ + GPIO_ALTPADCFGK_PAD41_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD41_SR_Enum; + +/* ============================================ GPIO ALTPADCFGK PAD40_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD40_SR */ + GPIO_ALTPADCFGK_PAD40_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD40_SR_Enum; + +/* ====================================================== ALTPADCFGL ======================================================= */ +/* =========================================== GPIO ALTPADCFGL PAD47_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD47_SR */ + GPIO_ALTPADCFGL_PAD47_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD47_SR_Enum; + +/* =========================================== GPIO ALTPADCFGL PAD46_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD46_SR */ + GPIO_ALTPADCFGL_PAD46_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD46_SR_Enum; + +/* =========================================== GPIO ALTPADCFGL PAD45_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD45_SR */ + GPIO_ALTPADCFGL_PAD45_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD45_SR_Enum; + +/* ============================================ GPIO ALTPADCFGL PAD44_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD44_SR */ + GPIO_ALTPADCFGL_PAD44_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD44_SR_Enum; + +/* ====================================================== ALTPADCFGM ======================================================= */ +/* =========================================== GPIO ALTPADCFGM PAD49_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGM_PAD49_SR */ + GPIO_ALTPADCFGM_PAD49_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGM_PAD49_SR_Enum; + +/* ============================================ GPIO ALTPADCFGM PAD48_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGM_PAD48_SR */ + GPIO_ALTPADCFGM_PAD48_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGM_PAD48_SR_Enum; + +/* ========================================================= SCDET ========================================================= */ +/* ======================================================== CTENCFG ======================================================== */ +/* ============================================== GPIO CTENCFG EN31 [31..31] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN31 */ + GPIO_CTENCFG_EN31_DIS = 1, /*!< DIS : Disable CT31 for output */ + GPIO_CTENCFG_EN31_EN = 0, /*!< EN : Enable CT31 for output */ +} GPIO_CTENCFG_EN31_Enum; + +/* ============================================== GPIO CTENCFG EN30 [30..30] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN30 */ + GPIO_CTENCFG_EN30_DIS = 1, /*!< DIS : Disable CT30 for output */ + GPIO_CTENCFG_EN30_EN = 0, /*!< EN : Enable CT30 for output */ +} GPIO_CTENCFG_EN30_Enum; + +/* ============================================== GPIO CTENCFG EN29 [29..29] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN29 */ + GPIO_CTENCFG_EN29_DIS = 1, /*!< DIS : Disable CT29 for output */ + GPIO_CTENCFG_EN29_EN = 0, /*!< EN : Enable CT29 for output */ +} GPIO_CTENCFG_EN29_Enum; + +/* ============================================== GPIO CTENCFG EN28 [28..28] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN28 */ + GPIO_CTENCFG_EN28_DIS = 1, /*!< DIS : Disable CT28 for output */ + GPIO_CTENCFG_EN28_EN = 0, /*!< EN : Enable CT28 for output */ +} GPIO_CTENCFG_EN28_Enum; + +/* ============================================== GPIO CTENCFG EN27 [27..27] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN27 */ + GPIO_CTENCFG_EN27_DIS = 1, /*!< DIS : Disable CT27 for output */ + GPIO_CTENCFG_EN27_EN = 0, /*!< EN : Enable CT27 for output */ +} GPIO_CTENCFG_EN27_Enum; + +/* ============================================== GPIO CTENCFG EN26 [26..26] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN26 */ + GPIO_CTENCFG_EN26_DIS = 1, /*!< DIS : Disable CT26 for output */ + GPIO_CTENCFG_EN26_EN = 0, /*!< EN : Enable CT26 for output */ +} GPIO_CTENCFG_EN26_Enum; + +/* ============================================== GPIO CTENCFG EN25 [25..25] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN25 */ + GPIO_CTENCFG_EN25_DIS = 1, /*!< DIS : Disable CT25 for output */ + GPIO_CTENCFG_EN25_EN = 0, /*!< EN : Enable CT25 for output */ +} GPIO_CTENCFG_EN25_Enum; + +/* ============================================== GPIO CTENCFG EN24 [24..24] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN24 */ + GPIO_CTENCFG_EN24_DIS = 1, /*!< DIS : Disable CT24 for output */ + GPIO_CTENCFG_EN24_EN = 0, /*!< EN : Enable CT24 for output */ +} GPIO_CTENCFG_EN24_Enum; + +/* ============================================== GPIO CTENCFG EN23 [23..23] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN23 */ + GPIO_CTENCFG_EN23_DIS = 1, /*!< DIS : Disable CT23 for output */ + GPIO_CTENCFG_EN23_EN = 0, /*!< EN : Enable CT23 for output */ +} GPIO_CTENCFG_EN23_Enum; + +/* ============================================== GPIO CTENCFG EN22 [22..22] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN22 */ + GPIO_CTENCFG_EN22_DIS = 1, /*!< DIS : Disable CT22 for output */ + GPIO_CTENCFG_EN22_EN = 0, /*!< EN : Enable CT22 for output */ +} GPIO_CTENCFG_EN22_Enum; + +/* ============================================== GPIO CTENCFG EN21 [21..21] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN21 */ + GPIO_CTENCFG_EN21_DIS = 1, /*!< DIS : Disable CT21 for output */ + GPIO_CTENCFG_EN21_EN = 0, /*!< EN : Enable CT21 for output */ +} GPIO_CTENCFG_EN21_Enum; + +/* ============================================== GPIO CTENCFG EN20 [20..20] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN20 */ + GPIO_CTENCFG_EN20_DIS = 1, /*!< DIS : Disable CT20 for output */ + GPIO_CTENCFG_EN20_EN = 0, /*!< EN : Enable CT20 for output */ +} GPIO_CTENCFG_EN20_Enum; + +/* ============================================== GPIO CTENCFG EN19 [19..19] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN19 */ + GPIO_CTENCFG_EN19_DIS = 1, /*!< DIS : Disable CT19 for output */ + GPIO_CTENCFG_EN19_EN = 0, /*!< EN : Enable CT19 for output */ +} GPIO_CTENCFG_EN19_Enum; + +/* ============================================== GPIO CTENCFG EN18 [18..18] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN18 */ + GPIO_CTENCFG_EN18_DIS = 1, /*!< DIS : Disable CT18 for output */ + GPIO_CTENCFG_EN18_EN = 0, /*!< EN : Enable CT18 for output */ +} GPIO_CTENCFG_EN18_Enum; + +/* ============================================== GPIO CTENCFG EN17 [17..17] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN17 */ + GPIO_CTENCFG_EN17_DIS = 1, /*!< DIS : Disable CT17 for output */ + GPIO_CTENCFG_EN17_EN = 0, /*!< EN : Enable CT17 for output */ +} GPIO_CTENCFG_EN17_Enum; + +/* ============================================== GPIO CTENCFG EN16 [16..16] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN16 */ + GPIO_CTENCFG_EN16_DIS = 1, /*!< DIS : Disable CT16 for output */ + GPIO_CTENCFG_EN16_EN = 0, /*!< EN : Enable CT16 for output */ +} GPIO_CTENCFG_EN16_Enum; + +/* ============================================== GPIO CTENCFG EN15 [15..15] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN15 */ + GPIO_CTENCFG_EN15_DIS = 1, /*!< DIS : Disable CT15 for output */ + GPIO_CTENCFG_EN15_EN = 0, /*!< EN : Enable CT15 for output */ +} GPIO_CTENCFG_EN15_Enum; + +/* ============================================== GPIO CTENCFG EN14 [14..14] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN14 */ + GPIO_CTENCFG_EN14_DIS = 1, /*!< DIS : Disable CT14 for output */ + GPIO_CTENCFG_EN14_EN = 0, /*!< EN : Enable CT14 for output */ +} GPIO_CTENCFG_EN14_Enum; + +/* ============================================== GPIO CTENCFG EN13 [13..13] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN13 */ + GPIO_CTENCFG_EN13_DIS = 1, /*!< DIS : Disable CT13 for output */ + GPIO_CTENCFG_EN13_EN = 0, /*!< EN : Enable CT13 for output */ +} GPIO_CTENCFG_EN13_Enum; + +/* ============================================== GPIO CTENCFG EN12 [12..12] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN12 */ + GPIO_CTENCFG_EN12_DIS = 1, /*!< DIS : Disable CT12 for output */ + GPIO_CTENCFG_EN12_EN = 0, /*!< EN : Enable CT12 for output */ +} GPIO_CTENCFG_EN12_Enum; + +/* ============================================== GPIO CTENCFG EN11 [11..11] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN11 */ + GPIO_CTENCFG_EN11_DIS = 1, /*!< DIS : Disable CT11 for output */ + GPIO_CTENCFG_EN11_EN = 0, /*!< EN : Enable CT11 for output */ +} GPIO_CTENCFG_EN11_Enum; + +/* ============================================== GPIO CTENCFG EN10 [10..10] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN10 */ + GPIO_CTENCFG_EN10_DIS = 1, /*!< DIS : Disable CT10 for output */ + GPIO_CTENCFG_EN10_EN = 0, /*!< EN : Enable CT10 for output */ +} GPIO_CTENCFG_EN10_Enum; + +/* ================================================ GPIO CTENCFG EN9 [9..9] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN9 */ + GPIO_CTENCFG_EN9_DIS = 0, /*!< DIS : Disable CT9 for output */ +} GPIO_CTENCFG_EN9_Enum; + +/* ================================================ GPIO CTENCFG EN8 [8..8] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN8 */ + GPIO_CTENCFG_EN8_DIS = 1, /*!< DIS : Disable CT8 for output */ + GPIO_CTENCFG_EN8_EN = 0, /*!< EN : Enable CT8 for output */ +} GPIO_CTENCFG_EN8_Enum; + +/* ================================================ GPIO CTENCFG EN7 [7..7] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN7 */ + GPIO_CTENCFG_EN7_DIS = 1, /*!< DIS : Disable CT7 for output */ + GPIO_CTENCFG_EN7_EN = 0, /*!< EN : Enable CT7 for output */ +} GPIO_CTENCFG_EN7_Enum; + +/* ================================================ GPIO CTENCFG EN6 [6..6] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN6 */ + GPIO_CTENCFG_EN6_DIS = 1, /*!< DIS : Disable CT6 for output */ + GPIO_CTENCFG_EN6_EN = 0, /*!< EN : Enable CT6 for output */ +} GPIO_CTENCFG_EN6_Enum; + +/* ================================================ GPIO CTENCFG EN5 [5..5] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN5 */ + GPIO_CTENCFG_EN5_DIS = 1, /*!< DIS : Disable CT5 for output */ + GPIO_CTENCFG_EN5_EN = 0, /*!< EN : Enable CT5 for output */ +} GPIO_CTENCFG_EN5_Enum; + +/* ================================================ GPIO CTENCFG EN4 [4..4] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN4 */ + GPIO_CTENCFG_EN4_DIS = 1, /*!< DIS : Disable CT4 for output */ + GPIO_CTENCFG_EN4_EN = 0, /*!< EN : Enable CT4 for output */ +} GPIO_CTENCFG_EN4_Enum; + +/* ================================================ GPIO CTENCFG EN3 [3..3] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN3 */ + GPIO_CTENCFG_EN3_DIS = 1, /*!< DIS : Disable CT3 for output */ + GPIO_CTENCFG_EN3_EN = 0, /*!< EN : Enable CT3 for output */ +} GPIO_CTENCFG_EN3_Enum; + +/* ================================================ GPIO CTENCFG EN2 [2..2] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN2 */ + GPIO_CTENCFG_EN2_DIS = 1, /*!< DIS : Disable CT2 for output */ + GPIO_CTENCFG_EN2_EN = 0, /*!< EN : Enable CT2 for output */ +} GPIO_CTENCFG_EN2_Enum; + +/* ================================================ GPIO CTENCFG EN1 [1..1] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN1 */ + GPIO_CTENCFG_EN1_DIS = 1, /*!< DIS : Disable CT1 for output */ + GPIO_CTENCFG_EN1_EN = 0, /*!< EN : Enable CT1 for output */ +} GPIO_CTENCFG_EN1_Enum; + +/* ================================================ GPIO CTENCFG EN0 [0..0] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN0 */ + GPIO_CTENCFG_EN0_DIS = 1, /*!< DIS : Disable CT0 for output */ + GPIO_CTENCFG_EN0_EN = 0, /*!< EN : Enable CT0 for output */ +} GPIO_CTENCFG_EN0_Enum; + +/* ======================================================== INT0EN ========================================================= */ +/* ======================================================= INT0STAT ======================================================== */ +/* ======================================================== INT0CLR ======================================================== */ +/* ======================================================== INT0SET ======================================================== */ +/* ======================================================== INT1EN ========================================================= */ +/* ======================================================= INT1STAT ======================================================== */ +/* ======================================================== INT1CLR ======================================================== */ +/* ======================================================== INT1SET ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ IOM0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FIFO ========================================================== */ +/* ======================================================== FIFOPTR ======================================================== */ +/* ======================================================== FIFOTHR ======================================================== */ +/* ======================================================== FIFOPOP ======================================================== */ +/* ======================================================= FIFOPUSH ======================================================== */ +/* ======================================================= FIFOCTRL ======================================================== */ +/* ======================================================== FIFOLOC ======================================================== */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================== CLKCFG ========================================================= */ +/* ============================================== IOM0 CLKCFG DIVEN [12..12] =============================================== */ +typedef enum { /*!< IOM0_CLKCFG_DIVEN */ + IOM0_CLKCFG_DIVEN_DIS = 0, /*!< DIS : Disable TOTPER division. */ + IOM0_CLKCFG_DIVEN_EN = 1, /*!< EN : Enable TOTPER division. */ +} IOM0_CLKCFG_DIVEN_Enum; + +/* =============================================== IOM0 CLKCFG DIV3 [11..11] =============================================== */ +typedef enum { /*!< IOM0_CLKCFG_DIV3 */ + IOM0_CLKCFG_DIV3_DIS = 0, /*!< DIS : Select divide by 1. */ + IOM0_CLKCFG_DIV3_EN = 1, /*!< EN : Select divide by 3. */ +} IOM0_CLKCFG_DIV3_Enum; + +/* =============================================== IOM0 CLKCFG FSEL [8..10] ================================================ */ +typedef enum { /*!< IOM0_CLKCFG_FSEL */ + IOM0_CLKCFG_FSEL_MIN_PWR = 0, /*!< MIN_PWR : Selects the minimum power clock. This setting should + be used whenever the IOM is not active. */ + IOM0_CLKCFG_FSEL_HFRC = 1, /*!< HFRC : Selects the HFRC as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV8 = 4, /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV16 = 5, /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV32 = 6, /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV64 = 7, /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock. */ +} IOM0_CLKCFG_FSEL_Enum; + +/* ====================================================== SUBMODCTRL ======================================================= */ +/* =========================================== IOM0 SUBMODCTRL SMOD1TYPE [5..7] ============================================ */ +typedef enum { /*!< IOM0_SUBMODCTRL_SMOD1TYPE */ + IOM0_SUBMODCTRL_SMOD1TYPE_MSPI = 0, /*!< MSPI : SPI Master submodule */ + IOM0_SUBMODCTRL_SMOD1TYPE_I2C_MASTER = 1, /*!< I2C_MASTER : MI2C submodule */ + IOM0_SUBMODCTRL_SMOD1TYPE_SSPI = 2, /*!< SSPI : SPI Slave submodule */ + IOM0_SUBMODCTRL_SMOD1TYPE_SI2C = 3, /*!< SI2C : I2C Slave submodule */ + IOM0_SUBMODCTRL_SMOD1TYPE_NA = 7, /*!< NA : NOT INSTALLED */ +} IOM0_SUBMODCTRL_SMOD1TYPE_Enum; + +/* =========================================== IOM0 SUBMODCTRL SMOD0TYPE [1..3] ============================================ */ +typedef enum { /*!< IOM0_SUBMODCTRL_SMOD0TYPE */ + IOM0_SUBMODCTRL_SMOD0TYPE_SPI_MASTER = 0, /*!< SPI_MASTER : MSPI submodule */ + IOM0_SUBMODCTRL_SMOD0TYPE_I2C_MASTER = 1, /*!< I2C_MASTER : I2C Master submodule */ + IOM0_SUBMODCTRL_SMOD0TYPE_SSPI = 2, /*!< SSPI : SPI Slave submodule */ + IOM0_SUBMODCTRL_SMOD0TYPE_SI2C = 3, /*!< SI2C : I2C Slave submodule */ + IOM0_SUBMODCTRL_SMOD0TYPE_NA = 7, /*!< NA : NOT INSTALLED */ +} IOM0_SUBMODCTRL_SMOD0TYPE_Enum; + +/* ========================================================== CMD ========================================================== */ +/* ================================================== IOM0 CMD CMD [0..4] ================================================== */ +typedef enum { /*!< IOM0_CMD_CMD */ + IOM0_CMD_CMD_WRITE = 1, /*!< WRITE : Write command using count of offset bytes specified + in the OFFSETCNT field */ + IOM0_CMD_CMD_READ = 2, /*!< READ : Read command using count of offset bytes specified in + the OFFSETCNT field */ + IOM0_CMD_CMD_TMW = 3, /*!< TMW : SPI only. Test mode to do constant write operations. Useful + for debug and power measurements. Will continually send + data in OFFSET field */ + IOM0_CMD_CMD_TMR = 4, /*!< TMR : SPI Only. Test mode to do constant read operations. Useful + for debug and power measurements. Will continually read + data from external input */ +} IOM0_CMD_CMD_Enum; + +/* ========================================================== DCX ========================================================== */ +/* ================================================= IOM0 DCX DCXEN [4..4] ================================================= */ +typedef enum { /*!< IOM0_DCX_DCXEN */ + IOM0_DCX_DCXEN_EN = 1, /*!< EN : Enable DCX. */ + IOM0_DCX_DCXEN_DIS = 0, /*!< DIS : Disable DCX. */ +} IOM0_DCX_DCXEN_Enum; + +/* ======================================================= OFFSETHI ======================================================== */ +/* ======================================================== CMDSTAT ======================================================== */ +/* ============================================== IOM0 CMDSTAT CMDSTAT [5..7] ============================================== */ +typedef enum { /*!< IOM0_CMDSTAT_CMDSTAT */ + IOM0_CMDSTAT_CMDSTAT_ERR = 1, /*!< ERR : Error encountered with command */ + IOM0_CMDSTAT_CMDSTAT_ACTIVE = 2, /*!< ACTIVE : Actively processing command */ + IOM0_CMDSTAT_CMDSTAT_IDLE = 4, /*!< IDLE : Idle state, no active command, no error */ + IOM0_CMDSTAT_CMDSTAT_WAIT = 6, /*!< WAIT : Command in progress, but waiting on data from host */ +} IOM0_CMDSTAT_CMDSTAT_Enum; + +/* ======================================================= DMATRIGEN ======================================================= */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +/* ======================================================== DMACFG ========================================================= */ +/* ============================================== IOM0 DMACFG DPWROFF [9..9] =============================================== */ +typedef enum { /*!< IOM0_DMACFG_DPWROFF */ + IOM0_DMACFG_DPWROFF_DIS = 0, /*!< DIS : Power off disabled */ + IOM0_DMACFG_DPWROFF_EN = 1, /*!< EN : Power off enabled */ +} IOM0_DMACFG_DPWROFF_Enum; + +/* =============================================== IOM0 DMACFG DMAPRI [8..8] =============================================== */ +typedef enum { /*!< IOM0_DMACFG_DMAPRI */ + IOM0_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + IOM0_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} IOM0_DMACFG_DMAPRI_Enum; + +/* =============================================== IOM0 DMACFG DMADIR [1..1] =============================================== */ +typedef enum { /*!< IOM0_DMACFG_DMADIR */ + IOM0_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when + doing IOM read operations, ie reading data from external + devices. */ + IOM0_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. To be set when doing + IOM write operations, ie writing data to external devices. */ +} IOM0_DMACFG_DMADIR_Enum; + +/* =============================================== IOM0 DMACFG DMAEN [0..0] ================================================ */ +typedef enum { /*!< IOM0_DMACFG_DMAEN */ + IOM0_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ + IOM0_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ +} IOM0_DMACFG_DMAEN_Enum; + +/* ====================================================== DMATOTCOUNT ====================================================== */ +/* ====================================================== DMATARGADDR ====================================================== */ +/* ======================================================== DMASTAT ======================================================== */ +/* ========================================================= CQCFG ========================================================= */ +/* ================================================ IOM0 CQCFG CQPRI [1..1] ================================================ */ +typedef enum { /*!< IOM0_CQCFG_CQPRI */ + IOM0_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + IOM0_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} IOM0_CQCFG_CQPRI_Enum; + +/* ================================================ IOM0 CQCFG CQEN [0..0] ================================================= */ +typedef enum { /*!< IOM0_CQCFG_CQEN */ + IOM0_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */ + IOM0_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */ +} IOM0_CQCFG_CQEN_Enum; + +/* ======================================================== CQADDR ========================================================= */ +/* ======================================================== CQSTAT ========================================================= */ +/* ======================================================== CQFLAGS ======================================================== */ +/* ====================================================== CQSETCLEAR ======================================================= */ +/* ======================================================= CQPAUSEEN ======================================================= */ +/* ============================================= IOM0 CQPAUSEEN CQPEN [0..15] ============================================== */ +typedef enum { /*!< IOM0_CQPAUSEEN_CQPEN */ + IOM0_CQPAUSEEN_CQPEN_IDXEQ = 32768, /*!< IDXEQ : Pauses the command queue when the current index matches + the last index */ + IOM0_CQPAUSEEN_CQPEN_BLEXOREN = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with + SWFLAG4 is '1' */ + IOM0_CQPAUSEEN_CQPEN_IOMXOREN = 8192, /*!< IOMXOREN : Pause command queue when input IOM bit XORed with + SWFLAG3 is '1' */ + IOM0_CQPAUSEEN_CQPEN_GPIOXOREN = 4096, /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed + with SWFLAG2 is '1' */ + IOM0_CQPAUSEEN_CQPEN_MSPI1XNOREN = 2048, /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed + with SWFLAG1 is '1' */ + IOM0_CQPAUSEEN_CQPEN_MSPI0XNOREN = 1024, /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed + with SWFLAG0 is '1' */ + IOM0_CQPAUSEEN_CQPEN_MSPI1XOREN = 512, /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed + with SWFLAG1 is '1' */ + IOM0_CQPAUSEEN_CQPEN_MSPI0XOREN = 256, /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed + with SWFLAG0 is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7 = 128, /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7 + is '1'. */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6 = 64, /*!< SWFLAGEN6 : Pause the command queue when software flag bit 6 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5 = 32, /*!< SWFLAGEN5 : Pause the command queue when software flag bit 5 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN4 = 16, /*!< SWFLAGEN4 : Pause the command queue when software flag bit 4 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN3 = 8, /*!< SWFLAGEN3 : Pause the command queue when software flag bit 3 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN2 = 4, /*!< SWFLAGEN2 : Pause the command queue when software flag bit 2 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN1 = 2, /*!< SWFLAGEN1 : Pause the command queue when software flag bit 1 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN0 = 1, /*!< SWFLAGEN0 : Pause the command queue when software flag bit 0 + is '1' */ +} IOM0_CQPAUSEEN_CQPEN_Enum; + +/* ======================================================= CQCURIDX ======================================================== */ +/* ======================================================= CQENDIDX ======================================================== */ +/* ======================================================== STATUS ========================================================= */ +/* =============================================== IOM0 STATUS IDLEST [2..2] =============================================== */ +typedef enum { /*!< IOM0_STATUS_IDLEST */ + IOM0_STATUS_IDLEST_IDLE = 1, /*!< IDLE : The I/O state machine is in the idle state. */ +} IOM0_STATUS_IDLEST_Enum; + +/* =============================================== IOM0 STATUS CMDACT [1..1] =============================================== */ +typedef enum { /*!< IOM0_STATUS_CMDACT */ + IOM0_STATUS_CMDACT_ACTIVE = 1, /*!< ACTIVE : An I/O command is active. Indicates the active module + has an active command and is processing this. De-asserted + when the command is completed. */ +} IOM0_STATUS_CMDACT_Enum; + +/* ================================================ IOM0 STATUS ERR [0..0] ================================================= */ +typedef enum { /*!< IOM0_STATUS_ERR */ + IOM0_STATUS_ERR_ERROR = 1, /*!< ERROR : Bit has been deprecated and will always return 0. */ +} IOM0_STATUS_ERR_Enum; + +/* ======================================================== MSPICFG ======================================================== */ +/* ============================================= IOM0 MSPICFG SPILSB [23..23] ============================================== */ +typedef enum { /*!< IOM0_MSPICFG_SPILSB */ + IOM0_MSPICFG_SPILSB_MSB = 0, /*!< MSB : Send and receive MSB bit first */ + IOM0_MSPICFG_SPILSB_LSB = 1, /*!< LSB : Send and receive LSB bit first */ +} IOM0_MSPICFG_SPILSB_Enum; + +/* ============================================= IOM0 MSPICFG RDFCPOL [22..22] ============================================= */ +typedef enum { /*!< IOM0_MSPICFG_RDFCPOL */ + IOM0_MSPICFG_RDFCPOL_HIGH = 0, /*!< HIGH : Flow control signal high creates flow control. */ + IOM0_MSPICFG_RDFCPOL_LOW = 1, /*!< LOW : Flow control signal low creates flow control. */ +} IOM0_MSPICFG_RDFCPOL_Enum; + +/* ============================================= IOM0 MSPICFG WTFCPOL [21..21] ============================================= */ +typedef enum { /*!< IOM0_MSPICFG_WTFCPOL */ + IOM0_MSPICFG_WTFCPOL_HIGH = 0, /*!< HIGH : Flow control signal high(1) creates flow control and + byte transfers will stop until the flow control signal + goes low. */ + IOM0_MSPICFG_WTFCPOL_LOW = 1, /*!< LOW : Flow control signal low(0) creates flow control and byte + transfers will stop until the flow control signal goes + high(1). */ +} IOM0_MSPICFG_WTFCPOL_Enum; + +/* ============================================= IOM0 MSPICFG WTFCIRQ [20..20] ============================================= */ +typedef enum { /*!< IOM0_MSPICFG_WTFCIRQ */ + IOM0_MSPICFG_WTFCIRQ_MISO = 0, /*!< MISO : MISO is used as the write mode flow control signal. */ + IOM0_MSPICFG_WTFCIRQ_IRQ = 1, /*!< IRQ : IRQ is used as the write mode flow control signal. */ +} IOM0_MSPICFG_WTFCIRQ_Enum; + +/* ============================================= IOM0 MSPICFG MOSIINV [18..18] ============================================= */ +typedef enum { /*!< IOM0_MSPICFG_MOSIINV */ + IOM0_MSPICFG_MOSIINV_NORMAL = 0, /*!< NORMAL : MOSI is set to 0 in read mode and 1 in write mode. */ + IOM0_MSPICFG_MOSIINV_INVERT = 1, /*!< INVERT : MOSI is set to 1 in read mode and 0 in write mode. */ +} IOM0_MSPICFG_MOSIINV_Enum; + +/* ============================================== IOM0 MSPICFG RDFC [17..17] =============================================== */ +typedef enum { /*!< IOM0_MSPICFG_RDFC */ + IOM0_MSPICFG_RDFC_DIS = 0, /*!< DIS : Read mode flow control disabled. */ + IOM0_MSPICFG_RDFC_EN = 1, /*!< EN : Read mode flow control enabled. */ +} IOM0_MSPICFG_RDFC_Enum; + +/* ============================================== IOM0 MSPICFG WTFC [16..16] =============================================== */ +typedef enum { /*!< IOM0_MSPICFG_WTFC */ + IOM0_MSPICFG_WTFC_DIS = 0, /*!< DIS : Write mode flow control disabled. */ + IOM0_MSPICFG_WTFC_EN = 1, /*!< EN : Write mode flow control enabled. */ +} IOM0_MSPICFG_WTFC_Enum; + +/* =============================================== IOM0 MSPICFG SPHA [1..1] ================================================ */ +typedef enum { /*!< IOM0_MSPICFG_SPHA */ + IOM0_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0, /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge. */ + IOM0_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1, /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock + edge. */ +} IOM0_MSPICFG_SPHA_Enum; + +/* =============================================== IOM0 MSPICFG SPOL [0..0] ================================================ */ +typedef enum { /*!< IOM0_MSPICFG_SPOL */ + IOM0_MSPICFG_SPOL_CLK_BASE_0 = 0, /*!< CLK_BASE_0 : The base value of the clock is 0. */ + IOM0_MSPICFG_SPOL_CLK_BASE_1 = 1, /*!< CLK_BASE_1 : The base value of the clock is 1. */ +} IOM0_MSPICFG_SPOL_Enum; + +/* ======================================================== MI2CCFG ======================================================== */ +/* =============================================== IOM0 MI2CCFG ARBEN [2..2] =============================================== */ +typedef enum { /*!< IOM0_MI2CCFG_ARBEN */ + IOM0_MI2CCFG_ARBEN_ARBEN = 1, /*!< ARBEN : Enable multi-master bus arbitration support for this + i2c master */ + IOM0_MI2CCFG_ARBEN_ARBDIS = 0, /*!< ARBDIS : Disable multi-master bus arbitration support for this + i2c master */ +} IOM0_MI2CCFG_ARBEN_Enum; + +/* ============================================== IOM0 MI2CCFG I2CLSB [1..1] =============================================== */ +typedef enum { /*!< IOM0_MI2CCFG_I2CLSB */ + IOM0_MI2CCFG_I2CLSB_MSBFIRST = 0, /*!< MSBFIRST : Byte data is transmitted MSB first onto the bus/read + from the bus */ + IOM0_MI2CCFG_I2CLSB_LSBFIRST = 1, /*!< LSBFIRST : Byte data is transmitted LSB first onto the bus/read + from the bus */ +} IOM0_MI2CCFG_I2CLSB_Enum; + +/* ============================================== IOM0 MI2CCFG ADDRSZ [0..0] =============================================== */ +typedef enum { /*!< IOM0_MI2CCFG_ADDRSZ */ + IOM0_MI2CCFG_ADDRSZ_ADDRSZ7 = 0, /*!< ADDRSZ7 : Use 7b addressing for I2C master transactions */ + IOM0_MI2CCFG_ADDRSZ_ADDRSZ10 = 1, /*!< ADDRSZ10 : Use 10b addressing for I2C master transactions */ +} IOM0_MI2CCFG_ADDRSZ_Enum; + +/* ======================================================== DEVCFG ========================================================= */ +/* ======================================================== IOMDBG ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ IOSLAVE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FIFOPTR ======================================================== */ +/* ======================================================== FIFOCFG ======================================================== */ +/* ======================================================== FIFOTHR ======================================================== */ +/* ========================================================= FUPD ========================================================== */ +/* ======================================================== FIFOCTR ======================================================== */ +/* ======================================================== FIFOINC ======================================================== */ +/* ========================================================== CFG ========================================================== */ +/* ============================================== IOSLAVE CFG IFCEN [31..31] =============================================== */ +typedef enum { /*!< IOSLAVE_CFG_IFCEN */ + IOSLAVE_CFG_IFCEN_DIS = 0, /*!< DIS : Disable the IOSLAVE */ + IOSLAVE_CFG_IFCEN_EN = 1, /*!< EN : Enable the IOSLAVE */ +} IOSLAVE_CFG_IFCEN_Enum; + +/* ============================================== IOSLAVE CFG STARTRD [4..4] =============================================== */ +typedef enum { /*!< IOSLAVE_CFG_STARTRD */ + IOSLAVE_CFG_STARTRD_LATE = 0, /*!< LATE : Initiate I/O RAM read late in each transferred byte. */ + IOSLAVE_CFG_STARTRD_EARLY = 1, /*!< EARLY : Initiate I/O RAM read early in each transferred byte. */ +} IOSLAVE_CFG_STARTRD_Enum; + +/* ================================================ IOSLAVE CFG LSB [2..2] ================================================= */ +typedef enum { /*!< IOSLAVE_CFG_LSB */ + IOSLAVE_CFG_LSB_MSB_FIRST = 0, /*!< MSB_FIRST : Data is assumed to be sent and received with MSB + first. */ + IOSLAVE_CFG_LSB_LSB_FIRST = 1, /*!< LSB_FIRST : Data is assumed to be sent and received with LSB + first. */ +} IOSLAVE_CFG_LSB_Enum; + +/* ================================================ IOSLAVE CFG SPOL [1..1] ================================================ */ +typedef enum { /*!< IOSLAVE_CFG_SPOL */ + IOSLAVE_CFG_SPOL_SPI_MODES_0_3 = 0, /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3. */ + IOSLAVE_CFG_SPOL_SPI_MODES_1_2 = 1, /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2. */ +} IOSLAVE_CFG_SPOL_Enum; + +/* =============================================== IOSLAVE CFG IFCSEL [0..0] =============================================== */ +typedef enum { /*!< IOSLAVE_CFG_IFCSEL */ + IOSLAVE_CFG_IFCSEL_I2C = 0, /*!< I2C : Selects I2C interface for the IO Slave. */ + IOSLAVE_CFG_IFCSEL_SPI = 1, /*!< SPI : Selects SPI interface for the IO Slave. */ +} IOSLAVE_CFG_IFCSEL_Enum; + +/* ========================================================= PRENC ========================================================= */ +/* ======================================================= IOINTCTL ======================================================== */ +/* ======================================================== GENADD ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ====================================================== REGACCINTEN ====================================================== */ +/* ===================================================== REGACCINTSTAT ===================================================== */ +/* ===================================================== REGACCINTCLR ====================================================== */ +/* ===================================================== REGACCINTSET ====================================================== */ + + +/* =========================================================================================================================== */ +/* ================ MCUCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CHIPPN ========================================================= */ +/* ============================================ MCUCTRL CHIPPN PARTNUM [0..31] ============================================= */ +typedef enum { /*!< MCUCTRL_CHIPPN_PARTNUM */ + MCUCTRL_CHIPPN_PARTNUM_APOLLO3 = 100663296,/*!< APOLLO3 : Apollo3 Blue part number is 0x06xxxxxx. */ + MCUCTRL_CHIPPN_PARTNUM_APOLLO2 = 50331648,/*!< APOLLO2 : Apollo2 part number is 0x03xxxxxx. */ + MCUCTRL_CHIPPN_PARTNUM_APOLLO = 16777216,/*!< APOLLO : Apollo part number is 0x01xxxxxx. */ + MCUCTRL_CHIPPN_PARTNUM_PN_M = -16777216,/*!< PN_M : Mask for the part number field. */ + MCUCTRL_CHIPPN_PARTNUM_PN_S = 24, /*!< PN_S : Bit position for the part number field. */ + MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M = 15728640,/*!< FLASHSIZE_M : Mask for the FLASH_SIZE field.Values:0: 16KB1: + 32KB2: 64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 2MB */ + MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S = 20, /*!< FLASHSIZE_S : Bit position for the FLASH_SIZE field. */ + MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M = 983040,/*!< SRAMSIZE_M : Mask for the SRAM_SIZE field.Values:0: 16KB1: 32KB2: + 64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 384KB8: 768KB */ + MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S = 16, /*!< SRAMSIZE_S : Bit position for the SRAM_SIZE field. */ + MCUCTRL_CHIPPN_PARTNUM_REV_M = 65280, /*!< REV_M : Mask for the revision field. Bits [15:12] are major + rev, [11:8] are minor rev.Values:0: Major Rev A, Minor + Rev 01: Major Rev B, Minor Rev 1 */ + MCUCTRL_CHIPPN_PARTNUM_REV_S = 8, /*!< REV_S : Bit position for the revision field. */ + MCUCTRL_CHIPPN_PARTNUM_PKG_M = 192, /*!< PKG_M : Mask for the package field.Values:0: SIP1: QFN2: BGA3: + CSP */ + MCUCTRL_CHIPPN_PARTNUM_PKG_S = 6, /*!< PKG_S : Bit position for the package field. */ + MCUCTRL_CHIPPN_PARTNUM_PINS_M = 56, /*!< PINS_M : Mask for the pins field.Values:0: 25 pins1: 49 pins2: + 64 pins3: 81 pins4: 104 pins */ + MCUCTRL_CHIPPN_PARTNUM_PINS_S = 3, /*!< PINS_S : Bit position for the pins field. */ + MCUCTRL_CHIPPN_PARTNUM_TEMP_S = 1, /*!< TEMP_S : Bit position for the temperature field. */ + MCUCTRL_CHIPPN_PARTNUM_QUAL_S = 0, /*!< QUAL_S : Bit position for the qualified field. */ +} MCUCTRL_CHIPPN_PARTNUM_Enum; + +/* ======================================================== CHIPID0 ======================================================== */ +/* ============================================ MCUCTRL CHIPID0 CHIPID0 [0..31] ============================================ */ +typedef enum { /*!< MCUCTRL_CHIPID0_CHIPID0 */ + MCUCTRL_CHIPID0_CHIPID0_APOLLO3 = 0, /*!< APOLLO3 : Apollo3 Blue Plus CHIPID0. */ +} MCUCTRL_CHIPID0_CHIPID0_Enum; + +/* ======================================================== CHIPID1 ======================================================== */ +/* ============================================ MCUCTRL CHIPID1 CHIPID1 [0..31] ============================================ */ +typedef enum { /*!< MCUCTRL_CHIPID1_CHIPID1 */ + MCUCTRL_CHIPID1_CHIPID1_APOLLO3 = 0, /*!< APOLLO3 : Apollo3 Blue Plus CHIPID1. */ +} MCUCTRL_CHIPID1_CHIPID1_Enum; + +/* ======================================================== CHIPREV ======================================================== */ +/* ============================================= MCUCTRL CHIPREV REVMAJ [4..7] ============================================= */ +typedef enum { /*!< MCUCTRL_CHIPREV_REVMAJ */ + MCUCTRL_CHIPREV_REVMAJ_B = 2, /*!< B : Apollo3 Blue revision B */ + MCUCTRL_CHIPREV_REVMAJ_A = 1, /*!< A : Apollo3 Blue revision A */ +} MCUCTRL_CHIPREV_REVMAJ_Enum; + +/* ============================================= MCUCTRL CHIPREV REVMIN [0..3] ============================================= */ +typedef enum { /*!< MCUCTRL_CHIPREV_REVMIN */ + MCUCTRL_CHIPREV_REVMIN_REV1 = 2, /*!< REV1 : Apollo3 Blue minor rev 1. */ + MCUCTRL_CHIPREV_REVMIN_REV0 = 1, /*!< REV0 : Apollo3 Blue minor rev 0. Minor revision value, succeeding + minor revisions will increment from this value. */ +} MCUCTRL_CHIPREV_REVMIN_Enum; + +/* ======================================================= VENDORID ======================================================== */ +/* =========================================== MCUCTRL VENDORID VENDORID [0..31] =========================================== */ +typedef enum { /*!< MCUCTRL_VENDORID_VENDORID */ + MCUCTRL_VENDORID_VENDORID_AMBIQ = 1095582289,/*!< AMBIQ : Ambiq Vendor ID 'AMBQ' */ +} MCUCTRL_VENDORID_VENDORID_Enum; + +/* ========================================================== SKU ========================================================== */ +/* ===================================================== FEATUREENABLE ===================================================== */ +/* ======================================== MCUCTRL FEATUREENABLE BURSTAVAIL [6..6] ======================================== */ +typedef enum { /*!< MCUCTRL_FEATUREENABLE_BURSTAVAIL */ + MCUCTRL_FEATUREENABLE_BURSTAVAIL_AVAIL = 1, /*!< AVAIL : Burst functionality available */ + MCUCTRL_FEATUREENABLE_BURSTAVAIL_NOTAVAIL = 0,/*!< NOTAVAIL : Burst functionality not available */ +} MCUCTRL_FEATUREENABLE_BURSTAVAIL_Enum; + +/* ========================================= MCUCTRL FEATUREENABLE BURSTREQ [4..4] ========================================= */ +typedef enum { /*!< MCUCTRL_FEATUREENABLE_BURSTREQ */ + MCUCTRL_FEATUREENABLE_BURSTREQ_EN = 1, /*!< EN : Enable the Burst functionality */ + MCUCTRL_FEATUREENABLE_BURSTREQ_DIS = 0, /*!< DIS : Disable the Burst functionality */ +} MCUCTRL_FEATUREENABLE_BURSTREQ_Enum; + +/* ========================================= MCUCTRL FEATUREENABLE BLEAVAIL [2..2] ========================================= */ +typedef enum { /*!< MCUCTRL_FEATUREENABLE_BLEAVAIL */ + MCUCTRL_FEATUREENABLE_BLEAVAIL_AVAIL = 1, /*!< AVAIL : BLE functionality available */ + MCUCTRL_FEATUREENABLE_BLEAVAIL_NOTAVAIL = 0, /*!< NOTAVAIL : BLE functionality not available */ +} MCUCTRL_FEATUREENABLE_BLEAVAIL_Enum; + +/* ========================================== MCUCTRL FEATUREENABLE BLEREQ [0..0] ========================================== */ +typedef enum { /*!< MCUCTRL_FEATUREENABLE_BLEREQ */ + MCUCTRL_FEATUREENABLE_BLEREQ_EN = 1, /*!< EN : Enable the BLE functionality */ + MCUCTRL_FEATUREENABLE_BLEREQ_DIS = 0, /*!< DIS : Disable the BLE functionality */ +} MCUCTRL_FEATUREENABLE_BLEREQ_Enum; + +/* ======================================================= DEBUGGER ======================================================== */ +/* ======================================================== BODCTRL ======================================================== */ +/* ======================================================= ADCPWRDLY ======================================================= */ +/* ======================================================== ADCCAL ========================================================= */ +/* ========================================== MCUCTRL ADCCAL ADCCALIBRATED [1..1] ========================================== */ +typedef enum { /*!< MCUCTRL_ADCCAL_ADCCALIBRATED */ + MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE = 0, /*!< FALSE : ADC is not calibrated */ + MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE = 1, /*!< TRUE : ADC is calibrated */ +} MCUCTRL_ADCCAL_ADCCALIBRATED_Enum; + +/* =========================================== MCUCTRL ADCCAL CALONPWRUP [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_ADCCAL_CALONPWRUP */ + MCUCTRL_ADCCAL_CALONPWRUP_DIS = 0, /*!< DIS : Disable automatic calibration on initial power up */ + MCUCTRL_ADCCAL_CALONPWRUP_EN = 1, /*!< EN : Enable automatic calibration on initial power up */ +} MCUCTRL_ADCCAL_CALONPWRUP_Enum; + +/* ====================================================== ADCBATTLOAD ====================================================== */ +/* ========================================== MCUCTRL ADCBATTLOAD BATTLOAD [0..0] ========================================== */ +typedef enum { /*!< MCUCTRL_ADCBATTLOAD_BATTLOAD */ + MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS = 0, /*!< DIS : Battery load is disconnected */ + MCUCTRL_ADCBATTLOAD_BATTLOAD_EN = 1, /*!< EN : Battery load is enabled */ +} MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum; + +/* ======================================================== ADCTRIM ======================================================== */ +/* ====================================================== ADCREFCOMP ======================================================= */ +/* ======================================================= XTALCTRL ======================================================== */ +/* ========================================== MCUCTRL XTALCTRL PWDBODXTAL [5..5] =========================================== */ +typedef enum { /*!< MCUCTRL_XTALCTRL_PWDBODXTAL */ + MCUCTRL_XTALCTRL_PWDBODXTAL_PWRUPBOD = 0, /*!< PWRUPBOD : Power up XTAL on BOD. */ + MCUCTRL_XTALCTRL_PWDBODXTAL_PWRDNBOD = 1, /*!< PWRDNBOD : Power down XTAL on BOD. */ +} MCUCTRL_XTALCTRL_PWDBODXTAL_Enum; + +/* ========================================= MCUCTRL XTALCTRL PDNBCMPRXTAL [4..4] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALCTRL_PDNBCMPRXTAL */ + MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRUPCOMP = 1, /*!< PWRUPCOMP : Power up XTAL oscillator comparator. */ + MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRDNCOMP = 0, /*!< PWRDNCOMP : Power down XTAL oscillator comparator. */ +} MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Enum; + +/* ========================================= MCUCTRL XTALCTRL PDNBCOREXTAL [3..3] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALCTRL_PDNBCOREXTAL */ + MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRUPCORE = 1, /*!< PWRUPCORE : Power up XTAL oscillator core. */ + MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRDNCORE = 0, /*!< PWRDNCORE : Power down XTAL oscillator core. */ +} MCUCTRL_XTALCTRL_PDNBCOREXTAL_Enum; + +/* ========================================== MCUCTRL XTALCTRL BYPCMPRXTAL [2..2] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALCTRL_BYPCMPRXTAL */ + MCUCTRL_XTALCTRL_BYPCMPRXTAL_USECOMP = 0, /*!< USECOMP : Use the XTAL oscillator comparator. */ + MCUCTRL_XTALCTRL_BYPCMPRXTAL_BYPCOMP = 1, /*!< BYPCOMP : Bypass the XTAL oscillator comparator. */ +} MCUCTRL_XTALCTRL_BYPCMPRXTAL_Enum; + +/* ========================================= MCUCTRL XTALCTRL FDBKDSBLXTAL [1..1] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALCTRL_FDBKDSBLXTAL */ + MCUCTRL_XTALCTRL_FDBKDSBLXTAL_EN = 0, /*!< EN : Enable XTAL oscillator comparator. */ + MCUCTRL_XTALCTRL_FDBKDSBLXTAL_DIS = 1, /*!< DIS : Disable XTAL oscillator comparator. */ +} MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Enum; + +/* ============================================ MCUCTRL XTALCTRL XTALSWE [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_XTALCTRL_XTALSWE */ + MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS = 0, /*!< OVERRIDE_DIS : XTAL Software Override Disable. */ + MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN = 1, /*!< OVERRIDE_EN : XTAL Software Override Enable. */ +} MCUCTRL_XTALCTRL_XTALSWE_Enum; + +/* ====================================================== XTALGENCTRL ====================================================== */ +/* ========================================== MCUCTRL XTALGENCTRL ACWARMUP [0..1] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALGENCTRL_ACWARMUP */ + MCUCTRL_XTALGENCTRL_ACWARMUP_SEC1 = 0, /*!< SEC1 : Warm-up period of 1-2 seconds */ + MCUCTRL_XTALGENCTRL_ACWARMUP_SEC2 = 1, /*!< SEC2 : Warm-up period of 2-4 seconds */ + MCUCTRL_XTALGENCTRL_ACWARMUP_SEC4 = 2, /*!< SEC4 : Warm-up period of 4-8 seconds */ + MCUCTRL_XTALGENCTRL_ACWARMUP_SEC8 = 3, /*!< SEC8 : Warm-up period of 8-16 seconds */ +} MCUCTRL_XTALGENCTRL_ACWARMUP_Enum; + +/* ======================================================= MISCCTRL ======================================================== */ +/* ====================================================== BOOTLOADER ======================================================= */ +/* ======================================= MCUCTRL BOOTLOADER SECBOOTONRST [30..31] ======================================== */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOTONRST */ + MCUCTRL_BOOTLOADER_SECBOOTONRST_DISABLED = 0, /*!< DISABLED : Secure boot disabled */ + MCUCTRL_BOOTLOADER_SECBOOTONRST_ENABLED = 1, /*!< ENABLED : Secure boot enabled */ + MCUCTRL_BOOTLOADER_SECBOOTONRST_ERROR = 2, /*!< ERROR : Error in secure boot configuration */ +} MCUCTRL_BOOTLOADER_SECBOOTONRST_Enum; + +/* ========================================== MCUCTRL BOOTLOADER SECBOOT [28..29] ========================================== */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOT */ + MCUCTRL_BOOTLOADER_SECBOOT_DISABLED = 0, /*!< DISABLED : Secure boot disabled */ + MCUCTRL_BOOTLOADER_SECBOOT_ENABLED = 1, /*!< ENABLED : Secure boot enabled */ + MCUCTRL_BOOTLOADER_SECBOOT_ERROR = 2, /*!< ERROR : Error in secure boot configuration */ +} MCUCTRL_BOOTLOADER_SECBOOT_Enum; + +/* ====================================== MCUCTRL BOOTLOADER SECBOOTFEATURE [26..27] ======================================= */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOTFEATURE */ + MCUCTRL_BOOTLOADER_SECBOOTFEATURE_DISABLED = 0,/*!< DISABLED : Secure boot disabled */ + MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ENABLED = 1,/*!< ENABLED : Secure boot enabled */ + MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ERROR = 2, /*!< ERROR : Error in secure boot configuration */ +} MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Enum; + +/* ========================================== MCUCTRL BOOTLOADER PROTLOCK [2..2] =========================================== */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_PROTLOCK */ + MCUCTRL_BOOTLOADER_PROTLOCK_LOCK = 1, /*!< LOCK : Enable the secure boot lock */ +} MCUCTRL_BOOTLOADER_PROTLOCK_Enum; + +/* =========================================== MCUCTRL BOOTLOADER SBLOCK [1..1] ============================================ */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_SBLOCK */ + MCUCTRL_BOOTLOADER_SBLOCK_LOCK = 1, /*!< LOCK : Enable the secure boot lock */ +} MCUCTRL_BOOTLOADER_SBLOCK_Enum; + +/* ======================================== MCUCTRL BOOTLOADER BOOTLOADERLOW [0..0] ======================================== */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_BOOTLOADERLOW */ + MCUCTRL_BOOTLOADER_BOOTLOADERLOW_ADDR0 = 1, /*!< ADDR0 : Bootloader code at 0x00000000. */ +} MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Enum; + +/* ====================================================== SHADOWVALID ====================================================== */ +/* ======================================== MCUCTRL SHADOWVALID INFO0_VALID [2..2] ========================================= */ +typedef enum { /*!< MCUCTRL_SHADOWVALID_INFO0_VALID */ + MCUCTRL_SHADOWVALID_INFO0_VALID_VALID = 1, /*!< VALID : Flash INFO0 (customer) space contains valid data. */ +} MCUCTRL_SHADOWVALID_INFO0_VALID_Enum; + +/* ========================================== MCUCTRL SHADOWVALID BLDSLEEP [1..1] ========================================== */ +typedef enum { /*!< MCUCTRL_SHADOWVALID_BLDSLEEP */ + MCUCTRL_SHADOWVALID_BLDSLEEP_DEEPSLEEP = 1, /*!< DEEPSLEEP : Bootloader will go to deep sleep if no flash image + loaded */ +} MCUCTRL_SHADOWVALID_BLDSLEEP_Enum; + +/* =========================================== MCUCTRL SHADOWVALID VALID [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_SHADOWVALID_VALID */ + MCUCTRL_SHADOWVALID_VALID_VALID = 1, /*!< VALID : Flash information space contains valid data. */ +} MCUCTRL_SHADOWVALID_VALID_Enum; + +/* ======================================================= SCRATCH0 ======================================================== */ +/* ======================================================= SCRATCH1 ======================================================== */ +/* ==================================================== ICODEFAULTADDR ===================================================== */ +/* ==================================================== DCODEFAULTADDR ===================================================== */ +/* ===================================================== SYSFAULTADDR ====================================================== */ +/* ====================================================== FAULTSTATUS ====================================================== */ +/* ========================================== MCUCTRL FAULTSTATUS SYSFAULT [2..2] ========================================== */ +typedef enum { /*!< MCUCTRL_FAULTSTATUS_SYSFAULT */ + MCUCTRL_FAULTSTATUS_SYSFAULT_NOFAULT = 0, /*!< NOFAULT : No bus fault has been detected. */ + MCUCTRL_FAULTSTATUS_SYSFAULT_FAULT = 1, /*!< FAULT : Bus fault detected. */ +} MCUCTRL_FAULTSTATUS_SYSFAULT_Enum; + +/* ========================================= MCUCTRL FAULTSTATUS DCODEFAULT [1..1] ========================================= */ +typedef enum { /*!< MCUCTRL_FAULTSTATUS_DCODEFAULT */ + MCUCTRL_FAULTSTATUS_DCODEFAULT_NOFAULT = 0, /*!< NOFAULT : No DCODE fault has been detected. */ + MCUCTRL_FAULTSTATUS_DCODEFAULT_FAULT = 1, /*!< FAULT : DCODE fault detected. */ +} MCUCTRL_FAULTSTATUS_DCODEFAULT_Enum; + +/* ========================================= MCUCTRL FAULTSTATUS ICODEFAULT [0..0] ========================================= */ +typedef enum { /*!< MCUCTRL_FAULTSTATUS_ICODEFAULT */ + MCUCTRL_FAULTSTATUS_ICODEFAULT_NOFAULT = 0, /*!< NOFAULT : No ICODE fault has been detected. */ + MCUCTRL_FAULTSTATUS_ICODEFAULT_FAULT = 1, /*!< FAULT : ICODE fault detected. */ +} MCUCTRL_FAULTSTATUS_ICODEFAULT_Enum; + +/* ==================================================== FAULTCAPTUREEN ===================================================== */ +/* ===================================== MCUCTRL FAULTCAPTUREEN FAULTCAPTUREEN [0..0] ====================================== */ +typedef enum { /*!< MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN */ + MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_DIS = 0,/*!< DIS : Disable fault capture. */ + MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_EN = 1, /*!< EN : Enable fault capture. */ +} MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Enum; + +/* ========================================================= DBGR1 ========================================================= */ +/* ========================================================= DBGR2 ========================================================= */ +/* ======================================================= PMUENABLE ======================================================= */ +/* ============================================ MCUCTRL PMUENABLE ENABLE [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_PMUENABLE_ENABLE */ + MCUCTRL_PMUENABLE_ENABLE_DIS = 0, /*!< DIS : Disable MCU power management. */ + MCUCTRL_PMUENABLE_ENABLE_EN = 1, /*!< EN : Enable MCU power management. */ +} MCUCTRL_PMUENABLE_ENABLE_Enum; + +/* ======================================================= TPIUCTRL ======================================================== */ +/* ============================================ MCUCTRL TPIUCTRL CLKSEL [8..10] ============================================ */ +typedef enum { /*!< MCUCTRL_TPIUCTRL_CLKSEL */ + MCUCTRL_TPIUCTRL_CLKSEL_LOWPWR = 0, /*!< LOWPWR : Low power state. */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV2 = 1, /*!< HFRCDIV2 : Selects HFRC divided by 2 as the source TPIU clock */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV8 = 2, /*!< HFRCDIV8 : Selects HFRC divided by 8 as the source TPIU clock */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV16 = 3, /*!< HFRCDIV16 : Selects HFRC divided by 16 as the source TPIU clock */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV32 = 4, /*!< HFRCDIV32 : Selects HFRC divided by 32 as the source TPIU clock */ +} MCUCTRL_TPIUCTRL_CLKSEL_Enum; + +/* ============================================ MCUCTRL TPIUCTRL ENABLE [0..0] ============================================= */ +typedef enum { /*!< MCUCTRL_TPIUCTRL_ENABLE */ + MCUCTRL_TPIUCTRL_ENABLE_DIS = 0, /*!< DIS : Disable the TPIU. */ + MCUCTRL_TPIUCTRL_ENABLE_EN = 1, /*!< EN : Enable the TPIU. */ +} MCUCTRL_TPIUCTRL_ENABLE_Enum; + +/* ====================================================== OTAPOINTER ======================================================= */ +/* ====================================================== APBDMACTRL ======================================================= */ +/* ========================================= MCUCTRL APBDMACTRL DECODEABORT [1..1] ========================================= */ +typedef enum { /*!< MCUCTRL_APBDMACTRL_DECODEABORT */ + MCUCTRL_APBDMACTRL_DECODEABORT_DISABLE = 0, /*!< DISABLE : Bus operations to powered down peripherals are quietly + discarded */ + MCUCTRL_APBDMACTRL_DECODEABORT_ENABLE = 1, /*!< ENABLE : Bus operations to powered down peripherals result in + a bus fault. */ +} MCUCTRL_APBDMACTRL_DECODEABORT_Enum; + +/* ========================================= MCUCTRL APBDMACTRL DMA_ENABLE [0..0] ========================================== */ +typedef enum { /*!< MCUCTRL_APBDMACTRL_DMA_ENABLE */ + MCUCTRL_APBDMACTRL_DMA_ENABLE_DISABLE = 0, /*!< DISABLE : DMA operations disabled */ + MCUCTRL_APBDMACTRL_DMA_ENABLE_ENABLE = 1, /*!< ENABLE : DMA operations enabled */ +} MCUCTRL_APBDMACTRL_DMA_ENABLE_Enum; + +/* ======================================================= SRAMMODE ======================================================== */ +/* ====================================================== KEXTCLKSEL ======================================================= */ +/* ========================================= MCUCTRL KEXTCLKSEL KEXTCLKSEL [0..31] ========================================= */ +typedef enum { /*!< MCUCTRL_KEXTCLKSEL_KEXTCLKSEL */ + MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Key = 83, /*!< Key : Key */ +} MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Enum; + +/* ======================================================= SIMOBUCK2 ======================================================= */ +/* ======================================================= SIMOBUCK3 ======================================================= */ +/* ======================================================= SIMOBUCK4 ======================================================= */ +/* ======================================================= BLEBUCK2 ======================================================== */ +/* ====================================================== FLASHWPROT0 ====================================================== */ +/* ====================================================== FLASHWPROT1 ====================================================== */ +/* ====================================================== FLASHRPROT0 ====================================================== */ +/* ====================================================== FLASHRPROT1 ====================================================== */ +/* ================================================= DMASRAMWRITEPROTECT0 ================================================== */ +/* ================================================= DMASRAMWRITEPROTECT1 ================================================== */ +/* ================================================== DMASRAMREADPROTECT0 ================================================== */ +/* ================================================== DMASRAMREADPROTECT1 ================================================== */ + + +/* =========================================================================================================================== */ +/* ================ MSPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +/* ========================================================== CFG ========================================================== */ +/* ================================================ MSPI CFG CPOL [17..17] ================================================= */ +typedef enum { /*!< MSPI_CFG_CPOL */ + MSPI_CFG_CPOL_LOW = 0, /*!< LOW : Clock inactive state is low. */ + MSPI_CFG_CPOL_HIGH = 1, /*!< HIGH : Clock inactive state is high. */ +} MSPI_CFG_CPOL_Enum; + +/* ================================================ MSPI CFG CPHA [16..16] ================================================= */ +typedef enum { /*!< MSPI_CFG_CPHA */ + MSPI_CFG_CPHA_MIDDLE = 0, /*!< MIDDLE : Clock toggles in middle of data bit. */ + MSPI_CFG_CPHA_START = 1, /*!< START : Clock toggles at start of data bit. */ +} MSPI_CFG_CPHA_Enum; + +/* ================================================= MSPI CFG ASIZE [4..5] ================================================= */ +typedef enum { /*!< MSPI_CFG_ASIZE */ + MSPI_CFG_ASIZE_A1 = 0, /*!< A1 : Send one address byte */ + MSPI_CFG_ASIZE_A2 = 1, /*!< A2 : Send two address bytes */ + MSPI_CFG_ASIZE_A3 = 2, /*!< A3 : Send three address bytes */ + MSPI_CFG_ASIZE_A4 = 3, /*!< A4 : Send four address bytes */ +} MSPI_CFG_ASIZE_Enum; + +/* ================================================ MSPI CFG DEVCFG [0..3] ================================================= */ +typedef enum { /*!< MSPI_CFG_DEVCFG */ + MSPI_CFG_DEVCFG_SERIAL0 = 1, /*!< SERIAL0 : Single bit SPI flash on chip select 0 */ + MSPI_CFG_DEVCFG_SERIAL1 = 2, /*!< SERIAL1 : Single bit SPI flash on chip select 1 */ + MSPI_CFG_DEVCFG_DUAL0 = 5, /*!< DUAL0 : Dual SPI flash on chip select 0 */ + MSPI_CFG_DEVCFG_DUAL1 = 6, /*!< DUAL1 : Dual bit SPI flash on chip select 1 */ + MSPI_CFG_DEVCFG_QUAD0 = 9, /*!< QUAD0 : Quad SPI flash on chip select 0 */ + MSPI_CFG_DEVCFG_QUAD1 = 10, /*!< QUAD1 : Quad SPI flash on chip select 1 */ + MSPI_CFG_DEVCFG_OCTAL0 = 13, /*!< OCTAL0 : Octal SPI flash on chip select 0 */ + MSPI_CFG_DEVCFG_OCTAL1 = 14, /*!< OCTAL1 : Octal SPI flash on chip select 1 */ + MSPI_CFG_DEVCFG_QUADPAIRED = 15, /*!< QUADPAIRED : Dual Quad SPI flash on chip selects 0/1. */ + MSPI_CFG_DEVCFG_QUADPAIRED_SERIAL = 3, /*!< QUADPAIRED_SERIAL : Dual Quad SPI flash on chip selects 0/1, + but transmit in serial mode for initialization operations */ +} MSPI_CFG_DEVCFG_Enum; + +/* ========================================================= ADDR ========================================================== */ +/* ========================================================= INSTR ========================================================= */ +/* ======================================================== TXFIFO ========================================================= */ +/* ======================================================== RXFIFO ========================================================= */ +/* ======================================================= TXENTRIES ======================================================= */ +/* ======================================================= RXENTRIES ======================================================= */ +/* ======================================================= THRESHOLD ======================================================= */ +/* ======================================================== MSPICFG ======================================================== */ +/* ============================================== MSPI MSPICFG CLKDIV [8..13] ============================================== */ +typedef enum { /*!< MSPI_MSPICFG_CLKDIV */ + MSPI_MSPICFG_CLKDIV_CLK48 = 1, /*!< CLK48 : 48 MHz MSPI clock */ + MSPI_MSPICFG_CLKDIV_CLK24 = 2, /*!< CLK24 : 24 MHz MSPI clock */ + MSPI_MSPICFG_CLKDIV_CLK12 = 4, /*!< CLK12 : 12 MHz MSPI clock */ + MSPI_MSPICFG_CLKDIV_CLK6 = 8, /*!< CLK6 : 6 MHz MSPI clock */ + MSPI_MSPICFG_CLKDIV_CLK3 = 16, /*!< CLK3 : 3 MHz MSPI clock */ + MSPI_MSPICFG_CLKDIV_CLK1_5 = 32, /*!< CLK1_5 : 1.5 MHz MSPI clock */ +} MSPI_MSPICFG_CLKDIV_Enum; + +/* ============================================== MSPI MSPICFG IOMSEL [4..6] =============================================== */ +typedef enum { /*!< MSPI_MSPICFG_IOMSEL */ + MSPI_MSPICFG_IOMSEL_IOM0 = 0, /*!< IOM0 : IOM0 */ + MSPI_MSPICFG_IOMSEL_IOM1 = 1, /*!< IOM1 : IOM1 */ + MSPI_MSPICFG_IOMSEL_IOM2 = 2, /*!< IOM2 : IOM2 */ + MSPI_MSPICFG_IOMSEL_IOM3 = 3, /*!< IOM3 : IOM3 */ + MSPI_MSPICFG_IOMSEL_IOM4 = 4, /*!< IOM4 : IOM4 */ + MSPI_MSPICFG_IOMSEL_IOM5 = 5, /*!< IOM5 : IOM5 */ + MSPI_MSPICFG_IOMSEL_DISABLED = 7, /*!< DISABLED : No IOM selected. Signals always zero. */ +} MSPI_MSPICFG_IOMSEL_Enum; + +/* =============================================== MSPI MSPICFG TXNEG [3..3] =============================================== */ +typedef enum { /*!< MSPI_MSPICFG_TXNEG */ + MSPI_MSPICFG_TXNEG_NORMAL = 0, /*!< NORMAL : TX launched from posedge internal clock */ + MSPI_MSPICFG_TXNEG_NEGEDGE = 1, /*!< NEGEDGE : TX data launched from negedge of internal clock */ +} MSPI_MSPICFG_TXNEG_Enum; + +/* =============================================== MSPI MSPICFG RXNEG [2..2] =============================================== */ +typedef enum { /*!< MSPI_MSPICFG_RXNEG */ + MSPI_MSPICFG_RXNEG_NORMAL = 0, /*!< NORMAL : RX data sampled on posedge of internal clock */ + MSPI_MSPICFG_RXNEG_NEGEDGE = 1, /*!< NEGEDGE : RX data sampled on negedge of internal clock */ +} MSPI_MSPICFG_RXNEG_Enum; + +/* =============================================== MSPI MSPICFG RXCAP [1..1] =============================================== */ +typedef enum { /*!< MSPI_MSPICFG_RXCAP */ + MSPI_MSPICFG_RXCAP_NORMAL = 0, /*!< NORMAL : RX Capture phase aligns with CPHA setting */ + MSPI_MSPICFG_RXCAP_DELAY = 1, /*!< DELAY : RX Capture phase is delayed from CPHA setting by one + clock edge */ +} MSPI_MSPICFG_RXCAP_Enum; + +/* ============================================== MSPI MSPICFG APBCLK [0..0] =============================================== */ +typedef enum { /*!< MSPI_MSPICFG_APBCLK */ + MSPI_MSPICFG_APBCLK_DIS = 0, /*!< DIS : Disable continuous clock. */ + MSPI_MSPICFG_APBCLK_EN = 1, /*!< EN : Enable continuous clock. */ +} MSPI_MSPICFG_APBCLK_Enum; + +/* ======================================================== PADCFG ========================================================= */ +/* ======================================================= PADOUTEN ======================================================== */ +/* ============================================== MSPI PADOUTEN OUTEN [0..8] =============================================== */ +typedef enum { /*!< MSPI_PADOUTEN_OUTEN */ + MSPI_PADOUTEN_OUTEN_QUAD0 = 271, /*!< QUAD0 : Quad0 (4 data + 1 clock) */ + MSPI_PADOUTEN_OUTEN_QUAD1 = 496, /*!< QUAD1 : Quad1 (4 data + 1 clock) */ + MSPI_PADOUTEN_OUTEN_OCTAL = 511, /*!< OCTAL : Octal (8 data + 1 clock) */ + MSPI_PADOUTEN_OUTEN_SERIAL0 = 259, /*!< SERIAL0 : Serial (2 data + 1 clock) */ +} MSPI_PADOUTEN_OUTEN_Enum; + +/* ========================================================= FLASH ========================================================= */ +/* =============================================== MSPI FLASH XIPACK [2..3] ================================================ */ +typedef enum { /*!< MSPI_FLASH_XIPACK */ + MSPI_FLASH_XIPACK_NOACK = 0, /*!< NOACK : No acknowledgment sent. Data IOs are tri-stated the + first turnaround cycle */ + MSPI_FLASH_XIPACK_ACK = 2, /*!< ACK : Positive acknowledgment sent. Data IOs are driven to 0 + the first turnaround cycle to acknowledge XIP mode */ + MSPI_FLASH_XIPACK_TERMINATE = 3, /*!< TERMINATE : Negative acknowledgment sent. Data IOs are driven + to 1 the first turnaround cycle to terminate XIP mode. + XIPSENDI should be re-enabled for the next transfer */ +} MSPI_FLASH_XIPACK_Enum; + +/* ====================================================== SCRAMBLING ======================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================== DMACFG ========================================================= */ +/* =============================================== MSPI DMACFG DMAPRI [3..4] =============================================== */ +typedef enum { /*!< MSPI_DMACFG_DMAPRI */ + MSPI_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + MSPI_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ + MSPI_DMACFG_DMAPRI_AUTO = 2, /*!< AUTO : Auto Priority (priority raised once TX FIFO empties or + RX FIFO fills) */ +} MSPI_DMACFG_DMAPRI_Enum; + +/* =============================================== MSPI DMACFG DMADIR [2..2] =============================================== */ +typedef enum { /*!< MSPI_DMACFG_DMADIR */ + MSPI_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction */ + MSPI_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction */ +} MSPI_DMACFG_DMADIR_Enum; + +/* =============================================== MSPI DMACFG DMAEN [0..1] ================================================ */ +typedef enum { /*!< MSPI_DMACFG_DMAEN */ + MSPI_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ + MSPI_DMACFG_DMAEN_EN = 3, /*!< EN : Enable HW controlled DMA Function to manage DMA to flash + devices. HW will automatically handle issuance of instruction/address + bytes based on settings in the FLASH register. */ +} MSPI_DMACFG_DMAEN_Enum; + +/* ======================================================== DMASTAT ======================================================== */ +/* ====================================================== DMATARGADDR ====================================================== */ +/* ====================================================== DMADEVADDR ======================================================= */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +/* ======================================================= DMABCOUNT ======================================================= */ +/* ======================================================= DMATHRESH ======================================================= */ +/* ========================================================= CQCFG ========================================================= */ +/* ================================================ MSPI CQCFG CQPRI [1..1] ================================================ */ +typedef enum { /*!< MSPI_CQCFG_CQPRI */ + MSPI_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + MSPI_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} MSPI_CQCFG_CQPRI_Enum; + +/* ================================================ MSPI CQCFG CQEN [0..0] ================================================= */ +typedef enum { /*!< MSPI_CQCFG_CQEN */ + MSPI_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */ + MSPI_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */ +} MSPI_CQCFG_CQEN_Enum; + +/* ======================================================== CQADDR ========================================================= */ +/* ======================================================== CQSTAT ========================================================= */ +/* ======================================================== CQFLAGS ======================================================== */ +/* ============================================= MSPI CQFLAGS CQFLAGS [0..15] ============================================== */ +typedef enum { /*!< MSPI_CQFLAGS_CQFLAGS */ + MSPI_CQFLAGS_CQFLAGS_STOP = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete. */ + MSPI_CQFLAGS_CQFLAGS_CQIDX = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match. */ + MSPI_CQFLAGS_CQFLAGS_DMACPL = 2048, /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT) */ + MSPI_CQFLAGS_CQFLAGS_CMDCPL = 1024, /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register) */ + MSPI_CQFLAGS_CQFLAGS_IOM1READY = 512, /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This + status is the result of XNOR'ing the IOM0START with the + incoming status from the IOM. When high, MSPI can send + to the buffer. */ + MSPI_CQFLAGS_CQFLAGS_IOM0READY = 256, /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This + status is the result of XNOR'ing the IOM0START with the + incoming status from the IOM. When high, MSPI can send + to the buffer. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG7 = 128, /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG6 = 64, /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG5 = 32, /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG4 = 16, /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG3 = 8, /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG2 = 4, /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG1 = 2, /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG0 = 1, /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause + operations. */ +} MSPI_CQFLAGS_CQFLAGS_Enum; + +/* ====================================================== CQSETCLEAR ======================================================= */ +/* ======================================================== CQPAUSE ======================================================== */ +/* ============================================== MSPI CQPAUSE CQMASK [0..15] ============================================== */ +typedef enum { /*!< MSPI_CQPAUSE_CQMASK */ + MSPI_CQPAUSE_CQMASK_STOP = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete. */ + MSPI_CQPAUSE_CQMASK_CQIDX = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match. */ + MSPI_CQPAUSE_CQMASK_DMACPL = 2048, /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT) */ + MSPI_CQPAUSE_CQMASK_CMDCPL = 1024, /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register) */ + MSPI_CQPAUSE_CQMASK_IOM1READY = 512, /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This + status is the result of XNOR'ing the IOM0START with the + incoming status from the IOM. When high, MSPI can send + to the buffer. */ + MSPI_CQPAUSE_CQMASK_IOM0READY = 256, /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This + status is the result of XNOR'ing the IOM0START with the + incoming status from the IOM. When high, MSPI can send + to the buffer. */ + MSPI_CQPAUSE_CQMASK_SWFLAG7 = 128, /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG6 = 64, /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG5 = 32, /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG4 = 16, /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG3 = 8, /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG2 = 4, /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG1 = 2, /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG0 = 1, /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause + operations. */ +} MSPI_CQPAUSE_CQMASK_Enum; + +/* ======================================================= CQCURIDX ======================================================== */ +/* ======================================================= CQENDIDX ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PCFG ========================================================== */ +/* =============================================== PDM PCFG LRSWAP [31..31] ================================================ */ +typedef enum { /*!< PDM_PCFG_LRSWAP */ + PDM_PCFG_LRSWAP_EN = 1, /*!< EN : Swap left and right channels (FIFO Read RIGHT_LEFT). */ + PDM_PCFG_LRSWAP_NOSWAP = 0, /*!< NOSWAP : No channel swapping (IFO Read LEFT_RIGHT). */ +} PDM_PCFG_LRSWAP_Enum; + +/* ============================================== PDM PCFG PGARIGHT [26..30] =============================================== */ +typedef enum { /*!< PDM_PCFG_PGARIGHT */ + PDM_PCFG_PGARIGHT_P405DB = 31, /*!< P405DB : 40.5 db gain. */ + PDM_PCFG_PGARIGHT_P390DB = 30, /*!< P390DB : 39.0 db gain. */ + PDM_PCFG_PGARIGHT_P375DB = 29, /*!< P375DB : 37.5 db gain. */ + PDM_PCFG_PGARIGHT_P360DB = 28, /*!< P360DB : 36.0 db gain. */ + PDM_PCFG_PGARIGHT_P345DB = 27, /*!< P345DB : 34.5 db gain. */ + PDM_PCFG_PGARIGHT_P330DB = 26, /*!< P330DB : 33.0 db gain. */ + PDM_PCFG_PGARIGHT_P315DB = 25, /*!< P315DB : 31.5 db gain. */ + PDM_PCFG_PGARIGHT_P300DB = 24, /*!< P300DB : 30.0 db gain. */ + PDM_PCFG_PGARIGHT_P285DB = 23, /*!< P285DB : 28.5 db gain. */ + PDM_PCFG_PGARIGHT_P270DB = 22, /*!< P270DB : 27.0 db gain. */ + PDM_PCFG_PGARIGHT_P255DB = 21, /*!< P255DB : 25.5 db gain. */ + PDM_PCFG_PGARIGHT_P240DB = 20, /*!< P240DB : 24.0 db gain. */ + PDM_PCFG_PGARIGHT_P225DB = 19, /*!< P225DB : 22.5 db gain. */ + PDM_PCFG_PGARIGHT_P210DB = 18, /*!< P210DB : 21.0 db gain. */ + PDM_PCFG_PGARIGHT_P195DB = 17, /*!< P195DB : 19.5 db gain. */ + PDM_PCFG_PGARIGHT_P180DB = 16, /*!< P180DB : 18.0 db gain. */ + PDM_PCFG_PGARIGHT_P165DB = 15, /*!< P165DB : 16.5 db gain. */ + PDM_PCFG_PGARIGHT_P150DB = 14, /*!< P150DB : 15.0 db gain. */ + PDM_PCFG_PGARIGHT_P135DB = 13, /*!< P135DB : 13.5 db gain. */ + PDM_PCFG_PGARIGHT_P120DB = 12, /*!< P120DB : 12.0 db gain. */ + PDM_PCFG_PGARIGHT_P105DB = 11, /*!< P105DB : 10.5 db gain. */ + PDM_PCFG_PGARIGHT_P90DB = 10, /*!< P90DB : 9.0 db gain. */ + PDM_PCFG_PGARIGHT_P75DB = 9, /*!< P75DB : 7.5 db gain. */ + PDM_PCFG_PGARIGHT_P60DB = 8, /*!< P60DB : 6.0 db gain. */ + PDM_PCFG_PGARIGHT_P45DB = 7, /*!< P45DB : 4.5 db gain. */ + PDM_PCFG_PGARIGHT_P30DB = 6, /*!< P30DB : 3.0 db gain. */ + PDM_PCFG_PGARIGHT_P15DB = 5, /*!< P15DB : 1.5 db gain. */ + PDM_PCFG_PGARIGHT_0DB = 4, /*!< 0DB : 0.0 db gain. */ + PDM_PCFG_PGARIGHT_M15DB = 3, /*!< M15DB : -1.5 db gain. */ + PDM_PCFG_PGARIGHT_M300DB = 2, /*!< M300DB : -3.0 db gain. */ + PDM_PCFG_PGARIGHT_M45DB = 1, /*!< M45DB : -4.5 db gain. */ + PDM_PCFG_PGARIGHT_M60DB = 0, /*!< M60DB : -6.0 db gain. */ +} PDM_PCFG_PGARIGHT_Enum; + +/* =============================================== PDM PCFG PGALEFT [21..25] =============================================== */ +typedef enum { /*!< PDM_PCFG_PGALEFT */ + PDM_PCFG_PGALEFT_P405DB = 31, /*!< P405DB : 40.5 db gain. */ + PDM_PCFG_PGALEFT_P390DB = 30, /*!< P390DB : 39.0 db gain. */ + PDM_PCFG_PGALEFT_P375DB = 29, /*!< P375DB : 37.5 db gain. */ + PDM_PCFG_PGALEFT_P360DB = 28, /*!< P360DB : 36.0 db gain. */ + PDM_PCFG_PGALEFT_P345DB = 27, /*!< P345DB : 34.5 db gain. */ + PDM_PCFG_PGALEFT_P330DB = 26, /*!< P330DB : 33.0 db gain. */ + PDM_PCFG_PGALEFT_P315DB = 25, /*!< P315DB : 31.5 db gain. */ + PDM_PCFG_PGALEFT_P300DB = 24, /*!< P300DB : 30.0 db gain. */ + PDM_PCFG_PGALEFT_P285DB = 23, /*!< P285DB : 28.5 db gain. */ + PDM_PCFG_PGALEFT_P270DB = 22, /*!< P270DB : 27.0 db gain. */ + PDM_PCFG_PGALEFT_P255DB = 21, /*!< P255DB : 25.5 db gain. */ + PDM_PCFG_PGALEFT_P240DB = 20, /*!< P240DB : 24.0 db gain. */ + PDM_PCFG_PGALEFT_P225DB = 19, /*!< P225DB : 22.5 db gain. */ + PDM_PCFG_PGALEFT_P210DB = 18, /*!< P210DB : 21.0 db gain. */ + PDM_PCFG_PGALEFT_P195DB = 17, /*!< P195DB : 19.5 db gain. */ + PDM_PCFG_PGALEFT_P180DB = 16, /*!< P180DB : 18.0 db gain. */ + PDM_PCFG_PGALEFT_P165DB = 15, /*!< P165DB : 16.5 db gain. */ + PDM_PCFG_PGALEFT_P150DB = 14, /*!< P150DB : 15.0 db gain. */ + PDM_PCFG_PGALEFT_P135DB = 13, /*!< P135DB : 13.5 db gain. */ + PDM_PCFG_PGALEFT_P120DB = 12, /*!< P120DB : 12.0 db gain. */ + PDM_PCFG_PGALEFT_P105DB = 11, /*!< P105DB : 10.5 db gain. */ + PDM_PCFG_PGALEFT_P90DB = 10, /*!< P90DB : 9.0 db gain. */ + PDM_PCFG_PGALEFT_P75DB = 9, /*!< P75DB : 7.5 db gain. */ + PDM_PCFG_PGALEFT_P60DB = 8, /*!< P60DB : 6.0 db gain. */ + PDM_PCFG_PGALEFT_P45DB = 7, /*!< P45DB : 4.5 db gain. */ + PDM_PCFG_PGALEFT_P30DB = 6, /*!< P30DB : 3.0 db gain. */ + PDM_PCFG_PGALEFT_P15DB = 5, /*!< P15DB : 1.5 db gain. */ + PDM_PCFG_PGALEFT_0DB = 4, /*!< 0DB : 0.0 db gain. */ + PDM_PCFG_PGALEFT_M15DB = 3, /*!< M15DB : -1.5 db gain. */ + PDM_PCFG_PGALEFT_M300DB = 2, /*!< M300DB : -3.0 db gain. */ + PDM_PCFG_PGALEFT_M45DB = 1, /*!< M45DB : -4.5 db gain. */ + PDM_PCFG_PGALEFT_M60DB = 0, /*!< M60DB : -6.0 db gain. */ +} PDM_PCFG_PGALEFT_Enum; + +/* =============================================== PDM PCFG MCLKDIV [17..18] =============================================== */ +typedef enum { /*!< PDM_PCFG_MCLKDIV */ + PDM_PCFG_MCLKDIV_MCKDIV4 = 3, /*!< MCKDIV4 : Divide input clock by 4 */ + PDM_PCFG_MCLKDIV_MCKDIV3 = 2, /*!< MCKDIV3 : Divide input clock by 3 */ + PDM_PCFG_MCLKDIV_MCKDIV2 = 1, /*!< MCKDIV2 : Divide input clock by 2 */ + PDM_PCFG_MCLKDIV_MCKDIV1 = 0, /*!< MCKDIV1 : Divide input clock by 1 */ +} PDM_PCFG_MCLKDIV_Enum; + +/* ================================================ PDM PCFG ADCHPD [9..9] ================================================= */ +typedef enum { /*!< PDM_PCFG_ADCHPD */ + PDM_PCFG_ADCHPD_EN = 0, /*!< EN : Enable high pass filter. */ + PDM_PCFG_ADCHPD_DIS = 1, /*!< DIS : Disable high pass filter. */ +} PDM_PCFG_ADCHPD_Enum; + +/* =============================================== PDM PCFG SOFTMUTE [1..1] ================================================ */ +typedef enum { /*!< PDM_PCFG_SOFTMUTE */ + PDM_PCFG_SOFTMUTE_EN = 1, /*!< EN : Enable Soft Mute. */ + PDM_PCFG_SOFTMUTE_DIS = 0, /*!< DIS : Disable Soft Mute. */ +} PDM_PCFG_SOFTMUTE_Enum; + +/* =============================================== PDM PCFG PDMCOREEN [0..0] =============================================== */ +typedef enum { /*!< PDM_PCFG_PDMCOREEN */ + PDM_PCFG_PDMCOREEN_EN = 1, /*!< EN : Enable Data Streaming. */ + PDM_PCFG_PDMCOREEN_DIS = 0, /*!< DIS : Disable Data Streaming. */ +} PDM_PCFG_PDMCOREEN_Enum; + +/* ========================================================= VCFG ========================================================== */ +/* =============================================== PDM VCFG IOCLKEN [31..31] =============================================== */ +typedef enum { /*!< PDM_VCFG_IOCLKEN */ + PDM_VCFG_IOCLKEN_DIS = 0, /*!< DIS : Disable FIFO read. */ + PDM_VCFG_IOCLKEN_EN = 1, /*!< EN : Enable FIFO read. */ +} PDM_VCFG_IOCLKEN_Enum; + +/* ================================================ PDM VCFG RSTB [30..30] ================================================= */ +typedef enum { /*!< PDM_VCFG_RSTB */ + PDM_VCFG_RSTB_RESET = 0, /*!< RESET : Reset the core. */ + PDM_VCFG_RSTB_NORM = 1, /*!< NORM : Enable the core. */ +} PDM_VCFG_RSTB_Enum; + +/* ============================================== PDM VCFG PDMCLKSEL [27..29] ============================================== */ +typedef enum { /*!< PDM_VCFG_PDMCLKSEL */ + PDM_VCFG_PDMCLKSEL_DISABLE = 0, /*!< DISABLE : Static value. */ + PDM_VCFG_PDMCLKSEL_12MHz = 1, /*!< 12MHz : PDM clock is 12 MHz. */ + PDM_VCFG_PDMCLKSEL_6MHz = 2, /*!< 6MHz : PDM clock is 6 MHz. */ + PDM_VCFG_PDMCLKSEL_3MHz = 3, /*!< 3MHz : PDM clock is 3 MHz. */ + PDM_VCFG_PDMCLKSEL_1_5MHz = 4, /*!< 1_5MHz : PDM clock is 1.5 MHz. */ + PDM_VCFG_PDMCLKSEL_750KHz = 5, /*!< 750KHz : PDM clock is 750 KHz. */ + PDM_VCFG_PDMCLKSEL_375KHz = 6, /*!< 375KHz : PDM clock is 375 KHz. */ + PDM_VCFG_PDMCLKSEL_187KHz = 7, /*!< 187KHz : PDM clock is 187.5 KHz. */ +} PDM_VCFG_PDMCLKSEL_Enum; + +/* ============================================== PDM VCFG PDMCLKEN [26..26] =============================================== */ +typedef enum { /*!< PDM_VCFG_PDMCLKEN */ + PDM_VCFG_PDMCLKEN_DIS = 0, /*!< DIS : Disable serial clock. */ + PDM_VCFG_PDMCLKEN_EN = 1, /*!< EN : Enable serial clock. */ +} PDM_VCFG_PDMCLKEN_Enum; + +/* ================================================ PDM VCFG I2SEN [20..20] ================================================ */ +typedef enum { /*!< PDM_VCFG_I2SEN */ + PDM_VCFG_I2SEN_DIS = 0, /*!< DIS : Disable I2S interface. */ + PDM_VCFG_I2SEN_EN = 1, /*!< EN : Enable I2S interface. */ +} PDM_VCFG_I2SEN_Enum; + +/* =============================================== PDM VCFG BCLKINV [19..19] =============================================== */ +typedef enum { /*!< PDM_VCFG_BCLKINV */ + PDM_VCFG_BCLKINV_INV = 0, /*!< INV : BCLK inverted. */ + PDM_VCFG_BCLKINV_NORM = 1, /*!< NORM : BCLK not inverted. */ +} PDM_VCFG_BCLKINV_Enum; + +/* ============================================== PDM VCFG DMICKDEL [17..17] =============================================== */ +typedef enum { /*!< PDM_VCFG_DMICKDEL */ + PDM_VCFG_DMICKDEL_0CYC = 0, /*!< 0CYC : No delay. */ + PDM_VCFG_DMICKDEL_1CYC = 1, /*!< 1CYC : 1 cycle delay. */ +} PDM_VCFG_DMICKDEL_Enum; + +/* ================================================ PDM VCFG SELAP [16..16] ================================================ */ +typedef enum { /*!< PDM_VCFG_SELAP */ + PDM_VCFG_SELAP_I2S = 1, /*!< I2S : Clock source from I2S BCLK. */ + PDM_VCFG_SELAP_INTERNAL = 0, /*!< INTERNAL : Clock source from internal clock generator. */ +} PDM_VCFG_SELAP_Enum; + +/* ================================================ PDM VCFG PCMPACK [8..8] ================================================ */ +typedef enum { /*!< PDM_VCFG_PCMPACK */ + PDM_VCFG_PCMPACK_DIS = 0, /*!< DIS : Disable PCM packing. */ + PDM_VCFG_PCMPACK_EN = 1, /*!< EN : Enable PCM packing. */ +} PDM_VCFG_PCMPACK_Enum; + +/* ================================================= PDM VCFG CHSET [3..4] ================================================= */ +typedef enum { /*!< PDM_VCFG_CHSET */ + PDM_VCFG_CHSET_DIS = 0, /*!< DIS : Channel disabled. */ + PDM_VCFG_CHSET_LEFT = 1, /*!< LEFT : Mono left channel. */ + PDM_VCFG_CHSET_RIGHT = 2, /*!< RIGHT : Mono right channel. */ + PDM_VCFG_CHSET_STEREO = 3, /*!< STEREO : Stereo channels. */ +} PDM_VCFG_CHSET_Enum; + +/* ======================================================= VOICESTAT ======================================================= */ +/* ======================================================= FIFOREAD ======================================================== */ +/* ======================================================= FIFOFLUSH ======================================================= */ +/* ======================================================== FIFOTHR ======================================================== */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================= DMATRIGEN ======================================================= */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +/* ======================================================== DMACFG ========================================================= */ +/* =============================================== PDM DMACFG DMAPRI [8..8] ================================================ */ +typedef enum { /*!< PDM_DMACFG_DMAPRI */ + PDM_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + PDM_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} PDM_DMACFG_DMAPRI_Enum; + +/* =============================================== PDM DMACFG DMADIR [2..2] ================================================ */ +typedef enum { /*!< PDM_DMACFG_DMADIR */ + PDM_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. THe PDM module + will only DMA to memory. */ + PDM_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. Not available for PDM + module */ +} PDM_DMACFG_DMADIR_Enum; + +/* ================================================ PDM DMACFG DMAEN [0..0] ================================================ */ +typedef enum { /*!< PDM_DMACFG_DMAEN */ + PDM_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ + PDM_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ +} PDM_DMACFG_DMAEN_Enum; + +/* ====================================================== DMATOTCOUNT ====================================================== */ +/* ====================================================== DMATARGADDR ====================================================== */ +/* ======================================================== DMASTAT ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ PWRCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SUPPLYSRC ======================================================= */ +/* ========================================== PWRCTRL SUPPLYSRC BLEBUCKEN [0..0] =========================================== */ +typedef enum { /*!< PWRCTRL_SUPPLYSRC_BLEBUCKEN */ + PWRCTRL_SUPPLYSRC_BLEBUCKEN_EN = 1, /*!< EN : Enable the BLE Buck. */ + PWRCTRL_SUPPLYSRC_BLEBUCKEN_DIS = 0, /*!< DIS : Disable the BLE Buck. */ +} PWRCTRL_SUPPLYSRC_BLEBUCKEN_Enum; + +/* ===================================================== SUPPLYSTATUS ====================================================== */ +/* ========================================= PWRCTRL SUPPLYSTATUS BLEBUCKON [1..1] ========================================= */ +typedef enum { /*!< PWRCTRL_SUPPLYSTATUS_BLEBUCKON */ + PWRCTRL_SUPPLYSTATUS_BLEBUCKON_LDO = 0, /*!< LDO : Indicates the the LDO is supplying the BLE/Burst power + domain */ + PWRCTRL_SUPPLYSTATUS_BLEBUCKON_BUCK = 1, /*!< BUCK : Indicates the the Buck is supplying the BLE/Burst power + domain */ +} PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Enum; + +/* ======================================== PWRCTRL SUPPLYSTATUS SIMOBUCKON [0..0] ========================================= */ +typedef enum { /*!< PWRCTRL_SUPPLYSTATUS_SIMOBUCKON */ + PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_OFF = 0, /*!< OFF : Indicates the the SIMO Buck is OFF. */ + PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_ON = 1, /*!< ON : Indicates the the SIMO Buck is ON. */ +} PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Enum; + +/* ======================================================= DEVPWREN ======================================================== */ +/* =========================================== PWRCTRL DEVPWREN PWRBLEL [13..13] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRBLEL */ + PWRCTRL_DEVPWREN_PWRBLEL_EN = 1, /*!< EN : Power up BLE controller */ + PWRCTRL_DEVPWREN_PWRBLEL_DIS = 0, /*!< DIS : Power down BLE controller */ +} PWRCTRL_DEVPWREN_PWRBLEL_Enum; + +/* =========================================== PWRCTRL DEVPWREN PWRPDM [12..12] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRPDM */ + PWRCTRL_DEVPWREN_PWRPDM_EN = 1, /*!< EN : Power up PDM */ + PWRCTRL_DEVPWREN_PWRPDM_DIS = 0, /*!< DIS : Power down PDM */ +} PWRCTRL_DEVPWREN_PWRPDM_Enum; + +/* =========================================== PWRCTRL DEVPWREN PWRMSPI [11..11] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRMSPI */ + PWRCTRL_DEVPWREN_PWRMSPI_EN = 1, /*!< EN : Power up MSPI */ + PWRCTRL_DEVPWREN_PWRMSPI_DIS = 0, /*!< DIS : Power down MSPI */ +} PWRCTRL_DEVPWREN_PWRMSPI_Enum; + +/* ========================================== PWRCTRL DEVPWREN PWRSCARD [10..10] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRSCARD */ + PWRCTRL_DEVPWREN_PWRSCARD_EN = 1, /*!< EN : Power up SCARD */ + PWRCTRL_DEVPWREN_PWRSCARD_DIS = 0, /*!< DIS : Power down SCARD */ +} PWRCTRL_DEVPWREN_PWRSCARD_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRADC [9..9] ============================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRADC */ + PWRCTRL_DEVPWREN_PWRADC_EN = 1, /*!< EN : Power up ADC */ + PWRCTRL_DEVPWREN_PWRADC_DIS = 0, /*!< DIS : Power Down ADC */ +} PWRCTRL_DEVPWREN_PWRADC_Enum; + +/* =========================================== PWRCTRL DEVPWREN PWRUART1 [8..8] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRUART1 */ + PWRCTRL_DEVPWREN_PWRUART1_EN = 1, /*!< EN : Power up UART 1 */ + PWRCTRL_DEVPWREN_PWRUART1_DIS = 0, /*!< DIS : Power down UART 1 */ +} PWRCTRL_DEVPWREN_PWRUART1_Enum; + +/* =========================================== PWRCTRL DEVPWREN PWRUART0 [7..7] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRUART0 */ + PWRCTRL_DEVPWREN_PWRUART0_EN = 1, /*!< EN : Power up UART 0 */ + PWRCTRL_DEVPWREN_PWRUART0_DIS = 0, /*!< DIS : Power down UART 0 */ +} PWRCTRL_DEVPWREN_PWRUART0_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM5 [6..6] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM5 */ + PWRCTRL_DEVPWREN_PWRIOM5_EN = 1, /*!< EN : Power up IO Master 5 */ + PWRCTRL_DEVPWREN_PWRIOM5_DIS = 0, /*!< DIS : Power down IO Master 5 */ +} PWRCTRL_DEVPWREN_PWRIOM5_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM4 [5..5] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM4 */ + PWRCTRL_DEVPWREN_PWRIOM4_EN = 1, /*!< EN : Power up IO Master 4 */ + PWRCTRL_DEVPWREN_PWRIOM4_DIS = 0, /*!< DIS : Power down IO Master 4 */ +} PWRCTRL_DEVPWREN_PWRIOM4_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM3 [4..4] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM3 */ + PWRCTRL_DEVPWREN_PWRIOM3_EN = 1, /*!< EN : Power up IO Master 3 */ + PWRCTRL_DEVPWREN_PWRIOM3_DIS = 0, /*!< DIS : Power down IO Master 3 */ +} PWRCTRL_DEVPWREN_PWRIOM3_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM2 [3..3] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM2 */ + PWRCTRL_DEVPWREN_PWRIOM2_EN = 1, /*!< EN : Power up IO Master 2 */ + PWRCTRL_DEVPWREN_PWRIOM2_DIS = 0, /*!< DIS : Power down IO Master 2 */ +} PWRCTRL_DEVPWREN_PWRIOM2_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM1 [2..2] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM1 */ + PWRCTRL_DEVPWREN_PWRIOM1_EN = 1, /*!< EN : Power up IO Master 1 */ + PWRCTRL_DEVPWREN_PWRIOM1_DIS = 0, /*!< DIS : Power down IO Master 1 */ +} PWRCTRL_DEVPWREN_PWRIOM1_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM0 [1..1] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM0 */ + PWRCTRL_DEVPWREN_PWRIOM0_EN = 1, /*!< EN : Power up IO Master 0 */ + PWRCTRL_DEVPWREN_PWRIOM0_DIS = 0, /*!< DIS : Power down IO Master 0 */ +} PWRCTRL_DEVPWREN_PWRIOM0_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOS [0..0] ============================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOS */ + PWRCTRL_DEVPWREN_PWRIOS_EN = 1, /*!< EN : Power up IO slave */ + PWRCTRL_DEVPWREN_PWRIOS_DIS = 0, /*!< DIS : Power down IO slave */ +} PWRCTRL_DEVPWREN_PWRIOS_Enum; + +/* ===================================================== MEMPWDINSLEEP ===================================================== */ +/* ====================================== PWRCTRL MEMPWDINSLEEP CACHEPWDSLP [31..31] ======================================= */ +typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP */ + PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN = 1, /*!< EN : Power down cache in deep sleep */ + PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_DIS = 0, /*!< DIS : Retain cache in deep sleep */ +} PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Enum; + +/* ====================================== PWRCTRL MEMPWDINSLEEP FLASH1PWDSLP [14..14] ====================================== */ +typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP */ + PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN = 1, /*!< EN : Flash1 is powered down during deepsleep */ + PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_DIS = 0, /*!< DIS : Flash1 is kept powered on during deepsleep */ +} PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Enum; + +/* ====================================== PWRCTRL MEMPWDINSLEEP FLASH0PWDSLP [13..13] ====================================== */ +typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP */ + PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN = 1, /*!< EN : Flash0 is powered down during deepsleep */ + PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_DIS = 0, /*!< DIS : Flash0 is kept powered on during deepsleep */ +} PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Enum; + +/* ======================================= PWRCTRL MEMPWDINSLEEP SRAMPWDSLP [3..12] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_NONE = 0, /*!< NONE : All banks retained */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0 = 1, /*!< GROUP0 : SRAM GROUP0 powered down (64KB-96KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1 = 2, /*!< GROUP1 : SRAM GROUP1 powered down (96KB-128KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2 = 4, /*!< GROUP2 : SRAM GROUP2 powered down (128KB-160KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3 = 8, /*!< GROUP3 : SRAM GROUP3 powered down (160KB-192KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4 = 16, /*!< GROUP4 : SRAM GROUP4 powered down (192KB-224KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5 = 32, /*!< GROUP5 : SRAM GROUP5 powered down (224KB-256KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6 = 64, /*!< GROUP6 : SRAM GROUP6 powered down (256KB-288KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7 = 128,/*!< GROUP7 : SRAM GROUP7 powered down (288KB-320KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8 = 256,/*!< GROUP8 : SRAM GROUP8 powered down (320KB-352KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9 = 512,/*!< GROUP9 : SRAM GROUP9 powered down (352KB-384KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM64K = 3, /*!< SRAM64K : Powerdown lower 64k SRAM (64KB-128KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM128K = 15,/*!< SRAM128K : Powerdown lower 128k SRAM (64KB-192KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER32K = 1022,/*!< ALLBUTLOWER32K : All SRAM banks but lower 32k powered down (96KB-384KB). */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER64K = 1020,/*!< ALLBUTLOWER64K : All banks but lower 64k powered down. */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER128K = 1008,/*!< ALLBUTLOWER128K : All banks but lower 128k powered down. */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL = 1023, /*!< ALL : All banks powered down. */ +} PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Enum; + +/* ======================================== PWRCTRL MEMPWDINSLEEP DTCMPWDSLP [0..2] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_NONE = 0, /*!< NONE : All DTCM retained */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0 = 1,/*!< GROUP0DTCM0 : Group0_DTCM0 powered down in deep sleep (0KB-8KB) */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM1 = 2,/*!< GROUP0DTCM1 : Group0_DTCM1 powered down in deep sleep (8KB-32KB) */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0 = 3, /*!< GROUP0 : Both DTCMs in group0 are powered down in deep sleep + (0KB-32KB) */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALLBUTGROUP0DTCM0 = 6,/*!< ALLBUTGROUP0DTCM0 : Group1 and Group0_DTCM1 are powered down + in deep sleep (8KB-64KB) */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP1 = 4, /*!< GROUP1 : Group1 DTCM powered down in deep sleep (32KB-64KB) */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL = 7, /*!< ALL : All DTCMs powered down in deep sleep (0KB-64KB) */ +} PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Enum; + +/* ======================================================= MEMPWREN ======================================================== */ +/* =========================================== PWRCTRL MEMPWREN CACHEB2 [31..31] =========================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREN_CACHEB2 */ + PWRCTRL_MEMPWREN_CACHEB2_EN = 1, /*!< EN : Power up Cache Bank 2 */ + PWRCTRL_MEMPWREN_CACHEB2_DIS = 0, /*!< DIS : Power down Cache Bank 2 */ +} PWRCTRL_MEMPWREN_CACHEB2_Enum; + +/* =========================================== PWRCTRL MEMPWREN CACHEB0 [30..30] =========================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREN_CACHEB0 */ + PWRCTRL_MEMPWREN_CACHEB0_EN = 1, /*!< EN : Power up Cache Bank 0 */ + PWRCTRL_MEMPWREN_CACHEB0_DIS = 0, /*!< DIS : Power down Cache Bank 0 */ +} PWRCTRL_MEMPWREN_CACHEB0_Enum; + +/* =========================================== PWRCTRL MEMPWREN FLASH1 [14..14] ============================================ */ +typedef enum { /*!< PWRCTRL_MEMPWREN_FLASH1 */ + PWRCTRL_MEMPWREN_FLASH1_EN = 1, /*!< EN : Power up Flash1 */ + PWRCTRL_MEMPWREN_FLASH1_DIS = 0, /*!< DIS : Power down Flash1 */ +} PWRCTRL_MEMPWREN_FLASH1_Enum; + +/* =========================================== PWRCTRL MEMPWREN FLASH0 [13..13] ============================================ */ +typedef enum { /*!< PWRCTRL_MEMPWREN_FLASH0 */ + PWRCTRL_MEMPWREN_FLASH0_EN = 1, /*!< EN : Power up Flash0 */ + PWRCTRL_MEMPWREN_FLASH0_DIS = 0, /*!< DIS : Power down Flash0 */ +} PWRCTRL_MEMPWREN_FLASH0_Enum; + +/* ============================================= PWRCTRL MEMPWREN SRAM [3..12] ============================================= */ +typedef enum { /*!< PWRCTRL_MEMPWREN_SRAM */ + PWRCTRL_MEMPWREN_SRAM_NONE = 0, /*!< NONE : Do not power ON any of the SRAM banks */ + PWRCTRL_MEMPWREN_SRAM_GROUP0 = 1, /*!< GROUP0 : Power ON only SRAM group0 (0KB-32KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP1 = 2, /*!< GROUP1 : Power ON only SRAM group1 (32KB-64KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP2 = 4, /*!< GROUP2 : Power ON only SRAM group2 (64KB-96KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP3 = 8, /*!< GROUP3 : Power ON only SRAM group3 (96KB-128KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP4 = 16, /*!< GROUP4 : Power ON only SRAM group4 (128KB-160KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP5 = 32, /*!< GROUP5 : Power ON only SRAM group5 (160KB-192KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP6 = 64, /*!< GROUP6 : Power ON only SRAM group6 (192KB-224KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP7 = 128, /*!< GROUP7 : Power ON only SRAM group7 (224KB-256KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP8 = 256, /*!< GROUP8 : Power ON only SRAM group8 (256KB-288KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP9 = 512, /*!< GROUP9 : Power ON only SRAM group9 (288KB-320KB) */ + PWRCTRL_MEMPWREN_SRAM_SRAM64K = 3, /*!< SRAM64K : Power ON only lower 64k */ + PWRCTRL_MEMPWREN_SRAM_SRAM128K = 15, /*!< SRAM128K : Power ON only lower 128k */ + PWRCTRL_MEMPWREN_SRAM_SRAM256K = 255, /*!< SRAM256K : Power ON only lower 256k */ + PWRCTRL_MEMPWREN_SRAM_ALL = 1023, /*!< ALL : All SRAM banks (320K) powered ON */ +} PWRCTRL_MEMPWREN_SRAM_Enum; + +/* ============================================= PWRCTRL MEMPWREN DTCM [0..2] ============================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREN_DTCM */ + PWRCTRL_MEMPWREN_DTCM_NONE = 0, /*!< NONE : Do not enable power to any DTCMs */ + PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0 = 1, /*!< GROUP0DTCM0 : Power ON only GROUP0_DTCM0 */ + PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM1 = 2, /*!< GROUP0DTCM1 : Power ON only GROUP0_DTCM1 */ + PWRCTRL_MEMPWREN_DTCM_GROUP0 = 3, /*!< GROUP0 : Power ON only DTCMs in group0 */ + PWRCTRL_MEMPWREN_DTCM_GROUP1 = 4, /*!< GROUP1 : Power ON only DTCMs in group1 */ + PWRCTRL_MEMPWREN_DTCM_ALL = 7, /*!< ALL : Power ON all DTCMs */ +} PWRCTRL_MEMPWREN_DTCM_Enum; + +/* ===================================================== MEMPWRSTATUS ====================================================== */ +/* ===================================================== DEVPWRSTATUS ====================================================== */ +/* ======================================================= SRAMCTRL ======================================================== */ +/* ======================================== PWRCTRL SRAMCTRL SRAMLIGHTSLEEP [8..19] ======================================== */ +typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP */ + PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_ALL = 255, /*!< ALL : Enable LIGHT SLEEP for ALL SRAMs */ + PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_DIS = 0, /*!< DIS : Disables LIGHT SLEEP for ALL SRAMs */ +} PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Enum; + +/* ======================================= PWRCTRL SRAMCTRL SRAMMASTERCLKGATE [2..2] ======================================= */ +typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE */ + PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_EN = 1, /*!< EN : Enable Master SRAM Clock Gate */ + PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_DIS = 0, /*!< DIS : Disables Master SRAM Clock Gating */ +} PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Enum; + +/* ========================================== PWRCTRL SRAMCTRL SRAMCLKGATE [1..1] ========================================== */ +typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMCLKGATE */ + PWRCTRL_SRAMCTRL_SRAMCLKGATE_EN = 1, /*!< EN : Enable Individual SRAM Clock Gating */ + PWRCTRL_SRAMCTRL_SRAMCLKGATE_DIS = 0, /*!< DIS : Disables Individual SRAM Clock Gating */ +} PWRCTRL_SRAMCTRL_SRAMCLKGATE_Enum; + +/* ======================================================= ADCSTATUS ======================================================= */ +/* ========================================================= MISC ========================================================== */ +/* ============================================ PWRCTRL MISC MEMVRLPBLE [6..6] ============================================= */ +typedef enum { /*!< PWRCTRL_MISC_MEMVRLPBLE */ + PWRCTRL_MISC_MEMVRLPBLE_EN = 1, /*!< EN : Mem VR can go to lp mode even when BLE is powered on. */ + PWRCTRL_MISC_MEMVRLPBLE_DIS = 0, /*!< DIS : Mem VR will stay in active mode when BLE is powered on. */ +} PWRCTRL_MISC_MEMVRLPBLE_Enum; + +/* ===================================================== DEVPWREVENTEN ===================================================== */ +/* ======================================= PWRCTRL DEVPWREVENTEN BURSTEVEN [31..31] ======================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BURSTEVEN */ + PWRCTRL_DEVPWREVENTEN_BURSTEVEN_EN = 1, /*!< EN : Enable BURST status event */ + PWRCTRL_DEVPWREVENTEN_BURSTEVEN_DIS = 0, /*!< DIS : Disable BURST status event */ +} PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Enum; + +/* ==================================== PWRCTRL DEVPWREVENTEN BURSTFEATUREEVEN [30..30] ==================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN */ + PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_EN = 1,/*!< EN : Enable BURSTFEATURE status event */ + PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_DIS = 0,/*!< DIS : Disable BURSTFEATURE status event */ +} PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Enum; + +/* ===================================== PWRCTRL DEVPWREVENTEN BLEFEATUREEVEN [29..29] ===================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN */ + PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_EN = 1, /*!< EN : Enable BLEFEATURE status event */ + PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_DIS = 0, /*!< DIS : Disable BLEFEATURE status event */ +} PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN BLELEVEN [8..8] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BLELEVEN */ + PWRCTRL_DEVPWREVENTEN_BLELEVEN_EN = 1, /*!< EN : Enable BLE power-on status event */ + PWRCTRL_DEVPWREVENTEN_BLELEVEN_DIS = 0, /*!< DIS : Disable BLE power-on status event */ +} PWRCTRL_DEVPWREVENTEN_BLELEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN PDMEVEN [7..7] ========================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_PDMEVEN */ + PWRCTRL_DEVPWREVENTEN_PDMEVEN_EN = 1, /*!< EN : Enable PDM power-on status event */ + PWRCTRL_DEVPWREVENTEN_PDMEVEN_DIS = 0, /*!< DIS : Disable PDM power-on status event */ +} PWRCTRL_DEVPWREVENTEN_PDMEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN MSPIEVEN [6..6] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MSPIEVEN */ + PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN = 1, /*!< EN : Enable MSPI power-on status event */ + PWRCTRL_DEVPWREVENTEN_MSPIEVEN_DIS = 0, /*!< DIS : Disable MSPI power-on status event */ +} PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN ADCEVEN [5..5] ========================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_ADCEVEN */ + PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN = 1, /*!< EN : Enable ADC power-on status event */ + PWRCTRL_DEVPWREVENTEN_ADCEVEN_DIS = 0, /*!< DIS : Disable ADC power-on status event */ +} PWRCTRL_DEVPWREVENTEN_ADCEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN HCPCEVEN [4..4] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPCEVEN */ + PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN = 1, /*!< EN : Enable HCPC power-on status event */ + PWRCTRL_DEVPWREVENTEN_HCPCEVEN_DIS = 0, /*!< DIS : Disable HCPC power-on status event */ +} PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN HCPBEVEN [3..3] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPBEVEN */ + PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN = 1, /*!< EN : Enable HCPB power-on status event */ + PWRCTRL_DEVPWREVENTEN_HCPBEVEN_DIS = 0, /*!< DIS : Disable HCPB power-on status event */ +} PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN HCPAEVEN [2..2] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPAEVEN */ + PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN = 1, /*!< EN : Enable HCPA power-on status event */ + PWRCTRL_DEVPWREVENTEN_HCPAEVEN_DIS = 0, /*!< DIS : Disable HCPA power-on status event */ +} PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN MCUHEVEN [1..1] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MCUHEVEN */ + PWRCTRL_DEVPWREVENTEN_MCUHEVEN_EN = 1, /*!< EN : Enable MCHU power-on status event */ + PWRCTRL_DEVPWREVENTEN_MCUHEVEN_DIS = 0, /*!< DIS : Disable MCUH power-on status event */ +} PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN MCULEVEN [0..0] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MCULEVEN */ + PWRCTRL_DEVPWREVENTEN_MCULEVEN_EN = 1, /*!< EN : Enable MCUL power-on status event */ + PWRCTRL_DEVPWREVENTEN_MCULEVEN_DIS = 0, /*!< DIS : Disable MCUL power-on status event */ +} PWRCTRL_DEVPWREVENTEN_MCULEVEN_Enum; + +/* ===================================================== MEMPWREVENTEN ===================================================== */ +/* ======================================= PWRCTRL MEMPWREVENTEN CACHEB2EN [31..31] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_CACHEB2EN */ + PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN = 1, /*!< EN : Enable CACHE BANK 2 status event */ + PWRCTRL_MEMPWREVENTEN_CACHEB2EN_DIS = 0, /*!< DIS : Disable CACHE BANK 2 status event */ +} PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Enum; + +/* ======================================= PWRCTRL MEMPWREVENTEN CACHEB0EN [30..30] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_CACHEB0EN */ + PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN = 1, /*!< EN : Enable CACHE BANK 0 status event */ + PWRCTRL_MEMPWREVENTEN_CACHEB0EN_DIS = 0, /*!< DIS : Disable CACHE BANK 0 status event */ +} PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Enum; + +/* ======================================== PWRCTRL MEMPWREVENTEN FLASH1EN [14..14] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_FLASH1EN */ + PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN = 1, /*!< EN : Enable FLASH status event */ + PWRCTRL_MEMPWREVENTEN_FLASH1EN_DIS = 0, /*!< DIS : Disables FLASH status event */ +} PWRCTRL_MEMPWREVENTEN_FLASH1EN_Enum; + +/* ======================================== PWRCTRL MEMPWREVENTEN FLASH0EN [13..13] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_FLASH0EN */ + PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN = 1, /*!< EN : Enable FLASH status event */ + PWRCTRL_MEMPWREVENTEN_FLASH0EN_DIS = 0, /*!< DIS : Disables FLASH status event */ +} PWRCTRL_MEMPWREVENTEN_FLASH0EN_Enum; + +/* ========================================= PWRCTRL MEMPWREVENTEN SRAMEN [3..12] ========================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_SRAMEN */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_NONE = 0, /*!< NONE : Disable SRAM power-on status event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN = 1, /*!< GROUP0EN : Enable SRAM group0 (0KB-32KB) power on status event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN = 2, /*!< GROUP1EN : Enable SRAM group1 (32KB-64KB) power on status event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN = 4, /*!< GROUP2EN : Enable SRAM group2 (64KB-96KB) power on status event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN = 8, /*!< GROUP3EN : Enable SRAM group3 (96KB-128KB) power on status event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN = 16, /*!< GROUP4EN : Enable SRAM group4 (128KB-160KB) power on status + event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN = 32, /*!< GROUP5EN : Enable SRAM group5 (160KB-192KB) power on status + event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN = 64, /*!< GROUP6EN : Enable SRAM group6 (192KB-224KB) power on status + event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN = 128, /*!< GROUP7EN : Enable SRAM group7 (224KB-256KB) power on status + event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN = 256, /*!< GROUP8EN : Enable SRAM group8 (256KB-288KB) power on status + event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN = 512, /*!< GROUP9EN : Enable SRAM group9 (288KB-320KB) power on status + event */ +} PWRCTRL_MEMPWREVENTEN_SRAMEN_Enum; + +/* ========================================== PWRCTRL MEMPWREVENTEN DTCMEN [0..2] ========================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_DTCMEN */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_NONE = 0, /*!< NONE : Do not enable DTCM power-on status event */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN = 1,/*!< GROUP0DTCM0EN : Enable GROUP0_DTCM0 power on status event */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM1EN = 2,/*!< GROUP0DTCM1EN : Enable GROUP0_DTCM1 power on status event */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN = 3, /*!< GROUP0EN : Enable DTCMs in group0 power on status event */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP1EN = 4, /*!< GROUP1EN : Enable DTCMs in group1 power on status event */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL = 7, /*!< ALL : Enable all DTCM power on status event */ +} PWRCTRL_MEMPWREVENTEN_DTCMEN_Enum; + + + +/* =========================================================================================================================== */ +/* ================ RSTGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* ========================================================= SWPOI ========================================================= */ +/* ============================================= RSTGEN SWPOI SWPOIKEY [0..7] ============================================== */ +typedef enum { /*!< RSTGEN_SWPOI_SWPOIKEY */ + RSTGEN_SWPOI_SWPOIKEY_KEYVALUE = 27, /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset. */ +} RSTGEN_SWPOI_SWPOIKEY_Enum; + +/* ========================================================= SWPOR ========================================================= */ +/* ============================================= RSTGEN SWPOR SWPORKEY [0..7] ============================================== */ +typedef enum { /*!< RSTGEN_SWPOR_SWPORKEY */ + RSTGEN_SWPOR_SWPORKEY_KEYVALUE = 212, /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset. */ +} RSTGEN_SWPOR_SWPORKEY_Enum; + +/* ======================================================== TPIURST ======================================================== */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ========================================================= STAT ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTRLOW ========================================================= */ +/* ========================================================= CTRUP ========================================================= */ +/* =============================================== RTC CTRUP CTERR [31..31] ================================================ */ +typedef enum { /*!< RTC_CTRUP_CTERR */ + RTC_CTRUP_CTERR_NOERR = 0, /*!< NOERR : No read error occurred */ + RTC_CTRUP_CTERR_RDERR = 1, /*!< RDERR : Read error occurred */ +} RTC_CTRUP_CTERR_Enum; + +/* ================================================ RTC CTRUP CEB [28..28] ================================================= */ +typedef enum { /*!< RTC_CTRUP_CEB */ + RTC_CTRUP_CEB_DIS = 0, /*!< DIS : Disable the Century bit from changing */ + RTC_CTRUP_CEB_EN = 1, /*!< EN : Enable the Century bit to change */ +} RTC_CTRUP_CEB_Enum; + +/* ================================================= RTC CTRUP CB [27..27] ================================================= */ +typedef enum { /*!< RTC_CTRUP_CB */ + RTC_CTRUP_CB_2000 = 0, /*!< 2000 : Century is 2000s */ + RTC_CTRUP_CB_1900_2100 = 1, /*!< 1900_2100 : Century is 1900s/2100s */ +} RTC_CTRUP_CB_Enum; + +/* ======================================================== ALMLOW ========================================================= */ +/* ========================================================= ALMUP ========================================================= */ +/* ======================================================== RTCCTL ========================================================= */ +/* =============================================== RTC RTCCTL HR1224 [5..5] ================================================ */ +typedef enum { /*!< RTC_RTCCTL_HR1224 */ + RTC_RTCCTL_HR1224_24HR = 0, /*!< 24HR : Hours in 24 hour mode */ + RTC_RTCCTL_HR1224_12HR = 1, /*!< 12HR : Hours in 12 hour mode */ +} RTC_RTCCTL_HR1224_Enum; + +/* ================================================ RTC RTCCTL RSTOP [4..4] ================================================ */ +typedef enum { /*!< RTC_RTCCTL_RSTOP */ + RTC_RTCCTL_RSTOP_RUN = 0, /*!< RUN : Allow the RTC input clock to run */ + RTC_RTCCTL_RSTOP_STOP = 1, /*!< STOP : Stop the RTC input clock */ +} RTC_RTCCTL_RSTOP_Enum; + +/* ================================================= RTC RTCCTL RPT [1..3] ================================================= */ +typedef enum { /*!< RTC_RTCCTL_RPT */ + RTC_RTCCTL_RPT_DIS = 0, /*!< DIS : Alarm interrupt disabled */ + RTC_RTCCTL_RPT_YEAR = 1, /*!< YEAR : Interrupt every year */ + RTC_RTCCTL_RPT_MONTH = 2, /*!< MONTH : Interrupt every month */ + RTC_RTCCTL_RPT_WEEK = 3, /*!< WEEK : Interrupt every week */ + RTC_RTCCTL_RPT_DAY = 4, /*!< DAY : Interrupt every day */ + RTC_RTCCTL_RPT_HR = 5, /*!< HR : Interrupt every hour */ + RTC_RTCCTL_RPT_MIN = 6, /*!< MIN : Interrupt every minute */ + RTC_RTCCTL_RPT_SEC = 7, /*!< SEC : Interrupt every second/10th/100th */ +} RTC_RTCCTL_RPT_Enum; + +/* ================================================ RTC RTCCTL WRTC [0..0] ================================================= */ +typedef enum { /*!< RTC_RTCCTL_WRTC */ + RTC_RTCCTL_WRTC_DIS = 0, /*!< DIS : Counter writes are disabled */ + RTC_RTCCTL_WRTC_EN = 1, /*!< EN : Counter writes are enabled */ +} RTC_RTCCTL_WRTC_Enum; + +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ SCARD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SR =========================================================== */ +/* ================================================== SCARD SR FHF [6..6] ================================================== */ +typedef enum { /*!< SCARD_SR_FHF */ + SCARD_SR_FHF_HALFFULL = 1, /*!< HALFFULL : FIFO is half full. */ +} SCARD_SR_FHF_Enum; + +/* ================================================ SCARD SR FT2REND [5..5] ================================================ */ +typedef enum { /*!< SCARD_SR_FT2REND */ + SCARD_SR_FT2REND_CMPL = 1, /*!< CMPL : TX to RX completed. */ + SCARD_SR_FT2REND_NOTCMPL = 0, /*!< NOTCMPL : TX to RX not completed. */ +} SCARD_SR_FT2REND_Enum; + +/* ================================================== SCARD SR PE [4..4] =================================================== */ +typedef enum { /*!< SCARD_SR_PE */ + SCARD_SR_PE_PEERR = 1, /*!< PEERR : Parity error. */ + SCARD_SR_PE_PENONE = 0, /*!< PENONE : No parity error. */ +} SCARD_SR_PE_Enum; + +/* ================================================== SCARD SR OVR [3..3] ================================================== */ +typedef enum { /*!< SCARD_SR_OVR */ + SCARD_SR_OVR_RXOVR = 1, /*!< RXOVR : RX FIFO overflow. */ + SCARD_SR_OVR_RXOVRNONE = 0, /*!< RXOVRNONE : RX FIFO no overflow. */ +} SCARD_SR_OVR_Enum; + +/* ================================================== SCARD SR FER [2..2] ================================================== */ +typedef enum { /*!< SCARD_SR_FER */ + SCARD_SR_FER_FRAMINGERR = 1, /*!< FRAMINGERR : Framing error. */ + SCARD_SR_FER_NOFRAMINGERR = 0, /*!< NOFRAMINGERR : No framing error detected. */ +} SCARD_SR_FER_Enum; + +/* ================================================ SCARD SR TBERBF [1..1] ================================================= */ +typedef enum { /*!< SCARD_SR_TBERBF */ + SCARD_SR_TBERBF_TXFIFOEMPTY = 1, /*!< TXFIFOEMPTY : Transmit: FIFO empty. */ + SCARD_SR_TBERBF_TXFIFONOTEMPTY = 0, /*!< TXFIFONOTEMPTY : Transmit: FIFO not empty. */ +} SCARD_SR_TBERBF_Enum; + +/* ================================================== SCARD SR FNE [0..0] ================================================== */ +typedef enum { /*!< SCARD_SR_FNE */ + SCARD_SR_FNE_NOTEMPTY = 1, /*!< NOTEMPTY : RX FIFO not empty. */ + SCARD_SR_FNE_EMPTY = 0, /*!< EMPTY : RX FIFO empty. */ +} SCARD_SR_FNE_Enum; + +/* ========================================================== IER ========================================================== */ +/* ========================================================== TCR ========================================================== */ +/* ========================================================== UCR ========================================================== */ +/* ========================================================== DR =========================================================== */ +/* ========================================================= BPRL ========================================================== */ +/* ========================================================= BPRH ========================================================== */ +/* ========================================================= UCR1 ========================================================== */ +/* ========================================================== SR1 ========================================================== */ +/* ================================================= SCARD SR1 IDLE [3..3] ================================================= */ +typedef enum { /*!< SCARD_SR1_IDLE */ + SCARD_SR1_IDLE_IDLE = 1, /*!< IDLE : ISO7816 idle. */ + SCARD_SR1_IDLE_ACTIVE = 0, /*!< ACTIVE : ISO7816 active. */ +} SCARD_SR1_IDLE_Enum; + +/* =============================================== SCARD SR1 SYNCEND [2..2] ================================================ */ +typedef enum { /*!< SCARD_SR1_SYNCEND */ + SCARD_SR1_SYNCEND_CMPL = 1, /*!< CMPL : Synchronization complete. */ + SCARD_SR1_SYNCEND_INCMPL = 0, /*!< INCMPL : Incomplete. */ +} SCARD_SR1_SYNCEND_Enum; + +/* ================================================= SCARD SR1 PRL [1..1] ================================================== */ +typedef enum { /*!< SCARD_SR1_PRL */ + SCARD_SR1_PRL_INSREM = 1, /*!< INSREM : Card inserted/removed. */ +} SCARD_SR1_PRL_Enum; + +/* =============================================== SCARD SR1 ECNTOVER [0..0] =============================================== */ +typedef enum { /*!< SCARD_SR1_ECNTOVER */ + SCARD_SR1_ECNTOVER_OVR = 1, /*!< OVR : ETU overflow. */ +} SCARD_SR1_ECNTOVER_Enum; + +/* ========================================================= IER1 ========================================================== */ +/* ========================================================= ECNTL ========================================================= */ +/* ========================================================= ECNTH ========================================================= */ +/* ========================================================== GTR ========================================================== */ +/* ======================================================== RETXCNT ======================================================== */ +/* ====================================================== RETXCNTRMI ======================================================= */ +/* ======================================================== CLKCTRL ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ SECURITY ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +/* ============================================= SECURITY CTRL FUNCTION [4..7] ============================================= */ +typedef enum { /*!< SECURITY_CTRL_FUNCTION */ + SECURITY_CTRL_FUNCTION_CRC32 = 0, /*!< CRC32 : Perform CRC32 operation */ +} SECURITY_CTRL_FUNCTION_Enum; + +/* ======================================================== SRCADDR ======================================================== */ +/* ========================================================== LEN ========================================================== */ +/* ======================================================== RESULT ========================================================= */ +/* ======================================================= LOCKCTRL ======================================================== */ +/* ============================================ SECURITY LOCKCTRL SELECT [0..7] ============================================ */ +typedef enum { /*!< SECURITY_LOCKCTRL_SELECT */ + SECURITY_LOCKCTRL_SELECT_CUSTOMER_KEY = 1, /*!< CUSTOMER_KEY : Unlock Customer Key (access to top half of info0) */ + SECURITY_LOCKCTRL_SELECT_NONE = 0, /*!< NONE : Lock Control should be set to NONE when not in use. */ +} SECURITY_LOCKCTRL_SELECT_Enum; + +/* ======================================================= LOCKSTAT ======================================================== */ +/* =========================================== SECURITY LOCKSTAT STATUS [0..31] ============================================ */ +typedef enum { /*!< SECURITY_LOCKSTAT_STATUS */ + SECURITY_LOCKSTAT_STATUS_CUSTOMER_KEY = 1, /*!< CUSTOMER_KEY : Customer Key is unlocked (access is granted to + top half of info0) */ + SECURITY_LOCKSTAT_STATUS_NONE = 0, /*!< NONE : No resources are unlocked */ +} SECURITY_LOCKSTAT_STATUS_Enum; + +/* ========================================================= KEY0 ========================================================== */ +/* ========================================================= KEY1 ========================================================== */ +/* ========================================================= KEY2 ========================================================== */ +/* ========================================================= KEY3 ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DR =========================================================== */ +/* =============================================== UART0 DR OEDATA [11..11] ================================================ */ +typedef enum { /*!< UART0_DR_OEDATA */ + UART0_DR_OEDATA_NOERR = 0, /*!< NOERR : No error on UART OEDATA, overrun error indicator. */ + UART0_DR_OEDATA_ERR = 1, /*!< ERR : Error on UART OEDATA, overrun error indicator. */ +} UART0_DR_OEDATA_Enum; + +/* =============================================== UART0 DR BEDATA [10..10] ================================================ */ +typedef enum { /*!< UART0_DR_BEDATA */ + UART0_DR_BEDATA_NOERR = 0, /*!< NOERR : No error on UART BEDATA, break error indicator. */ + UART0_DR_BEDATA_ERR = 1, /*!< ERR : Error on UART BEDATA, break error indicator. */ +} UART0_DR_BEDATA_Enum; + +/* ================================================ UART0 DR PEDATA [9..9] ================================================= */ +typedef enum { /*!< UART0_DR_PEDATA */ + UART0_DR_PEDATA_NOERR = 0, /*!< NOERR : No error on UART PEDATA, parity error indicator. */ + UART0_DR_PEDATA_ERR = 1, /*!< ERR : Error on UART PEDATA, parity error indicator. */ +} UART0_DR_PEDATA_Enum; + +/* ================================================ UART0 DR FEDATA [8..8] ================================================= */ +typedef enum { /*!< UART0_DR_FEDATA */ + UART0_DR_FEDATA_NOERR = 0, /*!< NOERR : No error on UART FEDATA, framing error indicator. */ + UART0_DR_FEDATA_ERR = 1, /*!< ERR : Error on UART FEDATA, framing error indicator. */ +} UART0_DR_FEDATA_Enum; + +/* ========================================================== RSR ========================================================== */ +/* ================================================ UART0 RSR OESTAT [3..3] ================================================ */ +typedef enum { /*!< UART0_RSR_OESTAT */ + UART0_RSR_OESTAT_NOERR = 0, /*!< NOERR : No error on UART OESTAT, overrun error indicator. */ + UART0_RSR_OESTAT_ERR = 1, /*!< ERR : Error on UART OESTAT, overrun error indicator. */ +} UART0_RSR_OESTAT_Enum; + +/* ================================================ UART0 RSR BESTAT [2..2] ================================================ */ +typedef enum { /*!< UART0_RSR_BESTAT */ + UART0_RSR_BESTAT_NOERR = 0, /*!< NOERR : No error on UART BESTAT, break error indicator. */ + UART0_RSR_BESTAT_ERR = 1, /*!< ERR : Error on UART BESTAT, break error indicator. */ +} UART0_RSR_BESTAT_Enum; + +/* ================================================ UART0 RSR PESTAT [1..1] ================================================ */ +typedef enum { /*!< UART0_RSR_PESTAT */ + UART0_RSR_PESTAT_NOERR = 0, /*!< NOERR : No error on UART PESTAT, parity error indicator. */ + UART0_RSR_PESTAT_ERR = 1, /*!< ERR : Error on UART PESTAT, parity error indicator. */ +} UART0_RSR_PESTAT_Enum; + +/* ================================================ UART0 RSR FESTAT [0..0] ================================================ */ +typedef enum { /*!< UART0_RSR_FESTAT */ + UART0_RSR_FESTAT_NOERR = 0, /*!< NOERR : No error on UART FESTAT, framing error indicator. */ + UART0_RSR_FESTAT_ERR = 1, /*!< ERR : Error on UART FESTAT, framing error indicator. */ +} UART0_RSR_FESTAT_Enum; + +/* ========================================================== FR =========================================================== */ +/* ================================================= UART0 FR TXFE [7..7] ================================================== */ +typedef enum { /*!< UART0_FR_TXFE */ + UART0_FR_TXFE_XMTFIFO_EMPTY = 1, /*!< XMTFIFO_EMPTY : Transmit fifo is empty. */ +} UART0_FR_TXFE_Enum; + +/* ================================================= UART0 FR RXFF [6..6] ================================================== */ +typedef enum { /*!< UART0_FR_RXFF */ + UART0_FR_RXFF_RCVFIFO_FULL = 1, /*!< RCVFIFO_FULL : Receive fifo is full. */ +} UART0_FR_RXFF_Enum; + +/* ================================================= UART0 FR TXFF [5..5] ================================================== */ +typedef enum { /*!< UART0_FR_TXFF */ + UART0_FR_TXFF_XMTFIFO_FULL = 1, /*!< XMTFIFO_FULL : Transmit fifo is full. */ +} UART0_FR_TXFF_Enum; + +/* ================================================= UART0 FR RXFE [4..4] ================================================== */ +typedef enum { /*!< UART0_FR_RXFE */ + UART0_FR_RXFE_RCVFIFO_EMPTY = 1, /*!< RCVFIFO_EMPTY : Receive fifo is empty. */ +} UART0_FR_RXFE_Enum; + +/* ================================================= UART0 FR BUSY [3..3] ================================================== */ +typedef enum { /*!< UART0_FR_BUSY */ + UART0_FR_BUSY_BUSY = 1, /*!< BUSY : UART busy indicator. */ +} UART0_FR_BUSY_Enum; + +/* ================================================== UART0 FR DCD [2..2] ================================================== */ +typedef enum { /*!< UART0_FR_DCD */ + UART0_FR_DCD_DETECTED = 1, /*!< DETECTED : Data carrier detect detected. */ +} UART0_FR_DCD_Enum; + +/* ================================================== UART0 FR DSR [1..1] ================================================== */ +typedef enum { /*!< UART0_FR_DSR */ + UART0_FR_DSR_READY = 1, /*!< READY : Data set ready. */ +} UART0_FR_DSR_Enum; + +/* ================================================== UART0 FR CTS [0..0] ================================================== */ +typedef enum { /*!< UART0_FR_CTS */ + UART0_FR_CTS_CLEARTOSEND = 1, /*!< CLEARTOSEND : Clear to send is indicated. */ +} UART0_FR_CTS_Enum; + +/* ========================================================= ILPR ========================================================== */ +/* ========================================================= IBRD ========================================================== */ +/* ========================================================= FBRD ========================================================== */ +/* ========================================================= LCRH ========================================================== */ +/* ========================================================== CR =========================================================== */ +/* ================================================ UART0 CR CLKSEL [4..6] ================================================= */ +typedef enum { /*!< UART0_CR_CLKSEL */ + UART0_CR_CLKSEL_NOCLK = 0, /*!< NOCLK : No UART clock. This is the low power default. */ + UART0_CR_CLKSEL_24MHZ = 1, /*!< 24MHZ : 24 MHz clock. */ + UART0_CR_CLKSEL_12MHZ = 2, /*!< 12MHZ : 12 MHz clock. */ + UART0_CR_CLKSEL_6MHZ = 3, /*!< 6MHZ : 6 MHz clock. */ + UART0_CR_CLKSEL_3MHZ = 4, /*!< 3MHZ : 3 MHz clock. */ +} UART0_CR_CLKSEL_Enum; + +/* ========================================================= IFLS ========================================================== */ +/* ========================================================== IER ========================================================== */ +/* ========================================================== IES ========================================================== */ +/* ========================================================== MIS ========================================================== */ +/* ========================================================== IEC ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ VCOMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* =============================================== VCOMP CFG LVLSEL [16..19] =============================================== */ +typedef enum { /*!< VCOMP_CFG_LVLSEL */ + VCOMP_CFG_LVLSEL_0P58V = 0, /*!< 0P58V : Set Reference input to 0.58 Volts. */ + VCOMP_CFG_LVLSEL_0P77V = 1, /*!< 0P77V : Set Reference input to 0.77 Volts. */ + VCOMP_CFG_LVLSEL_0P97V = 2, /*!< 0P97V : Set Reference input to 0.97 Volts. */ + VCOMP_CFG_LVLSEL_1P16V = 3, /*!< 1P16V : Set Reference input to 1.16 Volts. */ + VCOMP_CFG_LVLSEL_1P35V = 4, /*!< 1P35V : Set Reference input to 1.35 Volts. */ + VCOMP_CFG_LVLSEL_1P55V = 5, /*!< 1P55V : Set Reference input to 1.55 Volts. */ + VCOMP_CFG_LVLSEL_1P74V = 6, /*!< 1P74V : Set Reference input to 1.74 Volts. */ + VCOMP_CFG_LVLSEL_1P93V = 7, /*!< 1P93V : Set Reference input to 1.93 Volts. */ + VCOMP_CFG_LVLSEL_2P13V = 8, /*!< 2P13V : Set Reference input to 2.13 Volts. */ + VCOMP_CFG_LVLSEL_2P32V = 9, /*!< 2P32V : Set Reference input to 2.32 Volts. */ + VCOMP_CFG_LVLSEL_2P51V = 10, /*!< 2P51V : Set Reference input to 2.51 Volts. */ + VCOMP_CFG_LVLSEL_2P71V = 11, /*!< 2P71V : Set Reference input to 2.71 Volts. */ + VCOMP_CFG_LVLSEL_2P90V = 12, /*!< 2P90V : Set Reference input to 2.90 Volts. */ + VCOMP_CFG_LVLSEL_3P09V = 13, /*!< 3P09V : Set Reference input to 3.09 Volts. */ + VCOMP_CFG_LVLSEL_3P29V = 14, /*!< 3P29V : Set Reference input to 3.29 Volts. */ + VCOMP_CFG_LVLSEL_3P48V = 15, /*!< 3P48V : Set Reference input to 3.48 Volts. */ +} VCOMP_CFG_LVLSEL_Enum; + +/* ================================================= VCOMP CFG NSEL [8..9] ================================================= */ +typedef enum { /*!< VCOMP_CFG_NSEL */ + VCOMP_CFG_NSEL_VREFEXT1 = 0, /*!< VREFEXT1 : Use external reference 1 for reference input. */ + VCOMP_CFG_NSEL_VREFEXT2 = 1, /*!< VREFEXT2 : Use external reference 2 for reference input. */ + VCOMP_CFG_NSEL_VREFEXT3 = 2, /*!< VREFEXT3 : Use external reference 3 for reference input. */ + VCOMP_CFG_NSEL_DAC = 3, /*!< DAC : Use DAC output selected by LVLSEL for reference input. */ +} VCOMP_CFG_NSEL_Enum; + +/* ================================================= VCOMP CFG PSEL [0..1] ================================================= */ +typedef enum { /*!< VCOMP_CFG_PSEL */ + VCOMP_CFG_PSEL_VDDADJ = 0, /*!< VDDADJ : Use VDDADJ for the positive input. */ + VCOMP_CFG_PSEL_VTEMP = 1, /*!< VTEMP : Use the temperature sensor output for the positive input. + Note: If this channel is selected for PSEL, the bandap + circuit required for temperature comparisons will automatically + turn on. The bandgap circuit requires 11us to stabalize. */ + VCOMP_CFG_PSEL_VEXT1 = 2, /*!< VEXT1 : Use external voltage 0 for positive input. */ + VCOMP_CFG_PSEL_VEXT2 = 3, /*!< VEXT2 : Use external voltage 1 for positive input. */ +} VCOMP_CFG_PSEL_Enum; + +/* ========================================================= STAT ========================================================== */ +/* =============================================== VCOMP STAT PWDSTAT [1..1] =============================================== */ +typedef enum { /*!< VCOMP_STAT_PWDSTAT */ + VCOMP_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : The voltage comparator is powered down. */ +} VCOMP_STAT_PWDSTAT_Enum; + +/* =============================================== VCOMP STAT CMPOUT [0..0] ================================================ */ +typedef enum { /*!< VCOMP_STAT_CMPOUT */ + VCOMP_STAT_CMPOUT_VOUT_LOW = 0, /*!< VOUT_LOW : The negative input of the comparator is greater than + the positive input. */ + VCOMP_STAT_CMPOUT_VOUT_HIGH = 1, /*!< VOUT_HIGH : The positive input of the comparator is greater + than the negative input. */ +} VCOMP_STAT_CMPOUT_Enum; + +/* ======================================================== PWDKEY ========================================================= */ +/* ============================================== VCOMP PWDKEY PWDKEY [0..31] ============================================== */ +typedef enum { /*!< VCOMP_PWDKEY_PWDKEY */ + VCOMP_PWDKEY_PWDKEY_Key = 55, /*!< Key : Key */ +} VCOMP_PWDKEY_PWDKEY_Enum; + +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* ================================================ WDT CFG CLKSEL [24..26] ================================================ */ +typedef enum { /*!< WDT_CFG_CLKSEL */ + WDT_CFG_CLKSEL_OFF = 0, /*!< OFF : Low Power Mode. This setting disables the watch dog timer. */ + WDT_CFG_CLKSEL_128HZ = 1, /*!< 128HZ : 128 Hz LFRC clock. */ + WDT_CFG_CLKSEL_16HZ = 2, /*!< 16HZ : 16 Hz LFRC clock. */ + WDT_CFG_CLKSEL_1HZ = 3, /*!< 1HZ : 1 Hz LFRC clock. */ + WDT_CFG_CLKSEL_1_16HZ = 4, /*!< 1_16HZ : 1/16th Hz LFRC clock. */ +} WDT_CFG_CLKSEL_Enum; + +/* ========================================================= RSTRT ========================================================= */ +/* ================================================ WDT RSTRT RSTRT [0..7] ================================================= */ +typedef enum { /*!< WDT_RSTRT_RSTRT */ + WDT_RSTRT_RSTRT_KEYVALUE = 178, /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart + the WDT. This is a write only register. */ +} WDT_RSTRT_RSTRT_Enum; + +/* ========================================================= LOCK ========================================================== */ +/* ================================================= WDT LOCK LOCK [0..7] ================================================== */ +typedef enum { /*!< WDT_LOCK_LOCK */ + WDT_LOCK_LOCK_KEYVALUE = 58, /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock + the WDT. */ +} WDT_LOCK_LOCK_Enum; + +/* ========================================================= COUNT ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + +/** @} */ /* End of group EnumValue_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#ifdef OVERFLOW_RESTORE +#define OVERFLOW OVERFLOW_RESTORE +#undef OVERFLOW_RESTORE +#endif // OVERFLOW_RESTORE + +#endif /* APOLLO3_H */ + + +/** @} */ /* End of group apollo3 */ + +/** @} */ /* End of group Ambiq Micro */ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/system_apollo3.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/system_apollo3.h new file mode 100644 index 0000000..3ddfb26 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/system_apollo3.h @@ -0,0 +1,70 @@ +//***************************************************************************** +// +//! @file system_Apollo3.h +//! +//! @brief Ambiq Micro Apollo3 MCU specific functions. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef SYSTEM_APOLLO3_H +#define SYSTEM_APOLLO3_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void SystemInit (void); +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif // SYSTEM_APOLLO3_H + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Source/system_apollo3.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Source/system_apollo3.c new file mode 100644 index 0000000..896e54e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Source/system_apollo3.c @@ -0,0 +1,114 @@ +//***************************************************************************** +// +//! @file system_apollo3.c +//! +//! @brief Ambiq Micro Apollo3 MCU specific functions. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include "system_apollo3.h" +#include "apollo3.h" + +//***************************************************************************** +// +// Defines +// +//***************************************************************************** + +// +// Clocks +// +#define __HSI (6000000UL) +#define __XTAL (32768UL) // Crystal Oscillator frequency +#define __SYS_OSC_CLK (48000000) // Main oscillator frequency +#define __SYSTEM_CLOCK (1*__SYS_OSC_CLK) + +// +// Initialize SystemCoreClock with the system core clock frequency value +// achieved after system intitialization. +// This means system core clock frequency after call to SystemInit() +// +uint32_t SystemCoreClock = __SYSTEM_CLOCK; // System Clock Frequency (Core Clock) + +//***************************************************************************** +// +//! @brief Set the global clock frequncy. +//! +//! This function sets the global clock frequency. +//! +//! @return None. +// +//***************************************************************************** +void +SystemCoreClockUpdate(void) +{ + // + // Calculate the system frequency based upon the current register settings. + // This function can be used to retrieve the system core clock frequeny + // after user changed register sittings. + // + SystemCoreClock = __SYS_OSC_CLK / (CLKGEN->CCTRL_b.CORESEL + 1); +} + +//***************************************************************************** +// +//! @brief Initialize the system. +//! +//! This function sets up the microcontroller system. +//! +//! @return None. +// +//***************************************************************************** +void +SystemInit(void) +{ + // + // Initialize the system + // Do not use global variables because this function is called before + // reaching pre-main. RW section maybe overwritten afterwards. + // + SystemCoreClock = __SYSTEM_CLOCK; + + CLKGEN->CLKKEY = 0x47; // Enable write to CCTRL + CLKGEN->CCTRL_b.CORESEL = 0; // Div by 1 for 48MHz + CLKGEN->CLKKEY = 0; // Disable write to CCTRL +} + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/version_cmsis_info.txt b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/version_cmsis_info.txt new file mode 100644 index 0000000..d78a88c --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/version_cmsis_info.txt @@ -0,0 +1,24 @@ + +Last updated: August 15, 2019 + +This file contains origination information about the various +CMSIS header and library files located in this folder. + + +ARM/Include/: +AmbiqSuite SDK file: Pack Origination: +cmsis*.h CMSIS/5.6.0/CMSIS/Core/Include/ +core_cm4.h CMSIS/5.6.0/CMSIS/Core/Include/ +mpu_armv7.h CMSIS/5.6.0/CMSIS/Core/Include/ +arm_math.h CMSIS/5.6.0/CMSIS/Include/ + + +ARM/Lib/ARM/: +AmbiqSuite SDK file: Pack Origination: +arm_cortexM4lf_math.lib CMSIS/5.6.0/CMSIS/DSP/Lib/ARM/ +arm_cortexM4l_math.lib CMSIS/5.6.0/CMSIS/DSP/Lib/ARM/ +libarm_cortexM4lf_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/GCC/ +libarm_cortexM4l_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/GCC/ +iar_cortexM4lf_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/IAR/ +iar_cortexM4l_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/IAR/ + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/am_sdk_version.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/am_sdk_version.h new file mode 100644 index 0000000..a346225 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/am_sdk_version.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// am_sdk_version.h +//! @file +//! +//! @brief Defines SDK version. +//! +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_SDK_VERSION_H +#define AM_SDK_VERSION_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macros to define HAL SDK version. +// +//***************************************************************************** +// +// Define the current HAL version. +// +#ifndef AM_HAL_VERSION_MAJ +#define AM_HAL_VERSION_MAJ 2 +#define AM_HAL_VERSION_MIN 4 +#define AM_HAL_VERSION_REV 2 +#endif // AM_HAL_VERSION_MAJ + +#ifdef __cplusplus +} +#endif + +#endif // AM_SDK_VERSION_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/am_mcu_apollo.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/am_mcu_apollo.h new file mode 100644 index 0000000..fbc03dc --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/am_mcu_apollo.h @@ -0,0 +1,156 @@ +//***************************************************************************** +// +// am_mcu_apollo.h +//! @file +//! +//! @brief Top Include for Apollo class devices. +//! +//! This file provides all the includes necessary for an apollo device. +//! +//! @addtogroup hal Hardware Abstraction Layer (HAL) +// +//! @defgroup apollo3hal HAL for Apollo3 +//! @ingroup hal +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_MCU_APOLLO_H +#define AM_MCU_APOLLO_H + +//***************************************************************************** +// +// Define AM_CMSIS_REGS to indicate that CMSIS registers are supported. +// +//***************************************************************************** +#define AM_CMSIS_REGS 1 + +//***************************************************************************** +// +// C99 +// +//***************************************************************************** +#include +#include +#include +#include +#if AM_CMSIS_REGS +#include "apollo3.h" +#else // AM_CMSIS_REGS +#ifdef __IAR_SYSTEMS_ICC__ +#include "intrinsics.h" // __CLZ() and other intrinsics +#endif // AM_CMSIS_REGS +#endif + +//***************************************************************************** +// +// Global HAL +// +//***************************************************************************** +// +// Define the following macro to disable API parameter validation. +// Defining this macro will result in smaller, more efficient HAL code, but +// will disable parameter checking/validation throughout the HAL. +// +//#define AM_HAL_DISABLE_API_VALIDATION + +// +// Define the following macro to disable assert messaging. +// Defining this macro will result in smaller, more efficient HAL code, but +// will eliminate debug messaging. +// +//#define AM_HAL_DEBUG_NO_ASSERT + +//***************************************************************************** +// +// Registers +// +//***************************************************************************** +#include "regs/am_reg_base_addresses.h" + +#include "regs/am_reg_macros.h" + +#include "regs/am_reg.h" +#include "regs/am_reg_m4.h" +#include "regs/am_reg_jedec.h" + +//***************************************************************************** +// +// HAL +// +//***************************************************************************** +#include "hal/am_hal_status.h" +#include "hal/am_hal_sysctrl.h" +#include "hal/am_hal_adc.h" +#include "hal/am_hal_ble.h" +#include "hal/am_hal_ble_patch.h" +#include "hal/am_hal_burst.h" +#include "hal/am_hal_cachectrl.h" +#include "hal/am_hal_clkgen.h" +#include "hal/am_hal_cmdq.h" +#include "hal/am_hal_ctimer.h" +#include "hal/am_hal_debug.h" +#include "hal/am_hal_flash.h" +#include "hal/am_hal_global.h" +#include "hal/am_hal_gpio.h" +#include "hal/am_hal_interrupt.h" +#include "hal/am_hal_iom.h" +#include "hal/am_hal_ios.h" +#include "hal/am_hal_itm.h" +#include "hal/am_hal_mcuctrl.h" +#include "hal/am_hal_mspi.h" +#include "hal/am_hal_pdm.h" +#include "hal/am_hal_pin.h" +#include "hal/am_hal_pwrctrl.h" +#include "hal/am_hal_pwrctrl_internal.h" +#include "hal/am_hal_queue.h" +#include "hal/am_hal_reset.h" +#include "hal/am_hal_rtc.h" +#include "hal/am_hal_scard.h" +#include "hal/am_hal_secure_ota.h" +#include "hal/am_hal_stimer.h" +#include "hal/am_hal_security.h" +#include "hal/am_hal_systick.h" +#include "hal/am_hal_tpiu.h" +#include "hal/am_hal_uart.h" +#include "hal/am_hal_wdt.h" + +#endif // AM_MCU_APOLLO_H + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.c new file mode 100644 index 0000000..525e6f0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.c @@ -0,0 +1,1276 @@ +//***************************************************************************** +// +// am_hal_adc.c +//! @file +//! +//! @brief Functions for interfacing with the Analog to Digital Converter. +//! +//! @addtogroup adc3 Analog-to-Digital Converter (ADC) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Private Types. +// +//***************************************************************************** + +#define AM_HAL_MAGIC_ADC 0xAFAFAF +#define AM_HAL_ADC_CHK_HANDLE(h) ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_ADC)) + +// **************************************************************************** +// +// Apollo3 Temperature Trim Value Locations and default coefficients. +// +// **************************************************************************** +#define AM_HAL_ADC_CALIB_TEMP_ADDR (0x50023840) +#define AM_HAL_ADC_CALIB_AMBIENT_ADDR (0x50023844) +#define AM_HAL_ADC_CALIB_ADC_OFFSET_ADDR (0x50023848) + +// **************************************************************************** +// +// Default coefficients (used when trims not provided): +// TEMP_DEFAULT = Temperature in deg K (e.g. 299.5 - 273.15 = 26.35) +// AMBIENT_DEFAULT = Voltage measurement at default temperature. +// OFFSET_DEFAULT = Default ADC offset at 1v. +// +// **************************************************************************** +#define AM_HAL_ADC_CALIB_TEMP_DEFAULT (299.5F) +#define AM_HAL_ADC_CALIB_AMBIENT_DEFAULT (1.02809F) +#define AM_HAL_ADC_CALIB_ADC_OFFSET_DEFAULT (-0.004281F) + + +// +// ADC Power save register state. +// +typedef struct +{ + bool bValid; + uint32_t regCFG; + uint32_t regSL0CFG; + uint32_t regSL1CFG; + uint32_t regSL2CFG; + uint32_t regSL3CFG; + uint32_t regSL4CFG; + uint32_t regSL5CFG; + uint32_t regSL6CFG; + uint32_t regSL7CFG; + uint32_t regWULIM; + uint32_t regWLLIM; + uint32_t regINTEN; +} am_hal_adc_register_state_t; + +// +// ADC State structure. +// +typedef struct +{ + // + // Handle validation prefix. + // + am_hal_handle_prefix_t prefix; + + // + // Physical module number. + // + uint32_t ui32Module; + + // + // ADC Capabilities. + // + am_hal_adc_capabilities_t capabilities; + + // Power Save-Restore register state + am_hal_adc_register_state_t registerState; + +} am_hal_adc_state_t; + +//***************************************************************************** +// +//! @brief Private SRAM view of temperature trims. +//! +//! This static SRAM union is private to the ADC HAL functions. +// +//***************************************************************************** +static union +{ + //! These trim values are loaded as uint32_t values. + struct + { + //! Temperature of the package test head (in degrees Kelvin) + uint32_t ui32CalibrationTemperature; + + //! Voltage corresponding to temperature measured on test head. + uint32_t ui32CalibrationVoltage; + + //! ADC offset voltage measured on the package test head. + uint32_t ui32CalibrationOffset; + + //! Flag if default (guess) or measured. + bool bMeasured; + } ui32; + //! These trim values are accessed as floats when used in temp calculations. + struct + { + //! Temperature of the package test head in degrees Kelvin + float fCalibrationTemperature; + + //! Voltage corresponding to temperature measured on test head. + float fCalibrationVoltage; + + //! ADC offset voltage measured on the package test head. + float fCalibrationOffset; + + //! Flag if default (guess) or measured. + float fMeasuredFlag; + } flt; +} priv_temp_trims; + +//***************************************************************************** +// +// Global Variables. +// +//***************************************************************************** +am_hal_adc_state_t g_ADCState[AM_REG_ADC_NUM_MODULES]; + +uint32_t g_ADCSlotsConfigured; + +//***************************************************************************** +// +//! @brief ADC initialization function +//! +//! @param ui32Module - module instance. +//! @param handle - returns the handle for the module instance. +//! +//! This function accepts a module instance, allocates the interface and then +//! returns a handle to be used by the remaining interface functions. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_initialize(uint32_t ui32Module, void **ppHandle) +{ + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate the module number + // + if ( ui32Module >= AM_REG_ADC_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Check for valid arguements. + // + if ( !ppHandle ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if ( g_ADCState[ui32Module].prefix.s.bInit ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Initialize the handle. + // + g_ADCState[ui32Module].prefix.s.bInit = true; + g_ADCState[ui32Module].prefix.s.magic = AM_HAL_MAGIC_ADC; + g_ADCState[ui32Module].ui32Module = ui32Module; + + // + // Initialize the number of slots configured. + // + g_ADCSlotsConfigured = 0; + + // + // Return the handle. + // + *ppHandle = (void *)&g_ADCState[ui32Module]; + + // + // Before returning, grab the temperature trims. + // + priv_temp_trims.ui32.ui32CalibrationTemperature = + am_hal_flash_load_ui32((uint32_t*)AM_HAL_ADC_CALIB_TEMP_ADDR); + priv_temp_trims.ui32.ui32CalibrationVoltage = + am_hal_flash_load_ui32((uint32_t*)AM_HAL_ADC_CALIB_AMBIENT_ADDR); + priv_temp_trims.ui32.ui32CalibrationOffset = + am_hal_flash_load_ui32((uint32_t*)AM_HAL_ADC_CALIB_ADC_OFFSET_ADDR); + + if ( (priv_temp_trims.ui32.ui32CalibrationTemperature == 0xffffffff) || + (priv_temp_trims.ui32.ui32CalibrationVoltage == 0xffffffff) || + (priv_temp_trims.ui32.ui32CalibrationOffset == 0xffffffff) ) + { + // + // Since the device has not been calibrated on the tester, we'll load + // default calibration values. These default values should result + // in worst-case temperature measurements of +-6 degress C. + // + priv_temp_trims.flt.fCalibrationTemperature = AM_HAL_ADC_CALIB_TEMP_DEFAULT; + priv_temp_trims.flt.fCalibrationVoltage = AM_HAL_ADC_CALIB_AMBIENT_DEFAULT; + priv_temp_trims.flt.fCalibrationOffset = AM_HAL_ADC_CALIB_ADC_OFFSET_DEFAULT; + priv_temp_trims.ui32.bMeasured = false; + } + else + { + priv_temp_trims.ui32.bMeasured = true; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief MSPI deinitialization function +//! +//! @param handle - returns the handle for the module instance. +//! +//! This function accepts a handle to an instance and de-initializes the +//! interface. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_deinitialize(void *pHandle) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if ( pADCState->prefix.s.bEnable ) + { + status = am_hal_adc_disable(pHandle); + } + + pADCState->prefix.s.bInit = false; + + // + // Return the status. + // + return status; +} + +//***************************************************************************** +// +//! @brief ADC configuration function +//! +//! @param handle - handle for the module instance. +//! @param pConfig - pointer to the configuration structure. +//! +//! This function configures the ADC for operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_configure(void *pHandle, + am_hal_adc_config_t *psConfig) +{ + uint32_t ui32Config; + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + uint32_t ui32Module = pADCState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Config = 0; + + // + // Set the ADC clock source. + // + ui32Config |= _VAL2FLD(ADC_CFG_CLKSEL, psConfig->eClock); + + // + // Set the ADC trigger polarity. + // + ui32Config |= _VAL2FLD(ADC_CFG_TRIGPOL, psConfig->ePolarity); + + // + // Set the ADC trigger. + // + ui32Config |= _VAL2FLD(ADC_CFG_TRIGSEL, psConfig->eTrigger); + + // + // Set the ADC reference voltage. + // + ui32Config |= _VAL2FLD(ADC_CFG_REFSEL, psConfig->eReference); + + // + // Set the Destructive FIFO read. + // + ui32Config |= _VAL2FLD(ADC_CFG_DFIFORDEN, 1); + + // + // Set the ADC clock mode. + // + ui32Config |= _VAL2FLD(ADC_CFG_CKMODE, psConfig->eClockMode); + + // + // Set the ADC low power mode. + // + ui32Config |= _VAL2FLD(ADC_CFG_LPMODE, psConfig->ePowerMode); + + // + // Set the ADC repetition mode. + // + ui32Config |= _VAL2FLD(ADC_CFG_RPTEN, psConfig->eRepeat); + + // + // Set the configuration in the ADC peripheral. + // + ADCn(ui32Module)->CFG = ui32Config; + + // + // Return status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC slot configuration function +//! +//! @param handle - handle for the module instance. +//! @param pConfig - pointer to the configuration structure. +//! +//! This function configures the ADC slot for operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_configure_slot(void *pHandle, + uint32_t ui32SlotNumber, + am_hal_adc_slot_config_t *pSlotConfig) +{ + uint32_t ui32Config; + uint32_t ui32RegOffset; + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + uint32_t ui32Module = pADCState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check the slot number. + // + if ( ui32SlotNumber >= AM_HAL_ADC_MAX_SLOTS ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Config = 0; + + // + // Set the measurements to average + // + ui32Config |= _VAL2FLD(ADC_SL0CFG_ADSEL0, pSlotConfig->eMeasToAvg); + + // + // Set the precision mode. + // + ui32Config |= _VAL2FLD(ADC_SL0CFG_PRMODE0, pSlotConfig->ePrecisionMode); + + // + // Set the channel. + // + ui32Config |= _VAL2FLD(ADC_SL0CFG_CHSEL0, pSlotConfig->eChannel); + + // + // Enable window comparison if configured. + // + ui32Config |= _VAL2FLD(ADC_SL0CFG_WCEN0, pSlotConfig->bWindowCompare); + + // + // Enable the slot if configured. + // + ui32Config |= _VAL2FLD(ADC_SL0CFG_SLEN0, pSlotConfig->bEnabled); + + // + // Locate the correct register for this ADC slot. + // + ui32RegOffset = ((uint32_t)&ADCn(ui32Module)->SL0CFG) + (4 * ui32SlotNumber); + + // + // Write the register with the caller's configuration value. + // + AM_REGVAL(ui32RegOffset) = ui32Config; + + // + // Update the nubmer of slots configured. + // + g_ADCSlotsConfigured++; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC DMA configuration function +//! +//! @param handle - handle for the module instance. +//! @param pConfig - pointer to the configuration structure. +//! +//! This function configures the ADC DMA for operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_configure_dma(void *pHandle, + am_hal_adc_dma_config_t *pDMAConfig) +{ + uint32_t ui32Config; + uint32_t ui32Module = ((am_hal_adc_state_t *)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Config = 0; + + // + // Configure the DMA complete power-off. + // + ui32Config |= _VAL2FLD(ADC_DMACFG_DPWROFF, 0); // DPWROFF not supported! + + // + // Configure the data to be transferred. + // + if ( g_ADCSlotsConfigured > 1 ) + { + // Need slot number to distinguish between slot results. + ui32Config |= _VAL2FLD(ADC_DMACFG_DMAMSK, ADC_DMACFG_DMAMSK_DIS); + } + else + { + ui32Config |= _VAL2FLD(ADC_DMACFG_DMAMSK, ADC_DMACFG_DMAMSK_EN); + } + + // + // Enable DMA Halt on Status (DMAERR or DMACPL) by default. + // + ui32Config |= _VAL2FLD(ADC_DMACFG_DMAHONSTAT, ADC_DMACFG_DMAHONSTAT_EN); + + // + // Configure the DMA dynamic priority handling. + // + ui32Config |= _VAL2FLD(ADC_DMACFG_DMADYNPRI, pDMAConfig->bDynamicPriority); + + // + // Configure the DMA static priority. + // + ui32Config |= _VAL2FLD(ADC_DMACFG_DMAPRI, pDMAConfig->ePriority); + + // + // Enable the DMA (does not start until ADC is enabled and triggered). + // + ui32Config |= _VAL2FLD(ADC_DMACFG_DMAEN, ADC_DMACFG_DMAEN_EN); + + // + // Set the DMA configuration. + // + ADCn(ui32Module)->DMACFG = ui32Config; + + // + // Set the DMA transfer count. + // + ADCn(ui32Module)->DMATOTCOUNT_b.TOTCOUNT = pDMAConfig->ui32SampleCount; + + // + // Set the DMA target address. + // + ADCn(ui32Module)->DMATARGADDR = pDMAConfig->ui32TargetAddress; + + // + // Set the DMA trigger on FIFO 75% full. + // + ADCn(ui32Module)->DMATRIGEN = ADC_DMATRIGEN_DFIFO75_Msk; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC device specific control function. +//! +//! @param handle - handle for the module instance. +//! +//! This function provides for special control functions for the ADC operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t am_hal_adc_control(void *pHandle, + am_hal_adc_request_e eRequest, + void *pArgs) +{ + uint32_t ui32Module = ((am_hal_adc_state_t *)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + switch ( eRequest ) + { + case AM_HAL_ADC_REQ_WINDOW_CONFIG: + { + am_hal_adc_window_config_t *pWindowConfig = (am_hal_adc_window_config_t *)pArgs; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the window limits. + // + if ( (pWindowConfig->ui32Upper > ADC_WULIM_ULIM_Msk) || + (pWindowConfig->ui32Lower > ADC_WLLIM_LLIM_Msk) ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // + // Set the window comparison upper and lower limits. + // + ADCn(ui32Module)->WULIM = _VAL2FLD(ADC_WULIM_ULIM, pWindowConfig->ui32Upper); + ADCn(ui32Module)->WLLIM = _VAL2FLD(ADC_WLLIM_LLIM, pWindowConfig->ui32Lower); + + // + // Set the window scale per precision mode if indicated. + // + ADCn(ui32Module)->SCWLIM = _VAL2FLD(ADC_SCWLIM_SCWLIMEN, + pWindowConfig->bScaleLimits); + } + break; + + case AM_HAL_ADC_REQ_TEMP_CELSIUS_GET: + // + // pArgs must point to an array of 3 floats. To assure that the + // array is valid, upon calling the 3rd float (pArgs[2]) must be + // set to the value -123.456F. + // + if ( pArgs != NULL ) + { + float *pfArray = (float*)pArgs; + float fTemp, fCalibration_temp, fCalibration_voltage, fCalibration_offset, fVoltage; + + if ( pfArray[2] == -123.456F ) + { + // + // Get the scaled voltage obtained from the ADC sample. + // The ADC sample value is scaled up by the reference voltage + // (e.g. 1.5F), then divided by 65536.0F. + // + fVoltage = pfArray[0]; + + // + // Get calibration temperature from trimmed values & convert to degrees K. + // + fCalibration_temp = priv_temp_trims.flt.fCalibrationTemperature; + fCalibration_voltage = priv_temp_trims.flt.fCalibrationVoltage; + fCalibration_offset = priv_temp_trims.flt.fCalibrationOffset; + + // + // Compute the temperature. + // + fTemp = fCalibration_temp; + fTemp /= (fCalibration_voltage - fCalibration_offset); + fTemp *= (fVoltage - fCalibration_offset); + + // + // Give it back to the caller in Celsius. + // + pfArray[1] = fTemp - 273.15f; + } + else + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_ADC_REQ_TEMP_TRIMS_GET: + // + // pArgs must point to an array of 4 floats. To assure that the + // array is valid, upon calling the 4th float (pArgs[3]) must be + // set to the value -123.456. + // On return, pArgs[3] is set to 1 if the returned values are + // calibrated, or 0 if default calibration values. + // + if ( pArgs != NULL ) + { + float *pfArray = (float*)pArgs; + if ( pfArray[3] == -123.456F ) + { + // + // Return trim temperature as a float. + // + pfArray[0] = priv_temp_trims.flt.fCalibrationTemperature; + + // + // Return trim voltage as a float. + // + pfArray[1] = priv_temp_trims.flt.fCalibrationVoltage; + + // + // Return trim ADC offset voltage as a float. + // + pfArray[2] = priv_temp_trims.flt.fCalibrationOffset; + + // + // Set the calibrated or uncalibrated flag + // + ((uint32_t*)pArgs)[3] = priv_temp_trims.ui32.bMeasured; + } + else + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC enable function +//! +//! @param handle - handle for the module instance. +//! +//! This function enables the ADC operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_enable(void *pHandle) +{ + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + uint32_t ui32Module = pADCState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( pADCState->prefix.s.bEnable ) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Enable the ADC. + // + ADCn(ui32Module)->CFG_b.ADCEN = 0x1; + + // + // Set flag to indicate module is enabled. + // + pADCState->prefix.s.bEnable = true; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC disable function +//! +//! @param handle - handle for the module instance. +//! +//! This function disables the ADC operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_disable(void *pHandle) +{ + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + uint32_t ui32Module = pADCState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Disable the ADC. + // + ADCn(ui32Module)->CFG_b.ADCEN = 0x0; + + // + // Set flag to indicate module is disabled. + // + pADCState->prefix.s.bEnable = false; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC status function +//! +//! @param handle - handle for the interface. +//! +//! This function returns the current status of the DMA operation. +//! +//! @return status - DMA status flags. +// +//***************************************************************************** +uint32_t +am_hal_adc_status_get(void *pHandle, am_hal_adc_status_t *pStatus ) +{ + uint32_t ui32Module = ((am_hal_adc_state_t *)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Get the power status. + // + pStatus->bPoweredOn = (ADCn(ui32Module)->STAT & ADC_STAT_PWDSTAT_Msk) == + _VAL2FLD(ADC_STAT_PWDSTAT, ADC_STAT_PWDSTAT_ON); + + // + // Get the low power mode 1 status. + // + pStatus->bLPMode1 = (ADCn(ui32Module)->STAT & ADC_STAT_PWDSTAT_Msk) == + _VAL2FLD(ADC_STAT_PWDSTAT, ADC_STAT_PWDSTAT_POWERED_DOWN); + + // + // Get the DMA status. + // + pStatus->bErr = ((ADCn(ui32Module)->DMASTAT & ADC_DMASTAT_DMAERR_Msk) > 0); + pStatus->bCmp = ((ADCn(ui32Module)->DMASTAT & ADC_DMASTAT_DMACPL_Msk) > 0); + pStatus->bTIP = ((ADCn(ui32Module)->DMASTAT & ADC_DMASTAT_DMATIP_Msk) > 0); + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC enable interrupts function +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - ADC interrupt mask. +//! +//! This function enables the specific indicated interrupts. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_interrupt_enable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Enable the interrupts. + // + ADCn(ui32Module)->INTEN |= ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC disable interrupts function +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - ADC interrupt mask. +//! +//! This function disable the specific indicated interrupts. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_interrupt_disable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Disable the interrupts. + // + ADCn(ui32Module)->INTEN &= ~ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC interrupt status function +//! +//! @param handle - handle for the interface. +//! +//! This function returns the specific indicated interrupt status. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_interrupt_status(void *pHandle, + uint32_t *pui32Status, + bool bEnabledOnly) +{ + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // if requested, only return the interrupts that are enabled. + // + if ( bEnabledOnly ) + { + uint32_t ui32RetVal = ADCn(ui32Module)->INTSTAT; + *pui32Status = ADCn(ui32Module)->INTEN & ui32RetVal; + } + else + { + *pui32Status = ADCn(ui32Module)->INTSTAT; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +//! @brief ADC interrupt clear +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - uint32_t for interrupts to clear +//! +//! This function clears the interrupts for the given peripheral. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_interrupt_clear(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Clear the interrupts. + // + ADCn(ui32Module)->INTCLR = ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// ADC sample read function +// +// This function reads samples from the ADC FIFO or an SRAM sample buffer +// returned by a DMA operation. +// +//***************************************************************************** +uint32_t am_hal_adc_samples_read(void *pHandle, bool bFullSample, + uint32_t *pui32InSampleBuffer, + uint32_t *pui32InOutNumberSamples, + am_hal_adc_sample_t *pui32OutBuffer) +{ + uint32_t ui32Sample; + uint32_t ui32RequestedSamples = *pui32InOutNumberSamples; + + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check the output sample buffer pointer. + // + if ( NULL == pui32OutBuffer ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + + *pui32InOutNumberSamples = 0; + + // + // Check if we are reading directly from FIFO or DMA SRAM buffer. + // + if ( NULL == pui32InSampleBuffer ) + { + // + // Grab a value from the ADC FIFO + // + do + { + ui32Sample = ADCn(ui32Module)->FIFOPR; + pui32OutBuffer->ui32Slot = AM_HAL_ADC_FIFO_SLOT(ui32Sample); + pui32OutBuffer->ui32Sample = bFullSample ? + AM_HAL_ADC_FIFO_FULL_SAMPLE(ui32Sample) : + AM_HAL_ADC_FIFO_SAMPLE(ui32Sample); + pui32OutBuffer++; + (*pui32InOutNumberSamples)++; + } while ((AM_HAL_ADC_FIFO_COUNT(ui32Sample) > 0) && + (*pui32InOutNumberSamples < ui32RequestedSamples)); + } + else + { + // + // Process the samples from the provided sample buffer + // + do + { + ui32Sample = ADCn(ui32Module)->FIFOPR; + pui32OutBuffer->ui32Slot = AM_HAL_ADC_FIFO_SLOT(*pui32InSampleBuffer); + pui32OutBuffer->ui32Sample = AM_HAL_ADC_FIFO_SAMPLE(*pui32InSampleBuffer); + pui32InSampleBuffer++; + pui32OutBuffer++; + (*pui32InOutNumberSamples)++; + } while (*pui32InOutNumberSamples < ui32RequestedSamples); + } + + // + // Return FIFO valid bits. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Issue Software Trigger to the ADC. +//! +//! @param handle - handle for the module instance. +//! +//! This function triggers the ADC operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_sw_trigger(void *pHandle) +{ + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Write to the Software trigger register in the ADC. + // + ADCn(ui32Module)->SWT = 0x37; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC power control function +//! +//! @param handle - handle for the interface. +//! @param ePowerState - the desired power state to move the peripheral to. +//! @param bRetainState - flag (if true) to save/restore peripheral state upon +//! power state change. +//! +//! This function updates the peripheral to a given power state. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + uint32_t ui32Module = pADCState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Decode the requested power state and update MSPI operation accordingly. + // + switch (ePowerState) + { + case AM_HAL_SYSCTRL_WAKE: + if ( bRetainState && !pADCState->registerState.bValid ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable the ADC power domain. + // + am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_ADC); + + if ( bRetainState ) + { + ADCn(ui32Module)->SL0CFG = pADCState->registerState.regSL0CFG; + ADCn(ui32Module)->SL1CFG = pADCState->registerState.regSL1CFG; + ADCn(ui32Module)->SL2CFG = pADCState->registerState.regSL2CFG; + ADCn(ui32Module)->SL3CFG = pADCState->registerState.regSL3CFG; + ADCn(ui32Module)->SL4CFG = pADCState->registerState.regSL4CFG; + ADCn(ui32Module)->SL5CFG = pADCState->registerState.regSL5CFG; + ADCn(ui32Module)->SL6CFG = pADCState->registerState.regSL6CFG; + ADCn(ui32Module)->SL7CFG = pADCState->registerState.regSL7CFG; + ADCn(ui32Module)->WULIM = pADCState->registerState.regWULIM; + ADCn(ui32Module)->WLLIM = pADCState->registerState.regWLLIM; + ADCn(ui32Module)->INTEN = pADCState->registerState.regINTEN; + ADCn(ui32Module)->CFG = pADCState->registerState.regCFG; + + pADCState->registerState.bValid = false; + } + break; + + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + if ( bRetainState ) + { + pADCState->registerState.regSL0CFG = ADCn(ui32Module)->SL0CFG; + pADCState->registerState.regSL1CFG = ADCn(ui32Module)->SL1CFG; + pADCState->registerState.regSL2CFG = ADCn(ui32Module)->SL2CFG; + pADCState->registerState.regSL3CFG = ADCn(ui32Module)->SL3CFG; + pADCState->registerState.regSL4CFG = ADCn(ui32Module)->SL4CFG; + pADCState->registerState.regSL5CFG = ADCn(ui32Module)->SL5CFG; + pADCState->registerState.regSL6CFG = ADCn(ui32Module)->SL6CFG; + pADCState->registerState.regSL7CFG = ADCn(ui32Module)->SL7CFG; + pADCState->registerState.regWULIM = ADCn(ui32Module)->WULIM; + pADCState->registerState.regWLLIM = ADCn(ui32Module)->WLLIM; + pADCState->registerState.regINTEN = ADCn(ui32Module)->INTEN; + pADCState->registerState.regCFG = ADCn(ui32Module)->CFG; + + pADCState->registerState.bValid = true; + } + + // + // Disable the ADC power domain. + // + am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_ADC); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.h new file mode 100644 index 0000000..59a9d9e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.h @@ -0,0 +1,679 @@ +//***************************************************************************** +// +// am_hal_adc.h +//! @file +//! +//! @brief Functions for interfacing with the Analog to Digital Converter +//! +//! @addtogroup adc3 Analog-to-Digital Converter (ADC) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_ADC_H +#define AM_HAL_ADC_H + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable IOM module number. +// +#define ADCn(n) ((ADC_Type*)(ADC_BASE + (n * (ADC_BASE - ADC_BASE)))) +//***************************************************************************** + +// +// Maximum number of slots. +// +#define AM_HAL_ADC_MAX_SLOTS 8 + +// +// ADC clock selection. +// +typedef enum +{ + AM_HAL_ADC_CLKSEL_OFF, + AM_HAL_ADC_CLKSEL_HFRC, + AM_HAL_ADC_CLKSEL_HFRC_DIV2 +} am_hal_adc_clksel_e; + +// +// ADC trigger polarity +// +typedef enum +{ + AM_HAL_ADC_TRIGPOL_RISING, + AM_HAL_ADC_TRIGPOL_FALLING +} am_hal_adc_trigpol_e; + +// +// ADC trigger selection +// +typedef enum +{ + AM_HAL_ADC_TRIGSEL_EXT0, + AM_HAL_ADC_TRIGSEL_EXT1, + AM_HAL_ADC_TRIGSEL_EXT2, + AM_HAL_ADC_TRIGSEL_EXT3, + AM_HAL_ADC_TRIGSEL_VCOMP, + AM_HAL_ADC_TRIGSEL_SOFTWARE = 7 +} am_hal_adc_trigsel_e; + +// +// ADC reference selection. +// +typedef enum +{ + AM_HAL_ADC_REFSEL_INT_2P0, + AM_HAL_ADC_REFSEL_INT_1P5, + AM_HAL_ADC_REFSEL_EXT_2P0, + AM_HAL_ADC_REFSEL_EXT_1P5 +} am_hal_adc_refsel_e; + +// +// ADC clock mode selection. +// +typedef enum +{ + AM_HAL_ADC_CLKMODE_LOW_POWER, // Disable the clock between scans for LPMODE0. + // Set LPCKMODE to 0x1 while configuring the ADC. + AM_HAL_ADC_CLKMODE_LOW_LATENCY // Low Latency Clock Mode. When set, HFRC and the + // adc_clk will remain on while in functioning in LPMODE0. +} am_hal_adc_clkmode_e; + +// +// ADC low-power mode selection. +// +typedef enum +{ + AM_HAL_ADC_LPMODE0, // Low Latency Clock Mode. When set, HFRC and the adc_clk + // will remain on while in functioning in LPMODE0. + AM_HAL_ADC_LPMODE1 // Powers down all circuity and clocks associated with the + // ADC until the next trigger event. Between scans, the reference + // buffer requires up to 50us of delay from a scan trigger event + // before the conversion will commence while operating in this mode. +} am_hal_adc_lpmode_e; + +// +// ADC repetition selection. +// +typedef enum +{ + AM_HAL_ADC_SINGLE_SCAN, + AM_HAL_ADC_REPEATING_SCAN +} am_hal_adc_repeat_e; + +// +// ADC measurement averaging configuration. +// +typedef enum +{ + AM_HAL_ADC_SLOT_AVG_1, + AM_HAL_ADC_SLOT_AVG_2, + AM_HAL_ADC_SLOT_AVG_4, + AM_HAL_ADC_SLOT_AVG_8, + AM_HAL_ADC_SLOT_AVG_16, + AM_HAL_ADC_SLOT_AVG_32, + AM_HAL_ADC_SLOT_AVG_64, + AM_HAL_ADC_SLOT_AVG_128 +} am_hal_adc_meas_avg_e; + +// +// ADC slot precision mode. +// +typedef enum +{ + AM_HAL_ADC_SLOT_14BIT, + AM_HAL_ADC_SLOT_12BIT, + AM_HAL_ADC_SLOT_10BIT, + AM_HAL_ADC_SLOT_8BIT +} am_hal_adc_slot_prec_e; + +// +// ADC slot channel selection. +// +typedef enum +{ + // Single-ended channels + AM_HAL_ADC_SLOT_CHSEL_SE0, + AM_HAL_ADC_SLOT_CHSEL_SE1, + AM_HAL_ADC_SLOT_CHSEL_SE2, + AM_HAL_ADC_SLOT_CHSEL_SE3, + AM_HAL_ADC_SLOT_CHSEL_SE4, + AM_HAL_ADC_SLOT_CHSEL_SE5, + AM_HAL_ADC_SLOT_CHSEL_SE6, + AM_HAL_ADC_SLOT_CHSEL_SE7, + AM_HAL_ADC_SLOT_CHSEL_SE8, + AM_HAL_ADC_SLOT_CHSEL_SE9, + // Differential channels. + AM_HAL_ADC_SLOT_CHSEL_DF0, + AM_HAL_ADC_SLOT_CHSEL_DF1, + // Miscellaneous other signals. + AM_HAL_ADC_SLOT_CHSEL_TEMP, + AM_HAL_ADC_SLOT_CHSEL_BATT, + AM_HAL_ADC_SLOT_CHSEL_VSS +} am_hal_adc_slot_chan_e; + +// +// DMA priority. +// +typedef enum +{ + AM_HAL_ADC_PRIOR_BEST_EFFORT, + AM_HAL_ADC_PRIOR_SERVICE_IMMED +} am_hal_adc_dma_prior_e; + +//! +//! ADC control function request types for am_hal_adc_control(). +//! +//! AM_HAL_ADC_REQ_TEMP_CELSIUS_GET: +//! pArgs must point to an array of 3 floats. To assure that the +//! array is valid, upon calling the 3rd float (pArgs[2]) must be +//! set to the value -123.456F. +//! AM_HAL_ADC_REQ_TEMP_TRIMS_GET: +//! pArgs must point to an array of 4 floats. To assure that the +//! array is valid, upon calling the 4th float (pArgs[3]) must be +//! set to the to the value -123.456F. +//! On return, pArgs[3] is set to 1 if the returned values are +//! calibrated, or 0 if default calibration values. +//! +typedef enum +{ + AM_HAL_ADC_REQ_WINDOW_CONFIG, + AM_HAL_ADC_REQ_TEMP_CELSIUS_GET, + AM_HAL_ADC_REQ_TEMP_TRIMS_GET, +} am_hal_adc_request_e; + +// +// ADC Sample structure. +// +typedef struct +{ + uint32_t ui32Sample; + uint32_t ui32Slot; +} am_hal_adc_sample_t; + + +//***************************************************************************** +// +//! @brief Configuration structure for the ADC. +// +//***************************************************************************** +typedef struct +{ + //! Select the ADC clock source. + am_hal_adc_clksel_e eClock; + + //! Select the ADC trigger polarity. + am_hal_adc_trigpol_e ePolarity; + + //! Select the ADC trigger source. + am_hal_adc_trigsel_e eTrigger; + + //! Select the ADC reference voltage. + am_hal_adc_refsel_e eReference; + + //! Whether to disable clocks between samples. + am_hal_adc_clkmode_e eClockMode; + + //! Select the ADC power mode. + am_hal_adc_lpmode_e ePowerMode; + + //! Select whether the ADC will re-trigger based on a signal from timer 3. + am_hal_adc_repeat_e eRepeat; + +} am_hal_adc_config_t; + +//***************************************************************************** +// +//! @brief Configuration structure for the ADC slot. +// +//***************************************************************************** +typedef struct +{ + //! Select the number of measurements to average + am_hal_adc_meas_avg_e eMeasToAvg; + + //! Select the precision mode + am_hal_adc_slot_prec_e ePrecisionMode; + + //! Select the channel + am_hal_adc_slot_chan_e eChannel; + + //! Select window comparison mode + bool bWindowCompare; + + //! Enable the slot + bool bEnabled; + +} am_hal_adc_slot_config_t; + +//***************************************************************************** +// +//! @brief Configuration structure for the ADC DMA +// +//***************************************************************************** +typedef struct +{ + //! ADC DMA dynamic priority enabled. + bool bDynamicPriority; + + //! ADC DMA static priority. + am_hal_adc_dma_prior_e ePriority; + + //! Enable DMA for ADC + bool bDMAEnable; + + //! Transfer count in samples + uint32_t ui32SampleCount; + + //! Target address + uint32_t ui32TargetAddress; + +} am_hal_adc_dma_config_t; + +//***************************************************************************** +// +//! @brief Window configuration structure for the ADC. +// +//***************************************************************************** +typedef struct +{ + //! Scale window comparison + bool bScaleLimits; + + //! Window limits + uint32_t ui32Upper; + uint32_t ui32Lower; + +} am_hal_adc_window_config_t; + +//***************************************************************************** +// +//! @brief Capabilities structure for the ADC. +// +//***************************************************************************** +typedef struct +{ + uint32_t dummy; + +} am_hal_adc_capabilities_t; + + +//***************************************************************************** +// +//! @brief Status structure for the ADC. +// +//***************************************************************************** +typedef struct +{ + // + // ADC power status. + // + bool bPoweredOn; + bool bLPMode1; + + // + // DMA status. + // + bool bErr; + bool bCmp; + bool bTIP; + +} am_hal_adc_status_t; + +// +// Transfer callback function prototype +// +typedef void (*am_hal_adc_callback_t)(void *pCallbackCtxt, uint32_t status); + +//***************************************************************************** +// +//! @name ADC Interrupts +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to enable an individual ADC interrupt cause. +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_INT_DERR (_VAL2FLD(ADC_INTEN_DERR, 1)) +#define AM_HAL_ADC_INT_DCMP (_VAL2FLD(ADC_INTEN_DCMP, 1)) +#define AM_HAL_ADC_INT_WCINC (_VAL2FLD(ADC_INTEN_WCINC, 1)) +#define AM_HAL_ADC_INT_WCEXC (_VAL2FLD(ADC_INTEN_WCEXC, 1)) +#define AM_HAL_ADC_INT_FIFOOVR2 (_VAL2FLD(ADC_INTEN_FIFOOVR2, 1)) +#define AM_HAL_ADC_INT_FIFOOVR1 (_VAL2FLD(ADC_INTEN_FIFOOVR1, 1)) +#define AM_HAL_ADC_INT_SCNCMP (_VAL2FLD(ADC_INTEN_SCNCMP, 1)) +#define AM_HAL_ADC_INT_CNVCMP (_VAL2FLD(ADC_INTEN_CNVCMP, 1)) +//! @} + +//***************************************************************************** +// +//! @brief ADC Fifo Read macros +//! +//! These are helper macros for interpreting FIFO data. Each ADC FIFO entry +//! contains information about the slot number and the FIFO depth alongside the +//! current sample. These macros perform the correct masking and shifting to +//! read those values. +//! +//! The SAMPLE and FULL_SAMPLE options refer to the fractional part of averaged +//! samples. If you are not using hardware averaging or don't need the +//! fractional part of the ADC sample, you should just use +//! AM_HAL_ADC_FIFO_SAMPLE. +//! +//! If you do need the fractional part, use AM_HAL_ADC_FIFO_FULL_SAMPLE. This +//! macro will keep six bits of precision past the decimal point. Depending on +//! the number of averaged samples, anywhere between 1 and 6 of these bits will +//! be valid. Please consult the datasheet to find out how many bits of data +//! are valid for your chosen averaging settings. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_FIFO_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value) >> 6) +#define AM_HAL_ADC_FIFO_FULL_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value)) +#define AM_HAL_ADC_FIFO_SLOT(value) (_FLD2VAL(ADC_FIFO_SLOTNUM, value)) +#define AM_HAL_ADC_FIFO_COUNT(value) (_FLD2VAL(ADC_FIFO_COUNT, value)) +//! @} + +#ifdef __cplusplus +extern "C" +{ +#endif + + //***************************************************************************** + // + //! @brief ADC initialization function + //! + //! @param ui32Module - module instance. + //! @param handle - returns the handle for the module instance. + //! + //! This function accepts a module instance, allocates the interface and then + //! returns a handle to be used by the remaining interface functions. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_initialize(uint32_t ui32Module, void **ppHandle); + + //***************************************************************************** + // + //! @brief MSPI deinitialization function + //! + //! @param handle - returns the handle for the module instance. + //! + //! This function accepts a handle to an instance and de-initializes the + //! interface. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_deinitialize(void *pHandle); + + //***************************************************************************** + // + //! @brief ADC configuration function + //! + //! @param handle - handle for the module instance. + //! @param pConfig - pointer to the configuration structure. + //! + //! This function configures the ADC for operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_configure(void *pHandle, + am_hal_adc_config_t *psConfig); + + //***************************************************************************** + // + //! @brief ADC slot configuration function + //! + //! @param handle - handle for the module instance. + //! @param pConfig - pointer to the configuration structure. + //! + //! This function configures the ADC slot for operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_configure_slot(void *pHandle, + uint32_t ui32SlotNumber, + am_hal_adc_slot_config_t *pSlotConfig); + + //***************************************************************************** + // + //! @brief ADC DMA configuration function + //! + //! @param handle - handle for the module instance. + //! @param pConfig - pointer to the configuration structure. + //! + //! This function configures the ADC DMA for operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_configure_dma(void *pHandle, + am_hal_adc_dma_config_t *pDMAConfig); + + //***************************************************************************** + // + //! @brief ADC device specific control function. + //! + //! @param handle - handle for the module instance. + //! @eRequest - One of: + //! AM_HAL_ADC_REQ_WINDOW_CONFIG + //! AM_HAL_ADC_REQ_TEMP_CELSIUS_GET (pArgs is required, see enums). + //! AM_HAL_ADC_REQ_TEMP_TRIMS_GET (pArgs is required, see enums). + //! + //! This function provides for special control functions for the ADC operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_control(void *pHandle, + am_hal_adc_request_e eRequest, + void *pArgs); + + //***************************************************************************** + // + //! @brief ADC enable function + //! + //! @param handle - handle for the module instance. + //! + //! This function enables the ADC operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_enable(void *pHandle); + + //***************************************************************************** + // + //! @brief ADC disable function + //! + //! @param handle - handle for the module instance. + //! + //! This function disables the ADC operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_disable(void *pHandle); + + //***************************************************************************** + // + //! @brief ADC status function + //! + //! @param handle - handle for the interface. + //! + //! This function returns the current status of the DMA operation. + //! + //! @return status - DMA status flags. + // + //***************************************************************************** + extern uint32_t am_hal_adc_status_get(void *pHandle, + am_hal_adc_status_t *pStatus ); + + //***************************************************************************** + // + //! @brief ADC enable interrupts function + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - ADC interrupt mask. + //! + //! This function enables the specific indicated interrupts. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_interrupt_enable(void *pHandle, uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief ADC disable interrupts function + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - ADC interrupt mask. + //! + //! This function disable the specific indicated interrupts. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_interrupt_disable(void *pHandle, uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief ADC interrupt status function + //! + //! @param handle - handle for the interface. + //! + //! This function returns the specific indicated interrupt status. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_interrupt_status(void *pHandle, + uint32_t *pui32Status, + bool bEnabledOnly); + + //***************************************************************************** + // + //! @brief ADC interrupt clear + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - uint32_t for interrupts to clear + //! + //! This function clears the interrupts for the given peripheral. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_interrupt_clear(void *pHandle, uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief ADC sample read function + //! + //! @param pHandle - handle for the module instance. + //! @param bFullSample - true to get a full sample including + //! the fractional part. + //! @param pui32InSampleBuffer - Ptr to the input sample buffer. + //! If NULL then samples will be read directly + //! from the FIFO. + //! @param pui32InOutNumberSamples - Ptr to variable containing the number of + //! samples. + //! @param pui32OutSampleBuffer - Ptr to the required output sample buffer. + //! + //! This function reads samples from the ADC FIFO or an SRAM sample buffer + //! returned by a DMA operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_samples_read(void *pHandle, bool bFullSample, + uint32_t *pui32InSampleBuffer, + uint32_t *pui32InOutNumberSamples, + am_hal_adc_sample_t *pui32OutBuffer); + + //***************************************************************************** + // + //! @brief ADC FIFO trigger function + //! + //! @param handle - handle for the module instance. + //! + //! This function triggers the ADC operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_sw_trigger(void *pHandle); + + //***************************************************************************** + // + //! @brief ADC power control function + //! + //! @param handle - handle for the interface. + //! @param ePowerState - the desired power state to move the peripheral to. + //! @param bRetainState - flag (if true) to save/restore peripheral state upon + //! power state change. + //! + //! This function updates the peripheral to a given power state. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_ADC_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.c new file mode 100644 index 0000000..6bd5a53 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.c @@ -0,0 +1,3165 @@ +//***************************************************************************** +// +//! @file am_hal_ble.c +//! +//! @brief HAL functions for the BLE interface. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include +#include "am_mcu_apollo.h" +#include "am_hal_ble_patch.h" +#include "am_hal_ble_patch_b0.h" + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +am_hal_ble_state_t g_sBLEState[AM_REG_BLEIF_NUM_MODULES]; + +//***************************************************************************** +// +// Helper macros for rev B0 parts. +// +//***************************************************************************** +#define BLEIF_INTSTAT_BLECSSTATN_Msk BLEIF_INTSTAT_B2MSHUTDN_Msk +#define BLEIF_INTSTAT_BLECIRQN_Msk BLEIF_INTSTAT_B2MACTIVE_Msk + +#define SKIP_FALLING_EDGES 0 + +//***************************************************************************** +// +// SPI "options" +// +// These values affect the behavior of the BLE HAL in regards to the SPI bus, +// but end users aren't likely to need to modify them. They are collected here +// for testing and debugging purposes. +// +//***************************************************************************** +// The amount of extra delay to add between successive SPI TX packets (in +// microseconds). +#define AM_BLE_TX_PACKET_SPACING_US 1 + +// The BLE core takes a little while to wake up from a fresh boot, which means +// that the patch_apply function might time-out on the first few tries. Set +// this variable to let it try again for a finite number of trials. +#define AM_BLE_NUM_PATCH_TRIALS 5000 + +// Patch complete can also take some time. +#define AM_BLE_NUM_PATCH_CMP_TRIALS 5000 + +// How long the MCU should wait for SPI_STATUS before assuming the BLE core is +// busy (measured in 10 us increments). +#define AM_BLE_STATUS_TIMEOUT 300 + +//***************************************************************************** +// +// Private types. +// +//***************************************************************************** +#define AM_HAL_MAGIC_BLE 0x775230 + +#define AM_HAL_BLE_CHK_HANDLE(h) \ + ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit \ + && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_BLE)) + +//***************************************************************************** +// +// BLE Core maximum patch packet size. +// +// Specified as part of the protocol. +// +//***************************************************************************** +#define MAX_PATCH_PACKET_LEN 0x80 + +//***************************************************************************** +// +// Some of the NationZ register addresses are different between A1/A2 and B0. +// +//***************************************************************************** + +#define AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_A1 0x20006054 +#define AM_HAL_BLE_IP_RAM_MODEX_TRIM_ADDR_A1 0x20006070 +#define AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_A1 0x20006038 +#define AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_A1 (0x200067b8 + 0x0c) + +#define AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_B0 0x20006858 +#define AM_HAL_BLE_IP_RAM_MODEX_TRIM_ADDR_B0 0x20006874 +#define AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_B0 0x20006838 +#define AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0 (0x20006e0c + 0x0c) + +//***************************************************************************** +// +// Static function prototypes. +// +//***************************************************************************** +static bool am_hal_ble_bus_lock(am_hal_ble_state_t *pBle); +static void am_hal_ble_bus_release(am_hal_ble_state_t *pBle); +static uint32_t am_hal_ble_fifo_drain(void *pHandle); +static void am_hal_ble_fifo_read(void *pHandle, uint32_t *pui32Data, uint32_t ui32NumBytes); +static bool am_hal_ble_check_status(am_hal_ble_state_t *pBle); +static bool am_hal_ble_check_irq(am_hal_ble_state_t *pBle); +static uint32_t am_hal_ble_cmd_write(void *pHandle, am_hal_ble_transfer_t *psTransfer); +static uint32_t am_hal_ble_load_modex_trim_set(void *pHandle); +static uint32_t nonblocking_write(am_hal_ble_state_t *pBle, am_hal_ble_transfer_t *psTransfer); +static uint32_t nonblocking_read(am_hal_ble_state_t *pBle, am_hal_ble_transfer_t *psTransfer); +static uint8_t am_hal_ble_read_trimdata_from_info1(void); + +//***************************************************************************** +// +// Look up Table for NZ CRC16 generation +// +//***************************************************************************** +static const uint16_t ccitt_table[] = +{ + 0x0000, 0x8005, 0x800F, 0x000A, 0x801B, 0x001E, 0x0014, 0x8011, + 0x8033, 0x0036, 0x003C, 0x8039, 0x0028, 0x802D, 0x8027, 0x0022, + 0x8063, 0x0066, 0x006C, 0x8069, 0x0078, 0x807D, 0x8077, 0x0072, + 0x0050, 0x8055, 0x805F, 0x005A, 0x804B, 0x004E, 0x0044, 0x8041, + 0x80C3, 0x00C6, 0x00CC, 0x80C9, 0x00D8, 0x80DD, 0x80D7, 0x00D2, + 0x00F0, 0x80F5, 0x80FF, 0x00FA, 0x80EB, 0x00EE, 0x00E4, 0x80E1, + 0x00A0, 0x80A5, 0x80AF, 0x00AA, 0x80BB, 0x00BE, 0x00B4, 0x80B1, + 0x8093, 0x0096, 0x009C, 0x8099, 0x0088, 0x808D, 0x8087, 0x0082, + 0x8183, 0x0186, 0x018C, 0x8189, 0x0198, 0x819D, 0x8197, 0x0192, + 0x01B0, 0x81B5, 0x81BF, 0x01BA, 0x81AB, 0x01AE, 0x01A4, 0x81A1, + 0x01E0, 0x81E5, 0x81EF, 0x01EA, 0x81FB, 0x01FE, 0x01F4, 0x81F1, + 0x81D3, 0x01D6, 0x01DC, 0x81D9, 0x01C8, 0x81CD, 0x81C7, 0x01C2, + 0x0140, 0x8145, 0x814F, 0x014A, 0x815B, 0x015E, 0x0154, 0x8151, + 0x8173, 0x0176, 0x017C, 0x8179, 0x0168, 0x816D, 0x8167, 0x0162, + 0x8123, 0x0126, 0x012C, 0x8129, 0x0138, 0x813D, 0x8137, 0x0132, + 0x0110, 0x8115, 0x811F, 0x011A, 0x810B, 0x010E, 0x0104, 0x8101, + 0x8303, 0x0306, 0x030C, 0x8309, 0x0318, 0x831D, 0x8317, 0x0312, + 0x0330, 0x8335, 0x833F, 0x033A, 0x832B, 0x032E, 0x0324, 0x8321, + 0x0360, 0x8365, 0x836F, 0x036A, 0x837B, 0x037E, 0x0374, 0x8371, + 0x8353, 0x0356, 0x035C, 0x8359, 0x0348, 0x834D, 0x8347, 0x0342, + 0x03C0, 0x83C5, 0x83CF, 0x03CA, 0x83DB, 0x03DE, 0x03D4, 0x83D1, + 0x83F3, 0x03F6, 0x03FC, 0x83F9, 0x03E8, 0x83ED, 0x83E7, 0x03E2, + 0x83A3, 0x03A6, 0x03AC, 0x83A9, 0x03B8, 0x83BD, 0x83B7, 0x03B2, + 0x0390, 0x8395, 0x839F, 0x039A, 0x838B, 0x038E, 0x0384, 0x8381, + 0x0280, 0x8285, 0x828F, 0x028A, 0x829B, 0x029E, 0x0294, 0x8291, + 0x82B3, 0x02B6, 0x02BC, 0x82B9, 0x02A8, 0x82AD, 0x82A7, 0x02A2, + 0x82E3, 0x02E6, 0x02EC, 0x82E9, 0x02F8, 0x82FD, 0x82F7, 0x02F2, + 0x02D0, 0x82D5, 0x82DF, 0x02DA, 0x82CB, 0x02CE, 0x02C4, 0x82C1, + 0x8243, 0x0246, 0x024C, 0x8249, 0x0258, 0x825D, 0x8257, 0x0252, + 0x0270, 0x8275, 0x827F, 0x027A, 0x826B, 0x026E, 0x0264, 0x8261, + 0x0220, 0x8225, 0x822F, 0x022A, 0x823B, 0x023E, 0x0234, 0x8231, + 0x8213, 0x0216, 0x021C, 0x8219, 0x0208, 0x820D, 0x8207, 0x0202 +}; + +//***************************************************************************** +// +// Helper macros for delays. +// +//***************************************************************************** +#define delay_ms(ms) am_hal_flash_delay(FLASH_CYCLES_US(1000 * (ms))) +#define delay_us(us) am_hal_flash_delay(FLASH_CYCLES_US(us)) + +#define WHILE_TIMEOUT_MS(expr, timeout, error) \ + { \ + uint32_t ui32Timeout = 0; \ + while (expr) \ + { \ + if (ui32Timeout == (timeout * 1000)) \ + { \ + return error; \ + } \ + \ + delay_us(1); \ + ui32Timeout++; \ + } \ + } + +#define WHILE_TIMEOUT_MS_BREAK(expr, timeout, error) \ + { \ + uint32_t ui32Timeout = 0; \ + while (expr) \ + { \ + if (ui32Timeout == (timeout * 1000)) \ + { \ + break; \ + } \ + \ + delay_us(1); \ + ui32Timeout++; \ + } \ + } +//***************************************************************************** +// +// Helper function for checking BLE data. +// +//***************************************************************************** +static bool +buffer_compare(void *b1, void *b2, uint32_t len) +{ + uint8_t *p1 = b1; + uint8_t *p2 = b2; + + for (uint32_t i = 0; i < len; i++) + { + if (p1[i] != p2[i]) + { + return false; + } + } + + return true; +} + +//***************************************************************************** +// +// Helper function for CRC caculation of BLE patch. +// +//***************************************************************************** +static uint16_t +am_hal_ble_crc_nz(uint8_t *pui8Data, uint32_t len) +{ + uint16_t ui16CurValue = 0; + uint32_t i; + + for (i = 0; i < len; i++) + { + ui16CurValue = ccitt_table[(((uint8_t)(ui16CurValue >> 8)) ^ pui8Data[i]) & 0xFF] ^ (ui16CurValue << 8); + } + + return ((ui16CurValue ^ 0) & ((1 << 16) - 1)); +} + +//***************************************************************************** +// +// Default options for the BLE module. +// +//***************************************************************************** +const am_hal_ble_config_t am_hal_ble_default_config = +{ + // Configure the HCI interface clock for 6 MHz + .ui32SpiClkCfg = AM_HAL_BLE_HCI_CLK_DIV8, + + // Set HCI read and write thresholds to 32 bytes each. + .ui32ReadThreshold = 32, + .ui32WriteThreshold = 32, + + // The MCU will supply the clock to the BLE core. + .ui32BleClockConfig = AM_HAL_BLE_CORE_MCU_CLK, + + // Default settings for expected BLE clock drift. + .ui32ClockDrift = 0, + .ui32SleepClockDrift = 50, + + // Default setting - AGC Enabled + .bAgcEnabled = true, + + // Default setting - Sleep Algo enabled + .bSleepEnabled = true, + + // Apply the default patches when am_hal_ble_boot() is called. + .bUseDefaultPatches = true, +}; + +//***************************************************************************** +// +// Function for controlling the WAKE signal. +// +//***************************************************************************** +uint32_t +am_hal_ble_wakeup_set(void *pHandle, uint32_t ui32Mode) +{ + am_hal_ble_state_t *pBle = pHandle; + + // + // Check the handle. + // + if ( !AM_HAL_BLE_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + +// am_hal_debug_gpio_set(BLE_DEBUG_TRACE_08); + + if ( ui32Mode ) + { + BLEIFn(pBle->ui32Module)->BLECFG_b.WAKEUPCTL = BLEIF_BLECFG_WAKEUPCTL_ON; + am_hal_debug_gpio_set(BLE_DEBUG_TRACE_08); + } + else + { +#ifndef AM_DISABLE_BLE_SLEEP + BLEIFn(pBle->ui32Module)->BLECFG_b.WAKEUPCTL = BLEIF_BLECFG_WAKEUPCTL_OFF; + am_hal_debug_gpio_clear(BLE_DEBUG_TRACE_08); +#endif + } + + return AM_HAL_STATUS_SUCCESS; + +// am_hal_debug_gpio_clear(BLE_DEBUG_TRACE_08); +} + +//***************************************************************************** +// +// Buffer for patch data. +// +//***************************************************************************** +am_hal_ble_buffer(128 + 4) g_psPatchBuffer; + +//***************************************************************************** +// +// Initialize the global variables associated with a BLE module, and return its +// handle. +// +//***************************************************************************** +uint32_t +am_hal_ble_initialize(uint32_t ui32Module, void **ppHandle) +{ + // + // Check the arguments. + // + if (ui32Module >= AM_REG_BLEIF_NUM_MODULES) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if (!ppHandle) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if (g_sBLEState[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Initialize the handle. + // + memset(&g_sBLEState[ui32Module].sCurrentTransfer, 0, sizeof(am_hal_ble_transfer_t)); + memset(&g_sBLEState[ui32Module].sSavedTransfer, 0, sizeof(am_hal_ble_transfer_t)); + + g_sBLEState[ui32Module].prefix.s.bInit = true; + g_sBLEState[ui32Module].prefix.s.magic = AM_HAL_MAGIC_BLE; + g_sBLEState[ui32Module].ui32Module = ui32Module; + g_sBLEState[ui32Module].ui32TransferIndex = 0; + g_sBLEState[ui32Module].bPatchComplete = 0; + g_sBLEState[ui32Module].bContinuePacket = 0; + g_sBLEState[ui32Module].bSavedPacket = 0; + g_sBLEState[ui32Module].bBusy = 0; + g_sBLEState[ui32Module].bCmdComplete = 0; + g_sBLEState[ui32Module].bDmaComplete = 0; + g_sBLEState[ui32Module].bFlowControlComplete = 0; + g_sBLEState[ui32Module].bUseDefaultPatches = false; + + // + // Pass the handle back to the caller. + // + *ppHandle = &g_sBLEState[ui32Module]; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_initialize() + +//***************************************************************************** +// +// Initialize the global variables associated with a BLE module, and return its +// handle. +// +//***************************************************************************** +uint32_t +am_hal_ble_deinitialize(void *pHandle) +{ + am_hal_ble_state_t *pBLE = (am_hal_ble_state_t *)pHandle; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Initialize the handle. + // + memset(&(pBLE->sCurrentTransfer), 0, sizeof(am_hal_ble_transfer_t)); + + pBLE->prefix.s.bInit = false; + pBLE->prefix.s.magic = 0; + pBLE->ui32Module = 0; + pBLE->ui32TransferIndex = 0; + pBLE->bPatchComplete = 0; + pBLE->bContinuePacket = 0; + pBLE->bSavedPacket = 0; + pBLE->bBusy = 0; + pBLE->bCmdComplete = 0; + pBLE->bDmaComplete = 0; + pBLE->bFlowControlComplete = 0; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_deinitialize() + +//***************************************************************************** +// +// Configuration function. +// +//***************************************************************************** +uint32_t +am_hal_ble_config(void *pHandle, const am_hal_ble_config_t *psConfig) +{ + uint32_t ui32Module; + uint32_t ui32BleClkConfig; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // Configure the SPI. + // + BLEIFn(ui32Module)->MSPICFG = 0x3; + BLEIFn(ui32Module)->MSPICFG_b.RDFC = 0; + BLEIFn(ui32Module)->MSPICFG_b.WTFC = 0; + BLEIFn(ui32Module)->MSPICFG_b.WTFCPOL = 1; + BLEIFn(ui32Module)->FIFOTHR_b.FIFOWTHR = psConfig->ui32WriteThreshold; + BLEIFn(ui32Module)->FIFOTHR_b.FIFORTHR = psConfig->ui32ReadThreshold; + BLEIFn(ui32Module)->FIFOCTRL |= BLEIF_FIFOCTRL_POPWR_Msk; + + // + // Clock configuration register writes need to be combined to a single + // operation. + // + ui32BleClkConfig = _VAL2FLD(BLEIF_CLKCFG_FSEL, psConfig->ui32SpiClkCfg); + ui32BleClkConfig |= _VAL2FLD(BLEIF_CLKCFG_IOCLKEN, 1); + + if (psConfig->ui32BleClockConfig == AM_HAL_BLE_CORE_MCU_CLK) + { + ui32BleClkConfig |= _VAL2FLD(BLEIF_CLKCFG_CLK32KEN, 1); + } + + BLEIFn(ui32Module)->CLKCFG = ui32BleClkConfig; + + if (APOLLO3_A1) + { + // + // Modify the BLE core's NVDS settings to match our configuration. + // + uint8_t *pui8NVDSData = (uint8_t *) am_ble_nvds_patch.pui32Data; + + // + // Set the clock source. + // + pui8NVDSData[AM_HAL_BLE_NVDS_CLOCKSOURCE_OFFSET + 3] = + (psConfig->ui32BleClockConfig & 0xFF); + + // + // Set the expected BLE clock drift PPM + // + pui8NVDSData[AM_HAL_BLE_NVDS_CLOCKDRIFT_OFFSET + 3] = + (psConfig->ui32ClockDrift & 0x00FF); + + pui8NVDSData[AM_HAL_BLE_NVDS_CLOCKDRIFT_OFFSET + 4] = + (psConfig->ui32ClockDrift & 0xFF00) >> 8; + + // + // Set the sleep clock drift PPM. + // + pui8NVDSData[AM_HAL_BLE_NVDS_SLEEPCLOCKDRIFT_OFFSET + 3] = + (psConfig->ui32SleepClockDrift & 0x00FF); + + pui8NVDSData[AM_HAL_BLE_NVDS_SLEEPCLOCKDRIFT_OFFSET + 4] = + (psConfig->ui32SleepClockDrift & 0xFF00) >> 8; + + // + // Configure Sleep mode. + // + pui8NVDSData[AM_HAL_BLE_NVDS_SLEEPENABLE_OFFSET + 3] = (psConfig->bSleepEnabled == true) ? 1 : 0; + // + // Configure AGC. + // + pui8NVDSData[AM_HAL_BLE_NVDS_AGC_OFFSET + 3] = (psConfig->bAgcEnabled == true) ? 1 : 0; + + // + // Update the CRC. + // + am_ble_nvds_patch.ui32CRC = am_hal_ble_crc_nz(pui8NVDSData, + am_ble_nvds_patch.ui32Length); + } + + // + // Save the addresses to the patches we intend to use. + // + g_sBLEState[ui32Module].bUseDefaultPatches = psConfig->bUseDefaultPatches; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_config() + +//***************************************************************************** +// +// Enable BLE +// +//***************************************************************************** +uint32_t +am_hal_ble_power_control(void *pHandle, uint32_t ui32PowerState) +{ + uint32_t ui32Module; + + // + // BLE buck is shared by Burst as well + // Enable the BLE buck trim values if in use + // + am_hal_pwrctrl_blebuck_trim(); + + // + // Check the handle. + // + if ( !AM_HAL_BLE_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + if (ui32PowerState == AM_HAL_BLE_POWER_ACTIVE) + { + // + // Don't run this initialization if the BLE is already enabled. + // + if ( PWRCTRL->DEVPWRSTATUS_b.BLEL == 0) + { + MCUCTRL->FEATUREENABLE |= 1; + WHILE_TIMEOUT_MS ( ((MCUCTRL->FEATUREENABLE & 0x7) != 0x7), 100, + AM_HAL_BLE_FEATURE_DISABLED ); + + // + // Enable the BLE module. + // + if (am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_BLEL) != + AM_HAL_STATUS_SUCCESS) + { + return AM_HAL_BLE_REGULATOR_FAILED; + } + + // + // Release the BLE module RESET, start the "power state machine", and + // enable the clocks. + // + BLEIFn(ui32Module)->CLKCFG = _VAL2FLD(BLEIF_CLKCFG_CLK32KEN, 1); + BLEIFn(ui32Module)->BLEDBG_b.DBGDATA = 1 << 14; + + // + // The reset bit is different between A0 and subsequent revisions. + // + if ( APOLLO3_GE_A1 ) + { + MCUCTRL->MISCCTRL_b.BLE_RESETN = 1; + } + else + { + AM_REGVAL(0x40020198) = 0x1 << 2; + } + + delay_ms(5); + BLEIFn(ui32Module)->BLECFG_b.PWRSMEN = 1; + + // + // Wait for indication that the power is on. + // + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.PWRST != 3, 1000, + AM_HAL_BLE_POWERUP_INCOMPLETE ); + } + } + else if (ui32PowerState == AM_HAL_BLE_POWER_OFF) + { + // + // Reverse of power-up. Disable clocks, set reset, then disable power. + // + BLEIFn(ui32Module)->CLKCFG = 0; + BLEIF->BLEDBG_b.DBGDATA = 0; + + if ( APOLLO3_GE_A1 ) + { + MCUCTRL->MISCCTRL_b.BLE_RESETN = 0; + } + else + { + AM_REGVAL(0x40020198) &= ~(0x1 << 2); + } + + BLEIF->BLECFG_b.PWRSMEN = 0; + + if (am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_BLEL) != + AM_HAL_STATUS_SUCCESS) + { + return AM_HAL_BLE_SHUTDOWN_FAILED; + } + + delay_us(100); + } + else + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_power_control() + +//***************************************************************************** +// +// Perform all of the operations necessary to prepare the BLE controller for +// HCI operation. +// +//***************************************************************************** +uint32_t +am_hal_ble_boot(void *pHandle) +{ + uint32_t ui32Status; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // The handle is good, so we can access it as a structure. + // + am_hal_ble_state_t *pBLE = pHandle; + + if (pBLE->bUseDefaultPatches) + { + // + // The B0 silicon patching method is slightly different from A1. B0 silicon + // does not require the Copy Patch method introduced for A1 silicon. + // + if (APOLLO3_A0 || APOLLO3_A1) + { + ui32Status = am_hal_ble_default_copy_patch_apply(pHandle); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + } + + // + // Apply the BLE trim value + // + ui32Status = am_hal_ble_default_trim_set_ramcode(pHandle); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + + // + // Apply the NVDS patch. + // + ui32Status = am_hal_ble_default_patch_apply(pHandle); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + + // + // Complete the patching step + // + ui32Status = am_hal_ble_patch_complete(pHandle); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + } + + if (am_hal_ble_check_32k_clock(pBLE) == AM_HAL_STATUS_FAIL) + { + return AM_HAL_BLE_32K_CLOCK_UNSTABLE; + } + else + { + return AM_HAL_STATUS_SUCCESS; + } +} // am_hal_ble_boot() + +//***************************************************************************** +// +// Apply a patch. +// +// Returns 0 for success or a numerical error code for failures. +// +//***************************************************************************** +uint32_t +am_hal_ble_patch_apply(void *pHandle, am_hal_ble_patch_t *psPatch) +{ + uint8_t pui8ExpectedResponse[32]; + uint32_t ui32ErrorStatus; + uint32_t ui32Trial; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + uint32_t ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + am_hal_ble_transfer_t sTransfer; + am_hal_ble_buffer(16) psPatchBuffer; + + // + // Send a header packet. + // + psPatchBuffer.bytes[0] = 0x01; + psPatchBuffer.bytes[1] = psPatch->ui32Type; + psPatchBuffer.bytes[2] = 0xF1; + psPatchBuffer.bytes[3] = 0x02; + psPatchBuffer.bytes[4] = (psPatch->ui32Length & 0xFF); + psPatchBuffer.bytes[5] = ((psPatch->ui32Length >> 8) & 0xFF); + + // + // This first packet might take a few tries. + // + for ( ui32Trial = 0; ui32Trial < AM_BLE_NUM_PATCH_TRIALS; ui32Trial++) + { + ui32ErrorStatus = am_hal_ble_blocking_hci_write(pHandle, + AM_HAL_BLE_RAW, + psPatchBuffer.words, + 6); + + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS ) + { + break; + } + } + + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + return ui32ErrorStatus; + } + + // + // Wait for the header response. It should be 5 bytes long. + // + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 1000, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = psPatchBuffer.words; + sTransfer.ui16Length = 5; + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + pui8ExpectedResponse[0] = 0x04; + pui8ExpectedResponse[1] = psPatch->ui32Type; + pui8ExpectedResponse[2] = 0xF1; + pui8ExpectedResponse[3] = 0x01; + pui8ExpectedResponse[4] = 0x00; + + if (!buffer_compare(psPatchBuffer.words, pui8ExpectedResponse, 5)) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Send all of the data, including the acknowledgements. + // + uint32_t ui32RemainingBytes = psPatch->ui32Length; + uint32_t ui32Index = 0; + + while (ui32RemainingBytes) + { + // + // Figure out how many bytes to send in the next packet. + // + uint32_t ui32TransferSize = (ui32RemainingBytes > MAX_PATCH_PACKET_LEN ? + MAX_PATCH_PACKET_LEN : ui32RemainingBytes); + + // + // Send a data header. + // + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_WRITE; + sTransfer.pui32Data = g_psPatchBuffer.words; + sTransfer.ui16Length = ui32TransferSize + 4; + sTransfer.bContinue = false; + + g_psPatchBuffer.bytes[0] = 0x01; + g_psPatchBuffer.bytes[1] = psPatch->ui32Type; + g_psPatchBuffer.bytes[2] = 0xF2; + g_psPatchBuffer.bytes[3] = ui32TransferSize; + + // copy data into buffer + memcpy(&g_psPatchBuffer.bytes[4], (uint8_t *)&(psPatch->pui32Data[ui32Index / 4]), ui32TransferSize); + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + // + // Read the acknowledgement. + // + WHILE_TIMEOUT_MS( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 1000, + AM_HAL_BLE_NO_HCI_RESPONSE); + + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = psPatchBuffer.words; + sTransfer.ui16Length = 5; + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + pui8ExpectedResponse[0] = 0x04; + pui8ExpectedResponse[1] = psPatch->ui32Type; + pui8ExpectedResponse[2] = 0xF2; + pui8ExpectedResponse[3] = 0x01; + pui8ExpectedResponse[4] = 0x00; + + if (!buffer_compare(psPatchBuffer.words, pui8ExpectedResponse, 5)) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Update the tracking variables + // + ui32RemainingBytes -= ui32TransferSize; + ui32Index += ui32TransferSize; + } + + // + // Send the CRC, and make sure we got it right. + // + psPatchBuffer.bytes[0] = 0x01; + psPatchBuffer.bytes[1] = psPatch->ui32Type; + psPatchBuffer.bytes[2] = 0xF3; + psPatchBuffer.bytes[3] = 0x02; + psPatchBuffer.bytes[4] = (psPatch->ui32CRC & 0xFF); + psPatchBuffer.bytes[5] = ((psPatch->ui32CRC >> 8) & 0xFF); + + if (am_hal_ble_blocking_hci_write(pHandle, AM_HAL_BLE_RAW, psPatchBuffer.words, 6) != + AM_HAL_STATUS_SUCCESS) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Wait for the header response. It should be 5 bytes long. + // + WHILE_TIMEOUT_MS( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 1000, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = psPatchBuffer.words; + sTransfer.ui16Length = 5; + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + pui8ExpectedResponse[0] = 0x04; + pui8ExpectedResponse[1] = psPatch->ui32Type; + pui8ExpectedResponse[2] = 0xF3; + pui8ExpectedResponse[3] = 0x01; + pui8ExpectedResponse[4] = 0x00; + + if (!buffer_compare(psPatchBuffer.words, pui8ExpectedResponse, 5)) + { + return AM_HAL_STATUS_FAIL; + } + else + { + return AM_HAL_STATUS_SUCCESS; + } +} // am_hal_ble_patch_apply() + +uint32_t +am_hal_ble_patch_copy_end_apply(void *pHandle) +{ + uint8_t pui8ExpectedResponse[32]; + uint32_t ui32ErrorStatus; + uint32_t ui32Trial; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + uint32_t ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + am_hal_ble_transfer_t sTransfer; + am_hal_ble_buffer(16) psPatchBuffer; + + // + // Send a header packet. + // + psPatchBuffer.bytes[0] = 0x01; + psPatchBuffer.bytes[1] = 0xEE; + psPatchBuffer.bytes[2] = 0xF1; + psPatchBuffer.bytes[3] = 0x02; + psPatchBuffer.bytes[4] = 0x00; + psPatchBuffer.bytes[5] = 0x00; + + // + // This first packet might take a few tries. + // + for ( ui32Trial = 0; ui32Trial < AM_BLE_NUM_PATCH_TRIALS; ui32Trial++) + { + ui32ErrorStatus = am_hal_ble_blocking_hci_write(pHandle, + AM_HAL_BLE_RAW, + psPatchBuffer.words, + 6); + + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS ) + { + + break; + } + } + + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + + return ui32ErrorStatus; + } + + // + // Wait for the header response. It should be 5 bytes long. + // + WHILE_TIMEOUT_MS( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 1000, AM_HAL_BLE_NO_HCI_RESPONSE); + + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = psPatchBuffer.words; + sTransfer.ui16Length = 5; + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + + return ui32ErrorStatus; + } + + pui8ExpectedResponse[0] = 0x04; + pui8ExpectedResponse[1] = 0xEE; + pui8ExpectedResponse[2] = 0xF1; + pui8ExpectedResponse[3] = 0x01; + pui8ExpectedResponse[4] = 0x00; + + if (!buffer_compare(psPatchBuffer.words, pui8ExpectedResponse, 5)) + { + + return AM_HAL_STATUS_FAIL; + } + return 0; +} // am_hal_ble_patch_copy_end_apply() + +//***************************************************************************** +// +// Apply the default copy patch. +// +// Returns 0 for success or a numerical error code for failures. +// +//***************************************************************************** +uint32_t +am_hal_ble_default_copy_patch_apply(void *pHandle) +{ + uint32_t ui32Status; + uint16_t ui16Crc; + + am_hal_ble_patch_t **psCopyPatch; + + psCopyPatch = am_hal_ble_default_copy_patches; + + ui16Crc = am_hal_ble_crc_nz((uint8_t*)(psCopyPatch[0]->pui32Data), psCopyPatch[0]->ui32Length); + psCopyPatch[0]->ui32CRC = ui16Crc; + ui32Status = am_hal_ble_patch_apply(pHandle, psCopyPatch[0]); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + + ui32Status = am_hal_ble_patch_copy_end_apply(pHandle); + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Apply the default patch. +// +// Returns 0 for success or a numerical error code for failures. +// +//***************************************************************************** +uint32_t +am_hal_ble_default_patch_apply(void *pHandle) +{ + uint32_t ui32Status, i = 0; + uint16_t ui16Crc; + uint32_t ui32NumPatches; + am_hal_ble_patch_t **psDefaultPatches; + + if (APOLLO3_A0 || APOLLO3_A1) + { + ui32NumPatches = am_hal_ble_num_default_patches; + psDefaultPatches = am_hal_ble_default_patches; + } + else + { + ui32NumPatches = am_hal_ble_num_default_patches_b0; + psDefaultPatches = am_hal_ble_default_patches_b0; + } + + for ( i = 0; i < ui32NumPatches; i++ ) + { + ui16Crc = am_hal_ble_crc_nz((uint8_t*)(psDefaultPatches[i]->pui32Data), psDefaultPatches[i]->ui32Length); + psDefaultPatches[i]->ui32CRC = ui16Crc; + ui32Status = am_hal_ble_patch_apply(pHandle, psDefaultPatches[i]); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_default_patch_apply() + +//***************************************************************************** +// +// Complete the patching process +// +//***************************************************************************** +uint32_t +am_hal_ble_patch_complete(void *pHandle) +{ + uint32_t ui32ErrorStatus; + am_hal_ble_transfer_t sTransfer; + am_hal_ble_buffer(12) sTxBuffer; + am_hal_ble_buffer(12) sRxBuffer; + uint32_t ui32Trial; + + am_hal_ble_state_t *pBLE = pHandle; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + uint32_t ui32Module = pBLE->ui32Module; + + // + // Write the "patch complete" command. + // + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_WRITE; + sTransfer.pui32Data = sTxBuffer.words; + sTransfer.ui16Length = 6; + + sTxBuffer.bytes[0] = 0x01; + sTxBuffer.bytes[1] = 0xEE; + sTxBuffer.bytes[2] = 0xF1; + sTxBuffer.bytes[3] = 0x02; + sTxBuffer.bytes[4] = 0x00; + sTxBuffer.bytes[5] = 0x00; + + for ( ui32Trial = 0; ui32Trial < AM_BLE_NUM_PATCH_CMP_TRIALS; ui32Trial++) + { + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS ) + { + break; + } + } + + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 100, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + // + // Read back the response. + // + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = sRxBuffer.words; + sTransfer.ui16Length = 2; + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + // + // Check to see which format the response came back in. If it doesn't have + // a 2-byte length header, we need to manually override the length, and + // continue on to adjust the HCI format in the next packet. Otherwise, we + // can just return from here. + // + if ( sRxBuffer.bytes[1] == 0xEE ) + { + sTransfer.ui16Length = 3; + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + } + else + { + sTransfer.ui16Length = (sRxBuffer.bytes[0] + (sRxBuffer.bytes[1] << 8)); + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + // + // Make sure to remember that we've sent the "patch complete" packet. + // + pBLE->bPatchComplete = true; + + return AM_HAL_STATUS_SUCCESS; + } + + // + // If we made it here, we need to tell the radio that we need two-byte + // headers prepended to each HCI packet it sends us. + // + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_WRITE; + sTransfer.pui32Data = sTxBuffer.words; + sTransfer.ui16Length = 5; + + sTxBuffer.bytes[0] = 0x01; + sTxBuffer.bytes[1] = 0x04; + sTxBuffer.bytes[2] = 0xFD; + sTxBuffer.bytes[3] = 0x01; + sTxBuffer.bytes[4] = 0x01; + + for ( ui32Trial = 0; ui32Trial < AM_BLE_NUM_PATCH_CMP_TRIALS; ui32Trial++) + { + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS ) + { + break; + } + } + + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + return ui32ErrorStatus; + } + + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 100, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = sRxBuffer.words; + sTransfer.ui16Length = 9; + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + // + // Now that we're done patching, we can let the radio sleep. + // + am_hal_ble_wakeup_set(pBLE, 0); + + // + // Make sure to remember that we've sent the "patch complete" packet. + // + pBLE->bPatchComplete = true; + + // + // Delay to give the BLE core time to take the patch (assuming a patch was sent). + // + delay_ms(500); + + // + // Load the modex trim data to the BLE controller. + // + am_hal_ble_load_modex_trim_set(pBLE); + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_patch_complete() + +//***************************************************************************** +// +// Set one of the trim values for the BLE core. +// +//***************************************************************************** +uint32_t +am_hal_ble_trim_set(void *pHandle, uint32_t ui32BleCoreAddress, uint32_t ui32TrimValue, uint32_t ui32TrimMask) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32TrimValueSwapped, ui32LockValue, ui32ReadVal, ui32WriteVal; + + ui32TrimValueSwapped = (((ui32TrimValue & 0x000000FF) << 24) | + ((ui32TrimValue & 0x0000FF00) << 8) | + ((ui32TrimValue & 0x00FF0000) >> 8) | + ((ui32TrimValue & 0xFF000000) >> 24)); + + if (ui32TrimValue != 0xFFFFFFFF) + { + // + // Unlock the BLE registers and save the "lock register" value. + // + am_hal_ble_plf_reg_read(pBLE, 0x43000004, &ui32LockValue); + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + + // + // Check to see if we need a bitfield mask. If not, we can just write + // directly. + // + if (ui32TrimMask == 0xFFFFFFFF) + { + am_hal_ble_plf_reg_write(pBLE, ui32BleCoreAddress, ui32TrimValueSwapped); + } + else + { + // + // If we do need a mask, read the register, mask out the old bits, + // OR in the new, and write the new value back. + // + am_hal_ble_plf_reg_read(pBLE, ui32BleCoreAddress, &ui32ReadVal); + ui32WriteVal = ((ui32ReadVal & (~ui32TrimMask)) | ui32TrimValueSwapped); + + am_hal_ble_plf_reg_write(pBLE, ui32BleCoreAddress, ui32WriteVal); + } + + // + // Unlock the BLE register. + // + am_hal_ble_plf_reg_write(pBLE, 0x43000004, ui32LockValue); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_trim_set() + +//***************************************************************************** +// +// Set the bandgap voltage, bandgap current, and retention LDO output values +// based on the tested values stored in non-volatile memory. +// +//***************************************************************************** +uint32_t +am_hal_ble_default_trim_set_ramcode(void *pHandle) +{ + uint32_t ui32TrimValue; + uint32_t ui32TrimValueSwapped; + uint32_t *pRamCode; + + if (APOLLO3_B0) + { + pRamCode = (uint32_t *) (am_ble_performance_patch_b0.pui32Data); + } + else + { + pRamCode = (uint32_t *) (am_ble_performance_patch.pui32Data); + } + + // + // Set the bandgap voltage and current. + // + //ui32TrimValue = (AM_REGVAL(0x50023800) | (0x0F000000)) & (0xEFFFFFFF); + ui32TrimValue = AM_REGVAL(0x50023800); + ui32TrimValueSwapped = (((ui32TrimValue & 0x000000FF) << 24) | + ((ui32TrimValue & 0x0000FF00) << 8) | + ((ui32TrimValue & 0x00FF0000) >> 8) | + ((ui32TrimValue & 0xFF000000) >> 24)); + + if (ui32TrimValueSwapped != 0xFFFFFFFF) + { + pRamCode[2] = ui32TrimValueSwapped; + } + + // + // Set the retention LDO voltage. + // + ui32TrimValue = AM_REGVAL(0x50023804); + if (ui32TrimValue != 0xFFFFFFFF) + { + // 0xFFFFFFFF means the part has not been trimed. + ui32TrimValue += 0x40000000; // Increase the retention voltage to > 0.75v + } + ui32TrimValueSwapped = (((ui32TrimValue & 0x000000FF) << 24) | + ((ui32TrimValue & 0x0000FF00) << 8) | + ((ui32TrimValue & 0x00FF0000) >> 8) | + ((ui32TrimValue & 0xFF000000) >> 24)); + + if ( ui32TrimValueSwapped != 0xFFFFFFFF ) + { + pRamCode[3] = ((pRamCode[3] & (~0x1F0)) | ui32TrimValueSwapped); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_default_trim_set_ramcode() + +//***************************************************************************** +// +// Builds a vendor-specific BLE command. +// +//***************************************************************************** +uint32_t +am_hal_ble_vs_command_build(uint32_t *pui32Command, uint32_t ui32OpCode, + uint32_t ui32TotalLength, uint8_t *pui8Parameters) +{ + uint8_t *pui8Dest = (uint8_t *) pui32Command; + + // + // Build the header portion of the command from the given argments. + // + pui8Dest[0] = 0x01; + pui8Dest[1] = ui32OpCode & 0xFF; + pui8Dest[2] = (ui32OpCode >> 8) & 0xFF; + pui8Dest[3] = (ui32TotalLength - 4) & 0xFF; + + // + // Finish filling the array with any parameters that may be required. + // + for (uint32_t i = 4; i < ui32TotalLength; i++) + { + pui8Dest[i] = pui8Parameters[i - 4]; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_vs_command_build() + +//***************************************************************************** +// +// Returns the number of bytes written. +// +//***************************************************************************** +uint32_t +am_hal_ble_blocking_hci_write(void *pHandle, uint8_t ui8Type, + uint32_t *pui32Data, uint32_t ui32NumBytes) +{ + uint32_t ui32ErrorStatus; + + am_hal_ble_transfer_t HciWrite = + { + .pui32Data = pui32Data, + .pui8Offset = {ui8Type, 0x0, 0x0}, + .ui8OffsetLen = 0, + .ui16Length = ui32NumBytes, + .ui8Command = AM_HAL_BLE_WRITE, + .ui8RepeatCount = 0, + .bContinue = false, + .pfnTransferCompleteCB = 0x0, + .pvContext = 0x0, + }; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return 0; + } + + // + // Fix up the offset length based on the packet type, and send the bytes. + // + if (ui8Type != AM_HAL_BLE_RAW) + { + HciWrite.ui8OffsetLen = 1; + } + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &HciWrite); + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + return ui32ErrorStatus; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_blocking_hci_write() + +//***************************************************************************** +// +// Returns the number of bytes received. +// +//***************************************************************************** +uint32_t +am_hal_ble_blocking_hci_read(void *pHandle, uint32_t *pui32Data, uint32_t *pui32BytesReceived) +{ + uint32_t ui32Module, ui32NumBytes, ui32ErrorStatus; + + am_hal_ble_buffer(2) sLengthBytes; + + am_hal_ble_transfer_t HciRead = + { + .pui32Data = sLengthBytes.words, + .pui8Offset = {0x0, 0x0, 0x0}, + .ui8OffsetLen = 0, + .ui16Length = 2, + .ui8Command = AM_HAL_BLE_READ, + .ui8RepeatCount = 0, + .bContinue = false, + .pfnTransferCompleteCB = 0x0, + .pvContext = 0x0, + }; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return 0; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // Make sure the IRQ signal is set. + // + if ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ ) + { + // + // Read the length bytes. + // + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &HciRead); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + return ui32ErrorStatus; + } + + // + // Read the rest of the packet. + // + HciRead.pui32Data = pui32Data; + HciRead.ui16Length = (sLengthBytes.bytes[0] + + (sLengthBytes.bytes[1] << 8)); + + // + // Check if the length is not out of the boundary + // + // Fixme: it is assumed here all the sizes of the buffer are 256 + if (HciRead.ui16Length > 256) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &HciRead); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + return ui32ErrorStatus; + } + + ui32NumBytes = HciRead.ui16Length; + } + else + { + ui32NumBytes = 0; + } + + if (pui32BytesReceived) + { + *pui32BytesReceived = ui32NumBytes; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_blocking_hci_read() + +//***************************************************************************** +// +// Returns the number of bytes written. +// +//***************************************************************************** +uint32_t +am_hal_ble_nonblocking_hci_write(void *pHandle, uint8_t ui8Type, + uint32_t *pui32Data, uint32_t ui32NumBytes, + am_hal_ble_transfer_complete_cb_t pfnCallback, + void *pvContext) +{ + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return 0; + } + + am_hal_ble_transfer_t HciWrite = + { + .pui32Data = pui32Data, + .pui8Offset = {ui8Type, 0x0, 0x0}, + .ui8OffsetLen = 0, + .ui16Length = ui32NumBytes, + .ui8Command = AM_HAL_BLE_WRITE, + .ui8RepeatCount = 0, + .bContinue = false, + .pfnTransferCompleteCB = pfnCallback, + .pvContext = pvContext, + }; + + // + // Fix up the offset length based on the packet type, and send the bytes. + // + if (ui8Type != AM_HAL_BLE_RAW) + { + HciWrite.ui8OffsetLen = 1; + } + + uint32_t ui32Status = am_hal_ble_nonblocking_transfer(pHandle, &HciWrite); + + return ui32Status; +} // am_hal_ble_nonblocking_hci_write() + +//***************************************************************************** +// +// Returns the number of bytes received. +// +//***************************************************************************** +uint32_t +am_hal_ble_nonblocking_hci_read(void *pHandle, uint32_t *pui32Data, + am_hal_ble_transfer_complete_cb_t pfnCallback, + void *pvContext) +{ + uint32_t ui32Status; + am_hal_ble_state_t *pBle = pHandle; + + am_hal_ble_buffer(2) sLengthBytes; + + am_hal_ble_transfer_t HciRead = + { + .pui32Data = sLengthBytes.words, + .pui8Offset = {0x0, 0x0, 0x0}, + .ui8OffsetLen = 0, + .ui16Length = 2, + .ui8Command = AM_HAL_BLE_READ, + .ui8RepeatCount = 0, + .bContinue = false, + .pfnTransferCompleteCB = pfnCallback, + .pvContext = pvContext, + }; + + // + // Check the handle. + // + if ( !AM_HAL_BLE_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Make sure the IRQ signal is set. + // + if ( am_hal_ble_check_irq(pBle) ) + { + // + // Read the length bytes. + // + ui32Status = am_hal_ble_blocking_transfer(pHandle, &HciRead); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + // + // Read the rest of the packet. + // + HciRead.pfnTransferCompleteCB = pfnCallback; + HciRead.pui32Data = pui32Data; + HciRead.ui16Length = (sLengthBytes.bytes[0] + + (sLengthBytes.bytes[1] << 8)); + + return am_hal_ble_nonblocking_transfer(pHandle, &HciRead); + } + + // + // If we get here, return fail. + // + return AM_HAL_STATUS_FAIL; +} // am_hal_ble_nonblocking_hci_read() + +//***************************************************************************** +// +// Return true if BSTATUS is high. +// +//***************************************************************************** +static bool +am_hal_ble_check_status(am_hal_ble_state_t *pBle) +{ + // + // We need to make a special exception for "continue" packets, since the + // BLE radio may deassert the STATUS signal mid-packet. + // + if (pBle->bContinuePacket) + { + pBle->bContinuePacket = false; + return true; + } + + if ( BLEIFn(0)->BSTATUS_b.SPISTATUS == 0) + { + return false; + } + + return true; +} // am_hal_ble_check_status() + +//***************************************************************************** +// +// Return true if IRQ is high. +// +//***************************************************************************** +static bool +am_hal_ble_check_irq(am_hal_ble_state_t *pBle) +{ + if ( BLEIFn(pBle->ui32Module)->BSTATUS_b.BLEIRQ ) + { + return true; + } + + return false; +} // am_hal_ble_check_irq() + +//***************************************************************************** +// +// Return true if we recently received a BSTATUS edge. +// +//***************************************************************************** +static bool +am_hal_ble_check_status_edge(am_hal_ble_state_t *pBle) +{ + // + // We need to make a special exception for "continue" packets, since the + // BLE radio may deassert the STATUS signal mid-packet. + // + if (pBle->bContinuePacket) + { + pBle->bContinuePacket = false; + return true; + } + + if (pBle->bPatchComplete == false) + { + return am_hal_ble_check_status(pBle); + } + + if ( BLEIFn(0)->INTSTAT_b.BLECSSTAT == 0) + { + return false; + } + + return true; +} // am_hal_ble_check_status_edge() + +//***************************************************************************** +// +// Blocking write to the BLE module. +// +//***************************************************************************** +uint32_t +am_hal_ble_blocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer) +{ + am_hal_ble_state_t *pBle = pHandle; + uint32_t ui32IntEnable; + uint32_t ui32Module; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // If the transfer doesn't have any bytes in it, just return success. + // + if (psTransfer->ui16Length == 0) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Make sure we don't get any interrupts that might interfere with this + // operation. We will save the interrupt enable register state so we can + // restore it later. Also, make sure "command complete" is clear, so we can + // detect the end of the transaction. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN_b.BLECIRQ = 0; + BLEIFn(ui32Module)->INTEN_b.BLECSSTAT = 0; + BLEIFn(ui32Module)->INTEN_b.CMDCMP = 0; + BLEIFn(ui32Module)->INTEN_b.THR = 0; + BLEIFn(ui32Module)->INTCLR_b.CMDCMP = 1; + BLEIFn(ui32Module)->INTCLR_b.BLECSSTAT = 1; + + // + // If we're writing, we need to lock down the bus now. Set the wakeup + // signal, and start monitoring STATUS. If STATUS isn't high within our + // configured timeout, we have to assume that the BLE core is unresponsive + // and report an error back to the caller. + // + if (psTransfer->ui8Command == AM_HAL_BLE_WRITE) + { + uint32_t ui32SpiStatus = false; + + if ( pBle->bLastPacketWasTX == true) + { + // + // wait some time to give the controller more time to consume + // the last TX packet + // + if (!pBle->bPatchComplete) + { + delay_ms(3); + } + pBle->bLastPacketWasTX = false; + } + + if (pBle->bPatchComplete) + { + uint32_t statusTimeout = 0; + while (am_hal_ble_check_status(pBle) == true) + { + statusTimeout++; + delay_us(10); + if (statusTimeout > 300) + { + break; + } + } + } + + // + // Make sure the IO clock for the STATUS signal is on. + // + BLEIFn(0)->BLEDBG_b.IOCLKON = 1; + delay_us(5); + + // + // Set WAKE, and wait for a positive edge on the STATUS signal. + // + am_hal_ble_wakeup_set(pBle, 1); + + // + // If we don't see an edge on STATUS in X ms, assume it's not coming + // and return with an AM_HAL_BLE_STATUS_SPI_NOT_READY error. + // + uint32_t ui32Timeout = 0; + uint32_t ui32TimeoutLimit = AM_BLE_STATUS_TIMEOUT; + + while (1) + { + if (am_hal_ble_check_status_edge(pBle) == true) + { + if (am_hal_ble_bus_lock(pBle)) + { + ui32SpiStatus = AM_HAL_STATUS_SUCCESS; + break; + } + } + else if ((ui32Timeout == ui32TimeoutLimit) || + (BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ)) + { + ui32SpiStatus = AM_HAL_BLE_STATUS_SPI_NOT_READY; + am_hal_ble_wakeup_set(pBle, 0); + break; + } + + ui32Timeout++; + delay_us(10); + } + + // + // Disable IOCLK + // + BLEIFn(0)->BLEDBG_b.IOCLKON = 0; + + if (ui32SpiStatus != AM_HAL_STATUS_SUCCESS) + { + // + // Restore the interrupt state. + // + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + am_hal_ble_wakeup_set(pBle, 0); + return ui32SpiStatus; + } + } + else + { + if (BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0) + { + // + // Restore the interrupt state. + // + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + return AM_HAL_BLE_STATUS_IRQ_LOW; + } + + if (!am_hal_ble_bus_lock(pBle)) + { + // + // Restore the interrupt state. + // + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + return AM_HAL_BLE_STATUS_BUS_BUSY; + } + } + + if (psTransfer->bContinue) + { + pBle->bContinuePacket = true; + } + + // + // Set the current transfer, and clear the command complete interrupt so we + // can tell when the next command completes. + // + memcpy(&pBle->sCurrentTransfer, psTransfer, sizeof(am_hal_ble_transfer_t)); + + // + // Critical section to protect the gap between command and data. + // + AM_CRITICAL_BEGIN; + + // + // Write the command word. + // + am_hal_ble_cmd_write(pHandle, psTransfer); + + // + // Now we need to manage the fifos based on the type of transfer. In either + // case, we will keep draining or refilling the FIFO until the full + // transaction is complete. + // + if (psTransfer->ui8Command == AM_HAL_BLE_WRITE) + { + bool bCmdCmp = false; + uint32_t numWait = 0; + // Adjust the byte count to be sent/received for repeat count + uint32_t ui32Bytes = pBle->sCurrentTransfer.ui16Length; + + uint32_t ui32FifoRem; + uint32_t *pui32Buffer = pBle->sCurrentTransfer.pui32Data; + + // + // Write the command word. + // + am_hal_ble_cmd_write(pHandle, psTransfer); + + // + // Keep looping until we're out of bytes to send or command complete (error). + // + while (ui32Bytes) + { + // + // Limit the wait to reasonable limit - instead of blocking forever + // + numWait = 0; + while ((ui32FifoRem = BLEIFn(ui32Module)->FIFOPTR_b.FIFO0REM) < 4) + { + bCmdCmp = BLEIFn(ui32Module)->INTSTAT_b.CMDCMP; + if (bCmdCmp || (numWait++ >= AM_HAL_IOM_MAX_BLOCKING_WAIT)) + { + // + // FIFO not expected to change any more - get out + // + break; + } + else + { + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + } + if (bCmdCmp || (ui32FifoRem < 4)) + { + // + // Something went wrong - bail out + // + break; + } + + while ((ui32FifoRem >= 4) && ui32Bytes) + { + BLEIFn(ui32Module)->FIFOPUSH = *pui32Buffer++; + ui32FifoRem -= 4; + if (ui32Bytes >= 4) + { + ui32Bytes -= 4; + } + else + { + ui32Bytes = 0; + } + } + } + WHILE_TIMEOUT_MS_BREAK ( BLEIFn(ui32Module)->INTSTAT_b.CMDCMP == 0, 2, + AM_HAL_BLE_HCI_PACKET_INCOMPLETE ); + am_hal_ble_wakeup_set(pBle, 0); + } + else + { + while (pBle->ui32TransferIndex < pBle->sCurrentTransfer.ui16Length) + { + am_hal_ble_fifo_drain(pHandle); + } + } + + // + // End the critical section. + // + AM_CRITICAL_END; //fixme moved further down to cover am_hal_ble_bus_release(); + + // + // Wait for the transaction to complete, and clear out any interrupts that + // may have come up. + // + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->INTSTAT_b.CMDCMP == 0, 10, + AM_HAL_BLE_HCI_PACKET_INCOMPLETE ); + BLEIFn(ui32Module)->INTCLR_b.CMDCMP = 1; + BLEIFn(ui32Module)->INTCLR_b.THR = 1; + + // + // Clear out the current transfer. We're done. + // + memset(&pBle->sCurrentTransfer, 0, sizeof(am_hal_ble_transfer_t)); + pBle->ui32TransferIndex = 0; + + // + // Let the radio go back to sleep. + // + if (psTransfer->ui8Command == AM_HAL_BLE_WRITE) + { + am_hal_ble_wakeup_set(pBle, 0); + pBle->bLastPacketWasTX = true; + } + + if ((psTransfer->ui8Command == AM_HAL_BLE_READ) && + (pBle->bPatchComplete == true)) + { + pBle->bLastPacketWasTX = false; + } + + // + // Restore the interrupt state. + // + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + // + // Release the bus. + // + am_hal_ble_bus_release(pBle); + + // + // End the critical section. + // + // AM_CRITICAL_END; //fixme moved further down to cover am_hal_ble_bus_release(); + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_blocking_transfer() + +//***************************************************************************** +// +// Nonblocking write to the BLE module. +// +//***************************************************************************** +uint32_t +am_hal_ble_nonblocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer) +{ + am_hal_ble_state_t *pBle = pHandle; + uint32_t ui32Status; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check to see if this is a write or a read. + // + if (psTransfer->ui8Command == AM_HAL_BLE_WRITE) + { + ui32Status = nonblocking_write(pBle, psTransfer); + } + else // AM_HAL_BLE_READ case. + { + ui32Status = nonblocking_read(pBle, psTransfer); + } + + return ui32Status; +} // am_hal_ble_nonblocking_transfer() + +//***************************************************************************** +// +// Function for performing non-blocking writes to the HCI interface. +// +// This function will start a BLE write on the physical bus. The caller should +// have already set WAKEUP and received a STATUS interrupt before they call +// this function. When the write operation is complete, the MCU will receive a +// command complete interrupt. +// +// Before calling this function, the caller is responsible for ensuring that +// STATUS is high, that BLEIRQ is low, and the the bus isn't already in use. If +// any of these problems exists when this function is called, it will simply +// return with an error status. +// +//***************************************************************************** +static uint32_t +nonblocking_write(am_hal_ble_state_t *pBle, am_hal_ble_transfer_t *psTransfer) +{ + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32Module = pBle->ui32Module; + + // + // This function goes in a critical section to make sure that the operation + // isn't interrupted or started again. + // + AM_CRITICAL_BEGIN; + + do + { + // + // Check for any of the various reasons that we might not be able to + // perform a write right now. If the bus is busy, if the BLE core requires + // a READ operation, or if the BLE core simply isn't ready yet, stop here + // and throw an error. + // + if ( pBle->bBusy ) + { + ui32Status = AM_HAL_BLE_STATUS_BUS_BUSY; + break; + } + + if ( am_hal_ble_check_irq(pBle) ) + { + ui32Status = AM_HAL_BLE_REQUESTING_READ; + break; + } + + if ( !am_hal_ble_check_status(pBle) ) + { + ui32Status = AM_HAL_BLE_STATUS_SPI_NOT_READY; + break; + } + + if (psTransfer->ui16Length == 0) + { + ui32Status = AM_HAL_STATUS_SUCCESS; + break; + } + + // + // With the obvious error cases out of the way, we can claim the bus and + // start the transaction. + // + if ( pBle->bLastPacketWasTX == true ) + { + delay_us(AM_BLE_TX_PACKET_SPACING_US); + } + + pBle->bBusy = true; + pBle->bLastPacketWasTX = true; + + // + // Save the current transfer. + // + memcpy(&pBle->sCurrentTransfer, psTransfer, sizeof(am_hal_ble_transfer_t)); + + // + // Prepare the DMA. + // + BLEIFn(ui32Module)->DMATARGADDR = (uint32_t)pBle->sCurrentTransfer.pui32Data; + BLEIFn(ui32Module)->DMATOTCOUNT = pBle->sCurrentTransfer.ui16Length; + BLEIFn(ui32Module)->DMATRIGEN = BLEIF_DMATRIGEN_DTHREN_Msk; + BLEIFn(ui32Module)->DMACFG = + (_VAL2FLD(BLEIF_DMACFG_DMADIR, BLEIF_DMACFG_DMADIR_M2P) | + _VAL2FLD(BLEIF_DMACFG_DMAPRI, BLEIF_DMACFG_DMAPRI_HIGH)); + + // + // Write the command word, and enable the DMA. + // + ui32Status = am_hal_ble_cmd_write(pBle, &pBle->sCurrentTransfer); + + BLEIFn(ui32Module)->DMACFG |= _VAL2FLD(BLEIF_DMACFG_DMAEN, BLEIF_DMACFG_DMAEN_EN); + + // + // Make sure WAKE goes low as quickly as possible after starting the write. + // + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + am_hal_ble_wakeup_set(pBle, 0); + } + } + while (0); + + // + // No matter what happened above, the function should end here. We'll end + // the critical section and alert the caller of our status. + // + AM_CRITICAL_END; + return ui32Status; +} // nonblocking_write() + +//***************************************************************************** +// +// This function performs a nonblocking read from the BLE core. +// +//***************************************************************************** +static uint32_t +nonblocking_read(am_hal_ble_state_t *pBle, am_hal_ble_transfer_t *psTransfer) +{ + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32Module = pBle->ui32Module; + + // + // This function goes in a critical section to make sure that the operation + // isn't interrupted or started again. + // + AM_CRITICAL_BEGIN; + + do + { + if ( pBle->bBusy ) + { + ui32Status = AM_HAL_BLE_STATUS_BUS_BUSY; + break; + } + + if ( !am_hal_ble_check_irq(pBle) ) + { + ui32Status = AM_HAL_BLE_STATUS_IRQ_LOW; + break; + } + + if (psTransfer->ui16Length == 0) + { + ui32Status = AM_HAL_STATUS_SUCCESS; + break; + } + + // + // With the obvious error cases out of the way, we can claim the bus and + // start the transaction. + // + if ( pBle->bLastPacketWasTX == true ) + { + delay_us(AM_BLE_TX_PACKET_SPACING_US); + } + + pBle->bBusy = true; + pBle->bLastPacketWasTX = false; + + // + // Set the current transfer. + // + memcpy(&pBle->sCurrentTransfer, psTransfer, sizeof(am_hal_ble_transfer_t)); + + BLEIFn(ui32Module)->DMATARGADDR = (uint32_t) pBle->sCurrentTransfer.pui32Data; + BLEIFn(ui32Module)->DMATOTCOUNT = pBle->sCurrentTransfer.ui16Length; + BLEIFn(ui32Module)->DMATRIGEN = (BLEIF_DMATRIGEN_DTHREN_Msk | BLEIF_INTCLR_CMDCMP_Msk); + BLEIFn(ui32Module)->DMACFG = + (_VAL2FLD(BLEIF_DMACFG_DMADIR, BLEIF_DMACFG_DMADIR_P2M) | + _VAL2FLD(BLEIF_DMACFG_DMAPRI, BLEIF_DMACFG_DMAPRI_HIGH)); + + // + // Write the command word, and enable the DMA. + // + ui32Status = am_hal_ble_cmd_write(pBle, &pBle->sCurrentTransfer); + BLEIFn(ui32Module)->DMACFG |= _VAL2FLD(BLEIF_DMACFG_DMAEN, BLEIF_DMACFG_DMAEN_EN); + } + while (0); + + // + // No matter what happened above, the function should end here. We'll end + // the critical section and alert the caller of our status. + // + AM_CRITICAL_END; + return ui32Status; +} // nonblocking_read() + +//***************************************************************************** +// +// Mark the BLE interface busy so it doesn't get used by more than one +// interface. +// +//***************************************************************************** +static bool +am_hal_ble_bus_lock(am_hal_ble_state_t *pBle) +{ + bool bLockObtained; + + // + // In one atomic sweep, check to see if the bus is busy, and reserve it if + // it isn't. + // + AM_CRITICAL_BEGIN; + + if (pBle->bBusy == false) + { + am_hal_debug_gpio_set(BLE_DEBUG_TRACE_11); + pBle->bBusy = true; + bLockObtained = true; + pBle->bCmdComplete = 0; + pBle->bDmaComplete = 0; + pBle->bFlowControlComplete = 0; + } + else + { + bLockObtained = false; + } + + AM_CRITICAL_END; + + // + // Tell the caller if we successfully locked the bus. + // + return bLockObtained; +} // am_hal_ble_bus_lock() + +//***************************************************************************** +// +// Release the bus so someone else can use it. +// +//***************************************************************************** +static void +am_hal_ble_bus_release(am_hal_ble_state_t *pBle) +{ + pBle->bBusy = false; + am_hal_debug_gpio_clear(BLE_DEBUG_TRACE_11); +} + +//***************************************************************************** +// +// Pull data out of the fifo for reads. +// +//***************************************************************************** +static uint32_t +am_hal_ble_fifo_drain(void *pHandle) +{ + uint32_t ui32Module; + uint32_t ui32ReadSize, ui32RxDataLen, ui32BytesLeft; + uint32_t *pDest; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return 0; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // Rename some pointers for convenience. + // + am_hal_ble_state_t *pBle = pHandle; + am_hal_ble_transfer_t *pTransfer = &pBle->sCurrentTransfer; + + // + // Check to see how much data there is in the FIFO, and also how many + // bytes are remaining in the transfer. + // + ui32RxDataLen = BLEIFn(ui32Module)->FIFOPTR_b.FIFO1SIZ; + ui32BytesLeft = (pTransfer->ui16Length - pBle->ui32TransferIndex); + + // + // Calculate how much we can drain the fifo. + // + if (ui32RxDataLen < 4) + { + return 0; + } + else if (ui32RxDataLen >= pTransfer->ui16Length) + { + ui32ReadSize = ui32BytesLeft; + } + else + { + ui32ReadSize = ui32RxDataLen & (~0x3); + } + + // + // Calculate the place where we last left off, feed the FIFO starting from + // that location, and update the index to match. + // + pDest = &pTransfer->pui32Data[pBle->ui32TransferIndex / 4]; + + am_hal_ble_fifo_read(pHandle, pDest, ui32ReadSize); + + pBle->ui32TransferIndex += ui32ReadSize; + + // + // Return the number of bytes we wrote. + // + return ui32ReadSize; +} // am_hal_ble_fifo_drain() + +//***************************************************************************** +// +// Write the command word for a BLE transfer. +// +//***************************************************************************** +uint32_t +am_hal_ble_cmd_write(void *pHandle, am_hal_ble_transfer_t *psTransfer) +{ + uint32_t ui32CmdWord, ui32OffsetHigh; + uint32_t ui32Module; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // Figure out the command word and the offset register. Then write them. + // + switch (psTransfer->ui8OffsetLen) + { + case 0: + ui32CmdWord = 0; + ui32OffsetHigh = 0; + break; + + case 1: + ui32CmdWord = _VAL2FLD(BLEIF_CMD_OFFSETLO, psTransfer->pui8Offset[0]); + ui32OffsetHigh = 0; + break; + + case 2: + ui32CmdWord = _VAL2FLD(BLEIF_CMD_OFFSETLO, psTransfer->pui8Offset[1]); + ui32OffsetHigh = psTransfer->pui8Offset[0]; + break; + + case 3: + ui32CmdWord = _VAL2FLD(BLEIF_CMD_OFFSETLO, psTransfer->pui8Offset[2]); + ui32OffsetHigh = ((psTransfer->pui8Offset[1]) | + (psTransfer->pui8Offset[0] << 8)); + break; + + default: + // Offset length was incorrect. + return AM_HAL_STATUS_INVALID_ARG; + } + + ui32CmdWord |= (_VAL2FLD(BLEIF_CMD_OFFSETCNT, psTransfer->ui8OffsetLen) | + _VAL2FLD(BLEIF_CMD_TSIZE, psTransfer->ui16Length) | + _VAL2FLD(BLEIF_CMD_CONT, psTransfer->bContinue) | + psTransfer->ui8Command); + + BLEIFn(ui32Module)->OFFSETHI = ui32OffsetHigh; + BLEIFn(ui32Module)->CMD = ui32CmdWord; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_cmd_write() + +//***************************************************************************** +// +// Read ui32NumBytes from the RX FIFO. +// +//***************************************************************************** +static void +am_hal_ble_fifo_read(void *pHandle, uint32_t *pui32Data, uint32_t ui32NumBytes) +{ + uint32_t ui32Index; + uint32_t ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + for (ui32Index = 0; (ui32Index * 4) < ui32NumBytes; ui32Index++) + { + pui32Data[ui32Index] = BLEIFn(ui32Module)->FIFOPOP; + +#ifndef AM_HAL_BLE_NO_FIFO_PROTECTION + BLEIFn(ui32Module)->FIFOPOP = 0; +#endif + + } +} // am_hal_ble_fifo_read() + +//***************************************************************************** +// +// Call the appropriate callbacks when DMA transfers complete. +// +//***************************************************************************** +uint32_t +am_hal_ble_int_service(void *pHandle, uint32_t ui32Status) +{ + am_hal_ble_state_t *pBle = pHandle; + uint32_t ui32Module; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // The handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // Track each of the interrupts signaling the end of an HCI transfer. + // + if ( ui32Status & BLEIF_INTSTAT_CMDCMP_Msk ) + { + pBle->bCmdComplete = true; + } + + if ( ui32Status & BLEIF_INTSTAT_DCMP_Msk ) + { + pBle->bDmaComplete = true; + } + + // + // For B0 parts, we can detect when key flow control signals from the BLE + // core are de-asserted. + // + if (APOLLO3_GE_B0) + { + // + // Check for falling IRQ + // + if ( (ui32Status & BLEIF_INTSTAT_BLECIRQN_Msk) && + (pBle->sCurrentTransfer.ui8Command == AM_HAL_BLE_READ) ) + { + pBle->bFlowControlComplete = true; + } + + // + // Check for falling status. + // + if ( (ui32Status & BLEIF_INTSTAT_BLECSSTATN_Msk ) && + (pBle->sCurrentTransfer.ui8Command == AM_HAL_BLE_WRITE) ) + { + pBle->bFlowControlComplete = true; + } + } + + // + // If we get a command complete, we need to release the wake signal, + // disable the DMA, release the bus, and call any callback that might + // exist. + // + // For revision A parts, "command complete" means that the DMA operation + // and the BLE SPI interface have both finished their operations. For rev B + // parts, we will also wait for the flow control signal (either STATUS or + // IRQ) to be removed. + // + if ( pBle->bCmdComplete && pBle->bDmaComplete && + ((pBle->bFlowControlComplete) || (!APOLLO3_GE_B0) || SKIP_FALLING_EDGES) ) + { + // + // Clean up our state flags. + // + pBle->bCmdComplete = false; + pBle->bDmaComplete = false; + pBle->bFlowControlComplete = false; + + // + // If our FIFOs aren't empty right now, either the DMA didn't finish, + // or this interrupt handler is somehow being called incorrectly. + // + if ( BLEIFn(ui32Module)->FIFOPTR != 0x20002000 ) + { + return AM_HAL_BLE_FIFO_ERROR; + } + + // + // Drop the wake request if we had one, and make sure we remember if + // the last packet was a transmit packet. + // + if ((pBle->sCurrentTransfer.ui8Command == AM_HAL_BLE_WRITE) && + (pBle->bPatchComplete == true)) + { + pBle->bLastPacketWasTX = true; + am_hal_ble_wakeup_set(pBle, 0); + } + + // + // If this was a read packet, remember that it wasn't a TX packet. + // + if (pBle->sCurrentTransfer.ui8Command == AM_HAL_BLE_READ) + { + pBle->bLastPacketWasTX = false; + } + + // + // Disable the DMA + // + BLEIFn(ui32Module)->DMACFG = 0; + + am_hal_ble_bus_release(pBle); + + if ( pBle->sCurrentTransfer.pfnTransferCompleteCB ) + { + am_hal_ble_transfer_complete_cb_t pfnCallback; + uint32_t ui32Length; + uint8_t *pui8Data; + void *pvContext; + + pfnCallback = pBle->sCurrentTransfer.pfnTransferCompleteCB; + pui8Data = (uint8_t * ) pBle->sCurrentTransfer.pui32Data; + ui32Length = pBle->sCurrentTransfer.ui16Length; + pvContext = pBle->sCurrentTransfer.pvContext; + + pfnCallback(pui8Data, ui32Length, pvContext); + } + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_int_service() + +//***************************************************************************** +// +// Interrupt Enable +// +//***************************************************************************** +uint32_t +am_hal_ble_int_enable(void *pHandle, uint32_t ui32InterruptMask) +{ + uint32_t ui32Module; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + AM_CRITICAL_BEGIN + BLEIFn(ui32Module)->INTEN |= ui32InterruptMask; + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_int_enable() + +//***************************************************************************** +// +// Interrupt Enable +// +//***************************************************************************** +uint32_t +am_hal_ble_int_disable(void *pHandle, uint32_t ui32InterruptMask) +{ + uint32_t ui32Module; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + AM_CRITICAL_BEGIN + BLEIFn(ui32Module)->INTEN &= ~ui32InterruptMask; + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_int_disable() + +//***************************************************************************** +// +// Check the status of the interrupts. +// +//***************************************************************************** +uint32_t +am_hal_ble_int_status(void *pHandle, bool bEnabledOnly) +{ + uint32_t ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + if (bEnabledOnly) + { + uint32_t ui32IntEn = BLEIFn(ui32Module)->INTEN; + return ( BLEIFn(ui32Module)->INTSTAT & ui32IntEn ); + } + else + { + return BLEIFn(ui32Module)->INTSTAT; + } +} // am_hal_ble_int_status() + +//***************************************************************************** +// +// Clear the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_ble_int_clear(void *pHandle, uint32_t ui32InterruptMask) +{ + uint32_t ui32Module; + + // + // Check the handle. + // + if ( !AM_HAL_BLE_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *)pHandle)->ui32Module; + + BLEIFn(ui32Module)->INTCLR = ui32InterruptMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_int_clear() + +//***************************************************************************** +// +// check 32768Hz clock is ready. +// +//***************************************************************************** +uint32_t +am_hal_ble_check_32k_clock(void *pHandle) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t rc32k_clock = 0xFFFFFFFF; + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_B0, &rc32k_clock); + } + else + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_A1, &rc32k_clock); + } + + // Normal 32KHz clock is about 0x8000 + if ( (rc32k_clock > 0x8200) || (rc32k_clock < 0x7B00) ) + { + return AM_HAL_STATUS_FAIL; + } + else + { + return AM_HAL_STATUS_SUCCESS; + } +} // am_hal_ble_check_32k_clock() + +//***************************************************************************** +// +// Read a register value from the BLE core. +// +//***************************************************************************** +uint32_t +am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Value) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint8_t pui8Parameter[4]; + uint32_t ui32IntEnable; + + uint32_t ui32Module = pBLE->ui32Module; + + // + // Make a buffer big enough to hold the register write command, and a + // second one big enough to hold the response. + // + am_hal_ble_buffer(AM_HAL_BLE_PLF_REGISTER_READ_LENGTH) sWriteCommand; + am_hal_ble_buffer(32) sResponse; + + // + // Prepare our register write value. + // + pui8Parameter[0] = ui32Address; + pui8Parameter[1] = (ui32Address >> 8); + pui8Parameter[2] = (ui32Address >> 16); + pui8Parameter[3] = (ui32Address >> 24); + + sResponse.words[0] = 0; + sResponse.words[1] = 0; + sResponse.words[2] = 0; + + // + // Fill the buffer with the specific command we want to write, and send it. + // + am_hal_ble_vs_command_build(sWriteCommand.words, + AM_HAL_BLE_PLF_REGISTER_READ_OPCODE, + AM_HAL_BLE_PLF_REGISTER_READ_LENGTH, + pui8Parameter); + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + AM_HAL_BLE_PLF_REGISTER_READ_LENGTH); + + // + // Make sure the IO clock for the STATUS signal is on. + // + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response, and return it to the caller via our variable. + // + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 500, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + *pui32Value = (((sResponse.words[1] & 0xFF000000) >> 24) | + ((sResponse.words[2] & 0x00FFFFFF) << 8)); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_ble_plf_reg_read() + +//***************************************************************************** +// +// Write a register value to the BLE core. +// +//***************************************************************************** +uint32_t +am_hal_ble_plf_reg_write(void *pHandle, uint32_t ui32Address, uint32_t ui32Value) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint8_t pui8Parameter[8]; + uint32_t ui32IntEnable; + + uint32_t ui32Module = pBLE->ui32Module; + + // + // Make a buffer big enough to hold the register write command, and a + // second one big enough to hold the response. + // + am_hal_ble_buffer(AM_HAL_BLE_PLF_REGISTER_WRITE_LENGTH) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + + // + // Prepare our register write value. + // + pui8Parameter[0] = ui32Address; + pui8Parameter[1] = (ui32Address >> 8); + pui8Parameter[2] = (ui32Address >> 16); + pui8Parameter[3] = (ui32Address >> 24); + pui8Parameter[4] = ui32Value; + pui8Parameter[5] = (ui32Value >> 8); + pui8Parameter[6] = (ui32Value >> 16); + pui8Parameter[7] = (ui32Value >> 24); + + // + // Fill the buffer with the specific command we want to write, and send it. + // + am_hal_ble_vs_command_build(sWriteCommand.words, + AM_HAL_BLE_PLF_REGISTER_WRITE_OPCODE, + AM_HAL_BLE_PLF_REGISTER_WRITE_LENGTH, + pui8Parameter); + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + AM_HAL_BLE_PLF_REGISTER_WRITE_LENGTH); + + // + // Make sure the IO clock for the STATUS signal is on. + // + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 50, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_ble_plf_reg_write() + +//***************************************************************************** +// +// Set the modulation frequency offset from INFO1, +// based on the tested values stored in non-volatile memory. +// +//***************************************************************************** +uint32_t +am_hal_ble_load_modex_trim_set(void *pHandle) +{ + uint8_t ui8TrimValue; + // + // load the modex trim data from info1. + // + ui8TrimValue = am_hal_ble_read_trimdata_from_info1(); + if ( ui8TrimValue ) + { + am_hal_ble_transmitter_modex_set(pHandle, ui8TrimValue); + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_FAIL; + } +} // am_hal_ble_load_modex_trim_set() + +//***************************************************************************** +// +// Load the modulation frequency offset from INFO1, +// based on the tested values stored in non-volatile memory. +// +//***************************************************************************** +uint8_t +am_hal_ble_read_trimdata_from_info1(void) +{ + uint32_t ui32TrimValue = 0, temp = 0; + uint8_t TrimData = 0; + + temp = ui32TrimValue = AM_REGVAL(0x50023808); + temp &= 0xffffff00; + + if ( temp == 0x18240600 ) + { + TrimData = ui32TrimValue & 0xFF; + } + else + { + TrimData = 0; + } + + if ( (TrimData > 0x40) || (TrimData < 0x20) ) + { + TrimData = 0; + } + + return TrimData; +} // am_hal_ble_read_trimdata_from_info1() + +//***************************************************************************** +// +// Manually set modulation characteristic +// based on the tested values at customer side. +// manually set frequency offset for 10101010 or 01010101 pattern +// parameter default value is 0x34, increase to get larger frequency offset +// +//***************************************************************************** +uint32_t +am_hal_ble_transmitter_modex_set(void *pHandle, uint8_t ui8ModFrqOffset) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t RegValueMCGR, RegValueBACKCR, RegValueSTCR, RegValueDACSPICR, temp = 0; + + ui8ModFrqOffset &= 0x7F; + + am_hal_ble_plf_reg_read(pBLE, 0x43000004, &RegValueMCGR); + + // + // Unlock the BLE registers. + // + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + am_hal_ble_plf_reg_read(pBLE, 0x52000008, &temp); + temp |= 0x08; + am_hal_ble_plf_reg_read(pBLE, 0x52000000, &RegValueSTCR); + RegValueSTCR |= (1 << 10); + am_hal_ble_plf_reg_write(pBLE, 0x52000000, RegValueSTCR); + + am_hal_ble_plf_reg_read(pBLE, 0x45800070, &RegValueBACKCR); + am_hal_ble_plf_reg_write(pBLE, 0x45800070, (RegValueBACKCR | 0x8)); + RegValueDACSPICR = (ui8ModFrqOffset << 1) | 0x1; + am_hal_ble_plf_reg_write(pBLE, 0x52000014, RegValueDACSPICR); + + am_hal_ble_plf_reg_write(pBLE, 0x52000008, temp); + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_MODEX_TRIM_ADDR_B0, ui8ModFrqOffset); + } + else + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_MODEX_TRIM_ADDR_A1, ui8ModFrqOffset); + } + am_hal_ble_plf_reg_write(pBLE, 0x43000004, RegValueMCGR); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_transmitter_modex_set() + +//***************************************************************************** +// +// Set BLE sleep enable/disable for the BLE core. +// enable = 'true' set sleep enable, enable = 'false' set sleep disable +// +//***************************************************************************** +uint32_t +am_hal_ble_sleep_set(void *pHandle, bool enable) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t sleepenable = 0; + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0, &sleepenable); + } + else + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_A1, &sleepenable); + } + + sleepenable &= 0xffff0100; + + if ( enable ) + { + sleepenable |= 0x0101; + } + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0, sleepenable); + } + else + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_A1, sleepenable); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_sleep_set() + +//***************************************************************************** +// +// Get current sleep enable status +// return 'true' = sleep enable , 'false' = sleep disable +// +//***************************************************************************** +bool +am_hal_ble_sleep_get(void *pHandle) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t sleepenable = 0; + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0, &sleepenable); + } + else + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_A1, &sleepenable); + } + + if ( (sleepenable & 0xFFFF) > 0 ) + { + return true; + } + + return false; +} // am_hal_ble_sleep_get() + +//***************************************************************************** +// +// set the tx power of BLE +// values. +// ui32TxPower: 0x03->-20dBm 0x04->-10dBm 0x05->-5dBm 0x08->0dBm 0x0F->3dBm +// +//***************************************************************************** +uint32_t +am_hal_ble_tx_power_set(void *pHandle, uint8_t ui32TxPower) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t RegValueMCGR, tempreg = 0; + uint32_t ui32PowerValue = 0x00000008; + ui32PowerValue |= (ui32TxPower & 0xF) << 16; + + am_hal_ble_plf_reg_read(pBLE, 0x43000004, &RegValueMCGR); + + // + // Unlock the BLE registers. + // + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_B0, &tempreg); + } + else + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_A1, &tempreg); + } + + tempreg &= 0xffffff00; + tempreg |= ui32TxPower; + am_hal_ble_plf_reg_write(pBLE, 0x52400018, ui32PowerValue); + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_B0, tempreg); + } + else + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_A1, tempreg); + } + + am_hal_ble_plf_reg_write(pBLE, 0x43000004, RegValueMCGR); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_tx_power_set() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.h new file mode 100644 index 0000000..fc6de38 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.h @@ -0,0 +1,1004 @@ +//***************************************************************************** +// +//! @file am_hal_ble.h +//! +//! @brief HAL functions for the BLE interface. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_BLE_H +#define AM_HAL_BLE_H + +#include "am_hal_global.h" +#include "am_hal_status.h" + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable BLEIF module number. +// +#define BLEIFn(n) ((BLEIF_Type*)(BLEIF_BASE + (n * (BLEIF_BASE - BLEIF_BASE)))) +//***************************************************************************** + +//***************************************************************************** +// +// BLE-specific status values. +// +//***************************************************************************** +typedef enum +{ + // + // This error occurs when an HCI read or write function is called while + // another HCI communication function is already in progress. + // + AM_HAL_BLE_STATUS_BUS_BUSY = AM_HAL_STATUS_MODULE_SPECIFIC_START, + + // + // This error happens when the MCU tries to execute an HCI read, but the + // BLE core hasn't asserted the BLEIRQ line. Try waiting for a BLEIRQ + // interrupt, or polling the BLECIRQ bit in the BSTATUS register before + // calling an HCI read function. + // + AM_HAL_BLE_STATUS_IRQ_LOW, + + // + // This error means that the MCU tried to execute an HCI write, but the BLE + // core didn't assert its SPI_STATUS signal within the allotted timeout. + // This might mean that there has been some error inside the BLE core. This + // may require a reboot of the BLE core. + // + AM_HAL_BLE_STATUS_SPI_NOT_READY, + + // + // This error means we were trying to write, but the BLE core has requested + // a READ instead. We will need to perform a read before we can retry this + // write. + // + AM_HAL_BLE_REQUESTING_READ, + + // + // We are expecting an HCI response to a packet we just sent, but the BLE + // core isn't asserting BLEIRQ. Its software may have crashed, and it may + // need to restart. + // + AM_HAL_BLE_NO_HCI_RESPONSE, + + // + // Any of these errors indicate a problem with the BLE hardware that + // requires a complete restart. + // + AM_HAL_BLE_FEATURE_DISABLED, + AM_HAL_BLE_SHUTDOWN_FAILED, + AM_HAL_BLE_REGULATOR_FAILED, + AM_HAL_BLE_POWERUP_INCOMPLETE, + AM_HAL_BLE_HCI_PACKET_INCOMPLETE, + AM_HAL_BLE_FIFO_ERROR, + AM_HAL_BLE_32K_CLOCK_UNSTABLE, +} +am_ble_status_e; + +//***************************************************************************** +// +// BLE power modes. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_BLE_POWER_ACTIVE, + AM_HAL_BLE_POWER_OFF, +} +am_hal_ble_power_state_e; + +//***************************************************************************** +// +// BLE SPI Clock settings. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_BLE_HCI_CLK_DIV2 = BLEIF_CLKCFG_FSEL_HFRC_DIV2, + AM_HAL_BLE_HCI_CLK_DIV4 = BLEIF_CLKCFG_FSEL_HFRC_DIV4, + AM_HAL_BLE_HCI_CLK_DIV8 = BLEIF_CLKCFG_FSEL_HFRC_DIV8, + AM_HAL_BLE_HCI_CLK_DIV16 = BLEIF_CLKCFG_FSEL_HFRC_DIV16, + AM_HAL_BLE_HCI_CLK_DIV32 = BLEIF_CLKCFG_FSEL_HFRC_DIV32, + AM_HAL_BLE_HCI_CLK_DIV64 = BLEIF_CLKCFG_FSEL_HFRC_DIV8, +} +am_hal_ble_hci_clock_e; + +//***************************************************************************** +// +// BLE Core Clock settings. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_BLE_CORE_MCU_CLK = 0x02, + AM_HAL_BLE_CORE_INTERNAL_CLK = 0x00, +} +am_hal_ble_core_clock_e; + +//***************************************************************************** +// +// Interrupts. +// +//***************************************************************************** +// The B2M_STATE went into the shutdown state +#define AM_BLEIF_INT_B2MSHUTDN AM_REG_BLEIF_INTEN_B2MSHUTDN_M +// The B2M_STATE went into the active state +#define AM_BLEIF_INT_B2MACTIVE AM_REG_BLEIF_INTEN_B2MACTIVE_M +// The B2M_STATE went into the sleep state +#define AM_BLEIF_INT_B2MSLEEP AM_REG_BLEIF_INTEN_B2MSLEEP_M +// command queue received and error +#define AM_BLEIF_INT_CQERR AM_REG_BLEIF_INTEN_CQERR_M +// CQ write operation performed a register write with the register address bit +// 0 set to 1. The low address bits in the CQ address fields are unused and +// bit 0 can be used to trigger an interrupt to indicate when this register +// write is performed by the CQ operation. +#define AM_BLEIF_INT_CQUPD AM_REG_BLEIF_INTEN_CQUPD_M +// The command queue is waiting interrupt +#define AM_BLEIF_INT_CQPAUSED AM_REG_BLEIF_INTEN_CQPAUSED_M +// DMA Error +#define AM_BLEIF_INT_DERR AM_REG_BLEIF_INTEN_DERR_M +// DMA Complete +#define AM_BLEIF_INT_DCMP AM_REG_BLEIF_INTEN_DCMP_M +// THis is the BLE Core IRQ signal +#define AM_BLEIF_INT_BLECIRQ AM_REG_BLEIF_INTEN_BLECIRQ_M +// This is the illegal command interrupt. +#define AM_BLEIF_INT_ICMD AM_REG_BLEIF_INTEN_ICMD_M +// This is the illegal FIFO access interrupt. +#define AM_BLEIF_INT_IACC AM_REG_BLEIF_INTEN_IACC_M +// Any change in the B2M_STATE signal from the BLE Core will set this interrupt +#define AM_BLEIF_INT_B2MST AM_REG_BLEIF_INTEN_B2MST_M +// This is the Write FIFO Overflow interrupt. +#define AM_BLEIF_INT_FOVFL AM_REG_BLEIF_INTEN_FOVFL_M +// This is the Read FIFO Underflow interrupt. +#define AM_BLEIF_INT_FUNDFL AM_REG_BLEIF_INTEN_FUNDFL_M +// This is the FIFO Threshold interrupt. +#define AM_BLEIF_INT_THR AM_REG_BLEIF_INTEN_THR_M +// This is the Command Complete interrupt. +#define AM_BLEIF_INT_CMDCMP AM_REG_BLEIF_INTEN_CMDCMP_M + +#define AM_HAL_BLE_INT_B2MSHUTDN BLEIF_INTEN_B2MSHUTDN_Msk // The B2M_STATE went into the shutdown state +#define AM_HAL_BLE_INT_B2MACTIVE BLEIF_INTEN_B2MACTIVE_Msk // The B2M_STATE went into the active state +#define AM_HAL_BLE_INT_B2MSLEEP BLEIF_INTEN_B2MSLEEP_Msk // The B2M_STATE went into the sleep state +#define AM_HAL_BLE_INT_CQERR BLEIF_INTEN_CQERR_Msk // command queue received and error + +// CQ write operation performed a register write with the register address bit +// 0 set to 1. The low address bits in the CQ address fields are unused and +// bit 0 can be used to trigger an interrupt to indicate when this register +// write is performed by the CQ operation. +#define AM_HAL_BLE_INT_CQUPD BLEIF_INTEN_CQUPD_Msk + +#define AM_HAL_BLE_INT_CQPAUSED BLEIF_INTEN_CQPAUSED_Msk // The command queue is waiting interrupt +#define AM_HAL_BLE_INT_DERR BLEIF_INTEN_DERR_Msk // DMA Error +#define AM_HAL_BLE_INT_DCMP BLEIF_INTEN_DCMP_Msk // DMA Complete +#define AM_HAL_BLE_INT_BLECSSTAT BLEIF_INTEN_BLECSSTAT_Msk // This is the BLE Core SPI STATUS signal. +#define AM_HAL_BLE_INT_BLECIRQ BLEIF_INTEN_BLECIRQ_Msk // This is the BLE Core IRQ signal +#define AM_HAL_BLE_INT_ICMD BLEIF_INTEN_ICMD_Msk // This is the illegal command interrupt. +#define AM_HAL_BLE_INT_IACC BLEIF_INTEN_IACC_Msk // This is the illegal FIFO access interrupt. +#define AM_HAL_BLE_INT_B2MST BLEIF_INTEN_B2MST_Msk // Any change in the B2M_STATE signal from the BLE Core will set this interrupt +#define AM_HAL_BLE_INT_FOVFL BLEIF_INTEN_FOVFL_Msk // This is the Write FIFO Overflow interrupt. +#define AM_HAL_BLE_INT_FUNDFL BLEIF_INTEN_FUNDFL_Msk // This is the Read FIFO Underflow interrupt. +#define AM_HAL_BLE_INT_THR BLEIF_INTEN_THR_Msk // This is the FIFO Threshold interrupt. +#define AM_HAL_BLE_INT_CMDCMP BLEIF_INTEN_CMDCMP_Msk // This is the Command Complete interrupt. + +#define AM_HAL_BLE_INT_BLECSSTATN BLEIF_INTSTAT_B2MSHUTDN_Msk +#define AM_HAL_BLE_INT_BLECIRQN BLEIF_INTSTAT_B2MACTIVE_Msk + +//***************************************************************************** +// +// Type definitions. +// +//***************************************************************************** +#define am_hal_ble_buffer(A) \ + union \ + { \ + uint32_t words[(A + 3) >> 2]; \ + uint8_t bytes[A]; \ + } + +// Function pointer for non-blocking ble read callbacks. +typedef void (*am_hal_ble_transfer_complete_cb_t)(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext); + +// +// Patch container +// +typedef struct +{ + uint32_t ui32Type; + uint32_t ui32Length; + uint32_t ui32CRC; + const uint32_t *pui32Data; +} +am_hal_ble_patch_t; + +// +// Configuration structure for the BLE module. +// +typedef struct +{ + // HCI interface options. + uint32_t ui32SpiClkCfg; // Configure the HCI interface clock. + uint32_t ui32ReadThreshold; // Internal HCI READ FIFO size + uint32_t ui32WriteThreshold; // Internal HCI WRITE FIFO size. + + // BLE options. + uint32_t ui32BleClockConfig; // Configure the BLE core clock. + uint32_t ui32ClockDrift; // Set the expected BLE clock drift. + uint32_t ui32SleepClockDrift; // Set the expected sleep clock accuracy. + bool bAgcEnabled; // Enable/Disable AGC + bool bSleepEnabled; // Enable/Disable Sleep Algorithm + + // Patches + bool bUseDefaultPatches; // Apply the default patches? +} +am_hal_ble_config_t; + +// +// Default options for the BLE module. +// +extern const am_hal_ble_config_t am_hal_ble_default_config; + +//***************************************************************************** +// +// Structure for sending SPI commands. +// +//***************************************************************************** +typedef struct +{ + uint32_t *pui32Data; + uint8_t pui8Offset[3]; + uint8_t ui8OffsetLen; + uint16_t ui16Length; + uint8_t ui8Command; + uint8_t ui8RepeatCount; + bool bContinue; + am_hal_ble_transfer_complete_cb_t pfnTransferCompleteCB; + void *pvContext; +} +am_hal_ble_transfer_t; + +//***************************************************************************** +// +// Vendor Specific commands. +// +// Note: Lengths are reported as "4 + ". Each vendor-specific +// header is 4 bytes long. This definition allows the macro version of the +// length to be used in all BLE APIs. +// +//***************************************************************************** +#define AM_HAL_BLE_SET_BD_ADDR_OPCODE 0xFC32 +#define AM_HAL_BLE_SET_BD_ADDR_LENGTH (4 + 6) + +#define AM_HAL_BLE_SET_TX_POWER_OPCODE 0xFC3B +#define AM_HAL_BLE_SET_TX_POWER_LENGTH (4 + 3) + +#define AM_HAL_BLE_READ_VERSIONS_OPCODE 0xFD01 +#define AM_HAL_BLE_READ_VERSIONS_LENGTH (4 + 0) + +#define AM_HAL_BLE_PLF_REGISTER_READ_OPCODE 0xFD02 +#define AM_HAL_BLE_PLF_REGISTER_READ_LENGTH (4 + 4) + +#define AM_HAL_BLE_PLF_REGISTER_WRITE_OPCODE 0xFD03 +#define AM_HAL_BLE_PLF_REGISTER_WRITE_LENGTH (4 + 8) + +#define AM_HAL_BLE_GET_RSSI_OPCODE 0x1405 +#define AM_HAL_BLE_GET_RSSI_LENGTH (4 + 0) + +#define AM_HAL_BLE_SET_SLEEP_OPCODE 0xFD09 +#define AM_HAL_BLE_SET_SLEEP_LENGTH (4 + 0) + +#define AM_HAL_BLE_SPI_SENDFRAME_OPCODE 0xFD04 +#define AM_HAL_BLE_SPI_SENDFRAME_LENGTH (4 + 1) + +#define AM_HAL_BLE_SET_BD_ADDR_CMD(...) {0x01, 0x32, 0xFC, 0x06, __VA_ARGS__} +#define AM_HAL_BLE_SET_TX_POWER_CMD(...) {0x01, 0x3B, 0xFC, 0x03, __VA_ARGS__} +#define AM_HAL_BLE_SET_READ_VERSIONS_CMD() {0x01, 0x01, 0xFD, 0x00} +#define AM_HAL_BLE_PLF_REGISTER_READ_CMD(...) {0x01, 0x02, 0xFD, 0x04, __VA_ARGS__} +#define AM_HAL_BLE_PLF_REGISTER_WRITE_CMD(...) {0x01, 0x03, 0xFD, 0x08, __VA_ARGS__} +#define AM_HAL_BLE_GET_RSSI_CMD() {0x01, 0x05, 0x14, 0x00} +#define AM_HAL_BLE_SET_SLEEP_CMD() {0x01, 0x09, 0xFD, 0x00} +#define AM_HAL_BLE_SPI_SENDFRAME_CMD(...) {0x01, 0x04, 0xFD, 0x01, __VA_ARGS__} + +//***************************************************************************** +// +// State variables for the BLE module. +// +//***************************************************************************** +typedef struct +{ + // Handle validation prefix. + am_hal_handle_prefix_t prefix; + + // Which BLE module instance is this? + uint32_t ui32Module; + + // Apply the default patches during the "boot" function? + bool bUseDefaultPatches; + + // What was the last command that we started? + am_hal_ble_transfer_t sCurrentTransfer; + + // If a write is interrupted by a read, we have to save the write + // transaction to execute later. That saved write goes here. + am_hal_ble_transfer_t sSavedTransfer; + + // How far along are we? + uint32_t ui32TransferIndex; + + // Has this radio already been patched? + bool bPatchComplete; + + // Are we in the middle of a continue packet? + bool bContinuePacket; + + // Was our last operation to send a TX packet? If we have two TX packets in + // a row, we need special handling to get the timing right. + bool bLastPacketWasTX; + + // Do we have a saved packet? + bool bSavedPacket; + + // Is the bus already in use? + bool bBusy; + + // Has the last command completed? + bool bCmdComplete; + + // Has the last DMA action completed? + bool bDmaComplete; + + // Has the BLE core's flow control signal been reset? + bool bFlowControlComplete; +} +am_hal_ble_state_t; + +//***************************************************************************** +// +// SPI command macros. +// +//***************************************************************************** +#define AM_HAL_BLE_WRITE 1 +#define AM_HAL_BLE_READ 2 + +//***************************************************************************** +// +// HCI packet types. +// +//***************************************************************************** +#define AM_HAL_BLE_RAW 0x0 +#define AM_HAL_BLE_CMD 0x1 +#define AM_HAL_BLE_ACL 0x2 +#define AM_HAL_BLE_EVT 0x4 + +//***************************************************************************** +// +// External function declarations. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Basics +// +// Initialization, enable/disable, and general configuration. +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief Initialize the internal state variables for the BLE module. +//! +//! @param ui32Module - Which BLE module to use. +//! @param ppHandle - Pointer to a handle variable to be initialized. +//! +//! This function initializes the internal state variables associated with a +//! particular BLE module and yields a handle that may be used to perform +//! additional operations with that BLE module. +//! +//! This function must be called before any other BLE module operation. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_initialize(uint32_t ui32Module, void **ppHandle); + +//***************************************************************************** +// +//! @brief De-initialize the internal state variables for the BLE module. +//! +//! @param pHandle - Handle variable to be de-initialized. +//! +//! This function invalidates a previously initialized BLE module handle and +//! deletes the contents of the internal state variables associated with it. +//! This could be used in situations where the caller wants to prevent future +//! function calls to a particular BLE module. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_deinitialize(void *pHandle); + +//***************************************************************************** +// +//! @brief Configure a BLE module. +//! +//! @param pHandle - Handle for the BLE module. +//! @param psConfig - Pointer to a BLE configuration structure. +//! +//! This routine performs the necessary configuration steps to prepare the +//! physical BLE interface for operation. This function should be called after +//! \e am_hal_ble_enable() and before any other BLE operation. The \e psConfig +//! parameter may be used to set a specific interface clock frequency or modify +//! the FIFO read and write thresholds, but most users will get the best +//! results from the default settings stored in the global configuration +//! structure \e am_hal_ble_default_config. +//! +//! @note This function will only work if the BLE module has previously been +//! enabled. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_config(void *pHandle, const am_hal_ble_config_t *psConfig); + +//***************************************************************************** +// +//! @brief Enable the BLE module. +//! +//! @param pHandle - Handle for the BLE module. +//! @param ui32PowerState - Determines whether BLE is powered on or off. +//! +//! Performs the power-up or power-down sequence for the BLE module referred to +//! be \e pHandle. This should be called after am_hal_ble_initialize(), but +//! before am_hal_ble_config(). +//! +//! The ui32PowerState variable must be set to either AM_HAL_BLE_POWER_ACTIVE +//! or AM_HAL_BLE_POWER_OFF. +//! +//! After this function is called, the BLE core will be in its startup or +//! "patching" mode. +//! +//! @return BLE status code. +// +//***************************************************************************** +uint32_t am_hal_ble_power_control(void *pHandle, uint32_t ui32PowerState); + +//***************************************************************************** +// +//! @brief Boot the BLE module +//! +//! @param pHandle - Handle for the BLE module. +//! +//! This function performs the complete patching process for the BLE core and +//! returns with the BLE core in HCI mode. If you ask for the default patches +//! your am_hal_ble_config_t structure, then this is the last function you need +//! to call on startup. You don't need to call any of the patching functions. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_boot(void *pHandle); + +//***************************************************************************** +// +// Patching functions. +// +// The following functions allow the caller to apply "patches" to the BLE core +// during its startup phase. These are pre-made configuration files that change +// the operation parameters of the BLE radio. If you have received a patch file +// from the manufacturer, you may use the \e am_hal_ble_patch_apply() function +// during startup to apply these settings to the BLE core. Otherwise, you may +// skip this step by calling the \e am_hal_ble_patch_complete() function. +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief Apply a patch to the BLE core. +//! +//! @param pHandle Handle for the BLE module. +//! @param psPatch Pointer to a structure describing the patch. +//! +//! The BLE core is an independent processor that executes code from an +//! on-board ROM. Its behavior can be altered through "patches" which are +//! binary snippets of code that may be loaded at startup to overlay or replace +//! sections of the original ROM (for instance, to modify trim settings). This +//! function allows the caller to apply one of these patches. +//! +//! Patches must be applied after the BLE module is enabled and configured, but +//! before standard HCI operation begins. This is the only time where the BLE +//! core is able to accept patch files. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_patch_apply(void *pHandle, am_hal_ble_patch_t *psPatch); + +extern uint32_t am_hal_ble_default_copy_patch_apply(void *pHandle); + +//***************************************************************************** +// +//! @brief Apply the default manufacturer patch to the BLE core. +//! +//! @param pHandle Handle for the BLE module. +//! @param psPatch Pointer to a structure describing the patch. +//! +//! The BLE core is an independent processor that executes code from an +//! on-board ROM. Its behavior can be altered through "patches" which are +//! binary snippets of code that may be loaded at startup to overlay or replace +//! sections of the original ROM (for instance, to modify trim settings). This +//! function allows the caller to apply one of these patches. +//! +//! Patches must be applied after the BLE module is enabled and configured, but +//! before standard HCI operation begins. This is the only time where the BLE +//! core is able to accept patch files. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_default_patch_apply(void *pHandle); + +//***************************************************************************** +// +//! @brief Complete the patching phase. +//! +//! @param pHandle Handle for the BLE module. +//! +//! After the BLE core is enabled and configured, it enters a "patching mode" +//! where it can accept patches from the main CPU. Once all patches have been +//! applied using the \e am_hal_ble_patch_apply() function. The application +//! must call this function to command the BLE core to switch to standard HCI +//! mode. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_patch_complete(void *pHandle); + +//***************************************************************************** +// +// Manually enable/disable transmitter +// set ui8TxCtrl as 1 to manually enale transmitter, 0 back to default +// +//***************************************************************************** +extern uint32_t am_hal_ble_transmitter_control(void *pHandle, uint8_t ui8TxCtrl); + +//***************************************************************************** +// +// Manually enable/disable transmitter to output carrier signal +// set ui8TxChannel as 0 to 0x27 for each transmit channel, 0xFF back to normal modulate mode +// +//***************************************************************************** +extern uint32_t am_hal_ble_transmitter_control_ex(void *pHandle, uint8_t ui8TxChannel); +//***************************************************************************** +// +// Manually set modulation characteristic +// based on the tested values at customer side. +// manually set frequency offset for 10101010 or 01010101 pattern +// +//***************************************************************************** +extern uint32_t am_hal_ble_transmitter_modex_set(void *pHandle, uint8_t ui8ModFrqOffset); + +//***************************************************************************** +// +//! @brief Performs a blocking read or write to the BLE core. +//! +//! @param pHandle - Handle for the BLE module. +//! @param psTransfer - Structure describing the transaction to execute. +//! +//! Send or receive data from the +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_blocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer); + +//***************************************************************************** +// +//! @brief Complete the patching phase. +//! +//! @param pHandle Handle for the BLE module. +//! +//! After the BLE core is enabled and configured, it enters a "patching mode" +//! where it can accept patches from the main CPU. Once all patches have been +//! applied using the \e am_hal_ble_patch_apply() function. The application +//! must call this function to command the BLE core to switch to standard HCI +//! mode. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_nonblocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer); + +// High-level HCI APIs +extern uint32_t am_hal_ble_vs_command_build(uint32_t *pui32Command, + uint32_t ui32OpCode, + uint32_t ui32TotalLength, + uint8_t *pui8Parameters); + +extern uint32_t am_hal_ble_blocking_hci_read(void *pHandle, + uint32_t *pui32Data, + uint32_t *pui32BytesReceived); + +extern uint32_t am_hal_ble_blocking_hci_write(void *pHandle, + uint8_t ui8Type, + uint32_t *pui32Data, + uint32_t ui32NumBytes); + +extern uint32_t am_hal_ble_nonblocking_hci_read(void *pHandle, + uint32_t *pui32Data, + am_hal_ble_transfer_complete_cb_t pfnCallback, + void *pvContext); + +extern uint32_t am_hal_ble_nonblocking_hci_write(void *pHandle, + uint8_t ui8Type, + uint32_t *pui32Data, + uint32_t ui32NumBytes, + am_hal_ble_transfer_complete_cb_t pfnCallback, + void *pvContext); + +//***************************************************************************** +// +//! @brief Set one of the trim values for the BLE core. +//! +//! @param pHandle is the BLE module handle +//! @param ui32BleCoreAddress is the target address for the trim value. +//! @param ui32TrimValue is the trim value to write to the BLE core. +//! +//! This function takes a BLE core trim value from the MCU memory and writes it +//! to a trim register in the BLE core. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_trim_set(void *pHandle, uint32_t ui32BleCoreAddress, + uint32_t ui32TrimValue, uint32_t ui32TrimMask); + +//***************************************************************************** +// +//! @brief Sets the default trim values for the BLE core. +//! +//! @param pHandle is the BLE module handle +//! +//! This function reads the default trim values for the BLE core from +//! non-volatile memory, and writes them to the BLE core registers. +//! Specifically, this function adjusts the BLE core bandgap voltage, bandgap +//! current, and memory-retention LDO voltage based on chip-specific, +//! manufacturer-determined settings. +//! +//! For best performance and power consumption, this function should be called +//! after the patching process is complete, but before normal HCI operation +//! begins. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_default_trim_set(void *pHandle); + +uint32_t am_hal_ble_default_trim_set_ramcode(void *pHandle); + +//***************************************************************************** +// +//! @brief Change the TX power setting. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param ui32TxPower is the desired power setting. +//! 0x03->-20dBm 0x04->-10dBm 0x05->-5dBm 0x08->0dBm 0x0F->4dBm +//! +//! This function sends a vendor-specific command to change the TX power level +//! setting for the BLE core. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_tx_power_set(void *pHandle, uint8_t ui32TxPower); + +//***************************************************************************** +// +//! @brief Generate continuously moderated signal for SRRC/CE test. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param enable, true for enabling continous signal, false for disable +//! +//! This function programs an internal register to control transmit mode in +//! BLE controller. +//! +//! @return BLE status code. +// +//***************************************************************************** + +extern uint32_t am_hal_ble_set_constant_transmission(void *pHandle, bool enable); + +//***************************************************************************** +// +//! @brief Generate continuously moderated signal for SRRC/CE test on a +//! specified rf channel. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param channel, 0 to 0x27 for a valid radio channnel while 0xff to set +//! radio transmit mode to normal. +//! +//! This function calls am_hal_ble_set_constant_transmission() and send HCI +//! test command with channel information to BLE controller. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_set_constant_transmission_ex(void *pHandle, uint8_t channel); + +//***************************************************************************** +// +//! @brief This is to workaround a bug for channel 1 in DTM mode. +//! +//! @param pHandle is the Handle for the BLE module. +//! +//! @return BLE status code. +// +// +extern uint32_t am_hal_ble_init_rf_channel(void *pHandle); + +//***************************************************************************** +// +//! @brief This function should be called with enable set to true for +//! BQB testing. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param enable, true for enabling BQB test mode, false for normal mode +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_BQB_test_init(void *pHandle, bool enable); + +//***************************************************************************** +// +//! @brief Set BLE sleep enable/disable for the BLE core. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param enable 'true' set sleep enable, 'false' set sleep disable +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_sleep_set(void *pHandle, bool enable); + +//***************************************************************************** +// +//! @brief Sends a signal to wake up the BLE controller +//! +//! @param pHandle is the Handle for the BLE module. +//! @param ui32Mode is determines the value of the WAKE signal. +//! +//! The BLE core needs to be awake before we send data to it. This function +//! sends a signal to the BLE core that tells it that we intend to send it +//! data. When the BLE core wakes up, it will generate a BLECSSTAT interrupt, +//! and the SPISTATUS bit in the BSTATUS register will be set. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_wakeup_set(void *pHandle, uint32_t ui32Mode); + +//***************************************************************************** +// +//! @brief Read a register value directly from the BLE Core. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param ui32Address is the address of the register. +//! @param *pui32Value is a pointer where the register value will be stored. +//! +//! This function uses a vendor-specific sequence of blocking HCI commands to +//! read one of the internal registers within the BLE Core. The value stored in +//! this register will be written to the location specified by \e pui32Value. +//! +//! This function is mostly used during initial radio setup or for internal +//! test commands. Standard applications will not need to call this function +//! directly. +//! +//! @note This function uses multiple blocking HCI commands in sequence. It +//! should not be used in any situation where blocking commands are not +//! desired. Do not use it in applications where interrupt-driven BLE +//! operations have already started. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Value); + +//***************************************************************************** +// +//! @brief Write a register value directly to the BLE Core. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param ui32Address is the address of the register. +//! @param ui32Value is the value to write. +//! +//! This function uses a vendor-specific sequence of blocking HCI commands to +//! write one of the internal registers within the BLE Core. +//! +//! This function is mostly used during initial radio setup or for internal +//! test commands. Standard applications will not need to call this function +//! directly. +//! +//! @note This function uses multiple blocking HCI commands in sequence. It +//! should not be used in any situation where blocking commands are not +//! desired. Do not use it in applications where interrupt-driven BLE +//! operations have already started. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_plf_reg_write(void *pHandle, uint32_t ui32Address, uint32_t ui32Value); + +//***************************************************************************** +// +//! @brief Change the sleep behavior of the BLE core. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param enable sets the desired sleep behavior. +//! +//! This function uses a vendor-specific sequence of blocking HCI commands to +//! change the default behavior of the BLE core between radio events. Set \e +//! enable to true to allow the BLE core to sleep between radio events, or +//! false to keep the BLE core awake at all times. The default behavior on +//! startup allows the BLE core to sleep. Most applications will not need to +//! modify this setting. +//! +//! @note This function uses multiple blocking HCI commands in sequence. It +//! should not be used in any situation where blocking commands are not +//! desired. Do not use it in applications where interrupt-driven BLE +//! operations have already started. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_sleep_set(void *pHandle, bool enable); + +//***************************************************************************** +// +//! @brief Check the sleep behavior of the BLE core. +//! +//! @param pHandle is the Handle for the BLE module. +//! +//! This function uses a vendor-specific sequence of blocking HCI commands to +//! check whether the BLE core is set to go to sleep between BLE transactions. +//! This function will return "true" if BLE sleep is enabled, or "false" if it +//! is disabled. +//! +//! @note This function uses multiple blocking HCI commands in sequence. It +//! should not be used in any situation where blocking commands are not +//! desired. Do not use it in applications where interrupt-driven BLE +//! operations have already started. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern bool am_hal_ble_sleep_get(void *pHandle); + +//***************************************************************************** +// +//! @brief Change the TX power setting of the BLE core. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param uint8_t is the desired power setting. +//! +//! This function uses a vendor-specific sequence of blocking HCI commands to +//! change the TX power setting of the radio. +//! +//! @note This function uses multiple blocking HCI commands in sequence. It +//! should not be used in any situation where blocking commands are not +//! desired. Do not use it in applications where interrupt-driven BLE +//! operations have already started. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_tx_power_set(void *pHandle, uint8_t ui32TxPower); + +//***************************************************************************** +// +// Interrupts. +// +//***************************************************************************** +extern uint32_t am_hal_ble_int_service(void *pHandle, uint32_t ui32Status); +extern uint32_t am_hal_ble_int_enable(void *pHandle, uint32_t ui32InterruptMask); +extern uint32_t am_hal_ble_int_disable(void *pHandle, uint32_t ui32InterruptMask); +extern uint32_t am_hal_ble_int_status(void *pHandle, bool bEnabledOnly); +extern uint32_t am_hal_ble_int_clear(void *pHandle, uint32_t ui32InterruptMask); +extern uint32_t am_hal_ble_check_32k_clock(void *pHandle); +//***************************************************************************** +// +// Debug trace pins. +// +//***************************************************************************** +#ifdef AM_DEBUG_BLE_TIMING + +#define BLE_DEBUG_TRACE_01 11 +#define BLE_DEBUG_TRACE_02 28 +#define BLE_DEBUG_TRACE_03 26 +#define BLE_DEBUG_TRACE_04 4 +#define BLE_DEBUG_TRACE_05 18 +#define BLE_DEBUG_TRACE_06 14 +#define BLE_DEBUG_TRACE_07 6 +#define BLE_DEBUG_TRACE_08 45 +#define BLE_DEBUG_TRACE_09 12 +#define BLE_DEBUG_TRACE_10 13 +#define BLE_DEBUG_TRACE_11 10 +#define BLE_LOCK_TRACE_PIN BLE_DEBUG_TRACE_11 + +#define am_hal_debug_gpio_set(x) am_hal_gpio_state_write(x, AM_HAL_GPIO_OUTPUT_SET) + +#define am_hal_debug_gpio_clear(x) am_hal_gpio_state_write(x, AM_HAL_GPIO_OUTPUT_CLEAR) + +#define am_hal_debug_gpio_toggle(x) am_hal_gpio_state_write(x, AM_HAL_GPIO_OUTPUT_TOGGLE) + +#define am_hal_debug_gpio_pinconfig(x) am_hal_gpio_pinconfig(x, g_AM_HAL_GPIO_OUTPUT) + +#else + +#define am_hal_debug_gpio_set(...) +#define am_hal_debug_gpio_clear(...) +#define am_hal_debug_gpio_toggle(...) +#define am_hal_debug_gpio_pinconfig(...) + +#endif // AM_DEBUG_BLE_TIMING + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_BLE_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.c new file mode 100644 index 0000000..c0ffcc0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.c @@ -0,0 +1,705 @@ +//***************************************************************************** +// +//! @file am_hal_ble_patch.c +//! +//! @brief This is a binary patch for the BLE core. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// BLE LL local supported feature flags. +// +// Bit position | Link Layer Feature +// 0 | LE Encryption +// 1 | Connection Parameters Request Procedure +// 2 | Extended Reject Indication +// 3 | Slave-initiated Features Exchange +// 4 | LE Ping +// 5 | LE Data Packet Length Extension +// 6 | LL Privacy +// 7 | Extended Scanner Filter Policies +// +// Specified 4.6 Feature Support, Link Layer Specification, Core V4.2. +// +//***************************************************************************** +#ifndef AM_HAL_BLE_LOCAL_FEATURE +#define AM_HAL_BLE_LOCAL_FEATURE 0x21 +#endif + +//***************************************************************************** +// +// Patches included in this file. +// +//***************************************************************************** +am_hal_ble_patch_t am_ble_buffer_patch; +am_hal_ble_patch_t am_ble_performance_patch; +am_hal_ble_patch_t am_ble_performance_copy_patch; +am_hal_ble_patch_t am_ble_nvds_patch; + +//***************************************************************************** +// +// Patch application order. +// +//***************************************************************************** +am_hal_ble_patch_t *am_hal_ble_default_patch_array[] = +{ + // FTCODE patches (type 0xAA) + + // RAMCODE patches (type 0xBB) + &am_ble_performance_patch, + + // Standard patches (type 0xCC) + &am_ble_buffer_patch, + + // nvds param (type 0xDD) + &am_ble_nvds_patch, +}; + +am_hal_ble_patch_t *am_hal_ble_default_copy_patch_array[] = +{ + // FTCODE patches (type 0xAA) + + // RAMCODE patches (type 0xBB) + &am_ble_performance_copy_patch, + +}; + +#define AM_HAL_BLE_NUM_DEFAULT_PATCHES \ + (sizeof(am_hal_ble_default_patch_array) / \ + sizeof(am_hal_ble_default_patch_array[0])) + +am_hal_ble_patch_t **am_hal_ble_default_patches = am_hal_ble_default_patch_array; +am_hal_ble_patch_t **am_hal_ble_default_copy_patches = am_hal_ble_default_copy_patch_array; + +const uint32_t am_hal_ble_num_default_patches = AM_HAL_BLE_NUM_DEFAULT_PATCHES; + +//***************************************************************************** +// +// Patch Name: RAMCODE COPY PATCH v1.10 for Apollo3 A1 +// +// Bi-directional data fix +// Modulation deviation fix +// Extend patch memory +// Transmit speed patch +// Added AGC table and enabled AGC +// Added local feature support setting +// Fix to connection interval calculation issue with MTK chip sets (OPPO R15 fix) +// Set VCO to 250mv +// Modex auto calibration update +// Fix connection interval calculation issue +// Increase RF LDO ref voltage form 1.0v to 1.1v +// Decrease DAC channel delay cycle +// Increase the VCO swing from 250mv to 300mv +// Fix MD trans schedule issue (disabled) +// Fix link loss issue +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Fix channel map rejected issue +// Optimized AGC Table +// Date: 2019-01-30 +//***************************************************************************** + +const am_hal_ble_buffer(0x0912) am_ble_performance_copy_patch_data = +{ + .bytes = + { + 0x00,0x11,0x6e,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0xc5,0x01, + 0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff,0x70,0xb5,0x00,0x20,0x0c,0x49,0x49,0x88, + 0x0c,0x4a,0x8b,0x18,0x1a,0x88,0x0c,0x49,0x9b,0x1c,0x00,0x24,0x13,0x25,0x2d,0x02, + 0x0c,0x54,0x40,0x1c,0xa8,0x42,0xfb,0xdb,0x00,0x20,0x00,0x2a,0x04,0xdd,0x1c,0x5c, + 0x0c,0x54,0x40,0x1c,0x90,0x42,0xfa,0xdb,0x04,0x48,0x80,0x47,0x00,0x20,0x70,0xbd, + 0x00,0x48,0x00,0x20,0x02,0x48,0x00,0x20,0x00,0x35,0x00,0x20,0xaf,0x33,0x01,0x00, + 0xa0,0x08,0x1f,0xb5,0x00,0x24,0x00,0x98,0x1d,0x28,0x43,0xd2,0x01,0x00,0x79,0x44, + 0x09,0x79,0x49,0x18,0x8f,0x44,0x0e,0x13,0x40,0x1a,0x25,0x40,0x40,0x40,0x40,0x40, + 0x40,0x40,0x40,0x40,0x40,0x40,0x2a,0x40,0x40,0x40,0x40,0x2d,0x40,0x32,0x40,0x35, + 0x38,0x40,0x40,0x00,0x01,0x98,0xc0,0xb2,0x00,0xf0,0x07,0xfa,0x2c,0xe0,0x02,0x98, + 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0x01,0x00,0x40,0x60,0x00,0x20,0xa1,0x3b,0x00,0x00,0x99,0x4d,0x01,0x00,0xcc,0x34, + 0x63,0x04,0x70,0x60,0x00,0x20,0x3a,0x60,0x00,0x20,0x4e,0x60,0x00,0x20,0xad,0x34, + 0x01,0x00 + } +}; + +am_hal_ble_patch_t am_ble_performance_copy_patch = +{ + .ui32Type = 0xBB, + .ui32Length = 0x0912, + .ui32CRC = 0x9516, + .pui32Data = am_ble_performance_copy_patch_data.words, +}; + +//***************************************************************************** +// +// Patch Name: RAMCODE PATCH v1.10 for Apollo3 A1 +// +// Bi-directional data fix +// Modulation deviation fix +// Extend patch memory +// Transmit speed patch +// Added AGC table and enabled AGC +// Added local feature support setting +// Fix to connection interval calculation issue with MTK chip sets (OPPO R15 fix) +// Set VCO to 250mv +// Modex auto calibration update +// Fix connection interval calculation issue +// Increase RF LDO ref voltage form 1.0v to 1.1v +// Decrease DAC channel delay cycle +// Increase the VCO swing from 250mv to 300mv +// Fix MD trans schedule issue (disabled) +// Fix link loss issue +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Fix channel map rejected issue +// Optimized AGC Table +// Date: 2019-01-30 +//***************************************************************************** + +am_hal_ble_buffer(0x0104) am_ble_performance_patch_data = +{ + .bytes = + { + 0x00,0x11,0x02,0x01,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x01,0xc5,0x01, + 0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x1b,0x00,0xa1,0x06,0x1f,0xb5,0x82,0xb0,0x08,0x98,0x00,0x90, + 0x02,0xa8,0x0f,0xc8,0x01,0x4c,0xa0,0x47,0x06,0xb0,0x10,0xbd,0x01,0x35,0x00,0x20, + 0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x08,0x48,0x80,0x47,0x00,0xbf,0x00,0xbf, + 0x02,0x2d,0x05,0xd1,0x06,0x48,0x80,0x47,0x00,0xbf,0x00,0xbf,0x05,0x48,0x80,0x47, + 0x00,0x21,0x03,0x9a,0x04,0x98,0x90,0x47,0x03,0x48,0x00,0x47,0x99,0x4a,0x01,0x00, + 0x25,0x4b,0x01,0x00,0xaf,0x4a,0x01,0x00,0x8f,0x4c,0x01,0x00,0x00,0x00,0x00,0x00, + 0x04,0x48,0x01,0x68,0x28,0x22,0x11,0x43,0x50,0x22,0x91,0x43,0x01,0x60,0x00,0xbf, + 0x01,0x48,0x00,0x47,0x00,0x00,0xc0,0x52,0x63,0x2a,0x00,0x00,0x00,0x00,0x00,0x00, + 0x04,0x48,0x01,0x68,0x50,0x22,0x11,0x43,0x28,0x22,0x91,0x43,0x01,0x60,0x00,0xbf, + 0x01,0x48,0x00,0x47,0x00,0x00,0xc0,0x52,0x83,0x2a,0x00,0x00,0x00,0xbf,0x00,0xbf, + 0x00,0xbf,0x00,0xbf,0x08,0x98,0x00,0x28,0x01,0xd0,0x01,0x20,0x02,0x90,0x00,0x20, + 0x60,0x85,0x01,0x48,0x00,0x47,0x00,0xbf,0xd5,0xed,0x00,0x00,0x00,0xbf,0x00,0xbf, + 0x60,0x88,0x00,0x28,0x04,0xd1,0x10,0x7d,0x08,0x28,0x01,0xd3,0x04,0x20,0x10,0x75, + 0x02,0x98,0x81,0x79,0x01,0x20,0x01,0x43,0x02,0x98,0x81,0x71,0x00,0x48,0x00,0x47, + 0xa5,0xf7,0x00,0x00 + } +}; + +am_hal_ble_patch_t am_ble_performance_patch = +{ + .ui32Type = 0xBB, + .ui32Length = 0x0104, + .ui32CRC = 0x933d, + .pui32Data = am_ble_performance_patch_data.words, +}; + +//***************************************************************************** +// +// Patch Name: Function PATCH v1.10 for Apollo3 A1 +// +// Bi-directional data fix +// Modulation deviation fix +// Extend patch memory +// Transmit speed patch +// Added AGC table and enabled AGC +// Added local feature support setting +// Fix to connection interval calculation issue with MTK chip sets (OPPO R15 fix) +// Set VCO to 250mv +// Modex auto calibration update +// Fix connection interval calculation issue +// Increase RF LDO ref voltage form 1.0v to 1.1v +// Decrease DAC channel delay cycle +// Increase the VCO swing from 250mv to 300mv +// Fix MD trans schedule issue (disabled) +// Fix link loss issue +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Fix channel map rejected issue +// Optimized AGC Table +// Date: 2019-01-30 +//***************************************************************************** + +const am_hal_ble_buffer(0x0d38) am_ble_buffer_patch_data = +{ + .bytes = + { + 0x00,0x22,0x38,0x0d,0xff,0xff,0x00,0x00,0x32,0x35,0x09,0x00,0x65,0x39,0x09,0x00, + 0x2b,0x45,0x09,0x00,0xa9,0x48,0x09,0x00,0xf7,0x53,0x09,0x00,0x1a,0x5c,0x09,0x00, + 0x1c,0x64,0x09,0x00,0xfd,0x6a,0x09,0x00,0x1a,0x75,0x09,0x00,0xde,0x7b,0x09,0x00, + 0x4b,0x85,0x09,0x00,0xb3,0x8b,0x09,0x00,0x1f,0x95,0x09,0x00,0x4f,0x9c,0x09,0x00, + 0xf5,0xa2,0x09,0x00,0x1e,0xad,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x00,0x47, + 0x41,0x48,0x00,0x20,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x05,0xb0,0xf0,0xbd,0x00,0x00, + 0x90,0x67,0x00,0x20,0x10,0x27,0x00,0x00,0x00,0x10,0x00,0x20,0x88,0x13,0x00,0x00, + 0x18,0x10,0x00,0x20,0xff,0x03,0x00,0x00,0xff,0xb5,0xff,0xb0,0x82,0xb0,0x07,0x46, + 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0x00,0x19,0x4c,0x0d,0x00,0x19,0x4c,0x0e,0x00,0x19,0xc9,0x0f,0x40,0x18,0xc0,0x08, + 0x00,0x2b,0x01,0xd0,0x10,0x18,0x01,0xe0,0x10,0x1a,0x40,0x1e,0x40,0x1e,0x10,0xbc, + 0x70,0x47,0x00,0x00,0x54,0x60,0x00,0x20,0xf0,0xb4,0x00,0x23,0x18,0x4c,0xe5,0x6b, + 0x18,0x49,0x7d,0x22,0x09,0x68,0x12,0x02,0x91,0x42,0x02,0xd3,0x8a,0x1a,0x01,0x23, + 0x00,0xe0,0x52,0x1a,0x06,0x46,0x56,0x43,0xf2,0x13,0x51,0x43,0x71,0x1a,0x1e,0x26, + 0x4e,0x43,0x4f,0x10,0xf6,0x19,0x8f,0x11,0xf6,0x19,0x49,0x12,0x71,0x18,0xce,0x13, + 0x00,0x2b,0x01,0xd0,0x80,0x1a,0x00,0xe0,0x10,0x18,0x42,0x19,0x91,0x08,0x8d,0x00, + 0x52,0x1b,0x00,0x2b,0x04,0xd0,0x43,0x01,0x18,0x1a,0x40,0x18,0x80,0x1b,0x03,0xe0, + 0x43,0x01,0x18,0x1a,0x40,0x18,0x80,0x19,0xe2,0x63,0xf0,0xbc,0x70,0x47,0x00,0x00, + 0x80,0x67,0x00,0x20,0x54,0x60,0x00,0x20 + } +}; + +am_hal_ble_patch_t am_ble_buffer_patch = +{ + .ui32Type = 0xCC, + .ui32Length = 0x0d38, + .ui32CRC = 0xf515, + .pui32Data = am_ble_buffer_patch_data.words, +}; + +//***************************************************************************** +// +// Patch Name: NVDS v1.10 for Apollo3 A1 +// +// Bi-directional data fix +// Modulation deviation fix +// Extend patch memory +// Transmit speed patch +// Added AGC table and enabled AGC +// Added local feature support setting +// Fix to connection interval calculation issue with MTK chip sets (OPPO R15 fix) +// Set VCO to 250mv +// Modex auto calibration update +// Fix connection interval calculation issue +// Increase RF LDO ref voltage form 1.0v to 1.1v +// Decrease DAC channel delay cycle +// Increase the VCO swing from 250mv to 300mv +// Fix MD schedule issue (disabled) +// Fix link loss issue +// Reduce duration from TX to TX +// Optimized power consumption (32K clock drift,sleep clock accuracy,,advertising interval (undirect)) +// Date: 2019-01-30 +// +//***************************************************************************** +am_hal_ble_buffer(0x00be) am_ble_buffer_nvds_data = +{ + .bytes = + { + 0x4e,0x56,0x44,0x53, //NVDS_MAGIC_NUMBER + 0x01,0x06,0x06,0xef,0xab,0x23,0x88,0x77,0x56, //bluetooth address + 0x02,0x06,0x0a,0x4e,0x5a,0x38,0x38,0x30,0x31,0x56,0x31,0x41,0x00, //device name + 0x03,0x06,0x01,0x00, //system clock frequency, 00=32MHz 01=24MHz others=16MHz + 0x07,0x06,0x02,0x00,0x00, //32K clock drift, 0x01f4 = 500 ppm + 0x0c,0x06,0x02,50,0x00, //sleep clock accuracy, 0x01f4 = 500 ppm + 0x08,0x06,0x01,0x00, //01 for BQB qualification, 00 for normal usage + 0x09,0x06,0x01,0x02, //clock source selection, 00 = internal RC32KHz, 02= use Apollo3 MCU 32.768KHz + 0x0a,0x06,0x04,0x00,0x00,0x00,0x00, //eb 0x00000000 = auto detect and low frequency clock calibration + 0x0b,0x06,0x01,0x96, //rx_ifs 0x96 = 150us + 0x23,0x06,0x01,0x95, //tx_ifs 0x95 = 149us + 0x0d,0x06,0x02,0xe8,0x03, //duration allowed for XO32M stabilization from external wakeup signal + 0x0e,0x06,0x02,0xe8,0x03, //duration allowed for XO32M stabilization from internal wakeup signal + 0x0f,0x06,0x02,0x2c,0x01, //duration allowed for radio to leave low power mode + 0x10,0x06,0x04,0x00,0xc2,0x01,0x00, //set UART_BAUDRATE + 0x11,0x06,0x01,0x01, //sleep algorithm enabled + 0x12,0x06,0x01,0x01, //external wake-up support + 0x13,0x06,0x02,0xf4,0x01, //duration of sleep and wake-up algorithm + 0x14,0x06,0x02,0x60,0x00, //BLE Company ID + 0x15,0x06,0x01,0x08, //BLE major version + 0x16,0x06,0x01,0x03, //BLE minor version + 0x17,0x06,0x01,0x29, //BLE SW version build + 0x18,0x06,0x02,0xdc,0x05, //advertising interval (undirect) + 0x19,0x06,0x02,0xe2,0x04, //advertising interval (direct) + 0x20,0x06,0x01,0x01, //agc switch + 0x21,0x06,0x01,0x02, //EA programming latency + 0x22,0x06,0x01,0x00, //EA asap latency + 0x24,0x06,0x04,0x42,0x02,0x60,0x09, //radio TRX timing + 0x25,0x06,0x01,0x11, //modem polarity setting + 0x26,0x06,0x01,0x00, //modem sync setting + 0x27,0x06,0x01,0x02, //BLE reset delay + 0x2d,0x06,0x01,0x00, //2 byte mode switch, 01 to enable + 0x28,0x06,0x02,0xf6,0x3f, //initial agc gain setting + 0x29,0x06,0x01,0x0f, //initial Tx output power, 0x0f is +4dBm + 0x35,0x06,0x01,0x08, //maximum Tx ouput power setting + 0x37,0x06,0x01,0x00, //RC32K calibration control, 0xAA to enable + 0x05,0x06,0x02,0x34,0x00, //no use + 0x04,0x06,0x01,0x20, //internal dvdd voltage level control if using 0.9V from MCU side + 0x00,0x00,0x00,0x00 //dummy + } +}; + +am_hal_ble_patch_t am_ble_nvds_patch = +{ + .ui32Type = 0xDD, + .ui32Length = 0x00be, + .ui32CRC = 0x7e77, + .pui32Data = am_ble_buffer_nvds_data.words, +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.h new file mode 100644 index 0000000..f961626 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.h @@ -0,0 +1,106 @@ +//***************************************************************************** +// +//! @file am_hal_ble_patch.h +//! +//! @brief This is a binary patch for the BLE core. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_BLE_PATCH_H +#define AM_HAL_BLE_PATCH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Patch array pointer. +// +//***************************************************************************** +extern am_hal_ble_patch_t **am_hal_ble_default_patches; +extern am_hal_ble_patch_t **am_hal_ble_default_copy_patches; +extern const uint32_t am_hal_ble_num_default_patches; + +//***************************************************************************** +// +// Pointers for specific patches. +// +//***************************************************************************** +extern am_hal_ble_patch_t am_ble_performance_patch; +extern am_hal_ble_patch_t am_ble_nvds_patch; + +//***************************************************************************** +// +// Default patch structure. +// +//***************************************************************************** +extern am_hal_ble_patch_t g_AMBLEDefaultPatch; + +//***************************************************************************** +// +// Macros for accessing specific NVDS parameters. +// +//***************************************************************************** +#define AM_HAL_BLE_NVDS_CLOCKDRIFT_OFFSET 30 +#define AM_HAL_BLE_NVDS_SLEEPCLOCKDRIFT_OFFSET 35 +#define AM_HAL_BLE_NVDS_CLOCKSOURCE_OFFSET 44 +#define AM_HAL_BLE_NVDS_SLEEPENABLE_OFFSET 85 +#define AM_HAL_BLE_NVDS_AGC_OFFSET 125 + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_BLE_PATCH_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.c new file mode 100644 index 0000000..800bf7b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.c @@ -0,0 +1,390 @@ +//***************************************************************************** +// +//! @file am_hal_ble_patch_b0.c +//! +//! @brief This is a binary patch for the BLE core. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +// BLE LL local supported feature flags. +// +// Bit position | Link Layer Feature +// 0 | LE Encryption +// 1 | Connection Parameters Request Procedure +// 2 | Extended Reject Indication +// 3 | Slave-initiated Features Exchange +// 4 | LE Ping +// 5 | LE Data Packet Length Extension +// 6 | LL Privacy +// 7 | Extended Scanner Filter Policies +// +// Specified 4.6 Feature Support, Link Layer Specification, Core V4.2. +// +//***************************************************************************** +#ifndef AM_HAL_BLE_LOCAL_FEATURE +#define AM_HAL_BLE_LOCAL_FEATURE 0x21 +#endif + + + +//***************************************************************************** +// +// Patches included in this file. +// +//***************************************************************************** +am_hal_ble_patch_t am_ble_buffer_patch_b0; +am_hal_ble_patch_t am_ble_performance_patch_b0; +am_hal_ble_patch_t am_ble_nvds_patch_b0; + +//***************************************************************************** +// +// Patch application order. +// +//***************************************************************************** +am_hal_ble_patch_t *am_hal_ble_default_patch_array_b0[] = +{ + // FTCODE patches (type 0xAA) + + // RAMCODE patches (type 0xBB) + &am_ble_performance_patch_b0, + + // Standard patches (type 0xCC) + &am_ble_buffer_patch_b0, + + // nvds param (type 0xDD) + &am_ble_nvds_patch_b0, +}; + +#define AM_HAL_BLE_NUM_DEFAULT_PATCHES_B0 \ + (sizeof(am_hal_ble_default_patch_array_b0) / \ + sizeof(am_hal_ble_default_patch_array_b0[0])) + +am_hal_ble_patch_t **am_hal_ble_default_patches_b0 = am_hal_ble_default_patch_array_b0; +const uint32_t am_hal_ble_num_default_patches_b0 = AM_HAL_BLE_NUM_DEFAULT_PATCHES_B0; + +//***************************************************************************** +// +// Patch Name: RAMCODE PATCH v0.4 for Apollo3 B0 + +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Optimized AGC Table +// Fixed Channelmap indication rejected issue +// Fixed 800M Spur +// Fixed feature issue +// Fixed disconnect issue //long time large data transfer +// Date: 2019-10-25 +//***************************************************************************** + + am_hal_ble_buffer(0x0654)am_ble_performance_patch_data_b0 = +{ + .bytes = + { + 0x00,0x11,0x50,0x06,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x01,0xc5,0x01, + 0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x81,0x06,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x1f,0xb5,0x00,0x24,0x00,0x98,0x22,0x28,0x2d,0xd2,0x01,0x00, + 0x79,0x44,0x09,0x79,0x49,0x18,0x8f,0x44,0x10,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, + 0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x15,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x18, + 0x2a,0x1b,0x1e,0x2a,0x2a,0x28,0x28,0x28,0x28,0x24,0x01,0x98,0xc0,0xb2,0x00,0xf0, + 0x95,0xf8,0x14,0xe0,0x00,0xf0,0x16,0xf8,0x11,0xe0,0x00,0xf0,0xd1,0xf9,0x0e,0xe0, + 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+//***************************************************************************** + + + +//***************************************************************************** +// +// Patch Name: Function PATCH v0.4 for Apollo3 B0 +// +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Optimized AGC Table +// Fixed Channelmap indication rejected issue +// Fixed 800M Spur +// Fixed feature issue +// Fixed disconnect issue //long time large data transfer +// Date: 2019-10-25 +//***************************************************************************** + +const am_hal_ble_buffer(0x0230)am_ble_buffer_patch_data_b0 = +{ + .bytes = + { + 0x00,0x22,0x30,0x02,0x1f,0x00,0x00,0x00,0x84,0x65,0x06,0x00,0x73,0x6d,0x06,0x00, + 0x75,0x75,0x06,0x00,0x17,0x7b,0x06,0x00,0xa9,0x85,0x06,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x20,0xec,0xf7, + 0xf9,0xfc,0x00,0x28,0x0a,0xd0,0x00,0x20,0x00,0x90,0x03,0x46,0x02,0x46,0x01,0x46, + 0x24,0x68,0x21,0x20,0x35,0x34,0xa0,0x47,0x00,0xbf,0x38,0xbd,0xef,0xf7,0xfb,0xfe, + 0x0f,0x49,0x00,0x28,0x02,0xd0,0x08,0x78,0x01,0x28,0x12,0xd0,0x08,0x78,0x02,0x28, + 0x0f,0xd0,0x00,0x28,0x06,0xd0,0x01,0x28,0x04,0xd0,0x00,0xf0,0x0c,0x6e,0x00,0x20, + 0x00,0x00,0x00,0x04,0x1c,0x6e,0x00,0x20,0x00,0x49,0x08,0x47,0x41,0x34,0x00,0x20, + 0x23,0x4e,0xca,0x7c,0x75,0x68,0xc9,0x6a,0x00,0x2a,0x1d,0xd0,0x7d,0x22,0x12,0x02, + 0x91,0x42,0x02,0xd3,0x8a,0x1a,0x01,0x20,0x00,0xe0,0x52,0x1a,0x00,0x28,0x05,0xd0, + 0x20,0x46,0x50,0x43,0xea,0xf7,0x02,0xfa,0x20,0x1a,0x04,0xe0,0xea,0xf7,0xde,0xf9, + 0x00,0x19,0x01,0x02,0xc2,0x00,0x69,0x18,0x12,0x18,0x89,0x18,0x4a,0x0a,0x53,0x02, + 0xc9,0x1a,0x71,0x60,0x1e,0x21,0x48,0x43,0x80,0x18,0x70,0xbd,0x2c,0x68,0x00,0x20, + 0x0c,0x6e,0x00,0x20,0x00,0x49,0x08,0x47,0xb1,0x34,0x00,0x20,0xc1,0x7c,0xc0,0x6a, + 0x00,0x29,0x15,0xd0,0x7d,0x21,0x09,0x02,0x88,0x42,0x02,0xd3,0x02,0xd5,0x04,0x20, + 0x60,0x70,0x34,0xe0,0x28,0x69,0x06,0xf0,0xb5,0xf8,0x00,0x28,0x02,0xd0,0x02,0x20, + 0x60,0x70,0x2c,0xe0,0x03,0x98,0x04,0xf0,0x1f,0xfa,0x04,0x28,0x07,0xd1,0x68,0x46, + 0x01,0x79,0x02,0x20,0x88,0x43,0x05,0xd0,0x00,0x20,0x00,0x28,0x04,0xd0,0x00,0xbf, + 0x00,0x20,0x1c,0xe0,0x01,0x20,0xf8,0xe7,0xf0,0x88,0x00,0x90, + //0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + AM_HAL_BLE_LOCAL_FEATURE,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff, + 0xff,0x03,0x00,0x00,0xff,0x00,0x3c,0x1f,0x00,0x00,0x00,0x00,0x01,0x20,0x00,0x00, + 0x8d,0x84,0x00,0x00,0x02,0x20,0x00,0x00,0xcd,0x7d,0x00,0x00,0x03,0x20,0x00,0x00, + 0xd1,0x7e,0x00,0x00,0x05,0x20,0x00,0x00,0xfd,0x84,0x00,0x00,0xf0,0xb4,0x00,0x23, + 0x18,0x4c,0x25,0x69,0x18,0x49,0x7d,0x22,0x09,0x68,0x12,0x02,0x91,0x42,0x02,0xd3, + 0x8a,0x1a,0x01,0x23,0x00,0xe0,0x52,0x1a,0x06,0x46,0x56,0x43,0xf2,0x13,0x51,0x43, + 0x71,0x1a,0x1e,0x26,0x4e,0x43,0x4f,0x10,0xf6,0x19,0x8f,0x11,0xf6,0x19,0x49,0x12, + 0x71,0x18,0xce,0x13,0x00,0x2b,0x01,0xd0,0x80,0x1a,0x00,0xe0,0x10,0x18,0x42,0x19, + 0x91,0x08,0x8d,0x00,0x52,0x1b,0x00,0x2b,0x04,0xd0,0x43,0x01,0x18,0x1a,0x40,0x18, + 0x80,0x1b,0x03,0xe0,0x43,0x01,0x18,0x1a,0x40,0x18,0x80,0x19,0x22,0x61,0xf0,0xbc, + 0x70,0x47,0x00,0x00,0x00,0x6e,0x00,0x20,0x58,0x68,0x00,0x20,0x10,0xb4,0x00,0x23, + 0x14,0x21,0x02,0x46,0x4a,0x43,0x11,0x49,0x7d,0x24,0x09,0x68,0x24,0x02,0xa1,0x42, + 0x02,0xd9,0x09,0x1b,0x01,0x23,0x00,0xe0,0x61,0x1a,0x48,0x43,0x81,0x00,0x41,0x18, + 0x88,0x0a,0x0c,0x0c,0x00,0x19,0x4c,0x0c,0x00,0x19,0x4c,0x0d,0x00,0x19,0x4c,0x0e, + 0x00,0x19,0xc9,0x0f,0x40,0x18,0xc0,0x08,0x00,0x2b,0x01,0xd0,0x10,0x18,0x01,0xe0, + 0x10,0x1a,0x40,0x1e,0x40,0x1e,0x10,0xbc,0x70,0x47,0x00,0x00,0x58,0x68,0x00,0x20 + } +}; + +am_hal_ble_patch_t am_ble_buffer_patch_b0 = +{ + .ui32Type = 0xCC, + .ui32Length = 0x0230, + .ui32CRC = 0x320c, + .pui32Data = am_ble_buffer_patch_data_b0.words, +}; + + +//***************************************************************************** +// +// Patch Name: Function PATCH v0.4 for Apollo3 B0 +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Optimized AGC Table +// Fixed Channelmap indication rejected issue +// Fixed 800M Spur +// Fixed feature issue +// Date: 2019-05-15 +//***************************************************************************** + + +am_hal_ble_buffer(0x00c2) am_ble_buffer_nvds_data_b0 = +{ + .bytes = + { + 0x4e,0x56,0x44,0x53, //NVDS_MAGIC_NUMBER + 0x01,0x06,0x06,0xef,0xbb,0x23,0x88,0x77,0x66, //bluetooth address + 0x02,0x06,0x0a,0x4e,0x5a,0x38,0x38,0x30,0x31,0x56,0x31,0x41,0x00, //device name + 0x03,0x06,0x01,0x00, //system clock frequency, 00=32MHz 01=24MHz others=16MHz + 0x07,0x06,0x02,0x00,0x00, //32K clock drift, 0x01f4 = 500 ppm + 0x0c,0x06,0x02,50,0x00, //sleep clock accuracy in ppm, 0x01f4 = 500 ppm + 0x08,0x06,0x01,0x00, //01 for BQB qualification, 00 for normal usage + 0x09,0x06,0x01,0x02, //clock source selection, 00 = internal RC32KHz, 02= use Apollo3 MCU 32.768KHz + 0x0a,0x06,0x04,0x00,0x00,0x00,0x00, //0x00000000 = auto detect and low frequency clock calibration + 0x0b,0x06,0x01,0x96, //rx_ifs 0x96 = 150us + 0x23,0x06,0x01,0x95, //tx_ifs 0x95 = 149us + 0x0d,0x06,0x02,0xe8,0x3, //duration allowed for XO32M stabilization from external wakeup + 0x0e,0x06,0x02,0xe8,0x3, //duration allowed for XO32M stabilization from internal wakeup signal + 0x0f,0x06,0x02,0x2c,0x01, //duration allowed for radio to leave low power mode + 0x10,0x06,0x04,0x00,0xc2,0x01,0x00, //set UART_BAUDRATE + 0x11,0x06,0x01,0x01, //sleep algorithm enabled + // 0x11,0x06,0x01,0x00, //sleep algorithm disabled + 0x12,0x06,0x01,0x01, //external wake-up support + 0x13,0x06,0x02,0xf4,0x01, //duration of sleep and wake-up algorithm + 0x14,0x06,0x02,0x60,0x00, //BLE Company ID + 0x15,0x06,0x01,0x08, //BLE major version + 0x16,0x06,0x01,0x03, //BLE minor version + 0x17,0x06,0x01,0x29, //BLE SW version build + 0x18,0x06,0x02,0xdc,0x05, //advertising interval (undirect) + 0x19,0x06,0x02,0xe2,0x04, //advertising interval (direct) + 0x20,0x06,0x01,0x01, //agc switch on + 0x21,0x06,0x01,0x02, //EA programming latency,set '2' with master mode + 0x22,0x06,0x01,0x00, //EA asap latency + 0x24,0x06,0x04,0x5C,0x09,0x6A,0x09, //radio TRX timing + 0x25,0x06,0x01,0x11, //modem polarity setting + 0x26,0x06,0x01,0x00, //modem sync setting + 0x27,0x06,0x01,0x02, //BLE reset delay + 0x2d,0x06,0x01,0x00, //2 byte mode switch, 01 to enable + 0x28,0x06,0x02,0xf6,0x2d, //initial agc gain setting + 0x29,0x06,0x01,0x0f, //initial Tx output power, 0x0f is +4dBm + 0x35,0x06,0x01,0x08, //maximum Tx ouput power setting + 0x37,0x06,0x01,0x00, //RC32K calibration control, 0xAA to enable + 0x05,0x06,0x02,0x34,0x00, //no use + 0x04,0x06,0x01,0x20, //internal dvdd voltage level control if using 0.9V from MCU side + 0x2e,0x06,0x01,0x00, //instant indication,set "0" to disbale instant reject + 0x00,0x00,0x00,0x00 //dummy + } +}; + +am_hal_ble_patch_t am_ble_nvds_patch_b0 = +{ + .ui32Type = 0xDD, + .ui32Length = 0x00c2, + .ui32CRC = 0x112b, + .pui32Data = am_ble_buffer_nvds_data_b0.words, +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.h new file mode 100644 index 0000000..2e44466 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.h @@ -0,0 +1,106 @@ +//***************************************************************************** +// +//! @file am_hal_ble_patch_b0.h +//! +//! @brief This is a binary patch for the BLE core. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_BLE_PATCH_B0_H +#define AM_HAL_BLE_PATCH_B0_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Patch array pointer. +// +//***************************************************************************** +extern am_hal_ble_patch_t **am_hal_ble_default_patches_b0; +extern am_hal_ble_patch_t **am_hal_ble_default_copy_patches_b0; +extern const uint32_t am_hal_ble_num_default_patches_b0; + +//***************************************************************************** +// +// Pointers for specific patches. +// +//***************************************************************************** +extern am_hal_ble_patch_t am_ble_performance_patch_b0; +extern am_hal_ble_patch_t am_ble_nvds_patch_b0; + +//***************************************************************************** +// +// Default patch structure. +// +//***************************************************************************** +extern am_hal_ble_patch_t g_AMBLEDefaultPatchB0; + +//***************************************************************************** +// +// Macros for accessing specific NVDS parameters. +// +//***************************************************************************** +#define AM_HAL_BLE_NVDS_CLOCKDRIFT_OFFSET 30 +#define AM_HAL_BLE_NVDS_SLEEPCLOCKDRIFT_OFFSET 35 +#define AM_HAL_BLE_NVDS_CLOCKSOURCE_OFFSET 44 +#define AM_HAL_BLE_NVDS_SLEEPENABLE_OFFSET 85 +#define AM_HAL_BLE_NVDS_AGC_OFFSET 125 + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_BLE_PATCH_B0_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.c new file mode 100644 index 0000000..66e68fb --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.c @@ -0,0 +1,282 @@ +//***************************************************************************** +// +// am_hal_burst.c +//! @file +//! +//! @brief Functions for controlling Burst Mode operation. +//! +//! @addtogroup burstmode3 +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +// +// Globals. +// +bool g_am_hal_burst_mode_available = false; + +// **************************************************************************** +// +// am_hal_burst_mode_initialize() +// Burst mode initialization function +// +// **************************************************************************** +uint32_t +am_hal_burst_mode_initialize(am_hal_burst_avail_e *peBurstAvail) +{ + uint32_t ui32Status; + // + // Check if the Burst Mode feature is available based on the SKU. + // + if ( 0 == MCUCTRL->SKU_b.ALLOWBURST ) + { + // + // Burst mode is not available. + // + g_am_hal_burst_mode_available = false; + *peBurstAvail = AM_HAL_BURST_NOTAVAIL; + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable the Burst Feature Event (DEVPWREVENTEN). + // + PWRCTRL->DEVPWREVENTEN_b.BURSTEVEN = 1; + + // + // BLE buck is shared by Burst as well + // Enable the BLE buck trim values if in use + // + if (PWRCTRL->SUPPLYSRC_b.BLEBUCKEN) + { + am_hal_pwrctrl_blebuck_trim(); + } + + // + // Enable the Burst Functionality (FEATUREENABLE). + // + MCUCTRL->FEATUREENABLE_b.BURSTREQ = 1; + + ui32Status = am_hal_flash_delay_status_check(10000, + (uint32_t)&MCUCTRL->FEATUREENABLE, + MCUCTRL_FEATUREENABLE_BURSTACK_Msk, + MCUCTRL_FEATUREENABLE_BURSTACK_Msk, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + g_am_hal_burst_mode_available = false; + *peBurstAvail = AM_HAL_BURST_NOTAVAIL; + return ui32Status; + } + + if ( 0 == MCUCTRL->FEATUREENABLE_b.BURSTAVAIL ) + { + // + // Burst mode is not available. + // + g_am_hal_burst_mode_available = false; + *peBurstAvail = AM_HAL_BURST_NOTAVAIL; + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Check the ACK for the Burst Functionality. + // + if ( MCUCTRL->FEATUREENABLE_b.BURSTACK == 0 ) + { + // + // If NACK, return status. + // + g_am_hal_burst_mode_available = false; + *peBurstAvail = AM_HAL_BURST_NOTAVAIL; + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Return Availability + // + g_am_hal_burst_mode_available = true; + *peBurstAvail = AM_HAL_BURST_AVAIL; + return AM_HAL_STATUS_SUCCESS; +} + +// **************************************************************************** +// +// am_hal_burst_mode_enable() +// Burst mode enable function +// +// **************************************************************************** +uint32_t +am_hal_burst_mode_enable(am_hal_burst_mode_e *peBurstStatus) +{ + uint32_t ui32Status; + + // + // Check if Burst Mode is allowed and return status if it is not. + // + if (!g_am_hal_burst_mode_available) + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Request Burst Mode Enable (FREQCTRL) + // + CLKGEN->FREQCTRL_b.BURSTREQ = CLKGEN_FREQCTRL_BURSTREQ_EN; + +// while (0 == AM_BFR(CLKGEN, FREQCTRL, BURSTACK)); + ui32Status = am_hal_flash_delay_status_check(10000, + (uint32_t)&CLKGEN->FREQCTRL, + CLKGEN_FREQCTRL_BURSTSTATUS_Msk, + CLKGEN_FREQCTRL_BURSTSTATUS_Msk, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + return ui32Status; + } + + // + // Check that the Burst Request was ACK'd. + // + if ( 0 == CLKGEN->FREQCTRL_b.BURSTACK ) + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + return AM_HAL_STATUS_FAIL; + } + + // + // Check the Burst Mode Status (FREQCTRL) + // + if ( CLKGEN->FREQCTRL_b.BURSTSTATUS > 0) + { + *peBurstStatus = AM_HAL_BURST_MODE; + } + else + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + } + + return AM_HAL_STATUS_SUCCESS; +} + +// **************************************************************************** +// +// am_hal_burst_mode_disable() +// Burst mode disable function +// +// **************************************************************************** +uint32_t +am_hal_burst_mode_disable(am_hal_burst_mode_e *peBurstStatus) +{ + uint32_t ui32Status; + + // + // Request Burst Mode Enable (FREQCTRL) + // + // + // Safely disable burst mode. + // + AM_CRITICAL_BEGIN + am_hal_flash_store_ui32((uint32_t*)&CLKGEN->FREQCTRL, CLKGEN_FREQCTRL_BURSTREQ_DIS); + AM_CRITICAL_END + + // + // Disable the Burst Feature Event (DEVPWREVENTEN). + // + PWRCTRL->DEVPWREVENTEN_b.BURSTEVEN = 0; + + ui32Status = am_hal_flash_delay_status_check(10000, + (uint32_t)&CLKGEN->FREQCTRL, + CLKGEN_FREQCTRL_BURSTSTATUS_Msk, + 0, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + return ui32Status; + } + + // + // Check the Burst Mode Status (FREQCTRL) + // + // + // Check the Burst Mode Status (FREQCTRL) + // + if ( CLKGEN->FREQCTRL_b.BURSTSTATUS > 0 ) + { + *peBurstStatus = AM_HAL_BURST_MODE; + } + else + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + } + + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// am_hal_burst_mode_status() - Return current burst mode state. +// +// Implemented as a macro, this function returns the current burst mode state. +// AM_HAL_BURST_MODE +// AM_HAL_NORMAL_MODE +// +//***************************************************************************** + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.h new file mode 100644 index 0000000..e95c670 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.h @@ -0,0 +1,149 @@ +//***************************************************************************** +// +// am_hal_burst.h +//! @file +//! +//! @brief Functions for controlling Burst Mode operation. +//! +//! @addtogroup burstmode3 +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_BURST_H +#define AM_HAL_BURST_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +// Burst Mode Status enums +// +//***************************************************************************** +// +// Avail - the result of a feature availability interrogation. +// +typedef enum +{ + AM_HAL_BURST_AVAIL, + AM_HAL_BURST_NOTAVAIL +} am_hal_burst_avail_e; + +// +// Mode - the result of a change request. +// +typedef enum +{ + AM_HAL_BURST_MODE, + AM_HAL_NORMAL_MODE, +} am_hal_burst_mode_e; + +//***************************************************************************** +// +//! @brief Burst mode initialization function +//! +//! @param peBurstAvail - Availibility of feature +//! +//! This function initializes the Apollo3 MCU for Burst Mode operation. It does +//! not set the MCU into Burst Mode. This should be called once at system +//! initialization if Burst Mode is going to be used in the system. +//! +//! @return status of API call. +// +//***************************************************************************** +extern uint32_t am_hal_burst_mode_initialize(am_hal_burst_avail_e *peBurstAvail); + +//***************************************************************************** +// +//! @brief Burst mode enable function +//! +//! @param peBurstStatus - resulting mode after call. +//! +//! This function enables the Apollo3 MCU into Burst Mode operation. +//! +//! @return status of API call. +// +//***************************************************************************** +extern uint32_t am_hal_burst_mode_enable(am_hal_burst_mode_e *peBurstStatus); + +//***************************************************************************** +// +//! @brief Burst mode disable function +//! +//! @param peBurstStatus - resulting mode after call. +//! +//! This function disables the Apollo3 MCU from Burst Mode operation. It returns +//! the MCU to Normal Mode. +//! +//! @return status of API call. +// +//***************************************************************************** +extern uint32_t am_hal_burst_mode_disable(am_hal_burst_mode_e *peBurstStatus); + +//***************************************************************************** +// +//! @brief Return current burst mode state +//! +//! Implemented as a macro, this function returns the current burst mode state. +//! AM_HAL_BURST_MODE +//! AM_HAL_NORMAL_MODE +// +//***************************************************************************** +#define am_hal_burst_mode_status() \ + (CLKGEN->FREQCTRL_b.BURSTSTATUS ? AM_HAL_BURST_MODE : AM_HAL_NORMAL_MODE) + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_BURST_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.c new file mode 100644 index 0000000..1006de2 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.c @@ -0,0 +1,460 @@ +//***************************************************************************** +// +// am_hal_cachectrl.c +//! @file +//! +//! @brief Functions for interfacing with the CACHE controller. +//! +//! @addtogroup cachectrl3 Cache Control (CACHE) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Default settings for the cache. +// +//***************************************************************************** +const am_hal_cachectrl_config_t am_hal_cachectrl_defaults = +{ + .bLRU = 0, + .eDescript = AM_HAL_CACHECTRL_DESCR_1WAY_128B_1024E, + .eMode = AM_HAL_CACHECTRL_CONFIG_MODE_INSTR_DATA, +}; + +//***************************************************************************** +// +// Configure the cache with given and recommended settings, but do not enable. +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_config(const am_hal_cachectrl_config_t *psConfig) +{ + // + // In the case where cache is currently enabled, we need to gracefully + // bow out of that configuration before reconfiguring. The best way to + // accomplish that is to shut down the ID bits, leaving the cache enabled. + // Once the instr and data caches have been disabled, we can safely set + // any new configuration, including disabling the controller. + // + AM_CRITICAL_BEGIN + CACHECTRL->CACHECFG &= + ~(CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk | + CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk); + AM_CRITICAL_END + + CACHECTRL->CACHECFG = + _VAL2FLD(CACHECTRL_CACHECFG_ENABLE, 0) | + _VAL2FLD(CACHECTRL_CACHECFG_CACHE_CLKGATE, 1) | + _VAL2FLD(CACHECTRL_CACHECFG_CACHE_LS, 0) | + _VAL2FLD(CACHECTRL_CACHECFG_DATA_CLKGATE, 1) | + _VAL2FLD(CACHECTRL_CACHECFG_ENABLE_MONITOR, 0) | + _VAL2FLD(CACHECTRL_CACHECFG_LRU, psConfig->bLRU) | + _VAL2FLD(CACHECTRL_CACHECFG_CONFIG, psConfig->eDescript) | + ((psConfig->eMode << CACHECTRL_CACHECFG_ICACHE_ENABLE_Pos) & + (CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk | + CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk)); + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_cachectrl_config() + +//***************************************************************************** +// +// Enable the cache. +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_enable(void) +{ + // + // Enable the cache + // + CACHECTRL->CACHECFG |= _VAL2FLD(CACHECTRL_CACHECFG_ENABLE, 1); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_cachectrl_enable() + +//***************************************************************************** +// +// Disable the cache. +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_disable(void) +{ + // + // Shut down as gracefully as possible. + // Disable the I/D cache enable bits first to allow a little time + // for any in-flight transactions to hand off to the line buffer. + // Then clear the enable. + // + AM_CRITICAL_BEGIN + CACHECTRL->CACHECFG &= ~(_VAL2FLD(CACHECTRL_CACHECFG_ICACHE_ENABLE, 1) | + _VAL2FLD(CACHECTRL_CACHECFG_DCACHE_ENABLE, 1)); + CACHECTRL->CACHECFG &= ~_VAL2FLD(CACHECTRL_CACHECFG_ENABLE, 1); + AM_CRITICAL_END + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_cachectrl_disable() + +//***************************************************************************** +// +// Control helper functions. +// +//***************************************************************************** +static bool +set_LPMMODE(uint32_t ui32value) +{ + uint32_t ui32Val; + uint32_t *pui32RegAddr; + + if ( ui32value > (CACHECTRL_FLASHCFG_LPMMODE_Msk >> CACHECTRL_FLASHCFG_LPMMODE_Pos) ) + { + return false; + } + + // + // Compute register address (assumes each reg is 1 word offset). + // + pui32RegAddr = (uint32_t*)&CACHECTRL->FLASHCFG; + + AM_CRITICAL_BEGIN + ui32Val = am_hal_flash_load_ui32(pui32RegAddr); + ui32Val &= ~(CACHECTRL_FLASHCFG_LPMMODE_Msk | + CACHECTRL_FLASHCFG_LPM_RD_WAIT_Msk); + ui32Val |= _VAL2FLD(CACHECTRL_FLASHCFG_LPMMODE, ui32value) | + _VAL2FLD(CACHECTRL_FLASHCFG_LPM_RD_WAIT, 0x7); + am_hal_flash_store_ui32(pui32RegAddr, ui32Val); + AM_CRITICAL_END + + return true; +} // set_LPMMODE() + +static bool +set_SEDELAY(uint32_t ui32value) +{ + uint32_t ui32Val; + uint32_t *pui32RegAddr; + + if ( ui32value > (CACHECTRL_FLASHCFG_SEDELAY_Msk >> CACHECTRL_FLASHCFG_SEDELAY_Pos) ) + { + return false; + } + + // + // Compute register address (assumes each reg is 1 word offset). + // + pui32RegAddr = (uint32_t*)&CACHECTRL->FLASHCFG; + + AM_CRITICAL_BEGIN + ui32Val = am_hal_flash_load_ui32(pui32RegAddr); + ui32Val &= ~(CACHECTRL_FLASHCFG_SEDELAY_Msk | + CACHECTRL_FLASHCFG_LPM_RD_WAIT_Msk); + ui32Val |= _VAL2FLD(CACHECTRL_FLASHCFG_SEDELAY, ui32value) | + _VAL2FLD(CACHECTRL_FLASHCFG_LPM_RD_WAIT, 0x7); + am_hal_flash_store_ui32(pui32RegAddr, ui32Val); + AM_CRITICAL_END + + return true; +} // set_SEDELAY() + +static bool +set_RDWAIT(uint32_t ui32value) +{ + uint32_t ui32Val; + uint32_t *pui32RegAddr; + + if ( ui32value > (CACHECTRL_FLASHCFG_RD_WAIT_Msk >> CACHECTRL_FLASHCFG_RD_WAIT_Pos) ) + { + return false; + } + + // + // Compute register address (assumes each reg is 1 word offset). + // + pui32RegAddr = (uint32_t*)&CACHECTRL->FLASHCFG; + + AM_CRITICAL_BEGIN + ui32Val = am_hal_flash_load_ui32(pui32RegAddr); + ui32Val &= ~(CACHECTRL_FLASHCFG_RD_WAIT_Msk | + CACHECTRL_FLASHCFG_LPM_RD_WAIT_Msk); + ui32Val |= _VAL2FLD(CACHECTRL_FLASHCFG_RD_WAIT, ui32value) | + _VAL2FLD(CACHECTRL_FLASHCFG_LPM_RD_WAIT, 0x7); + am_hal_flash_store_ui32(pui32RegAddr, ui32Val); + AM_CRITICAL_END + + return true; +} // set_RDWAIT() + +//***************************************************************************** +// +// Select the cache configuration type. +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_control(am_hal_cachectrl_control_e eControl, void *pArgs) +{ + uint32_t ui32Arg; + uint32_t ui32SetMask = 0; + + switch ( eControl ) + { + case AM_HAL_CACHECTRL_CONTROL_FLASH_CACHE_INVALIDATE: + ui32SetMask = CACHECTRL_CTRL_INVALIDATE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_STATISTICS_RESET: + if ( !_FLD2VAL(CACHECTRL_CACHECFG_ENABLE_MONITOR, CACHECTRL->CACHECFG) ) + { + // + // The monitor must be enabled for the reset to have any affect. + // + return AM_HAL_STATUS_INVALID_OPERATION; + } + else + { + ui32SetMask = CACHECTRL_CTRL_RESET_STAT_Msk; + } + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_ENABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk | + CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_DISABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk | + CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_ENABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_DISABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_ENABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_DISABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_MONITOR_ENABLE: + ui32SetMask = 0; + AM_CRITICAL_BEGIN + CACHECTRL->CACHECFG |= CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk; + AM_CRITICAL_END + break; + case AM_HAL_CACHECTRL_CONTROL_MONITOR_DISABLE: + ui32SetMask = 0; + AM_CRITICAL_BEGIN + CACHECTRL->CACHECFG &= ~CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk; + AM_CRITICAL_END + break; + case AM_HAL_CACHECTRL_CONTROL_LPMMODE_RESET: + // + // Safely set the reset values for LPMMODE, SEDELAY, and RDWAIT. + // + if ( !set_LPMMODE(AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_NEVER) || + !set_SEDELAY(0x7) || + !set_RDWAIT(0x3) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_LPMMODE_RECOMMENDED: + // + // Safely set the as recommended values (from the datasheet) + // for LPMMODE, SEDELAY, and RDWAIT. + // + if ( !set_LPMMODE(AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_STANDBY) || + !set_SEDELAY(0x5) || + !set_RDWAIT(0x1) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_LPMMODE_AGGRESSIVE: + // + // Safely set aggressive values for LPMMODE, SEDELAY, and RDWAIT. + // (For now select recommended values.) + // + if ( !set_LPMMODE(AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_STANDBY) || + !set_SEDELAY(0x6) || + !set_RDWAIT(0x1) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_LPMMODE_SET: + // + // Safely set LPMMODE, SEDELAY, or RDWAIT. + // The new value is passed by reference via pArgs. That is, pArgs is + // assumed to be a pointer to a uint32_t of the new value. + // + if ( !pArgs ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + ui32Arg = *(uint32_t*)pArgs; + if ( !set_LPMMODE(ui32Arg) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_SEDELAY_SET: + if ( !pArgs ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + ui32Arg = *(uint32_t*)pArgs; + if ( !set_SEDELAY(ui32Arg) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_RDWAIT_SET: + if ( !pArgs ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + ui32Arg = *(uint32_t*)pArgs; + if ( !set_RDWAIT(ui32Arg) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_NC_CFG: + { + if ( pArgs == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + am_hal_cachectrl_nc_cfg_t *pNcCfg; + pNcCfg = (am_hal_cachectrl_nc_cfg_t *)pArgs; +#ifndef AM_HAL_DISABLE_API_VALIDATION + // Make sure the addresses are valid + if ((pNcCfg->ui32StartAddr & ~CACHECTRL_NCR0START_ADDR_Msk) || + (pNcCfg->ui32EndAddr & ~CACHECTRL_NCR0START_ADDR_Msk)) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + if (pNcCfg->eNCRegion == AM_HAL_CACHECTRL_NCR0) + { + CACHECTRL->NCR0START = pNcCfg->ui32StartAddr; + CACHECTRL->NCR0END = pNcCfg->ui32EndAddr; + CACHECTRL->CACHECFG_b.ENABLE_NC0 = pNcCfg->bEnable; + } + else if (pNcCfg->eNCRegion == AM_HAL_CACHECTRL_NCR1) + { + CACHECTRL->NCR1START = pNcCfg->ui32StartAddr; + CACHECTRL->NCR1END = pNcCfg->ui32EndAddr; + CACHECTRL->CACHECFG_b.ENABLE_NC1 = pNcCfg->bEnable; + } +#ifndef AM_HAL_DISABLE_API_VALIDATION + else + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + return AM_HAL_STATUS_SUCCESS; + } + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // All fields in the CACHECTRL register are write-only or read-only. + // A write to CACHECTRL acts as a mask-set. That is, only the bits + // written as '1' have an effect, any bits written as '0' are unaffected. + // + // Important note - setting of an enable and disable simultanously has + // unpredicable results. + // + if ( ui32SetMask ) + { + CACHECTRL->CTRL = ui32SetMask; + } + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_cachectrl_control() + +//***************************************************************************** +// +// Cache controller status function +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_status_get(am_hal_cachectrl_status_t *psStatus) +{ + uint32_t ui32Status; + + if ( psStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + ui32Status = CACHECTRL->CTRL; + + psStatus->bFlash0SleepMode = + _FLD2VAL(CACHECTRL_CTRL_FLASH0_SLM_STATUS, ui32Status); + psStatus->bFlash1SleepMode = + _FLD2VAL(CACHECTRL_CTRL_FLASH1_SLM_STATUS, ui32Status); + psStatus->bCacheReady = + _FLD2VAL(CACHECTRL_CTRL_CACHE_READY, ui32Status); + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_cachectrl_status_get() + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.h new file mode 100644 index 0000000..fc39115 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.h @@ -0,0 +1,289 @@ +// **************************************************************************** +// +// am_hal_cachectrl.h +//! @file +//! +//! @brief Functions for accessing and configuring the CACHE controller. +//! +//! @addtogroup cachectrl3 Cache Control (CACHE) +//! @ingroup apollo3hal +//! @{ +// +// **************************************************************************** + +// **************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +// **************************************************************************** +#ifndef AM_HAL_CACHECTRL_H +#define AM_HAL_CACHECTRL_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Designate this peripheral. +// +#define AM_APOLLO3_CACHECTRL 1 + +// +// Cachectrl status. +// +typedef struct +{ + bool bFlash0SleepMode; + bool bFlash1SleepMode; + bool bCacheReady; +} am_hal_cachectrl_status_t; + +// **************************************************************************** +// +//! @name Cache Config +//! @brief Configuration selection for the cache. +//! +//! These macros may be used in conjunction with the +//! am_hal_cachectrl_cache_config() function to select the cache type. +//! +//! @{ +// +// **************************************************************************** +// +// Cache description type, where: +// nWay = number of ways (associativity) +// 128B = 128 bits linesize +// 512E = 512 entries, 1024E = 1024 entries +// +typedef enum +{ + AM_HAL_CACHECTRL_DESCR_1WAY_128B_512E = CACHECTRL_CACHECFG_CONFIG_W1_128B_512E, + AM_HAL_CACHECTRL_DESCR_2WAY_128B_512E = CACHECTRL_CACHECFG_CONFIG_W2_128B_512E, + AM_HAL_CACHECTRL_DESCR_1WAY_128B_1024E = CACHECTRL_CACHECFG_CONFIG_W1_128B_1024E +} am_hal_cachectrl_descr_e; + +typedef enum +{ + AM_HAL_CACHECTRL_NCR0 = 0, + AM_HAL_CACHECTRL_NCR1 = 1 +} am_hal_cachectrl_nc_region_e; + +// Config struture for AM_HAL_CACHECTRL_CONTROL_NC_CFG +typedef struct +{ + am_hal_cachectrl_nc_region_e eNCRegion; + bool bEnable; + uint32_t ui32StartAddr; + uint32_t ui32EndAddr; +} am_hal_cachectrl_nc_cfg_t; + +// +// Control operations. +// +typedef enum +{ + AM_HAL_CACHECTRL_CONTROL_FLASH_CACHE_INVALIDATE = 1, + AM_HAL_CACHECTRL_CONTROL_STATISTICS_RESET, + AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_ENABLE, + AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_DISABLE, + AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_ENABLE, + AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_DISABLE, + AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_ENABLE, + AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_DISABLE, + AM_HAL_CACHECTRL_CONTROL_MONITOR_ENABLE, + AM_HAL_CACHECTRL_CONTROL_MONITOR_DISABLE, + AM_HAL_CACHECTRL_CONTROL_LPMMODE_RESET, + AM_HAL_CACHECTRL_CONTROL_LPMMODE_RECOMMENDED, + AM_HAL_CACHECTRL_CONTROL_LPMMODE_AGGRESSIVE, + AM_HAL_CACHECTRL_CONTROL_LPMMODE_SET, + AM_HAL_CACHECTRL_CONTROL_SEDELAY_SET, + AM_HAL_CACHECTRL_CONTROL_RDWAIT_SET, + // Configure up to two non-cacheable regions + AM_HAL_CACHECTRL_CONTROL_NC_CFG, +} am_hal_cachectrl_control_e; + +// +// Cache config values used for ui8Mode. +// +typedef enum +{ + // Note - this enum ordering is critical, do not modify. + AM_HAL_CACHECTRL_CONFIG_MODE_DISABLE, + AM_HAL_CACHECTRL_CONFIG_MODE_INSTR, + AM_HAL_CACHECTRL_CONFIG_MODE_DATA, + AM_HAL_CACHECTRL_CONFIG_MODE_INSTR_DATA +} am_hal_cachectrl_config_mode_e; + +// +// FLASHCFG LPMMODE. +// +typedef enum +{ + AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_NEVER = CACHECTRL_FLASHCFG_LPMMODE_NEVER, + AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_STANDBY = CACHECTRL_FLASHCFG_LPMMODE_STANDBY, + AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_ALWAYS = CACHECTRL_FLASHCFG_LPMMODE_ALWAYS +} am_hal_cachectrl_flashcfg_lppmode_e; + +// **************************************************************************** +// +// Cache configuration structure +// This structure used for am_hal_cachectrl_config(). +// +// **************************************************************************** +typedef struct +{ + // + //! Set to one of: + //! AM_HAL_CACHECTRL_DESCR_1WAY_128B_512E + //! Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active) + //! AM_HAL_CACHECTRL_DESCR_2WAY_128B_512E + //! Two way set associative, 128-bit linesize, 512 entries (8 SRAMs active) + //! AM_HAL_CACHECTRL_DESCR_1WAY_128B_1024E + //! Direct-mapped set associative, 128-bit linesize, 1024 entries (8 SRAMs active) + am_hal_cachectrl_descr_e eDescript; + + // + //! Set to one of the following: + //! AM_HAL_CACHECTRL_CONFIG_MODE_DISABLE - Disable both instr and data caching + //! AM_HAL_CACHECTRL_CONFIG_MODE_INSTR - Enable instr caching only + //! AM_HAL_CACHECTRL_CONFIG_MODE_DATA - Enable data caching only + //! AM_HAL_CACHECTRL_CONFIG_MODE_INSTR_DATA - Enable both instr and data caching + am_hal_cachectrl_config_mode_e eMode; + + // + //! Set to true to enable the LRU (least recently used) replacement policy. + //! Set to false to enable the LRR (least recently replaced) replacement policy. + //! Note - LRR minimizes writes to the TAG SRAM. + // + bool bLRU; + +} am_hal_cachectrl_config_t; + +extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults; + +// **************************************************************************** +// +// Function prototypes +// +// **************************************************************************** +// **************************************************************************** +// +//! @brief Configure the cache using the supplied settings. +//! +//! @param psConfig - pointer to a config structure containing cache settings. +//! +//! This function takes in a structure of cache settings and uses them to +//! configure the cache. This function will configures all of the settings in +//! the structure as well as recommended settings for various other cache +//! configuration parameters. +//! +//! This function does NOT enable the cache, which is handled in a separate +//! function. In fact, if the cache is enabled prior to calling this function, +//! it will return from the call disabled. +//! +//! For most applications, the default cache settings will be the most +//! efficient choice. To use the default cache settings with this function, use +//! the address of the global am_hal_cachectrl_defaults structure as the +//! psConfig argument. +//! +//! @return Status. +// +// **************************************************************************** +extern uint32_t am_hal_cachectrl_config(const am_hal_cachectrl_config_t *psConfig); + +// **************************************************************************** +// +//! @brief Enable the cache. +//! +//! Enable the cache for operation. +//! +//! @return Status. +// +// **************************************************************************** +extern uint32_t am_hal_cachectrl_enable(void); + +// **************************************************************************** +// +//! @brief Disable the cache. +//! +//! Use this function to disable cache. Other configuration settings are not +//! not required. +//! +//! @return Status. +// +// **************************************************************************** +extern uint32_t am_hal_cachectrl_disable(void); + +// **************************************************************************** +// +//! @brief Assert various specific controls on the cache. +//! +//! This function is used to apply various controls on the cache. +//! +//! @param eControl - One of the following: +//! AM_HAL_CACHECTRL_CONTROL_FLASH_CACHE_INVALIDATE +//! AM_HAL_CACHECTRL_CONTROL_STATISTICS_RESET +//! AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_ENABLE, +//! AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_DISABLE, +//! AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_ENABLE +//! AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_DISABLE +//! AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_ENABLE +//! AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_DISABLE +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_cachectrl_control(am_hal_cachectrl_control_e eControl, + void *pArgs); + +// **************************************************************************** +// +//! @brief Cache controller status function +//! +//! This function returns the current status of the cache. +//! +//! @param psStatus - ptr to a status structure to receive the current statuses. +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_cachectrl_status_get(am_hal_cachectrl_status_t *psStatus); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CACHECTRL_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.c new file mode 100644 index 0000000..6a9d530 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.c @@ -0,0 +1,410 @@ +// **************************************************************************** +// +// am_hal_clkgen.c +//! @file +//! +//! @brief Functions for interfacing with the CLKGEN. +//! +//! @addtogroup clkgen3 Clock Generator (CLKGEN) +//! @ingroup apollo3hal +//! @{ +// +// **************************************************************************** + +// **************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +// **************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + + +// **************************************************************************** +// +// am_hal_clkgen_control() +// Apply various specific commands/controls on the CLKGEN module. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_control(am_hal_clkgen_control_e eControl, void *pArgs) +{ + uint32_t ui32Regval; + + // + // Take a snapshot of the reset status, if not done already + // + if (!gAmHalResetStatus) + { + gAmHalResetStatus = RSTGEN->STAT; + } + + switch ( eControl ) + { + case AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX: + // + // Unlock the clock control register. + // Set the HFRC divisor to the required operating value. + // Lock the clock configuration registers. + // + CLKGEN->CLKKEY = CLKGEN_CLKKEY_CLKKEY_Key; + CLKGEN->CCTRL = CLKGEN_CCTRL_CORESEL_HFRC; + CLKGEN->CLKKEY = 0; + break; + + case AM_HAL_CLKGEN_CONTROL_SYSCLK_DIV2: + CLKGEN->CLKKEY = CLKGEN_CLKKEY_CLKKEY_Key; + CLKGEN->CCTRL = CLKGEN_CCTRL_CORESEL_HFRC_DIV2; + CLKGEN->CLKKEY = 0; + break; + + case AM_HAL_CLKGEN_CONTROL_LFRC_START: + CLKGEN->OCTRL_b.STOPRC = CLKGEN_OCTRL_STOPRC_EN; + break; + + case AM_HAL_CLKGEN_CONTROL_XTAL_START: + CLKGEN->OCTRL_b.STOPXT = CLKGEN_OCTRL_STOPXT_EN; + break; + + case AM_HAL_CLKGEN_CONTROL_LFRC_STOP: + CLKGEN->OCTRL_b.STOPRC = CLKGEN_OCTRL_STOPRC_STOP; + break; + + case AM_HAL_CLKGEN_CONTROL_XTAL_STOP: + // Software Workaround to guarantee proper function of HFADJ. + if (APOLLO3_B0) + { + MCUCTRL->XTALCTRL_b.XTALICOMPTRIM = 1; + } + CLKGEN->OCTRL_b.STOPXT = CLKGEN_OCTRL_STOPXT_STOP; + break; + + case AM_HAL_CLKGEN_CONTROL_RTC_SEL_LFRC: + CLKGEN->OCTRL_b.OSEL = CLKGEN_OCTRL_OSEL_RTC_LFRC; + break; + + case AM_HAL_CLKGEN_CONTROL_RTC_SEL_XTAL: + CLKGEN->OCTRL_b.OSEL = CLKGEN_OCTRL_OSEL_RTC_XT; + break; + + case AM_HAL_CLKGEN_CONTROL_HFADJ_ENABLE: + // Software Workaround to guarantee proper function of HFADJ. + if (APOLLO3_B0) + { + MCUCTRL->XTALCTRL_b.XTALICOMPTRIM = 3; + am_hal_flash_delay(FLASH_CYCLES_US(1000)); + } + if ( pArgs == 0 ) + { + ui32Regval = + _VAL2FLD(CLKGEN_HFADJ_HFADJGAIN, CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2) | /* Default value (Apollo3) */ + _VAL2FLD(CLKGEN_HFADJ_HFWARMUP, CLKGEN_HFADJ_HFWARMUP_1SEC) | /* Default value */ + _VAL2FLD(CLKGEN_HFADJ_HFXTADJ, 0x5B8) | /* Default value */ + _VAL2FLD(CLKGEN_HFADJ_HFADJCK, CLKGEN_HFADJ_HFADJCK_4SEC) | /* Default value */ + _VAL2FLD(CLKGEN_HFADJ_HFADJEN, CLKGEN_HFADJ_HFADJEN_EN); + } + else + { + ui32Regval = *(uint32_t*)pArgs; + } + + // + // Make sure the ENABLE bit is set. + // + ui32Regval |= _VAL2FLD(CLKGEN_HFADJ_HFADJEN, CLKGEN_HFADJ_HFADJEN_EN); + CLKGEN->HFADJ = ui32Regval; + break; + + case AM_HAL_CLKGEN_CONTROL_HFADJ_DISABLE: + CLKGEN->HFADJ_b.HFADJEN = 0; + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_control() + +// **************************************************************************** +// +// am_hal_clkgen_status_get() +// This function returns the current value of various CLKGEN statuses. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_status_get(am_hal_clkgen_status_t *psStatus) +{ + uint32_t ui32Status; + + if ( psStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + psStatus->ui32SysclkFreq = + CLKGEN->CCTRL_b.CORESEL ? + AM_HAL_CLKGEN_FREQ_MAX_HZ / 2 : + AM_HAL_CLKGEN_FREQ_MAX_HZ; + + ui32Status = CLKGEN->STATUS; + + psStatus->eRTCOSC = + _FLD2VAL(CLKGEN_STATUS_OMODE, ui32Status) ? + AM_HAL_CLKGEN_STATUS_RTCOSC_LFRC : + AM_HAL_CLKGEN_STATUS_RTCOSC_XTAL; + + psStatus->bXtalFailure = + _FLD2VAL(CLKGEN_STATUS_OSCF, ui32Status); + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_status_get() + +// **************************************************************************** +// +// am_hal_clkgen_clkout_enable() +// This function is used to select and enable CLKOUT. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_clkout_enable(bool bEnable, am_hal_clkgen_clkout_e eClkSelect) +{ + if ( !bEnable ) + { + CLKGEN->CLKOUT_b.CKEN = 0; + } + + // + // Do a basic validation of the eClkSelect parameter. + // Not every value in the range is valid, but at least this simple check + // provides a reasonable chance that the parameter is valid. + // + if ( eClkSelect <= (am_hal_clkgen_clkout_e)CLKGEN_CLKOUT_CKSEL_LFRCNE ) + { + // + // Are we actually changing the frequency? + // + if ( CLKGEN->CLKOUT_b.CKSEL != eClkSelect ) + { + // + // Disable before changing the clock + // + CLKGEN->CLKOUT_b.CKEN = 0; + + // + // Set the new clock select + // + CLKGEN->CLKOUT_b.CKSEL = eClkSelect; + } + + // + // Enable/disable as requested. + // + CLKGEN->CLKOUT_b.CKEN = bEnable; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_clkout_enable() + +// **************************************************************************** +// +// am_hal_clkgen_interrupt_enable() +// Enable selected CLKGEN Interrupts. +// +// **************************************************************************** +uint32_t am_hal_clkgen_interrupt_enable(am_hal_clkgen_interrupt_e ui32IntMask) +{ + if ( (ui32IntMask & + (CLKGEN_INTRPTEN_OF_Msk | + CLKGEN_INTRPTEN_ACC_Msk | + CLKGEN_INTRPTEN_ACF_Msk)) == 0 ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Set the interrupt enables according to the mask. + // + CLKGEN->INTRPTEN |= ui32IntMask; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_interrupt_enable() + +// **************************************************************************** +// +// am_hal_clkgen_interrupt_disable( +// Disable selected CLKGEN Interrupts. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_interrupt_disable(am_hal_clkgen_interrupt_e ui32IntMask) +{ + if ( (ui32IntMask & + (CLKGEN_INTRPTEN_OF_Msk | + CLKGEN_INTRPTEN_ACC_Msk | + CLKGEN_INTRPTEN_ACF_Msk)) == 0 ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Disable the interrupts. + // + CLKGEN->INTRPTEN &= ~ui32IntMask; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_interrupt_disable() + +//***************************************************************************** +// +// am_hal_clkgen_interrupt_clear() +// IOM interrupt clear +// +//***************************************************************************** +uint32_t +am_hal_clkgen_interrupt_clear(am_hal_clkgen_interrupt_e ui32IntMask) +{ + if ( (ui32IntMask & + (CLKGEN_INTRPTEN_OF_Msk | + CLKGEN_INTRPTEN_ACC_Msk | + CLKGEN_INTRPTEN_ACF_Msk)) == 0 ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Clear the requested interrupts. + // + CLKGEN->INTRPTCLR = ui32IntMask; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_interrupt_clear() + +// **************************************************************************** +// +// am_hal_clkgen_interrupt_status_get() +// Return CLKGEN interrupts. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_interrupt_status_get(bool bEnabledOnly, + uint32_t *pui32IntStatus) +{ + uint32_t ui32IntStatus; + + if ( !pui32IntStatus ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + ui32IntStatus = CLKGEN->INTRPTSTAT; + + if ( bEnabledOnly ) + { + ui32IntStatus &= CLKGEN->INTRPTEN; + } + + *pui32IntStatus = ui32IntStatus; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_interrupt_status_get) + +// **************************************************************************** +// +// This function sets the CLKGEN interrupts. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_interrupt_set(am_hal_clkgen_interrupt_e ui32IntMask) +{ + if ( (ui32IntMask & + (CLKGEN_INTRPTEN_OF_Msk | + CLKGEN_INTRPTEN_ACC_Msk | + CLKGEN_INTRPTEN_ACF_Msk)) == 0 ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Set the interrupt status. + // + CLKGEN->INTRPTSET = ui32IntMask; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_interrupt_set() + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.h new file mode 100644 index 0000000..154686d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.h @@ -0,0 +1,367 @@ +//***************************************************************************** +// +// am_hal_clkgen.h +//! @file +//! +//! @brief Functions for accessing and configuring the CLKGEN. +//! +//! @addtogroup clkgen3 Clock Generator (CLKGEN) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_CLKGEN_H +#define AM_HAL_CLKGEN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// +// Designate this peripheral. +// +#define AM_APOLLO3_CLKGEN 1 + +//***************************************************************************** +// +//! @name System Clock max frequency +//! @brief Defines the maximum clock frequency for this device. +//! +//! These macros provide a definition of the maximum clock frequency. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CLKGEN_FREQ_MAX_HZ 48000000 +#define AM_HAL_CLKGEN_FREQ_MAX_KHZ (AM_HAL_CLKGEN_FREQ_MAX_HZ / 1000) +#define AM_HAL_CLKGEN_FREQ_MAX_MHZ (AM_HAL_CLKGEN_FREQ_MAX_HZ / 1000000) +#define AM_HAL_CLKGEN_CORESEL_MAXDIV 1 +//! @} + +// +// Control operations. +// +typedef enum +{ + AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, + AM_HAL_CLKGEN_CONTROL_XTAL_START, + AM_HAL_CLKGEN_CONTROL_LFRC_START, + AM_HAL_CLKGEN_CONTROL_XTAL_STOP, + AM_HAL_CLKGEN_CONTROL_LFRC_STOP, + AM_HAL_CLKGEN_CONTROL_SYSCLK_DIV2, + AM_HAL_CLKGEN_CONTROL_RTC_SEL_XTAL, + AM_HAL_CLKGEN_CONTROL_RTC_SEL_LFRC, + AM_HAL_CLKGEN_CONTROL_HFADJ_ENABLE, + AM_HAL_CLKGEN_CONTROL_HFADJ_DISABLE, +} am_hal_clkgen_control_e; + +// +// Current RTC oscillator. +// +typedef enum +{ + AM_HAL_CLKGEN_STATUS_RTCOSC_XTAL, + AM_HAL_CLKGEN_STATUS_RTCOSC_LFRC, +} am_hal_clkgen_status_rtcosc_e; + +// +// CLKOUT +// +typedef enum +{ + AM_HAL_CLKGEN_CLKOUT_LFRC_1024 = 0x0, // LFRC + AM_HAL_CLKGEN_CLKOUT_XTAL_16384, // XTAL / 2 + AM_HAL_CLKGEN_CLKOUT_XTAL_8192, // XTAL / 4 + AM_HAL_CLKGEN_CLKOUT_XTAL_4096, // XTAL / 8 + AM_HAL_CLKGEN_CLKOUT_XTAL_2048, // XTAL / 16 + AM_HAL_CLKGEN_CLKOUT_XTAL_1024, // XTAL / 32 + AM_HAL_CLKGEN_CLKOUT_RTC_1HZ = 0x10, // RTC + AM_HAL_CLKGEN_CLKOUT_XTAL_0_015 = 0x16, // XTAL / 2097152 = 0.015625 Hz + AM_HAL_CLKGEN_CLKOUT_XTAL_32768, // XTAL + AM_HAL_CLKGEN_CLKOUT_CG_100, // ClkGen 100Hz + AM_HAL_CLKGEN_CLKOUT_LFRC_512 = 0x23, // LFRC / 2 = 512 Hz + AM_HAL_CLKGEN_CLKOUT_LFRC_32, // LFRC / 32 = 32 Hz + AM_HAL_CLKGEN_CLKOUT_LFRC_2, // LFRC / 512 = 2 Hz + AM_HAL_CLKGEN_CLKOUT_LFRC_0_03, // LFRC / 32768 = 0.03125 Hz + AM_HAL_CLKGEN_CLKOUT_XTAL_128, // XTAL / 256 = 128 Hz + AM_HAL_CLKGEN_CLKOUT_XTAL_4, // XTAL / 8192 = 4 Hz + AM_HAL_CLKGEN_CLKOUT_XTAL_0_5, // XTAL / 65536 = 0.5 Hz + // The next 5 are Uncalibrated LFRC + AM_HAL_CLKGEN_CLKOUT_ULFRC_64, // ULFRC / 16 = 64 Hz (uncal LFRC) + AM_HAL_CLKGEN_CLKOUT_ULFRC_8, // ULFRC / 128 = 8 Hz (uncal LFRC) + AM_HAL_CLKGEN_CLKOUT_ULFRC_1, // ULFRC / 1024 = 1 Hz (uncal LFRC) + AM_HAL_CLKGEN_CLKOUT_ULFRC_0_25, // ULFRC / 4096 = 0.25 Hz (uncal LFRC) + AM_HAL_CLKGEN_CLKOUT_ULFRC_0_0009, // ULFRC / 1M = 0.000976 Hz (uncal LFRC) + // + AM_HAL_CLKGEN_CLKOUT_LFRC_0_0004 = 0x31, // LFRC / 2M = 0.00048828125 Hz + // Following are Not Autoenabled ("NE") + AM_HAL_CLKGEN_CLKOUT_XTALNE_32768 = 0x35, // XTALNE / 1 = 32768 Hz + AM_HAL_CLKGEN_CLKOUT_XTALNE_2048, // XTALNE / 16 = 2048 Hz + AM_HAL_CLKGEN_CLKOUT_LFRCNE_32, // LFRCNE / 32 = 32 Hz + AM_HAL_CLKGEN_CLKOUT_LFRCNE_1024 = 0x39 // LFRCNE / 1 = 1024 Hz +} am_hal_clkgen_clkout_e; + +// +// ClkGen Interrupts +// +typedef enum +{ + AM_HAL_CLKGEN_INTERRUPT_OF = CLKGEN_INTRPTEN_OF_Msk, + AM_HAL_CLKGEN_INTERRUPT_ACC = CLKGEN_INTRPTEN_ACC_Msk, + AM_HAL_CLKGEN_INTERRUPT_ACF = CLKGEN_INTRPTEN_ACF_Msk +} am_hal_clkgen_interrupt_e; + +// +// Status structure. +// +typedef struct +{ + // + // ui32SysclkFreq + // Returns the current system clock frequency, in hertz. + // + uint32_t ui32SysclkFreq; + + // + // ui32RTCoscillator + // + // Returns the current RTC oscillator as one of: + // AM_HAL_CLKGEN_STATUS_RTCOSC_LFRC + // AM_HAL_CLKGEN_STATUS_RTCOSC_XTAL + // + uint32_t eRTCOSC; + + // + // bXtalFailure + // true = XTAL has failed (is enabled but not oscillating). Also if the + // LFRC is selected as the oscillator in OCTRL.OSEL. + // + bool bXtalFailure; +} am_hal_clkgen_status_t; + + +// **************************************************************************** +// +//! @brief Apply various specific commands/controls on the CLKGEN module. +//! +//! This function is used to apply various controls on CLKGEN. +//! +//! @note IMPORTANT! This function MUST be called very early in execution of +//! an application with the parameter AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX +//! in order to set Apollo3 to its required operating frequency. +//! +//! @param eControl - One of the following: +//! AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX +//! AM_HAL_CLKGEN_CONTROL_XTAL_START +//! AM_HAL_CLKGEN_CONTROL_LFRC_START +//! AM_HAL_CLKGEN_CONTROL_XTAL_STOP +//! AM_HAL_CLKGEN_CONTROL_LFRC_STOP +//! AM_HAL_CLKGEN_CONTROL_RTC_SEL_XTAL +//! AM_HAL_CLKGEN_CONTROL_RTC_SEL_LFRC +//! AM_HAL_CLKGEN_CONTROL_HFADJ_ENABLE +//! AM_HAL_CLKGEN_CONTROL_HFADJ_DISABLE +//! +//! @return status - generic or interface specific status. +//! +//! @note After starting the XTAL, a 2 second warm-up delay is required. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_control(am_hal_clkgen_control_e eControl, + void *pArgs); + +// **************************************************************************** +// +//! @brief Get CLKGEN status. +//! +//! This function returns the current value of various CLKGEN statuses. +//! +//! @param psStatus - ptr to a status structure to receive the current statuses. +//! +//! @return status - generic or interface specific status. +//! +//! @note After selection of the RTC Oscillator, a 2 second delay is required +//! before the new oscillator takes effect. Therefore the CLKGEN.STATUS.OMODE +//! bit will not reflect the new status until after the 2s wait period. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_status_get(am_hal_clkgen_status_t *psStatus); + +// **************************************************************************** +// +//! @brief Enable CLKOUT. +//! +//! This function is used to enable and select a CLKOUT frequency. +//! +//! @param bEnable: true to enable, false to disable. +//! @param eClkSelect - One of the following: +//! AM_HAL_CLKGEN_CLKOUT_LFRC_1024 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_16384 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_8192 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_4096 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_2048 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_1024 +//! AM_HAL_CLKGEN_CLKOUT_RTC_1HZ +//! AM_HAL_CLKGEN_CLKOUT_XTAL_0_015 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_32768 +//! AM_HAL_CLKGEN_CLKOUT_CG_100 +//! AM_HAL_CLKGEN_CLKOUT_LFRC_512 +//! AM_HAL_CLKGEN_CLKOUT_LFRC_32 +//! AM_HAL_CLKGEN_CLKOUT_LFRC_2 +//! AM_HAL_CLKGEN_CLKOUT_LFRC_0_03 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_128 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_4 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_0_5 +//! +//! The next 5 are Uncalibrated LFRC +//! AM_HAL_CLKGEN_CLKOUT_ULFRC_64 +//! AM_HAL_CLKGEN_CLKOUT_ULFRC_8 +//! AM_HAL_CLKGEN_CLKOUT_ULFRC_1 +//! AM_HAL_CLKGEN_CLKOUT_ULFRC_0_25 +//! AM_HAL_CLKGEN_CLKOUT_ULFRC_0_0009 +//! +//! AM_HAL_CLKGEN_CLKOUT_LFRC_0_0004 +//! +//! Following are Not Autoenabled ("NE") +//! AM_HAL_CLKGEN_CLKOUT_XTALNE_32768 +//! AM_HAL_CLKGEN_CLKOUT_XTALNE_2048 +//! AM_HAL_CLKGEN_CLKOUT_LFRCNE_32 +//! AM_HAL_CLKGEN_CLKOUT_LFRCNE_1024 +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_clkout_enable(bool bEnable, + am_hal_clkgen_clkout_e eClkSelect); + +// **************************************************************************** +// +//! @brief Enable selected CLKGEN Interrupts. +//! +//! Use this function to enable the interrupts. +//! +//! @param ui32IntMask - One or more of the following bitmasks. +//! AM_HAL_CLKGEN_INTERRUPT_OF +//! AM_HAL_CLKGEN_INTERRUPT_ACC +//! AM_HAL_CLKGEN_INTERRUPT_ACF +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_interrupt_enable(am_hal_clkgen_interrupt_e ui32IntMask); + +// **************************************************************************** +// +//! @brief Disable selected CLKGEN Interrupts. +//! +//! Use this function to disable the CLKGEN interrupts. +//! +//! @param ui32IntMask - One or more of the following bitmasks. +//! AM_HAL_CLKGEN_INTERRUPT_OF +//! AM_HAL_CLKGEN_INTERRUPT_ACC +//! AM_HAL_CLKGEN_INTERRUPT_ACF +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_interrupt_disable(am_hal_clkgen_interrupt_e ui32IntMask); + +//***************************************************************************** +// +//! @brief IOM interrupt clear +//! +//! @param ui32IntMask - interface specific interrupt mask. +//! +//! This function clears the interrupts for the given peripheral. +//! +//! The following are valid clear bits, any of which can be ORed together. +//! AM_HAL_CLKGEN_INTERRUPT_OF +//! AM_HAL_CLKGEN_INTERRUPT_ACC +//! AM_HAL_CLKGEN_INTERRUPT_ACF +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_clkgen_interrupt_clear(am_hal_clkgen_interrupt_e ui32IntMask); + +// **************************************************************************** +// +//! @brief Return CLKGEN interrupts. +//! +//! Use this function to get all CLKGEN interrupts, or only the interrupts +//! that are enabled. +//! +//! @return All or only enabled CLKGEN interrupts. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_interrupt_status_get(bool bEnabledOnly, + uint32_t *pui32IntStatus); + +// **************************************************************************** +// +//! @brief Sets the interrupt status. +//! +//! This function sets the CLKGEN interrupts. +//! +//! @param ui32IntMask - One or more of the following bitmasks. +//! AM_HAL_CLKGEN_INTERRUPT_OF +//! AM_HAL_CLKGEN_INTERRUPT_ACC +//! AM_HAL_CLKGEN_INTERRUPT_ACF +//! +//! @return None. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_interrupt_set(am_hal_clkgen_interrupt_e ui32IntMask); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CLKGEN_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.c new file mode 100644 index 0000000..487e75d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.c @@ -0,0 +1,848 @@ +//***************************************************************************** +// +// am_hal_cmdq.c +//! @file +//! +//! @brief Functions for support command queue operations. +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +#define AM_HAL_MAGIC_CMDQ 0xCDCDCD +#define AM_HAL_CMDQ_CHK_HANDLE(h) ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_CMDQ)) + +// Make sure certain register assumptions are valid - else throw compile error +// Make sure the max HWIDX value is same for BLEIF, MSPI & IOM +// Make sure the CQCFG structure is same for BLEIF, MSPI & IOM +#if ((IOM0_CQCURIDX_CQCURIDX_Msk != MSPI_CQCURIDX_CQCURIDX_Msk) || \ + (IOM0_CQCURIDX_CQCURIDX_Pos != MSPI_CQCURIDX_CQCURIDX_Pos) || \ + (IOM0_CQCFG_CQEN_Pos != MSPI_CQCFG_CQEN_Pos) || \ + (IOM0_CQCFG_CQEN_Msk != MSPI_CQCFG_CQEN_Msk) || \ + (IOM0_CQCFG_CQPRI_Pos != MSPI_CQCFG_CQPRI_Pos) || \ + (IOM0_CQCFG_CQPRI_Msk != MSPI_CQCFG_CQPRI_Msk) || \ + (IOM0_CQCURIDX_CQCURIDX_Msk != BLEIF_CQCURIDX_CQCURIDX_Msk) || \ + (IOM0_CQCURIDX_CQCURIDX_Pos != BLEIF_CQCURIDX_CQCURIDX_Pos) || \ + (IOM0_CQCFG_CQEN_Pos != BLEIF_CQCFG_CQEN_Pos) || \ + (IOM0_CQCFG_CQEN_Msk != BLEIF_CQCFG_CQEN_Msk) || \ + (IOM0_CQCFG_CQPRI_Pos != BLEIF_CQCFG_CQPRI_Pos) || \ + (IOM0_CQCFG_CQPRI_Msk != BLEIF_CQCFG_CQPRI_Msk) \ + ) +#error "MSPI and IOM HWIDX, CQCFG implementation needs to match for current CMDQ HAL implementation" +#endif + +#define AM_HAL_CMDQ_HW_IDX_MAX (IOM0_CQCURIDX_CQCURIDX_Msk >> IOM0_CQCURIDX_CQCURIDX_Pos) // 8 bit value +#define AM_HAL_CMDQ_ENABLE_CQ(cfgReg) {AM_REGVAL((cfgReg)) |= _VAL2FLD(IOM0_CQCFG_CQEN, IOM0_CQCFG_CQEN_EN); } +#define AM_HAL_CMDQ_DISABLE_CQ(cfgReg) {AM_REGVAL((cfgReg)) &= ~_VAL2FLD(IOM0_CQCFG_CQEN, IOM0_CQCFG_CQEN_EN); } +#define AM_HAL_CMDQ_INIT_CQCFG(cfgReg, pri, enable) {AM_REGVAL((cfgReg)) = _VAL2FLD(IOM0_CQCFG_CQPRI, (pri)) | _VAL2FLD(IOM0_CQCFG_CQEN, (enable)); } + + +// Need to set the lsb of the CQ entry address for hardware to raise a CQUPD interrupt when processing this entry +#define AM_HAL_CMDQ_ENABLE_CQUPD_INT 0x1 + +typedef struct +{ + volatile uint32_t* regCQCfg; + volatile uint32_t* regCQAddr; + volatile uint32_t* regCurIdx; + volatile uint32_t* regEndIdx; + volatile uint32_t* regCQPause; + uint32_t bitMaskCQPauseIdx; + volatile uint32_t* regCQStat; + + // Different hardware blocks have different bit assignments for status flags + uint32_t bitMaskCQStatTIP; + uint32_t bitMaskCQStatErr; + uint32_t bitMaskCQStatPaused; +} am_hal_cmdq_registers_t; + +typedef struct +{ + am_hal_handle_prefix_t prefix; + uint32_t cmdQBufStart; + uint32_t cmdQBufEnd; + uint32_t cmdQHead; + uint32_t cmdQTail; + uint32_t cmdQNextTail; + uint32_t cmdQSize; + uint32_t curIdx; + uint32_t endIdx; + const am_hal_cmdq_registers_t *pReg; + uint32_t rawSeqStart; +} am_hal_cmdq_t; + +// Global variables +static am_hal_cmdq_t gAmHalCmdq[AM_HAL_CMDQ_IF_MAX]; + +static const am_hal_cmdq_registers_t gAmHalCmdQReg[AM_HAL_CMDQ_IF_MAX] = +{ + // AM_HAL_CMDQ_IF_IOM0 + { + &IOM0->CQCFG, &IOM0->CQADDR, + &IOM0->CQCURIDX, &IOM0->CQENDIDX, + &IOM0->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM0->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_IOM1 + { + &IOM1->CQCFG, &IOM1->CQADDR, + &IOM1->CQCURIDX, &IOM1->CQENDIDX, + &IOM1->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM1->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_IOM2 + { + &IOM2->CQCFG, &IOM2->CQADDR, + &IOM2->CQCURIDX, &IOM2->CQENDIDX, + &IOM2->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM2->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_IOM3 + { + &IOM3->CQCFG, &IOM3->CQADDR, + &IOM3->CQCURIDX, &IOM3->CQENDIDX, + &IOM3->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM3->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_IOM4 + { + &IOM4->CQCFG, &IOM4->CQADDR, + &IOM4->CQCURIDX, &IOM4->CQENDIDX, + &IOM4->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM4->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_IOM5 + { + &IOM5->CQCFG, &IOM5->CQADDR, + &IOM5->CQCURIDX, &IOM5->CQENDIDX, + &IOM5->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM5->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_MSPI + { + &MSPI->CQCFG, &MSPI->CQADDR, + &MSPI->CQCURIDX, &MSPI->CQENDIDX, + &MSPI->CQPAUSE, MSPI_CQPAUSE_CQMASK_CQIDX, + &MSPI->CQSTAT, MSPI_CQSTAT_CQTIP_Msk, + MSPI_CQSTAT_CQERR_Msk, MSPI_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_BLEIF + { + &BLEIF->CQCFG, &BLEIF->CQADDR, + &BLEIF->CQCURIDX, &BLEIF->CQENDIDX, + &BLEIF->CQPAUSEEN, BLEIF_CQPAUSEEN_CQPEN_CNTEQ, + &BLEIF->CQSTAT, BLEIF_CQSTAT_CQTIP_Msk, + BLEIF_CQSTAT_CQERR_Msk, BLEIF_CQSTAT_CQPAUSED_Msk + }, +}; + +// Sync up with the current hardware indices and pointers +static void +update_indices(am_hal_cmdq_t *pCmdQ) +{ + int32_t hwCurIdx; + + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + hwCurIdx = AM_REGVAL(pCmdQ->pReg->regCurIdx) & AM_HAL_CMDQ_HW_IDX_MAX; + + // Derive the 32b values from the current hardware index values + // It is guaranteed that pCmdQ->endIdx is <= pCmdQ->curIdx + AM_HAL_CMDQ_HW_IDX_MAX - 1 + pCmdQ->curIdx = (pCmdQ->endIdx & ~AM_HAL_CMDQ_HW_IDX_MAX) | hwCurIdx; + if (AM_HAL_U32_SMALLER(pCmdQ->endIdx, pCmdQ->curIdx)) + { + pCmdQ->curIdx -= (AM_HAL_CMDQ_HW_IDX_MAX + 1); + } + pCmdQ->cmdQHead = AM_REGVAL(pCmdQ->pReg->regCQAddr); + + // + // End the critical section. + // + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Initialize a Command Queue +//! +//! Initializes the command queue data structure for the given interface +//! +//! @param hwIf identifies the underlying hardware interface +//! @param cmdQSize Size of supplied memory in multiple of 8 Bytes +//! @param pCmdQBuf Command Queue Buffer +//! @param ppHandle Return Parameter - handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_init(am_hal_cmdq_if_e hwIf, am_hal_cmdq_cfg_t *pCfg, void **ppHandle) +{ + am_hal_cmdq_t *pCmdQ; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (hwIf >= AM_HAL_CMDQ_IF_MAX) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + if (!pCfg || !pCfg->pCmdQBuf || !ppHandle || (pCfg->cmdQSize < 2)) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (gAmHalCmdq[hwIf].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + pCmdQ = &gAmHalCmdq[hwIf]; + pCmdQ->cmdQSize = pCfg->cmdQSize * sizeof(am_hal_cmdq_entry_t); + pCmdQ->cmdQTail = pCmdQ->cmdQNextTail = pCmdQ->cmdQHead = pCmdQ->cmdQBufStart = (uint32_t)pCfg->pCmdQBuf; + pCmdQ->cmdQBufEnd = (uint32_t)pCfg->pCmdQBuf + pCfg->cmdQSize * sizeof(am_hal_cmdq_entry_t); + pCmdQ->prefix.s.bInit = true; + pCmdQ->prefix.s.bEnable = false; + pCmdQ->prefix.s.magic = AM_HAL_MAGIC_CMDQ; + pCmdQ->pReg = &gAmHalCmdQReg[hwIf]; + pCmdQ->curIdx = 0; + pCmdQ->endIdx = 0; + AM_REGVAL(pCmdQ->pReg->regCurIdx) = 0; + AM_REGVAL(pCmdQ->pReg->regEndIdx) = 0; + AM_REGVAL(pCmdQ->pReg->regCQPause) |= pCmdQ->pReg->bitMaskCQPauseIdx; + // Initialize the hardware registers + AM_REGVAL(pCmdQ->pReg->regCQAddr) = (uint32_t)pCfg->pCmdQBuf; + AM_HAL_CMDQ_INIT_CQCFG(pCmdQ->pReg->regCQCfg, pCfg->priority, false); + *ppHandle = pCmdQ; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Enable a Command Queue +//! +//! Enables the command queue for the given interface +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_enable(void *pHandle) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if (pCmdQ->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + AM_HAL_CMDQ_ENABLE_CQ(pCmdQ->pReg->regCQCfg); + pCmdQ->prefix.s.bEnable = true; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Disable a Command Queue +//! +//! Disables the command queue for the given interface +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_disable(void *pHandle) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (!pCmdQ->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } + AM_HAL_CMDQ_DISABLE_CQ(pCmdQ->pReg->regCQCfg); + pCmdQ->prefix.s.bEnable = false; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Allocate a block of commands for posting to a command queue +//! +//! Allocates a contiguous block of command queue entries from the available +//! space in command queue +//! +//! @param pHandle handle for the command queue +//! @param numCmd Size of the command block (each block being 8 bytes) +//! @param ppBlock - Return parameter - Pointer to contiguous block of commands, +//! which can be posted +//! @param pIdx - Return parameter - monotonically increasing transaction index +//! +//! This function will take care of determining that enough space is available +//! to create the desired block. It also takes care of necessary wrap-around +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_alloc_block(void *pHandle, uint32_t numCmd, am_hal_cmdq_entry_t **ppBlock, uint32_t *pIdx) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + am_hal_cmdq_entry_t *pCmdQEntry; + uint32_t blockAddr; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!ppBlock || !pIdx) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pCmdQ->cmdQTail != pCmdQ->cmdQNextTail) + { + // Previously allocated block has not been posted/aborted yet + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + update_indices(pCmdQ); + // We need to not use the hwIdx completely, as otherwise we can not distinguish between + // Empty and full case + if (AM_HAL_U32_SMALLER((pCmdQ->curIdx + AM_HAL_CMDQ_HW_IDX_MAX - 1), (pCmdQ->endIdx))) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + // Determine if we can allocate the block, and if so, where + if (pCmdQ->cmdQTail >= pCmdQ->cmdQHead) + { + // Choices: Following last block if there is enough space before wrap + // Otherwise, need to allocate block from the top of the memory + // For a sequence - we'll always come to this case, as the sequence is not started before building + + // Need space for 2 more entries - one for updating curIdx, other for CQ Wrap + if ((pCmdQ->cmdQTail + (numCmd + 2)*sizeof(am_hal_cmdq_entry_t)) <= pCmdQ->cmdQBufEnd) + { + // Enough space in the queue without wrap + blockAddr = pCmdQ->cmdQTail; + } + else + { + // Need to wrap + // Need space for 1 more entry - for updating curIdx + if ((pCmdQ->cmdQBufStart + (numCmd + 1) * sizeof(am_hal_cmdq_entry_t)) < pCmdQ->cmdQHead) + { + // Initialize the tail of CmdQ for Wrap + pCmdQEntry = (am_hal_cmdq_entry_t *)pCmdQ->cmdQTail; + pCmdQEntry->address = (uint32_t)pCmdQ->pReg->regCQAddr; + pCmdQEntry->value = pCmdQ->cmdQBufStart; + blockAddr = pCmdQ->cmdQBufStart; + } + else + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + } + } + else + { + // Need space for 1 more entry - for updating curIdx + if ((pCmdQ->cmdQTail + (numCmd + 1) * sizeof(am_hal_cmdq_entry_t)) < pCmdQ->cmdQHead) + { + blockAddr = pCmdQ->cmdQTail; + } + else + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + } + *ppBlock = (am_hal_cmdq_entry_t *)blockAddr; + *pIdx = ++pCmdQ->endIdx; + pCmdQ->cmdQNextTail = blockAddr + numCmd * sizeof(am_hal_cmdq_entry_t); + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Release a block of commands previously allocated +//! +//! Releases the contiguous block of command queue entries previously allocated +//! without posting +//! +//! @param pHandle handle for the command queue +//! +//! This function will internally handles the curIdx/endIdx manipulation. +//! It also takes care of necessary wrap-around +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_release_block(void *pHandle) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (pCmdQ->cmdQTail == pCmdQ->cmdQNextTail) + { + // No block has been allocated + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // Free up the block + pCmdQ->cmdQNextTail = pCmdQ->cmdQTail; + pCmdQ->endIdx--; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Post the last block allocated +//! +//! Post the contiguous block of command queue entries previously allocated +//! +//! @param pHandle handle for the command queue +//! @param bInt Whether the UPD interrupt is desired once the block is processed +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_post_block(void *pHandle, bool bInt) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + am_hal_cmdq_entry_t *pCmdQEntry; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (pCmdQ->cmdQTail == pCmdQ->cmdQNextTail) + { + // No block has been allocated + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // CmdQ entries have already been populated. Just need to inform hardware of the new endIdx + // Fill up the index update entry + pCmdQEntry = (am_hal_cmdq_entry_t *)pCmdQ->cmdQNextTail; + pCmdQEntry->address = ((uint32_t)pCmdQ->pReg->regCurIdx) | (bInt ? AM_HAL_CMDQ_ENABLE_CQUPD_INT : 0); + pCmdQEntry->value = pCmdQ->endIdx; + // cmdQNextTail should now point to the first entry after the allocated block + pCmdQ->cmdQTail = pCmdQ->cmdQNextTail = (uint32_t)(pCmdQEntry + 1); + AM_REGVAL(pCmdQ->pReg->regEndIdx) = pCmdQ->endIdx & AM_HAL_CMDQ_HW_IDX_MAX; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Get Command Queue status +//! +//! Get the current state of the Command queue +//! +//! @param pHandle handle for the command queue +//! @param pStatus Return Parameter - status information +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_get_status(void *pHandle, am_hal_cmdq_status_t *pStatus) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + uint32_t status; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!pStatus) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + update_indices(pCmdQ); + pStatus->lastIdxProcessed = pCmdQ->curIdx; + pStatus->lastIdxAllocated = pCmdQ->endIdx; + pStatus->lastIdxPosted = pCmdQ->endIdx - ((pCmdQ->cmdQNextTail == pCmdQ->cmdQTail) ? 0 : 1); + status = AM_REGVAL(pCmdQ->pReg->regCQStat); + pStatus->bTIP = status & pCmdQ->pReg->bitMaskCQStatTIP; + pStatus->bPaused = status & pCmdQ->pReg->bitMaskCQStatPaused; + pStatus->bErr = status & pCmdQ->pReg->bitMaskCQStatErr; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Terminate a Command Queue +//! +//! Terminates the command queue data structure +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_term(void *pHandle, bool bForce) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + update_indices(pCmdQ); + if (!bForce && (pCmdQ->curIdx != pCmdQ->endIdx)) + { + return AM_HAL_STATUS_IN_USE; + } + pCmdQ->prefix.s.bInit = false; + // Disable Command Queue + AM_HAL_CMDQ_DISABLE_CQ(pCmdQ->pReg->regCQCfg); + AM_REGVAL(pCmdQ->pReg->regCQPause) &= ~pCmdQ->pReg->bitMaskCQPauseIdx; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Clear the CQ error and resume with the next transaction. +//! The CQ is left disabled after this call +//! It is the responsibility of the caller to re-enable the CQ +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_error_resume(void *pHandle) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + am_hal_cmdq_entry_t *pCQAddr; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if (!pCmdQ->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // First Disable the Command Queue + AM_HAL_CMDQ_DISABLE_CQ(pCmdQ->pReg->regCQCfg); + + // Need to identify end of block for the transaction where hardware is stuck + // Move the CQADDR to the last entry in the block which will update the curIdx + // and then move on. + pCQAddr = (am_hal_cmdq_entry_t *)AM_REGVAL(pCmdQ->pReg->regCQAddr); + while ((pCQAddr->address & ~AM_HAL_CMDQ_ENABLE_CQUPD_INT) != (uint32_t)(pCmdQ->pReg->regCurIdx)) + { + // Is this element changing the CQ Address itself? + if (pCQAddr->address == (uint32_t)(pCmdQ->pReg->regCQAddr)) + { + pCQAddr = (am_hal_cmdq_entry_t *)pCQAddr->value; + } + else + { + ++pCQAddr; + } + } + + // The pCQAddr now points to the address of the command which will update the curIdx + // Disable update interrupt, as we would have already handled this error + *(&pCQAddr->address) = (uint32_t)pCmdQ->pReg->regCurIdx; + AM_REGVAL(pCmdQ->pReg->regCQAddr) = (uint32_t)pCQAddr; + + pCmdQ->prefix.s.bEnable = false; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Pause the CQ after finishing the current transaction. +//! The CQ is in paused state after this function returns, at the beginning of next transaction +//! +//! @param pHandle handle for the command queue +//! @param pSETCLRAddr Points to the SETCLR register for the module +//! @param ui32CQPauseSETCLR Value to be written to Pause the CQ +//! @param ui32CQUnpauseSETCLR Value to be written to unpause the CQ +//! @param ui32usMaxDelay Max time to wait (in uS) +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_pause(void *pHandle, uint32_t *pSETCLRAddr, uint32_t ui32CQPauseSETCLR, uint32_t ui32CQUnpauseSETCLR, uint32_t ui32usMaxDelay) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + uint32_t cqAddr; + am_hal_cmdq_entry_t *pCQAddr; + am_hal_cmdq_entry_t cqEntry; + uint32_t status = AM_HAL_STATUS_SUCCESS; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if (!pCmdQ->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // First Pause the Command Queue + *pSETCLRAddr = ui32CQPauseSETCLR; + status = am_hal_flash_delay_status_change(ui32usMaxDelay, (uint32_t)pCmdQ->pReg->regCQStat, pCmdQ->pReg->bitMaskCQStatPaused, pCmdQ->pReg->bitMaskCQStatPaused); + if (status != AM_HAL_STATUS_SUCCESS) + { + return status; + } + // Now seek for the end of current transaction + cqAddr = AM_REGVAL(pCmdQ->pReg->regCQAddr); + if (cqAddr == pCmdQ->cmdQNextTail) + { + // Already at the end + // No need to do anything else + } + else + { + // Need to identify end of block for the transaction + pCQAddr = (am_hal_cmdq_entry_t *)cqAddr; + while ((pCQAddr->address & ~AM_HAL_CMDQ_ENABLE_CQUPD_INT) != (uint32_t)(pCmdQ->pReg->regCurIdx)) + { + if ( (uint32_t) ++pCQAddr >= pCmdQ->cmdQBufEnd ) + { + // This should not happen + return AM_HAL_STATUS_FAIL; + } + } + + // The pCQAddr now points to the address of the command which will update the curIdx + // We need to resume the CQ till it finishes this entry + // For that we'll temporarily replace the next entry to cause a Pause + // Backup the current content + cqEntry = *(++pCQAddr); + pCQAddr->address = (uint32_t)pSETCLRAddr; + pCQAddr->value = ui32CQPauseSETCLR; + // Wait for it to execute this new entry, or get paused for some other condition + do + { + // Resume the CQ + *pSETCLRAddr = ui32CQUnpauseSETCLR; + // Ensure CQ sees it + am_hal_flash_delay(3); + // Now wait for it to be paused again + status = am_hal_flash_delay_status_change(ui32usMaxDelay, (uint32_t)pCmdQ->pReg->regCQStat, pCmdQ->pReg->bitMaskCQStatPaused, pCmdQ->pReg->bitMaskCQStatPaused); + if (status != AM_HAL_STATUS_SUCCESS) + { + return status; + } + // Try Setting the PAUSE condition while in same position + *pSETCLRAddr = ui32CQPauseSETCLR; + // Ensure CQ sees it + am_hal_flash_delay(3); + status = am_hal_flash_delay_status_change(ui32usMaxDelay, (uint32_t)pCmdQ->pReg->regCQStat, pCmdQ->pReg->bitMaskCQStatPaused, pCmdQ->pReg->bitMaskCQStatPaused); + if (status != AM_HAL_STATUS_SUCCESS) + { + return status; + } + if (cqAddr == AM_REGVAL(pCmdQ->pReg->regCQAddr)) + { + // CQ no longer moving + break; + } + else + { + cqAddr = AM_REGVAL(pCmdQ->pReg->regCQAddr); + } +#if 0 + // Now that it is paused - check if we have reached our entry - or it paused somewhere else + cqAddr = AM_REGVAL(pCmdQ->pReg->regCQAddr); + if (cqAddr != (uint32_t)(pCQAddr + 1)) + { + // It paused due to some other reason + // Try Setting the PAUSE condition while in same position + *pSETCLRAddr = ui32CQPauseSETCLR; + // Ensure CQ sees it + am_hal_flash_delay(3); + status = am_hal_flash_delay_status_change(ui32usMaxDelay, (uint32_t)pCmdQ->pReg->regCQStat, pCmdQ->pReg->bitMaskCQStatPaused, pCmdQ->pReg->bitMaskCQStatPaused); + if (status != AM_HAL_STATUS_SUCCESS) + { + return status; + } + if (AM_REGVAL(pCmdQ->pReg->regCQAddr) == cqAddr) + { + // CQ did not move after we set the PAUSE - so it is at a designated pause place + // Safe to return now + break; + } + else + { + // CQ is moving...need to retry + } + } + else + { + // Reached the desired place + break; + } +#endif + } while(1); + // Now let's revert the CQ content and set the CQADDR to correct place for it to resume later + // when the CQ is unpaused + *pCQAddr = cqEntry; + if (AM_REGVAL(pCmdQ->pReg->regCQAddr) == (uint32_t)(pCQAddr + 1)) + { + AM_REGVAL(pCmdQ->pReg->regCQAddr) = (uint32_t)pCQAddr; + } + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Reset the Command Queue +//! +//! Reset the Command Queue & associated data structures +//! This will force the CQ reset +//! Caller needs to ensure CQ is in steady state before this is done +//! This also disables the CQ +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_reset(void *pHandle) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (pCmdQ->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + AM_HAL_CMDQ_DISABLE_CQ(pCmdQ->pReg->regCQCfg); + pCmdQ->cmdQTail = pCmdQ->cmdQNextTail = pCmdQ->cmdQHead = pCmdQ->cmdQBufStart; + pCmdQ->curIdx = 0; + pCmdQ->endIdx = 0; + AM_REGVAL(pCmdQ->pReg->regCurIdx) = 0; + AM_REGVAL(pCmdQ->pReg->regEndIdx) = 0; + // Initialize the hardware registers + AM_REGVAL(pCmdQ->pReg->regCQAddr) = pCmdQ->cmdQBufStart; + pCmdQ->prefix.s.bEnable = false; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Post the last block allocated with the additional wrap to start +//! +//! Post the contiguous block of command queue entries previously allocated +//! with the additional wrap to start +//! +//! @param pHandle handle for the command queue +//! @param bInt Whether the UPD interrupt is desired once the block is processed +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_post_loop_block(void *pHandle, bool bInt) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + am_hal_cmdq_entry_t *pCmdQEntry; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (pCmdQ->cmdQTail == pCmdQ->cmdQNextTail) + { + // No block has been allocated + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // CmdQ entries have already been populated. Just need to inform hardware of the new endIdx + // Reset the index to 0 + pCmdQEntry = (am_hal_cmdq_entry_t *)pCmdQ->cmdQNextTail; + pCmdQEntry->address = (uint32_t)pCmdQ->pReg->regCurIdx; + pCmdQEntry->value = 0; + pCmdQEntry++; + // Fill up the loopback entry + // At the alloc time, we were guaranteed one extra entry for loopback + pCmdQEntry->address = (uint32_t)pCmdQ->pReg->regCQAddr | (bInt ? AM_HAL_CMDQ_ENABLE_CQUPD_INT : 0); + pCmdQEntry->value = pCmdQ->cmdQBufStart; + // cmdQNextTail should now point to the first entry after the allocated block + pCmdQ->cmdQTail = pCmdQ->cmdQNextTail = (uint32_t)(pCmdQEntry + 1); + // Since we are not updating the curIdx - this will cause CQ to run indefinetely + AM_REGVAL(pCmdQ->pReg->regEndIdx) = pCmdQ->endIdx & AM_HAL_CMDQ_HW_IDX_MAX; + return AM_HAL_STATUS_SUCCESS; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.h new file mode 100644 index 0000000..6e697cd --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.h @@ -0,0 +1,293 @@ +//***************************************************************************** +// +// am_hal_cmdq.h +//! @file +//! +//! @brief Functions for support command queue operations. +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_CMDQ_H +#define AM_HAL_CMDQ_H + +// Identification for underlying hardware interface +typedef enum +{ + AM_HAL_CMDQ_IF_IOM0, + AM_HAL_CMDQ_IF_IOM1, + AM_HAL_CMDQ_IF_IOM2, + AM_HAL_CMDQ_IF_IOM3, + AM_HAL_CMDQ_IF_IOM4, + AM_HAL_CMDQ_IF_IOM5, + AM_HAL_CMDQ_IF_MSPI, + AM_HAL_CMDQ_IF_BLEIF, + AM_HAL_CMDQ_IF_MAX, +} am_hal_cmdq_if_e; + +typedef enum +{ + AM_HAL_CMDQ_PRIO_LOW, + AM_HAL_CMDQ_PRIO_HI, +} am_hal_cmdq_priority_e; + +typedef struct +{ + uint32_t cmdQSize; + uint32_t *pCmdQBuf; + am_hal_cmdq_priority_e priority; +} am_hal_cmdq_cfg_t; + +typedef struct +{ + uint32_t address; + uint32_t value; +} am_hal_cmdq_entry_t; + +typedef struct +{ + uint32_t lastIdxProcessed; + uint32_t lastIdxPosted; + uint32_t lastIdxAllocated; + bool bTIP; + bool bPaused; + bool bErr; +} am_hal_cmdq_status_t; + + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! @brief Initialize a Command Queue +//! +//! Initializes the command queue data structure for the given interface +//! +//! @param hwIf identifies the underlying hardware interface +//! @param cmdQSize Size of supplied memory in multiple of 8 Bytes +//! @param pCmdQBuf Command Queue Buffer +//! @param ppHandle Return Parameter - handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_init(am_hal_cmdq_if_e hwIf, am_hal_cmdq_cfg_t *pCfg, void **ppHandle); + + +//***************************************************************************** +// +//! @brief Enable a Command Queue +//! +//! Enables the command queue for the given interface +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_enable(void *pHandle); + +//***************************************************************************** +// +//! @brief Disable a Command Queue +//! +//! Disables the command queue for the given interface +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_disable(void *pHandle); + +//***************************************************************************** +// +//! @brief Allocate a block of commands for posting to a command queue +//! +//! Allocates a contiguous block of command queue entries from the available +//! space in command queue +//! +//! @param pHandle handle for the command queue +//! @param numCmd Size of the command block (each block being 8 bytes) +//! @param ppBlock - Return parameter - Pointer to contiguous block of commands, +//! which can be posted +//! @param pIdx - Return parameter - monotonically increasing transaction index +//! +//! This function will take care of determining that enough space is available +//! to create the desired block. It also takes care of necessary wrap-around +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_alloc_block(void *pHandle, uint32_t numCmd, am_hal_cmdq_entry_t **ppBlock, uint32_t *pIdx); + +//***************************************************************************** +// +//! @brief Release a block of commands previously allocated +//! +//! Releases the contiguous block of command queue entries previously allocated +//! without posting +//! +//! @param pHandle handle for the command queue +//! +//! This function will internally handles the curIdx/endIdx manipulation. +//! It also takes care of necessary wrap-around +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_release_block(void *pHandle); + +//***************************************************************************** +// +//! @brief Post the last block allocated +//! +//! Post the contiguous block of command queue entries previously allocated +//! +//! @param pHandle handle for the command queue +//! @param bInt Whether the UPD interrupt is desired once the block is processed +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_post_block(void *pHandle, bool bInt); + +//***************************************************************************** +// +//! @brief Get Command Queue status +//! +//! Get the current state of the Command queue +//! +//! @param pHandle handle for the command queue +//! @param pStatus Return Parameter - status information +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_get_status(void *pHandle, am_hal_cmdq_status_t *pStatus); + +//***************************************************************************** +// +//! @brief Terminate a Command Queue +//! +//! Terminates the command queue data structure +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_term(void *pHandle, bool bForce); + + +//***************************************************************************** +// +//! @brief Clear the CQ error and resume with the next transaction. +//! +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_error_resume(void *pHandle); + +//***************************************************************************** +// +//! @brief Pause the CQ after finishing the current transaction. +//! The CQ is in paused state after this function returns, at the beginning of next transaction +//! +//! @param pHandle handle for the command queue +//! @param pSETCLRAddr Points to the SETCLR register for the module +//! @param ui32CQPauseSETCLR Value to be written to Pause the CQ +//! @param ui32CQUnpauseSETCLR Value to be written to unpause the CQ +//! @param ui32usMaxDelay Max time to wait (in uS) +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_pause(void *pHandle, uint32_t *pSETCLRAddr, + uint32_t ui32CQPauseSETCLR, + uint32_t ui32CQUnpauseSETCLR, uint32_t ui32usMaxDelay); + +//***************************************************************************** +// +//! @brief Reset the Command Queue +//! +//! Reset the Command Queue & associated data structures +//! This will force the CQ reset +//! Caller needs to ensure CQ is in steady state before this is done +//! This also disables the CQ +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_reset(void *pHandle); + +//***************************************************************************** +// +//! @brief Post the last block allocated with the additional wrap to start +//! +//! Post the contiguous block of command queue entries previously allocated +//! with the additional wrap to start +//! +//! @param pHandle handle for the command queue +//! @param bInt Whether the UPD interrupt is desired once the block is processed +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_post_loop_block(void *pHandle, bool bInt); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CMDQ_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.c new file mode 100644 index 0000000..4798503 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.c @@ -0,0 +1,2294 @@ +//***************************************************************************** +// +// am_hal_ctimer.c +//! @file +//! +//! @brief Functions for interfacing with the Counter/Timer module. +//! +//! @addtogroup ctimer3 Counter/Timer (CTIMER) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Adjacency check +// +// This is related to the timer read workaround. This macro checks to see if +// the two supplied count values are within one "tick" of eachother. It should +// still pass in the event of a timer rollover. +// +//***************************************************************************** +//! Timer read workaround: Do count values differ by one tick or less. +#define adjacent(A, B) (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0)) + +//***************************************************************************** +// +//! Array of function pointers for handling CTimer interrupts. +// +//***************************************************************************** +static am_hal_ctimer_handler_t g_am_hal_ctimer_ppfnHandlers[32]; + +// +// Store the timer clock source value depending on segment. +// Getting the source clock everytime from the CTRL register will incur bus +// latency. This table is maintained to minimize the read latency when +// attempting to retrieve the CLKSRC. +// CLKSRC is 5 bits, so uint8_t is adequate for the table. +// +static uint8_t +g_ui8ClkSrc[AM_HAL_CTIMER_TIMERS_NUM][2] = +{ + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF} +}; + +// +// Table of TMR register addresses. +// +static const uint32_t +g_ui32TMRAddrTbl[AM_HAL_CTIMER_TIMERS_NUM] = +{ + AM_REGADDR(CTIMER,TMR0), AM_REGADDR(CTIMER,TMR1), AM_REGADDR(CTIMER,TMR2), + AM_REGADDR(CTIMER,TMR3), AM_REGADDR(CTIMER,TMR4), AM_REGADDR(CTIMER,TMR5), + AM_REGADDR(CTIMER,TMR6), AM_REGADDR(CTIMER,TMR7) +}; + +// +// Given the 5-bit clock source value as an index, this lookup table returns the +// number of LSbs to be masked off for the back2back reads. +// +static const uint8_t +g_ui8TmrClkSrcMask[32] = // 5-bit field = 32 table entries +{ + 0x0F, // 0: CTIMER_CTRL0_TMRA0CLK_TMRPIN (CLK_PIN) + 0x0F, // 1: CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4 (HFRC_12MHZ) + 0x03, // 2: CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16 (HFRC_3MHZ) + 0x01, // 3: CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256 (HFRC_187_5KHZ) + 0x01, // 4: CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024 (HFRC_47KHZ) + 0x01, // 5: CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K (HFRC_12KHZ) + 0x00, // 6: CTIMER_CTRL0_TMRA0CLK_XT (XT_32_768KHZ) + 0x00, // 7: CTIMER_CTRL0_TMRA0CLK_XT_DIV2 (XT_16_384KHZ) + 0x00, // 8: CTIMER_CTRL0_TMRA0CLK_XT_DIV16 (XT_2_048KHZ) + 0x00, // 9: CTIMER_CTRL0_TMRA0CLK_XT_DIV128 (XT_256HZ) + 0x00, // 10: CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2 (LFRC_512HZ) + 0x00, // 11: CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32 (LFRC_32HZ) + 0x00, // 12: CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K (LFRC_1HZ) + 0x00, // 13: CTIMER_CTRL0_TMRA0CLK_LFRC (LFRC_1_16HZ) + 0x00, // 14: CTIMER_CTRL0_TMRA0CLK_RTC_100HZ (RTC_100HZ) + 0x00, // 15: CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4 (HCLK_DIV4) + 0x00, // 16: CTIMER_CTRL0_TMRA0CLK_XT_DIV4 (XT_DIV4) + 0x00, // 17: CTIMER_CTRL0_TMRA0CLK_XT_DIV8 (XT_DIV8) + 0x00, // 18: CTIMER_CTRL0_TMRA0CLK_XT_DIV32 (XT_DIV32) + 0x00, // 19: Reserved + 0x0F, // 20: CTIMERxx OUT + 0x0F, // 21: " + 0x0F, // 22: " + 0x0F, // 23: " + 0x0F, // 24: " + 0x0F, // 25: " + 0x0F, // 26: " + 0x0F, // 27: " + 0x0F, // 28: " + 0x00, // 29: CTIMER_CTRL0_TMRA0CLK_BUCKBLE + 0x00, // 30: CTIMER_CTRL0_TMRA0CLK_BUCKB + 0x00 // 31: CTIMER_CTRL0_TMRA0CLK_BUCKA +}; + +//***************************************************************************** +// +// Lookup tables used by am_hal_ctimer_output_config(). +// +// CTx_tbl[] relates the padnum and pad funcsel based on a given CTx. +// Valid pads for CTx are: 4-7, 11-13, 18-19, 22-33, 35, 37, 39, 42-49. +// +// outcfg_tbl[] contains attributes of the 4 output signal types for each +// of the 32 CTx signals. Therefore it is indexed by CTnumber 0-31. +// This table provides only the non-common OUTCFG attributes (2-5, other +// settings are shown below). +// OUTCFG 0 = Force output to 0. +// OUTCFG 1 = Force output to 1. +// OUTCFG 6 = A6OUT2. +// OUTCFG 7 = A7OUT2. +// +//***************************************************************************** +#define CTXPADNUM(ctx) ((CTx_tbl[ctx] >> 0) & 0x3f) +#define CTXPADFNC(ctx) ((CTx_tbl[ctx] >> 8) & 0x7) +#define CTX(pad, fn) ((fn << 8) | (pad << 0)) +static const uint16_t CTx_tbl[32] = +{ + CTX(12,2), CTX(25,2), CTX(13,2), CTX(26,2), CTX(18,2), // 0 - 4 + CTX(27,2), CTX(19,2), CTX(28,2), CTX( 5,7), CTX(29,2), // 5 - 9 + CTX( 6,5), CTX(30,2), CTX(22,2), CTX(31,2), CTX(23,2), // 10 - 14 + CTX(32,2), CTX(42,2), CTX( 4,6), CTX(43,2), CTX( 7,7), // 15 - 19 + CTX(44,2), CTX(24,5), CTX(45,2), CTX(33,6), CTX(46,2), // 20 - 24 + CTX(39,2), CTX(47,2), CTX(35,5), CTX(48,2), CTX(37,7), // 25 - 29 + CTX(49,2), CTX(11,2) // 30 - 31 +}; + +#define OUTC(timB,timN,N2) ((N2 << 4) | (timB << 3) | (timN << 0)) +#define OUTCTIMN(ctx,n) (outcfg_tbl[ctx][n] & (0x7 << 0)) +#define OUTCTIMB(ctx,n) (outcfg_tbl[ctx][n] & (0x1 << 3)) +#define OUTCO2(ctx,n) (outcfg_tbl[ctx][n] & (0x1 << 4)) +static const uint8_t outcfg_tbl[32][4] = +{ + {OUTC(0,0,0), OUTC(1,2,1), OUTC(0,5,1), OUTC(0,6,0)}, // CTX0: A0OUT, B2OUT2, A5OUT2, A6OUT + {OUTC(0,0,1), OUTC(0,0,0), OUTC(0,5,0), OUTC(1,7,1)}, // CTX1: A0OUT2, A0OUT, A5OUT, B7OUT2 + {OUTC(1,0,0), OUTC(1,1,1), OUTC(1,6,1), OUTC(0,7,0)}, // CTX2: B0OUT, B1OUT2, B6OUT2, A7OUT + {OUTC(1,0,1), OUTC(1,0,0), OUTC(0,1,0), OUTC(0,6,0)}, // CTX3: B0OUT2, B0OUT, A1OUT, A6OUT + {OUTC(0,1,0), OUTC(0,2,1), OUTC(0,5,1), OUTC(1,5,0)}, // CTX4: A1OUT, A2OUT2, A5OUT2, B5OUT + {OUTC(0,1,1), OUTC(0,1,0), OUTC(1,6,0), OUTC(0,7,0)}, // CTX5: A1OUT2, A1OUT, B6OUT, A7OUT + {OUTC(1,1,0), OUTC(0,1,0), OUTC(1,5,1), OUTC(1,7,0)}, // CTX6: B1OUT, A1OUT, B5OUT2, B7OUT + {OUTC(1,1,1), OUTC(1,1,0), OUTC(1,5,0), OUTC(0,7,0)}, // CTX7: B1OUT2, B1OUT, B5OUT, A7OUT + {OUTC(0,2,0), OUTC(0,3,1), OUTC(0,4,1), OUTC(1,6,0)}, // CTX8: A2OUT, A3OUT2, A4OUT2, B6OUT + {OUTC(0,2,1), OUTC(0,2,0), OUTC(0,4,0), OUTC(1,0,0)}, // CTX9: A2OUT2, A2OUT, A4OUT, B0OUT + {OUTC(1,2,0), OUTC(1,3,1), OUTC(1,4,1), OUTC(0,6,0)}, // CTX10: B2OUT, B3OUT2, B4OUT2, A6OUT + {OUTC(1,2,1), OUTC(1,2,0), OUTC(1,4,0), OUTC(1,5,1)}, // CTX11: B2OUT2, B2OUT, B4OUT, B5OUT2 + {OUTC(0,3,0), OUTC(1,1,0), OUTC(1,0,1), OUTC(1,6,1)}, // CTX12: A3OUT, B1OUT, B0OUT2, B6OUT2 + {OUTC(0,3,1), OUTC(0,3,0), OUTC(0,6,0), OUTC(1,4,1)}, // CTX13: A3OUT2, A3OUT, A6OUT, B4OUT2 + {OUTC(1,3,0), OUTC(1,1,0), OUTC(1,7,1), OUTC(0,7,0)}, // CTX14: B3OUT, B1OUT, B7OUT2, A7OUT + {OUTC(1,3,1), OUTC(1,3,0), OUTC(0,7,0), OUTC(0,4,1)}, // CTX15: B3OUT2, B3OUT, A7OUT, A4OUT2 + {OUTC(0,4,0), OUTC(0,0,0), OUTC(0,0,1), OUTC(1,3,1)}, // CTX16: A4OUT, A0OUT, A0OUT2, B3OUT2 + {OUTC(0,4,1), OUTC(1,7,0), OUTC(0,4,0), OUTC(0,1,1)}, // CTX17: A4OUT2, B7OUT, A4OUT, A1OUT2 + {OUTC(1,4,0), OUTC(1,0,0), OUTC(0,0,0), OUTC(0,3,1)}, // CTX18: B4OUT, B0OUT, A0OUT, A3OUT2 + {OUTC(1,4,1), OUTC(0,2,0), OUTC(1,4,0), OUTC(1,1,1)}, // CTX19: B4OUT2, A2OUT, B4OUT, B1OUT2 + {OUTC(0,5,0), OUTC(0,1,0), OUTC(0,1,1), OUTC(1,2,1)}, // CTX20: A5OUT, A1OUT, A1OUT2, B2OUT2 + {OUTC(0,5,1), OUTC(0,1,0), OUTC(1,5,0), OUTC(0,0,1)}, // CTX21: A5OUT2, A1OUT, B5OUT, A0OUT2 + {OUTC(1,5,0), OUTC(0,6,0), OUTC(0,1,0), OUTC(0,2,1)}, // CTX22: B5OUT, A6OUT, A1OUT, A2OUT2 + {OUTC(1,5,1), OUTC(0,7,0), OUTC(0,5,0), OUTC(1,0,1)}, // CTX23: B5OUT2, A7OUT, A5OUT, B0OUT2 + {OUTC(0,6,0), OUTC(0,2,0), OUTC(0,1,0), OUTC(1,1,1)}, // CTX24: A6OUT, A2OUT, A1OUT, B1OUT2 + {OUTC(1,4,1), OUTC(1,2,0), OUTC(0,6,0), OUTC(0,2,1)}, // CTX25: B4OUT2, B2OUT, A6OUT, A2OUT2 + {OUTC(1,6,0), OUTC(1,2,0), OUTC(0,5,0), OUTC(0,1,1)}, // CTX26: B6OUT, B2OUT, A5OUT, A1OUT2 + {OUTC(1,6,1), OUTC(0,1,0), OUTC(1,6,0), OUTC(1,2,1)}, // CTX27: B6OUT2, A1OUT, B6OUT, B2OUT2 + {OUTC(0,7,0), OUTC(0,3,0), OUTC(0,5,1), OUTC(1,0,1)}, // CTX28: A7OUT, A3OUT, A5OUT2, B0OUT2 + {OUTC(1,5,1), OUTC(0,1,0), OUTC(0,7,0), OUTC(0,3,1)}, // CTX29: B5OUT2, A1OUT, A7OUT, A3OUT2 + {OUTC(1,7,0), OUTC(1,3,0), OUTC(0,4,1), OUTC(0,0,1)}, // CTX30: B7OUT, B3OUT, A4OUT2, A0OUT2 + {OUTC(1,7,1), OUTC(0,6,0), OUTC(1,7,0), OUTC(1,3,1)}, // CTX31: B7OUT2, A6OUT, B7OUT, B3OUT2 +}; + +//***************************************************************************** +// +// Static function for reading the timer value. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm void +am_hal_triple_read( uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + push {r1, r4} // Save r1=ui32Data, r4 + mrs r4, PRIMASK // Save current interrupt state + cpsid i // Disable INTs while reading the reg + ldr r1, [r0, #0] // Read the designated register 3 times + ldr r2, [r0, #0] // " + ldr r3, [r0, #0] // " + msr PRIMASK, r4 // Restore interrupt state + pop {r0, r4} // Get r0=ui32Data, restore r4 + str r1, [r0, #0] // Store 1st read value to array + str r2, [r0, #4] // Store 2nd read value to array + str r3, [r0, #8] // Store 3rd read value to array + bx lr // Return to caller +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +void +am_hal_triple_read(uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + __asm ( + " push {R1, R4}\n" + " mrs R4, PRIMASK\n" + " cpsid i\n" + " nop\n" + " ldr R1, [R0, #0]\n" + " ldr R2, [R0, #0]\n" + " ldr R3, [R0, #0]\n" + " msr PRIMASK, r4\n" + " pop {R0, R4}\n" + " str R1, [R0, #0]\n" + " str R2, [R0, #4]\n" + " str R3, [R0, #8]\n" + : + : [u32TimerAddr] "r" (u32TimerAddr), + [ui32Data] "r" (&ui32Data[0]) + : "r0", "r1", "r2", "r3", "r4" + ); +} +#elif defined(__GNUC_STDC_INLINE__) +__attribute__((naked)) +void +am_hal_triple_read(uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + __asm + ( + " push {r1, r4}\n" // Save r1=ui32Data, r4 + " mrs r4, PRIMASK \n" // Save current interrupt state + " cpsid i \n" // Disable INTs while reading the reg + " ldr r1, [r0, #0]\n" // Read the designated register 3 times + " ldr r2, [r0, #0]\n" // " + " ldr r3, [r0, #0]\n" // " + " msr PRIMASK, r4 \n" // Restore interrupt state + " pop {r0, r4}\n" // Get r0=ui32Data, restore r4 + " str r1, [r0, #0]\n" // Store 1st read value to array + " str r2, [r0, #4]\n" // Store 2nd read value to array + " str r3, [r0, #8]\n" // Store 3rd read value to array + " bx lr \n" // Return to caller + ); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless void +am_hal_triple_read( uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + __asm(" push {r1, r4} "); // Save r1=ui32Data, r4 + __asm(" mrs r4, PRIMASK "); // Save current interrupt state + __asm(" cpsid i "); // Disable INTs while reading the reg + __asm(" ldr r1, [r0, #0]"); // Read the designated register 3 times + __asm(" ldr r2, [r0, #0]"); // " + __asm(" ldr r3, [r0, #0]"); // " + __asm(" msr PRIMASK, r4 "); // Restore interrupt state + __asm(" pop {r0, r4} "); // Get r0=ui32Data, restore r4 + __asm(" str r1, [r0, #0]"); // Store 1st read value to array + __asm(" str r2, [r0, #4]"); // Store 2nd read value to array + __asm(" str r3, [r0, #8]"); // Store 3rd read value to array + __asm(" bx lr "); // Return to caller +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + + + +//***************************************************************************** +// +// ctimer_clr() +// +// For the appropriate ctimer configuration register, set the CLR bit high +// in the appropriate timer segment (A, B, or both). +// +// The CLR bit is required to be set in order to completely initialize +// the timer at config time. The timer clear occurs asynchrnously during the +// low-to-high transition of the CLR bit. +// +// This function only sets the CLR bit. It is assumed that the actual timer +// configuration will occur following the call to this function and will clear +// the CLR bit at that time. +// +//***************************************************************************** +static void +ctimer_clr(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + // + // Find the address of the correct control register and set the CLR bit + // for the timer segment in that control register. + // + volatile uint32_t *pui32ConfigReg = + (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + AM_CRITICAL_BEGIN + AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & + (CTIMER_CTRL0_TMRA0CLR_Msk | + CTIMER_CTRL0_TMRB0CLR_Msk)); + AM_CRITICAL_END + +} // ctimer_clr() + +//***************************************************************************** +// +//! @brief Convenience function for responding to CTimer interrupts. +//! +//! @param ui32Status is the interrupt status as returned by +//! am_hal_ctimer_int_status_get() +//! +//! This function may be called from am_ctimer_isr() to read the status of +//! the CTimer interrupts, determine which source caused the most recent +//! interrupt, and call an interrupt handler function to respond. The interrupt +//! handler to be called must be first registered with the +//! am_hal_ctimer_int_register() function. +//! +//! In the event that multiple sources are active, the corresponding +//! interrupt handlers will be called in numerical order based on interrupt def. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_service(uint32_t ui32Status) +{ + + am_hal_ctimer_handler_t pfnHandler; + + while ( ui32Status ) + { + uint32_t ui32Clz; + // + // Pick one of any remaining active interrupt bits + // +#ifdef __IAR_SYSTEMS_ICC__ + ui32Clz = __CLZ(ui32Status); +#else + ui32Clz = __builtin_clz(ui32Status); +#endif + + // + // Turn off the bit we picked in the working copy + // + ui32Status &= ~(0x80000000 >> ui32Clz); + + // + // Check the bit handler table to see if there is an interrupt handler + // registered for this particular bit. + // + pfnHandler = g_am_hal_ctimer_ppfnHandlers[31 - ui32Clz]; + if ( pfnHandler ) + { + // + // If we found an interrupt handler routine, call it now. + // + pfnHandler(); + } + } + +} // am_hal_ctimer_int_service() + +//***************************************************************************** +// +//! @brief Register an interrupt handler for CTimer. +//! +//! @param ui32Interrupt - interrupt number to assign this interrupt handler to. +//! @param pfnHandler - Function to call when this interrupt is received. +//! +//! This function allows the caller to specify a function that should be called +//! any time a Ctimer interrupt is received. Registering an +//! interrupt handler using this function adds the function pointer to an array +//! in SRAM. This interrupt handler will be called by am_hal_ctimer_int_service() +//! whenever the ui32Status parameter indicates that the corresponding interrupt. +//! +//! To remove an interrupt handler that has already been registered, the +//! pfnHandler parameter may be set to zero. +//! +//! @note This function will not have any effect unless the +//! am_hal_ctimer_int_service() function is being used. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_register(uint32_t ui32Interrupt, + am_hal_ctimer_handler_t pfnHandler) +{ + uint32_t intIdx = 0; + + // + // Check to make sure the interrupt number is valid. (Debug builds only) + // + switch (ui32Interrupt) + { + case CTIMER_INTEN_CTMRA0C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA0C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB0C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB0C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA1C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA1C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB1C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB1C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA2C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA2C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB2C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB2C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA3C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA3C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB3C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB3C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA4C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA4C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB4C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB4C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA5C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA5C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB5C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB5C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA6C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA6C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB6C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB6C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA7C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA7C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB7C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB7C0INT_Pos; + break; + + // Counter/Timer A0 interrupt based on COMPR1. + case CTIMER_INTEN_CTMRA0C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA0C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB0C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB0C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRA1C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA1C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB1C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB1C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRA2C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA2C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB2C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB2C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRA3C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA3C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB3C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB3C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRA4C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA4C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB4C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB4C1INT_Pos; + break; + case CTIMER_INTEN_CTMRA5C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA5C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB5C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB5C1INT_Pos; + break; + case CTIMER_INTEN_CTMRA6C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA6C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB6C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB6C1INT_Pos; + break; + case CTIMER_INTEN_CTMRA7C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA7C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB7C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB7C1INT_Pos; + break; + + default: + am_hal_debug_assert_msg(false, "CTimer interrupt number out of range."); + } + + g_am_hal_ctimer_ppfnHandlers[intIdx] = pfnHandler; + +} // am_hal_ctimer_int_register() + +//***************************************************************************** +// +//! @brief Set up the counter/timer. +//! +//! @param ui32ConfigVal is the value to set the global enable register. +//! +//! This function sets the global enable register inside a critical section. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_globen(uint32_t ui32ConfigVal) +{ + uint32_t *pui32ConfigReg; + + // + // Find the correct register to write. + // + pui32ConfigReg = (uint32_t *)(&CTIMERn(0)->GLOBEN); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + + // + // Write our configuration value. + // + AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_globen() + +//***************************************************************************** +// +//! @brief Set up the counter/timer. +//! +//! @param ui32TimerNumber is the number of the Timer that should be +//! configured. +//! +//! @param psConfig is a pointer to a structure that holds important settings +//! for the timer. +//! +//! This function should be used to perform the initial set-up of the +//! counter-timer. +//! +//! @note This function is deprecated and will eventually be replaced by +//! am_hal_ctimer_config_single(), which performs the same configuration +//! without requiring a structure and without assuming both timer halves +//! are being configured. +//! Please use am_hal_ctimer_config_single() for new development. +//! +//! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! +// +//***************************************************************************** +void +am_hal_ctimer_config(uint32_t ui32TimerNumber, + am_hal_ctimer_config_t *psConfig) +{ + uint32_t ui32ConfigVal; + uint32_t ui32Seg, ui32ClkSrc; + uint32_t *pui32ConfigReg; + + // + // Make sure the timer is completely initialized on configuration by + // setting the CLR bit. + // + ctimer_clr(ui32TimerNumber, AM_HAL_CTIMER_BOTH); + + // + // Start preparing the configuration word for this timer. The configuration + // values for Timer A and Timer B provided in the config structure should + // match the register definitions already, so we will mostly just need to + // OR them together. + // + ui32ConfigVal = ( (psConfig->ui32TimerAConfig) | + (psConfig->ui32TimerBConfig << 16) ); + + // + // OR in the Link bit if the timers need to be linked. + // + ui32ConfigVal |= psConfig->ui32Link ? AM_HAL_CTIMER_LINK : 0; + + // + // Find the correct register to write. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + + // + // Write our configuration value. + // + AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + + // + // Save the clock source for this timer. + // + if ( ( psConfig->ui32TimerAConfig != 0 ) || psConfig->ui32Link ) + { + ui32Seg = 0; + ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, psConfig->ui32TimerAConfig); + } + else if ( psConfig->ui32TimerBConfig != 0) + { + ui32Seg = 1; + ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, psConfig->ui32TimerBConfig); + } + else + { + return; + } + + // + // Save the clock source for this timer/segment. + // + g_ui8ClkSrc[ui32TimerNumber][ui32Seg] = ui32ClkSrc; + +} // am_hal_ctimer_config() + +//***************************************************************************** +// +//! @brief Set up the counter/timer. +//! +//! @param ui32TimerNumber is the number of the Timer that should be +//! configured. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! enabled. +//! +//! @param ui32ConfigVal specifies the configuration options for the selected +//! timer. +//! +//! This function should be used to perform the initial set-up of the +//! counter-timer. It can be used to configure either a 16-bit timer (A or B) or a +//! 32-bit timer using the BOTH option. +//! +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! The timer's clock source, mode, interrupt, and external pin behavior are +//! all controlled through the \e ui32Configval parameter. The valid options +//! for ui32ConfigVal include any ORed together combination of the following: +//! +//! Clock configuration macros: +//! +//! AM_HAL_CTIMER_HFRC_24MHZ +//! AM_HAL_CTIMER_LFRC_512HZ +//! ... etc. (See am_hal_ctimer.h for the full set of options.) +//! +//! Mode selection macros: +//! +//! AM_HAL_CTIMER_FN_ONCE +//! AM_HAL_CTIMER_FN_REPEAT +//! AM_HAL_CTIMER_FN_PWM_ONCE +//! AM_HAL_CTIMER_FN_PWM_REPEAT +//! AM_HAL_CTIMER_FN_CONTINUOUS +//! +//! Interrupt control: +//! +//! AM_HAL_CTIMER_INT_ENABLE +//! +//! Pin control: +//! +//! AM_HAL_CTIMER_PIN_ENABLE +//! AM_HAL_CTIMER_PIN_INVERT +//! +//! ADC trigger (Timer 3 only): +//! +//! AM_HAL_CTIMER_ADC_TRIG +//! +//! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! +// +//***************************************************************************** +void +am_hal_ctimer_config_single(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32ConfigVal) +{ + volatile uint32_t *pui32ConfigReg; + uint32_t ui32Seg, ui32ClkSrc; + + // + // Make sure the timer is completely initialized on configuration by + // setting the CLR bit. + // + ctimer_clr(ui32TimerNumber, ui32TimerSegment); + + // + // Find the correct register to write based on the timer number. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + uint32_t ui32WriteVal; + + // + // Save the value that's already in the register. + // + ui32WriteVal = AM_REGVAL(pui32ConfigReg); + + // + // If we're working with TIMERB, we need to shift our configuration value + // up by 16 bits. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32ConfigVal = ((ui32ConfigVal & 0xFFFF) << 16); + } + + // + // Replace part of the saved register value with the configuration value + // from the caller. + // + ui32WriteVal = (ui32WriteVal & ~(ui32TimerSegment)) | ui32ConfigVal; + + // + // If we're configuring both timers, we need to set the "link" bit. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) + { + ui32WriteVal |= AM_HAL_CTIMER_LINK; + } + + // + // Write our completed configuration value. + // + AM_REGVAL(pui32ConfigReg) = ui32WriteVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + + // + // Save the clock source for this timer. + // + switch ( ui32TimerSegment ) + { + case AM_HAL_CTIMER_TIMERA: + case AM_HAL_CTIMER_BOTH: + ui32Seg = 0; + break; + case AM_HAL_CTIMER_TIMERB: + ui32Seg = 1; + break; + default: + return; + } + + ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, ui32ConfigVal); + + // + // Save the clock source for this timer/segment. + // + g_ui8ClkSrc[ui32TimerNumber][ui32Seg] = (uint8_t)ui32ClkSrc; + +} // am_hal_ctimer_config_single() + +//***************************************************************************** +// +//! @brief Set up the counter/timer trigger. +//! +//! @param ui32TimerNumber is the number of the Timer that should be +//! configured. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! enabled. +//! +//! @param ui32ConfigVal specifies the configuration options for the selected +//! timer trigger AUXn register. +//! +//! This function should be used to perform the configuration of the trigger +//! for the counter-timer (A or B). +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! +//! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! +// +//***************************************************************************** +void +am_hal_ctimer_config_trigger(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32ConfigVal) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct register to write based on the timer number. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, AUX0); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + uint32_t ui32WriteVal; + + // + // Save the value that's already in the register. + // + ui32WriteVal = AM_REGVAL(pui32ConfigReg); + + // + // If we're working with TIMERB, we need to shift our configuration value + // up by 16 bits. + // + + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32ConfigVal = ((ui32ConfigVal & 0xFFFF) << 16); + } + + // + // Replace part of the saved register value with the configuration value + // from the caller. + // + ui32WriteVal = (ui32WriteVal & ~(ui32TimerSegment)) | ui32ConfigVal; + + // + // Write our completed configuration value. + // + AM_REGVAL(pui32ConfigReg) = ui32WriteVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_config_trigger() + +//***************************************************************************** +// +//! @brief Start a timer +//! +//! @param ui32TimerNumber is the number of the timer to enable +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! enabled. Valid values for ui32TimerSegment are: +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! This function will enable a timer to begin incrementing. The \e +//! ui32TimerNumber parameter selects the timer that should be enabled, for +//! example, a 0 would target TIMER0. The \e ui32TimerSegment parameter allows +//! the caller to individually select a segment within a timer to be enabled, +//! such as TIMER0A, TIMER0B, or both. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_start(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + uint32_t ui32Seg, ui32ClkSrc; + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + + // + // Read the current value. + // + uint32_t ui32ConfigVal = *pui32ConfigReg; + + // + // Clear out the "clear" bit. + // + ui32ConfigVal &= ~(ui32TimerSegment & (CTIMER_CTRL0_TMRA0CLR_Msk | + CTIMER_CTRL0_TMRB0CLR_Msk)); + + // + // Set the "enable bit" + // + ui32ConfigVal |= (ui32TimerSegment & (CTIMER_CTRL0_TMRA0EN_Msk | + CTIMER_CTRL0_TMRB0EN_Msk)); + + // + // While we already have the CTRL reg, get and save the CLKSRC. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32Seg = 1; + ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRB0CLK, ui32ConfigVal); + } + else + { + ui32Seg = 0; + ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, ui32ConfigVal); + } + + // + // Save the clock source for this timer/segment. + // + g_ui8ClkSrc[ui32TimerNumber][ui32Seg] = ui32ClkSrc; + + // + // Write the configuration to start the timer. + // + AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_start() + +//***************************************************************************** +// +//! @brief Stop a timer +//! +//! @param ui32TimerNumber is the number of the timer to disable. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! disabled. +//! +//! This function will stop the selected timer from incrementing. The \e +//! ui32TimerNumber parameter selects the timer that should be disabled, for +//! example, a 0 would target TIMER0. The \e ui32TimerSegment parameter allows +//! the caller to individually select a segment within a timer to be disabled, +//! such as TIMER0A, TIMER0B, or both. +//! +//! This function will stop a counter/timer from counting, but does not return +//! the count value to 'zero'. If you would like to reset the counter back to +//! zero, try the am_hal_ctimer_clear() function instead. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_stop(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Clear the "enable" bit + // + AM_REGVAL(pui32ConfigReg) &= ~(ui32TimerSegment & + (CTIMER_CTRL0_TMRA0EN_Msk | + CTIMER_CTRL0_TMRB0EN_Msk)); + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_stop() + +//***************************************************************************** +// +//! @brief Stops a timer and resets its value back to zero. +//! +//! @param ui32TimerNumber is the number of the timer to clear. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! cleared. +//! +//! This function will stop a free-running counter-timer, reset its value to +//! zero, and leave the timer disabled. When you would like to restart the +//! counter, you will need to call am_hal_ctimer_start(). +//! +//! The \e ui32TimerSegment parameter allows the caller to individually select +//! a segment within, such as TIMER0A, TIMER0B, or both. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +//! +//! +//! @note Setting the CLR bit is necessary for completing timer initialization +//! including after MCU resets. +//! +// +//***************************************************************************** +void +am_hal_ctimer_clear(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Set the "clear" bit + // + AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & + (CTIMER_CTRL0_TMRA0CLR_Msk | + CTIMER_CTRL0_TMRB0CLR_Msk)); + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_clear() + +//***************************************************************************** +// +//! @brief Returns the current free-running value of the selected timer. +//! +//! @param ui32TimerNumber is the number of the timer to read. +//! @param ui32TimerSegment specifies which segment of the timer should be +//! read. +//! +//! This function returns the current free-running value of the selected timer. +//! +//! @note When reading from a linked timer, be sure to use AM_HAL_CTIMER both +//! for the segment argument. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return Current timer value. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_read(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + uint32_t ui32RetVal = 0; + uint32_t ui32ClkMsk, ui32Seg, ui32TmrAddr, ui32Ctrl; + uint8_t ui8ClkSrc; + uint32_t ui32Values[3]; + + // + // Determine the timer segment. + // + ui32Seg = ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) ? 1 : 0; + + // + // Get the address of the register for this timer. + // + ui32TmrAddr = g_ui32TMRAddrTbl[ui32TimerNumber]; + + // + // Get the clock source for this timer. + // + ui8ClkSrc = g_ui8ClkSrc[ui32TimerNumber][ui32Seg]; + + if ( ui8ClkSrc == 0xFF ) + { + // + // If user did not configure using am_hal_ctimer_config_single() or + // am_hal_ctimer_config(), read the register to get the clock source. + // Note that this will incur bus latencies. + // + ui32Ctrl = AM_REGVAL(ui32TmrAddr + 0xC); + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui8ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRB0CLK, ui32Ctrl); + } + else + { + ui8ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, ui32Ctrl); + } + + // + // And save the clock source to the lookup table. + // + g_ui8ClkSrc[ui32TimerNumber][ui32Seg] = ui8ClkSrc; + } + + // + // Based on the source clock, mask off bits not needed for the comparison. + // + ui32ClkMsk = g_ui8TmrClkSrcMask[ui8ClkSrc & _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, 0xFFFFFFFF)]; + + if ( ui32ClkMsk != 0 ) + { + if ( am_hal_burst_mode_status() == AM_HAL_BURST_MODE ) + { + // + // In burst mode, extend the mask by 1 bit. + // + ui32ClkMsk <<= 1; + ui32ClkMsk |= 0x1; + } + + // + // Invert the mask so that the unneeded bits can be masked off. + // + ui32ClkMsk = ~ui32ClkMsk; + + // + // Read the register into ui32Values[]. + // + am_hal_triple_read(ui32TmrAddr, ui32Values); + + // + // Now determine which of the three values is the correct value. + // If the first 2 match, then the values are both correct and we're done. + // Otherwise, the third value is taken to be the correct value. + // + if ( (ui32Values[0] & ui32ClkMsk) == (ui32Values[1] & ui32ClkMsk) ) + { + // + // If the first two values match, then neither one was a bad read. + // We'll take this as the current time. + // + ui32RetVal = ui32Values[1]; + } + else + { + ui32RetVal = ui32Values[2]; + } + } + else + { + // + // No need for the workaround. Just read and return the register. + // + ui32RetVal = AM_REGVAL(ui32TmrAddr); + } + + // + // Get the correct return value + // + ui32RetVal &= ui32TimerSegment; + + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32RetVal >>= 16; + } + + return ui32RetVal; + +} // am_hal_ctimer_read() + +//***************************************************************************** +// +//! @brief Configure timer pin output. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! @param ui32TimerOutputConfig Output Configuration options. +//! +//! This function will configure the output pin for the selected timer. +//! +//! ui32TimerNumber +//! The timer number, 0-7. +//! ui32TimerSegment +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! ui32PadNum +//! Pad number to be used for the output signal. +//! eOutputType +//! AM_HAL_CTIMER_OUTPUT_NORMAL +//! AM_HAL_CTIMER_OUTPUT_SECONDARY +//! AM_HAL_CTIMER_OUTPUT_FORCE0 +//! AM_HAL_CTIMER_OUTPUT_FORCE1 +//! eDriveStrength +//! AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA = 0x0, +//! AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA = 0x1, +//! AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA = 0x2, +//! AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA = 0x3 +//! +//! @return None. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_output_config(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32PadNum, + uint32_t eOutputType, + uint32_t eDriveStrength) +{ + uint32_t ux, ui32Ctx, ui32CtxPadNum; + uint32_t ui32CtxOutcfgFnc, ui32CtxOutcfgMsk, ui32CfgShf; + uint32_t ui32OutcfgValue; + + am_hal_gpio_pincfg_t sPinCfg = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + if ( (ui32PadNum > 49) || (ui32TimerNumber > 7) || + (eOutputType > AM_HAL_CTIMER_OUTPUT_FORCE1) || + ( (ui32TimerSegment != AM_HAL_CTIMER_TIMERA) && + (ui32TimerSegment != AM_HAL_CTIMER_TIMERB) && + (ui32TimerSegment != AM_HAL_CTIMER_BOTH) ) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Lookup the CTx number based on the given pad number. + // + for ( ux = 0; ux < 32; ux++ ) + { + ui32CtxPadNum = CTXPADNUM(ux); + if ( ui32CtxPadNum == ui32PadNum ) + { + ui32Ctx = ux; + break; + } + ui32CtxPadNum = 0xFF; + } + + if ( ui32CtxPadNum >= AM_HAL_GPIO_MAX_PADS ) + { + // No valid pad found. + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( ( ui32TimerNumber >= 6 ) && + ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA ) && + (eOutputType == AM_HAL_CTIMER_OUTPUT_SECONDARY) ) + { + // + // A6OUT2 is function 6 for every CTx. + // A7OUT2 is function 7 for every CTx. + // Set the function to either 6 or 7. + // + ui32CtxOutcfgFnc = ui32TimerNumber; + } + else if ( eOutputType >= AM_HAL_CTIMER_OUTPUT_FORCE0 ) + { + // Set the function to 0 or 1. + ui32CtxOutcfgFnc = eOutputType - AM_HAL_CTIMER_OUTPUT_FORCE0; + } + else + { + // + // Now, scan outcfg_tbl[] to determine how to set the pin. + // + for ( ux = 0; ux < 4; ux++ ) + { + if ( (OUTCTIMN(ui32Ctx, ux) == ui32TimerNumber) ) + { + bool bTimerB = OUTCTIMB(ui32Ctx, ux); + bool bO2 = OUTCO2(ui32Ctx, ux) ? true : false; + bool bOut2 = (eOutputType == AM_HAL_CTIMER_OUTPUT_SECONDARY); + if ( ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA ) && + (!bTimerB) && + (bO2 == bOut2) ) + { + break; + } + + if ( ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) && + (bTimerB) && + (bO2 == bOut2) ) + { + break; + } + } + } + + if ( ux >= 4 ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + ui32CtxOutcfgFnc = ux + 2; + } + + // + // Looks like everything is valid. Configure the pin. + // Do the actual configuring inside a critical section. + // + ux = ui32Ctx % 10; + ui32CfgShf = ux * 3; + if ( ux > 4 ) + { + ui32CfgShf += 1; + } + ui32CtxOutcfgMsk = 0x7 << ui32CfgShf; + ui32CtxOutcfgFnc <<= ui32CfgShf; + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Note: It turns out that the offsets of the 4 OUTCFG registers are not + // evenly spaced. Therefore we purposely use this 'if' chain to program + // them explicitly (as opposed to doing modulo math to compute an addr). + // + if ( ui32Ctx < 10 ) + { + ui32OutcfgValue = CTIMER->OUTCFG0; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG0 = ui32OutcfgValue; + } + else if ( ui32Ctx < 20 ) + { + ui32OutcfgValue = CTIMER->OUTCFG1; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG1 = ui32OutcfgValue; + } + else if ( ui32Ctx < 30 ) + { + ui32OutcfgValue = CTIMER->OUTCFG2; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG2 = ui32OutcfgValue; + } + else + { + ui32OutcfgValue = CTIMER->OUTCFG3; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG3 = ui32OutcfgValue; + } + + GPIO->CTENCFG &= ~(1 << ui32Ctx); + + // + // Done with critical section. + // + AM_CRITICAL_END + + // + // Configure the GPIO for the given pad. + // + sPinCfg.uFuncSel = CTXPADFNC(ui32Ctx); + sPinCfg.eDriveStrength = eDriveStrength; + am_hal_gpio_pinconfig(ui32CtxPadNum, sPinCfg); + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_ctimer_output_config() + +//***************************************************************************** +// +//! @brief Configure timer inputs. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! @param ui32TimerInputConfig Input Configuration options. +//! +//! This function will configure the input pin for the selected timer. +//! +//! Valid values for ui32TimerSegment are: +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_input_config(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32TimerInputConfig) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_input_config() + +//***************************************************************************** +// +//! @brief Set a compare register. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @param ui32CompareReg specifies which compare register should be set +//! (either 0 or 1) +//! +//! @param ui32Value is the value that should be written to the compare +//! register. +//! +//! This function allows the caller to set the values in the compare registers +//! for a timer. These registers control the period and duty cycle of the +//! timers and their associated output pins. Please see the datasheet for +//! further information on the operation of the compare registers. The \e +//! ui32TimerSegment parameter allows the caller to individually select a +//! segment within, such as TIMER0A, TIMER0B, or both. +//! +//! @note For simple manipulations of period or duty cycle for timers and PWMs, +//! you may find it easier to use the am_hal_ctimer_period_set() function. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_compare_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32CompareReg, uint32_t ui32Value) +{ + volatile uint32_t *pui32CmprRegA, *pui32CmprRegB; + uint32_t ui32CmprRegA, ui32CmprRegB, ui32ValB; + + // + // Find the correct compare register to write. + // Assume A or BOTH. We'll change later if B. + // + pui32CmprRegA = (uint32_t *)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRA0); + pui32CmprRegB = (uint32_t *)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRB0); + + ui32ValB = ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) ? + ui32Value >> 16 : ui32Value & 0xFFFF; + + // + // Write the compare register with the selected value. + // Begin critical section while CMPR registers are modified. + // + AM_CRITICAL_BEGIN + + ui32CmprRegA = *pui32CmprRegA; + ui32CmprRegB = *pui32CmprRegB; + + if ( ui32CompareReg == 1 ) + { + // + // CMPR reg 1 + // Get the lower 16b (but may not be used if TIMERB). + // + ui32CmprRegA = ( (ui32CmprRegA & CTIMER_CMPRA0_CMPR0A0_Msk) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32Value & 0xFFFF) ); + + // + // Get the upper 16b (but may not be used if TIMERA) + // + ui32CmprRegB = ( (ui32CmprRegB & CTIMER_CMPRA0_CMPR0A0_Msk) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32ValB) ); + } + else + { + // + // CMPR reg 0 + // Get the lower 16b (but may not be used if TIMERB) + // + ui32CmprRegA = ( (ui32CmprRegA & CTIMER_CMPRA0_CMPR1A0_Msk) | + _VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32Value & 0xFFFF) ); + + // + // Set the upper 16b (but may not be used if TIMERA) + // + ui32CmprRegB = ( (ui32CmprRegB & CTIMER_CMPRA0_CMPR1A0_Msk) | + _VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32ValB) ); + } + + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + *pui32CmprRegB = ui32CmprRegB; + } + else + { + // + // It's TIMERA or BOTH. + // + *pui32CmprRegA = ui32CmprRegA; + + if ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) + { + *pui32CmprRegB = ui32CmprRegB; + } + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_compare_set() + +//***************************************************************************** +// +//! @brief Set a compare register. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @param ui32CompareReg specifies which compare register should be set +//! (either 0 or 1) +//! +//! @param ui32Value is the value that should be written to the compare +//! register. +//! +//! This function allows the caller to set the values in the compare registers +//! for a timer. These registers control the period and duty cycle of the +//! timers and their associated output pins. Please see the datasheet for +//! further information on the operation of the compare registers. The \e +//! ui32TimerSegment parameter allows the caller to individually select a +//! segment within, such as TIMER0A, TIMER0B, or both. +//! +//! @note For simple manipulations of period or duty cycle for timers and PWMs, +//! you may find it easier to use the am_hal_ctimer_period_set() function. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_aux_compare_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32CompareReg, uint32_t ui32Value) +{ + volatile uint32_t *pui32CmprRegA, *pui32CmprRegB; + uint32_t ui32CmprRegA, ui32CmprRegB, ui32ValB; + + // + // Find the correct compare register to write. + // Assume A or BOTH. We'll change later if B. + // + pui32CmprRegA = (uint32_t *)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRAUXA0); + pui32CmprRegB = (uint32_t *)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRAUXB0); + + ui32ValB = ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) ? + ui32Value >> 16 : ui32Value & 0xFFFF; + + // + // Write the compare register with the selected value. + // Begin critical section while CMPR registers are modified. + // + AM_CRITICAL_BEGIN + + ui32CmprRegA = *pui32CmprRegA; + ui32CmprRegB = *pui32CmprRegB; + + if ( ui32CompareReg == 1 ) + { + // + // CMPR reg 1 + // Get the lower 16b (but may not be used if TIMERB). + // + ui32CmprRegA = ( (ui32CmprRegA & CTIMER_CMPRAUXA0_CMPR2A0_Msk) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32Value & 0xFFFF) ); + + // + // Get the upper 16b (but may not be used if TIMERA) + // + ui32CmprRegB = ( (ui32CmprRegB & CTIMER_CMPRAUXA0_CMPR2A0_Msk) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32ValB) ); + } + else + { + // + // CMPR reg 0 + // Get the lower 16b (but may not be used if TIMERB) + // + ui32CmprRegA = ( (ui32CmprRegA & CTIMER_CMPRAUXA0_CMPR3A0_Msk) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32Value & 0xFFFF) ); + + // + // Set the upper 16b (but may not be used if TIMERA) + // + ui32CmprRegB = ( (ui32CmprRegB & CTIMER_CMPRAUXA0_CMPR3A0_Msk) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32ValB) ); + } + + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + *pui32CmprRegB = ui32CmprRegB; + } + else + { + // + // It's TIMERA or BOTH. + // + *pui32CmprRegA = ui32CmprRegA; + + if ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) + { + *pui32CmprRegB = ui32CmprRegB; + } + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_aux_compare_set() + +//***************************************************************************** +// +//! @brief Set the period and duty cycle of a timer. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! @param ui32Period specifies the desired period. This parameter effectively +//! specifies the CTIMER CMPR field(s). The CMPR fields are handled in hardware +//! as (n+1) values, therefore ui32Period is actually specified as 1 less than +//! the desired period. Finally, as mentioned in the data sheet, the CMPR fields +//! cannot be 0 (a value of 1), so neither can ui32Period be 0. +//! +//! @param ui32OnTime set the number of clocks where the output signal is high. +//! +//! This function should be used for simple manipulations of the period and +//! duty cycle of a counter/timer. To set the period and/or duty cycle of a +//! linked timer pair, use AM_HAL_CTIMER_BOTH as the timer segment argument. If +//! you would like to set the period and/or duty cycle for both TIMERA and +//! TIMERB you will need to call this function twice: once for TIMERA, and once +//! for TIMERB. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @note The ui32OnTime parameter will only work if the timer is currently +//! operating in one of the PWM modes. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_period_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32Period, uint32_t ui32OnTime) +{ + volatile uint32_t *pui32ControlReg; + volatile uint32_t *pui32CompareRegA; + volatile uint32_t *pui32CompareRegB; + uint32_t ui32Mode, ui32Comp0, ui32Comp1; + + // + // Find the correct control register to pull the function select field + // from. + // + pui32ControlReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Find the correct compare registers to write. + // + pui32CompareRegA = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRA0); + + pui32CompareRegB = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRB0); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Extract the timer mode from the register based on the ui32TimerSegment + // selected by the user. + // + ui32Mode = *pui32ControlReg; + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32Mode = ui32Mode >> 16; + } + + // + // Mask to get to the bits we're interested in. + // + ui32Mode = ui32Mode & CTIMER_CTRL0_TMRA0FN_Msk; + + // + // If the mode is a PWM mode, we'll need to calculate the correct CMPR0 and + // CMPR1 values here. + // + if (ui32Mode == AM_HAL_CTIMER_FN_PWM_ONCE || + ui32Mode == AM_HAL_CTIMER_FN_PWM_REPEAT) + { + ui32Comp0 = ui32Period - ui32OnTime; + ui32Comp1 = ui32Period; + } + else + { + ui32Comp0 = ui32Period; + ui32Comp1 = 0; + } + + // + // Based on the timer segment argument, write the calculated Compare 0 and + // Compare 1 values to the correct halves of the correct registers. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA ) + { + // + // For timer A, write the values to the TIMERA compare register. + // + *pui32CompareRegA = (_VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32Comp1)); + } + else if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + // + // For timer B, write the values to the TIMERA compare register. + // + *pui32CompareRegB = (_VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32Comp1)); + } + else + { + // + // For the linked case, write the lower halves of the values to the + // TIMERA compare register, and the upper halves to the TIMERB compare + // register. + // + *pui32CompareRegA = (_VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32Comp1)); + + *pui32CompareRegB = (_VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32Comp0 >> 16) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32Comp1 >> 16)); + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_period_set() + +//***************************************************************************** +// +//! @brief Set the period and duty cycle of a timer. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! @param ui32Period specifies the desired period. This parameter effectively +//! specifies the CTIMER CMPR field(s). The CMPR fields are handled in hardware +//! as (n+1) values, therefore ui32Period is actually specified as 1 less than +//! the desired period. Finally, as mentioned in the data sheet, the CMPR fields +//! cannot be 0 (a value of 1), so neither can ui32Period be 0. +//! +//! @param ui32OnTime set the number of clocks where the output signal is high. +//! +//! This function should be used for simple manipulations of the period and +//! duty cycle of a counter/timer. To set the period and/or duty cycle of a +//! linked timer pair, use AM_HAL_CTIMER_BOTH as the timer segment argument. If +//! you would like to set the period and/or duty cycle for both TIMERA and +//! TIMERB you will need to call this function twice: once for TIMERA, and once +//! for TIMERB. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @note The ui32OnTime parameter will only work if the timer is currently +//! operating in one of the PWM modes. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_aux_period_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32Period, uint32_t ui32OnTime) +{ + volatile uint32_t *pui32ControlReg; + volatile uint32_t *pui32CompareRegA; + volatile uint32_t *pui32CompareRegB; + uint32_t ui32Mode, ui32Comp0, ui32Comp1; + + // + // Find the correct control register to pull the function select field + // from. + // + pui32ControlReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Find the correct compare registers to write. + // + pui32CompareRegA = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRAUXA0); + + pui32CompareRegB = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRAUXB0); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Extract the timer mode from the register based on the ui32TimerSegment + // selected by the user. + // + ui32Mode = *pui32ControlReg; + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32Mode = ui32Mode >> 16; + } + + // + // Mask to get to the bits we're interested in. + // + ui32Mode = ui32Mode & CTIMER_CTRL0_TMRA0FN_Msk; + + // + // If the mode is a PWM mode, we'll need to calculate the correct CMPR0 and + // CMPR1 values here. + // + if (ui32Mode == AM_HAL_CTIMER_FN_PWM_ONCE || + ui32Mode == AM_HAL_CTIMER_FN_PWM_REPEAT) + { + ui32Comp0 = ui32Period - ui32OnTime; + ui32Comp1 = ui32Period; + } + else + { + ui32Comp0 = ui32Period; + ui32Comp1 = 0; + } + + // + // Based on the timer segment argument, write the calculated Compare 0 and + // Compare 1 values to the correct halves of the correct registers. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA ) + { + // + // For timer A, write the values to the TIMERA compare register. + // + *pui32CompareRegA = (_VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32Comp1)); + } + else if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + // + // For timer B, write the values to the TIMERA compare register. + // + *pui32CompareRegB = (_VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32Comp1)); + } + else + { + // + // For the linked case, write the lower halves of the values to the + // TIMERA compare register, and the upper halves to the TIMERB compare + // register. + // + *pui32CompareRegA = (_VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32Comp1)); + + *pui32CompareRegB = (_VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32Comp0 >> 16) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32Comp1 >> 16)); + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_aux_period_set() + +//***************************************************************************** +// +//! @brief Enable the TIMERA3 ADC trigger +//! +//! This function enables the ADC trigger within TIMERA3. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_adc_trigger_enable(void) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Enable the ADC trigger. + // + CTIMER->CTRL3_b.ADCEN = 1; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_adc_trigger_enable() + +//***************************************************************************** +// +//! @brief Disable the TIMERA3 ADC trigger +//! +//! This function disables the ADC trigger within TIMERA3. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_adc_trigger_disable(void) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable the ADC trigger. + // + CTIMERn(0)->CTRL3 &= ~CTIMER_CTRL3_ADCEN_Msk; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_adc_trigger_disable() + +//***************************************************************************** +// +//! @brief Enables the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will enable the selected interrupts in the main CTIMER +//! interrupt enable register. In order to receive an interrupt from a timer, +//! you will need to enable the interrupt for that timer in this main register, +//! as well as in the timer control register (accessible though +//! am_hal_ctimer_config()), and in the NVIC. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_CTIMER_INT_TIMERAxCx, AM_HAL_CTIMER_INT_TIMERAxCx, +//! +//! @note The AM_HAL_CTIMER_INT_TIMER defines were re-definitions of +//! AM_REG_CTIMER_INTEN_CTMRAxCxINT_M register defines. They are +//! dropped in this release to go back to a single source definition. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_enable(uint32_t ui32Interrupt) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Enable the interrupt at the module level. + // + CTIMERn(0)->INTEN |= ui32Interrupt; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_int_enable() + +//***************************************************************************** +// +//! @brief Return the enabled timer interrupts. +//! +//! This function will return all enabled interrupts in the main CTIMER +//! interrupt enable register. +//! +//! @return return enabled interrupts. This will be a logical or of: +//! +//! AM_REG_CTIMER_INTEN_CTMRAxC0INT_M, AM_HAL_CTIMER_INT_TIMERAxC1, +//! +//! @return Return the enabled timer interrupts. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_int_enable_get(void) +{ + // + // Return enabled interrupts. + // + return CTIMERn(0)->INTEN; + +} // am_hal_ctimer_int_enable_get() + +//***************************************************************************** +// +//! @brief Disables the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will disable the selected interrupts in the main CTIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_REG_CTIMER_INTEN_CTMRAxC0INT_M, AM_HAL_CTIMER_INT_TIMERAxC1, +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_disable(uint32_t ui32Interrupt) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable the interrupt at the module level. + // + CTIMERn(0)->INTEN &= ~ui32Interrupt; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_int_disable() + +//***************************************************************************** +// +//! @brief Clears the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will clear the selected interrupts in the main CTIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_REG_CTIMER_INTEN_CTMRAxC0INT_M, AM_HAL_CTIMER_INT_TIMERAxC1, +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_clear(uint32_t ui32Interrupt) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable the interrupt at the module level. + // + CTIMERn(0)->INTCLR = ui32Interrupt; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_int_clear() + +//***************************************************************************** +// +//! @brief Sets the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will set the selected interrupts in the main CTIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_REG_CTIMER_INTEN_CTMRAxC0INT_M, AM_HAL_CTIMER_INT_TIMERAxC1, +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_set(uint32_t ui32Interrupt) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Set the interrupts. + // + CTIMERn(0)->INTSET = ui32Interrupt; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_int_set() + +//***************************************************************************** +// +//! @brief Returns either the enabled or raw timer interrupt status. +//! +//! This function will return the timer interrupt status. +//! +//! @param bEnabledOnly if true returns the status of the enabled interrupts +//! only. +//! +//! The return value will be the logical OR of one or more of the following +//! values: +//! +//! AM_REG_CTIMER_INTEN_CTMRAxC0INT_M, AM_HAL_CTIMER_INT_TIMERAxC1, +//! +//! @return u32RetVal either the timer interrupt status, or interrupt enabled. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_int_status_get(bool bEnabledOnly) +{ + uint32_t u32RetVal = 0; + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Return the desired status. + // + + if ( bEnabledOnly ) + { + u32RetVal = CTIMERn(0)->INTSTAT; + u32RetVal &= CTIMERn(0)->INTEN; + } + else + { + u32RetVal = CTIMERn(0)->INTSTAT; + } + + // + // Done with critical section. + // + AM_CRITICAL_END + + return u32RetVal; + +} // am_hal_ctimer_int_status_get() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.h new file mode 100644 index 0000000..74b5383 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.h @@ -0,0 +1,555 @@ +//***************************************************************************** +// +// am_hal_ctimer.h +//! @file +//! +//! @brief Functions for accessing and configuring the CTIMER. +//! +//! @addtogroup ctimer3 Counter/Timer (CTIMER) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_CTIMER_H +#define AM_HAL_CTIMER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Designate this peripheral. +// +#define AM_APOLLO3_CTIMER 1 + +//***************************************************************************** +// +// CTIMERADDRn() +// This is a specialized version of AM_REGADDRn(). It is necessary because +// the CTIMER does not work as a multi-module peripheral. In typical +// multi-module peripherals, the base address is defined as MODULE0_BASE. +// For CTIMER it's CTIMER_BASE (there is no module 0 defined). +// +// Usage: +// CTIMER_ADDRn(CTIMER, n, reg). +// +// periph: Must always be CTIMER. +// n: The timer number specified as a macro, variable, etc. +// reg: The register name always ending in '0'. E.g. TMR0, CTRL0, CMPRB0, +// etc (regardless of the timernum specified by 'n'). +// +//***************************************************************************** +#define CTIMERADDRn(periph, n, reg) ( periph##_BASE + \ + offsetof(periph##_Type, reg) + \ + (n * (offsetof(periph##_Type, TMR1) - offsetof(periph##_Type, TMR0))) ) + +// +// Enumerations for the eOutputType argument of am_hal_ctimer_output_config(). +// +typedef enum +{ + AM_HAL_CTIMER_OUTPUT_NORMAL = 0x0, + AM_HAL_CTIMER_OUTPUT_SECONDARY = 0x1, + AM_HAL_CTIMER_OUTPUT_FORCE0 = 0x2, + AM_HAL_CTIMER_OUTPUT_FORCE1 = 0x3 +} am_hal_ctimer_outputtype_e; + + +//***************************************************************************** +// +//! CMSIS-Style macro for handling a variable CTIMER module number. +// +//***************************************************************************** +#define CTIMERn(n) ((CTIMER_Type*)(CTIMER_BASE + (n * ((uint32_t)&CTIMER->TMR1 - (uint32_t)&CTIMER->TMR0)))) + +//***************************************************************************** +// +//! Number of timers +// +//***************************************************************************** +#define AM_HAL_CTIMER_TIMERS_NUM 8 + +//***************************************************************************** +// +//! Timer offset value +// +//***************************************************************************** +#define AM_HAL_CTIMER_TIMER_OFFSET ((uint32_t)&CTIMER->TMR1 - (uint32_t)&CTIMER->TMR0) + +//***************************************************************************** +// +//! @name Interrupt Status Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_INT_TIMERA0C0 CTIMER_INTEN_CTMRA0C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA0C1 CTIMER_INTEN_CTMRA0C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA1C0 CTIMER_INTEN_CTMRA1C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA1C1 CTIMER_INTEN_CTMRA1C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA2C0 CTIMER_INTEN_CTMRA2C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA2C1 CTIMER_INTEN_CTMRA2C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA3C0 CTIMER_INTEN_CTMRA3C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA3C1 CTIMER_INTEN_CTMRA3C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA4C0 CTIMER_INTEN_CTMRA4C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA4C1 CTIMER_INTEN_CTMRA4C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA5C0 CTIMER_INTEN_CTMRA5C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA5C1 CTIMER_INTEN_CTMRA5C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA6C0 CTIMER_INTEN_CTMRA6C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA6C1 CTIMER_INTEN_CTMRA6C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA7C0 CTIMER_INTEN_CTMRA7C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA7C1 CTIMER_INTEN_CTMRA7C1INT_Msk + +#define AM_HAL_CTIMER_INT_TIMERB0C0 CTIMER_INTEN_CTMRB0C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB0C1 CTIMER_INTEN_CTMRB0C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB1C0 CTIMER_INTEN_CTMRB1C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB1C1 CTIMER_INTEN_CTMRB1C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB2C0 CTIMER_INTEN_CTMRB2C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB2C1 CTIMER_INTEN_CTMRB2C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB3C0 CTIMER_INTEN_CTMRB3C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB3C1 CTIMER_INTEN_CTMRB3C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB4C0 CTIMER_INTEN_CTMRB4C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB4C1 CTIMER_INTEN_CTMRB4C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB5C0 CTIMER_INTEN_CTMRB5C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB5C1 CTIMER_INTEN_CTMRB5C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB6C0 CTIMER_INTEN_CTMRB6C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB6C1 CTIMER_INTEN_CTMRB6C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB7C0 CTIMER_INTEN_CTMRB7C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB7C1 CTIMER_INTEN_CTMRB7C1INT_Msk +//! @} + +//***************************************************************************** +// +// DEPRECATED Interrupt Status Bits +// +//***************************************************************************** +#define AM_HAL_CTIMER_INT_TIMERA0 AM_HAL_CTIMER_INT_TIMERA0C0 +#define AM_HAL_CTIMER_INT_TIMERB0 AM_HAL_CTIMER_INT_TIMERB0C0 +#define AM_HAL_CTIMER_INT_TIMERA1 AM_HAL_CTIMER_INT_TIMERA1C0 +#define AM_HAL_CTIMER_INT_TIMERB1 AM_HAL_CTIMER_INT_TIMERB1C0 +#define AM_HAL_CTIMER_INT_TIMERA2 AM_HAL_CTIMER_INT_TIMERA2C0 +#define AM_HAL_CTIMER_INT_TIMERB2 AM_HAL_CTIMER_INT_TIMERB2C0 +#define AM_HAL_CTIMER_INT_TIMERA3 AM_HAL_CTIMER_INT_TIMERA3C0 +#define AM_HAL_CTIMER_INT_TIMERB3 AM_HAL_CTIMER_INT_TIMERB3C0 + +//***************************************************************************** +// +//! @name Configuration options +//! @brief Configuration options for \e am_hal_ctimer_config_t +//! +//! These options are to be used with the \e am_hal_ctimer_config_t structure +//! used by \e am_hal_ctimer_config +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_CLK_PIN _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x00) +#define AM_HAL_CTIMER_HFRC_12MHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x01) +#define AM_HAL_CTIMER_HFRC_3MHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x02) +#define AM_HAL_CTIMER_HFRC_187_5KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x03) +#define AM_HAL_CTIMER_HFRC_47KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x04) +#define AM_HAL_CTIMER_HFRC_12KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x05) +#define AM_HAL_CTIMER_XT_32_768KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x06) +#define AM_HAL_CTIMER_XT_16_384KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x07) +#define AM_HAL_CTIMER_XT_2_048KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x08) +#define AM_HAL_CTIMER_XT_256HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x09) +#define AM_HAL_CTIMER_LFRC_512HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0A) +#define AM_HAL_CTIMER_LFRC_32HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0B) +#define AM_HAL_CTIMER_LFRC_1HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0C) +#define AM_HAL_CTIMER_LFRC_1_16HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0D) +#define AM_HAL_CTIMER_RTC_100HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0E) +#define AM_HAL_CTIMER_HCLK_DIV4 _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0F) +#define AM_HAL_CTIMER_XT_DIV4 _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x10) +#define AM_HAL_CTIMER_XT_DIV8 _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x11) +#define AM_HAL_CTIMER_XT_DIV32 _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x12) +#define AM_HAL_CTIMER_RSVD _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x13) +//! @} + +//***************************************************************************** +// +//! Timer function macros. +//! +//! @{ +// +//***************************************************************************** +//! Single Count: Counts one time to the compare value, then the output +//! changes polarity and stays at that level, with an optional interrupt. +#define AM_HAL_CTIMER_FN_ONCE _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 0) +//! Repeated Count: Periodic 1-clock-cycle wide pulses with optional interrupts. +#define AM_HAL_CTIMER_FN_REPEAT _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 1) +//! Single Pulse (One Shot): A single pulse of programmed width, with an optional interrupt. +#define AM_HAL_CTIMER_FN_PWM_ONCE _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 2) +//! Repeated Pulse: A rectangular (or square) waveform with programmed high and +//! low widths, and optional interrupts on each cycle. +#define AM_HAL_CTIMER_FN_PWM_REPEAT _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 3) +//! Single Pattern: one burst of bits specified by the CMPR0/1/2/3 registers. +#define AM_HAL_CTIMER_FN_PTN_ONCE _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 4) +//! Repeated Pattern: repeated burst of bits specified by the CMPR0/1/2/3 registers. +#define AM_HAL_CTIMER_FN_PTN_REPEAT _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 5) +//! Continuous: Free running timer with a single level change on the output and +//! a single optional interrupt. +#define AM_HAL_CTIMER_FN_CONTINUOUS _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 6) +//! Alternate Pulse: like Repeated Pulse but alternating between two different +//! pulse width/spacing settings. +#define AM_HAL_CTIMER_FN_PWM_ALTERNATE _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 7) +//! @} + +//***************************************************************************** +// +//! Half-timer options. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_INT_ENABLE CTIMER_CTRL0_TMRA0IE0_Msk +//#define AM_HAL_CTIMER_PIN_ENABLE CTIMER_CTRL0_TMRA0PE_Msk +#define AM_HAL_CTIMER_PIN_INVERT CTIMER_CTRL0_TMRA0POL_Msk +#define AM_HAL_CTIMER_CLEAR CTIMER_CTRL0_TMRA0CLR_Msk +//! @} + +//***************************************************************************** +// +//! Additional timer options. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_LINK CTIMER_CTRL0_CTLINK0_Msk +#define AM_HAL_CTIMER_ADC_TRIG CTIMER_CTRL3_ADCEN_Msk +//! @} + +//***************************************************************************** +// +//! Timer selection macros. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_TIMERA 0x0000FFFF +#define AM_HAL_CTIMER_TIMERB 0xFFFF0000 +#define AM_HAL_CTIMER_BOTH 0xFFFFFFFF +//! @} + +//***************************************************************************** +// +//! Timer trigger options for Apollo3 Blue (rev B0 and later) including +//! Apollo3 Blue Plus. +//! +//! Valid only for CTIMER4 and CTIMER5 when CTLINK==1 and TMRA4TRIG==1 +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP0 CTIMER_AUX4_TMRB4TRIG_A7OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP1 CTIMER_AUX4_TMRB4TRIG_B7OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP2 CTIMER_AUX4_TMRB4TRIG_A1OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP3 CTIMER_AUX4_TMRB4TRIG_B1OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP0 CTIMER_AUX4_TMRB4TRIG_B3OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP1 CTIMER_AUX4_TMRB4TRIG_A3OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP2 CTIMER_AUX4_TMRB4TRIG_A1OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP3 CTIMER_AUX4_TMRB4TRIG_B1OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP4 CTIMER_AUX4_TMRB4TRIG_A6OUT2DUAL +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP5 CTIMER_AUX4_TMRB4TRIG_A7OUT2DUAL +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP6 CTIMER_AUX4_TMRB4TRIG_B5OUT2DUAL +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP7 CTIMER_AUX4_TMRB4TRIG_A5OUT2DUAL + +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP0 CTIMER_AUX5_TMRB5TRIG_A7OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP1 CTIMER_AUX5_TMRB5TRIG_B7OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP2 CTIMER_AUX5_TMRB5TRIG_A1OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP3 CTIMER_AUX5_TMRB5TRIG_B1OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP0 CTIMER_AUX5_TMRB5TRIG_B3OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP1 CTIMER_AUX5_TMRB5TRIG_A3OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP2 CTIMER_AUX5_TMRB5TRIG_A1OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP3 CTIMER_AUX5_TMRB5TRIG_B1OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP4 CTIMER_AUX5_TMRB5TRIG_A6OUT2DUAL +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP5 CTIMER_AUX5_TMRB5TRIG_A7OUT2DUAL +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP6 CTIMER_AUX5_TMRB5TRIG_B5OUT2DUAL +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP7 CTIMER_AUX5_TMRB5TRIG_A5OUT2DUAL +//! @} + +//***************************************************************************** +// +//! @name All-In-One Configuration +//! @brief New API for multiple timer configuration. +//! +//! These options are to be used with the \e am_hal_ctimer_config_t structure +//! used by \e am_hal_ctimer_config +//! @{ +// +//***************************************************************************** +//! CTimer AIO Compare Configuration. +typedef struct +{ + // + //! Function Number. + // + uint32_t FN; + // + //! Timer Segment. Timer A, B, BOTH selector. + // + uint32_t AB; + // + //! Compare Register A0. + // + uint32_t A0; + // + //! Compare Register A1. + // + uint32_t A1; + // + //! Compare Register A2. + // + uint32_t A2; + // + //! Compare Register A3. + // + uint32_t A3; + // + //! Compare Register B0. + // + uint32_t B0; + // + //! Compare Register B1. + // + uint32_t B1; + // + //! Compare Register B2. + // + uint32_t B2; + // + //! Compare Register B3. + // + uint32_t B3; + // + //! LMT field values. + // + uint32_t LMT; + // + //! A "T" indicates that a 1 is loaded if the OUT2 output is used, otherwise a 0 is loaded. + // + uint32_t EN23; + // + //! TRIG: a single pattern will be triggered; TERM: a repeated pattern will be terminated. + // + uint32_t TRIG; + // + //! Select clock source: internal, external, a buck pulse, or output of another CTIMER. + // + uint32_t CLK; + // + //! Enable the primary interrupt INT. + // + uint32_t IE0; + // + //! Enable the secondary interrupt INT2. + // + uint32_t IE1; + // + //! Select the polarity of the OUT output. + // + uint32_t POL; + // + //! Select the polarity of the OUT2 output. + // + uint32_t POL23; + // + //! Select polarity of both OUT and OUT2 as a function of the trigger input. + // + uint32_t TINV; + // + //! Disable clock synchronization on read. + // + uint32_t NOSYNC; + // + //! Enable the timer. + // This is ANDed with the global enable in GLOBEN, and allows the counter to begin counting. + // + uint32_t EN; + // + // Clear the timer. This will hold the timer at zero even if EN is asserted. + // It is typically cleared at the end of a configuration and + // is probably not included in the function structure. + // + //uint32_t CLR; + +} +am_hal_ctimer_aio_config_t; + +//! CTimer AIO Output Selection and Interconnect. +typedef struct +{ + //! Pad 0-9 + uint32_t OUTCFG0; + //! Pad 10-19 + uint32_t OUTCFG1; + //! Pad 20-29 + uint32_t OUTCFG2; + //! Pad 30-31 + uint32_t OUTCFG3; +} +am_hal_ctimer_aio_connect_t; +//! @} + +//***************************************************************************** +// +//! Timer configuration structure +// +//***************************************************************************** +typedef struct +{ + // + //! Set to 1 to operate this timer as a 32-bit timer instead of two 16-bit + //! timers. + // + uint32_t ui32Link; + + // + //! Configuration options for TIMERA + // + uint32_t ui32TimerAConfig; + + // + //! Configuration options for TIMERB + // + uint32_t ui32TimerBConfig; + +} +am_hal_ctimer_config_t; + +//***************************************************************************** +// +//! Function pointer type for CTimer interrupt handlers. +// +//***************************************************************************** +typedef void (*am_hal_ctimer_handler_t)(void); + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_ctimer_globen(uint32_t ui32ConfigVal); + +extern void am_hal_ctimer_config(uint32_t ui32TimerNumber, + am_hal_ctimer_config_t *psConfig); + +extern void am_hal_ctimer_config_single(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32ConfigVal); + +extern void am_hal_ctimer_config_trigger(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32ConfigVal); + +extern void am_hal_ctimer_start(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern void am_hal_ctimer_stop(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern void am_hal_ctimer_clear(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern uint32_t am_hal_ctimer_read(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern uint32_t am_hal_ctimer_output_config(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32PadNum, + uint32_t eOutputType, + uint32_t eDriveStrength); + +extern void am_hal_ctimer_input_config(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32TimerOutputConfig); + +extern void am_hal_ctimer_compare_set(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32CompareReg, + uint32_t ui32Value); + +extern void am_hal_ctimer_aux_compare_set(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32CompareReg, + uint32_t ui32Value); + +extern void am_hal_ctimer_period_set(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32Period, + uint32_t ui32OnTime); + +extern void am_hal_ctimer_aux_period_set(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32Period, + uint32_t ui32OnTime); + +extern void am_hal_ctimer_adc_trigger_enable(void); +extern void am_hal_ctimer_adc_trigger_disable(void); +extern void am_hal_ctimer_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_ctimer_int_enable_get(void); +extern void am_hal_ctimer_int_disable(uint32_t ui32Interrupt); +extern void am_hal_ctimer_int_set(uint32_t ui32Interrupt); +extern void am_hal_ctimer_int_clear(uint32_t ui32Interrupt); +extern uint32_t am_hal_ctimer_int_status_get(bool bEnabledOnly); +extern void am_hal_ctimer_int_register(uint32_t ui32Interrupt, + am_hal_ctimer_handler_t pfnHandler); +extern void am_hal_ctimer_int_service(uint32_t ui32Status); + +// +// General function to do triple back-to-back reads. +// +extern void am_hal_triple_read(uint32_t u32TimerAddr, uint32_t ui32Data[]); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CTIMER_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.c new file mode 100644 index 0000000..e112781 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.c @@ -0,0 +1,96 @@ +//***************************************************************************** +// +// am_hal_debug.c +//! @file +//! +//! @brief Useful functions for debugging. +//! +//! These functions and macros were created to assist with debugging. They are +//! intended to be as unintrusive as possible and designed to be removed from +//! the compilation of a project when they are no longer needed. +//! +//! @addtogroup haldebug3 HAL Debug/Assert Utilities +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Default implementation of a failed ASSERT statement. +//! +//! @param pcFile is the name of the source file where the error occurred. +//! @param ui32Line is the line number where the error occurred. +//! @param pcMessage is an optional message describing the failure. +//! +//! This function is called by am_hal_debug_assert() macro when the supplied +//! condition is not true. The implementation here simply halts the application +//! for further analysis. Individual applications may define their own +//! implementations of am_hal_debug_error() to provide more detailed feedback +//! about the failed am_hal_debug_assert() statement. +//! +//! @return Never. +// +//***************************************************************************** +#if defined (__IAR_SYSTEMS_ICC__) +__weak void +#else +void __attribute__((weak)) +#endif +am_hal_debug_error(const char *pcFile, uint32_t ui32Line, const char *pcMessage) +{ + // + // Halt for analysis. + // + while(1); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.h new file mode 100644 index 0000000..dfc4a86 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.h @@ -0,0 +1,141 @@ +//***************************************************************************** +// +// am_hal_debug.h +//! @file +//! +//! @brief Useful macros for debugging. +//! +//! These functions and macros were created to assist with debugging. They are +//! intended to be as unintrusive as possible and designed to be removed from +//! the compilation of a project when they are no longer needed. +//! +//! @addtogroup haldebug3 HAL Debug/Assert Utilities +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_DEBUG_H +#define AM_HAL_DEBUG_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +// Determine DBG_FILENAME +// +//***************************************************************************** +// +// By spec and convention, the standard __FILE__ compiler macro includes a full +// path (absolute or relative) to the file being compiled. This makes recreating +// binaries virtually impossible unless rebuilt on the same or identically +// configured system. +// +// To be able to build consistent binaries on different systems, we want to make +// sure the full pathname is not included in the binary. Only IAR EWARM provides +// an easy mechanism to provide only the filename without the path. For other +// platforms, we will simply use a generic pathname. +// +#if defined (__IAR_SYSTEMS_ICC__) +// +// With EWARM the --no_path_in_file_macros option reduces __FILE__ to only the +// module name. Therefore this define assumes the option is being used. +// +#define DBG_FILENAME __FILE__ +#elif defined(__KEIL__) +// +// Keil provides __MODULE__ which is simply the module name portion of __FILE__. +// +#define DBG_FILENAME __MODULE__ +#elif defined(__ARMCC_VERSION) +#define DBG_FILENAME __FILE__ +#else +// +// With GCC, we're out of luck. +// +#define DBG_FILENAME "debug_filename.ext" +//#define DBG_FILENAME __FILE__ +#endif + +//***************************************************************************** +// +// Debug assert macros. +// +//***************************************************************************** +#ifndef AM_HAL_DEBUG_NO_ASSERT + +#define am_hal_debug_assert_msg(bCondition, pcMessage) \ + if ( !(bCondition)) am_hal_debug_error(DBG_FILENAME, __LINE__, pcMessage) + +#define am_hal_debug_assert(bCondition) \ + if ( !(bCondition)) am_hal_debug_error(DBG_FILENAME, __LINE__, 0) + +#else + +#define am_hal_debug_assert_msg(bCondition, pcMessage) +#define am_hal_debug_assert(bCondition) + +#endif // AM_DEBUG_ASSERT + +//***************************************************************************** +// +// External function prototypes. +// +//***************************************************************************** +extern void am_hal_debug_error(const char *pcFile, uint32_t ui32Line, + const char *pcMessage); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_DEBUG_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.c new file mode 100644 index 0000000..ed9d945 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.c @@ -0,0 +1,1883 @@ +//***************************************************************************** +// +// am_hal_flash.c +//! @file +//! +//! @brief Functions for performing Flash operations. +//! +//! IMPORTANT: Interrupts are active during execution of all HAL flash +//! functions. If an interrupt occurs during execution of a flash function +//! that programs or erases flash or INFO space, errors will occur if the +//! interrupt service routine (ISR) is located in on-chip flash. +//! If interrupts are expected during execution of a flash function that +//! programs or erases either flash or INFO space: +//! - Interrupts must be disabled via a critical section handler prior to +//! calling the flash function. +//! - Alternatively, applicable ISRs must be located in non-flash address space +//! (i.e. SRAM, off-chip ROM, etc.). +//! +//! @addtogroup flash3 Flash +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +// +// Look-up table +// +const g_am_hal_flash_t g_am_hal_flash = +{ + ((int (*)(uint32_t, uint32_t)) 0x0800004d), // flash_mass_erase + ((int (*)(uint32_t, uint32_t, uint32_t)) 0x08000051), // flash_page_erase + ((int (*)(uint32_t, uint32_t *, uint32_t *, uint32_t)) 0x08000055), // flash_program_main + ((int (*)(uint32_t, uint32_t, uint32_t *, uint32_t, uint32_t))0x08000059), // flash_program_info_area + ((int (*)(uint32_t, uint32_t)) 0x0800006d), // flash_mass_erase_nb + ((int (*)(uint32_t, uint32_t, uint32_t)) 0x08000071), // flash_page_erase_nb + ((int (*)( uint32_t, uint32_t)) 0x08000095), // flash_page_erase2_nb + ((bool (*)(void)) 0x0800007d), // flash_nb_operation_complete + ((uint32_t (*)(uint32_t *)) 0x08000075), // flash_util_read_word + ((void (*)( uint32_t *, uint32_t)) 0x08000079), // flash_util_write_word + ((void (*)(uint32_t )) 0x0800009D), // bootrom_delay_cycles + ((int (*)( uint32_t, uint32_t)) 0x08000081), // flash_info_erase + ((int (*)( uint32_t, uint32_t)) 0x08000089), // flash_info_plus_main_erase + ((int (*)(uint32_t)) 0x08000091), // flash_info_plus_main_erase_both + ((int (*)( uint32_t )) 0x08000099), // flash_recovery + ((void (*)(void)) 0x0800005d), // flash_program_main_from_sram + ((void (*)(void)) 0x08000061), // flash_program_info_area_from_sram + ((void (*)(void)) 0x08000065), // flash_erase_main_pages_from_sram + ((void (*)(void)) 0x08000069), // flash_mass_erase_from_sram + ((void (*)(void)) 0x08000085), // flash_info_erase_from_sram + ((void (*)(void)) 0x0800008D), // flash_info_plus_main_erase_from_sram + ((void (*)(void)) 0x080000A1), // flash_nb_operation_complete_from_sram + ((void (*)(void)) 0x080000A5), // flash_page_erase2_nb_from_sram + ((void (*)(void)) 0x080000A9) // flash_recovery_from_sram +}; + +const uint32_t ui32SramMaxAddr = (AM_HAL_FLASH_SRAM_LARGEST_VALID_ADDR + 1); +//***************************************************************************** +// +//! @brief This function performs a mass erase on a flash instance. +//! +//! @param ui32ProgramKey - The flash program key. +//! @param ui32FlashInst - The flash instance to erase. +//! +//! This function will erase the desired instance of flash. +//! +//! @note For Apollo3, each flash instance contains a maximum of 512KB. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32ProgramKey is invalid. +//! 2 ui32FlashInst is invalid. +//! 3 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_mass_erase(uint32_t ui32ProgramKey, uint32_t ui32FlashInst) +{ + return g_am_hal_flash.flash_mass_erase(ui32ProgramKey, ui32FlashInst); +} // am_hal_flash_mass_erase() + +//***************************************************************************** +// +//! @brief This function performs a page erase on a flash instance. +//! +//! @param ui32ProgramKey - The flash program key. +//! @param ui32FlashInst - The flash instance to reference the page number with. +//! @param ui32PageNum - The flash page relative to the specified instance. +//! +//! This function will erase the desired flash page in the desired instance of +//! flash. +//! +//! @note For Apollo3, each flash page is 8KB (or AM_HAL_FLASH_PAGE_SIZE). +//! Each flash instance contains a maximum of 64 pages (or +//! AM_HAL_FLASH_INSTANCE_PAGES). +//! +//! @note When given an absolute flash address, a couple of helpful macros can +//! be utilized when calling this function. +//! For example: +//! am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, +//! AM_HAL_FLASH_ADDR2INST(ui32Addr), +//! AM_HAL_FLASH_ADDR2PAGE(ui32Addr) ); +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32ProgramKey is invalid. +//! 2 ui32FlashInst is invalid. +//! 3 ui32PageNum is invalid. +//! 4 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_page_erase(uint32_t ui32ProgramKey, uint32_t ui32FlashInst, + uint32_t ui32PageNum) +{ + return g_am_hal_flash.flash_page_erase(ui32ProgramKey, + ui32FlashInst, + ui32PageNum); +} // am_hal_flash_page_erase() + +//***************************************************************************** +// +//! @brief This programs up to N words of the Main array on one flash instance. +//! +//! @param ui32ProgramKey - The programming key, AM_HAL_FLASH_PROGRAM_KEY. +//! @param pui32Src - Pointer to word aligned array of data to program into +//! the flash instance. +//! @param pui32Dst - Pointer to the word aligned flash location where +//! programming of the flash instance is to begin. +//! @param ui32NumWords - The number of words to be programmed. +//! +//! This function will program multiple words in main flash. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32ProgramKey is invalid. +//! 2 pui32Dst is invalid. +//! 3 Flash addressing range would be exceeded. That is, (pui32Dst + +//! (ui32NumWords * 4)) is greater than the last valid address. +//! 4 pui32Src is invalid. +//! 5 Unused - will never be returned. +//! 6 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_program_main(uint32_t ui32ProgramKey, uint32_t *pui32Src, + uint32_t *pui32Dst, uint32_t ui32NumWords) +{ + uint32_t ui32MaxSrcAddr = (uint32_t)pui32Src + (ui32NumWords << 2); + + // + // Workaround, the last word of SRAM cannot be the source + // of programming by BootRom, check to see if it is the last + // + if ( ui32MaxSrcAddr == ui32SramMaxAddr ) + { + uint32_t ui32Temp; + int iRetVal; + + // + // program the other words using the boot-rom function + // + if ( ui32NumWords > 1 ) + { + iRetVal = g_am_hal_flash.flash_program_main( + ui32ProgramKey, + pui32Src, + pui32Dst, + ui32NumWords - 1); + + // + // return if anything wrong + // + if ( iRetVal != 0 ) + { + return iRetVal; + } + } + + // + // program the last word of the pSrc from a local + // variable if it is the last word of SRAM + // + ui32Temp = *(uint32_t *)(ui32MaxSrcAddr - 4); + + return g_am_hal_flash.flash_program_main( + ui32ProgramKey, + &ui32Temp, + pui32Dst + ui32NumWords - 1, + 1); + } + + return g_am_hal_flash.flash_program_main(ui32ProgramKey, pui32Src, + pui32Dst, ui32NumWords); +} // am_hal_flash_program_main() + + +//***************************************************************************** +// +//! @brief This clears the specified bits in the addressed flash word +//! +//! @param ui32ProgramKey - The programming key, AM_HAL_FLASH_PROGRAM_KEY. +//! @param pui32Addr - Pointer to word aligned flash word to program into +//! @param ui32BitMask - The bits to be cleared +//! +//! This function will clear one of more bits in a word in main flash. +//! This function is mainly used when the same word is to be written multiple times +//! few bits at a time, between erase cycle +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @note We can reprogram a bit in flash to 0 only once. This function takes +//! care of not re-clearing bits if they are already programmed as 0 +//! +//! @return 0 for success, non-zero for failure. +//! +//! Note: See am_hal_flash_program_main() for further details on return codes. +// +//***************************************************************************** +int +am_hal_flash_clear_bits(uint32_t ui32ProgramKey, uint32_t *pui32Addr, + uint32_t ui32BitMask) +{ + uint32_t ui32Val = ~ui32BitMask; + + // + // CAUTION: We can reprogram a bit in flash to 0 only once...so make sure + // that we do not re-clear bits + // + ui32Val |= ~(*pui32Addr); + + return g_am_hal_flash.flash_program_main(ui32ProgramKey, &ui32Val, + pui32Addr, 1); +} // am_hal_flash_clear_bits() + +//***************************************************************************** +// +//! @brief This function programs multiple words in the customer INFO space. +//! +//! @param ui32InfoKey - The customer INFO space key. +//! @param ui32InfoInst - The INFO space instance, 0 or 1. +//! @param *pui32Src - Pointer to word aligned array of data to program into +//! the customer INFO space. +//! @param ui32Offset - Word offset into customer INFO space (offset of 0 is +//! the first word, 1 is second word, etc.). +//! @param ui32NumWords - The number of words to be programmed, must not +//! exceed AM_HAL_FLASH_INFO_SIZE/4. +//! +//! This function will program multiple words in the customer INFO space. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid. +//! 2 ui32InfoInst is invalid. +//! 3 ui32Offset is invalid. +//! 4 INFO addressing range would be exceeded. That is, (ui32Offset + +//! ui32NumWords) is greater than the last valid address. +//! 5 pui32Src is invalid. +//! 6 pui32Src is invalid. +//! 7 Hardware error. +//! 8 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_program_info(uint32_t ui32InfoKey, uint32_t ui32InfoInst, + uint32_t *pui32Src, uint32_t ui32Offset, + uint32_t ui32NumWords) +{ + uint32_t ui32MaxSrcAddr = (uint32_t)pui32Src + (ui32NumWords << 2); + + // + // workround, the last word of SRAM cannot be the source + // of programming by BootRom, check to see if it is the last + // + if ( ui32MaxSrcAddr == ui32SramMaxAddr ) + { + uint32_t ui32Temp; + int iRetVal; + + // + // program the other words using the boot-rom function + // + if ( ui32NumWords > 1 ) + { + iRetVal = g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + ui32InfoInst, + pui32Src, + ui32Offset, + ui32NumWords - 1); + + // + // return if anything wrong + // + if ( iRetVal != 0 ) + { + return iRetVal; + } + } + + // + // program the last word of the pSrc from a local + // variable if it is the last word of SRAM + // + ui32Temp = *(uint32_t *)(ui32MaxSrcAddr - 4); + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + ui32InfoInst, + &ui32Temp, + ui32Offset + ui32NumWords - 1, + 1); + } + + return g_am_hal_flash.flash_program_info_area(ui32InfoKey, ui32InfoInst, pui32Src, + ui32Offset, ui32NumWords); + +} // am_hal_flash_program_info() + +//***************************************************************************** +// +//! @brief This function erases an instance of the customer INFO space. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! (AM_HAL_FLASH_INFO_KEY). +//! @param ui32Inst - The flash instance, either 0 or 1. +//! +//! This function will erase the the customer INFO space of the specified +//! instance. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid. +//! 2 ui32Inst is invalid. +//! 3 Hardware error. +//! 4 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_erase_info(uint32_t ui32InfoKey, + uint32_t ui32Inst) +{ + return g_am_hal_flash.flash_info_erase(ui32InfoKey, ui32Inst); +} // am_hal_flash_erase_info() + +//***************************************************************************** +// +//! @brief This function erases the main instance + the customer INFO space. +//! +//! @param ui32InfoKey - The customer INFO space key. +//! @param ui32Inst - The flash instance, either 0 or 1. +//! +//! This function will erase the main flash + the customer INFO space of the +//! specified instance. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid. +//! 2 ui32Inst is invalid. +//! 3 Hardware error. +//! 4 Flash controller hardware timeout. +//! 11 Internal error. +//! 12 Internal error. +//! 13 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_erase_main_plus_info(uint32_t ui32InfoKey, + uint32_t ui32Inst) +{ + return g_am_hal_flash.flash_info_plus_main_erase(ui32InfoKey, + ui32Inst); +} // am_hal_flash_erase_main_plus_info() + +//***************************************************************************** +// +//! @brief This function erases the main flash + the customer INFO space. +//! +//! @param ui32InfoKey - The customer INFO space key. +//! +//! This function will erase both instances the main flash + the +//! customer INFO space. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid, instance 0. +//! 2 Internal error, instance 0. +//! 3 Hardware error, instance 0. +//! 4 Flash controller hardware timeout, instance 0. +//! 11 Internal error. +//! 12 Internal error. +//! 13 Flash controller hardware timeout. +//! 21 ui32InfoKey is invalid, instance 1. +//! 22 Internal error, instance 1. +//! 23 Hardware error, instance 1. +//! 24 Flash controller hardware timeout, instance 1. +//! 31 Internal error, instance 1. +//! 32 Internal error, instance 1. +//! 33 Flash controller hardware timeout, instance 1. +// +//***************************************************************************** +int +am_hal_flash_erase_main_plus_info_both_instances(uint32_t ui32InfoKey) +{ + return g_am_hal_flash.flash_info_plus_main_erase_both(ui32InfoKey); +} // am_hal_flash_erase_main_plus_info_both_instances() + +//***************************************************************************** +// +//! @brief This function erases both main flash instances + both customer INFO +//! space instances. +//! +//! @param ui32RecoveryKey - The recovery key. +//! +//! This function erases both main instances and both customer INFOinstances +//! even if the customer INFO space is programmed to not be erasable. This +//! function completely erases the flash main and info instances and wipes the +//! SRAM. Upon completion of the erasure operations, it does a POI (power on +//! initialization) reset. +//! +//! @note The customer key lock is enforced by this function. Therefore, the +//! customer key must be written prior to calling otherwise, the function will +//! fail. Therefore, always check for a return code. If the function returns, +//! a failure has occured. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Does not return if successful. Returns failure code otherwise. +//! Failing return code indicates: +//! 0x00000001 ui32RecoveryKey is invalid. +//! 0x00000002 Customer key lock not set. +//! 0x00001001 Internal error. +//! 0x00001002 Internal error. +//! 0x00001003 Info erase, instance 0 - hardware error. +//! 0x00001004 Info erase, instance 0 - flash controller hardware timeout. +//! 0xi000ppee Error erasing page in instance, pp=page number, ee=error code. +//! i=2|3, instance 0. +//! i=4|5, instance 1. +//! ee=1|2|3 Internal or hardware error. +//! ee=4 Flash controller hardware timeout. +// +//***************************************************************************** +void +am_hal_flash_recovery(uint32_t ui32RecoveryKey) +{ + g_am_hal_flash.flash_recovery(ui32RecoveryKey); +} // am_hal_flash_recovery() + +//***************************************************************************** +// +//! @brief Use the bootrom to implement a spin loop. +//! +//! @param ui32Iterations - Number of iterations to delay. +//! +//! Use this function to implement a CPU busy waiting spin loop without cache +//! or delay uncertainties. +//! +//! Notes for Apollo3: +//! - The ROM-based function executes at 3 cycles per iteration plus the normal +//! function call, entry, and exit overhead and latencies. +//! - Cache settings affect call overhead. However, the cache does not affect +//! the time while inside the BOOTROM function. +//! - The function accounts for burst vs normal mode, along with some of the +//! overhead encountered with executing the function itself (such as the +//! check for burst mode). +//! - Use of the FLASH_CYCLES_US() or FLASH_CYCLES_US_NOCACHE() macros for the +//! ui32Iterations parameter will result in approximate microsecond timing. +//! - The parameter ui32Iterations==0 is allowed but is still incurs a delay. +//! +//! Example: +//! - MCU operating at 48MHz -> 20.83 ns / cycle +//! - Therefore each iteration (once inside the bootrom function) will consume +//! 62.5ns (non-burst-mode). +//! +//! @note Interrupts are not disabled during execution of this function. +//! Therefore, any interrupt taken will affect the delay timing. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_flash_delay(uint32_t ui32Iterations) +{ + // + // The read of the FREQCTRL register in order to check for burst mode + // could take up to 13 cycles, and almost double if in burst mode. + // There are also overhead delays encountered in this function, such + // as computing the cycle count adjustment itself. + // Let's account for these delays as much as possible. + // + register uint32_t ui32CycleCntAdj; + + if ( am_hal_burst_mode_status() == AM_HAL_BURST_MODE ) + { + ui32Iterations <<= 1; + + // + // There's an additional shift to account for. + // + ui32CycleCntAdj = ((13 * 2) + 16) / 3; + } + else + { + ui32CycleCntAdj = ((13 * 1) + 20) / 3; + } + + // + // Allow for the overhead of the burst-mode check and these comparisons + // by eliminating an appropriate number of iterations. + // + if ( ui32Iterations > ui32CycleCntAdj ) + { + ui32Iterations -= ui32CycleCntAdj; + + g_am_hal_flash.bootrom_delay_cycles(ui32Iterations); + } + +} // am_hal_flash_delay() + +//***************************************************************************** +// +//! @brief Delays for a desired amount of cycles while also waiting for a +//! status to change a value. +//! +//! @param ui32usMaxDelay - Maximum number of ~1uS delay loops. +//! @param ui32Address - Address of the register for the status change. +//! @param ui32Mask - Mask for the status change. +//! @param ui32Value - Target value for the status change. +//! +//! This function will delay for approximately the given number of microseconds +//! while checking for a status change, exiting when either the given time has +//! expired or the status change is detected. +//! +//! @returns 0 = timeout. +//! 1 = status change detected. +// +//***************************************************************************** +uint32_t +am_hal_flash_delay_status_change(uint32_t ui32usMaxDelay, uint32_t ui32Address, + uint32_t ui32Mask, uint32_t ui32Value) +{ + while ( 1 ) + { + // + // Check the status + // + if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) + { + return AM_HAL_STATUS_SUCCESS; + } + + if ( ui32usMaxDelay-- ) + { + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + break; + } + } + + return AM_HAL_STATUS_TIMEOUT; + +} // am_hal_flash_delay_status_change() + +//***************************************************************************** +// +//! @brief Delays for a desired amount of cycles while also waiting for a +//! status to equal OR not-equal to a value. +//! +//! @param ui32usMaxDelay - Maximum number of ~1uS delay loops. +//! @param ui32Address - Address of the register for the status change. +//! @param ui32Mask - Mask for the status change. +//! @param ui32Value - Target value for the status change. +//! @param bIsEqual - Check for equal if true; not-equal if false. +//! +//! This function will delay for approximately the given number of microseconds +//! while checking for a status change, exiting when either the given time has +//! expired or the status change is detected. +//! +//! @returns 0 = timeout. +//! 1 = status change detected. +// +//***************************************************************************** +uint32_t +am_hal_flash_delay_status_check(uint32_t ui32usMaxDelay, uint32_t ui32Address, + uint32_t ui32Mask, uint32_t ui32Value, + bool bIsEqual) +{ + while ( 1 ) + { + // + // Check the status + // + if ( bIsEqual ) + { + if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) + { + return AM_HAL_STATUS_SUCCESS; + } + } + else + { + if ( ( AM_REGVAL(ui32Address) & ui32Mask ) != ui32Value ) + { + return AM_HAL_STATUS_SUCCESS; + } + } + + if ( ui32usMaxDelay-- ) + { + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + break; + } + } + + return AM_HAL_STATUS_TIMEOUT; + +} // am_hal_flash_delay_status_check() + +//***************************************************************************** +// +//! @brief Static Helper Function to check customer info valid bits erasure. +//! +//! Use this function to test the state of the 128 valid bits at the beginning +//! of customer info space. If these are all erased then return true. +//! +//! @return true if the customer info bits are currently erased. +// +//***************************************************************************** +static bool +customer_info_signature_erased(void) +{ + uint32_t *pui32Signature = (uint32_t *) AM_HAL_FLASH_INFO_ADDR; + + return ( (pui32Signature[3] == 0xFFFFFFFF) && + (pui32Signature[2] == 0xFFFFFFFF) && + (pui32Signature[1] == 0xFFFFFFFF) && + (pui32Signature[0] == 0xFFFFFFFF) ) ? true : false; + +} // customer_info_signature_erased() + +//***************************************************************************** +// +//! @brief Static Helper Function to set customer info valid bits +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space. If these bits are not set correctly then the +//! customer protection bits in the INFO space will not be honored by the +//! hardware. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +static int +customer_info_signature_set(uint32_t ui32InfoKey) +{ + uint32_t ui32Valid[4]; + int iRC; + + // + // If they are already set then we are done. + // + if ( am_hal_flash_customer_info_signature_check() ) + { + return 0; + } + + // + // If they are not erased at this point we have an error. + // + if ( !customer_info_signature_erased() ) + { + return (2 << 16); + } + + // + // OK they need to be set so do it. + // + ui32Valid[3] = AM_HAL_FLASH_INFO_SIGNATURE3; + ui32Valid[2] = AM_HAL_FLASH_INFO_SIGNATURE2; + ui32Valid[1] = AM_HAL_FLASH_INFO_SIGNATURE1; + ui32Valid[0] = AM_HAL_FLASH_INFO_SIGNATURE0; + + iRC = g_am_hal_flash.flash_program_info_area(ui32InfoKey, + 0, // instance + ui32Valid, // source data + 0, // offset + 4); // number of words + + // + // See am_hal_flash_program_info() for further details on return codes. + // + return iRC | ((iRC) ? (1 << 16) : 0); + +} // customer_info_signature_set() + +//***************************************************************************** +// +//! @brief Check that the customer info bits are valid. +//! +//! Use this function to test the state of the 128 valid bits at the beginning +//! of customer info space. If these are not set correctly then the customer +//! protection bits in the INFO space will not be honored by the hardware. +//! +//! @return true if valid. +// +//***************************************************************************** +bool +am_hal_flash_customer_info_signature_check(void) +{ + uint32_t *pui32Signature = (uint32_t *)AM_HAL_FLASH_INFO_ADDR; + + return ( (pui32Signature[3] == AM_HAL_FLASH_INFO_SIGNATURE3) && + (pui32Signature[2] == AM_HAL_FLASH_INFO_SIGNATURE2) && + (pui32Signature[1] == AM_HAL_FLASH_INFO_SIGNATURE1) && + (pui32Signature[0] == AM_HAL_FLASH_INFO_SIGNATURE0) ); + +} // am_hal_flash_customer_info_signature_check() + +//***************************************************************************** +// +//! @brief INFO signature set. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +bool +am_hal_flash_info_signature_set(uint32_t ui32InfoKey) +{ + // + // Check and set signature. + // + return customer_info_signature_set(ui32InfoKey) ? false : true; + +} // am_hal_flash_info_signature_set() + +//***************************************************************************** +// +//! @brief Disable FLASH INFO space. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then disable FLASH erasure. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_info_erase_disable(uint32_t ui32InfoKey) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Clear bit in INFO space to disable erasure. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_info_erase_disable() + +//***************************************************************************** +// +//! @brief Check for Disabled FLASH INFO space. +//! +//! Use this function to determine whether FLASH INFO erasure is disabled. +//! +//! @return true if FLASH INFO erase is disabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_info_erase_disable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not valid at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the SRAM WIPE bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M ? false : true; + +} // am_hal_flash_info_erase_disable_check() + +//***************************************************************************** +// +//! @brief Mask off 1 to 4 quadrants of FLASH INFO space for programming. +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then and the mask bits with the INFO +//! space programming disable bits. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! @param ui32Mask - A mask of the 4 quadrants of info space where +//! bit0 = First quadrant (first 2KB). +//! bit1 = Second quadrant (second 2KB). +//! bit2 = Third quadrant (third 2KB). +//! bit3 = Fourth quadrant (fourth 2KB). +//! +//! @note This function disables only, any quadrant already disabled is not +//! reenabled. That is, any ui32Mask bits specified as 0 are essentially nops. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_info_program_disable(uint32_t ui32InfoKey, uint32_t ui32Mask) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Make sure we have a valid mask and get the mask into the correct position. + // + ui32Mask <<= AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S; + ui32Mask &= AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M; + + // + // The security bit set to 1 enables programming, 0 disables programming. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & ~ui32Mask; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_info_program_disable() + +//***************************************************************************** +// +//! @brief Return a mask specifying which quadrants of customer INFO space have +//! been disabled for programming. +//! +//! Use this function to determine whether programming of customer INFO space +//! has been disabled. +//! +//! @return A 4-bit mask of the disabled quadrants. +//! 0xFFFFFFFF indicates an error. +//! 0x0 indicates all customer INFO space programming is enabled. +//! 0xF indicates all customer INFO space programming is disabled. +//! bit0 indicates the first customer INFO space is disabled for programming. +//! bit1 indicates the second customer INFO space is disabled for programming. +//! bit2 indicates the third customer INFO space is disabled for programming. +//! bit3 indicates the fourth customer INFO space is disabled for programming. +// +//***************************************************************************** +uint32_t +am_hal_flash_info_program_disable_get(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return 0xFFFFFFFF; + } + + // + // If not valid at this point, then INFO programming can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return 0xFFFFFFFF; + } + + // + // Looking good so far, now return a mask of the disabled bits. + // + return ((AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M) ^ + AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M) >> + AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S; + +} // am_hal_flash_info_program_disable_get() + +//***************************************************************************** +// +//! @brief Enable FLASH debugger protection (FLASH gets wiped if a debugger is +//! connected). +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then set the FLASH wipe bit to zero. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_wipe_flash_enable(uint32_t ui32InfoKey) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Clear the FLASH Wipe bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_wipe_flash_enable() + +//***************************************************************************** +// +//! @brief check for FLASH wipe protection enabled. +//! +//! Use this function to determine if FLASH wipe protection is enabled. +//! +//! @return true if FLASH wipe protection is enabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_wipe_flash_enable_check(void) +{ + // + // If they are erased at this point then flash wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not valid at this point then flash wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the Flash WIPE bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M ? false : true; + +} // am_hal_flash_wipe_flash_enable_check() + +//***************************************************************************** +// +//! @brief Enable SRAM protection so SRAM gets wiped if a debgger is connected. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then set the SRAM wipe bit to zero. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_wipe_sram_enable(uint32_t ui32InfoKey) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Clear the SRAM Wipe bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_wipe_sram_enable() + +//***************************************************************************** +// +//! @brief check for SRAM protection enabled. +//! +//! Use this function to determine if SRAM protection is enabled. +//! +//! @return true if SRAM wipe protection is enabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_wipe_sram_enable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not vale at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the SRAM WIPE bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M ? false : true; + +} // am_hal_flash_wipe_sram_enable_check() + +//***************************************************************************** +// +//! @brief Disable Output from ITM/SWO. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Set the SWO disable bit to zero. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_swo_disable(uint32_t ui32InfoKey) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Clear the SWO bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_swo_disable() + +//***************************************************************************** +// +//! @brief check for SWO disabled. +//! +//! Use this function to determine if the SWO is disabled. +//! +//! @return true if the ITM/SWO is disabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_swo_disable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not vale at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the SWO bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M ? false : true; + +} // am_hal_flash_swo_disable_check() + +//***************************************************************************** +// +//! @brief Disable Connections from a debugger on the SWD interface. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Set the debugger disable bit to zero. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_debugger_disable(uint32_t ui32InfoKey) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Clear the DEBUGGER bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_debugger_disable() + +//***************************************************************************** +// +//! @brief check for debugger disabled. +//! +//! Use this function to determine if the debugger is disabled. +//! +//! @return true if the debugger is disabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_debugger_disable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not vale at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the debugger disable bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M ? false : true; + +} // am_hal_flash_debugger_disable_check() + +//***************************************************************************** +// +//! @brief This static helper function generates a 64-bit protection mask. +//! +//! @param pui32StartAddress - Starting address in flash to begin protection. +//! @param pui32StopAddress - Ending address in flash to stop protection. +//! +//! This function computes a chunk map for the protection range. +//! +//! @return Inverse of the actual chunk mask. That is, chunks to be protected +//! are represented as 0 in the returned mask, while chunks to be left alone +//! are represented as 1. This value can therefore be directly ANDed with the +//! existing bits in INFO space. +//! Note that -1 is returned if input parameters are invalid - this return +//! value would indicate that no chunks are to be protected. +//! +// +//***************************************************************************** +static uint64_t +generate_chunk_mask(uint32_t *pui32StartAddress, uint32_t *pui32StopAddress) +{ + uint32_t ui32ChunkStart, ui32ChunkStop; + uint32_t ui32Width; + uint64_t ui64Mask; + + // + // Validate the address input parameters + // + if ( (pui32StartAddress > pui32StopAddress) || + (pui32StopAddress > (uint32_t*)AM_HAL_FLASH_LARGEST_VALID_ADDR) ) + { + // + // Argument error, return value to leave all chunks unprotected. + // + return 0xFFFFFFFFFFFFFFFF; + } + + // + // Extract chunk related information + // + ui32ChunkStart = AM_HAL_FLASH_INFO_ADDR2CHUNK((uint32_t)pui32StartAddress); + ui32ChunkStop = AM_HAL_FLASH_INFO_ADDR2CHUNK((uint32_t)pui32StopAddress); + ui32Width = ui32ChunkStop - ui32ChunkStart + 1; + + if ( ui32Width == 64 ) + { + ui64Mask = (uint64_t)0xFFFFFFFFFFFFFFFFLLU; + } + else + { + ui64Mask = ( ((uint64_t)0x0000000000000001) << ui32Width) - 1; + ui64Mask <<= ui32ChunkStart; + } + + // + // OK now return the chunk mask (inverted). + // + return ~ui64Mask; + +} // generate_chunk_mask() + +//***************************************************************************** +// +//! @brief This function sets copy protection for a range of flash chunks. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! @param pui32StartAddress - Starting address in flash to begin protection. +//! @param pui32StopAddress - Ending address in flash to stop protection. +//! +//! This function will set copy protection bits for a range of flash chunks +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return +//! 0 for success. +//! 0x400000 if the protection bits were already programmed (mask the return +//! value with 0x3FFFFF to ignore this case and treat as success). +//! Otherwise, non-zero for failure. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_copy_protect_set(uint32_t ui32InfoKey, + uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + int iRC; + bool bModified = false; + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t ui32Protection[2]; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_COPYPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return 0x100000; + } + + // + // Go get the current settings for copy protection. + // + ui32Protection[0] = pui32Protection[0]; + ui32Protection[1] = pui32Protection[1]; + + // + // AND mask off the necessary protection bits in the lower word. + // + ui32Work = (uint32_t)ui64Mask; + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[0] ) ) + { + bModified = true; + // Need to change only the bits changing - bits already set to 0 should not be rewritten to 0 + // Flash has limits on number of times a bit can be set to 0 + ui32Protection[0] = ui32Work | ~ui32Protection[0]; + iRC = g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32Protection[0], // source data + (AM_HAL_FLASH_INFO_COPYPROT_O / 4) + 0, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x10000; + } + } + + // + // AND mask off the necessary protection bits in the upper word. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[1] ) ) + { + bModified = true; + // Need to change only the bits changing - bits already set to 0 should not be rewritten to 0 + // Flash has limits on number of times a bit can be set to 0 + ui32Protection[1] = ui32Work | ~ui32Protection[1]; + iRC = g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32Protection[1], // source data + (AM_HAL_FLASH_INFO_COPYPROT_O / 4) + 1, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x20000; + } + } + + if ( bModified ) + { + return 0; + } + else + { + return 0x400000; + } + +} // am_hal_flash_copy_protect_set() + +//***************************************************************************** +// +//! @brief This function checks copy protection for a range of flash chunks. +//! +//! @param pui32StartAddress - Starting address in flash. +//! @param pui32StopAddress - Ending address in flash. +//! +//! This function will check copy protection bits for a range of flash chunks +//! it expects all chunks in the range to be protected. +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @return false for at least one chunk in the covered range is not protected, +//! and true if all chunks in the covered range are protected. +//! +// +//***************************************************************************** +bool +am_hal_flash_copy_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_COPYPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)ui64Mask; + if ( ~ui32Work & pui32Protection[0] ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ~ui32Work & pui32Protection[1] ) + { + return false; + } + + // + // If we get here, there are no unprotected chunks within specified range. + // + return true; + +} // am_hal_flash_copy_protect_check() + +//***************************************************************************** +// +//! @brief This function sets write protection for a range of flash chunks. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! @param pui32StartAddress - Starting address in flash to begin protection. +//! @param pui32StopAddress - Ending address in flash to stop protection. +//! +//! This function will set write protection bits for a range of flash chunks +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return +//! 0 for success. +//! 0x400000 if the protection bits were already programmed (mask the return +//! value with 0x3FFFFF to ignore this case and treat as success). +//! Otherwise, non-zero for failure. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_write_protect_set(uint32_t ui32InfoKey, + uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + int iRC; + bool bModified = false; + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t ui32Protection[2]; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_WRITPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return 0x100000; + } + + // + // Go get the current settings for copy protection. + // + ui32Protection[0] = pui32Protection[0]; + ui32Protection[1] = pui32Protection[1]; + + // + // AND mask off the necessary protection bits in the lower word. + // + ui32Work = (uint32_t)ui64Mask; + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[0] ) ) + { + bModified = true; + // Need to change only the bits changing - bits already set to 0 should not be rewritten to 0 + // Flash has limits on number of times a bit can be set to 0 + ui32Protection[0] = ui32Work | ~ui32Protection[0]; + iRC = g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32Protection[0], // source data + (AM_HAL_FLASH_INFO_WRITPROT_O / 4) + 0, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x10000; + } + } + + // + // AND mask off the necessary protection bits in the upper word. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[1] ) ) + { + bModified = true; + // Need to change only the bits changing - bits already set to 0 should not be rewritten to 0 + // Flash has limits on number of times a bit can be set to 0 + ui32Protection[1] = ui32Work | ~ui32Protection[1]; + iRC = g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32Protection[1], // source data + (AM_HAL_FLASH_INFO_WRITPROT_O / 4) + 1, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x20000; + } + } + + if ( bModified ) + { + return 0; + } + else + { + return 0x400000; + } + +} // am_hal_flash_write_protect_set() + +//***************************************************************************** +// +//! @brief This function checks write protection for a range of flash chunks. +//! +//! @param pui32StartAddress - Starting address in flash. +//! @param pui32StopAddress - Ending address in flash. +//! +//! This function will check write protection bits for a range of flash chunks +//! it expects all chunks in the range to be protected. +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @return false for at least one chunk in the covered range is not protected, +//! and true if all chunks in the covered range are protected. +//! +// +//***************************************************************************** +bool +am_hal_flash_write_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_WRITPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)ui64Mask; + if ( ~ui32Work & pui32Protection[0] ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ~ui32Work & pui32Protection[1] ) + { + return false; + } + + // + // If we get here, there are no unprotected chunks within specified range. + // + return true; + +}// am_hal_flash_write_protect_check() + +//***************************************************************************** +// +//! @brief Read a uint32 value from a valid memory or peripheral location. +//! +//! @param ui32Address - The location to be read. +//! +//! Use this function to safely read a value from peripheral or memory locations. +//! +//! This function calls a function that resides BOOTROM or SRAM to do the actual +//! read, thus completely avoiding any conflict with flash or INFO space. +//! +//! @return The value read from the given address. +// +//***************************************************************************** +uint32_t +am_hal_flash_load_ui32(uint32_t *pui32Address) +{ + return g_am_hal_flash.flash_util_read_word(pui32Address); +} // am_hal_flash_load_ui32() + +//***************************************************************************** +// +//! @brief Write a given uint32 value to a valid memory or peripheral location. +//! +//! @param pui32Address - The location to be written. +//! +//! Use this function to safely store a value to peripheral or memory locations. +//! +//! This function calls a function that resides in BOOTROM or SRAM to do the +//! actual write, thus completely avoiding any conflict with flash or INFO. +//! +//! @return The value read from the given address. +// +//***************************************************************************** +#if defined(__GNUC_STDC_INLINE__) +uint32_t SRAM_write_ui32[12 / 4] = + { + // + // A very simple, word-aligned function residing in SRAM (stack). This + // function writes a given memory location while executing outside of + // flash. It then does a read back to ensure that the write completed. + // Prototype: uint32_t SRAM_write_ui32(ui32Addr, ui32Value); + // + 0xBF006001, // 6001 str r1,[r0,#0] + // BF00 nop + 0xBF006800, // 6800 ldr r0,[r0,#0] + // BF00 nop + 0xBF004770 // 4770 bx lr + // BF00 nop + }; +#elif (defined (__ARMCC_VERSION) || defined(__IAR_SYSTEMS_ICC__)) +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +void +am_hal_flash_store_ui32(uint32_t *pui32Address, uint32_t ui32Value) +{ +#if (defined (__ARMCC_VERSION) || defined(__IAR_SYSTEMS_ICC__)) + uint32_t SRAM_write_ui32[12 / 4] = + { + // + // A very simple, word-aligned function residing in SRAM (stack). This + // function writes a given memory location while executing outside of + // flash. It then does a read back to ensure that the write completed. + // Prototype: uint32_t SRAM_write_ui32(ui32Addr, ui32Value); + // + 0xBF006001, // 6001 str r1,[r0,#0] + // BF00 nop + 0xBF006800, // 6800 ldr r0,[r0,#0] + // BF00 nop + 0xBF004770 // 4770 bx lr + // BF00 nop + }; +#elif defined(__GNUC_STDC_INLINE__) +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + + // + // Call the simple routine that has been coded in SRAM. + // First set up a function pointer to the array, being sure to set the + // .T bit (Thumb bit, bit0) in the branch address, then use that + // function ptr to call the SRAM function. + // + uint32_t SRAMCode = (uint32_t)SRAM_write_ui32 | 0x1; + uint32_t (*pFunc)(uint32_t*, uint32_t) = (uint32_t (*)(uint32_t*, uint32_t))SRAMCode; + (*pFunc)(pui32Address, ui32Value); + +} // am_hal_flash_store_ui32() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.h new file mode 100644 index 0000000..ce4f55c --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.h @@ -0,0 +1,365 @@ +//***************************************************************************** +// +// am_hal_flash.h +//! @file +//! +//! @brief Functions for performing Flash operations. +//! +//! @addtogroup flash3 Flash +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_FLASH_H +#define AM_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +//***************************************************************************** +// +// Flash Program keys. +// +//***************************************************************************** +#define AM_HAL_FLASH_PROGRAM_KEY 0x12344321 +#define AM_HAL_FLASH_INFO_KEY 0xD894E09E + + + +//***************************************************************************** +// +// Some helpful SRAM values and macros. +// +//***************************************************************************** +#define AM_HAL_FLASH_SRAM_ADDR 0x10000000 +#define AM_HAL_FLASH_SRAM_SIZE (384 * 1024) +#define AM_HAL_FLASH_SRAM_LARGEST_VALID_ADDR (AM_HAL_FLASH_SRAM_ADDR + AM_HAL_FLASH_SRAM_SIZE - 1) + +//***************************************************************************** +// +// Some helpful flash values and macros. +// +//***************************************************************************** +#define AM_HAL_FLASH_ADDR 0x00000000 +#define AM_HAL_FLASH_INSTANCE_SIZE ( 512 * 1024 ) +#define AM_HAL_FLASH_NUM_INSTANCES 2 +#define AM_HAL_FLASH_PAGE_SIZE ( 8 * 1024 ) +#define AM_HAL_FLASH_INFO_SIZE AM_HAL_FLASH_PAGE_SIZE +#define AM_HAL_FLASH_INSTANCE_PAGES ( AM_HAL_FLASH_INSTANCE_SIZE / AM_HAL_FLASH_PAGE_SIZE ) +#define AM_HAL_FLASH_TOTAL_SIZE ( AM_HAL_FLASH_INSTANCE_SIZE * AM_HAL_FLASH_NUM_INSTANCES ) +#define AM_HAL_FLASH_LARGEST_VALID_ADDR ( AM_HAL_FLASH_ADDR + AM_HAL_FLASH_TOTAL_SIZE - 1 ) +#define AM_HAL_FLASH_APPL_ADDR 0xC000 + +// +// Macros to determine whether a given address is a valid internal +// flash or SRAM address. +// +#define ISADDRSRAM(x) ((x >= AM_HAL_FLASH_SRAM_ADDR) && \ + (x <= (AM_HAL_FLASH_SRAM_LARGEST_VALID_ADDR & ~0x3))) +#if AM_HAL_FLASH_ADDR == 0x0 +#define ISADDRFLASH(x) (x <= (AM_HAL_FLASH_LARGEST_VALID_ADDR & ~0x3)) +#else +#define ISADDRFLASH(x) ((x >= AM_HAL_FLASH_ADDR) && \ + (x <= (AM_HAL_FLASH_LARGEST_VALID_ADDR & ~0x3))) +#endif + +// +// Macros to describe the flash ROW layout. +// +#define AM_HAL_FLASH_ROW_WIDTH_BYTES (512) + +// +// Convert an absolute flash address to an instance +// +#define AM_HAL_FLASH_ADDR2INST(addr) ( ( addr >> 19 ) & (AM_HAL_FLASH_NUM_INSTANCES - 1) ) + +// +// Convert an absolute flash address to a page number relative to the instance +// +#define AM_HAL_FLASH_ADDR2PAGE(addr) ( ( addr >> 13 ) & 0x3F ) + +// +// Convert an absolute flash address to an absolute page number +// +#define AM_HAL_FLASH_ADDR2ABSPAGE(addr) ( addr >> 13 ) + +//***************************************************************************** +// +//! Given an integer number of microseconds, convert to a value representing +//! the number of am_hal_flash_delay() cycles that will provide that amount +//! of delay. This macro is designed to take into account some of the call +//! overhead and latencies. +//! +//! e.g. To provide a 10us delay: +//! am_hal_flash_delay( FLASH_CYCLES_US(10) ); +//! +//! As of SDK 2.1, burst mode is accounted for in am_hal_flash_delay(). +//! +//! The FLASH_CYCLES_US macro assumes: +//! - Burst or normal mode operation. +//! - If cache is not enabled, use FLASH_CYCLES_US_NOCACHE() instead. +// +//***************************************************************************** +#define CYCLESPERITER (AM_HAL_CLKGEN_FREQ_MAX_MHZ / 3) +#define FLASH_CYCLES_US(n) ((n * CYCLESPERITER) + 0) +#define FLASH_CYCLES_US_NOCACHE(n) ( (n == 0) ? 0 : (n * CYCLESPERITER) - 5) + +// +// Backward compatibility +// +#define am_hal_flash_program_otp am_hal_flash_program_info +#define am_hal_flash_program_otp_sram am_hal_flash_program_info_sram + +//***************************************************************************** +// +//! Structure of pointers to helper functions invoking flash operations. +// +//! The functions we are pointing to here are in the Apollo 3 +//! integrated BOOTROM. +// +//***************************************************************************** +typedef struct am_hal_flash_helper_struct +{ + // + // The basics. + // + int (*flash_mass_erase)(uint32_t, uint32_t); + int (*flash_page_erase)(uint32_t, uint32_t, uint32_t); + int (*flash_program_main)(uint32_t, uint32_t *, uint32_t *, uint32_t); + int (*flash_program_info_area)(uint32_t, uint32_t, uint32_t *, uint32_t, uint32_t); + + // + // Non-blocking variants, but be careful these are not interrupt safe so + // mask interrupts while these very long operations proceed. + // + int (*flash_mass_erase_nb)(uint32_t, uint32_t); + int (*flash_page_erase_nb)(uint32_t, uint32_t, uint32_t); + int (*flash_page_erase2_nb)( uint32_t value, uint32_t address); + bool (*flash_nb_operation_complete)(void); + + // + // Useful utilities. + // + uint32_t (*flash_util_read_word)( uint32_t *); + void (*flash_util_write_word)( uint32_t *, uint32_t); + void (*bootrom_delay_cycles)(uint32_t ui32Cycles); + + // + // Essentially these are recovery options. + // + int (*flash_info_erase)( uint32_t, uint32_t); + int (*flash_info_plus_main_erase)( uint32_t, uint32_t); + int (*flash_info_plus_main_erase_both)( uint32_t value); + int (*flash_recovery)( uint32_t value); + + // + // The following functions pointers will generally never be called from + // user programs. They are here primarily to document these entry points + // which are usable from a debugger or debugger script. + // + void (*flash_program_main_from_sram)(void); + void (*flash_program_info_area_from_sram)(void); + void (*flash_erase_main_pages_from_sram)(void); + void (*flash_mass_erase_from_sram)(void); + void (*flash_info_erase_from_sram)(void); + void (*flash_info_plus_main_erase_from_sram)(void); + void (*flash_nb_operation_complete_from_sram)(void); + void (*flash_page_erase2_nb_from_sram)(void); + void (*flash_recovery_from_sram)(void); + +} g_am_hal_flash_t; +extern const g_am_hal_flash_t g_am_hal_flash; + + +//***************************************************************************** +// +// Define some FLASH INFO SPACE values and macros. +// +//***************************************************************************** +#define AM_HAL_FLASH_INFO_ADDR 0x50020000 +#define AM_HAL_FLASH_INFO_SECURITY_O 0x10 +#define AM_HAL_FLASH_INFO_WRITPROT_O 0x40 +#define AM_HAL_FLASH_INFO_COPYPROT_O 0x50 + +#define AM_HAL_FLASH_INFO_SECURITY_ADDR (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_SECURITY_O) +#define AM_HAL_FLASH_INFO_WRITPROT_ADDR (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_WRITPROT_O) +#define AM_HAL_FLASH_INFO_COPYPROT_ADDR (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_COPYPROT_O) +#define AM_HAL_FLASH_INFO_CUST_TRIM_ADDR (AM_HAL_FLASH_INFO_ADDR + 0x14) + +// +// Define the customer info signature data (at AM_HAL_FLASH_INFO_ADDR). +// These bits must exist in the customer info space in order for many of the +// security and protection functions to work. +// +#define AM_HAL_FLASH_INFO_SIGNATURE0 0x48EAAD88 +#define AM_HAL_FLASH_INFO_SIGNATURE1 0xC9705737 +#define AM_HAL_FLASH_INFO_SIGNATURE2 0x0A6B8458 +#define AM_HAL_FLASH_INFO_SIGNATURE3 0xE41A9D74 + +// +// Define the customer security bits (at AM_HAL_FLASH_INFO_SECURITY_ADDR) +// +#define AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_S 0 +#define AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_S 1 +#define AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_S 2 +#define AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_S 3 +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S 4 +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_S 8 +#define AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S 9 + +#define AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_S)) +#define AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_S)) +#define AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_S)) +#define AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_S)) +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M ((uint32_t)(0xF << AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S)) +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_S)) +#define AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S)) +#define AM_HAL_FLASH_INFO_SECURITY_DEEPSLEEP_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S)) +#define AM_HAL_FLASH_INFO_SECURITY_DEEPSLEEP ((uint32_t)(0x0 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S)) + +// +// Protection chunk macros +// AM_HAL_FLASH_INFO_CHUNK2ADDR: Convert a chunk number to an address +// AM_HAL_FLASH_INFO_CHUNK2INST: Convert a chunk number to an instance number +// AM_HAL_FLASH_INFO_ADDR2CHUNK: Convert an address to a chunk number +// +#define AM_HAL_FLASH_INFO_CHUNKSIZE (16*1024) + +#define AM_HAL_FLASH_INFO_CHUNK2ADDR(n) (AM_HAL_FLASH_ADDR + (n << 14)) +#define AM_HAL_FLASH_INFO_CHUNK2INST(n) ((n >> 5) & 1 +#define AM_HAL_FLASH_INFO_ADDR2CHUNK(n) ((n) >> 14) + +//***************************************************************************** +// +// Function prototypes for the helper functions +// +//***************************************************************************** +extern int am_hal_flash_mass_erase(uint32_t ui32ProgramKey, uint32_t ui32FlashInst); +extern int am_hal_flash_page_erase(uint32_t ui32ProgramKey, uint32_t ui32FlashInst, + uint32_t ui32PageNum); +extern int am_hal_flash_program_main(uint32_t ui32ProgramKey, uint32_t *pSrc, + uint32_t *pDst, uint32_t NumberOfWords); + +// +// Recovery type functions for Customer INFO space. +// +extern int am_hal_flash_program_info(uint32_t ui32InfoKey, uint32_t ui32InfoInst, + uint32_t *pui32Src, uint32_t ui32Offset, + uint32_t ui32NumWords); +extern int am_hal_flash_erase_info(uint32_t ui32InfoKey, + uint32_t ui32Instance); +extern int am_hal_flash_erase_main_plus_info(uint32_t ui32InfoKey, + uint32_t ui32Instance); +extern int am_hal_flash_erase_main_plus_info_both_instances( + uint32_t ui32InfoKey); +extern void am_hal_flash_recovery(uint32_t ui32RecoveryKey); + +// +// This function safely writes to a peripheral or memory address while executing +// from SRAM, thus avoiding any conflict with flash or INFO space. +// +extern void am_hal_flash_store_ui32(uint32_t *pui32Address, uint32_t ui32Data); + +// +// BOOTROM resident reader, writer and delay utility functions. +// +extern uint32_t am_hal_flash_load_ui32(uint32_t *pui32Address); +extern void am_hal_flash_delay(uint32_t ui32Iterations); +extern uint32_t am_hal_flash_delay_status_change(uint32_t ui32Iterations, + uint32_t ui32Address, + uint32_t ui32Mask, + uint32_t ui32Value); +extern uint32_t am_hal_flash_delay_status_check(uint32_t ui32Iterations, + uint32_t ui32Address, + uint32_t ui32Mask, + uint32_t ui32Value, + bool bIsEqual); + +// +// These functions update security/protection bits in the customer INFO blOCK. +// +extern bool am_hal_flash_customer_info_signature_check(void); +extern bool am_hal_flash_info_signature_set(uint32_t ui32InfoKey); +extern int32_t am_hal_flash_info_erase_disable(uint32_t ui32InfoKey); +extern bool am_hal_flash_info_erase_disable_check(void); +extern int32_t am_hal_flash_info_program_disable(uint32_t ui32InfoKey, uint32_t ui32Mask); +extern uint32_t am_hal_flash_info_program_disable_get(void); +extern int32_t am_hal_flash_wipe_flash_enable(uint32_t ui32InfoKey); +extern bool am_hal_flash_wipe_flash_enable_check(void); +extern int32_t am_hal_flash_wipe_sram_enable(uint32_t ui32InfoKey); +extern bool am_hal_flash_wipe_sram_enable_check(void); +extern int32_t am_hal_flash_swo_disable(uint32_t ui32InfoKey); +extern bool am_hal_flash_swo_disable_check(void); +extern int32_t am_hal_flash_debugger_disable(uint32_t ui32InfoKey); +extern bool am_hal_flash_debugger_disable_check(void); + +extern int32_t am_hal_flash_copy_protect_set(uint32_t ui32InfoKey, + uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern bool am_hal_flash_copy_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern int32_t am_hal_flash_write_protect_set(uint32_t ui32InfoKey, + uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern bool am_hal_flash_write_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern int am_hal_flash_clear_bits(uint32_t ui32ProgramKey, + uint32_t *pui32Addr, + uint32_t ui32BitMask); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_FLASH_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.c new file mode 100644 index 0000000..37ce3ec --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.c @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// am_hal_global.c +//! @file +//! +//! @brief Locate global variables here. +//! +//! This module contains global variables that are used throughout the HAL. +//! +//! One use in particular is that it uses a global HAL flags variable that +//! contains flags used in various parts of the HAL. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** +uint32_t volatile g_ui32HALflags = 0x00000000; + +//***************************************************************************** +// +// Version information +// +//***************************************************************************** +const uint8_t g_ui8HALcompiler[] = COMPILER_VERSION; +const am_hal_version_t g_ui32HALversion = +{ + .s.bAMREGS = false, + .s.Major = AM_HAL_VERSION_MAJ, + .s.Minor = AM_HAL_VERSION_MIN, + .s.Revision = AM_HAL_VERSION_REV +}; diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.h new file mode 100644 index 0000000..a7ba87b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.h @@ -0,0 +1,167 @@ +//***************************************************************************** +// +// am_hal_global.h +//! @file +//! +//! @brief Locate all HAL global variables here. +//! +//! This module contains global variables that are used throughout the HAL, +//! but not necessarily those designated as const (which typically end up in +//! flash). Consolidating globals here will make it easier to manage them. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_GLOBAL_H +#define AM_HAL_GLOBAL_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Include the SDK global version information. +// +//***************************************************************************** +#include "../../am_sdk_version.h" + +//***************************************************************************** +// +// Device definitions +// +//***************************************************************************** +#define AM_HAL_DEVICE_NAME "Apollo3 Blue" + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** +// Utility for compile time assertions +// Will cause divide by 0 error at build time +#define _AM_ASSERT_CONCAT_(a, b) a##b +#define _AM_ASSERT_CONCAT(a, b) _AM_ASSERT_CONCAT_(a, b) +#define am_ct_assert(e) enum { _AM_ASSERT_CONCAT(assert_line_, __LINE__) = 1/(!!(e)) } + +//***************************************************************************** +// +// Macros to determine compiler version information +// +//***************************************************************************** +// +// Since the stringize operator itself does not first expand macros, two levels +// of indirection are required in order to fully resolve the pre-defined +// compiler (integer) macros. The 1st level expands the macro, and the 2nd +// level actually stringizes it. +// This method will also work even if the argument is not a macro. However, if +// the argument is already a string, the string will end up with inserted quote +// marks. +// +#define STRINGIZE_VAL(n) STRINGIZE_VAL2(n) +#define STRINGIZE_VAL2(n) #n + +#ifdef __GNUC__ +#define COMPILER_VERSION ("GCC " __VERSION__) +#elif defined(__ARMCC_VERSION) +#define COMPILER_VERSION ("ARMCC " STRINGIZE_VAL(__ARMCC_VERSION)) +#elif defined(__KEIL__) +#define COMPILER_VERSION "KEIL_CARM " STRINGIZE_VAL(__CA__) +#elif defined(__IAR_SYSTEMS_ICC__) +#define COMPILER_VERSION __VERSION__ +#else +#define COMPILER_VERSION "Compiler unknown" +#endif + +//***************************************************************************** +// +// Utility Macros +// +//***************************************************************************** +// As long as the two values are not apart by more that 2^31, this should give +// correct result, taking care of wraparound +#define AM_HAL_U32_GREATER(val1, val2) ((int32_t)((int32_t)(val1) - (int32_t)(val2)) > 0) +#define AM_HAL_U32_SMALLER(val1, val2) ((int32_t)((int32_t)(val1) - (int32_t)(val2)) < 0) + +//****************************************************************************** +// +// Global typedefs +// +//****************************************************************************** +typedef union +{ + uint32_t u32; + struct + { + uint32_t resvd : 7; // [6:0] + uint32_t bAMREGS : 1; // [7] + uint32_t Revision : 8; // [15:8] + uint32_t Minor : 8; // [23:16] + uint32_t Major : 8; // [31:24] + } s; +} am_hal_version_t; + +typedef union +{ + uint32_t u32; + struct + { + uint32_t magic : 24; + uint32_t bInit : 1; + uint32_t bEnable : 1; + uint32_t resv : 6; + } s; +} am_hal_handle_prefix_t; + +//***************************************************************************** +// +// Global Variables extern declarations. +// +//***************************************************************************** +extern volatile uint32_t g_ui32HALflags; +extern const uint8_t g_ui8HALcompiler[]; +extern const am_hal_version_t g_ui32HALversion; + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_GLOBAL_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.c new file mode 100644 index 0000000..50ec4b4 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.c @@ -0,0 +1,1560 @@ +//***************************************************************************** +// +// am_hal_gpio.c +//! @file +//! +//! @brief Functions for interfacing with the GPIO module +//! +//! @addtogroup gpio3 GPIO +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// Local defines. +//***************************************************************************** +// +// Generally define GPIO PADREG and GPIOCFG bitfields +// +#define PADREG_FLD_76_S 6 +#define PADREG_FLD_FNSEL_S 3 +#define PADREG_FLD_DRVSTR_S 2 +#define PADREG_FLD_INPEN_S 1 +#define PADREG_FLD_PULLUP_S 0 + +#define GPIOCFG_FLD_INTD_S 3 +#define GPIOCFG_FLD_OUTCFG_S 1 +#define GPIOCFG_FLD_INCFG_S 0 + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +//***************************************************************************** +// Define some common GPIO configurations. +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_DISABLE = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_TRISTATE = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_TRISTATE +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN +}; + +// +// Input with various pullups (weak, 1.5K, 6K, 12K, 24K) +// The 1.5K - 24K pullup values are valid for select I2C enabled pads. +// For Apollo3 these pins are 0-1,5-6,8-9,25,27,39-40,42-43,48-49. +// The "weak" value is used for almost every other pad except pin 20. +// +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_WEAK +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_1_5 = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_6 = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_6K +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_12 = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_12K +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_24 = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_24K +}; + +// +// Variations of output (drive strengths, read, etc) +// +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_4 = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_8 = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_12 = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_WITH_READ = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN +}; + +//***************************************************************************** +// +// g_ui8Inpen[] +// This lookup table determines whether the INPEN bit is required based on +// the pin number and FNSEL. +// +//***************************************************************************** +static const uint8_t +g_ui8Inpen[AM_HAL_GPIO_MAX_PADS] = +{ + //0 1 2 3 4 5 6 7 8 9 + 0x23, 0x23, 0x27, 0x62, 0xA1, 0x03, 0x87, 0x10, 0x03, 0x53, // Pins 0-9 + 0x00, 0xE1, 0x51, 0x81, 0x41, 0x55, 0x05, 0xC4, 0x80, 0x40, // Pins 10-19 + 0x01, 0xB1, 0x40, 0x41, 0x14, 0x31, 0xA0, 0x31, 0x00, 0xF1, // Pins 20-29 + 0x80, 0x11, 0x91, 0x21, 0xC1, 0x11, 0xE5, 0x11, 0x45, 0x30, // Pins 30-39 + 0x37, 0x00, 0x30, 0x31, 0x00, 0x71, 0x00, 0x40, 0x30, 0x31 // Pins 40-49 +}; + +//***************************************************************************** +// +// g_ui8Bit76Capabilities[] +// This lookup table specifies capabilities of each pad for PADREG bits 7:6. +// +//***************************************************************************** +#define CAP_PUP 0x01 // PULLUP +#define CAP_PDN 0x08 // PULLDOWN (pin 20 only) +#define CAP_VDD 0x02 // VDD PWR (power source) +#define CAP_VSS 0x04 // VSS PWR (ground sink) +#define CAP_RSV 0x80 // bits 7:6 are reserved for this pin +static const uint8_t +g_ui8Bit76Capabilities[AM_HAL_GPIO_MAX_PADS] = +{ + //0 1 2 3 4 5 6 7 8 9 + CAP_PUP, CAP_PUP, CAP_RSV, CAP_VDD, CAP_RSV, CAP_PUP, CAP_PUP, CAP_RSV, CAP_PUP, CAP_PUP, // Pins 0-9 + CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, // Pins 10-19 + CAP_PDN, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_PUP, CAP_RSV, CAP_PUP, CAP_RSV, CAP_RSV, // Pins 20-29 + CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_VDD, CAP_VSS, CAP_RSV, CAP_PUP, // Pins 30-39 + CAP_PUP, CAP_VSS, CAP_PUP, CAP_PUP, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_PUP, CAP_PUP // Pins 40-49 +}; + +//***************************************************************************** +// +// g_ui8nCEpins[] +// This lookup table lists the nCE funcsel value as a function of the pin. +// Almost every pad has a nCE function (except for 4 pads). Every one of those +// nCE functions can select a polarity (active low or high) via the INTD field. +// All non-nCE functions use INCFG and INTD to select interrupt transition types. +// A lookup will return 0-7 if the pin supports nCE, and 8 if it does not. +// +// The truth table summarizes behavior. For the purposes of this table, assume +// "A" is the funcsel that selects nCE (and thus polarity is needed) for the +// given pad. Then "!A" is any other funcsel and selects interrupt transition. +// +// funcsel INCFG INTD Behavior +// !A 0 0 Interrupt on L->H transition. +// !A 0 1 Interrupt on H->L transition. +// !A 1 0 No interrupts. +// !A 1 1 Interrupt either direction. +// A x 0 nCE polarity active low. +// A x 1 nCE polarity active high. +// +//***************************************************************************** +static const uint8_t +g_ui8nCEpins[AM_HAL_GPIO_MAX_PADS] = +{ + // 0 1 2 3 4 5 6 7 8 9 + 0x07, 0x07, 0x07, 0x02, 0x02, 0x08, 0x08, 0x00, 0x02, 0x02, // Pads 0-9 + 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, // Pads 10-19 + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, // Pads 20-29 + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x08, // Pads 30-39 + 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 // Pads 40-49 +}; + +//***************************************************************************** +// +// g_ui8NCEtable[] +// This lookup table lists all available NCEs. It basically reproduces the +// "NCE Encoding Table" from the datasheet. +// The format of this table is: +// High nibble=IOM number; 0-5, MSPI=6 (IOMNUM_MSPI). +// Low nibble=CE number (0-3). +// Every 4 bytes (word) represent the next GPIO number/index. +// +//***************************************************************************** +static const uint8_t +g_ui8NCEtable[AM_HAL_GPIO_MAX_PADS][4] = +{ + // 0 1 2 3 = OUTCFG + {0x32, 0x42, 0x52, 0x13}, // NCE0 + {0x02, 0x12, 0x22, 0x60}, // NCE1 + {0x33, 0x43, 0x53, 0x21}, // NCE2 + {0x30, 0x40, 0x50, 0x20}, // NCE3 + {0x31, 0x41, 0x51, 0x11}, // NCE4 + {0xFF, 0xFF, 0xFF, 0xFF}, // NCE5 + {0xFF, 0xFF, 0xFF, 0xFF}, // NCE6 + {0x31, 0x41, 0x51, 0x60}, // NCE7 + {0x30, 0x40, 0x50, 0x00}, // NCE8 + {0x33, 0x43, 0x53, 0x23}, // NCE9 + {0x32, 0x42, 0x52, 0x60}, // NCE10 + {0x00, 0x10, 0x20, 0x30}, // NCE11 + {0x30, 0x40, 0x50, 0x61}, // NCE12 + {0x31, 0x41, 0x51, 0x01}, // NCE13 + {0x02, 0x12, 0x22, 0x42}, // NCE14 + {0x03, 0x13, 0x23, 0x60}, // NCE15 + {0x00, 0x10, 0x20, 0x50}, // NCE16 + {0x01, 0x11, 0x21, 0x41}, // NCE17 + {0x02, 0x12, 0x22, 0x32}, // NCE18 + {0x03, 0x13, 0x33, 0x60}, // NCE19 + {0x31, 0x41, 0x51, 0x21}, // NCE20 + {0x32, 0x42, 0x52, 0x22}, // NCE21 + {0x33, 0x43, 0x53, 0x03}, // NCE22 + {0x00, 0x10, 0x20, 0x40}, // NCE23 + {0x01, 0x11, 0x21, 0x51}, // NCE24 + {0x32, 0x42, 0x52, 0x02}, // NCE25 + {0x33, 0x43, 0x53, 0x13}, // NCE26 + {0x30, 0x40, 0x50, 0x10}, // NCE27 + {0x31, 0x41, 0x51, 0x60}, // NCE28 + {0x32, 0x42, 0x52, 0x12}, // NCE29 + {0x33, 0x43, 0x53, 0x03}, // NCE30 + {0x00, 0x10, 0x20, 0x40}, // NCE31 + {0x01, 0x11, 0x21, 0x61}, // NCE32 + {0x02, 0x12, 0x22, 0x52}, // NCE33 + {0x03, 0x13, 0x23, 0x33}, // NCE34 + {0x00, 0x10, 0x20, 0x30}, // NCE35 + {0x31, 0x41, 0x51, 0x61}, // NCE36 + {0x32, 0x42, 0x52, 0x02}, // NCE37 + {0x03, 0x13, 0x33, 0x53}, // NCE38 + {0xFF, 0xFF, 0xFF, 0xFF}, // NCE39 + {0xFF, 0xFF, 0xFF, 0xFF}, // NCE40 + {0x01, 0x11, 0x21, 0x61}, // NCE41 + {0x00, 0x10, 0x20, 0x50}, // NCE42 + {0x01, 0x11, 0x21, 0x61}, // NCE43 + {0x02, 0x12, 0x22, 0x52}, // NCE44 + {0x33, 0x43, 0x53, 0x13}, // NCE45 + {0x30, 0x40, 0x50, 0x61}, // NCE46 + {0x01, 0x11, 0x21, 0x31}, // NCE47 + {0x02, 0x12, 0x22, 0x32}, // NCE48 + {0x03, 0x13, 0x23, 0x43} // NCE49 +}; + +// declare ap3_gpio_get_pinconfig_bitmasks +void ap3_gpio_get_pinconfig_bitmasks(am_hal_gpio_pincfg_allow_t sAllowableChanges, uint8_t *padRegMask, uint8_t *GPCfgMask, uint8_t *altPadCfgMask); + +//***************************************************************************** +// +// Array of function pointers for handling GPIO interrupts. +// +//***************************************************************************** +static am_hal_gpio_handler_t gpio_ppfnHandlers[AM_HAL_GPIO_MAX_PADS]; +static void *gpio_pHandlerCtxt[AM_HAL_GPIO_MAX_PADS]; + +//***************************************************************************** +// +// Helper functions +// popcount() - Determine how many bits are set in the given bitmasks. +// pincfg_equ() - compare 2 am_hal_gpio_pincfg_t structures for equality. +// +//***************************************************************************** +static bool +pincfg_equ(void *cfg1, void *cfg2) +{ + uint32_t ui32A, ui32B; + + // + // We're assuming that am_hal_gpio_pincfg_t boils down to a uint32_t, + // which is its intent. + // + ui32A = *((uint32_t*)cfg1); + ui32B = *((uint32_t*)cfg2); + + return ui32A == ui32B ? true : false; + +} // pincfg_equ() + +static uint32_t +popcount(uint64_t ui64bitmask) +{ + uint32_t uCnt = 0; + while ( ui64bitmask ) + { + uCnt += ui64bitmask & 1; + ui64bitmask >>= 1; + } + return uCnt; +} // popcount() + +//***************************************************************************** +// +//! @brief Configure an Apollo3 pin. +//! +//! @param ui32Pin - pin number to be configured. +//! @param ui32Config - Contains multiple descriptor fields. +//! +//! This function configures a pin according to the parameters in ui32Config. +//! All parameters are validated, and the given pin is configured according +//! to the designated parameters. +//! +//! @return Status. +// +//***************************************************************************** +uint32_t +am_hal_gpio_pinconfig(uint32_t ui32Pin, am_hal_gpio_pincfg_t bfGpioCfg) + +{ + uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg; + uint32_t ui32Funcsel, ui32PowerSw; + bool bClearEnable = false; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( ui32Pin >= AM_HAL_GPIO_MAX_PADS ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Initialize the PADREG accumulator variables. + // + ui32GPCfg = ui32Padreg = ui32AltPadCfg = 0; + + // + // Get the requested function and/or power switch. + // + ui32Funcsel = bfGpioCfg.uFuncSel; + ui32PowerSw = bfGpioCfg.ePowerSw; + + ui32Padreg |= ui32Funcsel << PADREG_FLD_FNSEL_S; + + // + // Check for invalid configuration requests. + // + if ( bfGpioCfg.ePullup != AM_HAL_GPIO_PIN_PULLUP_NONE ) + { + // + // This setting is needed for all pullup settings including + // AM_HAL_GPIO_PIN_PULLUP_WEAK and AM_HAL_GPIO_PIN_PULLDOWN. + // + ui32Padreg |= (0x1 << PADREG_FLD_PULLUP_S); + + // + // Check for specific pullup or pulldown settings. + // + if ( (bfGpioCfg.ePullup >= AM_HAL_GPIO_PIN_PULLUP_1_5K) && + (bfGpioCfg.ePullup <= AM_HAL_GPIO_PIN_PULLUP_24K) ) + { + ui32Padreg |= ((bfGpioCfg.ePullup - AM_HAL_GPIO_PIN_PULLUP_1_5K) << + PADREG_FLD_76_S); +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !(g_ui8Bit76Capabilities[ui32Pin] & CAP_PUP) ) + { + return AM_HAL_GPIO_ERR_PULLUP; + } + } + else if ( bfGpioCfg.ePullup == AM_HAL_GPIO_PIN_PULLDOWN ) + { + if ( ui32Pin != 20 ) + { + return AM_HAL_GPIO_ERR_PULLDOWN; + } + } + else if ( bfGpioCfg.ePullup == AM_HAL_GPIO_PIN_PULLUP_WEAK ) + { + // + // All pads except 20 support a weak pullup, for which we only need + // to set PADnPULL and clear 7:6 (already done at this point). + // + if ( ui32Pin == 20 ) + { + return AM_HAL_GPIO_ERR_PULLUP; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + } + } + + // + // Check if requesting a power switch pin + // + if ( ui32PowerSw != AM_HAL_GPIO_PIN_POWERSW_NONE ) + { + if ( (ui32PowerSw == AM_HAL_GPIO_PIN_POWERSW_VDD) && + (g_ui8Bit76Capabilities[ui32Pin] & CAP_VDD) ) + { + ui32Padreg |= 0x1 << PADREG_FLD_76_S; + } + else if ( (ui32PowerSw == AM_HAL_GPIO_PIN_POWERSW_VSS) && + (g_ui8Bit76Capabilities[ui32Pin] & CAP_VSS) ) + { + ui32Padreg |= 0x2 << PADREG_FLD_76_S; + } + else + { + return AM_HAL_GPIO_ERR_PWRSW; + } + } + + // + // Depending on the selected pin and FNSEL, determine if INPEN needs to be set. + // + ui32Padreg |= (g_ui8Inpen[ui32Pin] & (1 << ui32Funcsel)) ? (1 << PADREG_FLD_INPEN_S) : 0; + + // + // Configure ui32GpCfg based on whether nCE requested. + // + if ( g_ui8nCEpins[ui32Pin] == ui32Funcsel ) + { + uint32_t ui32Outcfg; + uint8_t ui8CEtbl; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // User is configuring a nCE. Verify the requested settings and set the + // polarity and OUTCFG values (INCFG is not used here and should be 0). + // Valid uNCE values are 0-3 (uNCE is a 2-bit field). + // Valid uIOMnum are 0-6 (0-5 for IOMs, 6 for MSPI, 7 is invalid). + // + if ( bfGpioCfg.uIOMnum > IOMNUM_MAX ) + { + return AM_HAL_GPIO_ERR_INVCE; // Invalid CE specified + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Construct the entry we expect to find in the table. We can determine + // the OUTCFG value by looking for that value in the pin row. + // + ui8CEtbl = (bfGpioCfg.uIOMnum << 4) | bfGpioCfg.uNCE; + for ( ui32Outcfg = 0; ui32Outcfg < 4; ui32Outcfg++ ) + { + if ( g_ui8NCEtable[ui32Pin][ui32Outcfg] == ui8CEtbl ) + { + break; + } + } + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( ui32Outcfg >= 4 ) + { + return AM_HAL_GPIO_ERR_INVCEPIN; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32GPCfg |= (ui32Outcfg << GPIOCFG_FLD_OUTCFG_S) | + (bfGpioCfg.eCEpol << GPIOCFG_FLD_INTD_S) | + (0 << GPIOCFG_FLD_INCFG_S); + } + else + { + // + // It's not nCE, it's one of the other funcsels. + // Start by setting the value of the requested GPIO input. + // + ui32Padreg |= (bfGpioCfg.eGPInput << PADREG_FLD_INPEN_S); + + // + // Map the requested interrupt direction settings into the Apollo3 + // GPIOCFG register field, which is a 4-bit field: + // [INTD(1):OUTCFG(2):INCFG(1)]. + // Bit0 of eIntDir maps to GPIOCFG.INTD (b3). + // Bit1 of eIntDir maps to GPIOCFG.INCFG (b0). + // + ui32GPCfg |= (bfGpioCfg.eGPOutcfg << GPIOCFG_FLD_OUTCFG_S) | + (((bfGpioCfg.eIntDir >> 0) & 0x1) << GPIOCFG_FLD_INTD_S) | + (((bfGpioCfg.eIntDir >> 1) & 0x1) << GPIOCFG_FLD_INCFG_S); + + if ( (bfGpioCfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL) || + pincfg_equ(&bfGpioCfg, (void*)&g_AM_HAL_GPIO_DISABLE) ) + { + // + // For pushpull configurations, we must be sure to clear the ENABLE + // bit. In pushpull, these bits turn on FAST GPIO. For regular + // GPIO, they must be clear. + // + bClearEnable = true; + } + + // + // There is some overlap between eGPRdZero and eIntDir as both settings + // utilize the overloaded INCFG bit. + // Therefore the two fields should be used in a mutually exclusive + // manner. For flexibility however they are not disallowed because + // their functionality is dependent on FUNCSEL and whether interrupts + // are used. + // + // In the vein of mutual exclusion, eGPRdZero is primarily intended for + // use when GPIO interrupts are not in use and can be used when no + // eIntDir setting is provided. + // If eIntDir is provided, eGPRdZero is ignored and can only be + // achieved via the AM_HAL_GPIO_PIN_INTDIR_NONE setting. + // + if ( bfGpioCfg.eIntDir == 0 ) + { + ui32GPCfg &= ~(1 << GPIOCFG_FLD_INCFG_S); + ui32GPCfg |= (bfGpioCfg.eGPRdZero << GPIOCFG_FLD_INCFG_S); + } + } + + switch ( bfGpioCfg.eDriveStrength ) + { + // DRIVESTRENGTH is a 2-bit field. + // bit0 maps to bit2 of a PADREG field. + // bit1 maps to bit0 of an ALTPADCFG field. + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA: + ui32Padreg |= (0 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (0 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA: + ui32Padreg |= (1 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (0 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA: + ui32Padreg |= (0 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (1 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA: + ui32Padreg |= (1 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (1 << 0); + break; + } + + // + // At this point, the 3 configuration variables, ui32GPCfg, ui32Padreg, + // and ui32AltPadCfg values are set (at bit position 0) and ready to write + // to their respective register bitfields. + // + uint32_t ui32GPCfgAddr, ui32PadregAddr, ui32AltpadAddr; + uint32_t ui32GPCfgClearMask, ui32PadClearMask; + uint32_t ui32GPCfgShft, ui32PadShft; + + ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3); + ui32PadregAddr = AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3); + ui32AltpadAddr = AM_REGADDR(GPIO, ALTPADCFGA) + (ui32Pin & ~0x3); + + ui32GPCfgShft = ((ui32Pin & 0x7) << 2); + ui32PadShft = ((ui32Pin & 0x3) << 3); + ui32GPCfgClearMask = ~((uint32_t)0xF << ui32GPCfgShft); + ui32PadClearMask = ~((uint32_t)0xFF << ui32PadShft); + + // + // Get the new values into their rightful bit positions. + // + ui32Padreg <<= ui32PadShft; + ui32AltPadCfg <<= ui32PadShft; + ui32GPCfg <<= ui32GPCfgShft; + + AM_CRITICAL_BEGIN + + if ( bClearEnable ) + { + // + // We're configuring a mode that requires clearing the Enable bit. + // + am_hal_gpio_output_tristate_disable(ui32Pin); + } + + GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key; + + AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) | ui32Padreg; + AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg; + AM_REGVAL(ui32AltpadAddr) = (AM_REGVAL(ui32AltpadAddr) & ui32PadClearMask) | ui32AltPadCfg; + + GPIO->PADKEY = 0; + + AM_CRITICAL_END + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_pinconfig() + +//***************************************************************************** +// +// brief Configure specified pins for FAST GPIO operation. +// +// ui64PinMask - a mask specifying up to 8 pins to be configured and +// used for FAST GPIO (only bits 0-49 are valid). +// bfGpioCfg - The GPIO configuration (same as am_hal_gpio_pinconfig()). +// All of the pins specified by ui64PinMask will be set to this +// configuration. +// ui32Masks - If provided, an array to receive 2 32-bit values of the +// SET and CLEAR masks that are used for the BBSETCLEAR reg. +// Two 32-bit wds are placed for each pin indicated by the mask. +// The 2 32-bit values will be placed at incremental indexes. +// For example, say pin numbers 5 and 19 are indicated in the +// mask, and an array pointer is provided in ui32Masks. This +// array must be allocated by the caller to be at least 4 words. +// ui32Masks[0] = the set mask used for pin 5. +// ui32Masks[1] = the clear mask used for pin 5. +// ui32Masks[2] = the set mask used for pin 19. +// ui32Masks[3] = the clear mask used for pin 19. +// It is recommended that this array be allocated to 16 uint32_t. +// +//***************************************************************************** +uint32_t +am_hal_gpio_fast_pinconfig(uint64_t ui64PinMask, + am_hal_gpio_pincfg_t bfGpioCfg, + uint32_t ui32Masks[]) +{ + uint32_t ux, ui32pinnum, ui32retval, ui32Mask; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (ui64PinMask & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1)) || + (popcount(ui64PinMask) > 8) || + (bfGpioCfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_TRISTATE) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Roll through the pin mask and configure any designated pins per the + // bfGpioCfg parameter, and enable for Fast GPIO. + // + ui32Mask = 0; + ui32pinnum = 0; + ux = 0; + while ( ui64PinMask ) + { + if ( ui64PinMask & 0x1 ) + { + // + // It is assumed that the caller will have disabled Fast GPIO and + // initialized the pin value before calling this function. Therefore + // no value initialization is done before the pin configuration, nor + // is the am_hal_gpio_fastgpio_disable() called here. + // + // Configure the pin. + // + ui32retval = am_hal_gpio_pinconfig(ui32pinnum, bfGpioCfg); + if ( ui32retval ) + { + return ui32retval; + } + + ui32Mask |= 1 << (ui32pinnum & 0x7); + + // + // Enable the FAST GPIO for this pin + // + am_hal_gpio_fastgpio_enable(ui32pinnum); + + if ( ui32Masks ) + { + ui32Masks[ux + 0] = _VAL2FLD(APBDMA_BBSETCLEAR_SET, ui32Mask); + ui32Masks[ux + 1] = _VAL2FLD(APBDMA_BBSETCLEAR_CLEAR, ui32Mask); + } + ux += 2; // Get next indexes + } + ui32pinnum++; + ui64PinMask >>= 1; + } + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_fast_pinconfig() + +//***************************************************************************** +// +//! @brief Read GPIO. +//! +//! @param ui32Pin - pin number to be read. +//! @param eReadType - State type to read. One of: +//! AM_HAL_GPIO_INPUT_READ +//! AM_HAL_GPIO_OUTPUT_READ +//! AM_HAL_GPIO_ENABLE_READ +//! @param pui32ReadState - Pointer to the value to contain the read state. +//! When reading the value of a bit, will be either 0 or 1. +//! +//! This function reads a pin state as given by ui32Type. +//! +//! @return Status. +// +//***************************************************************************** +uint32_t +am_hal_gpio_state_read(uint32_t ui32Pin, + am_hal_gpio_read_type_e eReadType, + uint32_t *pui32ReadState) +{ + uint32_t ui32ReadValue = 0xFFFFFFFF; + uint32_t ui32BaseAddr, ui32Shift; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( pui32ReadState == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if ( ui32Pin >= AM_HAL_GPIO_MAX_PADS ) + { + *pui32ReadState = ui32ReadValue; + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Compute base address + offset of 0 or 4. + // + ui32BaseAddr = ((ui32Pin & 0x20) >> 3); // 0 or 4 + ui32Shift = ui32Pin & 0x1F; + + switch ( eReadType ) + { + case AM_HAL_GPIO_INPUT_READ: + // + // Assumes eIntDir != AM_HAL_GPIO_PIN_INTDIR_NONE && + // eIntDir != AM_HAL_GPIO_PIN_INTDIR_BOTH + // If either of those configs are set, returns 0. + // + ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, RDA) + ui32BaseAddr); + ui32ReadValue = (ui32ReadValue >> ui32Shift) & 0x01; + break; + case AM_HAL_GPIO_OUTPUT_READ: + ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, WTA) + ui32BaseAddr); + ui32ReadValue = (ui32ReadValue >> ui32Shift) & 0x01; + break; + case AM_HAL_GPIO_ENABLE_READ: + ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, ENA) + ui32BaseAddr); + ui32ReadValue = (ui32ReadValue >> ui32Shift) & 0x01; + break; + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + *pui32ReadState = ui32ReadValue; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_gpio_state_read() + +//***************************************************************************** +// +//! @brief Write GPIO. +//! +//! @param ui32Pin - pin number to be read. +//! +//! @param ui32Type - State type to write. One of: +//! AM_HAL_GPIO_OUTPUT_SET - Write a one to a GPIO. +//! AM_HAL_GPIO_OUTPUT_CLEAR - Write a zero to a GPIO. +//! AM_HAL_GPIO_OUTPUT_TOGGLE - Toggle the GPIO value. +//! The following two apply when output is set for TriState (OUTCFG==3). +//! AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE - Enable a tri-state GPIO. +//! AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE - Disable a tri-state GPIO. +//! +//! This function writes a GPIO value. +//! +//! @return Status. +//! Fails if the pad is not configured for GPIO (PADFNCSEL != 3). +// +//***************************************************************************** +uint32_t +am_hal_gpio_state_write(uint32_t ui32Pin, am_hal_gpio_write_type_e eWriteType) +{ + uint32_t ui32Mask, ui32Off; + uint32_t ui32Return = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( ui32Pin >= AM_HAL_GPIO_MAX_PADS ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( eWriteType > AM_HAL_GPIO_OUTPUT_TRISTATE_TOGGLE ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Mask = (uint32_t)0x1 << (ui32Pin % 32); + ui32Off = (ui32Pin & 0x20) >> 3; // 0 or 4 + + AM_CRITICAL_BEGIN; + switch ( eWriteType ) + { + case AM_HAL_GPIO_OUTPUT_SET: // Write a one to a GPIO. + AM_REGVAL(AM_REGADDR(GPIO, WTSA) + ui32Off) = ui32Mask; + break; + case AM_HAL_GPIO_OUTPUT_CLEAR: // Write a zero to a GPIO. + AM_REGVAL(AM_REGADDR(GPIO, WTCA) + ui32Off) = ui32Mask; + break; + case AM_HAL_GPIO_OUTPUT_TOGGLE: // Toggle the GPIO value. + AM_REGVAL(AM_REGADDR(GPIO, WTA) + ui32Off) ^= ui32Mask; + break; + case AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE: // Enable a tri-state GPIO. + AM_REGVAL(AM_REGADDR(GPIO, ENSA) + ui32Off) = ui32Mask; + break; + case AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE: // Disable a tri-state GPIO. + AM_REGVAL(AM_REGADDR(GPIO, ENCA) + ui32Off) = ui32Mask; + break; + case AM_HAL_GPIO_OUTPUT_TRISTATE_TOGGLE: // Toggle a tri-state GPIO. + AM_REGVAL(AM_REGADDR(GPIO, ENCA) + ui32Off) ^= ui32Mask; + break; + default: + // Type values were validated on entry. + // We can't return from here because we're in a critical section. + ui32Return = AM_HAL_STATUS_INVALID_ARG; + break; + } + + AM_CRITICAL_END; + + return ui32Return; +} // am_hal_gpio_state_write() + +//***************************************************************************** +// +// Enable GPIO interrupts. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_enable(uint64_t ui64InterruptMask) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui64InterruptMask & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1) ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Enable the interrupts. + // + AM_CRITICAL_BEGIN + + GPIO->INT0EN |= (uint32_t)(ui64InterruptMask & 0xFFFFFFFF); + GPIO->INT1EN |= (uint32_t)(ui64InterruptMask >> 32); + + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_enable() + +//***************************************************************************** +// +// Disable GPIO interrupts. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_disable(uint64_t ui64InterruptMask) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui64InterruptMask & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1) ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Disable the interrupts. + // + AM_CRITICAL_BEGIN + + GPIO->INT0EN &= ~((uint32_t)(ui64InterruptMask & 0xFFFFFFFF)); + GPIO->INT1EN &= ~((uint32_t)(ui64InterruptMask >> 32)); + + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_disable() + +//***************************************************************************** +// +// Clear GPIO interrupts. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_clear(uint64_t ui64InterruptMask) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui64InterruptMask & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1) ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Clear the interrupts. + // + AM_CRITICAL_BEGIN + + GPIO->INT0CLR = (uint32_t)(ui64InterruptMask & 0xFFFFFFFF); + GPIO->INT1CLR = (uint32_t)(ui64InterruptMask >> 32); + + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_clear() + +//***************************************************************************** +// +// Get GPIO interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_status_get(bool bEnabledOnly, uint64_t *pui64IntStatus) +{ + + uint64_t ui64RetVal, ui64Mask; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( pui64IntStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Initialize variable outside critical section + // + ui64Mask = 0xFFFFFFFFFFFFFFFF; + + // + // Combine upper or lower GPIO words into one 64 bit return value. + // + AM_CRITICAL_BEGIN + + ui64RetVal = ((uint64_t)GPIO->INT1STAT) << 32; + ui64RetVal |= ((uint64_t)GPIO->INT0STAT) << 0; + + if ( bEnabledOnly ) + { + ui64Mask = ((uint64_t)GPIO->INT1EN) << 32; + ui64Mask |= ((uint64_t)GPIO->INT0EN) << 0; + } + + ui64RetVal &= ui64Mask; + + *pui64IntStatus = ui64RetVal; + + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_status_get() + +//***************************************************************************** +// +// GPIO interrupt service routine registration. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_register(uint32_t ui32GPIONumber, + am_hal_gpio_handler_t pfnHandler) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( pfnHandler == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Store the handler function pointer. + // + gpio_ppfnHandlers[ui32GPIONumber] = pfnHandler; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_register() + +//***************************************************************************** +// +//! @brief Advanced GPIO interrupt service routine registration. +//! +//! @param ui32GPIONumber - GPIO number (0-49) to be registered. +//! +//! @param pfnHandler - Function pointer to the callback. +//! +//! @param pCtxt - context for the callback. +//! +//! @return Status. +//! Fails if pfnHandler is NULL or ui32GPIONumber > 49. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_register_adv(uint32_t ui32GPIONumber, + am_hal_gpio_handler_adv_t pfnHandler, void *pCtxt) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( pfnHandler == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Store the handler function pointer. + // + gpio_ppfnHandlers[ui32GPIONumber] = (am_hal_gpio_handler_t)((uint32_t)pfnHandler & ~0x1); + gpio_pHandlerCtxt[ui32GPIONumber] = pCtxt; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_register_adv() + +//***************************************************************************** +// +// GPIO interrupt service routine. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_service(uint64_t ui64Status) +{ + uint32_t ui32RetStatus = AM_HAL_STATUS_SUCCESS; + uint32_t ui32Status, ui32Clz, ui32FFS, ui32Cnt; + + am_hal_gpio_handler_t pfnHandler; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui64Status & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1) ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( ui64Status == 0 ) + { + return AM_HAL_STATUS_FAIL; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Handle interrupts. + // The 1st iteration handles any active interrupts in the lower 32 bits. + // The 2nd iteration handles any active interrupts in the upper 32 bits. + // (The order of handling upper or lower bits is somewhat arbitrary.) + // + ui32Cnt = 0; + while ( ui32Cnt < 33 ) + { + // + // Get upper or lower status word. + // + ui32Status = (uint32_t)(ui64Status >> ui32Cnt); + + while ( ui32Status ) + { + // + // We need to FFS (Find First Set). We can easily zero-base FFS + // since we know that at least 1 bit is set in ui32Status. + // FFS(x) = 31 - clz(x & -x). // Zero-based version of FFS. + // + ui32FFS = ui32Status & (uint32_t)(-(int32_t)ui32Status); +#ifdef __IAR_SYSTEMS_ICC__ + ui32Clz = __CLZ(ui32FFS); +#else + ui32Clz = __builtin_clz(ui32FFS); +#endif + ui32FFS = 31 - ui32Clz; + + // + // Turn off the bit we picked in the working copy + // + ui32Status &= ~(0x00000001 << ui32FFS); + + // + // Check the bit handler table to see if there is an interrupt handler + // registered for this particular bit. + // + pfnHandler = gpio_ppfnHandlers[ui32Cnt + ui32FFS]; + if ( pfnHandler ) + { + // + // If we found an interrupt handler routine, call it now. + // + if ((uint32_t)pfnHandler & 0x1) + { + pfnHandler(); + } + else + { + am_hal_gpio_handler_adv_t padvHandler = (am_hal_gpio_handler_adv_t)((uint32_t)pfnHandler | 0x1); + padvHandler(gpio_pHandlerCtxt[ui32Cnt + ui32FFS]); + } + } + else + { + // + // No handler was registered for the GPIO that interrupted. + // Return an error. + // + ui32RetStatus = AM_HAL_STATUS_INVALID_OPERATION; + } + } + ui32Cnt += 32; + } + + // + // Return the status. + // + return ui32RetStatus; + +} // am_hal_gpio_interrupt_service() + + +//***************************************************************************** +// +//! @brief Configure an Apollo3 pin. +//! +//! @param ui32Pin - pin number to be configured. +//! @param ui32Config - Contains multiple descriptor fields. +//! +//! This function configures a pin according to the parameters in ui32Config. +//! All parameters are validated, and the given pin is configured according +//! to the designated parameters. +//! +//! @return Status. +// +//***************************************************************************** +uint32_t ap3_hal_gpio_pinconfig_partial(uint32_t ui32Pin, am_hal_gpio_pincfg_t bfGpioCfg, am_hal_gpio_pincfg_allow_t sAllowableChanges) //am_hal_gpio_pincfg_t bfGpioCfgMsk) +{ + uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg; + uint32_t ui32Funcsel, ui32PowerSw; + uint8_t padRegMask = 0, GPCfgMask = 0, altPadCfgMask = 0; + bool bClearEnable = false; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (ui32Pin >= AM_HAL_GPIO_MAX_PADS) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + ap3_gpio_get_pinconfig_bitmasks(sAllowableChanges, &padRegMask, &GPCfgMask, &altPadCfgMask); + // + // Initialize the PADREG accumulator variables. + // + ui32GPCfg = ui32Padreg = ui32AltPadCfg = 0; + + // + // Get the requested function and/or power switch. + // + ui32Funcsel = bfGpioCfg.uFuncSel; + ui32PowerSw = bfGpioCfg.ePowerSw; + + ui32Padreg |= ui32Funcsel << PADREG_FLD_FNSEL_S; + + // + // Check for invalid configuration requests. + // + if (bfGpioCfg.ePullup != AM_HAL_GPIO_PIN_PULLUP_NONE) + { + // + // This setting is needed for all pullup settings including + // AM_HAL_GPIO_PIN_PULLUP_WEAK and AM_HAL_GPIO_PIN_PULLDOWN. + // + ui32Padreg |= (0x1 << PADREG_FLD_PULLUP_S); + + // + // Check for specific pullup or pulldown settings. + // + if ((bfGpioCfg.ePullup >= AM_HAL_GPIO_PIN_PULLUP_1_5K) && + (bfGpioCfg.ePullup <= AM_HAL_GPIO_PIN_PULLUP_24K)) + { + ui32Padreg |= ((bfGpioCfg.ePullup - AM_HAL_GPIO_PIN_PULLUP_1_5K) << PADREG_FLD_76_S); +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!(g_ui8Bit76Capabilities[ui32Pin] & CAP_PUP)) + { + return AM_HAL_GPIO_ERR_PULLUP; + } + } + else if (bfGpioCfg.ePullup == AM_HAL_GPIO_PIN_PULLDOWN) + { + if (ui32Pin != 20) + { + return AM_HAL_GPIO_ERR_PULLDOWN; + } + } + else if (bfGpioCfg.ePullup == AM_HAL_GPIO_PIN_PULLUP_WEAK) + { + // + // All pads except 20 support a weak pullup, for which we only need + // to set PADnPULL and clear 7:6 (already done at this point). + // + if (ui32Pin == 20) + { + return AM_HAL_GPIO_ERR_PULLUP; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + } + } + + // + // Check if requesting a power switch pin + // + if (ui32PowerSw != AM_HAL_GPIO_PIN_POWERSW_NONE) + { + if ((ui32PowerSw == AM_HAL_GPIO_PIN_POWERSW_VDD) && + (g_ui8Bit76Capabilities[ui32Pin] & CAP_VDD)) + { + ui32Padreg |= 0x1 << PADREG_FLD_76_S; + } + else if ((ui32PowerSw == AM_HAL_GPIO_PIN_POWERSW_VSS) && + (g_ui8Bit76Capabilities[ui32Pin] & CAP_VSS)) + { + ui32Padreg |= 0x2 << PADREG_FLD_76_S; + } + else + { + return AM_HAL_GPIO_ERR_PWRSW; + } + } + + // + // Depending on the selected pin and FNSEL, determine if INPEN needs to be set. + // + ui32Padreg |= (g_ui8Inpen[ui32Pin] & (1 << ui32Funcsel)) ? (1 << PADREG_FLD_INPEN_S) : 0; + + // + // Configure ui32GpCfg based on whether nCE requested. + // + if (g_ui8nCEpins[ui32Pin] == ui32Funcsel) + { + uint32_t ui32Outcfg; + uint8_t ui8CEtbl; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // User is configuring a nCE. Verify the requested settings and set the + // polarity and OUTCFG values (INCFG is not used here and should be 0). + // Valid uNCE values are 0-3 (uNCE is a 2-bit field). + // Valid uIOMnum are 0-6 (0-5 for IOMs, 6 for MSPI, 7 is invalid). + // + if (bfGpioCfg.uIOMnum > IOMNUM_MAX) + { + return AM_HAL_GPIO_ERR_INVCE; // Invalid CE specified + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Construct the entry we expect to find in the table. We can determine + // the OUTCFG value by looking for that value in the pin row. + // + ui8CEtbl = (bfGpioCfg.uIOMnum << 4) | bfGpioCfg.uNCE; + for (ui32Outcfg = 0; ui32Outcfg < 4; ui32Outcfg++) + { + if (g_ui8NCEtable[ui32Pin][ui32Outcfg] == ui8CEtbl) + { + break; + } + } + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (ui32Outcfg >= 4) + { + return AM_HAL_GPIO_ERR_INVCEPIN; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32GPCfg |= (ui32Outcfg << GPIOCFG_FLD_OUTCFG_S) | + (bfGpioCfg.eCEpol << GPIOCFG_FLD_INTD_S) | + (0 << GPIOCFG_FLD_INCFG_S); + } + else + { + // + // It's not nCE, it's one of the other funcsels. + // Start by setting the value of the requested GPIO input. + // + ui32Padreg |= (bfGpioCfg.eGPInput << PADREG_FLD_INPEN_S); + + // + // Map the requested interrupt direction settings into the Apollo3 + // GPIOCFG register field, which is a 4-bit field: + // [INTD(1):OUTCFG(2):INCFG(1)]. + // Bit0 of eIntDir maps to GPIOCFG.INTD (b3). + // Bit1 of eIntDir maps to GPIOCFG.INCFG (b0). + // + ui32GPCfg |= (bfGpioCfg.eGPOutcfg << GPIOCFG_FLD_OUTCFG_S) | + (((bfGpioCfg.eIntDir >> 0) & 0x1) << GPIOCFG_FLD_INTD_S) | + (((bfGpioCfg.eIntDir >> 1) & 0x1) << GPIOCFG_FLD_INCFG_S); + + if ((bfGpioCfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL) || + pincfg_equ(&bfGpioCfg, (void *)&g_AM_HAL_GPIO_DISABLE)) + { + // + // For pushpull configurations, we must be sure to clear the ENABLE + // bit. In pushpull, these bits turn on FAST GPIO. For regular + // GPIO, they must be clear. + // + bClearEnable = true; + } + + // + // There is some overlap between eGPRdZero and eIntDir as both settings + // utilize the overloaded INCFG bit. + // Therefore the two fields should be used in a mutually exclusive + // manner. For flexibility however they are not disallowed because + // their functionality is dependent on FUNCSEL and whether interrupts + // are used. + // + // In the vein of mutual exclusion, eGPRdZero is primarily intended for + // use when GPIO interrupts are not in use and can be used when no + // eIntDir setting is provided. + // If eIntDir is provided, eGPRdZero is ignored and can only be + // achieved via the AM_HAL_GPIO_PIN_INTDIR_NONE setting. + // + if (bfGpioCfg.eIntDir == 0) + { + ui32GPCfg &= ~(1 << GPIOCFG_FLD_INCFG_S); + ui32GPCfg |= (bfGpioCfg.eGPRdZero << GPIOCFG_FLD_INCFG_S); + } + } + + switch (bfGpioCfg.eDriveStrength) + { + // DRIVESTRENGTH is a 2-bit field. + // bit0 maps to bit2 of a PADREG field. + // bit1 maps to bit0 of an ALTPADCFG field. + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA: + ui32Padreg |= (0 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (0 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA: + ui32Padreg |= (1 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (0 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA: + ui32Padreg |= (0 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (1 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA: + ui32Padreg |= (1 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (1 << 0); + break; + } + + // + // At this point, the 3 configuration variables, ui32GPCfg, ui32Padreg, + // and ui32AltPadCfg values are set (at bit position 0) and ready to write + // to their respective register bitfields. + // + uint32_t ui32GPCfgAddr, ui32PadregAddr, ui32AltpadAddr; + uint32_t ui32GPCfgClearMask, ui32PadClearMask, ui32AltPadClearMask; + uint32_t ui32GPCfgShft, ui32PadShft; + + ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3); + ui32PadregAddr = AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3); + ui32AltpadAddr = AM_REGADDR(GPIO, ALTPADCFGA) + (ui32Pin & ~0x3); + + ui32GPCfgShft = ((ui32Pin & 0x7) << 2); + ui32PadShft = ((ui32Pin & 0x3) << 3); + ui32GPCfgClearMask = ~((uint32_t)GPCfgMask << ui32GPCfgShft); + ui32PadClearMask = ~((uint32_t)padRegMask << ui32PadShft); + ui32AltPadClearMask = ~((uint32_t)altPadCfgMask << ui32PadShft); + + // + // Get the new values into their rightful bit positions. + // + ui32Padreg = (ui32Padreg & (uint32_t)padRegMask) << ui32PadShft; + ui32AltPadCfg = (ui32AltPadCfg & (uint32_t)altPadCfgMask) << ui32PadShft; + ui32GPCfg = (ui32GPCfg & (uint32_t)GPCfgMask) << ui32GPCfgShft; + + AM_CRITICAL_BEGIN + + if (bClearEnable) + { + // + // We're configuring a mode that requires clearing the Enable bit. + // + am_hal_gpio_output_tristate_disable(ui32Pin); + } + + GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key; + + AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) | ui32Padreg; + AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg; + AM_REGVAL(ui32AltpadAddr) = (AM_REGVAL(ui32AltpadAddr) & ui32AltPadClearMask) | ui32AltPadCfg; + + GPIO->PADKEY = 0; + + AM_CRITICAL_END + + return AM_HAL_STATUS_SUCCESS; + +} //ap3_hal_gpio_pinconfig_partial + +void ap3_gpio_get_pinconfig_bitmasks(am_hal_gpio_pincfg_allow_t sAllowableChanges, uint8_t *padRegMask, uint8_t *GPCfgMask, uint8_t *altPadCfgMask) +{ + *padRegMask = 0; + *GPCfgMask = 0; + *altPadCfgMask = 0; + + if (sAllowableChanges.uFuncSel) + { + *padRegMask |= 0x38; //bits 3-5 PadReg + } + if (sAllowableChanges.ePowerSw) + { + *padRegMask |= 0xC0; //bits 6 and 7 PadReg + } + if (sAllowableChanges.ePullup) + { + *padRegMask |= 0xC1; //bits 6 and 7 and 0 PadReg + } + if (sAllowableChanges.eDriveStrength) + { + *padRegMask |= 0x04; //bit 2 PadReg + *altPadCfgMask |= 0x10; //bit 4 AltPadReg + } + if (sAllowableChanges.eGPOutcfg) + { + *GPCfgMask |= 0x06; //bits 1 and 2 CFGReg + } + if (sAllowableChanges.eGPInput) + { + *padRegMask |= 0x02; //bit 1 PadReg + } + if (sAllowableChanges.eIntDir) + { + *GPCfgMask |= 0x09; //bit 0 and 3 CFGReg + } + if (sAllowableChanges.eGPRdZero) + { + *GPCfgMask |= 0x01; //bit 0 CFGReg + } +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.h new file mode 100644 index 0000000..648a40f --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.h @@ -0,0 +1,899 @@ +//***************************************************************************** +// +// am_hal_gpio.h +//! @file +//! +//! @brief Functions for accessing and configuring the GPIO module. +//! +//! @addtogroup gpio3 GPIO +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_GPIO_H +#define AM_HAL_GPIO_H 1 + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Designate this peripheral. +// +#define AM_APOLLO3_GPIO 1 + +// +// Maximum number of GPIOs on this device +// +#define AM_HAL_GPIO_MAX_PADS (50) +#define AM_HAL_GPIO_NUMWORDS ((AM_HAL_GPIO_MAX_PADS + 31) / 32) + +// +//! Macros to assist with defining a GPIO mask given a GPIO number. +//! +//! IMPORTANT: AM_HAL_GPIO_BIT(n) is DEPRECATED and is provided only for +//! backward compatibility. It is replaced with AM_HAL_GPIO_MASKBIT(). +// +#define AM_HAL_GPIO_BIT(n) (((uint64_t) 0x1) << n) /* DEPRECATED, PLEASE USE AM_HAL_GPIO_MASKBIT() */ + +//! +//! The following macros ensure forward compatibility with future SDK releases. +//! They should be used, in lieu of AM_HAL_GPIO_BIT(), when creating bitmasks +//! for GPIO interrupts. +//! AM_HAL_GPIO_MASKCREATE() +//! AM_HAL_GPIO_MASKBIT() +//! + +#define AM_HAL_GPIO_MASKCREATE(sMaskNm) uint64_t p##sMaskNm=0 +//! AM_HAL_GPIO_MASKCREATE() should be used before AM_HAL_GPIO_MASKBIT() to +//! ensure forward compatibility. In future releases it will allocate and +//! initialize a bitmask structure used in the various GPIO interrupt functions. +//! + +// Implented as an inline function below. +//#define AM_HAL_GPIO_MASKBIT(psMaskNm, n) (psMaskNm |= (((uint64_t) 0x1) << n)) +#define AM_HAL_GPIO_MASKBIT(psMaskNm, n) psMaskNm |= (((uint64_t) 0x1) << n) +//! AM_HAL_GPIO_MASKBIT(psMaskNm, n) +//! Support macros for use with AM_HAL_GPIO_MASKBIT(). +//! AM_HAL_GPIO_MASKCREATE() +//! AM_HAL_GPIO_MASKCLR() +//! +//! To set a single bit based on a pin number in an existing bitmask structure. +//! AM_HAL_GPIO_MASKBIT(pGpioIntMask, n) +//! where n is the desired GPIO bit number. +//! Note - this usage is analogous to the deprecated AM_HAL_GPIO_BIT(n). +//! + +#define AM_HAL_GPIO_MASKCLR(psMaskNm) +//! AM_HAL_GPIO_MASKCLR() +//! Clear an existing GpioIntMask bitmask structure. +//! Note that AM_HAL_GPIO_MASKCREATE() clears the bitmask struct on creation. +//! IMPORTANT - The AM_HAL_GPIO_MASKCLR() macro does not operate on any hardware +//! or register. It is used for initializing/clearing the memory allocated for +//! the bitmask structure. +//! +//! // Usage example for any Apollo device: +//! // Create a GPIO interrupt bitmask structure named GpioIntMask, initialize +//! // that structure, and create a ptr to that structure named pGpioIntMask. +//! // Then use that structure to pass a bitmask to the interrupt function. +//! AM_HAL_GPIO_MASKCREATE(GpioIntMask); +//! am_hal_gpio_interrupt_clear(AM_HAL_GPIO_MASKBIT(pGpioIntMask)); +//! + +//***************************************************************************** +//! +//! Structure for defining bitmasks used in the interrupt functions. +//! +//***************************************************************************** +typedef struct // Future use - not currently used for Apollo3. +{ + union + { + volatile uint32_t Msk[AM_HAL_GPIO_NUMWORDS]; + + struct + { + volatile uint32_t b0: 1; + volatile uint32_t b1: 1; + volatile uint32_t b2: 1; + volatile uint32_t b3: 1; + volatile uint32_t b4: 1; + volatile uint32_t b5: 1; + volatile uint32_t b6: 1; + volatile uint32_t b7: 1; + volatile uint32_t b8: 1; + volatile uint32_t b9: 1; + volatile uint32_t b10: 1; + volatile uint32_t b11: 1; + volatile uint32_t b12: 1; + volatile uint32_t b13: 1; + volatile uint32_t b14: 1; + volatile uint32_t b15: 1; + volatile uint32_t b16: 1; + volatile uint32_t b17: 1; + volatile uint32_t b18: 1; + volatile uint32_t b19: 1; + volatile uint32_t b20: 1; + volatile uint32_t b21: 1; + volatile uint32_t b22: 1; + volatile uint32_t b23: 1; + volatile uint32_t b24: 1; + volatile uint32_t b25: 1; + volatile uint32_t b26: 1; + volatile uint32_t b27: 1; + volatile uint32_t b28: 1; + volatile uint32_t b29: 1; + volatile uint32_t b30: 1; + volatile uint32_t b31: 1; + volatile uint32_t b32: 1; + volatile uint32_t b33: 1; + volatile uint32_t b34: 1; + volatile uint32_t b35: 1; + volatile uint32_t b36: 1; + volatile uint32_t b37: 1; + volatile uint32_t b38: 1; + volatile uint32_t b39: 1; + volatile uint32_t b40: 1; + volatile uint32_t b41: 1; + volatile uint32_t b42: 1; + volatile uint32_t b43: 1; + volatile uint32_t b44: 1; + volatile uint32_t b45: 1; + volatile uint32_t b46: 1; + volatile uint32_t b47: 1; + volatile uint32_t b48: 1; + volatile uint32_t b49: 1; + volatile uint32_t brsvd: 14; // Pad out to the next full word + } Msk_b; + } U; +} am_hal_gpio_mask_t; + +//***************************************************************************** +//! +//! Read types for am_hal_gpio_state_read(). +//! +//***************************************************************************** +typedef enum +{ + AM_HAL_GPIO_INPUT_READ, + AM_HAL_GPIO_OUTPUT_READ, + AM_HAL_GPIO_ENABLE_READ +} am_hal_gpio_read_type_e; + +//***************************************************************************** +//! +//! Write types for am_hal_gpio_state_write(). +//! +//***************************************************************************** +typedef enum +{ + AM_HAL_GPIO_OUTPUT_CLEAR, + AM_HAL_GPIO_OUTPUT_SET, + AM_HAL_GPIO_OUTPUT_TOGGLE, + AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE, + AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE, + AM_HAL_GPIO_OUTPUT_TRISTATE_TOGGLE +} am_hal_gpio_write_type_e; + + +//***************************************************************************** +//! +//! Types for ui32GpioCfg bitfields in am_hal_gpio_pinconfig(). +//! +//***************************************************************************** +//! +//! Power Switch configuration: am_hal_gpio_pincfg_t.ePowerSw enums +//! +typedef enum +{ + AM_HAL_GPIO_PIN_POWERSW_NONE, + AM_HAL_GPIO_PIN_POWERSW_VDD, + AM_HAL_GPIO_PIN_POWERSW_VSS, + AM_HAL_GPIO_PIN_POWERSW_INVALID, +} am_hal_gpio_powersw_e; + +//! +//! Pullup configuration: am_hal_gpio_pincfg_t.ePullup enums +//! +typedef enum +{ + // + //! Define pullup enums. + //! The 1.5K - 24K pullup values are valid for select I2C enabled pads. + //! For Apollo3 these pins are 0-1,5-6,8-9,25,27,39-40,42-43,48-49. + //! The "weak" value is used for almost every other pad except pin 20. + // + AM_HAL_GPIO_PIN_PULLUP_NONE = 0x00, + AM_HAL_GPIO_PIN_PULLUP_WEAK, + AM_HAL_GPIO_PIN_PULLUP_1_5K, + AM_HAL_GPIO_PIN_PULLUP_6K, + AM_HAL_GPIO_PIN_PULLUP_12K, + AM_HAL_GPIO_PIN_PULLUP_24K, + AM_HAL_GPIO_PIN_PULLDOWN +} am_hal_gpio_pullup_e; + +//! +//! Pad Drive Strength configuration: am_hal_gpio_pincfg_t.eDriveStrength enums +//! +typedef enum +{ + // + //! DRIVESTRENGTH is a 2-bit field. + //! bit0 maps to bit2 of a PADREG field. + //! bit1 maps to bit0 of an ALTPADCFG field. + // + AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA = 0x0, + AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA = 0x1, + AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA = 0x2, + AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA = 0x3 +} am_hal_gpio_drivestrength_e; + +//! +//! OUTCFG pad configuration: am_hal_gpio_pincfg_t.eGPOutcfg enums +//! Applies only to GPIO configured pins. +//! Ultimately maps to GPIOCFG.OUTCFG, bits [2:1]. +//! +typedef enum +{ + AM_HAL_GPIO_PIN_OUTCFG_DISABLE = 0x0, + AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL = 0x1, + AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN = 0x2, + AM_HAL_GPIO_PIN_OUTCFG_TRISTATE = 0x3 +} am_hal_gpio_outcfg_e; + +//! +//! GPIO input configuration: am_hal_gpio_pincfg_t.eGPInput enums +//! Applies only to GPIO configured pins! +//! Ultimately maps to PADREG.INPEN, bit1. +//! +typedef enum +{ + AM_HAL_GPIO_PIN_INPUT_AUTO = 0x0, + AM_HAL_GPIO_PIN_INPUT_NONE = 0x0, + AM_HAL_GPIO_PIN_INPUT_ENABLE = 0x1 +} am_hal_gpio_input_e; + +//! +//! GPIO interrupt direction configuration: am_hal_gpio_pincfg_t.eIntDir enums +//! Note: Setting INTDIR_NONE has the side-effect of disabling being able to +//! read a pin - the pin will always read back as 0. +//! +typedef enum +{ + // Bit1 of these values maps to GPIOCFG.INCFG (b0). + // Bit0 of these values maps to GPIOCFG.INTD (b3). + AM_HAL_GPIO_PIN_INTDIR_LO2HI = 0x0, + AM_HAL_GPIO_PIN_INTDIR_HI2LO = 0x1, + AM_HAL_GPIO_PIN_INTDIR_NONE = 0x2, + AM_HAL_GPIO_PIN_INTDIR_BOTH = 0x3 +} am_hal_gpio_intdir_e; + +//! +//! am_hal_gpio_pincfg_t.eGPRdZero +//! For GPIO configurations (funcsel=3), the pin value can be read or 0 can be +//! forced as the read value. +//! +typedef enum +{ + AM_HAL_GPIO_PIN_RDZERO_READPIN = 0x0, + AM_HAL_GPIO_PIN_RDZERO_ZERO = 0x1 +} am_hal_gpio_readen_e; + +//! +//! nCE polarity configuration: am_hal_gpio_pincfg_t.eCEpol enums +//! +typedef enum +{ + AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW = 0x0, + AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH = 0x1 +} am_hal_gpio_cepol_e; + + +// +// Apollo3 usage of bits [7:6] of a PADREG field: +// PULLUPs are available on pins: 0,1,5,6,8,9,25,27,39,40,42,43,48,49 +// RESERVED on pins: 2,4,7,10-24,26,28-35,38,44-47 +// VDD PWR on pins: 3, 36 (b7=0, b6=1) +// VSS PWR on pins: 37,41 (b7=1, b6=0) +// + +//! +//! Define the am_hal_gpio_pinconfig() bitfield structure. +//! uFuncSel a value of 0-7 corresponding to the FNCSEL field of PADREG. +//! ePowerSw: Select pins can be set as a power source or sink. +//! ePullup: Select pins can enable a pullup of varying values. +//! eDriveStrength: Select pins can be set for varying drive strengths. +//! eGPOutcfg: GPIO pin only, corresponds to GPIOCFG.OUTCFG field. +//! eGPInput: GPIO pin only, corresponds to PADREG.INPEN. +//! eGPRdZero: GPIO read zero. Corresponds to GPIOCFG.INCFG. +//! eIntDir: Interrupt direction, l2h, h2l, both, none. +//! eGPRdZero: Read the pin value, or always read the pin as zero. +//! uIOMnum: nCE pin IOMnumber (0-5, or 6 for MSPI) +//! nNCE: Selects the SPI channel (CE) number (0-3) +//! eCEpol: CE polarity. +//! +typedef struct +{ + uint32_t uFuncSel : 3; // [2:0] Function select (FUNCSEL) + uint32_t ePowerSw : 2; // [4:3] Pin is a power switch source (VCC) or sink (VSS) + uint32_t ePullup : 3; // [7:5] Pin will enable a pullup resistor + uint32_t eDriveStrength : 2; // [9:8] Pad strength designator + uint32_t eGPOutcfg : 2; // [11:10] OUTCFG (GPIO config only) + uint32_t eGPInput : 1; // [12:12] GPIO Input (GPIO config only) + uint32_t eIntDir : 2; // [14:13] Interrupt direction + uint32_t eGPRdZero : 1; // [15:15] GPIO read as zero + + // + // The following descriptors designate the chip enable features of the + // pin being configured. If not a CE, these descriptors are ignored. + // uIOMnum is 0-5 for the IOMs, or 6 for MSPI, 7 is invalid. + // + uint32_t uIOMnum : 3; // [18:16] IOM number (0-5), 6 for MSPI + uint32_t uNCE : 2; // [20:19] NCE number (0-3). + uint32_t eCEpol : 1; // [21:21] NCE polarity. + + uint32_t uRsvd22 : 10; // [31:22] +} am_hal_gpio_pincfg_t; + +typedef struct +{ + uint16_t uFuncSel : 1; + uint16_t ePowerSw : 1; + uint16_t ePullup : 1; + uint16_t eDriveStrength : 1; + uint16_t eGPOutcfg : 1; + uint16_t eGPInput : 1; + uint16_t eIntDir : 1; + uint16_t eGPRdZero : 1; + uint16_t uIOMnum : 1; + uint16_t uNCE : 1; + uint16_t eCEpol : 1; + + uint16_t _reserved : 5; +} am_hal_gpio_pincfg_allow_t; + +#define IOMNUM_MSPI 6 +#define IOMNUM_MAX IOMNUM_MSPI + +// +// Define shift and width values for the above bitfields. +// - C bitfields do not provide shift, width, or mask values. +// - Shift values are generally compiler specific. However for IAR, Keil, and +// GCC, the bitfields are all exactly as defined in the above structure. +// - These defines should be used sparingly. +// +#define UFUNCSEL_S 0 +#define EPOWERSW_S 3 +#define EPULLUP_S 5 +#define EDRVSTR_S 8 +#define EGPOUTCFG_S 10 +#define EGPINPUT_S 12 +#define EINTDIR_S 13 +#define UIOMNUM_S 16 +#define UNCE_S 19 +#define ECEPOL_S 21 + +#define UFUNCSEL_W 3 +#define EPOWERSW_W 2 +#define EPULLUP_W 3 +#define EDRVSTR_W 2 +#define EGPOUTCFG_W 2 +#define EGPINPUT_W 1 +#define EINTDIR_W 2 +#define UIOMNUM_W 3 +#define UNCE_W 2 +#define ECEPOL_W 1 + +//! +//! Define GPIO error codes that are returned by am_hal_gpio_pinconfig(). +//! +enum am_hal_gpio_pincfgerr +{ + AM_HAL_GPIO_ERR_PULLUP = (AM_HAL_STATUS_MODULE_SPECIFIC_START + 0x100), + AM_HAL_GPIO_ERR_PULLDOWN, + AM_HAL_GPIO_ERR_PWRSW, + AM_HAL_GPIO_ERR_INVCE, + AM_HAL_GPIO_ERR_INVCEPIN, + AM_HAL_GPIO_ERR_PULLUPENUM +}; + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +//***************************************************************************** +// Define some common GPIO pin configurations. +//***************************************************************************** +//! Basics +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_DISABLE; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_TRISTATE; + +//! Input variations +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT; +//! Input with various pullups (weak, 1.5K, 6K, 12K, 24K) +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_1_5; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_6; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_12; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_24; + +//! Output variations +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_4; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_8; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_12; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_WITH_READ; + +//***************************************************************************** +// +// Function pointer type for GPIO interrupt handlers. +// +//***************************************************************************** +typedef void (*am_hal_gpio_handler_t)(void); +typedef void (*am_hal_gpio_handler_adv_t)(void *); + +//***************************************************************************** +// +//! @brief Configure an Apollo3 pin. +//! +//! @param ui32Pin - pin number to be configured. +//! @param ui32GpioCfg - Contains multiple descriptor fields. +//! +//! This function configures a pin according to the descriptor parameters as +//! passed in sPinCfg. All parameters are validated with regard to each +//! other and according to the requested function. Once the parameters and +//! settings have been confirmed, the pin is configured accordingly. +//! +//! @return Status. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_pinconfig(uint32_t ui32Pin, + am_hal_gpio_pincfg_t sPincfg); + +//***************************************************************************** +// +//! @brief Configure specified pins for FAST GPIO operation. +//! +//! @param ui64PinMask - a mask specifying up to 8 pins to be configured and +//! used for FAST GPIO (only bits 0-49 are valid). +//! @param bfGpioCfg - The GPIO configuration (same as am_hal_gpio_pinconfig()). +//! All of the pins specified by ui64PinMask will be set to this +//! configuration. +//! @param ui32Masks - If NULL, not used. Otherwise if provided, an array to +//! receive two 32-bit values, per pin, of the SET and CLEAR +//! masks that can be used for the BBSETCLEAR register. +//! The two 32-bit values will be placed at incremental indexes. +//! For example, say pin numbers 5 and 19 are indicated in the +//! mask, and an array pointer is provided in ui32Masks. This +//! array must be allocated by the caller to be at least 4 wds. +//! ui32Masks[0] = the set mask used for pin 5. +//! ui32Masks[1] = the clear mask used for pin 5. +//! ui32Masks[2] = the set mask used for pin 19. +//! ui32Masks[3] = the clear mask used for pin 19. +//! +//! @return Status. +//! +//! Fast GPIO helper macros: +//! am_hal_gpio_fastgpio_set(n) - Sets the value for pin number 'n'. +//! am_hal_gpio_fastgpio_clr(n) - Clear the value for pin number 'n'. +//! +//! am_hal_gpio_fastgpio_enable(n) - Enable Fast GPIO on pin 'n'. +//! am_hal_gpio_fastgpio_disable(n) - Disable Fast GPIO on pin 'n'. +//! +//! Note - The enable and disable macros assume the pin has already been +//! configured. Once disabled, the state of the pin will revert to the +//! state of the normal GPIO configuration for that pin. +//! +//! NOTES on pin configuration: +//! - To avoid glitches on the pin, it is strongly recommended that before +// calling am_hal_gpio_fast_pinconfig() that am_hal_gpio_fastgpio_disable() +//! first be called to make sure that Fast GPIO is disabled before config. +//! - If the state of the pin is important, preset the value of the pin to the +//! desired value BEFORE calling am_hal_gpio_fast_pinconfig(). The set and +//! clear macros shown above can be used for this purpose. +//! +//! NOTES on general use of Fast GPIO: +//! Fast GPIO input or output will not work if the pin is configured as +//! tristate. The overloaded OUTPUT ENABLE control is used for enabling both +//! modes, so Apollo3 logic specifically disallows Fast GPIO input or output +//! when the pin is configured for tristate mode. +//! Fast GPIO input can be used for pushpull, opendrain, or disable modes. +//! +//! Fast GPIO pin groupings: +//! The FaST GPIO pins are grouped across a matrix of pins. Each +//! row of pins is controlled by a single data bit. +//! +//! Referring to the below chart: +//! If pin 35 were configured for Fast GPIO output, it would be set +//! when bit3 of BBSETCLEAR.SET was written with a 1. +//! It would be cleared when bit3 of BBSETCLEAR.CLEAR was written with 1. +//! +//! Note that if all the pins in a row were configured for Fast GPIO output, +//! all the pins would respond to set/clear. +//! +//! Input works in a similar fashion. +//! +//! BIT PIN controlled +//! --- --------------------------- +//! 0 0 8 16 24 32 40 48 +//! 1 1 9 17 25 33 41 49 +//! 2 2 10 18 26 34 42 +//! 3 3 11 19 27 35 43 +//! 4 4 12 20 28 36 44 +//! 5 5 13 21 29 37 45 +//! 6 6 14 22 30 38 46 +//! 7 7 15 23 31 39 47 +//! +// +//***************************************************************************** +extern uint32_t am_hal_gpio_fast_pinconfig(uint64_t ui64PinMask, + am_hal_gpio_pincfg_t bfGpioCfg, + uint32_t ui32Masks[]); + +//***************************************************************************** +// +//! @brief Read GPIO. +//! +//! @param ui32Pin - pin number to be read. +//! @param eReadType - State type to read. One of: +//! AM_HAL_GPIO_INPUT_READ +//! AM_HAL_GPIO_OUTPUT_READ +//! AM_HAL_GPIO_ENABLE_READ +//! +//! This function reads a pin state as given by eReadType. +//! +//! @return Status. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_state_read(uint32_t ui32Pin, + am_hal_gpio_read_type_e eReadType, + uint32_t *pu32RetVal); + +//***************************************************************************** +// +//! @brief Write GPIO. +//! +//! @param ui32Pin - pin number to be read. +//! +//! @param eWriteType - State type to write. One of: +//! AM_HAL_GPIO_OUTPUT_SET - Write a one to a GPIO. +//! AM_HAL_GPIO_OUTPUT_CLEAR - Write a zero to a GPIO. +//! AM_HAL_GPIO_OUTPUT_TOGGLE - Toggle the GPIO value. +//! The following two apply when output is set for TriState (OUTCFG==3). +//! AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE - Enable a tri-state GPIO. +//! AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE - Disable a tri-state GPIO. +//! +//! This function writes a GPIO value. +//! +//! @return Status. +//! Fails if the pad is not configured for GPIO (PADFNCSEL != 3). +// +//***************************************************************************** +extern uint32_t am_hal_gpio_state_write(uint32_t ui32Pin, + am_hal_gpio_write_type_e eWriteType); + +//***************************************************************************** +// +//! @brief Enable GPIO interrupts. +//! +//! @param ui64InterruptMask - Mask of GPIO interrupts to enable. +//! Only bits 0-49 are valid in the mask. +//! +//! @return Status. +//! Fails if any bit above bit49 is set in ui64InterruptMask. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_enable(uint64_t ui64InterruptMask); + +//***************************************************************************** +// +//! @brief Disable GPIO interrupts. +//! +//! @param ui64InterruptMask - Mask of GPIO interrupts to disable. +//! Only bits 0-49 are valid in the mask. +//! +//! @return Status. +//! Fails if any bit above bit49 is set in ui64InterruptMask. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_disable(uint64_t ui64InterruptMask); + +//***************************************************************************** +// +//! @brief Clear GPIO interrupts. +//! +//! @param ui64InterruptMask - Mask of GPIO interrupts to be cleared. +//! Only bits 0-49 are valid in the mask. +//! +//! @return Status. +//! Fails if any bit above bit49 is set in ui64InterruptMask. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_clear(uint64_t ui64InterruptMask); + +//***************************************************************************** +// +//! @brief Get GPIO interrupt status. +//! +//! @param bEnabledOnly - Return status only for currently enabled interrupts. +//! +//! @param pui64IntStatus - 64-bit variable to return a bitmask of the status +//! of the interrupts. +//! +//! @return Status. +//! Fails if pui64IntStatus is NULL. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_status_get(bool bEnabledOnly, + uint64_t *pui64IntStatus); + +//***************************************************************************** +// +//! @brief GPIO interrupt service routine registration. +//! +//! @param ui32GPIONumber - GPIO number (0-49) to be registered. +//! +//! @param pfnHandler - Function pointer to the callback. +//! +//! @return Status. +//! Fails if pfnHandler is NULL or ui32GPIONumber > 49. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_register(uint32_t ui32GPIONumber, + am_hal_gpio_handler_t pfnHandler); + +//***************************************************************************** +// +//! @brief Advanced GPIO interrupt service routine registration. +//! +//! @param ui32GPIONumber - GPIO number (0-49) to be registered. +//! +//! @param pfnHandler - Function pointer to the callback. +//! +//! @param pCtxt - context for the callback. +//! +//! @return Status. +//! Fails if pfnHandler is NULL or ui32GPIONumber > 49. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_register_adv(uint32_t ui32GPIONumber, + am_hal_gpio_handler_adv_t pfnHandler, void *pCtxt); + +//***************************************************************************** +// +// GPIO interrupt service routine. +//! @brief GPIO interrupt service routine registration. +//! +//! @param ui64Status - Mask of the interrupt(s) to be serviced. This mask is +//! typically obtained via a call to am_hal_gpio_interrupt_status_get(). +//! +//! The intended use is that the application first registers a handler for a +//! particular GPIO via am_hal_gpio_interrupt_register(), and to supply the +//! main ISR, am_gpio_isr(). +//! +//! On a GPIO interrupt, am_gpio_isr() calls am_hal_gpio_interrupt_status_get() +//! and provides the return value to this function. +//! +//! In the event that multiple GPIO interrupts are active, the corresponding +//! interrupt handlers will be called in numerical order by GPIO number +//! starting with the lowest GPIO number. +//! +//! @return Status. +//! AM_HAL_STATUS_INVALID_OPERATION if no handler had been registered +//! for any of the GPIOs that caused the interrupt. +//! AM_HAL_STATUS_OUT_OF_RANGE if any bit above bit49 is set. +//! AM_HAL_STATUS_FAIL if ui64Status is 0. +//! AM_HAL_STATUS_SUCCESS otherwise. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_service(uint64_t ui64Status); + +//***************************************************************************** +// +//! @brief Configure an Apollo3 pin. +//! +//! @param ui32Pin - pin number to be configured. +//! @param ui32Config - Contains multiple descriptor fields. +//! @param sAllowableChanges - Contains bools corresponding to config fields. +//! +//! This function configures a pin according to the parameters in ui32Config. +//! All parameters are validated, and the given pin is configured according +//! to the designated parameters. +//! +//! @return Status. +// +//***************************************************************************** +uint32_t ap3_hal_gpio_pinconfig_partial(uint32_t ui32Pin, am_hal_gpio_pincfg_t bfGpioCfg, am_hal_gpio_pincfg_allow_t sAllowableChanges); + +//***************************************************************************** +// +//! @brief Macros to read GPIO values in an optimized manner. +//! +//! @param n - The GPIO number to be read. +//! +//! In almost all cases, it is reasonable to use am_hal_gpio_state_read() to +//! read GPIO values with all of the inherent error checking, critical +//! sectioning, and general safety. +//! +//! However, occasionally there is a need to read a GPIO value in an optimized +//! manner. These 3 macros will accomplish that. Each macro will return a +//! value of 1 or 0. +//! +//! Note that the macros are named as lower-case counterparts to the +//! enumerations for the am_hal_gpio_state_read() function. That is: +//! +//! AM_HAL_GPIO_INPUT_READ -> am_hal_gpio_input_read(n) +//! AM_HAL_GPIO_OUTPUT_READ -> am_hal_gpio_output_read(n) +//! AM_HAL_GPIO_ENABLE_READ -> am_hal_gpio_enable_read(n) +//! +//! @return Each macro will return a 1 or 0 per the value of the requested GPIO. +//! +// +//***************************************************************************** +#define am_hal_gpio_input_read(n) ( \ + (AM_REGVAL( (AM_REGADDR(GPIO, RDA) + (((uint32_t)(n) & 0x20) >> 3)) ) >> /* Read appropriate register */ \ + ((uint32_t)(n) & 0x1F) ) & /* Shift by appropriate number of bits */ \ + ((uint32_t)0x1) ) /* Mask out the LSB */ + +#define am_hal_gpio_output_read(n) ( \ + (AM_REGVAL( (AM_REGADDR(GPIO, WTA) + (((uint32_t)(n) & 0x20) >> 3)) ) >> /* Read appropriate register */ \ + ((uint32_t)(n) & 0x1F) ) & /* Shift by appropriate number of bits */ \ + ((uint32_t)0x1) ) /* Mask out the LSB */ + +#define am_hal_gpio_enable_read(n) ( \ + (AM_REGVAL( (AM_REGADDR(GPIO, ENA) + (((uint32_t)(n) & 0x20) >> 3)) ) >> /* Read appropriate register */ \ + ((uint32_t)(n) & 0x1F) ) & /* Shift by appropriate number of bits */ \ + ((uint32_t)0x1) ) /* Mask out the LSB */ + + +//***************************************************************************** +// +//! @brief Macros to write GPIO values in an optimized manner. +//! +//! @param n - The GPIO number to be written. +//! +//! In almost all cases, it is reasonable to use am_hal_gpio_state_write() to +//! write GPIO values with all of the inherent error checking, critical +//! sectioning, and general safety. +//! +//! However, occasionally there is a need to write a GPIO value in an optimized +//! manner. These 3 macros will accomplish that. +//! +//! Note that the macros are named as lower-case counterparts to the +//! enumerations for the am_hal_gpio_state_read() function. That is: +//! +//! AM_HAL_GPIO_OUTPUT_CLEAR -> am_hal_gpio_output_clear(n,v) +//! AM_HAL_GPIO_OUTPUT_SET -> am_hal_gpio_output_set(n,v) +//! AM_HAL_GPIO_OUTPUT_TOGGLE -> am_hal_gpio_output_toggle(n,v) +//! AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE -> am_hal_gpio_output_tristate_disable(n,v) +//! AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE -> am_hal_gpio_output_tristate_enable(n,v) +//! AM_HAL_GPIO_OUTPUT_TRISTATE_TOGGLE -> am_hal_gpio_output_toggle(n,v) +//! +//! @return None. +//! +//***************************************************************************** +// +// Note - these macros use byte-oriented addressing. +// +#define am_hal_gpio_output_clear(n) \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, WTCA) + (((uint32_t)(n) & 0x20) >> 3))))) = \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))) + +#define am_hal_gpio_output_set(n) \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, WTSA) + (((uint32_t)(n) & 0x20) >> 3))))) = \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))) + +#define am_hal_gpio_output_toggle(n) \ + if ( 1 ) \ + { \ + AM_CRITICAL_BEGIN \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, WTA) + (((uint32_t)(n) & 0x20) >> 3))))) ^= \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))); \ + AM_CRITICAL_END \ + } + +#define am_hal_gpio_output_tristate_disable(n) \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, ENCA) + (((uint32_t)(n) & 0x20) >> 3))))) = \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))) + +#define am_hal_gpio_output_tristate_enable(n) \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, ENSA) + (((uint32_t)(n) & 0x20) >> 3))))) = \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))) + +#define am_hal_gpio_output_tristate_toggle(n) \ + if ( 1 ) \ + { \ + AM_CRITICAL_BEGIN \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, ENA) + (((uint32_t)(n) & 0x20) >> 3))))) ^= \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))); \ + AM_CRITICAL_END \ + } + + +//***************************************************************************** +//! +//! @brief Fast GPIO helper macros. +//! +//***************************************************************************** +// +// Define Fast GPIO enable and disable. +// +#define am_hal_gpio_fastgpio_enable(n) am_hal_gpio_output_tristate_enable(n) +#define am_hal_gpio_fastgpio_disable(n) am_hal_gpio_output_tristate_disable(n) + +// +// Macros for accessing Fast GPIO: set, clear, and read. +// The 'n' parameter is the pin number. +// Note - these macros are most efficient if 'n' is a constant value, and +// of course when compiled with -O3. +// +#define am_hal_gpio_fastgpio_read(n) ((APBDMA->BBINPUT >> (n & 0x7)) & 0x1) +#define am_hal_gpio_fastgpio_set(n) (APBDMA->BBSETCLEAR = _VAL2FLD(APBDMA_BBSETCLEAR_SET, (1 << (n & 0x7)))) +#define am_hal_gpio_fastgpio_clr(n) (APBDMA->BBSETCLEAR = _VAL2FLD(APBDMA_BBSETCLEAR_CLEAR, (1 << (n & 0x7)))) +#define am_hal_gpio_fastgpio_setmsk(m) (APBDMA->BBSETCLEAR = _VAL2FLD(APBDMA_BBSETCLEAR_SET, m)) +#define am_hal_gpio_fastgpio_clrmsk(m) (APBDMA->BBSETCLEAR = _VAL2FLD(APBDMA_BBSETCLEAR_CLEAR, m)) +#define am_hal_gpio_fastgpio_wrval(val) (APBDMA->BBSETCLEAR = \ + (_VAL2FLD(APBDMA_BBSETCLEAR_SET, val) | \ + _VAL2FLD(APBDMA_BBSETCLEAR_CLEAR, val ^ 0xFF))) + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_GPIO_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.c new file mode 100644 index 0000000..a4e74c6 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.c @@ -0,0 +1,225 @@ +//***************************************************************************** +// +// am_hal_interrupt.c +//! @file +//! +//! @brief Helper functions supporting interrupts and NVIC operation. +//! +//! These functions may be used for NVIC-level interrupt configuration. +//! +//! @addtogroup interrupt3 Interrupt (ARM NVIC support functions) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Globally enable interrupt service routines +//! +//! This function allows interrupt signals from the NVIC to trigger ISR entry +//! in the CPU. This function must be called if interrupts are to be serviced +//! in software. +//! +//! @return 1 if interrupts were previously disabled, 0 otherwise. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm uint32_t +am_hal_interrupt_master_enable(void) +{ + mrs r0, PRIMASK + cpsie i + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_enable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsie i"); + __asm(" bx lr"); +} +#elif defined(__GNUC_STDC_INLINE__) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_enable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsie i"); + __asm(" bx lr"); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless uint32_t +am_hal_interrupt_master_enable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsie i"); + __asm(" bx lr"); +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +//***************************************************************************** +// +//! @brief Globally disable interrupt service routines +//! +//! This function prevents interrupt signals from the NVIC from triggering ISR +//! entry in the CPU. This will effectively stop incoming interrupt sources +//! from triggering their corresponding ISRs. +//! +//! @note Any external interrupt signal that occurs while the master interrupt +//! disable is active will still reach the "pending" state in the NVIC, but it +//! will not be allowed to reach the "active" state or trigger the +//! corresponding ISR. Instead, these interrupts are essentially "queued" until +//! the next time the master interrupt enable instruction is executed. At that +//! time, the interrupt handlers will be executed in order of decreasing +//! priority. +//! +//! @return 1 if interrupts were previously disabled, 0 otherwise. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm uint32_t +am_hal_interrupt_master_disable(void) +{ + mrs r0, PRIMASK + cpsid i + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_disable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsid i"); + __asm(" bx lr"); +} +#elif defined(__GNUC_STDC_INLINE__) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_disable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsid i"); + __asm(" bx lr"); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless uint32_t +am_hal_interrupt_master_disable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsid i"); + __asm(" bx lr"); +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +//***************************************************************************** +// +//! @brief Sets the master interrupt state based on the input. +//! +//! @param ui32InterruptState - Desired PRIMASK value. +//! +//! This function directly writes the PRIMASK register in the ARM core. A value +//! of 1 will disable interrupts, while a value of zero will enable them. +//! +//! This function may be used along with am_hal_interrupt_master_disable() to +//! implement a nesting critical section. To do this, call +//! am_hal_interrupt_master_disable() to start the critical section, and save +//! its return value. To complete the critical section, call +//! am_hal_interrupt_master_set() using the saved return value as \e +//! ui32InterruptState. This will safely restore PRIMASK to the value it +//! contained just before the start of the critical section. +//! +//! @return None. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm void +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + msr PRIMASK, r0 + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +void __attribute__((naked)) +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + __asm(" msr PRIMASK, r0"); + __asm(" bx lr"); +} +#elif defined(__GNUC_STDC_INLINE__) +void __attribute__((naked)) +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + __asm(" msr PRIMASK, r0"); + __asm(" bx lr"); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless void +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + __asm(" msr PRIMASK, r0"); + __asm(" bx lr"); +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#endif + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.h new file mode 100644 index 0000000..148e046 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.h @@ -0,0 +1,84 @@ +//***************************************************************************** +// +// am_hal_interrupt.h +//! @file +//! +//! @brief Helper functions supporting interrupts and NVIC operation. +//! +//! These functions may be used for NVIC-level interrupt configuration. +//! +//! @addtogroup interrupt3 Interrupt (ARM NVIC support functions) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_INTERRUPT_H +#define AM_HAL_INTERRUPT_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Define the last peripheral interrupt as AM_HAL_INTERRUPT_MAX. +// The total number of interrupts in the vector table is therefore +// (AM_HAL_INTERRUPT_MAX + 1 + 16). +// +#define AM_HAL_INTERRUPT_MAX (CLKGEN_IRQn) + +extern uint32_t am_hal_interrupt_master_disable(void); +extern uint32_t am_hal_interrupt_master_enable(void); +extern void am_hal_interrupt_master_set(uint32_t ui32InterruptState); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_INTERRUPT_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.c new file mode 100644 index 0000000..191296f --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.c @@ -0,0 +1,3752 @@ +//***************************************************************************** +// +// am_hal_iom.c +//! @file +//! +//! @brief Functions for interfacing with IO Master serial (SPI/I2C) modules. +//! +//! @addtogroup iom3 IO Master (SPI/I2C) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __IAR_SYSTEMS_ICC__ +#define AM_INSTR_CLZ(n) __CLZ(n) +#else +#define AM_INSTR_CLZ(n) __builtin_clz(n) +#endif + +#define MANUAL_POP 0 + +#define AM_HAL_MAGIC_IOM 0x123456 +#define AM_HAL_IOM_CHK_HANDLE(h) ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_IOM)) + +// For IOM - Need to clear the flag for unpausing +#define AM_HAL_IOM_SC_PAUSE_CQ AM_HAL_IOM_SC_PAUSE(AM_HAL_IOM_PAUSE_FLAG_CQ) +#define AM_HAL_IOM_SC_PAUSE_SEQLOOP AM_HAL_IOM_SC_PAUSE(AM_HAL_IOM_PAUSE_FLAG_SEQLOOP) +#define AM_HAL_IOM_SC_UNPAUSE_CQ AM_HAL_IOM_SC_UNPAUSE(AM_HAL_IOM_PAUSE_FLAG_CQ) +#define AM_HAL_IOM_SC_UNPAUSE_SEQLOOP AM_HAL_IOM_SC_UNPAUSE(AM_HAL_IOM_PAUSE_FLAG_SEQLOOP) +#define AM_HAL_IOM_SC_PAUSE_BLOCK AM_HAL_IOM_SC_PAUSE(AM_HAL_IOM_PAUSE_FLAG_BLOCK) +#define AM_HAL_IOM_SC_UNPAUSE_BLOCK AM_HAL_IOM_SC_UNPAUSE(AM_HAL_IOM_PAUSE_FLAG_BLOCK) + +// Max time to wait when attempting to pause the command queue +#define AM_HAL_IOM_MAX_PAUSE_DELAY (100*1000) // 100ms + +//***************************************************************************** +// +// IOM interface clock selections +// +//***************************************************************************** +#define AM_REG_IOM_CLKCFG_FSEL_MIN_PWR 0x00000000 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC 0x00000100 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV2 0x00000200 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV4 0x00000300 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV8 0x00000400 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV16 0x00000500 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV32 0x00000600 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV64 0x00000700 + +// +// Only keep IOM interrupts we're interested in +// +// Necessary interrupts for respective modes +// For CQ - we rely only on the CQUPD interrupt +#define AM_HAL_IOM_INT_CQMODE (AM_HAL_IOM_INT_CQUPD | AM_HAL_IOM_INT_ERR) +// Need both CMDCMP & DCMP, as for Read we need to wait for DCMP after CMDCMP +#define AM_HAL_IOM_INT_DMAMODE (AM_HAL_IOM_INT_CMDCMP | AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_ERR) + +// Configures the interrupts to provided coniguration - clearing all pending interrupts +#define IOM_SET_INTEN(ui32Module, intCfg) \ + do \ + { \ + IOMn(ui32Module)->INTEN = 0; \ + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; \ + IOMn(ui32Module)->INTEN = (intCfg); \ + } while (0); + + +//***************************************************************************** +// +// Private Types. +// +//***************************************************************************** + +// +// Command Queue entry structure. +// +typedef struct +{ +#if (AM_HAL_IOM_CQ == 1) + uint32_t ui32PAUSENAddr; + uint32_t ui32PAUSEENVal; + uint32_t ui32PAUSEN2Addr; + uint32_t ui32PAUSEEN2Val; +#endif + uint32_t ui32OFFSETHIAddr; + uint32_t ui32OFFSETHIVal; + uint32_t ui32DEVCFGAddr; + uint32_t ui32DEVCFGVal; + uint32_t ui32DMACFGdis1Addr; + uint32_t ui32DMACFGdis1Val; + uint32_t ui32DMATOTCOUNTAddr; + uint32_t ui32DMATOTCOUNTVal; + uint32_t ui32DMATARGADDRAddr; + uint32_t ui32DMATARGADDRVal; + uint32_t ui32DMACFGAddr; + uint32_t ui32DMACFGVal; + // CMDRPT register has been repurposed for DCX + uint32_t ui32DCXAddr; + uint32_t ui32DCXVal; + uint32_t ui32CMDAddr; + uint32_t ui32CMDVal; +#if (AM_HAL_IOM_CQ == 1) + uint32_t ui32SETCLRAddr; + uint32_t ui32SETCLRVal; +#endif +} am_hal_iom_txn_cmdlist_t; + +// +// Command Queue entry structure for Sequence Repeat +// +typedef struct +{ + uint32_t ui32PAUSENAddr; + uint32_t ui32PAUSEENVal; + uint32_t ui32PAUSEN2Addr; + uint32_t ui32PAUSEEN2Val; + uint32_t ui32SETCLRAddr; + uint32_t ui32SETCLRVal; +} am_hal_iom_cq_loop_entry_t; + +#define AM_HAL_IOM_MAX_PENDING_TRANSACTIONS 256 // Must be power of 2 for the implementation below +#define AM_HAL_IOM_CQUPD_INT_FLAG (0x00000001) + +typedef struct +{ + bool bValid; + uint32_t regFIFOTHR; + uint32_t regDMATRIGEN; + uint32_t regCLKCFG; + uint32_t regSUBMODCTRL; + uint32_t regCQCFG; + uint32_t regCQADDR; + uint32_t regCQFLAGS; + uint32_t regCQPAUSEEN; + uint32_t regCQCURIDX; + uint32_t regCQENDIDX; + uint32_t regMSPICFG; + uint32_t regMI2CCFG; + uint32_t regINTEN; +} am_hal_iom_register_state_t; + +typedef enum +{ + AM_HAL_IOM_SEQ_NONE, + AM_HAL_IOM_SEQ_UNDER_CONSTRUCTION, + AM_HAL_IOM_SEQ_RUNNING, +} am_hal_iom_seq_e; + +typedef struct +{ + uint32_t ui32OFFSETHIVal; + uint32_t ui32DEVCFGVal; + uint32_t ui32DMATOTCOUNTVal; + uint32_t ui32DMATARGADDRVal; + uint32_t ui32DMACFGVal; + uint32_t ui32CMDVal; + am_hal_iom_callback_t pfnCallback; + void *pCallbackCtxt; +} am_hal_iom_dma_entry_t; + +typedef struct +{ + am_hal_handle_prefix_t prefix; + // + // Physical module number. + // + uint32_t ui32Module; + + // + // Interface mode (SPI or I2C). + // + am_hal_iom_mode_e eInterfaceMode; + uint32_t *pNBTxnBuf; + uint32_t ui32NBTxnBufLength; + + uint32_t ui32UserIntCfg; + uint32_t ui32TxnInt; + + uint32_t ui32LastIdxProcessed; + uint32_t ui32MaxTransactions; + volatile uint32_t ui32NumPendTransactions; + // + // Stores the CQ callbacks. + // + am_hal_iom_callback_t pfnCallback[AM_HAL_IOM_MAX_PENDING_TRANSACTIONS]; + void *pCallbackCtxt[AM_HAL_IOM_MAX_PENDING_TRANSACTIONS]; +#if (AM_HAL_IOM_CQ == 1) + void *pCmdQHdl; + // To support sequence + am_hal_iom_seq_e eSeq; + bool bAutonomous; + // This is used to track the number of transactions in a sequence + uint32_t ui32NumSeqTransactions; + volatile bool bRestart; + uint32_t block; + // To support high priority transactions - out of band + // High Priority DMA transactions + volatile bool bHP; + uint32_t ui32NumHPEntries; + uint32_t ui32NumHPPendingEntries; + uint32_t ui32MaxHPTransactions; + uint32_t ui32NextHPIdx; + uint32_t ui32LastHPIdxProcessed; + am_hal_iom_dma_entry_t *pHPTransactions; + // Max pending transactions based on NB Buffer size + uint32_t ui32MaxPending; + // Number of back to back transactions with no callbacks + uint32_t ui32NumUnSolicited; +#else + uint32_t ui32NextIdx; + am_hal_iom_txn_cmdlist_t *pTransactions; +#endif + // + // Delay timeout value. + // + uint32_t waitTimeout; + // Configured clock time + uint32_t ui32BitTimeTicks; + + am_hal_iom_register_state_t registerState; + uint8_t dcx[AM_HAL_IOM_MAX_CS_SPI + 1]; + +} am_hal_iom_state_t; + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +am_hal_iom_state_t g_IOMhandles[AM_REG_IOM_NUM_MODULES]; +//***************************************************************************** +// +// Internal Functions. +// +//***************************************************************************** +static uint32_t +get_pause_val(am_hal_iom_state_t *pIOMState, uint32_t pause) +{ + uint32_t retval; + switch (pIOMState->block) + { + case 1: + // Pause the CQ till the whole block is built + retval = pause | AM_HAL_IOM_CQP_PAUSE_DEFAULT | AM_HAL_IOM_PAUSE_FLAG_BLOCK; + pIOMState->block = 2; + break; + case 2: + // No pausing allowed + retval = AM_HAL_IOM_PAUSE_DEFAULT; + break; + default: // case 0 + retval = pause | AM_HAL_IOM_CQP_PAUSE_DEFAULT; + } + return retval; +} + +//***************************************************************************** +// +// Function to build the CMD value. +// Returns the CMD value, but does not set the CMD register. +// +// The OFFSETHI register must still be handled by the caller, e.g. +// AM_REGn(IOM, ui32Module, OFFSETHI) = (uint16_t)(ui32Offset >> 8); +// +//***************************************************************************** +static uint32_t +build_cmd(uint32_t ui32CS, uint32_t ui32Dir, uint32_t ui32Cont, + uint32_t ui32Offset, uint32_t ui32OffsetCnt, + uint32_t ui32nBytes) +{ + // + // Initialize the CMD variable + // + uint32_t ui32Cmd = 0; + + // + // If SPI, we'll need the chip select + // + ui32Cmd |= _VAL2FLD(IOM0_CMD_CMDSEL, ui32CS); + + // + // Build the CMD with number of bytes and direction. + // + ui32Cmd |= _VAL2FLD(IOM0_CMD_TSIZE, ui32nBytes); + + if (ui32Dir == AM_HAL_IOM_RX) + { + ui32Cmd |= _VAL2FLD(IOM0_CMD_CMD, IOM0_CMD_CMD_READ); + } + else + { + ui32Cmd |= _VAL2FLD(IOM0_CMD_CMD, IOM0_CMD_CMD_WRITE); + } + + ui32Cmd |= _VAL2FLD(IOM0_CMD_CONT, ui32Cont); + + // + // Now add the OFFSETLO and OFFSETCNT information. + // + ui32Cmd |= _VAL2FLD(IOM0_CMD_OFFSETLO, (uint8_t)ui32Offset); + ui32Cmd |= _VAL2FLD(IOM0_CMD_OFFSETCNT, ui32OffsetCnt); + + return ui32Cmd; +} // build_cmd() + +//***************************************************************************** +// +// Function to build CMD lists. +// +//***************************************************************************** +static void +build_txn_cmdlist(am_hal_iom_state_t *pIOMState, + am_hal_iom_txn_cmdlist_t *pCQEntry, + am_hal_iom_transfer_t *psTransaction) +{ + uint32_t ui32Cmd; + uint32_t ui32Module = pIOMState->ui32Module; + uint32_t ui32Dir = psTransaction->eDirection; + uint32_t ui32SRAMAddress; + + // + // Command for OFFSETHI + // + pCQEntry->ui32OFFSETHIAddr = (uint32_t)&IOMn(ui32Module)->OFFSETHI; + + pCQEntry->ui32OFFSETHIVal = (uint16_t)(psTransaction->ui32Instr >> 8); + + // + // Command for I2C DEVADDR field in DEVCFG + // + pCQEntry->ui32DEVCFGAddr = (uint32_t)&IOMn(ui32Module)->DEVCFG; + pCQEntry->ui32DEVCFGVal = _VAL2FLD(IOM0_DEVCFG_DEVADDR, psTransaction->uPeerInfo.ui32I2CDevAddr); + + // + // Command to disable DMA before writing TOTCOUNT. + // + pCQEntry->ui32DMACFGdis1Addr = (uint32_t)&IOMn(ui32Module)->DMACFG; + pCQEntry->ui32DMACFGdis1Val = 0x0; + + // + // Command to set DMATOTALCOUNT + // + pCQEntry->ui32DMATOTCOUNTAddr = (uint32_t)&IOMn(ui32Module)->DMATOTCOUNT; + pCQEntry->ui32DMATOTCOUNTVal = psTransaction->ui32NumBytes; + + // + // Command to set DMATARGADDR + // + pCQEntry->ui32DMATARGADDRAddr = (uint32_t)&IOMn(ui32Module)->DMATARGADDR; + ui32SRAMAddress = (ui32Dir == AM_HAL_IOM_TX) ? (uint32_t)psTransaction->pui32TxBuffer : (uint32_t)psTransaction->pui32RxBuffer; + pCQEntry->ui32DMATARGADDRVal = ui32SRAMAddress; + + // + // Command to set DMACFG to start the DMA operation + // + pCQEntry->ui32DMACFGAddr = (uint32_t)&IOMn(ui32Module)->DMACFG; + pCQEntry->ui32DMACFGVal = + _VAL2FLD(IOM0_DMACFG_DMAPRI, psTransaction->ui8Priority) | + _VAL2FLD(IOM0_DMACFG_DMADIR, ui32Dir == AM_HAL_IOM_TX ? 1 : 0); + + if (psTransaction->ui32NumBytes) + { + pCQEntry->ui32DMACFGVal |= IOM0_DMACFG_DMAEN_Msk; + } + + // CMDRPT register has been repurposed for DCX + pCQEntry->ui32DCXAddr = (uint32_t)&IOMn(ui32Module)->DCX; + pCQEntry->ui32DCXVal = (pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE) ? pIOMState->dcx[psTransaction->uPeerInfo.ui32SpiChipSelect] : 0; + // + // Command to start the transfer. + // + ui32Cmd = pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE ? + psTransaction->uPeerInfo.ui32SpiChipSelect : 0; + ui32Cmd = build_cmd(ui32Cmd, // ChipSelect + ui32Dir, // ui32Dir + psTransaction->bContinue, // ui32Cont + psTransaction->ui32Instr, // ui32Offset + psTransaction->ui32InstrLen, // ui32OffsetCnt + psTransaction->ui32NumBytes); // ui32Bytes + + pCQEntry->ui32CMDAddr = (uint32_t)&IOMn(ui32Module)->CMD; + pCQEntry->ui32CMDVal = ui32Cmd; + +#if (AM_HAL_IOM_CQ == 1) + pCQEntry->ui32PAUSENAddr = pCQEntry->ui32PAUSEN2Addr = (uint32_t)&IOMn(ui32Module)->CQPAUSEEN; + pCQEntry->ui32PAUSEEN2Val = AM_HAL_IOM_PAUSE_DEFAULT; + pCQEntry->ui32PAUSEENVal = get_pause_val(pIOMState, psTransaction->ui32PauseCondition); + pCQEntry->ui32SETCLRVal = psTransaction->ui32StatusSetClr; + pCQEntry->ui32SETCLRAddr = (uint32_t)&IOMn(ui32Module)->CQSETCLEAR; +#endif +} // build_txn_cmdlist() + +//***************************************************************************** +// +// enable_submodule() - Utilizes the built-in fields that indicate whether which +// submodule is supported, then enables that submodule. +// +// Input: ui32Type = 0, set for SPI. +// ui32Type = 1, set for I2C. +// +//***************************************************************************** +static void +enable_submodule(uint32_t ui32Module, uint32_t ui32Type) +{ + if ( IOMn(ui32Module)->SUBMODCTRL_b.SMOD0TYPE == ui32Type ) + { + IOMn(ui32Module)->SUBMODCTRL = + _VAL2FLD(IOM0_SUBMODCTRL_SMOD1EN, 0) | + _VAL2FLD(IOM0_SUBMODCTRL_SMOD0EN, 1); + } + else + { + IOMn(ui32Module)->SUBMODCTRL = + _VAL2FLD(IOM0_SUBMODCTRL_SMOD1EN, 1) | + _VAL2FLD(IOM0_SUBMODCTRL_SMOD0EN, 0); + } +} // enable_submodule() + +//***************************************************************************** +// +// Error handling. +// +//***************************************************************************** +uint32_t +internal_iom_get_int_err(uint32_t ui32Module, uint32_t ui32IntStatus) +{ + // + // Map the INTSTAT bits for transaction status + // + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + + // + // Let's accumulate the errors + // + ui32IntStatus |= IOMn(ui32Module)->INTSTAT; + + if (ui32IntStatus & AM_HAL_IOM_INT_SWERR) + { + // Error in hardware command issued or illegal access by SW + ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_I2CARBERR) + { + // Loss of I2C multi-master arbitration + ui32Status = AM_HAL_IOM_ERR_I2C_ARB; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_NAK) + { + // I2C NAK + ui32Status = AM_HAL_IOM_ERR_I2C_NAK; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_INTERR) + { + // Other Error + ui32Status = AM_HAL_STATUS_FAIL; + } + + return ui32Status; + +} // internal_iom_get_int_err() + +static void +internal_iom_reset_on_error(am_hal_iom_state_t *pIOMState, uint32_t ui32IntMask) +{ + uint32_t iterationsToWait = 2 * pIOMState->ui32BitTimeTicks; // effectively > 6 clocks + uint32_t ui32Module = pIOMState->ui32Module; + uint32_t curIntCfg = IOMn(ui32Module)->INTEN; + IOMn(ui32Module)->INTEN = 0; + + // Disable interrupts temporarily + if (ui32IntMask & AM_HAL_IOM_INT_DERR) + { + if ((IOMn(ui32Module)->DMACFG & IOM0_DMACFG_DMADIR_Msk) == _VAL2FLD(IOM0_DMACFG_DMADIR, IOM0_DMACFG_DMADIR_M2P)) + { + // Write + uint32_t dummy = 0xDEADBEEF; + uint32_t numBytesRemaining = IOMn(ui32Module)->DMATOTCOUNT; + + while (numBytesRemaining) + { + if (IOMn(ui32Module)->FIFOPTR_b.FIFO0REM >= 4) + { + // Write one 4-byte word to FIFO + IOMn(ui32Module)->FIFOPUSH = dummy; + if (numBytesRemaining > 4) + { + numBytesRemaining -= 4; + } + else + { + break; + } + } + } + // Now wait for command to finish + while ((IOMn(ui32Module)->STATUS & (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk)) != IOM0_STATUS_IDLEST_Msk); + } + else + { + // Read + // Let command finish + while (IOMn(ui32Module)->STATUS_b.CMDACT) + { + while (IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ >= 4) + { + // Read one 4-byte word from FIFO + IOMn(ui32Module)->FIFOPOP; +#if MANUAL_POP + IOMn(ui32Module)->FIFOPOP = 0x11111111; +#endif + } + } + // Now wait for command to finish + while ((IOMn(ui32Module)->STATUS & (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk)) != IOM0_STATUS_IDLEST_Msk); + // Flush any remaining data from FIFO + while (IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ) + { + while (IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ >= 4) + { + // Read one 4-byte word from FIFO + IOMn(ui32Module)->FIFOPOP; +#if MANUAL_POP + IOMn(ui32Module)->FIFOPOP = 0x11111111; +#endif + } + } + } + } + if (ui32IntMask & AM_HAL_IOM_INT_NAK) + { + // + // Wait for Idle + // + while ((IOMn(ui32Module)->STATUS & (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk)) != IOM0_STATUS_IDLEST_Msk); + + // + // Reset Submodule & FIFO + // + // Disable the submodules + // + IOMn(ui32Module)->SUBMODCTRL_b.SMOD1EN = 0; + // Reset Fifo + IOMn(ui32Module)->FIFOCTRL_b.FIFORSTN = 0; + + // Wait for few IO clock cycles + am_hal_flash_delay(iterationsToWait); + + IOMn(ui32Module)->FIFOCTRL_b.FIFORSTN = 1; + + // Enable submodule + IOMn(ui32Module)->SUBMODCTRL_b.SMOD1EN = 1; + } + + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; + + // Restore interrupts + IOMn(ui32Module)->INTEN = curIntCfg; +} + +//***************************************************************************** +// compute_freq() +//***************************************************************************** +// +// Compute the interface frequency based on the given parameters +// +static uint32_t +compute_freq(uint32_t ui32HFRCfreqHz, + uint32_t ui32Fsel, uint32_t ui32Div3, + uint32_t ui32DivEn, uint32_t ui32TotPer) +{ + uint32_t ui32Denomfinal, ui32ClkFreq; + + ui32Denomfinal = ((1 << (ui32Fsel - 1)) * (1 + ui32Div3 * 2) * (1 + ui32DivEn * (ui32TotPer))); + ui32ClkFreq = (ui32HFRCfreqHz) / ui32Denomfinal; // Compute the set frequency value + ui32ClkFreq += (((ui32HFRCfreqHz) % ui32Denomfinal) > (ui32Denomfinal / 2)) ? 1 : 0; + + return ui32ClkFreq; +} // compute_freq() + +//***************************************************************************** +// onebit() +//***************************************************************************** +// +// A power of 2? +// Return true if ui32Value has exactly 1 bit set, otherwise false. +// +static bool +onebit(uint32_t ui32Value) +{ + return ui32Value && !(ui32Value & (ui32Value - 1)); +} // onebit() + +//***************************************************************************** +// +// iom_get_interface_clock_cfg() +// +// Returns the proper settings for the CLKCFG register. +// +// ui32FreqHz - The desired interface frequency in Hz. +// +// Given a desired serial interface clock frequency, this function computes +// the appropriate settings for the various fields in the CLKCFG register +// and returns the 32-bit value that should be written to that register. +// The actual interface frequency may be slightly lower than the specified +// frequency, but the actual frequency is also returned. +// +// Note A couple of criteria that this algorithm follow are: +// 1. For power savings, choose the highest FSEL possible. +// 2. Use DIV3 when possible rather than DIVEN. +// +// Return An unsigned 64-bit value. +// The lower 32-bits represent the value to use to set CLKCFG. +// The upper 32-bits represent the actual frequency (in Hz) that will result +// from setting CLKCFG with the lower 32-bits. +// +// 0 (64 bits) = error. Note that the caller must check the entire 64 bits. +// It is not an error if only the low 32-bits are 0 (this is a valid value). +// But the entire 64 bits returning 0 is an error. +//! +//***************************************************************************** +static +uint64_t iom_get_interface_clock_cfg(uint32_t ui32FreqHz, uint32_t ui32Phase ) +{ + uint32_t ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer, ui32LowPer; + uint32_t ui32Denom, ui32v1, ui32Denomfinal, ui32ClkFreq, ui32ClkCfg; + uint32_t ui32HFRCfreqHz; + int32_t i32Div, i32N; + + if ( ui32FreqHz == 0 ) + { + return 0; + } + + // + // Set the HFRC clock frequency. + // + ui32HFRCfreqHz = AM_HAL_CLKGEN_FREQ_MAX_HZ; + + // + // Compute various parameters used for computing the optimal CLKCFG setting. + // + i32Div = (ui32HFRCfreqHz / ui32FreqHz) + ((ui32HFRCfreqHz % ui32FreqHz) ? 1 : 0); // Round up (ceiling) + + // + // Compute N (count the number of LS zeros of Div) = ctz(Div) = log2(Div & (-Div)) + // + i32N = 31 - AM_INSTR_CLZ((i32Div & (-i32Div))); + + if ( i32N > 6 ) + { + i32N = 6; + } + + ui32Div3 = ( (ui32FreqHz < (ui32HFRCfreqHz / 16384)) || + ( ((ui32FreqHz >= (ui32HFRCfreqHz / 3)) && + (ui32FreqHz <= ((ui32HFRCfreqHz / 2) - 1)) ) ) ) ? 1 : 0; + ui32Denom = ( 1 << i32N ) * ( 1 + (ui32Div3 * 2) ); + ui32TotPer = i32Div / ui32Denom; + ui32TotPer += (i32Div % ui32Denom) ? 1 : 0; + ui32v1 = 31 - AM_INSTR_CLZ(ui32TotPer); // v1 = log2(TotPer) + ui32Fsel = (ui32v1 > 7) ? ui32v1 + i32N - 7 : i32N; + ui32Fsel++; + + if ( ui32Fsel > 7 ) + { + // + // This is an error, can't go that low. + // + return 0; + } + + if ( ui32v1 > 7 ) + { + ui32DivEn = ui32TotPer; // Save TotPer for the round up calculation + ui32TotPer = ui32TotPer>>(ui32v1-7); + ui32TotPer += ((ui32DivEn) % (1 << (ui32v1 - 7))) ? 1 : 0; + } + + ui32DivEn = ( (ui32FreqHz >= (ui32HFRCfreqHz / 4)) || + ((1 << (ui32Fsel - 1)) == i32Div) ) ? 0 : 1; + + if (ui32Phase == 1) + { + ui32LowPer = (ui32TotPer - 2) / 2; // Longer high phase + } + else + { + ui32LowPer = (ui32TotPer - 1) / 2; // Longer low phase + } + + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_FSEL, ui32Fsel) | + _VAL2FLD(IOM0_CLKCFG_DIV3, ui32Div3) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, ui32DivEn) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, ui32LowPer) | + _VAL2FLD(IOM0_CLKCFG_TOTPER, ui32TotPer - 1); + + // + // Now, compute the actual frequency, which will be returned. + // + ui32ClkFreq = compute_freq(ui32HFRCfreqHz, ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer - 1); + + // + // Determine if the actual frequency is a power of 2 (MHz). + // + if ( (ui32ClkFreq % 250000) == 0 ) + { + // + // If the actual clock frequency is a power of 2 ranging from 250KHz up, + // we can simplify the CLKCFG value using DIV3 (which also results in a + // better duty cycle). + // + ui32Denomfinal = ui32ClkFreq / (uint32_t)250000; + + if ( onebit(ui32Denomfinal) ) + { + // + // These configurations can be simplified by using DIV3. Configs + // using DIV3 have a 50% duty cycle, while those from DIVEN will + // have a 66/33 duty cycle. + // + ui32TotPer = ui32LowPer = ui32DivEn = 0; + ui32Div3 = 1; + + // + // Now, compute the return values. + // + ui32ClkFreq = compute_freq(ui32HFRCfreqHz, ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer); + + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_FSEL, ui32Fsel) | + _VAL2FLD(IOM0_CLKCFG_DIV3, 1) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, 0) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, 0) | + _VAL2FLD(IOM0_CLKCFG_TOTPER, 0); + } + } + + return ( ((uint64_t)ui32ClkFreq) << 32) | (uint64_t)ui32ClkCfg; + +} //iom_get_interface_clock_cfg() + +#if (AM_HAL_IOM_CQ == 1) +//***************************************************************************** +// +//! @brief Initializes the IOM Command Queue. +//! +//! @param handle - handle for the interface. +//! @param ui32Length - length of the SRAM Command Queue buffer in words. +//! @param pTCB - pointer to the SRAM to use for the Command Queue. +//! +//! This function initializes the global command queue structure. +//! +//! @return HAL status of the operation. +// +//***************************************************************************** +uint32_t +am_hal_iom_CQInit(void *pHandle, uint32_t ui32Length, + uint32_t *pTCB) +{ + am_hal_cmdq_cfg_t cqCfg; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + uint32_t ui32Module = pIOMState->ui32Module; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + + pIOMState->pCmdQHdl = NULL; + pIOMState->ui32MaxTransactions = 0; + pIOMState->ui32NumUnSolicited = 0; + + cqCfg.pCmdQBuf = pTCB; + cqCfg.cmdQSize = ui32Length / 2; + cqCfg.priority = AM_HAL_CMDQ_PRIO_HI; + ui32Status = am_hal_cmdq_init((am_hal_cmdq_if_e)(AM_HAL_CMDQ_IF_IOM0 + ui32Module), + &cqCfg, &pIOMState->pCmdQHdl); + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + pIOMState->ui32MaxTransactions = AM_HAL_IOM_MAX_PENDING_TRANSACTIONS; + } + return ui32Status; +} // am_hal_iom_CQInit() + +//***************************************************************************** +// +//! @brief Resets the IOM Command Queue. +//! +//! @param ui32Module - IOM instance. +//! +//! This function resets the global command queue structure. +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +uint32_t +am_hal_IOM_CQReset(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + + if (pIOMState->pCmdQHdl) + { + am_hal_cmdq_term(pIOMState->pCmdQHdl, true); + pIOMState->pCmdQHdl = NULL; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_IOM_CQReset() + +//***************************************************************************** +// +//! @brief Adds a transaction the IOM Command Queue. +//! +//! @param handle - handle for the interface. +//! @param pTransaction - transaction to add to the CQ +//! @param pfnCallback - pointer the callback function to be executed when +//! transaction is complete. +//! +//! This function copies data from the IOM FIFO into the array \e pui32Data. +//! This is how input data from SPI or I2C transactions may be retrieved. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +uint32_t +am_hal_iom_CQAddTransaction(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + am_hal_iom_txn_cmdlist_t *pCQEntry; + am_hal_cmdq_entry_t *pCQBlock; + uint32_t index; + + // + // Check to see if there is enough room in the CQ + // + if ((pIOMState->ui32NumPendTransactions == AM_HAL_IOM_MAX_PENDING_TRANSACTIONS) || + (am_hal_cmdq_alloc_block(pIOMState->pCmdQHdl, sizeof(am_hal_iom_txn_cmdlist_t) / 8, &pCQBlock, &index))) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pCQEntry = (am_hal_iom_txn_cmdlist_t *)pCQBlock; + + + build_txn_cmdlist(pIOMState, pCQEntry, psTransaction); + + // + // Will resume here after DMA completes. + // + + // + // Because we set AM_HAL_IOM_CQUPD_INT_FLAG, an interrupt will occur once + // we reach this point in the Command Queue. In the service routine, we'll + // look for the appropriate callback. + // + // If ENDIDX has been reached, the CQ will pause here. Otherwise will + // continue with the next CQ entry. + // + + // + // Store the callback function pointer. + // + pIOMState->pfnCallback[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pfnCallback; + pIOMState->pCallbackCtxt[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pCallbackCtxt; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_iom_CQAddTransaction() + +//***************************************************************************** +// +//! @brief Enable the Command Queue operation. +//! +//! @param handle - handle for the interface. +//! +//! This function enables Command Queue operation. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +uint32_t +am_hal_iom_CQEnable(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + + if (0 == pIOMState->ui32NumPendTransactions) + { + uint32_t *pCqAddr = (uint32_t *)IOMn(pIOMState->ui32Module)->CQADDR; + // When CQ is enabled with nothing there - it always executes the first command + // insert dummy command + *pCqAddr = (uint32_t) &IOMn(pIOMState->ui32Module)->CQADDR; + *(pCqAddr + 1) = (uint32_t)pCqAddr; + } + // + // Enable the Command Queue operation + // + return am_hal_cmdq_enable(pIOMState->pCmdQHdl); + +} // am_hal_iom_CQEnable() + +//***************************************************************************** +// +//! @brief Disable the Command Queue operation. +//! +//! @param handle - handle for the interface. +//! +//! This function disables the Command Queue operation. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +uint32_t +am_hal_iom_CQDisable(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + + // + // Disable the Command Queue operation + // + return am_hal_cmdq_disable(pIOMState->pCmdQHdl); +} // am_hal_iom_CQDisable() + +static void iom_dummy_callback(void *pCallbackCtxt, uint32_t status) +{ + // Dummy - Do nothing +} + +static void iom_seq_loopback(void *pCallbackCtxt, uint32_t status) +{ + // Reset the state to allow serving callbacks for next set + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pCallbackCtxt; + pIOMState->ui32NumPendTransactions = pIOMState->ui32NumSeqTransactions + 1; + pIOMState->ui32LastIdxProcessed = 0; + pIOMState->bRestart = true; + // Now resume the CQ - to finish loopback + // Resume the CQ + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_SEQLOOP; +} + +static uint32_t iom_cq_pause(am_hal_iom_state_t *pIOMState) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32usMaxDelay = AM_HAL_IOM_MAX_PAUSE_DELAY; + // Pause the CQ + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_PAUSE_CQ; + // It is possible that CQ is disabled once the last transaction is processed + while ( IOMn(pIOMState->ui32Module)->CQCFG_b.CQEN ) + { + // Need to make sure we're paused at a designated pause point + if ( IOMn(pIOMState->ui32Module)->CQSTAT_b.CQPAUSED && (IOMn(pIOMState->ui32Module)->CQPAUSEEN & AM_HAL_IOM_PAUSE_FLAG_CQ) ) + { + break; + } + if ( ui32usMaxDelay-- ) + { + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + return AM_HAL_STATUS_TIMEOUT; + } + } + if (status == AM_HAL_STATUS_SUCCESS) + { + // Now that CQ is guaranteed to not progress further - we need to still wait in case the current CQ entry + // resulted in a DMA state....need to make sure we finish the current DMA + status = am_hal_flash_delay_status_check(AM_HAL_IOM_MAX_PAUSE_DELAY, + (uint32_t)&IOMn(pIOMState->ui32Module)->DMASTAT, + IOM0_DMASTAT_DMATIP_Msk, + _VAL2FLD(IOM0_DMASTAT_DMATIP, 0), + true); + + } + return status; +} + +static void +program_dma(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + uint32_t ui32Module = pIOMState->ui32Module; + uint32_t index = (pIOMState->ui32LastHPIdxProcessed + 1) % pIOMState->ui32MaxHPTransactions; + am_hal_iom_dma_entry_t *pDMAEntry = &pIOMState->pHPTransactions[index]; + + // + // OFFSETHI + // + IOMn(ui32Module)->OFFSETHI = pDMAEntry->ui32OFFSETHIVal; + + // + // I2C DEVADDR field in DEVCFG + // + IOMn(ui32Module)->DEVCFG = pDMAEntry->ui32DEVCFGVal; + + // + // disable DMA before writing TOTCOUNT. + // + IOMn(ui32Module)->DMACFG = 0x0; + + // + // set DMATOTALCOUNT + // + IOMn(ui32Module)->DMATOTCOUNT = pDMAEntry->ui32DMATOTCOUNTVal; + + // + // set DMATARGADDR + // + IOMn(ui32Module)->DMATARGADDR = pDMAEntry->ui32DMATARGADDRVal; + + // + // Command to set DMACFG to start the DMA operation + // + IOMn(ui32Module)->DMACFG = pDMAEntry->ui32DMACFGVal; + // + // Command to start the transfer. + // + IOMn(ui32Module)->CMD = pDMAEntry->ui32CMDVal; +} + +static uint32_t +sched_hiprio(am_hal_iom_state_t *pIOMState, uint32_t numTrans) +{ + uint32_t ui32NumPend; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + ui32NumPend = pIOMState->ui32NumHPEntries; + pIOMState->ui32NumHPEntries += numTrans; + + // + // End the critical section. + // + AM_CRITICAL_END + + + if (0 == ui32NumPend) + { + // Force CQ to Pause + ui32Status = iom_cq_pause(pIOMState); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + pIOMState->ui32TxnInt = 0; + // Clear & Enable DMACMP interrupt + IOMn(pIOMState->ui32Module)->INTCLR = AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP; + IOMn(pIOMState->ui32Module)->INTEN |= AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP; + pIOMState->bHP = true; + // + // Program the DMA + // + program_dma(pIOMState); + } + return ui32Status; +} + + +static uint32_t +iom_add_hp_transaction(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + am_hal_iom_dma_entry_t *pDMAEntry; + uint32_t ui32Dir = psTransaction->eDirection; + uint32_t ui32SRAMAddress; + + uint32_t index = pIOMState->ui32NextHPIdx % pIOMState->ui32MaxHPTransactions; + // + // Check to see if there is enough room in the queue + // + if ( pIOMState->ui32NumHPEntries == pIOMState->ui32MaxHPTransactions ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + ui32SRAMAddress = (ui32Dir == AM_HAL_IOM_TX) ? (uint32_t)psTransaction->pui32TxBuffer : (uint32_t)psTransaction->pui32RxBuffer; + pDMAEntry = &pIOMState->pHPTransactions[index]; + pDMAEntry->ui32OFFSETHIVal = (uint16_t)(psTransaction->ui32Instr >> 8); + pDMAEntry->ui32DEVCFGVal = _VAL2FLD(IOM0_DEVCFG_DEVADDR, psTransaction->uPeerInfo.ui32I2CDevAddr); + pDMAEntry->ui32DMATARGADDRVal = ui32SRAMAddress; + pDMAEntry->ui32DMATOTCOUNTVal = psTransaction->ui32NumBytes; + pDMAEntry->ui32DMACFGVal = + _VAL2FLD(IOM0_DMACFG_DMAPRI, psTransaction->ui8Priority) | + _VAL2FLD(IOM0_DMACFG_DMADIR, ui32Dir == AM_HAL_IOM_TX ? 1 : 0); + + if (psTransaction->ui32NumBytes) + { + pDMAEntry->ui32DMACFGVal |= IOM0_DMACFG_DMAEN_Msk; + } + // + // Command to start the transfer. + // + pDMAEntry->ui32CMDVal = build_cmd((pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE) ? psTransaction->uPeerInfo.ui32SpiChipSelect : 0, // ChipSelect + ui32Dir, // ui32Dir + psTransaction->bContinue, // ui32Cont + psTransaction->ui32Instr, // ui32Offset + psTransaction->ui32InstrLen, // ui32OffsetCnt + psTransaction->ui32NumBytes); // ui32Bytes + + pDMAEntry->pfnCallback = pfnCallback; + pDMAEntry->pCallbackCtxt = pCallbackCtxt; + + pIOMState->ui32NextHPIdx++; + return AM_HAL_STATUS_SUCCESS; +} // am_hal_iom_DmaAddTransaction() + +#else // AM_HAL_IOM_CQ != 1 +static void +run_txn_cmdlist(void *pCQEntry, uint32_t numEntries) +{ + uint32_t ix; + am_hal_cmdq_entry_t *pCmd = (am_hal_cmdq_entry_t *)pCQEntry; + + for ( ix = 0; ix < numEntries; ix++, pCmd++ ) + { + *((uint32_t *)pCmd->address) = pCmd->value; + } + +} // run_txn_cmdlist() + +//***************************************************************************** +// +//! @brief Adds a transaction the IOM Command Queue. +//! +//! @param handle - handle for the interface. +//! @param pTransaction - transaction to add to the CQ +//! @param pfnCallback - pointer the callback function to be executed when //! transaction is complete. +//! +//! This function copies data from the IOM FIFO into the array \e pui32Data. +//! This is how input data from SPI or I2C transactions may be retrieved. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +uint32_t +am_hal_iom_DmaAddTransaction(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + am_hal_iom_txn_cmdlist_t *pCQEntry; + uint32_t index = pIOMState->ui32NextIdx % pIOMState->ui32MaxTransactions; + + // + // Check to see if there is enough room in the queue + // + if ( pIOMState->ui32NumPendTransactions == pIOMState->ui32MaxTransactions ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pCQEntry = &pIOMState->pTransactions[index]; + + + build_txn_cmdlist(pIOMState, pCQEntry, psTransaction); + + // + // Store the callback function pointer. + // + pIOMState->pfnCallback[index] = pfnCallback; + pIOMState->pCallbackCtxt[index] = pCallbackCtxt; + pIOMState->ui32NextIdx++; + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_DmaAddTransaction() +#endif // AM_HAL_IOM_CQ == 1 + +//***************************************************************************** +// +// validate_transaction() +// +//***************************************************************************** +uint32_t +validate_transaction(am_hal_iom_state_t *pIOMState, + am_hal_iom_transfer_t *psTransaction, + bool bBlocking) +{ + uint32_t ui32Offset, ui32OffsetCnt, ui32Dir, ui32Bytes; + + // Note - psTransaction is expected to be validated before calling. + //if ( !psTransaction ) + //{ + // return AM_HAL_STATUS_INVALID_ARG; + //} + + ui32Offset = psTransaction->ui32Instr; + ui32OffsetCnt = psTransaction->ui32InstrLen; + ui32Dir = psTransaction->eDirection; + ui32Bytes = psTransaction->ui32NumBytes; + + // + // Validate parameters + // + if ( (ui32OffsetCnt > AM_HAL_IOM_MAX_OFFSETSIZE) || + (ui32Offset & (0xFFFFFFFF << (ui32OffsetCnt*8))) || + (ui32Bytes && (ui32Dir != AM_HAL_IOM_TX) && (psTransaction->pui32RxBuffer == NULL)) || + (ui32Bytes && (ui32Dir != AM_HAL_IOM_RX) && (psTransaction->pui32TxBuffer == NULL)) || + ((pIOMState->eInterfaceMode == AM_HAL_IOM_I2C_MODE) && + (psTransaction->ui32NumBytes > AM_HAL_IOM_MAX_TXNSIZE_I2C)) || + ((pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE) && + ((psTransaction->uPeerInfo.ui32SpiChipSelect > AM_HAL_IOM_MAX_CS_SPI) || + (psTransaction->ui32NumBytes > AM_HAL_IOM_MAX_TXNSIZE_SPI))) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (!bBlocking) + { +#if (AM_HAL_IOM_CQ != 1) + if (psTransaction->ui32PauseCondition != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (psTransaction->ui32StatusSetClr != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#else + if (psTransaction->ui32PauseCondition & AM_HAL_IOM_PAUSE_FLAG_RESV) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (psTransaction->ui32StatusSetClr & AM_HAL_IOM_SC_RESV_MASK) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif + } + + return AM_HAL_STATUS_SUCCESS; + +} // validate_transaction() + +//***************************************************************************** +// +// IOM uninitialize function +// +//***************************************************************************** +uint32_t +am_hal_iom_uninitialize(void *pHandle) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (pIOMState->prefix.s.bEnable) + { + am_hal_iom_disable(pHandle); + } + + pIOMState->prefix.s.bInit = false; + + // + // Return the status. + // + return status; + +} // am_hal_iom_uninitialize() + +//***************************************************************************** +// +// IOM initialization function +// +//***************************************************************************** +uint32_t +am_hal_iom_initialize(uint32_t ui32Module, void **ppHandle) +{ + // Compile time check to ensure ENTRY_SIZE macros are defined correctly + // incorrect definition will cause divide by 0 error at build time + am_ct_assert((sizeof(am_hal_iom_txn_cmdlist_t) + 8) == AM_HAL_IOM_CQ_ENTRY_SIZE); + am_ct_assert(sizeof(am_hal_iom_dma_entry_t) == AM_HAL_IOM_HIPRIO_ENTRY_SIZE); + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate the module number + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if (ppHandle == NULL) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (g_IOMhandles[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + g_IOMhandles[ui32Module].prefix.s.bInit = true; + g_IOMhandles[ui32Module].prefix.s.bEnable = false; + g_IOMhandles[ui32Module].prefix.s.magic = AM_HAL_MAGIC_IOM; + + // + // Initialize the handle. + // + g_IOMhandles[ui32Module].ui32Module = ui32Module; + + // + // Return the handle. + // + *ppHandle = (void *)&g_IOMhandles[ui32Module]; + + // + // Return the status + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_initialize() + +//***************************************************************************** +// +// IOM enable function +// +//***************************************************************************** +uint32_t +am_hal_iom_enable(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t status = AM_HAL_STATUS_SUCCESS; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if (pIOMState->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // Enable submodule +#if 1 + enable_submodule(pIOMState->ui32Module, ((pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE) ? 0 : 1)); +#endif + +#if MANUAL_POP + IOMn(pIOMState->ui32Module)->FIFOCTRL_b.POPWR = 1; +#endif + + // + // If Enable the Command Queue + // + if ( pIOMState->pNBTxnBuf ) + { + pIOMState->ui32NumPendTransactions = 0; + pIOMState->ui32LastIdxProcessed = 0; +#if (AM_HAL_IOM_CQ == 1) + // Initialize Flags used to force CQ Pause + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_CQ | AM_HAL_IOM_SC_PAUSE_SEQLOOP; + pIOMState->pHPTransactions = NULL; + pIOMState->bHP = false; + pIOMState->block = 0; + pIOMState->ui32NumHPPendingEntries = 0; + pIOMState->ui32NumHPEntries = 0; + pIOMState->eSeq = AM_HAL_IOM_SEQ_NONE; + pIOMState->ui32NumSeqTransactions = 0; + pIOMState->bAutonomous = true; + status = am_hal_iom_CQInit(pIOMState, + pIOMState->ui32NBTxnBufLength, + pIOMState->pNBTxnBuf); +#else + // Determine the maximum number of transactions based on the memory provided + pIOMState->ui32MaxTransactions = pIOMState->ui32NBTxnBufLength * 4 / sizeof(am_hal_iom_txn_cmdlist_t); + if (pIOMState->ui32MaxTransactions > 0) + { + if (pIOMState->ui32MaxTransactions > AM_HAL_IOM_MAX_PENDING_TRANSACTIONS) + { + pIOMState->ui32MaxTransactions = AM_HAL_IOM_MAX_PENDING_TRANSACTIONS; + } + pIOMState->ui32NextIdx = pIOMState->ui32LastIdxProcessed + 1; + pIOMState->pTransactions = (am_hal_iom_txn_cmdlist_t *)pIOMState->pNBTxnBuf; + } +#endif + // Initialize the DMA Trigger Setting + // + // DMATRIG, set DTHREN and/or DCMDCMPEN. + // Note - it is recommended that DTHREN always be set. + // +#if 1 + IOMn(pIOMState->ui32Module)->DMATRIGEN = _VAL2FLD(IOM0_DMATRIGEN_DTHREN, 1); +#endif + } + + if (status == AM_HAL_STATUS_SUCCESS) + { + pIOMState->prefix.s.bEnable = true; + } + + // + // We're done, return the status. + // + return status; + +} // am_hal_iom_enable() + +//***************************************************************************** +// +// IOM disable function +// +//***************************************************************************** +uint32_t +am_hal_iom_disable(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (!pIOMState->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } + + // Check if we have any pending transactions. + if (pIOMState->ui32NumPendTransactions) + { + return AM_HAL_STATUS_IN_USE; + } + + // + // Disable the submodules + // + IOMn(pIOMState->ui32Module)->SUBMODCTRL_b.SMOD0EN = 0; + IOMn(pIOMState->ui32Module)->SUBMODCTRL_b.SMOD1EN = 0; + +#if (AM_HAL_IOM_CQ == 1) + am_hal_IOM_CQReset(pHandle); +#endif + + pIOMState->prefix.s.bEnable = false; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_disable() + +//***************************************************************************** +// +// IOM get status function +// +//***************************************************************************** +uint32_t +am_hal_iom_status_get(void *pHandle, am_hal_iom_status_t *psStatus) +{ + uint32_t ui32Module, ui32IomStat; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!psStatus) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pIOMState->ui32Module; + + // + // Begin critical section while we gather status information. + // + AM_CRITICAL_BEGIN + + ui32IomStat = IOMn(ui32Module)->STATUS; + psStatus->bStatIdle = _FLD2VAL(IOM0_STATUS_IDLEST, ui32IomStat); + psStatus->bStatErr = _FLD2VAL(IOM0_STATUS_ERR, ui32IomStat); + psStatus->bStatCmdAct = _FLD2VAL(IOM0_STATUS_CMDACT, ui32IomStat); + + + // + // Return all the bitfields of DMASTAT. + // + psStatus->ui32DmaStat = IOMn(ui32Module)->DMASTAT; + + psStatus->ui32MaxTransactions = pIOMState->ui32MaxTransactions; + psStatus->ui32NumPendTransactions = pIOMState->ui32NumPendTransactions; + + // + // End the critical section. + // + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_status_get() + +//***************************************************************************** +// +// IOM enable interrupts function +// +//***************************************************************************** +uint32_t +am_hal_iom_interrupt_enable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (ui32IntMask & AM_HAL_IOM_INT_THR) + { + return AM_HAL_STATUS_INVALID_ARG; // Threshold Interupt should not be used. + } + + ui32Module = ((am_hal_iom_state_t*)pHandle)->ui32Module; + + // + // Set the interrupt enables according to the mask. + // + IOMn(ui32Module)->INTEN |= ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_interrupt_enable() + +//***************************************************************************** +// +// IOM disable interrupts function +// +//***************************************************************************** +uint32_t +am_hal_iom_interrupt_disable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_iom_state_t*)pHandle)->ui32Module; + + // + // Clear the interrupt enables according to the mask. + // + IOMn(ui32Module)->INTEN &= ~ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_interrupt_disable() + +//***************************************************************************** +// +// IOM get interrupt status +// +//***************************************************************************** +uint32_t +am_hal_iom_interrupt_status_get(void *pHandle, bool bEnabledOnly, + uint32_t *pui32IntStatus) +{ + uint32_t ui32IntStatus; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOM_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( !pui32IntStatus ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_iom_state_t*)pHandle)->ui32Module; + + ui32IntStatus = IOMn(ui32Module)->INTSTAT; + + if ( bEnabledOnly ) + { + ui32IntStatus &= IOMn(ui32Module)->INTEN; + } + + *pui32IntStatus = ui32IntStatus; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_interrupt_status_get() + +//***************************************************************************** +// +// IOM interrupt clear +// +//***************************************************************************** +uint32_t +am_hal_iom_interrupt_clear(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + ui32Module = ((am_hal_iom_state_t*)pHandle)->ui32Module; + + // + // Clear the requested interrupts. + // + IOMn(ui32Module)->INTCLR = ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_interrupt_clear() + +//***************************************************************************** +// +// IOM interrupt service routine +// +//***************************************************************************** +uint32_t am_hal_iom_interrupt_service(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t index; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pIOMState->ui32Module; + +#if (AM_HAL_IOM_CQ == 1) + if (pIOMState->bHP) + { + // + // Accumulate the INTSTAT for this transaction + // + pIOMState->ui32TxnInt |= ui32IntMask; + + // + // Check for the command completion + // + if (pIOMState->ui32TxnInt & (AM_HAL_IOM_INT_CMDCMP | AM_HAL_IOM_INT_DERR)) + { + // + // We need to wait for the DMA complete as well + // Special case for 0 length DMA - by checking the DMAEN register + // + if ((IOMn(ui32Module)->DMACFG_b.DMAEN == 0) || (pIOMState->ui32TxnInt & (AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_ERR))) + { + // Call the callback + // Need to determine the error, call the callback with proper status + pIOMState->ui32LastHPIdxProcessed++; + pIOMState->ui32NumHPEntries--; + index = pIOMState->ui32LastHPIdxProcessed % pIOMState->ui32MaxHPTransactions; + am_hal_iom_dma_entry_t *pDMAEntry = &pIOMState->pHPTransactions[index]; + if ( pDMAEntry->pfnCallback != NULL ) + { + pDMAEntry->pfnCallback(pDMAEntry->pCallbackCtxt, internal_iom_get_int_err(ui32Module, pIOMState->ui32TxnInt)); + pDMAEntry->pfnCallback = NULL; + } + + if (pIOMState->ui32TxnInt & AM_HAL_IOM_INT_ERR) + { + // + // Do Error recovery + // Disable DMA + // + IOMn(ui32Module)->DMACFG_b.DMAEN = 0; + + // + // Clear DMAERR in DMASTAT + // + IOMn(ui32Module)->DMASTAT = 0; + + // + // Reset Submodule & FIFO + // + internal_iom_reset_on_error(pIOMState, pIOMState->ui32TxnInt & AM_HAL_IOM_INT_ERR); + } + // + // Post next transaction if queue is not empty + // + if (pIOMState->ui32NumHPEntries) + { + // + // Initialize the DMA state machine (clear the DMACPL flag). + // + IOMn(ui32Module)->DMASTAT = 0; + //AM_REGn(IOM, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + pIOMState->ui32TxnInt = 0; + program_dma(pIOMState); + } + else + { + pIOMState->bHP = false; + // Unpause the CQ + // Restore interrupts + IOMn(ui32Module)->INTEN &= ~(AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP); + // Resume the CQ + IOMn(ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_CQ; + } + } + } + return AM_HAL_STATUS_SUCCESS; + } +#endif + if (pIOMState->ui32NumPendTransactions) + { +#if (AM_HAL_IOM_CQ == 1) + am_hal_cmdq_status_t status; + + // + // Get the current and last indexes. + // + if (pIOMState->pCmdQHdl && ((ui32Status = am_hal_cmdq_get_status(pIOMState->pCmdQHdl, &status)) == AM_HAL_STATUS_SUCCESS)) + { + // For Sequence - this can be updated in the callback + pIOMState->bRestart = false; + // + // Figure out which callbacks need to be handled. + // + while ((pIOMState->ui32LastIdxProcessed != status.lastIdxProcessed) && !(pIOMState->bRestart)) + { + pIOMState->ui32LastIdxProcessed++; + pIOMState->ui32NumPendTransactions--; + index = pIOMState->ui32LastIdxProcessed & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1); + if ( pIOMState->pfnCallback[index] != NULL ) + { + pIOMState->pfnCallback[index](pIOMState->pCallbackCtxt[index], AM_HAL_STATUS_SUCCESS); + if (pIOMState->eSeq != AM_HAL_IOM_SEQ_RUNNING) + { + pIOMState->pfnCallback[index] = NULL; + } + } + } + + // For Sequence - this can be updated in the callback + if (!pIOMState->bRestart) + { + // + // Check the CQError - If set it indicates that the current transaction encountered an error + // + if (ui32IntMask & AM_HAL_IOM_INT_ERR) + { + // Need to determine the error, call the callback with proper status + pIOMState->ui32LastIdxProcessed++; + pIOMState->ui32NumPendTransactions--; + index = pIOMState->ui32LastIdxProcessed & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1); + if ( pIOMState->pfnCallback[index] != NULL ) + { + pIOMState->pfnCallback[index](pIOMState->pCallbackCtxt[index], internal_iom_get_int_err(ui32Module, ui32IntMask)); + if (pIOMState->eSeq != AM_HAL_IOM_SEQ_RUNNING) + { + pIOMState->pfnCallback[index] = NULL; + } + } + + // + // Do Error recovery + // Disable CQ + // + IOMn(ui32Module)->CQCFG_b.CQEN = 0; + + // + // Disable DMA + // + IOMn(ui32Module)->DMACFG_b.DMAEN = 0; + + // + // Clear DMAERR in DMASTAT + // + IOMn(ui32Module)->DMASTAT = 0; + + // + // Reset Submodule & FIFO + // + internal_iom_reset_on_error(pIOMState, ui32IntMask & AM_HAL_IOM_INT_ERR); + + // + // Move the command queue at next transaction + // + am_hal_cmdq_error_resume(pIOMState->pCmdQHdl); + if (pIOMState->ui32NumPendTransactions) + { + // Re-enable the CQ + am_hal_iom_CQEnable(pIOMState); + } + } + } + + if (pIOMState->ui32NumPendTransactions == 0) + { + // + // Disable the Command Queue + // + am_hal_iom_CQDisable(pHandle); + } + } +#else // !AM_HAL_IOM_CQ + // + // Accumulate the INTSTAT for this transaction + // + pIOMState->ui32TxnInt |= ui32IntMask; + + // + // Check for the command completion + // + if (pIOMState->ui32TxnInt & (AM_HAL_IOM_INT_CMDCMP | AM_HAL_IOM_INT_DERR)) + { + // + // We need to wait for the DMA complete as well + // Special case for 0 length DMA - by checking the DMAEN register + // + if ((IOMn(ui32Module)->DMACFG_b.DMAEN == 0) || (pIOMState->ui32TxnInt & (AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_ERR))) + { + // Call the callback + // Need to determine the error, call the callback with proper status + pIOMState->ui32LastIdxProcessed++; + pIOMState->ui32NumPendTransactions--; + index = pIOMState->ui32LastIdxProcessed % pIOMState->ui32MaxTransactions; + if ( pIOMState->pfnCallback[index] != NULL ) + { + pIOMState->pfnCallback[index](pIOMState->pCallbackCtxt[index], internal_iom_get_int_err(ui32Module, pIOMState->ui32TxnInt)); + pIOMState->pfnCallback[index] = NULL; + } + + if (pIOMState->ui32TxnInt & AM_HAL_IOM_INT_ERR) + { + // + // Do Error recovery + // Disable DMA + // + IOMn(ui32Module)->DMACFG_b.DMAEN = 0; + + // + // Clear DMAERR in DMASTAT + // + IOMn(ui32Module)->DMASTAT = 0; + + // + // Reset Submodule & FIFO + // + internal_iom_reset_on_error(pIOMState, pIOMState->ui32TxnInt & AM_HAL_IOM_INT_ERR); + } + // + // Post next transaction if queue is not empty + // + if (pIOMState->ui32NumPendTransactions) + { + index = (pIOMState->ui32LastIdxProcessed + 1) % pIOMState->ui32MaxTransactions; + + // + // Initialize the DMA state machine (clear the DMACPL flag). + // + IOMn(ui32Module)->DMASTAT = 0; + //AM_REGn(IOM, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + pIOMState->ui32TxnInt = 0; + run_txn_cmdlist(&pIOMState->pTransactions[index], sizeof(am_hal_iom_txn_cmdlist_t) / sizeof(am_hal_cmdq_entry_t)); + } + } + } +#endif // !AM_HAL_IOM_CQ + + if (pIOMState->ui32NumPendTransactions == 0) + { +#if 0 // Taken off from here - we'll anyways disable it at the start of next transaction + // + // Disable DMA + // + IOMn(ui32Module)->DMACFG_b.DMAEN = 0; +#endif + + // + // Clear interrupts + // Restore IOM interrupts. + // + IOM_SET_INTEN(ui32Module, pIOMState->ui32UserIntCfg); + } + } + + // + // Return the status. + // + return ui32Status; + +} // am_hal_iom_interrupt_service() + +//***************************************************************************** +// +// IOM power control function +// +//***************************************************************************** +uint32_t +am_hal_iom_power_ctrl(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Decode the requested power state and update IOM operation accordingly. + // + switch (ePowerState) + { + case AM_HAL_SYSCTRL_WAKE: + if (bRetainState && !pIOMState->registerState.bValid) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_IOM0 + pIOMState->ui32Module)); + + if (bRetainState) + { + // + // Restore IOM registers + IOMn(pIOMState->ui32Module)->FIFOTHR = pIOMState->registerState.regFIFOTHR; + IOMn(pIOMState->ui32Module)->CLKCFG = pIOMState->registerState.regCLKCFG; + IOMn(pIOMState->ui32Module)->SUBMODCTRL = pIOMState->registerState.regSUBMODCTRL; + IOMn(pIOMState->ui32Module)->CQADDR = pIOMState->registerState.regCQADDR; + IOMn(pIOMState->ui32Module)->CQPAUSEEN = pIOMState->registerState.regCQPAUSEEN; + IOMn(pIOMState->ui32Module)->CQCURIDX = pIOMState->registerState.regCQCURIDX; + IOMn(pIOMState->ui32Module)->CQENDIDX = pIOMState->registerState.regCQENDIDX; + IOMn(pIOMState->ui32Module)->MSPICFG = pIOMState->registerState.regMSPICFG; + IOMn(pIOMState->ui32Module)->MI2CCFG = pIOMState->registerState.regMI2CCFG; + IOMn(pIOMState->ui32Module)->INTEN = pIOMState->registerState.regINTEN; + IOMn(pIOMState->ui32Module)->DMATRIGEN = pIOMState->registerState.regDMATRIGEN; + + // CQFGLAGS are Read-Only and hence can not be directly restored. + // We can try to restore the SWFlags here. Hardware flags depend on external conditions + // and hence can not be restored (assuming the external conditions remain the same, it should be set automatically. + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_SET(pIOMState->registerState.regCQFLAGS & 0xFF); + // + // Set CQCFG last - can not set the enable yet + // + IOMn(pIOMState->ui32Module)->CQCFG = pIOMState->registerState.regCQCFG & ~_VAL2FLD(IOM0_CQCFG_CQEN, IOM0_CQCFG_CQEN_EN); + if (pIOMState->registerState.regCQCFG & _VAL2FLD(IOM0_CQCFG_CQEN, IOM0_CQCFG_CQEN_EN)) + { + am_hal_iom_CQEnable(pIOMState); + } + pIOMState->registerState.bValid = false; + } + break; + + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + // Make sure IOM is not active currently + if (pIOMState->prefix.s.bEnable && + (((IOMn(pIOMState->ui32Module)->STATUS & (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk)) != IOM0_STATUS_IDLEST_Msk) || + pIOMState->ui32NumPendTransactions)) + { + return AM_HAL_STATUS_IN_USE; + } + if (bRetainState) + { + // Save IOM Registers + pIOMState->registerState.regFIFOTHR = IOMn(pIOMState->ui32Module)->FIFOTHR; + pIOMState->registerState.regCLKCFG = IOMn(pIOMState->ui32Module)->CLKCFG; + pIOMState->registerState.regSUBMODCTRL = IOMn(pIOMState->ui32Module)->SUBMODCTRL; + pIOMState->registerState.regCQCFG = IOMn(pIOMState->ui32Module)->CQCFG; + pIOMState->registerState.regCQADDR = IOMn(pIOMState->ui32Module)->CQADDR; + pIOMState->registerState.regCQFLAGS = IOMn(pIOMState->ui32Module)->CQFLAGS; + pIOMState->registerState.regCQPAUSEEN = IOMn(pIOMState->ui32Module)->CQPAUSEEN; + pIOMState->registerState.regCQCURIDX = IOMn(pIOMState->ui32Module)->CQCURIDX; + pIOMState->registerState.regCQENDIDX = IOMn(pIOMState->ui32Module)->CQENDIDX; + pIOMState->registerState.regMSPICFG = IOMn(pIOMState->ui32Module)->MSPICFG; + pIOMState->registerState.regMI2CCFG = IOMn(pIOMState->ui32Module)->MI2CCFG; + pIOMState->registerState.regINTEN = IOMn(pIOMState->ui32Module)->INTEN; + pIOMState->registerState.regDMATRIGEN = IOMn(pIOMState->ui32Module)->DMATRIGEN; + pIOMState->registerState.bValid = true; + } + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_IOM0 + pIOMState->ui32Module)); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_power_ctrl() + +//***************************************************************************** +// +// IOM configuration function. +// +//***************************************************************************** +uint32_t +am_hal_iom_configure(void *pHandle, am_hal_iom_config_t *psConfig) +{ + uint32_t ui32ClkCfg; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if ( (pHandle == NULL) || + (psConfig == NULL) || + (pIOMState->ui32Module >= AM_REG_IOM_NUM_MODULES) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + // Configure not allowed in Enabled state + if (pIOMState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pIOMState->ui32Module; + // + // Save the interface mode and chip select in the global handle. + // + pIOMState->eInterfaceMode = psConfig->eInterfaceMode; + + // + // Set the IOM read/write FIFO thresholds to default values. + // + IOMn(ui32Module)->FIFOTHR = + _VAL2FLD(IOM0_FIFOTHR_FIFORTHR, 16) | + _VAL2FLD(IOM0_FIFOTHR_FIFOWTHR, 16); + + if ( psConfig->eInterfaceMode == AM_HAL_IOM_SPI_MODE ) + { +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate the SPI mode + // + if ( psConfig->eSpiMode > AM_HAL_IOM_SPI_MODE_3 ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (psConfig->ui32ClockFreq > AM_HAL_IOM_MAX_FREQ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Determine the CLKCFG value for SPI. + // + ui32ClkCfg = iom_get_interface_clock_cfg(psConfig->ui32ClockFreq, (psConfig->eSpiMode & 2) >> 1); + + // + // Set the SPI configuration. + // + IOMn(ui32Module)->MSPICFG = + ( ((psConfig->eSpiMode << IOM0_MSPICFG_SPOL_Pos) & (IOM0_MSPICFG_SPHA_Msk | IOM0_MSPICFG_SPOL_Msk)) | + _VAL2FLD(IOM0_MSPICFG_FULLDUP, 0) | + _VAL2FLD(IOM0_MSPICFG_WTFC, IOM0_MSPICFG_WTFC_DIS) | + _VAL2FLD(IOM0_MSPICFG_RDFC, IOM0_MSPICFG_RDFC_DIS) | + _VAL2FLD(IOM0_MSPICFG_MOSIINV, IOM0_MSPICFG_MOSIINV_NORMAL) | + _VAL2FLD(IOM0_MSPICFG_WTFCIRQ, IOM0_MSPICFG_WTFCIRQ_MISO) | + _VAL2FLD(IOM0_MSPICFG_WTFCPOL, IOM0_MSPICFG_WTFCPOL_HIGH) | + _VAL2FLD(IOM0_MSPICFG_RDFCPOL, IOM0_MSPICFG_RDFCPOL_HIGH) | + _VAL2FLD(IOM0_MSPICFG_SPILSB, IOM0_MSPICFG_SPILSB_MSB) | + _VAL2FLD(IOM0_MSPICFG_DINDLY, 0) | + _VAL2FLD(IOM0_MSPICFG_DOUTDLY, 0) | + _VAL2FLD(IOM0_MSPICFG_MSPIRST, 0) ); + } + else if ( psConfig->eInterfaceMode == AM_HAL_IOM_I2C_MODE ) + { + + switch (psConfig->ui32ClockFreq) + { + case AM_HAL_IOM_100KHZ: + // + // settings below should give ~100 kHz + // + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_TOTPER, 0x77) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, 0x3B) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, IOM0_CLKCFG_DIVEN_EN) | + _VAL2FLD(IOM0_CLKCFG_DIV3, IOM0_CLKCFG_DIV3_DIS) | + _VAL2FLD(IOM0_CLKCFG_FSEL, IOM0_CLKCFG_FSEL_HFRC_DIV2) | + _VAL2FLD(IOM0_CLKCFG_IOCLKEN, 1); + IOMn(ui32Module)->MI2CCFG = _VAL2FLD(IOM0_MI2CCFG_STRDIS, 0) | + _VAL2FLD(IOM0_MI2CCFG_SMPCNT, 3) | + _VAL2FLD(IOM0_MI2CCFG_SDAENDLY, 15) | + _VAL2FLD(IOM0_MI2CCFG_SCLENDLY, 0) | + _VAL2FLD(IOM0_MI2CCFG_MI2CRST, 1) | + _VAL2FLD(IOM0_MI2CCFG_SDADLY, 3) | + _VAL2FLD(IOM0_MI2CCFG_ARBEN, IOM0_MI2CCFG_ARBEN_ARBDIS) | + _VAL2FLD(IOM0_MI2CCFG_I2CLSB, IOM0_MI2CCFG_I2CLSB_MSBFIRST) | + _VAL2FLD(IOM0_MI2CCFG_ADDRSZ, IOM0_MI2CCFG_ADDRSZ_ADDRSZ7); + break; + case AM_HAL_IOM_400KHZ: + // + // settings below should give ~400 kHz + // + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_TOTPER, 0x1D) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, 0x0E) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, IOM0_CLKCFG_DIVEN_EN) | + _VAL2FLD(IOM0_CLKCFG_DIV3, IOM0_CLKCFG_DIV3_DIS) | + _VAL2FLD(IOM0_CLKCFG_FSEL, IOM0_CLKCFG_FSEL_HFRC_DIV2) | + _VAL2FLD(IOM0_CLKCFG_IOCLKEN, 1); + IOMn(ui32Module)->MI2CCFG = _VAL2FLD(IOM0_MI2CCFG_STRDIS, 0) | + _VAL2FLD(IOM0_MI2CCFG_SMPCNT, 3) | + _VAL2FLD(IOM0_MI2CCFG_SDAENDLY, 15) | + _VAL2FLD(IOM0_MI2CCFG_SCLENDLY, 2) | + _VAL2FLD(IOM0_MI2CCFG_MI2CRST, 1) | + _VAL2FLD(IOM0_MI2CCFG_SDADLY, 3) | + _VAL2FLD(IOM0_MI2CCFG_ARBEN, IOM0_MI2CCFG_ARBEN_ARBDIS) | + _VAL2FLD(IOM0_MI2CCFG_I2CLSB, IOM0_MI2CCFG_I2CLSB_MSBFIRST) | + _VAL2FLD(IOM0_MI2CCFG_ADDRSZ, IOM0_MI2CCFG_ADDRSZ_ADDRSZ7); + break; + case AM_HAL_IOM_1MHZ: + // + // settings below should give ~860 kHz + // + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_TOTPER, 0x06) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, 0x03) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, IOM0_CLKCFG_DIVEN_EN) | + _VAL2FLD(IOM0_CLKCFG_DIV3, IOM0_CLKCFG_DIV3_DIS) | + _VAL2FLD(IOM0_CLKCFG_FSEL, IOM0_CLKCFG_FSEL_HFRC_DIV4) | + _VAL2FLD(IOM0_CLKCFG_IOCLKEN, 1); + IOMn(ui32Module)->MI2CCFG = _VAL2FLD(IOM0_MI2CCFG_STRDIS, 0) | + _VAL2FLD(IOM0_MI2CCFG_SMPCNT, 0x21) | + _VAL2FLD(IOM0_MI2CCFG_SDAENDLY, 3) | + _VAL2FLD(IOM0_MI2CCFG_SCLENDLY, 0) | + _VAL2FLD(IOM0_MI2CCFG_MI2CRST, 1) | + _VAL2FLD(IOM0_MI2CCFG_SDADLY, 0) | + _VAL2FLD(IOM0_MI2CCFG_ARBEN, IOM0_MI2CCFG_ARBEN_ARBDIS) | + _VAL2FLD(IOM0_MI2CCFG_I2CLSB, IOM0_MI2CCFG_I2CLSB_MSBFIRST) | + _VAL2FLD(IOM0_MI2CCFG_ADDRSZ, IOM0_MI2CCFG_ADDRSZ_ADDRSZ7); + break; + default: + { + //Calculate TOTPER and FSEL based on requested frequency + uint32_t reqFreq = psConfig->ui32ClockFreq; + uint32_t fsel = 2; + uint32_t totper = 0; + for( ; fsel < 128 ; fsel = fsel * 2) + { + //IOM and HFRC are not affected by burst mode + totper = (AM_HAL_IOM_48MHZ / (2 * fsel))/reqFreq - 1; + if(totper < 256) break; + } + + if(fsel == 128) + { + //If fsel is too large, return with error + return AM_HAL_STATUS_INVALID_ARG; + } + + uint32_t fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV2; + + if(fsel == 2) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV2; + else if(fsel == 4) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV4; + else if(fsel == 8) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV8; + else if(fsel == 16) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV16; + else if(fsel == 32) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV32; + else if(fsel == 64) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV64; + + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_TOTPER, totper) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, totper/2) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, IOM0_CLKCFG_DIVEN_EN) | + _VAL2FLD(IOM0_CLKCFG_DIV3, IOM0_CLKCFG_DIV3_DIS) | + _VAL2FLD(IOM0_CLKCFG_FSEL, fsel_bitvalue) | + _VAL2FLD(IOM0_CLKCFG_IOCLKEN, 1); + IOMn(ui32Module)->MI2CCFG = _VAL2FLD(IOM0_MI2CCFG_STRDIS, 0) | + _VAL2FLD(IOM0_MI2CCFG_SMPCNT, 0x21) | + _VAL2FLD(IOM0_MI2CCFG_SDAENDLY, 3) | + _VAL2FLD(IOM0_MI2CCFG_SCLENDLY, 0) | + _VAL2FLD(IOM0_MI2CCFG_MI2CRST, 1) | + _VAL2FLD(IOM0_MI2CCFG_SDADLY, 0) | + _VAL2FLD(IOM0_MI2CCFG_ARBEN, IOM0_MI2CCFG_ARBEN_ARBDIS) | + _VAL2FLD(IOM0_MI2CCFG_I2CLSB, IOM0_MI2CCFG_I2CLSB_MSBFIRST) | + _VAL2FLD(IOM0_MI2CCFG_ADDRSZ, IOM0_MI2CCFG_ADDRSZ_ADDRSZ7); + break; + } + } + + } + else + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Enable and set the clock configuration. + // + ui32ClkCfg |= _VAL2FLD(IOM0_CLKCFG_IOCLKEN, 1); + IOMn(ui32Module)->CLKCFG = ui32ClkCfg; + + pIOMState->ui32BitTimeTicks = AM_HAL_CLKGEN_FREQ_MAX_HZ / psConfig->ui32ClockFreq; + + // + // Set the delay timeout value to the default maximum value. + // + pIOMState->waitTimeout = 1000; + + pIOMState->pNBTxnBuf = psConfig->pNBTxnBuf; + pIOMState->ui32NBTxnBufLength = psConfig->ui32NBTxnBufLength; +#if (AM_HAL_IOM_CQ == 1) + // Worst case minimum CQ entries that can be accomodated in provided buffer + // Need to account for the wrap + pIOMState->ui32MaxPending = ((pIOMState->ui32NBTxnBufLength - 8) * 4 / AM_HAL_IOM_CQ_ENTRY_SIZE); + if (pIOMState->ui32MaxPending > AM_HAL_IOM_MAX_PENDING_TRANSACTIONS) + { + pIOMState->ui32MaxPending = AM_HAL_IOM_MAX_PENDING_TRANSACTIONS; + } +#endif + // Disable the DCX + for (uint8_t i = 0; i <= AM_HAL_IOM_MAX_CS_SPI; i++) + { + pIOMState->dcx[i] = 0; + } + + // + // Return the status. + // + return status; + +} // am_hal_iom_configure() + +//***************************************************************************** +// +// IOM blocking transfer function +// +//***************************************************************************** +uint32_t +am_hal_iom_blocking_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction) +{ + uint32_t ui32Cmd, ui32Offset, ui32OffsetCnt, ui32Dir, ui32Cont; + uint32_t ui32FifoRem, ui32FifoSiz; + uint32_t ui32Bytes; + uint32_t ui32IntConfig; + uint32_t *pui32Buffer; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t ui32Module; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + bool bCmdCmp = false; + uint32_t numWait = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOM_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( !psTransaction ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (psTransaction->eDirection > AM_HAL_IOM_RX) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Bytes = psTransaction->ui32NumBytes; + if ( ui32Bytes == 0 ) + { + // + // Only TX is supported for 0-length transactions. A 0-length + // transfer presumes that only an offset value is being written. + // + psTransaction->eDirection = AM_HAL_IOM_TX; + } + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate parameters + // + ui32Status = validate_transaction(pIOMState, psTransaction, true); + + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } +#endif // AM_HAL_DISABLE_API_VALIDATION +#if (AM_HAL_IOM_CQ == 1) + if (pIOMState->eSeq == AM_HAL_IOM_SEQ_RUNNING) + { + // Dynamic additions to sequence not allowed + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif + + ui32Module = pIOMState->ui32Module; + ui32Offset = psTransaction->ui32Instr; + ui32OffsetCnt = psTransaction->ui32InstrLen; + ui32Dir = psTransaction->eDirection; + ui32Cont = psTransaction->bContinue ? 1 : 0; + pui32Buffer = (ui32Dir == AM_HAL_IOM_TX) ? psTransaction->pui32TxBuffer : psTransaction->pui32RxBuffer; + + // + // Make sure any previous non-blocking transfers have completed. + // + ui32Status = am_hal_flash_delay_status_check(pIOMState->waitTimeout, + (uint32_t)&pIOMState->ui32NumPendTransactions, + 0xFFFFFFFF, + 0, + true); + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + // + // Make sure any previous blocking transfer has been completed. + // This check is required to make sure previous transaction has cleared if the blocking call + // finished with a timeout + // + ui32Status = am_hal_flash_delay_status_check(pIOMState->waitTimeout, + (uint32_t)&IOMn(ui32Module)->STATUS, + (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk), + IOM0_STATUS_IDLEST_Msk, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = IOMn(ui32Module)->INTEN; + // + // Disable IOM interrupts as we'll be polling + // + IOMn(ui32Module)->INTEN = 0; + // + // Disable DMA - in case the last transaction was DMA + // For CQ - we disable DMA only at the start of next transaction + // + IOMn(ui32Module)->DMACFG_b.DMAEN = 0; + + + // + // Clear interrupts + // + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; + + // + // Set the dev addr (either 7 or 10 bit as configured in MI2CCFG). + // + IOMn(ui32Module)->DEVCFG = psTransaction->uPeerInfo.ui32I2CDevAddr; + // CMDRPT register has been repurposed for DCX + // Set the DCX + IOMn(ui32Module)->DCX = (pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE) ? pIOMState->dcx[psTransaction->uPeerInfo.ui32SpiChipSelect] : 0; + // + // Build the CMD value + // + + ui32Cmd = pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE ? + psTransaction->uPeerInfo.ui32SpiChipSelect : 0; + ui32Cmd = build_cmd(ui32Cmd, ui32Dir, ui32Cont, ui32Offset, ui32OffsetCnt, ui32Bytes); + + // + // Set the OFFSETHI register. + // + IOMn(ui32Module)->OFFSETHI = (uint16_t)(ui32Offset >> 8); + + ui32Bytes = psTransaction->ui32NumBytes; + + if ( ui32Dir == AM_HAL_IOM_RX ) + { + // + // Start the transfer + // + IOMn(ui32Module)->CMD = ui32Cmd; + + + // + // Start a loop to catch the Rx data. + // + while ( ui32Bytes ) + { + // + // Limit the wait to reasonable limit - instead of blocking forever + // + numWait = 0; + while ((ui32FifoSiz = IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ) < 4) + { + if (numWait++ < AM_HAL_IOM_MAX_BLOCKING_WAIT) + { + if (bCmdCmp && (ui32Bytes > ui32FifoSiz)) + { + // + // No more data expected. Get out of the loop + // + break; + } + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + // + // We've waited long enough - get out! + // + break; + } + bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; + } + if (ui32FifoSiz < 4) + { + // + // Something went wrong - get out and report failure + // + break; + } + + while ((ui32FifoSiz >= 4) && ui32Bytes) + { + // + // Safe to read the FIFO, read 4 bytes + // + uint32_t ui32Read; + ui32Read = IOMn(ui32Module)->FIFOPOP; +#if MANUAL_POP + IOMn(ui32Module)->FIFOPOP = 0x11111111; +#endif + ui32FifoSiz -= 4; + if (ui32Bytes >= 4) + { + *pui32Buffer++ = ui32Read; + ui32Bytes -= 4; + } + else + { + // Copy byte by byte - so as to not corrupt the rest of the buffer + uint8_t *pui8Buffer = (uint8_t *)pui32Buffer; + do + { + *pui8Buffer++ = ui32Read & 0xFF; + ui32Read >>= 8; + } while (--ui32Bytes); + + } + } + } + } + else if ( ui32Dir == AM_HAL_IOM_TX ) + { + // Write data to FIFO first - before starting the transfer + + ui32FifoRem = IOMn(ui32Module)->FIFOPTR_b.FIFO0REM; + while ((ui32FifoRem >= 4) && ui32Bytes) + { + IOMn(ui32Module)->FIFOPUSH = *pui32Buffer++; + ui32FifoRem -= 4; + if (ui32Bytes >= 4) + { + ui32Bytes -= 4; + } + else + { + ui32Bytes = 0; + } + } + + // + // Start the transfer + // + IOMn(ui32Module)->CMD = ui32Cmd; + // + // Keep looping until we're out of bytes to send or command complete (error). + // + while (ui32Bytes) + { + // + // Limit the wait to reasonable limit - instead of blocking forever + // + numWait = 0; + while ((ui32FifoRem = IOMn(ui32Module)->FIFOPTR_b.FIFO0REM) < 4) + { + bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; + if (bCmdCmp || (numWait++ >= AM_HAL_IOM_MAX_BLOCKING_WAIT)) + { + // + // FIFO not expected to change any more - get out + // + break; + } + else + { + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + } + if (bCmdCmp || (ui32FifoRem < 4)) + { + // + // Something went wrong - bail out + // + break; + } + + while ((ui32FifoRem >= 4) && ui32Bytes) + { + IOMn(ui32Module)->FIFOPUSH = *pui32Buffer++; + ui32FifoRem -= 4; + if (ui32Bytes >= 4) + { + ui32Bytes -= 4; + } + else + { + ui32Bytes = 0; + } + } + } + } + + // + // Make sure transfer is completed. + // + ui32Status = am_hal_flash_delay_status_check(AM_HAL_IOM_MAX_BLOCKING_WAIT, + (uint32_t)&IOMn(ui32Module)->STATUS, + (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk), + IOM0_STATUS_IDLEST_Msk, + true); + + if ( ui32Status == AM_HAL_STATUS_SUCCESS ) + { + ui32Status = internal_iom_get_int_err(ui32Module, 0); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + if (ui32Bytes) + { + // Indicates transaction did not finish for some reason + ui32Status = AM_HAL_STATUS_FAIL; + } + } + } + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + // Do Error recovery + // Reset Submodule & FIFO + internal_iom_reset_on_error(pIOMState, IOMn(ui32Module)->INTSTAT); + } + + // + // Clear interrupts + // Re-enable IOM interrupts. + // + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; + IOMn(ui32Module)->INTEN = ui32IntConfig; + + // + // Return the status. + // + return ui32Status; + +} // am_hal_iom_blocking_transfer() + + +//***************************************************************************** +// +// IOM non-blocking transfer function +// +//***************************************************************************** +uint32_t +am_hal_iom_nonblocking_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32NumPend; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOM_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( !psTransaction ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (psTransaction->eDirection > AM_HAL_IOM_RX) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if ( psTransaction->ui32NumBytes == 0 ) + { + // + // Only TX is supported for 0-length transactions. A 0-length + // transfer presumes that only an offset value is being written. + // + psTransaction->eDirection = AM_HAL_IOM_TX; + } + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate parameters + // + ui32Status = validate_transaction(pIOMState, psTransaction, false); + + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + +#if (AM_HAL_IOM_CQ == 1) + am_hal_iom_callback_t pfnCallback1 = pfnCallback; + if (!pIOMState->pCmdQHdl) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + if (pIOMState->eSeq == AM_HAL_IOM_SEQ_RUNNING) + { + // Dynamic additions to sequence not allowed + return AM_HAL_STATUS_INVALID_OPERATION; + } + if (pIOMState->block && (psTransaction->ui32PauseCondition != 0)) + { + // Paused operations not allowed in block mode + return AM_HAL_STATUS_INVALID_OPERATION; + } + if ( !pfnCallback1 && !pIOMState->block && (pIOMState->eSeq == AM_HAL_IOM_SEQ_NONE) && + (pIOMState->ui32NumUnSolicited >= (pIOMState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumPendTransactions get updated in ISR + pfnCallback1 = iom_dummy_callback; + } + // + // DMA defaults to using the Command Queue + // + ui32Status = am_hal_iom_CQAddTransaction(pHandle, psTransaction, pfnCallback1, pCallbackCtxt); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + uint32_t ui32Critical = 0; + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Register for interrupt only if there is a callback + // + ui32Status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, pfnCallback1); + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + ui32NumPend = pIOMState->ui32NumPendTransactions++; + pIOMState->ui32NumSeqTransactions++; + if (pfnCallback) + { + pIOMState->bAutonomous = false; + pIOMState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pIOMState->ui32NumUnSolicited = 0; + } + else + { + pIOMState->ui32NumUnSolicited++; + } + } + if (0 == ui32NumPend) + { + pIOMState->ui32UserIntCfg = IOMn(pIOMState->ui32Module)->INTEN; + IOM_SET_INTEN(pIOMState->ui32Module, AM_HAL_IOM_INT_CQMODE); + am_hal_iom_CQEnable(pIOMState); + } + + } + else + { + am_hal_cmdq_release_block(pIOMState->pCmdQHdl); + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + } +#else // !AM_HAL_IOM_CQ + uint32_t ui32Module = pIOMState->ui32Module; + if (pIOMState->ui32MaxTransactions == 0) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + ui32Status = am_hal_iom_DmaAddTransaction(pHandle, psTransaction, pfnCallback, pCallbackCtxt); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + ui32NumPend = pIOMState->ui32NumPendTransactions++; + + // + // End the critical section. + // + AM_CRITICAL_END + + if (0 == ui32NumPend) + { + uint32_t index = (pIOMState->ui32LastIdxProcessed + 1) % pIOMState->ui32MaxTransactions; + + // + // Disable interrupts so that we don't get any undesired interrupts. + // + pIOMState->ui32UserIntCfg = IOMn(ui32Module)->INTEN; + + // + // Clear interrupts + // + IOM_SET_INTEN(ui32Module, AM_HAL_IOM_INT_DMAMODE); + + + // + // Initialize the DMA state machine (clear the DMACPL flag). + // + IOMn(ui32Module)->DMASTAT = 0; + pIOMState->ui32TxnInt = 0; + + // + // Run the command list + // + run_txn_cmdlist(&pIOMState->pTransactions[index], sizeof(am_hal_iom_txn_cmdlist_t) / sizeof(am_hal_cmdq_entry_t)); + } + } +#endif // !AM_HAL_IOM_CQ + + // + // Return the status. + // + return ui32Status; + +} // am_hal_iom_nonblocking_transfer() + +//***************************************************************************** +// +//! @brief Perform a simple full-duplex transaction to the SPI interface. +//! +//! This function performs SPI full-duplex operation to a selected SPI device. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32TxData array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui32TxData array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +uint32_t +am_hal_iom_spi_blocking_fullduplex(void *pHandle, + am_hal_iom_transfer_t *psTransaction) +{ + uint32_t ui32Cmd, ui32Offset, ui32OffsetCnt, ui32Dir, ui32Cont; + uint32_t ui32FifoRem, ui32FifoSiz; + uint32_t ui32Bytes; + uint32_t ui32RxBytes; + uint32_t ui32IntConfig; + uint32_t *pui32TxBuffer; + uint32_t *pui32RxBuffer; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t ui32Module; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + bool bCmdCmp = false; + uint32_t numWait = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOM_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( !psTransaction ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if ( psTransaction->eDirection != AM_HAL_IOM_FULLDUPLEX ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Validate parameters + // + ui32Status = validate_transaction(pIOMState, psTransaction, true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pIOMState->ui32Module; + ui32Offset = psTransaction->ui32Instr; + ui32OffsetCnt = psTransaction->ui32InstrLen; + ui32Bytes = psTransaction->ui32NumBytes; + ui32Dir = psTransaction->eDirection; + ui32Cont = psTransaction->bContinue ? 1 : 0; + pui32RxBuffer = psTransaction->pui32RxBuffer; + pui32TxBuffer = psTransaction->pui32TxBuffer; + + // + // Make sure any previous non-blocking transfers have completed. + // + ui32Status = am_hal_flash_delay_status_check(pIOMState->waitTimeout, + (uint32_t)&pIOMState->ui32NumPendTransactions, + 0xFFFFFFFF, + 0, + true); + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + // + // Make sure any previous blocking transfer has been completed. + // This check is required to make sure previous transaction has cleared if the blocking call + // finished with a timeout + // + ui32Status = am_hal_flash_delay_status_check(pIOMState->waitTimeout, + (uint32_t)&IOMn(ui32Module)->STATUS, + (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk), + IOM0_STATUS_IDLEST_Msk, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = IOMn(ui32Module)->INTEN; + + // + // Disable IOM interrupts as we'll be polling + // + IOMn(ui32Module)->INTEN = 0; + + // + // Clear interrupts + // + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; + + // + // Set the dev addr (either 7 or 10 bit as configured in MI2CCFG). + // + IOMn(ui32Module)->DEVCFG = psTransaction->uPeerInfo.ui32I2CDevAddr; + // CMDRPT register has been repurposed for DCX + // Set the DCX + IOMn(ui32Module)->DCX = pIOMState->dcx[psTransaction->uPeerInfo.ui32SpiChipSelect]; + + // + // Build the CMD value + // + + ui32Cmd = pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE ? + psTransaction->uPeerInfo.ui32SpiChipSelect : 0; + ui32Cmd = build_cmd(ui32Cmd, ui32Dir, ui32Cont, ui32Offset, ui32OffsetCnt, ui32Bytes); + + // + // Set the OFFSETHI register. + // + IOMn(ui32Module)->OFFSETHI = (uint16_t)(ui32Offset >> 8); + + // + // Set FULLDUPLEX mode + // + IOMn(ui32Module)->MSPICFG |= _VAL2FLD(IOM0_MSPICFG_FULLDUP, 1); + + // + // Start the transfer + // + IOMn(ui32Module)->CMD = ui32Cmd; + + ui32Bytes = psTransaction->ui32NumBytes; + ui32RxBytes = ui32Bytes; + + // + // Start a loop to catch the Rx data. + // + // + // Keep looping until we're out of bytes to send or command complete (error). + // + while (ui32Bytes || ui32RxBytes) + { + // + // Limit the wait to reasonable limit - instead of blocking forever + // + numWait = 0; + ui32FifoRem = IOMn(ui32Module)->FIFOPTR_b.FIFO0REM; + ui32FifoSiz = IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ; + + while ((ui32FifoRem < 4) && + (ui32FifoSiz < 4)) + { + if (numWait++ < AM_HAL_IOM_MAX_BLOCKING_WAIT) + { + if (bCmdCmp && (ui32RxBytes > ui32FifoSiz)) + { + // + // No more data expected. Get out of the loop + // + break; + } + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + // + // We've waited long enough - get out! + // + break; + } + bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; + ui32FifoRem = IOMn(ui32Module)->FIFOPTR_b.FIFO0REM; + ui32FifoSiz = IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ; + } + if (bCmdCmp || ((ui32FifoRem < 4) && (ui32FifoSiz < 4))) + { + // + // Something went wrong - bail out + // + break; + } + + while ((ui32FifoRem >= 4) && ui32Bytes) + { + IOMn(ui32Module)->FIFOPUSH = *pui32TxBuffer++; + ui32FifoRem -= 4; + if (ui32Bytes >= 4) + { + ui32Bytes -= 4; + } + else + { + ui32Bytes = 0; + } + } + while ((ui32FifoSiz >= 4) && ui32RxBytes) + { + // + // Safe to read the FIFO, read 4 bytes + // + *pui32RxBuffer++ = IOMn(ui32Module)->FIFOPOP; +#if MANUAL_POP + IOMn(ui32Module)->FIFOPOP = 0x11111111; +#endif + ui32FifoSiz -= 4; + if (ui32RxBytes >= 4) + { + ui32RxBytes -= 4; + } + else + { + ui32RxBytes = 0; + } + } + } + + // + // Make sure transfer is completed. + // + ui32Status = am_hal_flash_delay_status_check(AM_HAL_IOM_MAX_BLOCKING_WAIT, + (uint32_t)&IOMn(ui32Module)->STATUS, + (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk), + IOM0_STATUS_IDLEST_Msk, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + ui32Status = internal_iom_get_int_err(ui32Module, 0); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + if (ui32Bytes) + { + // Indicates transaction did not finish for some reason + ui32Status = AM_HAL_STATUS_FAIL; + } + } + else + { + // Do Error recovery + // Reset Submodule & FIFO + internal_iom_reset_on_error(pIOMState, IOMn(ui32Module)->INTSTAT); + } + + // + // Clear interrupts + // Re-enable IOM interrupts. + // + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; + IOMn(ui32Module)->INTEN = ui32IntConfig; + + // + // Return the status. + // + return ui32Status; + +} + +//***************************************************************************** +// +//! @brief IOM control function +//! +//! @param handle - handle for the IOM. +//! @param eReq - device specific special request code. +//! @param pArgs - pointer to the request specific arguments. +//! +//! This function allows advanced settings +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t am_hal_iom_control(void *pHandle, am_hal_iom_request_e eReq, void *pArgs) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t status = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if (eReq >= AM_HAL_IOM_REQ_MAX) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + uint32_t ui32Module = pIOMState->ui32Module; + switch (eReq) + { + case AM_HAL_IOM_REQ_FLAG_SETCLR: + if (pArgs) + { +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (*((uint32_t *)pArgs) & AM_HAL_IOM_SC_RESV_MASK) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + IOMn(ui32Module)->CQSETCLEAR = *((uint32_t *)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_IOM_REQ_SPI_LSB: + if (pArgs) + { + IOMn(ui32Module)->MSPICFG_b.SPILSB = *((uint32_t *)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_IOM_REQ_SPI_FULLDUPLEX: + if (pArgs) + { + IOMn(ui32Module)->MSPICFG_b.FULLDUP = *((uint32_t *)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_IOM_REQ_SPI_RDTHRESH: + if (pArgs) + { + IOMn(ui32Module)->FIFOTHR_b.FIFORTHR = *((uint32_t *)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_IOM_REQ_SPI_WRTHRESH: + if (pArgs) + { + IOMn(ui32Module)->FIFOTHR_b.FIFOWTHR = *((uint32_t *)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_IOM_REQ_PAUSE: + // Force CQ to Paused + status = iom_cq_pause(pIOMState); + break; + + case AM_HAL_IOM_REQ_UNPAUSE: + // Resume the CQ + IOMn(ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_CQ; + break; + + + case AM_HAL_IOM_REQ_SET_SEQMODE: + { + am_hal_iom_seq_e eSeq; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pArgs) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (!pIOMState->pNBTxnBuf) + { + // No space for CMDQ + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + eSeq = *((bool *)pArgs) ? AM_HAL_IOM_SEQ_UNDER_CONSTRUCTION: AM_HAL_IOM_SEQ_NONE; + if (eSeq == pIOMState->eSeq) + { + // Nothing to do + return AM_HAL_STATUS_SUCCESS; + } + +#if 0 // We should be able to operate on sequence even if there are HP transactions in progress + // Make sure there is no high priority transaction in progress + if (pIOMState->ui32NumHPEntries) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif + switch (pIOMState->eSeq) + { + case AM_HAL_IOM_SEQ_RUNNING: + { + // Force CQ to Pause + status = iom_cq_pause(pIOMState); + break; + } + case AM_HAL_IOM_SEQ_NONE: + { + // Make sure there is no non-blocking transaction in progress + if (pIOMState->ui32NumPendTransactions) + { + status = AM_HAL_STATUS_INVALID_OPERATION; + } + break; + } + default: + ; + } + if (status == AM_HAL_STATUS_SUCCESS) + { + // Reset the cmdq + am_hal_cmdq_reset(pIOMState->pCmdQHdl); + pIOMState->ui32LastIdxProcessed = 0; + pIOMState->ui32NumSeqTransactions = 0; + pIOMState->ui32NumPendTransactions = 0; + pIOMState->ui32NumUnSolicited = 0; + pIOMState->eSeq = eSeq; + pIOMState->bAutonomous = true; + } + break; + } + + case AM_HAL_IOM_REQ_SEQ_END: + { + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + am_hal_cmdq_entry_t *pCQBlock; + uint32_t index; + am_hal_iom_seq_end_t *pLoop = (am_hal_iom_seq_end_t *)pArgs; + uint32_t pause = 0; + uint32_t scUnpause = 0; + uint32_t ui32Critical = 0; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pArgs) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pLoop->ui32PauseCondition & AM_HAL_IOM_PAUSE_FLAG_RESV) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pLoop->ui32StatusSetClr & AM_HAL_IOM_SC_RESV_MASK) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pIOMState->eSeq != AM_HAL_IOM_SEQ_UNDER_CONSTRUCTION) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + if (pIOMState->block) + { + // End the block if the sequence is ending + pIOMState->block = 0; + // Unblock the whole batch of commands in this block + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_BLOCK; + } + + if ((pLoop->bLoop) && (!pIOMState->bAutonomous)) + { + // Need to insert special element in CQ to cause a callback + // This is to reset internal state + ui32Status = am_hal_cmdq_alloc_block(pIOMState->pCmdQHdl, 1, &pCQBlock, &index); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + else + { + // + // Store the callback function pointer. + // + pIOMState->pfnCallback[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = iom_seq_loopback; + pIOMState->pCallbackCtxt[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = (void *)pIOMState; + + // Dummy Entry + pCQBlock->address = (uint32_t)&IOMn(pIOMState->ui32Module)->CQSETCLEAR; + pCQBlock->value = 0; + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Post to the CQ. + // + ui32Status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, true); + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + am_hal_cmdq_release_block(pIOMState->pCmdQHdl); + } + else + { + uint32_t ui32NumPend = pIOMState->ui32NumPendTransactions++; + if (0 == ui32NumPend) + { + pIOMState->ui32UserIntCfg = IOMn(ui32Module)->INTEN; + IOM_SET_INTEN(ui32Module, AM_HAL_IOM_INT_CQMODE); + // Re-enable the CQ + am_hal_iom_CQEnable(pIOMState); + } + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + // Use SWFLAG6 to cause a pause + pause = AM_HAL_IOM_PAUSE_FLAG_SEQLOOP; + // Revert back the flag after SW callback unpauses it + scUnpause = AM_HAL_IOM_SC_PAUSE_SEQLOOP; + } + } + + // Insert the loopback + ui32Status = am_hal_cmdq_alloc_block(pIOMState->pCmdQHdl, sizeof(am_hal_iom_cq_loop_entry_t) / 8, &pCQBlock, &index); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + else + { + am_hal_iom_cq_loop_entry_t *pLoopEntry = (am_hal_iom_cq_loop_entry_t *)pCQBlock; + pLoopEntry->ui32PAUSENAddr = pLoopEntry->ui32PAUSEN2Addr = (uint32_t)&IOMn(ui32Module)->CQPAUSEEN; + pLoopEntry->ui32SETCLRAddr = (uint32_t)&IOMn(ui32Module)->CQSETCLEAR; + pLoopEntry->ui32PAUSEENVal = get_pause_val(pIOMState, pLoop->ui32PauseCondition | pause); + pLoopEntry->ui32PAUSEEN2Val = AM_HAL_IOM_PAUSE_DEFAULT; + pLoopEntry->ui32SETCLRVal = pLoop->ui32StatusSetClr | scUnpause; + + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Post to the CQ. + // + if (pLoop->bLoop) + { + ui32Status = am_hal_cmdq_post_loop_block(pIOMState->pCmdQHdl, false); + } + else + { + ui32Status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, false); + } + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + am_hal_cmdq_release_block(pIOMState->pCmdQHdl); + } + else + { + uint32_t ui32NumPend = pIOMState->ui32NumPendTransactions++; + pIOMState->eSeq = (pLoop->bLoop) ? AM_HAL_IOM_SEQ_RUNNING : AM_HAL_IOM_SEQ_NONE; + if (0 == ui32NumPend) + { + pIOMState->ui32UserIntCfg = IOMn(ui32Module)->INTEN; + IOM_SET_INTEN(ui32Module, AM_HAL_IOM_INT_CQMODE); + // Re-enable the CQ + am_hal_iom_CQEnable(pIOMState); + } + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + } + return AM_HAL_STATUS_SUCCESS; + //break; + } + case AM_HAL_IOM_REQ_INIT_HIPRIO: + { + am_hal_iom_hiprio_cfg_t *pHPCfg = (am_hal_iom_hiprio_cfg_t *)pArgs; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pHPCfg) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + pIOMState->ui32NumHPEntries = pIOMState->ui32LastHPIdxProcessed = 0; + pIOMState->ui32NextHPIdx = pIOMState->ui32LastHPIdxProcessed + 1; + pIOMState->pHPTransactions = (am_hal_iom_dma_entry_t *)pHPCfg->pBuf; + pIOMState->ui32MaxHPTransactions = pHPCfg->size / sizeof(am_hal_iom_dma_entry_t); + break; + } + + case AM_HAL_IOM_REQ_START_BLOCK: + // Pause the next block from proceeding till whole block is finished + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_PAUSE_BLOCK; + pIOMState->block = 1; + pIOMState->ui32NumHPPendingEntries = 0; + break; + + case AM_HAL_IOM_REQ_END_BLOCK: + // Unblock the whole batch of commands in this block + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_BLOCK; + pIOMState->block = 0; + if (pIOMState->ui32NumHPPendingEntries) + { + // Now it is okay to let go of the block of HiPrio transactions + status = sched_hiprio(pIOMState, pIOMState->ui32NumHPPendingEntries); + if (status == AM_HAL_STATUS_SUCCESS) + { + pIOMState->ui32NumHPPendingEntries = 0; + } + } + break; + + case AM_HAL_IOM_REQ_SET_DCX: + { + am_hal_iom_dcx_cfg_t *pDcxCfg = (am_hal_iom_dcx_cfg_t *)pArgs; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pDcxCfg) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if ((pIOMState->eInterfaceMode != AM_HAL_IOM_SPI_MODE) || + (pDcxCfg->cs == pDcxCfg->dcx) || + (pDcxCfg->cs > AM_HAL_IOM_MAX_CS_SPI) || + ((pDcxCfg->dcx != AM_HAL_IOM_DCX_INVALID) && (pDcxCfg->dcx > AM_HAL_IOM_MAX_CS_SPI))) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + if ( !APOLLO3_GE_B0 ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + pIOMState->dcx[pDcxCfg->cs] = (pDcxCfg->dcx == AM_HAL_IOM_DCX_INVALID) ? 0 : (IOM0_DCX_DCXEN_Msk | (0x1 << pDcxCfg->dcx)); + break; + } + + case AM_HAL_IOM_REQ_CQ_RAW: + { +#if (AM_HAL_IOM_CQ == 1) + am_hal_iom_cq_raw_t *pCqRaw = (am_hal_iom_cq_raw_t *)pArgs; + am_hal_cmdq_entry_t *pCQBlock; + am_hal_iom_callback_t pfnCallback1; + + uint32_t ui32Critical = 0; + uint32_t index; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pCqRaw) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (!pIOMState->pCmdQHdl) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // + // Check to see if there is enough room in the CQ + // + if ((pIOMState->ui32NumPendTransactions == AM_HAL_IOM_MAX_PENDING_TRANSACTIONS) || + (am_hal_cmdq_alloc_block(pIOMState->pCmdQHdl, pCqRaw->numEntries + 3, &pCQBlock, &index))) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pCQBlock->address = (uint32_t)&IOMn(pIOMState->ui32Module)->CQPAUSEEN; + pCQBlock->value = get_pause_val(pIOMState, pCqRaw->ui32PauseCondition); + pCQBlock++; + for (uint32_t i = 0; i < pCqRaw->numEntries; i++, pCQBlock++) + { + pCQBlock->address = pCqRaw->pCQEntry[i].address; + pCQBlock->value = pCqRaw->pCQEntry[i].value; + } + // If there is a need - populate the jump back address + if (pCqRaw->pJmpAddr) + { + *(pCqRaw->pJmpAddr) = (uint32_t)pCQBlock; + } + pCQBlock->address = (uint32_t)&IOMn(pIOMState->ui32Module)->CQPAUSEEN; + pCQBlock->value = AM_HAL_IOM_PAUSE_DEFAULT; + pCQBlock++; + pCQBlock->address = (uint32_t)&IOMn(pIOMState->ui32Module)->CQSETCLEAR; + pCQBlock->value = pCqRaw->ui32StatusSetClr; + + pfnCallback1 = pCqRaw->pfnCallback; + if ( !pfnCallback1 && !pIOMState->block && (pIOMState->eSeq == AM_HAL_IOM_SEQ_NONE) && + (pIOMState->ui32NumUnSolicited >= (pIOMState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumPendTransactions get updated in ISR + pfnCallback1 = iom_dummy_callback; + } + // + // Store the callback function pointer. + // + pIOMState->pfnCallback[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pfnCallback1; + pIOMState->pCallbackCtxt[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pCqRaw->pCallbackCtxt; + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Register for interrupt only if there is a callback + // + status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, pfnCallback1); + + if (status == AM_HAL_STATUS_SUCCESS) + { + uint32_t ui32NumPend = pIOMState->ui32NumPendTransactions++; + pIOMState->ui32NumSeqTransactions++; + if (pCqRaw->pfnCallback) + { + pIOMState->bAutonomous = false; + pIOMState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pIOMState->ui32NumUnSolicited = 0; + } + else + { + pIOMState->ui32NumUnSolicited++; + } + } + if (0 == ui32NumPend) + { + pIOMState->ui32UserIntCfg = IOMn(ui32Module)->INTEN; + IOM_SET_INTEN(ui32Module, AM_HAL_IOM_INT_CQMODE); + // Re-enable the CQ + am_hal_iom_CQEnable(pIOMState); + } + } + else + { + am_hal_cmdq_release_block(pIOMState->pCmdQHdl); + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); +#else // !AM_HAL_IOM_CQ + status = AM_HAL_STATUS_INVALID_ARG; +#endif + break; + } + + + default: + status = AM_HAL_STATUS_INVALID_ARG; + } + + return status; +} + +// +// IOM High Priority transfer function +// +uint32_t am_hal_iom_highprio_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!pIOMState->pNBTxnBuf) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + // + // Validate parameters + // + ui32Status = validate_transaction(pIOMState, psTransaction, false); + + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + if (psTransaction->ui32PauseCondition != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (psTransaction->ui32StatusSetClr != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (psTransaction->eDirection > AM_HAL_IOM_RX) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + if (!pIOMState->pHPTransactions) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + +#if (AM_HAL_IOM_CQ == 1) + + ui32Status = iom_add_hp_transaction(pHandle, psTransaction, pfnCallback, pCallbackCtxt); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + if (!(pIOMState->block)) + { + ui32Status = sched_hiprio(pIOMState, 1); + } + else + { + pIOMState->ui32NumHPPendingEntries++; + } + } + +#else + ui32Status = AM_HAL_STATUS_INVALID_OPERATION; +#endif // !AM_HAL_IOM_CQ + + // + // Return the status. + // + return ui32Status; +} + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.h new file mode 100644 index 0000000..c2c68e0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.h @@ -0,0 +1,844 @@ +//***************************************************************************** +// +//! @file am_hal_iom.h +//! +//! @brief Functions for accessing and configuring the IO Master module +//! +//! @addtogroup hal Hardware Abstraction Layer (HAL) +//! @addtogroup iom3 IO Master (SPI/I2C) +//! @ingroup hal +//! @{ + +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_IOM_H +#define AM_HAL_IOM_H + +#include "am_hal_status.h" +#include "am_hal_sysctrl.h" + + +//***************************************************************************** +// +//! CMSIS-Style macro for handling a variable IOM module number. +// +//***************************************************************************** +#define IOMn(n) ((IOM0_Type*)(IOM0_BASE + (n * (IOM1_BASE - IOM0_BASE)))) + +// +// Maximum time to wait for hardware to finish a blocking transaction +// This is an escape to allow for bailing out in case of faulty peripheral +// (e.g. a device pulling the I2C clock low) +// +#define AM_HAL_IOM_MAX_BLOCKING_WAIT 500000 // 0.5 sec + +// +// AM_HAL_IOM_CQ=1 will use the Command Queue in nonblocking transfers. +// 0 uses plain DMA (w/o CQ) in nonblocking transfers. +// This should be enabled only for A1 silicon. +// +#define AM_HAL_IOM_CQ 1 + +// Size guideline for allocation of application supploed buffers +#define AM_HAL_IOM_CQ_ENTRY_SIZE (24 * sizeof(uint32_t)) +#define AM_HAL_IOM_HIPRIO_ENTRY_SIZE (8 * sizeof(uint32_t)) + +#define AM_HAL_IOM_SC_CLEAR(flag) ((flag) << 16) +#define AM_HAL_IOM_SC_SET(flag) ((flag)) + +// For IOM - Need to Clear the flag for unpausing +#define AM_HAL_IOM_SC_UNPAUSE(flag) AM_HAL_IOM_SC_CLEAR(flag) +#define AM_HAL_IOM_SC_PAUSE(flag) AM_HAL_IOM_SC_SET(flag) + +// Use this macro to directly control the flags +#define AM_HAL_IOM_SETCLR(iom, scVal) \ + do { \ + IOMn((iom))->CQSETCLEAR = (scVal); \ + } while (0); + +// Flags 5, 7 & 6 are reserved by HAL +#define AM_HAL_IOM_PAUSE_FLAG_RESV (IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7 | IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6 | IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5) +#define AM_HAL_IOM_SC_RESV_MASK (AM_HAL_IOM_PAUSE_FLAG_RESV | (AM_HAL_IOM_PAUSE_FLAG_RESV << 8) | (AM_HAL_IOM_PAUSE_FLAG_RESV << 16)) + + +// We use SWFLAGEN7 to control SW pausing Command Queue - default unPause +// We use SWFLAGEN6 to pause on the sequece loopback - default Pause +#define AM_HAL_IOM_PAUSE_FLAG_IDX (_VAL2FLD(IOM0_CQPAUSEEN_CQPEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ)) +#define AM_HAL_IOM_PAUSE_FLAG_CQ (_VAL2FLD(IOM0_CQPAUSEEN_CQPEN, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7)) +#define AM_HAL_IOM_PAUSE_FLAG_SEQLOOP (_VAL2FLD(IOM0_CQPAUSEEN_CQPEN, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6)) +#define AM_HAL_IOM_PAUSE_FLAG_BLOCK (_VAL2FLD(IOM0_CQPAUSEEN_CQPEN, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5)) + +// By default - we Pause CQ for no more entries, or force pause from SW +#define AM_HAL_IOM_PAUSE_DEFAULT AM_HAL_IOM_PAUSE_FLAG_IDX +#define AM_HAL_IOM_CQP_PAUSE_DEFAULT (AM_HAL_IOM_PAUSE_FLAG_IDX | AM_HAL_IOM_PAUSE_FLAG_CQ) + +//***************************************************************************** +// +// IOM Specific status codes +// +//***************************************************************************** +typedef enum +{ + // Error in hardware command issued or illegal access by SW + AM_HAL_IOM_ERR_INVALID_OPER = AM_HAL_STATUS_MODULE_SPECIFIC_START, + // Loss of I2C multi-master arbitration + AM_HAL_IOM_ERR_I2C_ARB, + // I2C NAK + AM_HAL_IOM_ERR_I2C_NAK, +} am_hal_iom_err_e; + +//***************************************************************************** +// +// General defines +// +//***************************************************************************** +#define AM_HAL_IOM_FIFO_SIZE_MAX 32 +#define AM_HAL_IOM_MAX_OFFSETSIZE 3 +#define AM_HAL_IOM_MAX_TXNSIZE_SPI 4095 +#define AM_HAL_IOM_MAX_TXNSIZE_I2C 4095 +#define AM_HAL_IOM_MAX_CS_SPI 3 + +//***************************************************************************** +// +//! @brief enumeration types for the IOM. +// +//***************************************************************************** + +// +// IOM mode enumerations +// +typedef enum +{ + AM_HAL_IOM_SPI_MODE, + AM_HAL_IOM_I2C_MODE, + AM_HAL_IOM_NUM_MODES +} am_hal_iom_mode_e; + +// +// Transmit or receive enumerations. +// Make these enums consistent with the IOM CMD register values. +// +typedef enum +{ + AM_HAL_IOM_TX, + AM_HAL_IOM_RX, + AM_HAL_IOM_FULLDUPLEX, +} am_hal_iom_dir_e; + +// +// Enumerate the SPI modes. Note that these are arranged per the ordering of +// SPHA (bit1) and SPOL (bit0) in the IOM.MSPICFG register. +// +typedef enum +{ + AM_HAL_IOM_SPI_MODE_0, // CPOL = 0; CPHA = 0 + AM_HAL_IOM_SPI_MODE_2, // CPOL = 1; CPHA = 0 + AM_HAL_IOM_SPI_MODE_1, // CPOL = 0; CPHA = 1 + AM_HAL_IOM_SPI_MODE_3, // CPOL = 1; CPHA = 1 +} am_hal_iom_spi_mode_e; + + +//***************************************************************************** +// +//! @brief Transfer callback function prototype +// +//***************************************************************************** +typedef void (*am_hal_iom_callback_t)(void *pCallbackCtxt, uint32_t transactionStatus); +// +//***************************************************************************** +// +//! @brief Configuration structure for the IOM. +// +//***************************************************************************** +typedef struct +{ + // + //! Select the interface mode, SPI or I2C + // + am_hal_iom_mode_e eInterfaceMode; + + // + //! Select the interface clock frequency + // + uint32_t ui32ClockFreq; + + // + //! Select the SPI clock mode (polarity/phase). Ignored for I2C operation. + // + am_hal_iom_spi_mode_e eSpiMode; + + // + // Non-Blocking transaction memory configuration + // Set length and pointer to Transfer Control Buffer. + // Length is in 4 byte multiples + // + uint32_t *pNBTxnBuf; + uint32_t ui32NBTxnBufLength; +} +am_hal_iom_config_t; + +//***************************************************************************** +// +//! Configuration structure for an individual SPI device. +// +//***************************************************************************** +typedef struct +{ + // + //! IOM module to use for communicating with this device. + // + uint32_t ui32Module; + + // + //! Chip select signal that should be used for this device. + // + uint32_t ui32ChipSelect; + + // + //! Additional options that will ALWAYS be ORed into the command word. + // + uint32_t ui32Options; +} +am_hal_iom_spi_device_t; + +//***************************************************************************** +// +//! Configuration structure for an individual I2C device. +// +//***************************************************************************** +typedef struct +{ + // + //! IOM module to use for communicating with this device. + // + uint32_t ui32Module; + + // + //! I2C address associated with this device. + // + uint32_t ui32BusAddress; + + // + //! Additional options that will ALWAYS be ORed into the command word. + // + uint32_t ui32Options; +} +am_hal_iom_i2c_device_t; + +//***************************************************************************** +// +//! @brief Status structure for the IOM. +// +//***************************************************************************** +typedef struct +{ + // + // IOM status. + // + bool bStatIdle; + bool bStatCmdAct; + bool bStatErr; + + //! + //! DMA status + //! One of: + //! AM_HAL_IOM_STATUS_DMA_IN_PROGRESS + //! AM_HAL_IOM_STATUS_XFER_COMPLETE + //! AM_HAL_IOM_STATUS_DMAERR + //! + uint32_t ui32DmaStat; + + uint32_t ui32MaxTransactions; + uint32_t ui32NumPendTransactions; +} +am_hal_iom_status_t; + +// +// transfer structure +// +typedef struct +{ + union + { + // + //! Chip enable (chip select) for this transaction on this device. + // + uint32_t ui32SpiChipSelect; + uint32_t ui32I2CDevAddr; + } uPeerInfo; + + // + //! Instruction length (0,1,2, or 3). + // + uint32_t ui32InstrLen; + + // + //! Device Instruction (aka Command). Often used as the offset. + // + uint32_t ui32Instr; + + // + //! Number of bytes to transfer + // + uint32_t ui32NumBytes; + + // + //! Transfer Direction (Transmit/Receive) + // + am_hal_iom_dir_e eDirection; + + // + //! Buffer + // + uint32_t *pui32TxBuffer; + uint32_t *pui32RxBuffer; + + // + // Continue - holds the SPI or I2C bus for multiple transactions. + // + bool bContinue; + + // + // Repeat Count + // + uint8_t ui8RepeatCount; + + // + //! DMA: Priority 0 = Low (best effort); 1 = High (service immediately) + // + uint8_t ui8Priority; + + //! Command Queue Advanced control on gating conditions for transaction to start + // + uint32_t ui32PauseCondition; + //! Command Queue Advanced Post-Transaction status setting + uint32_t ui32StatusSetClr; + +} am_hal_iom_transfer_t; + +typedef struct +{ + bool bLoop; + //! Command Queue Transaction Gating + uint32_t ui32PauseCondition; + //! Command Queue Post-Transaction status setting + uint32_t ui32StatusSetClr; +} am_hal_iom_seq_end_t; + +typedef struct +{ + uint8_t *pBuf; // Buffer provided to store the high priority transaction context + uint32_t size; // Size of buffer in bytes +} am_hal_iom_hiprio_cfg_t; + +#define AM_HAL_IOM_DCX_INVALID 0xFF +typedef struct +{ + uint8_t cs; // CS for which this configuration applies + uint8_t dcx; // alternate CS line used for DCX - AM_HAL_IOM_DCX_INVALID indicates DCX is not used +} am_hal_iom_dcx_cfg_t; + +typedef struct +{ + //! Command Queue Advanced control on gating conditions for transaction to start + uint32_t ui32PauseCondition; + //! Command Queue Advanced Post-Transaction status setting + uint32_t ui32StatusSetClr; + am_hal_cmdq_entry_t *pCQEntry; + uint32_t numEntries; + am_hal_iom_callback_t pfnCallback; + void *pCallbackCtxt; + uint32_t *pJmpAddr; +} am_hal_iom_cq_raw_t; + +typedef enum +{ + // Used to set/clear 8 CQ Pause flags - reserved flags are defined as AM_HAL_IOM_PAUSE_FLAG_RESV + // Pass uint32_t as pArgs + AM_HAL_IOM_REQ_FLAG_SETCLR = 0, + // Pass uint32_t as pArgs + AM_HAL_IOM_REQ_SPI_LSB, + // Pass uint32_t as pArgs + AM_HAL_IOM_REQ_SPI_FULLDUPLEX, + // Pass uint32_t as pArgs + AM_HAL_IOM_REQ_SPI_RDTHRESH, + // Pass uint32_t as pArgs + AM_HAL_IOM_REQ_SPI_WRTHRESH, + // Pause the CQ gracefully + // pArgs N/A + AM_HAL_IOM_REQ_PAUSE, + // Unpause the CQ + // pArgs N/A + AM_HAL_IOM_REQ_UNPAUSE, + // Get in and out of Sequence Mode - which allows building a sequence, which either runs once, or repeats + // Pass in bool as pArgs - true/false + AM_HAL_IOM_REQ_SET_SEQMODE, + // pArgs N/A + AM_HAL_IOM_REQ_SEQ_END, + // Initialize configuration for high priority trasactions + // These transactions take precedence over existing CQ transactions + // Pass am_hal_iom_hiprio_cfg_t * as pArgs + AM_HAL_IOM_REQ_INIT_HIPRIO, + // Create a block of transactions which are not paused in between + // pArgs N/A + AM_HAL_IOM_REQ_START_BLOCK, + // pArgs N/A + AM_HAL_IOM_REQ_END_BLOCK, + // Control the DCX line + // Pass am_hal_iom_dcx_cfg_t * as pArgs + AM_HAL_IOM_REQ_SET_DCX, + // Raw CQ transaction + // Pass am_hal_iom_cq_raw_t * as pArgs + AM_HAL_IOM_REQ_CQ_RAW, + AM_HAL_IOM_REQ_MAX +} am_hal_iom_request_e; + +#define am_hal_iom_buffer(A) \ +union \ +{ \ + uint32_t words[(A + 3) >> 2]; \ + uint8_t bytes[A]; \ +} + +//***************************************************************************** +// +//! @name IOM Clock Frequencies +//! @brief Macro definitions for common SPI and I2C clock frequencies. +//! +//! These macros may be used with the ui32ClockFrequency member of the +//! am_hal_iom_config_t structure to set the clock frequency of the serial +//! interfaces. +//! +//! This list of frequencies is not exhaustive by any means. If your desired +//! frequency is not in this list, simply set ui32ClockFrequency to the +//! desired frequency (in Hz) when calling am_hal_iom_config(). +// +//***************************************************************************** +#define AM_HAL_IOM_48MHZ 48000000 +#define AM_HAL_IOM_24MHZ 24000000 +#define AM_HAL_IOM_16MHZ 16000000 +#define AM_HAL_IOM_12MHZ 12000000 +#define AM_HAL_IOM_8MHZ 8000000 +#define AM_HAL_IOM_6MHZ 6000000 +#define AM_HAL_IOM_4MHZ 4000000 +#define AM_HAL_IOM_3MHZ 3000000 +#define AM_HAL_IOM_2MHZ 2000000 +#define AM_HAL_IOM_1_5MHZ 1500000 +#define AM_HAL_IOM_1MHZ 1000000 +#define AM_HAL_IOM_750KHZ 750000 +#define AM_HAL_IOM_500KHZ 500000 +#define AM_HAL_IOM_400KHZ 400000 +#define AM_HAL_IOM_375KHZ 375000 +#define AM_HAL_IOM_250KHZ 250000 +#define AM_HAL_IOM_125KHZ 125000 +#define AM_HAL_IOM_100KHZ 100000 +#define AM_HAL_IOM_50KHZ 50000 +#define AM_HAL_IOM_10KHZ 10000 + +// Max Frequency supported in HAL +#define AM_HAL_IOM_MAX_FREQ AM_HAL_IOM_48MHZ + +//***************************************************************************** +// +// IOM Interrupts +// +//***************************************************************************** +#define AM_HAL_IOM_INT_CQERR IOM0_INTEN_CQERR_Msk // Error during command queue operations +#define AM_HAL_IOM_INT_CQUPD IOM0_INTEN_CQUPD_Msk // Command queue operation performed a register write with the register address bit 0 set to 1. +#define AM_HAL_IOM_INT_CQPAUSED IOM0_INTEN_CQPAUSED_Msk // Command queue operation paused +#define AM_HAL_IOM_INT_DERR IOM0_INTEN_DERR_Msk // DMA error received +#define AM_HAL_IOM_INT_DCMP IOM0_INTEN_DCMP_Msk // DMA transfer complete +#define AM_HAL_IOM_INT_ARB IOM0_INTEN_ARB_Msk // Arbitration loss +#define AM_HAL_IOM_INT_STOP IOM0_INTEN_STOP_Msk // STOP command +#define AM_HAL_IOM_INT_START IOM0_INTEN_START_Msk // START command +#define AM_HAL_IOM_INT_ICMD IOM0_INTEN_ICMD_Msk // ILLEGAL command +#define AM_HAL_IOM_INT_IACC IOM0_INTEN_IACC_Msk // Illegal FIFO access +#define AM_HAL_IOM_INT_NAK IOM0_INTEN_NAK_Msk // I2C NAK +#define AM_HAL_IOM_INT_FOVFL IOM0_INTEN_FOVFL_Msk // Write FIFO overflow +#define AM_HAL_IOM_INT_FUNDFL IOM0_INTEN_FUNDFL_Msk // Read FIFO underflow +#define AM_HAL_IOM_INT_THR IOM0_INTEN_THR_Msk // FIFO threshold interrupt +#define AM_HAL_IOM_INT_CMDCMP IOM0_INTEN_CMDCMP_Msk // Command complete + + +#define AM_HAL_IOM_INT_SWERR (AM_HAL_IOM_INT_ICMD | AM_HAL_IOM_INT_IACC | AM_HAL_IOM_INT_FOVFL | AM_HAL_IOM_INT_FUNDFL) +#define AM_HAL_IOM_INT_I2CARBERR (AM_HAL_IOM_INT_ARB) +#define AM_HAL_IOM_INT_INTERR (AM_HAL_IOM_INT_CQERR | AM_HAL_IOM_INT_DERR) +#define AM_HAL_IOM_INT_ALL 0xFFFFFFFF +// +// Unsuccessful end of a transaction results in one more more of the following +// +#define AM_HAL_IOM_INT_ERR (AM_HAL_IOM_INT_SWERR | AM_HAL_IOM_INT_I2CARBERR | AM_HAL_IOM_INT_INTERR | AM_HAL_IOM_INT_NAK) + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! @brief IOM initialization function +//! +//! @param ui32Module - module instance. +//! @param handle - returns the handle for the module instance. +//! +//! This function accepts a module instance, allocates the interface and then +//! returns a handle to be used by the remaining interface functions. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_initialize(uint32_t ui32Module, void **ppHandle); + +//***************************************************************************** +// +//! @brief IOM configuration function +//! +//! @param handle - handle for the IOM. +//! @param pConfig - pointer to the IOM specific configuration. +//! +//! This function configures the interface settings for the IO Master. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_configure(void *pHandle, am_hal_iom_config_t *psConfig); + +//***************************************************************************** +// +//! @brief IOM enable function +//! +//! @param handle - handle for the interface. +//! +//! This function enables the IOM for operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_enable(void *pHandle); + +//***************************************************************************** +// +//! @brief IOM disable function +//! +//! @param handle - handle for the interface. +//! +//! This function disables the IOMaster from operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_disable(void *pHandle); + +//***************************************************************************** +// +//! @brief IOM control function +//! +//! @param handle - handle for the IOM. +//! @param eReq - device specific special request code. +//! @param pArgs - pointer to the request specific arguments. +//! +//! This function allows advanced settings +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_control(void *pHandle, am_hal_iom_request_e eReq, void *pArgs); + +//***************************************************************************** +// +//! @brief IOM status function +//! +//! @param handle - handle for the interface. +//! @param psStatus - pointer to an interface specific structure used to +//! return the status of the interface. +//! +//! This function returns the current status of the interface. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_status_get(void *pHandle, am_hal_iom_status_t *psStatus); + +//***************************************************************************** +// +//! @brief IOM enable interrupts function +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - interface specific interrupt mask. +//! +//! This function enables the specific indicated interrupts. +//! +//! The following are valid enable bits, any of which can be ORed together. +//! AM_REG_IOM_INTEN_CQERR_M // Error during command queue operations +//! AM_REG_IOM_INTEN_CQCMP_M // Command queue operation complete +//! AM_REG_IOM_INTEN_DERR_M // DMA error received +//! AM_REG_IOM_INTEN_DCMP_M // DMA transfer complete +//! AM_REG_IOM_INTEN_ARB_M // Arbitration loss +//! AM_REG_IOM_INTEN_STOP_M // STOP command +//! AM_REG_IOM_INTEN_START_M // START command +//! AM_REG_IOM_INTEN_ICMD // ILLEGAL command +//! AM_REG_IOM_INTEN_IACC_M // Illegal FIFO access +//! AM_REG_IOM_INTEN_NAK_M // I2C NAK +//! AM_REG_IOM_INTEN_FOVFL_M // Write FIFO overflow +//! AM_REG_IOM_INTEN_FUNDFL_M // Read FIFO underflow +//! AM_REG_IOM_INTEN_THR_M // FIFO threshold interrupt +//! AM_REG_IOM_INTEN_CMDCMP_M // Command complete +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_interrupt_enable(void *pHandle, uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief IOM disable interrupts function +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - interface specific interrupt mask. +//! +//! This function disables the specified interrupts. +//! +//! @return status - generic or interface specific status. +//! +//! The following are valid disable bits, any of which can be ORed together. +//! AM_REG_IOM_INTEN_CQERR_M // Error during command queue operations +//! AM_REG_IOM_INTEN_CQCMP_M // Command queue operation complete +//! AM_REG_IOM_INTEN_DERR_M // DMA error received +//! AM_REG_IOM_INTEN_DCMP_M // DMA transfer complete +//! AM_REG_IOM_INTEN_ARB_M // Arbitration loss +//! AM_REG_IOM_INTEN_STOP_M // STOP command +//! AM_REG_IOM_INTEN_START_M // START command +//! AM_REG_IOM_INTEN_ICMD // ILLEGAL command +//! AM_REG_IOM_INTEN_IACC_M // Illegal FIFO access +//! AM_REG_IOM_INTEN_NAK_M // I2C NAK +//! AM_REG_IOM_INTEN_FOVFL_M // Write FIFO overflow +//! AM_REG_IOM_INTEN_FUNDFL_M // Read FIFO underflow +//! AM_REG_IOM_INTEN_THR_M // FIFO threshold interrupt +//! AM_REG_IOM_INTEN_CMDCMP_M // Command complete +// +//***************************************************************************** +extern uint32_t am_hal_iom_interrupt_disable(void *pHandle, uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief IOM get interrupt status +//! +//! @param handle - handle for the interface. +//! @param pui32IntStatus - pointer to a uint32_t to return the interrupt status +//! +//! This function returns the interrupt status for the given peripheral. +//! +//! The following are valid status bits. +//! AM_REG_IOM_INTSTAT_CQERR_M // Error during command queue operations +//! AM_REG_IOM_INTSTAT_CQCMP_M // Command queue operation complete +//! AM_REG_IOM_INTSTAT_DERR_M // DMA error received +//! AM_REG_IOM_INTSTAT_DCMP_M // DMA transfer complete +//! AM_REG_IOM_INTSTAT_ARB_M // Arbitration loss +//! AM_REG_IOM_INTSTAT_STOP_M // STOP command +//! AM_REG_IOM_INTSTAT_START_M // START command +//! AM_REG_IOM_INTSTAT_ICMD // ILLEGAL command +//! AM_REG_IOM_INTSTAT_IACC_M // Illegal FIFO access +//! AM_REG_IOM_INTSTAT_NAK_M // I2C NAK +//! AM_REG_IOM_INTSTAT_FOVFL_M // Write FIFO overflow +//! AM_REG_IOM_INTSTAT_FUNDFL_M // Read FIFO underflow +//! AM_REG_IOM_INTSTAT_THR_M // FIFO threshold interrupt +//! AM_REG_IOM_INTSTAT_CMDCMP_M // Command complete +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_interrupt_status_get(void *pHandle, bool bEnabledOnly, + uint32_t *pui32IntStatus); + +//***************************************************************************** +// +//! @brief IOM interrupt clear +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - interface specific interrupt mask. +//! +//! This function clears the interrupts for the given peripheral. +//! +//! The following are valid clear bits, any of which can be ORed together. +//! AM_REG_IOM_INTCLR_CQERR_M // Error during command queue operations +//! AM_REG_IOM_INTCLR_CQCMP_M // Command queue operation complete +//! AM_REG_IOM_INTCLR_DERR_M // DMA error received +//! AM_REG_IOM_INTCLR_DCMP_M // DMA transfer complete +//! AM_REG_IOM_INTCLR_ARB_M // Arbitration loss +//! AM_REG_IOM_INTCLR_STOP_M // STOP command +//! AM_REG_IOM_INTCLR_START_M // START command +//! AM_REG_IOM_INTCLR_ICMD // ILLEGAL command +//! AM_REG_IOM_INTCLR_IACC_M // Illegal FIFO access +//! AM_REG_IOM_INTCLR_NAK_M // I2C NAK +//! AM_REG_IOM_INTCLR_FOVFL_M // Write FIFO overflow +//! AM_REG_IOM_INTCLR_FUNDFL_M // Read FIFO underflow +//! AM_REG_IOM_INTCLR_THR_M // FIFO threshold interrupt +//! AM_REG_IOM_INTCLR_CMDCMP_M // Command complete +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_interrupt_clear(void *pHandle, uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief IOM interrupt service routine +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - interface specific interrupt mask indicating +//! interrupts to be serviced +//! +//! This function is designed to be called from within the user defined ISR +//! (am_iom_isr) in order to service the non-blocking, queued, or DMA processing +//! for a given module instance. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_interrupt_service(void *pHandle, uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief IOM power control function +//! +//! @param handle - handle for the interface. +//! @param ePowerState - the desired power state to move the peripheral to. +//! @param retainState - flag (if true) to save/restore perhipheral state upon +//! power state change. +//! +//! This function updates the peripheral to a given power state. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_power_ctrl(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool retainState); + +//***************************************************************************** +// +//! @brief IOM blocking transfer function +//! +//! @param handle - handle for the interface. +//! @param pTransaction - pointer to the transaction control structure. +//! +//! This function performs a transaction on the IOM in PIO mode. It handles +//! half duplex transactions only (TX or RX). +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_blocking_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction); + +//***************************************************************************** +// +//! @brief IOM non-blocking transfer function +//! +//! @param handle - handle for the interface. +//! @param pTransaction - pointer to the uniform transaction control structure. +//! @param pfnCallback - pointer the callback function to be executed when +//! transaction is complete can be set to NULL). +//! @param pCallbackCtxt- context registered which is passed on to the callback +//! function +//! +//! This function performs a transaction on the interface. It handles both full +//! and half duplex transactions. The callback is executed when the transaction +//! is complete. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_nonblocking_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt); + +//***************************************************************************** +// +//! @brief IOM uninitialize function +//! +//! @param handle - returns the handle for the module instance. +//! +//! This function accepts a handle to the initialized interface and returns +//! the peripheral instance to a known uninitialized state. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +// +// Uninitialize the interface and return the handle to a known state. +// +extern uint32_t am_hal_iom_uninitialize(void *pHandle); + +//***************************************************************************** +// +//! @brief Perform a Full Duplex transaction. +//! +//! @param handle - handle for the interface. +//! +//! @return HAL status of the operation. +// +//***************************************************************************** +uint32_t +am_hal_iom_spi_blocking_fullduplex(void *pHandle, + am_hal_iom_transfer_t *psTransaction); +// +// IOM High Priority transfer function +// +uint32_t am_hal_iom_highprio_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt); + + +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** +#endif // AM_HAL_IOM_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.c new file mode 100644 index 0000000..35bea24 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.c @@ -0,0 +1,1151 @@ +//***************************************************************************** +// +// am_hal_ios.c +//! @file +//! +//! @brief Functions for interfacing with the IO Slave module +//! +//! @addtogroup ios3 IO Slave (SPI/I2C) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +#define AM_HAL_IOS_MAX_SW_FIFO_SIZE 1023 +#define AM_HAL_MAGIC_IOS 0x123456 +#define AM_HAL_IOS_CHK_HANDLE(h) ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_IOS)) + +//***************************************************************************** +// +// SRAM Buffer structure +// +//***************************************************************************** +am_hal_ios_buffer_t g_sSRAMBuffer; + +//***************************************************************************** +// +// Private Types. +// +//***************************************************************************** +typedef struct +{ + bool bValid; + uint32_t regFIFOCFG; + uint32_t regFIFOTHR; + uint32_t regCFG; + uint32_t regINTEN; + uint32_t regACCINTEN; +} am_hal_ios_register_state_t; + +typedef struct +{ + am_hal_handle_prefix_t prefix; + // + // Physical module number. + // + uint32_t ui32Module; + + am_hal_ios_register_state_t registerState; + + uint8_t *pui8FIFOBase; + uint8_t *pui8FIFOEnd; + uint8_t *pui8FIFOPtr; + uint8_t ui32HwFifoSize; + uint32_t ui32FifoBaseOffset; +} am_hal_ios_state_t; + +//***************************************************************************** +// +// Forward declarations of static funcitons. +// +//***************************************************************************** +static void am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer, + void *pvArray, uint32_t ui32Bytes); +static void fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes); +static uint32_t am_hal_ios_fifo_ptr_set(void *pHandle, uint32_t ui32Offset); +//***************************************************************************** +// +// Function-like macros. +// +//***************************************************************************** +#define am_hal_ios_buffer_empty(psBuffer) \ + ((psBuffer)->ui32Length == 0) + +#define am_hal_ios_buffer_full(psBuffer) \ + ((psBuffer)->ui32Length == (psBuffer)->ui32Capacity) + +#define am_hal_ios_buffer_data_left(psBuffer) \ + ((psBuffer)->ui32Length) + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** +volatile uint8_t * const am_hal_ios_pui8LRAM = (uint8_t *)REG_IOSLAVE_BASEADDR; + +am_hal_ios_state_t g_IOShandles[AM_REG_IOSLAVE_NUM_MODULES]; + +//***************************************************************************** +// +// IOS power control function +// +//***************************************************************************** +uint32_t am_hal_ios_power_ctrl(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOS_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Decode the requested power state and update IOS operation accordingly. + // + switch (ePowerState) + { + case AM_HAL_SYSCTRL_WAKE: + if (bRetainState && !pIOSState->registerState.bValid) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_IOS + pIOSState->ui32Module)); + + if (bRetainState) + { + // + // Restore IOS registers + IOSLAVEn(pIOSState->ui32Module)->FIFOCFG = pIOSState->registerState.regFIFOCFG; + IOSLAVEn(pIOSState->ui32Module)->FIFOTHR = pIOSState->registerState.regFIFOTHR; + IOSLAVEn(pIOSState->ui32Module)->CFG = pIOSState->registerState.regCFG; + IOSLAVEn(pIOSState->ui32Module)->INTEN = pIOSState->registerState.regINTEN; + IOSLAVEn(pIOSState->ui32Module)->REGACCINTEN = pIOSState->registerState.regACCINTEN; + + pIOSState->registerState.bValid = false; + } + break; + + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + if (bRetainState) + { + // Save IOS Registers + pIOSState->registerState.regFIFOCFG = IOSLAVEn(pIOSState->ui32Module)->FIFOCFG; + pIOSState->registerState.regFIFOTHR = IOSLAVEn(pIOSState->ui32Module)->FIFOTHR; + pIOSState->registerState.regCFG = IOSLAVEn(pIOSState->ui32Module)->CFG; + pIOSState->registerState.regINTEN = IOSLAVEn(pIOSState->ui32Module)->INTEN; + pIOSState->registerState.regACCINTEN = IOSLAVEn(pIOSState->ui32Module)->REGACCINTEN; + pIOSState->registerState.bValid = true; + } + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_IOS + pIOSState->ui32Module)); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_power_ctrl() + +//***************************************************************************** +// +// IOS uninitialize function +// +//***************************************************************************** +uint32_t am_hal_ios_uninitialize(void *pHandle) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (pIOSState->prefix.s.bEnable) + { + am_hal_ios_disable(pHandle); + } + + pIOSState->prefix.s.bInit = false; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_uninitialize() + + +//***************************************************************************** +// +// IOS initialization function +// +//***************************************************************************** +uint32_t am_hal_ios_initialize(uint32_t ui32Module, void **ppHandle) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate the module number + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if (ppHandle == NULL) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (g_IOShandles[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + g_IOShandles[ui32Module].prefix.s.bInit = true; + g_IOShandles[ui32Module].prefix.s.bEnable = false; + g_IOShandles[ui32Module].prefix.s.magic = AM_HAL_MAGIC_IOS; + + // + // Initialize the handle. + // + g_IOShandles[ui32Module].ui32Module = ui32Module; + + // + // Return the handle. + // + *ppHandle = (void *)&g_IOShandles[ui32Module]; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_initialize() + +//***************************************************************************** +// +// IOS enable function +// +//***************************************************************************** +uint32_t am_hal_ios_enable(void *pHandle) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if (pIOSState->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + IOSLAVEn(pIOSState->ui32Module)->CFG |= _VAL2FLD(IOSLAVE_CFG_IFCEN, 1); + + pIOSState->prefix.s.bEnable = true; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_enable() + +//***************************************************************************** +// +// IOS disable function +// +//***************************************************************************** +uint32_t am_hal_ios_disable(void *pHandle) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (!pIOSState->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } + + IOSLAVEn(pIOSState->ui32Module)->CFG &= ~(_VAL2FLD(IOSLAVE_CFG_IFCEN, 1)); + + pIOSState->prefix.s.bEnable = false; + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_ios_disable() + +//***************************************************************************** +// +// IOS configuration function. +// +//***************************************************************************** +uint32_t am_hal_ios_configure(void *pHandle, am_hal_ios_config_t *psConfig) +{ + uint32_t ui32LRAMConfig = 0; + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if ( (psConfig == NULL) || + (pIOSState->ui32Module >= AM_REG_IOSLAVE_NUM_MODULES) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + // Configure not allowed in Enabled state + if (pIOSState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pIOSState->ui32Module; + + am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_IOS); + + // + // Record the FIFO parameters for later use. + // + pIOSState->pui8FIFOBase = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32FIFOBase); + pIOSState->pui8FIFOEnd = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32RAMBase); + pIOSState->ui32HwFifoSize = pIOSState->pui8FIFOEnd - pIOSState->pui8FIFOBase; + pIOSState->ui32FifoBaseOffset = psConfig->ui32FIFOBase; + + // + // Initialize the global SRAM buffer + // Total size, which is SRAM Buffer plus the hardware FIFO needs to be + // limited to 1023 + // + if ( psConfig->ui32SRAMBufferCap > (AM_HAL_IOS_MAX_SW_FIFO_SIZE - pIOSState->ui32HwFifoSize + 1) ) + { + psConfig->ui32SRAMBufferCap = (AM_HAL_IOS_MAX_SW_FIFO_SIZE - pIOSState->ui32HwFifoSize + 1); + } + am_hal_ios_buffer_init(&g_sSRAMBuffer, psConfig->pui8SRAMBuffer, psConfig->ui32SRAMBufferCap); + + // + // Calculate the value for the IO Slave FIFO configuration register. + // + ui32LRAMConfig = _VAL2FLD(IOSLAVE_FIFOCFG_ROBASE, psConfig->ui32ROBase >> 3); + ui32LRAMConfig |= _VAL2FLD(IOSLAVE_FIFOCFG_FIFOBASE, psConfig->ui32FIFOBase >> 3); + ui32LRAMConfig |= _VAL2FLD(IOSLAVE_FIFOCFG_FIFOMAX, psConfig->ui32RAMBase >> 3); + + // + // Just in case, disable the IOS + // + am_hal_ios_disable(pHandle); + + // + // Write the configuration register with the user's selected interface + // characteristics. + // + IOSLAVEn(ui32Module)->CFG = psConfig->ui32InterfaceSelect; + + // + // Write the FIFO configuration register to set the memory map for the LRAM. + // + IOSLAVEn(ui32Module)->FIFOCFG = ui32LRAMConfig; + + // + // Clear the FIFO State + // + IOSLAVEn(pIOSState->ui32Module)->FIFOCTR_b.FIFOCTR = 0x0; + IOSLAVEn(pIOSState->ui32Module)->FIFOPTR_b.FIFOSIZ = 0x0; + am_hal_ios_fifo_ptr_set(pHandle, pIOSState->ui32FifoBaseOffset); + + // + // Enable the IOS. The following configuration options can't be set while + // the IOS is disabled. + // + am_hal_ios_enable(pHandle); + + // + // Initialize the FIFO pointer to the beginning of the FIFO section. + // + am_hal_ios_fifo_ptr_set(pHandle, psConfig->ui32FIFOBase); + + // + // Write the FIFO threshold register. + // + IOSLAVEn(ui32Module)->FIFOTHR = psConfig->ui32FIFOThreshold; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_config() + +//***************************************************************************** +// +// IOS enable interrupts function +// +//***************************************************************************** +uint32_t am_hal_ios_interrupt_enable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // OR the desired interrupt into the enable register. + // + IOSLAVEn(ui32Module)->INTEN |= ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_int_enable() + +//***************************************************************************** +// +// IOS disable interrupts function +// +//***************************************************************************** +uint32_t am_hal_ios_interrupt_disable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Clear the desired bit from the interrupt enable register. + // + IOSLAVEn(ui32Module)->INTEN &= ~(ui32IntMask); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_int_disable() + +//***************************************************************************** +// +// IOS interrupt clear +// +//***************************************************************************** +uint32_t am_hal_ios_interrupt_clear(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Use the interrupt clear register to deactivate the chosen interrupt. + // + IOSLAVEn(ui32Module)->INTCLR = ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_int_clear() + +//***************************************************************************** +// +// IOS get interrupt status +// +//***************************************************************************** +uint32_t am_hal_ios_interrupt_status_get(void *pHandle, bool bEnabledOnly, + uint32_t *pui32IntStatus) +{ + uint32_t ui32IntStatus = 0; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOS_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( !pui32IntStatus ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + ui32IntStatus = IOSLAVEn(ui32Module)->INTSTAT; + + if ( bEnabledOnly ) + { + ui32IntStatus &= IOSLAVEn(ui32Module)->INTEN; + } + + *pui32IntStatus = ui32IntStatus; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_int_status_get() + +//***************************************************************************** +// +//! @brief Check the amount of space used in the FIFO +//! +//! @param pui32UsedSpace is bytes used in the Overall FIFO. +//! +//! This function returns the available data in the overall FIFO yet to be +//! read by the host. This takes into account the SRAM buffer and hardware FIFO +//! +//! @return success or error code +// +//***************************************************************************** +uint32_t am_hal_ios_fifo_space_used(void *pHandle, uint32_t *pui32UsedSpace) +{ + uint32_t ui32Module; + uint32_t ui32Val = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if ( !pui32UsedSpace ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Start a critical section for thread safety. + // + AM_CRITICAL_BEGIN + + ui32Val = g_sSRAMBuffer.ui32Length; + ui32Val += IOSLAVEn(ui32Module)->FIFOPTR_b.FIFOSIZ; + + // + // End the critical section + // + AM_CRITICAL_END + + *pui32UsedSpace = ui32Val; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_fifo_space_used() + +//***************************************************************************** +// +//! @brief Check the amount of space left in the FIFO +//! +//! @param pui32LeftSpace is bytes left in the Overall FIFO. +//! +//! This function returns the available space in the overall FIFO to accept +//! new data. This takes into account the SRAM buffer and hardware FIFO +//! +//! @return success or error code +// +//***************************************************************************** +uint32_t am_hal_ios_fifo_space_left(void *pHandle, uint32_t *pui32LeftSpace) +{ + uint32_t ui32Module; + uint32_t ui32Val = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if ( !pui32LeftSpace ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Start a critical section for thread safety. + // + AM_CRITICAL_BEGIN + + // + // We waste one byte in HW FIFO + // + ui32Val = g_sSRAMBuffer.ui32Capacity + ((am_hal_ios_state_t*)pHandle)->ui32HwFifoSize - 1; + ui32Val -= g_sSRAMBuffer.ui32Length; + ui32Val -= IOSLAVEn(ui32Module)->FIFOPTR_b.FIFOSIZ; + + // + // End the critical section + // + AM_CRITICAL_END + + *pui32LeftSpace = ui32Val; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_fifo_space_left() + +//***************************************************************************** +// +//! @brief Check the amount of space left in the hardware FIFO +//! +//! @param pui32LeftSpace is bytes left in the IOS FIFO. +//! +//! This function reads the IOSLAVE FIFOPTR register and determines the amount +//! of space left in the IOS LRAM FIFO. +//! +//! @return success or error code +// +//***************************************************************************** +static uint32_t fifo_space_left(void *pHandle, uint32_t *pui32LeftSpace) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if ( !pui32LeftSpace ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // We waste one byte in HW FIFO + // + *pui32LeftSpace = ((uint32_t)((am_hal_ios_state_t*)pHandle)->ui32HwFifoSize - IOSLAVEn(ui32Module)->FIFOPTR_b.FIFOSIZ - 1); + + return AM_HAL_STATUS_SUCCESS; +} // fifo_space_left() + +//***************************************************************************** +// +// Helper function for managing IOS FIFO writes. +// +//***************************************************************************** +static void fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + uint8_t *pFifoPtr = pIOSState->pui8FIFOPtr; + uint8_t *pFifoBase = pIOSState->pui8FIFOBase; + uint8_t *pFifoEnd = pIOSState->pui8FIFOEnd; + + while ( ui32NumBytes ) + { + // + // Write the data to the FIFO + // + *pFifoPtr++ = *pui8Data++; + ui32NumBytes--; + + // + // Make sure to wrap the FIFO pointer if necessary. + // + if ( pFifoPtr == pFifoEnd ) + { + pFifoPtr = pFifoBase; + } + } + pIOSState->pui8FIFOPtr = pFifoPtr; +} // fifo_write() + +//***************************************************************************** +// +// IOS interrupt service routine +// +//***************************************************************************** +uint32_t am_hal_ios_interrupt_service(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t thresh; + uint32_t freeSpace, usedSpace, chunk1, chunk2, ui32WriteIndex; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Check for FIFO size interrupts. + // + if ( ui32IntMask & AM_HAL_IOS_INT_FSIZE ) + { + thresh = IOSLAVEn(ui32Module)->FIFOTHR_b.FIFOTHR; + + // + // While the FIFO is at or below threshold Add more data + // If Fifo level is above threshold, we're guaranteed an FSIZ interrupt + // + while ( g_sSRAMBuffer.ui32Length && + ((usedSpace = IOSLAVEn(ui32Module)->FIFOPTR_b.FIFOSIZ) <= thresh) ) + { + // + // So, we do have some data in SRAM which needs to be moved to FIFO. + // A chunk of data is a continguous set of bytes in SRAM that can be + // written to FIFO. Determine the chunks of data from SRAM that can + // be written. Up to two chunks possible + // + ui32WriteIndex = g_sSRAMBuffer.ui32WriteIndex; + chunk1 = ((ui32WriteIndex > (uint32_t)g_sSRAMBuffer.ui32ReadIndex) ? \ + (ui32WriteIndex - (uint32_t)g_sSRAMBuffer.ui32ReadIndex) : \ + (g_sSRAMBuffer.ui32Capacity - (uint32_t)g_sSRAMBuffer.ui32ReadIndex)); + chunk2 = g_sSRAMBuffer.ui32Length - chunk1; + // We waste one byte in HW FIFO + freeSpace = ((am_hal_ios_state_t*)pHandle)->ui32HwFifoSize - usedSpace - 1; + // Write data in chunks + // Determine the chunks of data from SRAM that can be written + if ( chunk1 > freeSpace ) + { + fifo_write(pHandle, (uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), freeSpace); + // + // Advance the read index, wrapping if needed. + // + g_sSRAMBuffer.ui32ReadIndex += freeSpace; + // No need to check for wrap as we wrote less than chunk1 + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= freeSpace; + } + else + { + fifo_write(pHandle, (uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), chunk1); + + // + // Update the read index - wrapping as needed + // + g_sSRAMBuffer.ui32ReadIndex += chunk1; + g_sSRAMBuffer.ui32ReadIndex %= g_sSRAMBuffer.ui32Capacity; + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= chunk1; + freeSpace -= chunk1; + + if ( freeSpace && chunk2 ) + { + if ( chunk2 > freeSpace ) + { + fifo_write(pHandle, (uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), freeSpace); + + // + // Advance the read index, wrapping if needed. + // + g_sSRAMBuffer.ui32ReadIndex += freeSpace; + + // No need to check for wrap in chunk2 + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= freeSpace; + } + else + { + fifo_write(pHandle, (uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), chunk2); + // + // Advance the read index, wrapping if needed. + // + g_sSRAMBuffer.ui32ReadIndex += chunk2; + + // No need to check for wrap in chunk2 + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= chunk2; + } + } + } + + // + // Need to retake the FIFO space, after Threshold interrupt has been reenabled + // Clear any spurious FSIZE interrupt that might have got raised + // + IOSLAVEn(ui32Module)->INTCLR_b.FSIZE = 1; + } + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_fifo_service() + +//***************************************************************************** +// +//! @brief Writes the specified number of bytes to the IOS fifo. +//! +//! @param pui8Data is a pointer to the data to be written to the fifo. +//! @param ui32NumBytes is the number of bytes to send. +//! @param pui32WrittenBytes is number of bytes written (could be less than ui32NumBytes, if not enough space) +//! +//! This function will write data from the caller-provided array to the IOS +//! LRAM FIFO. If there is no space in the LRAM FIFO, the data will be copied +//! to a temporary SRAM buffer instead. +//! +//! The maximum message size for the IO Slave is 1023 bytes. +//! +//! @note In order for SRAM copy operations in the function to work correctly, +//! the \e am_hal_ios_buffer_service() function must be called in the ISR for +//! the ioslave module. +//! +//! @return success or error code +// +//***************************************************************************** +uint32_t am_hal_ios_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, uint32_t *pui32WrittenBytes) +{ + uint32_t ui32FIFOSpace = 0; + uint32_t ui32SRAMSpace; + uint32_t ui32SRAMLength; + uint32_t totalBytes = ui32NumBytes; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if ( !pui8Data || !pui32WrittenBytes) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // This operation will only work properly if an SRAM buffer has been + // allocated. Make sure that am_hal_ios_fifo_buffer_init() has been called, + // and the buffer pointer looks valid. + // + am_hal_debug_assert(g_sSRAMBuffer.pui8Data != 0); + + if ( ui32NumBytes == 0 ) + { + *pui32WrittenBytes = 0; + } + else + { + // + // Start a critical section for thread safety. + // + AM_CRITICAL_BEGIN + + ui32SRAMLength = g_sSRAMBuffer.ui32Length; + + // + // End the critical section + // + AM_CRITICAL_END + + // + // If the SRAM buffer is empty, we should just write directly to the FIFO. + // + if ( ui32SRAMLength == 0 ) + { + fifo_space_left(pHandle, &ui32FIFOSpace); + + // + // If the whole message fits, send it now. + // + if ( ui32NumBytes <= ui32FIFOSpace ) + { + fifo_write(pHandle, pui8Data, ui32NumBytes); + ui32NumBytes = 0; + } + else + { + fifo_write(pHandle, pui8Data, ui32FIFOSpace); + ui32NumBytes -= ui32FIFOSpace; + pui8Data += ui32FIFOSpace; + } + } + + // + // If there's still data, write it to the SRAM buffer. + // + if ( ui32NumBytes ) + { + uint32_t idx, writeIdx, capacity, fifoSize; + ui32SRAMSpace = g_sSRAMBuffer.ui32Capacity - ui32SRAMLength; + + writeIdx = g_sSRAMBuffer.ui32WriteIndex; + capacity = g_sSRAMBuffer.ui32Capacity; + + // + // Make sure that the data will fit inside the SRAM buffer. + // + if ( ui32SRAMSpace > ui32NumBytes ) + { + ui32SRAMSpace = ui32NumBytes; + } + + // + // If the data will fit, write it to the SRAM buffer. + // + for ( idx = 0; idx < ui32SRAMSpace; idx++ ) + { + g_sSRAMBuffer.pui8Data[(idx + writeIdx) % capacity] = pui8Data[idx]; + } + + ui32NumBytes -= idx; + + // + // Start a critical section for thread safety before updating length & wrIdx. + // + AM_CRITICAL_BEGIN + + // + // Advance the write index, making sure to wrap if necessary. + // + g_sSRAMBuffer.ui32WriteIndex = (idx + writeIdx) % capacity; + + // + // Update the length value appropriately. + // + g_sSRAMBuffer.ui32Length += idx; + + // + // End the critical section + // + AM_CRITICAL_END + + // It is possible that there is a race condition that the FIFO level has + // gone below the threshold by the time we set the wrIdx above, and hence + // we may never get the threshold interrupt to serve the SRAM data we + // just wrote + + // If that is the case, explicitly generate the FSIZE interrupt from here + fifoSize = IOSLAVEn(ui32Module)->FIFOPTR_b.FIFOSIZ; + + if ( fifoSize <= IOSLAVEn(ui32Module)->FIFOTHR_b.FIFOTHR ) + { + IOSLAVEn(ui32Module)->INTSET_b.FSIZE = 1; + } + } + + *pui32WrittenBytes = totalBytes - ui32NumBytes; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_fifo_write() + +//***************************************************************************** +// +//! @brief Sets the IOS FIFO pointer to the specified LRAM offset. +//! +//! @param ui32Offset is LRAM offset to set the FIFO pointer to. +//! +//! @return success or error code +// +//***************************************************************************** +static uint32_t am_hal_ios_fifo_ptr_set(void *pHandle, uint32_t ui32Offset) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Start a critical section for thread safety. + // + AM_CRITICAL_BEGIN + + // + // Set the FIFO Update bit. + // + IOSLAVEn(ui32Module)->FUPD = 0x1; + + // + // Change the FIFO offset. + // + IOSLAVEn(ui32Module)->FIFOPTR = ui32Offset; + + // + // Clear the FIFO update bit. + // + IOSLAVEn(ui32Module)->FUPD = 0x0; + + // + // Set the global FIFO-pointer tracking variable. + // + ((am_hal_ios_state_t*)pHandle)->pui8FIFOPtr = (uint8_t *) (REG_IOSLAVE_BASEADDR + ui32Offset); + + // + // End the critical section. + // + AM_CRITICAL_END + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_fifo_ptr_set() + +//***************************************************************************** +// +// Initialize an SRAM buffer for use with the IO Slave. +// +//***************************************************************************** +static void am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer, void *pvArray, + uint32_t ui32Bytes) +{ + psBuffer->ui32WriteIndex = 0; + psBuffer->ui32ReadIndex = 0; + psBuffer->ui32Length = 0; + psBuffer->ui32Capacity = ui32Bytes; + psBuffer->pui8Data = (uint8_t *)pvArray; +} // am_hal_ios_buffer_init() + +//***************************************************************************** +// +//! @brief IOS control function +//! +//! @param handle - handle for the IOS. +//! @param eReq - device specific special request code. +//! @param pArgs - pointer to the request specific arguments. +//! +//! This function allows advanced settings +//! +//! @return success or error code +// +//***************************************************************************** +uint32_t am_hal_ios_control(void *pHandle, am_hal_ios_request_e eReq, void *pArgs) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + uint32_t ui32Val = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if ((eReq < AM_HAL_IOS_REQ_ARG_MAX) && (NULL == pArgs)) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + switch (eReq) + { + case AM_HAL_IOS_REQ_HOST_INTSET: + IOSLAVEn(pIOSState->ui32Module)->IOINTCTL = _VAL2FLD(IOSLAVE_IOINTCTL_IOINTSET, *((uint32_t *)pArgs)); + break; + case AM_HAL_IOS_REQ_HOST_INTCLR: + IOSLAVEn(pIOSState->ui32Module)->IOINTCTL = _VAL2FLD(IOSLAVE_IOINTCTL_IOINTCLR, *((uint32_t *)pArgs)); + break; + case AM_HAL_IOS_REQ_HOST_INTGET: + *((uint32_t*)pArgs) = IOSLAVEn(pIOSState->ui32Module)->IOINTCTL_b.IOINT; + break; + case AM_HAL_IOS_REQ_HOST_INTEN_GET: + *((uint32_t*)pArgs) = IOSLAVEn(pIOSState->ui32Module)->IOINTCTL_b.IOINTEN; + break; + case AM_HAL_IOS_REQ_READ_GADATA: + *((uint32_t*)pArgs) = IOSLAVEn(pIOSState->ui32Module)->GENADD_b.GADATA; + break; + case AM_HAL_IOS_REQ_READ_POLL: + while ( IOSLAVEn(pIOSState->ui32Module)->FUPD & IOSLAVE_FUPD_IOREAD_Msk ); + break; + case AM_HAL_IOS_REQ_FIFO_UPDATE_CTR: + am_hal_ios_fifo_space_used(pHandle, &ui32Val); + IOSLAVEn(pIOSState->ui32Module)->FIFOCTR_b.FIFOCTR = ui32Val; + break; + case AM_HAL_IOS_REQ_FIFO_BUF_CLR: + am_hal_ios_buffer_init(&g_sSRAMBuffer, NULL, 0); + // + // Clear the FIFO State + // + IOSLAVEn(pIOSState->ui32Module)->FIFOCTR_b.FIFOCTR = 0x0; + IOSLAVEn(pIOSState->ui32Module)->FIFOPTR_b.FIFOSIZ = 0x0; + break; + case AM_HAL_IOS_REQ_MAX: + return AM_HAL_STATUS_INVALID_ARG; + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// End the doxygen group +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.h new file mode 100644 index 0000000..b2b7ebd --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.h @@ -0,0 +1,378 @@ +//***************************************************************************** +// +// am_hal_ios.h +//! @file +//! +//! @brief Functions for interfacing with the IO Slave module +//! +//! @addtogroup ios3 IO Slave (SPI/I2C) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_IOS_H +#define AM_HAL_IOS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable IOS module number. +// +#define IOSLAVEn(n) ((IOSLAVE_Type*)(IOSLAVE_BASE + (n * (IOSLAVE_BASE - IOSLAVE_BASE)))) +//***************************************************************************** + +//***************************************************************************** +// +//! @name Interface Configuration +//! @brief Macro definitions for configuring the physical interface of the IO +//! Slave +//! +//! These macros may be used with the am_hal_ios_config_t structure to set the +//! physical parameters of the SPI/I2C slave module. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_USE_SPI _VAL2FLD(IOSLAVE_CFG_IFCSEL, IOSLAVE_CFG_IFCSEL_SPI) +#define AM_HAL_IOS_SPIMODE_0 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_0_3) +#define AM_HAL_IOS_SPIMODE_1 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_1_2) +#define AM_HAL_IOS_SPIMODE_2 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_1_2) +#define AM_HAL_IOS_SPIMODE_3 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_0_3) + +#define AM_HAL_IOS_USE_I2C _VAL2FLD(IOSLAVE_CFG_IFCSEL, IOSLAVE_CFG_IFCSEL_I2C) +#define AM_HAL_IOS_I2C_ADDRESS(n) _VAL2FLD(IOSLAVE_CFG_I2CADDR, n) + +#define AM_HAL_IOS_LSB_FIRST _VAL2FLD(IOSLAVE_CFG_LSB, 1) +//! @} + +//***************************************************************************** +// +//! @name Register Access Interrupts +//! @brief Macro definitions for register access interrupts. +//! +//! These macros may be used with any of the +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_ACCESS_INT_00 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 31) +#define AM_HAL_IOS_ACCESS_INT_01 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 30) +#define AM_HAL_IOS_ACCESS_INT_02 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 29) +#define AM_HAL_IOS_ACCESS_INT_03 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 28) +#define AM_HAL_IOS_ACCESS_INT_04 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 27) +#define AM_HAL_IOS_ACCESS_INT_05 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 26) +#define AM_HAL_IOS_ACCESS_INT_06 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 25) +#define AM_HAL_IOS_ACCESS_INT_07 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 24) +#define AM_HAL_IOS_ACCESS_INT_08 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 23) +#define AM_HAL_IOS_ACCESS_INT_09 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 22) +#define AM_HAL_IOS_ACCESS_INT_0A _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 21) +#define AM_HAL_IOS_ACCESS_INT_0B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 20) +#define AM_HAL_IOS_ACCESS_INT_0C _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 19) +#define AM_HAL_IOS_ACCESS_INT_0D _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 18) +#define AM_HAL_IOS_ACCESS_INT_0E _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 17) +#define AM_HAL_IOS_ACCESS_INT_0F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 16) +#define AM_HAL_IOS_ACCESS_INT_13 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 15) +#define AM_HAL_IOS_ACCESS_INT_17 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 14) +#define AM_HAL_IOS_ACCESS_INT_1B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 13) +#define AM_HAL_IOS_ACCESS_INT_1F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 12) +#define AM_HAL_IOS_ACCESS_INT_23 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 11) +#define AM_HAL_IOS_ACCESS_INT_27 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 10) +#define AM_HAL_IOS_ACCESS_INT_2B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 9) +#define AM_HAL_IOS_ACCESS_INT_2F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 8) +#define AM_HAL_IOS_ACCESS_INT_33 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 7) +#define AM_HAL_IOS_ACCESS_INT_37 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 6) +#define AM_HAL_IOS_ACCESS_INT_3B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 5) +#define AM_HAL_IOS_ACCESS_INT_3F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 4) +#define AM_HAL_IOS_ACCESS_INT_43 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 3) +#define AM_HAL_IOS_ACCESS_INT_47 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 2) +#define AM_HAL_IOS_ACCESS_INT_4B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 1) +#define AM_HAL_IOS_ACCESS_INT_4F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 0) +#define AM_HAL_IOS_ACCESS_INT_ALL 0xFFFFFFFF +//! @} + +//***************************************************************************** +// +//! @name I/O Slave Interrupts +//! @brief Macro definitions for I/O slave (IOS) interrupts. +//! +//! These macros may be used with any of the +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_INT_FSIZE IOSLAVE_INTEN_FSIZE_Msk +#define AM_HAL_IOS_INT_FOVFL IOSLAVE_INTEN_FOVFL_Msk +#define AM_HAL_IOS_INT_FUNDFL IOSLAVE_INTEN_FUNDFL_Msk +#define AM_HAL_IOS_INT_FRDERR IOSLAVE_INTEN_FRDERR_Msk +#define AM_HAL_IOS_INT_GENAD IOSLAVE_INTEN_GENAD_Msk +#define AM_HAL_IOS_INT_IOINTW IOSLAVE_INTEN_IOINTW_Msk +#define AM_HAL_IOS_INT_XCMPWR IOSLAVE_INTEN_XCMPWR_Msk +#define AM_HAL_IOS_INT_XCMPWF IOSLAVE_INTEN_XCMPWF_Msk +#define AM_HAL_IOS_INT_XCMPRR IOSLAVE_INTEN_XCMPRR_Msk +#define AM_HAL_IOS_INT_XCMPRF IOSLAVE_INTEN_XCMPRF_Msk +#define AM_HAL_IOS_INT_ALL 0xFFFFFFFF +//! @} + +//***************************************************************************** +// +//! @name I/O Slave Interrupts triggers +//! @brief Macro definitions for I/O slave (IOS) interrupts. +//! +//! These macros may be used with am_hal_ios_interrupt_set and am_hal_ios_interrupt_clear +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_IOINTCTL_INT0 (0x01) +#define AM_HAL_IOS_IOINTCTL_INT1 (0x02) +#define AM_HAL_IOS_IOINTCTL_INT2 (0x04) +#define AM_HAL_IOS_IOINTCTL_INT3 (0x08) +#define AM_HAL_IOS_IOINTCTL_INT4 (0x10) +#define AM_HAL_IOS_IOINTCTL_INT5 (0x20) +//! @} + +//***************************************************************************** +// +// External variable definitions +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief LRAM pointer +//! +//! Pointer to the base of the IO Slave LRAM. +// +//***************************************************************************** +extern volatile uint8_t * const am_hal_ios_pui8LRAM; + +//***************************************************************************** +// +//! @brief Configuration structure for the IO slave module. +//! +//! This structure may be used along with the am_hal_ios_config() function to +//! select key parameters of the IO Slave module. See the descriptions of each +//! parameter within this structure for more information on what they control. +// +//***************************************************************************** +typedef struct +{ + // + //! Interface Selection + //! + //! This word selects the physical behavior of the IO Slave port. For SPI + //! mode, this word should be the logical OR of one or more of the + //! following: + //! + //! AM_HAL_IOS_USE_SPI + //! AM_HAL_IOS_SPIMODE_0 + //! AM_HAL_IOS_SPIMODE_1 + //! AM_HAL_IOS_SPIMODE_2 + //! AM_HAL_IOS_SPIMODE_3 + //! + //! For I2C mode, use the logical OR of one or more of these values instead + //! (where n is the 7 or 10-bit I2C address to use): + //! + //! AM_HAL_IOS_USE_I2C + //! AM_HAL_IOS_I2C_ADDRESS(n) + //! + //! Also, in any mode, you may OR in this value to reverse the order of + //! incoming data bits. + //! + //! AM_HAL_IOS_LSB_FIRST + // + uint32_t ui32InterfaceSelect; + + // + //! Read-Only section + //! + //! The IO Slave LRAM is split into three main sections. The first section + //! is a "Direct Write" section, which may be accessed for reads or write + //! either directly through the Apollo CPU, or over the SPI/I2C bus. The + //! "Direct Write" section always begins at LRAM offset 0x0. At the end of + //! the normal "Direct Write" space, there is a "Read Only" space, which is + //! read/write accessible to the Apollo CPU, but read-only over the I2C/SPI + //! Bus. This word selects the base address of this "Read Only" space. + //! + //! This value may be set to any multiple of 8 between 0x0 and 0x78, + //! inclusive. For the configuration to be valid, \e ui32ROBase must also + //! be less than or equal to \e ui32FIFOBase + //! + //! @note The address given here is in units of BYTES. Since the location + //! of the "Read Only" space may only be set in 8-byte increments, this + //! value must be a multiple of 8. + //! + //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions + //! will shift right by 8 internally. + // + uint32_t ui32ROBase; + + // + //! FIFO section + //! + //! After the "Direct Access" and "Read Only" sections is a section of LRAM + //! allocated to a FIFO. This section is accessible by the Apollo CPU + //! through the FIFO control registers, and accessible on the SPI/I2C bus + //! through the 0x7F address. This word selects the base address of the + //! FIFO space. The FIFO will extend from the address specified here to the + //! address specified in \e ui32RAMBase. + //! + //! This value may be set to any multiple of 8 between 0x0 and 0x78, + //! inclusive. For the configuration to be valid, \e ui32FIFOBase must also + //! be greater than or equal to \e ui32ROBase. + //! + //! @note The address given here is in units of BYTES. Since the location + //! of the "FIFO" space may only be set in 8-byte increments, this value + //! must be a multiple of 8. + //! + //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions + //! will shift right by 8 internally. + // + uint32_t ui32FIFOBase; + + // + //! RAM section + //! + //! At the end of the IOS LRAM, the user may allocate a "RAM" space that + //! can only be accessed by the Apollo CPU. This space will not interact + //! with the SPI/I2C bus at all, and may be used as general-purpose memory. + //! Unlike normal SRAM, this section of LRAM will retain its state through + //! Deep Sleep, so it may be used as a data retention space for + //! ultra-low-power applications. + //! + //! This value may be set to any multiple of 8 between 0x0 and 0x100, + //! inclusive. For the configuration to be valid, \e ui32RAMBase must also + //! be greater than or equal to \e ui32FIFOBase. + //! + //! @note The address given here is in units of BYTES. Since the location + //! of the "FIFO" space may only be set in 8-byte increments, this value + //! must be a multiple of 8. + //! + //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions + //! will shift right by 8 internally. + // + uint32_t ui32RAMBase; + + // + //! FIFO threshold + //! + //! The IO Slave module will trigger an interrupt when the number of + //! entries in the FIFO drops below this number of bytes. + // + uint32_t ui32FIFOThreshold; + + // + // Pointer to an SRAM + // + uint8_t *pui8SRAMBuffer; + uint32_t ui32SRAMBufferCap; +} +am_hal_ios_config_t; + +typedef enum +{ + // Request with arg + AM_HAL_IOS_REQ_HOST_INTSET = 0, + AM_HAL_IOS_REQ_HOST_INTCLR, + AM_HAL_IOS_REQ_HOST_INTGET, + AM_HAL_IOS_REQ_HOST_INTEN_GET, + AM_HAL_IOS_REQ_READ_GADATA, + AM_HAL_IOS_REQ_ARG_MAX, + + // Request without arg + AM_HAL_IOS_REQ_READ_POLL = AM_HAL_IOS_REQ_ARG_MAX, + AM_HAL_IOS_REQ_FIFO_UPDATE_CTR, + AM_HAL_IOS_REQ_FIFO_BUF_CLR, + AM_HAL_IOS_REQ_MAX +} am_hal_ios_request_e; + +typedef struct +{ + uint8_t *pui8Data; + volatile uint32_t ui32WriteIndex; + volatile uint32_t ui32ReadIndex; + volatile uint32_t ui32Length; + uint32_t ui32Capacity; +}am_hal_ios_buffer_t; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern uint32_t am_hal_ios_uninitialize(void *pHandle); +extern uint32_t am_hal_ios_initialize(uint32_t ui32Module, void **ppHandle); +extern uint32_t am_hal_ios_enable(void *pHandle); +extern uint32_t am_hal_ios_disable(void *pHandle); + +// the following interrupts go back to the NVIC +extern uint32_t am_hal_ios_configure(void *pHandle, am_hal_ios_config_t *psConfig); +extern uint32_t am_hal_ios_interrupt_enable(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_ios_interrupt_disable(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_ios_interrupt_clear(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_ios_interrupt_status_get(void *pHandle, bool bEnabledOnly, uint32_t *pui32IntStatus); +extern uint32_t am_hal_ios_interrupt_service(void *pHandle, uint32_t ui32IntMask); +// Returns the number of bytes actually written +extern uint32_t am_hal_ios_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, uint32_t *pui32WrittenBytes); +extern uint32_t am_hal_ios_fifo_space_used(void *pHandle, uint32_t *pui32UsedSpace); +extern uint32_t am_hal_ios_fifo_space_left(void *pHandle, uint32_t *pui32LeftSpace); + +extern uint32_t am_hal_ios_power_ctrl(void *pHandle, am_hal_sysctrl_power_state_e ePowerState, bool bRetainState); +extern uint32_t am_hal_ios_control(void *pHandle, am_hal_ios_request_e eReq, void *pArgs); + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_IOS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.c new file mode 100644 index 0000000..24011cd --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.c @@ -0,0 +1,435 @@ +//***************************************************************************** +// +// am_hal_itm.c +//! @file +//! +//! @brief Functions for operating the instrumentation trace macrocell +//! +//! @addtogroup itm3 Instrumentation Trace Macrocell (ITM) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief Enables the ITM +//! +//! This function enables the ARM ITM by setting the TRCENA bit in the DEMCR +//! register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_enable(void) +{ + // + // To be able to access ITM registers, set the Trace Enable bit + // in the Debug Exception and Monitor Control Register (DEMCR). + // + CoreDebug->DEMCR |= _VAL2FLD(CoreDebug_DEMCR_TRCENA, 1); + while ( !(CoreDebug->DEMCR & _VAL2FLD(CoreDebug_DEMCR_TRCENA, 1)) ); + + // + // Write the key to the ITM Lock Access register to unlock the ITM_TCR. + // + ITM->LAR = ITM_LAR_KEYVAL; + + // + // Set the enable bits in the ITM trace enable register, and the ITM + // control registers to enable trace data output. + // + ITM->TPR = 0x0000000F; + ITM->TER = 0xFFFFFFFF; + + // + // Write to the ITM control and status register. + // + ITM->TCR = + _VAL2FLD(ITM_TCR_TraceBusID, 0x15) | + _VAL2FLD(ITM_TCR_GTSFREQ, 1) | + _VAL2FLD(ITM_TCR_TSPrescale, 1) | + _VAL2FLD(ITM_TCR_SWOENA, 1) | + _VAL2FLD(ITM_TCR_DWTENA, 0) | + _VAL2FLD(ITM_TCR_SYNCENA, 0) | + _VAL2FLD(ITM_TCR_TSENA, 0) | + _VAL2FLD(ITM_TCR_ITMENA, 1); + + + +} + +//***************************************************************************** +// +//! @brief Disables the ITM +//! +//! This function completely disables the ARM ITM by resetting the TRCENA bit +//! in the DEMCR register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_disable(void) +{ + + if ( MCUCTRL->TPIUCTRL == 0 ) + { + // + // This is a disable without enable, which could be the case with some + // earlier versions of SBL. To avoid a hang, ITM (particularly TPIU + // clock) must first be enabled. + // + am_hal_itm_enable(); + } + + // + // Make sure the ITM/TPIU is not busy. + // + am_hal_itm_not_busy(); + + // + // Make sure the ITM_TCR is unlocked. + // + ITM->LAR = ITM_LAR_KEYVAL; + + // + // Disable the ITM. + // + for (int ix = 0; ix < 100; ix++) + { + ITM->TCR &= ~_VAL2FLD(ITM_TCR_ITMENA, 1); + while ( ITM->TCR & (_VAL2FLD(ITM_TCR_ITMENA, 1) | _VAL2FLD(ITM_TCR_BUSY, 1)) ); + } + + // + // Reset the TRCENA bit in the DEMCR register, which should disable the ITM + // for operation. + // + CoreDebug->DEMCR &= ~_VAL2FLD(CoreDebug_DEMCR_TRCENA, 1); + while ( CoreDebug->DEMCR & _VAL2FLD(CoreDebug_DEMCR_TRCENA, 1) ); + + // + // Disable the TPIU clock source in MCU control. + // + MCUCTRL->TPIUCTRL = + _VAL2FLD(MCUCTRL_TPIUCTRL_CLKSEL, MCUCTRL_TPIUCTRL_CLKSEL_LOWPWR) | + _VAL2FLD(MCUCTRL_TPIUCTRL_ENABLE, MCUCTRL_TPIUCTRL_ENABLE_DIS); + while (MCUCTRL->TPIUCTRL); + +} + +//***************************************************************************** +// +//! @brief Checks if itm is busy and provides a delay to flush the fifo +//! +//! This function disables the ARM ITM by resetting the TRCENA bit in the DEMCR +//! register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_not_busy(void) +{ + // + // Make sure the ITM/TPIU is not busy. + // + while (ITM->TCR & _VAL2FLD(ITM_TCR_BUSY, 1)); + + // + // wait for 50us for the data to flush out + // + am_hal_flash_delay(FLASH_CYCLES_US(50)); +} + +//***************************************************************************** +// +//! @brief Enables tracing on a given set of ITM ports +//! +//! @param ui8portNum - Set ports to be enabled +//! +//! Enables tracing on the ports referred to by \e ui8portNum by writing the +//! associated bit in the Trace Privilege Register in the ITM. The value for +//! ui8portNum should be the logical OR one or more of the following values: +//! +//! \e ITM_PRIVMASK_0_7 - enable ports 0 through 7 +//! \e ITM_PRIVMASK_8_15 - enable ports 8 through 15 +//! \e ITM_PRIVMASK_16_23 - enable ports 16 through 23 +//! \e ITM_PRIVMASK_24_31 - enable ports 24 through 31 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_trace_port_enable(uint8_t ui8portNum) +{ + ITM->TPR |= (0x00000001 << (ui8portNum>>3)); +} + +//***************************************************************************** +// +//! @brief Disable tracing on the given ITM stimulus port. +//! +//! @param ui8portNum +//! +//! Disables tracing on the ports referred to by \e ui8portNum by writing the +//! associated bit in the Trace Privilege Register in the ITM. The value for +//! ui8portNum should be the logical OR one or more of the following values: +//! +//! \e ITM_PRIVMASK_0_7 - disable ports 0 through 7 +//! \e ITM_PRIVMASK_8_15 - disable ports 8 through 15 +//! \e ITM_PRIVMASK_16_23 - disable ports 16 through 23 +//! \e ITM_PRIVMASK_24_31 - disable ports 24 through 31 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_trace_port_disable(uint8_t ui8portNum) +{ + ITM->TPR &= ~(0x00000001 << (ui8portNum >> 3)); +} + +//***************************************************************************** +// +//! @brief Poll the given ITM stimulus register until not busy. +//! +//! @param ui32StimReg - stimulus register +//! +//! @return true if not busy, false if busy (timed out or other error). +// +//***************************************************************************** +bool +am_hal_itm_stimulus_not_busy(uint32_t ui32StimReg) +{ + uint32_t ui32StimAddr = (uint32_t)&ITM->PORT[0] + (4 * ui32StimReg); + + // + // Busy waiting until it is available, non-zero means ready. + // + while ( !AM_REGVAL(ui32StimAddr) ); + + return true; +} + +//***************************************************************************** +// +//! @brief Writes a 32-bit value to the given ITM stimulus register. +//! +//! @param ui32StimReg - stimulus register +//! @param ui32Value - value to be written. +//! +//! Write a word to the desired stimulus register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_stimulus_reg_word_write(uint32_t ui32StimReg, uint32_t ui32Value) +{ + uint32_t ui32StimAddr = (uint32_t)&ITM->PORT[0] + (4 * ui32StimReg); + + + // + // Busy waiting until it is available, non-zero means ready + // + while (!AM_REGVAL(ui32StimAddr)); + + // + // Write the register. + // + AM_REGVAL(ui32StimAddr) = ui32Value; +} + +//***************************************************************************** +// +//! @brief Writes a short to the given ITM stimulus register. +//! +//! @param ui32StimReg - stimulus register +//! @param ui16Value - short to be written. +//! +//! Write a short to the desired stimulus register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_stimulus_reg_short_write(uint32_t ui32StimReg, uint16_t ui16Value) +{ + uint32_t ui32StimAddr = (uint32_t)&ITM->PORT[0] + (4 * ui32StimReg); + + // + // Busy waiting until it is available non-zero means ready + // + while ( !AM_REGVAL(ui32StimAddr) ); + + // + // Write the register. + // + *((volatile uint16_t *) ui32StimAddr) = ui16Value; +} + +//***************************************************************************** +// +//! @brief Writes a byte to the given ITM stimulus register. +//! +//! @param ui32StimReg - stimulus register +//! @param ui8Value - byte to be written. +//! +//! Write a byte to the desired stimulus register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_stimulus_reg_byte_write(uint32_t ui32StimReg, uint8_t ui8Value) +{ + uint32_t ui32StimAddr = (uint32_t)&ITM->PORT[0] + (4 * ui32StimReg); + + // + // Busy waiting until it is available (non-zero means ready) + // + while (!AM_REGVAL(ui32StimAddr)); + + // + // Write the register. + // + *((volatile uint8_t *) ui32StimAddr) = ui8Value; +} + +//***************************************************************************** +// +//! @brief Sends a Sync Packet. +//! +//! Sends a sync packet. This can be useful for external software should it +//! become out of sync with the ITM stream. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_sync_send(void) +{ + // + // Write the register. + // + am_hal_itm_stimulus_reg_word_write(AM_HAL_ITM_SYNC_REG, + AM_HAL_ITM_SYNC_VAL); +} + +//***************************************************************************** +// +//! @brief Poll the print stimulus registers until not busy. +//! +//! @return true if not busy, false if busy (timed out or other error). +// +//***************************************************************************** +bool +am_hal_itm_print_not_busy(void) +{ + // + // Poll stimulus register allocated for printing. + // + am_hal_itm_stimulus_not_busy(0); + + + return true; +} + +//***************************************************************************** +// +//! @brief Prints a char string out of the ITM. +//! +//! @param pcString pointer to the character sting +//! +//! This function prints a sting out of the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_print(char *pcString) +{ + uint32_t ui32Length = 0; + + // + // Determine the length of the string. + // + while (*(pcString + ui32Length)) + { + ui32Length++; + } + + // + // If there is no longer a word left, empty out the remaining characters. + // + while (ui32Length) + { + // + // Print string out the ITM. + // + am_hal_itm_stimulus_reg_byte_write(0, (uint8_t)*pcString++); + + // + // Subtract from length. + // + ui32Length--; + } +} +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.h new file mode 100644 index 0000000..2e48039 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.h @@ -0,0 +1,110 @@ +//***************************************************************************** +// +// am_hal_itm.h +//! @file +//! +//! @brief Functions for accessing and configuring the ARM ITM. +//! +//! @addtogroup itm3 Instrumentation Trace Macrocell (ITM) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_ITM_H +#define AM_HAL_ITM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Sync Packet Defines +// +//***************************************************************************** +#define AM_HAL_ITM_SYNC_REG 23 +#define AM_HAL_ITM_SYNC_VAL 0xF8F8F8F8 + +//***************************************************************************** +// +// PrintF Setup +// +//***************************************************************************** +#define AM_HAL_ITM_PRINT_NUM_BYTES 1 +#define AM_HAL_ITM_PRINT_NUM_REGS 1 +extern uint32_t am_hal_itm_print_registers[AM_HAL_ITM_PRINT_NUM_REGS]; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_itm_enable(void); +extern void am_hal_itm_disable(void); +extern void am_hal_itm_not_busy(void); +extern void am_hal_itm_sync_send(void); +extern void am_hal_itm_trace_port_enable(uint8_t ui8portNum); +extern void am_hal_itm_trace_port_disable(uint8_t ui8portNum); +extern bool am_hal_itm_stimulus_not_busy(uint32_t ui32StimReg); +extern void am_hal_itm_stimulus_reg_word_write(uint32_t ui32StimReg, + uint32_t ui32Value); +extern void am_hal_itm_stimulus_reg_short_write(uint32_t ui32StimReg, + uint16_t ui16Value); +extern void am_hal_itm_stimulus_reg_byte_write(uint32_t ui32StimReg, + uint8_t ui8Value); +extern bool am_hal_itm_print_not_busy(void); +extern void am_hal_itm_print(char *pcString); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_ITM_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.c new file mode 100644 index 0000000..8613c05 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.c @@ -0,0 +1,564 @@ +//***************************************************************************** +// +// am_hal_mcuctrl.c +//! @file +//! +//! @brief Functions for interfacing with the MCUCTRL. +//! +//! @addtogroup mcuctrl3 MCU Control (MCUCTRL) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Global Variables. +// +//***************************************************************************** +// +// Define the flash sizes from CHIPPN. +// +const uint32_t +g_am_hal_mcuctrl_flash_size[AM_HAL_MCUCTRL_CHIPPN_FLASH_SIZE_N] = +{ + 16 * 1024, /* 0x0 0x00004000 16 KB */ + 32 * 1024, /* 0x1 0x00008000 32 KB */ + 64 * 1024, /* 0x2 0x00010000 64 KB */ + 128 * 1024, /* 0x3 0x00020000 128 KB */ + 256 * 1024, /* 0x4 0x00040000 256 KB */ + 512 * 1024, /* 0x5 0x00080000 512 KB */ + 1 * 1024 * 1024, /* 0x6 0x00100000 1 MB */ + 2 * 1024 * 1024, /* 0x7 0x00200000 2 MB */ + 3 * 1024 * 1024 / 2, /* 0x8 0x00600000 1.5 MB */ + 0, 0, 0, 0, 0, 0, 0 +}; + +const uint32_t +g_am_hal_mcuctrl_sram_size[AM_HAL_MCUCTRL_CHIPPN_SRAM_SIZE_N] = +{ + 16 * 1024, /* 0x0 0x00004000 16 KB */ + 32 * 1024, /* 0x1 0x00008000 32 KB */ + 64 * 1024, /* 0x2 0x00010000 64 KB */ + 128 * 1024, /* 0x3 0x00020000 128 KB */ + 256 * 1024, /* 0x4 0x00040000 256 KB */ + 512 * 1024, /* 0x5 0x00080000 512 KB */ + 1 * 1024 * 1024, /* 0x6 0x00100000 1 MB */ + 384 * 1024, /* 0x7 0x00200000 384 KB */ + 768 * 1024, /* 0x8 0x000C0000 768 KB */ + 0, 0, 0, 0, 0, 0, 0 +}; + +// **************************************************************************** +// +// device_info_get() +// Gets all relevant device information. +// +// **************************************************************************** +static void +device_info_get(am_hal_mcuctrl_device_t *psDevice) +{ + // + // Read the Part Number. + // + psDevice->ui32ChipPN = MCUCTRL->CHIPPN; + + // + // Read the Chip ID0. + // + psDevice->ui32ChipID0 = MCUCTRL->CHIPID0; + + // + // Read the Chip ID1. + // + psDevice->ui32ChipID1 = MCUCTRL->CHIPID1; + + // + // Read the Chip Revision. + // + psDevice->ui32ChipRev = MCUCTRL->CHIPREV; + + // + // Read the Chip VENDOR ID. + // + psDevice->ui32VendorID = MCUCTRL->VENDORID; + + // + // Read the SKU (new for Apollo3). + // + psDevice->ui32SKU = MCUCTRL->SKU; + + // + // Qualified from Part Number. + // + psDevice->ui32Qualified = (psDevice->ui32ChipPN >> MCUCTRL_CHIPPN_PARTNUM_QUAL_S) & 0x1; + + // + // Flash size from Part Number. + // + psDevice->ui32FlashSize = + g_am_hal_mcuctrl_flash_size[ + (psDevice->ui32ChipPN & MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M) >> + MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S]; + + // + // SRAM size from Part Number. + // + psDevice->ui32SRAMSize = + g_am_hal_mcuctrl_sram_size[ + (psDevice->ui32ChipPN & MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M) >> + MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S]; + + // + // Now, let's look at the JEDEC info. + // The full partnumber is 12 bits total, but is scattered across 2 registers. + // Bits [11:8] are 0xE. + // Bits [7:4] are 0xE for Apollo, 0xD for Apollo2, 0xC for Apollo3. + // Bits [3:0] are defined differently for Apollo and Apollo2/Apollo3. + // For Apollo, the low nibble is 0x0. + // For Apollo2/Apollo3, the low nibble indicates flash and SRAM size. + // + psDevice->ui32JedecPN = JEDEC->PID0_b.PNL8 << 0; + psDevice->ui32JedecPN |= JEDEC->PID1_b.PNH4 << 8; + + // + // JEPID is the JEP-106 Manufacturer ID Code, which is assigned to Ambiq as + // 0x1B, with parity bit is 0x9B. It is 8 bits located across 2 registers. + // + psDevice->ui32JedecJEPID = JEDEC->PID1_b.JEPIDL << 0; + psDevice->ui32JedecJEPID |= JEDEC->PID2_b.JEPIDH << 4; + + // + // CHIPREV is 8 bits located across 2 registers. + // + psDevice->ui32JedecCHIPREV = JEDEC->PID2_b.CHIPREVH4 << 4; + psDevice->ui32JedecCHIPREV |= JEDEC->PID3_b.CHIPREVL4 << 0; + + // + // Let's get the Coresight ID (32-bits across 4 registers) + // For Apollo and Apollo2, it's expected to be 0xB105100D. + // + psDevice->ui32JedecCID = JEDEC->CID3_b.CID << 24; + psDevice->ui32JedecCID |= JEDEC->CID2_b.CID << 16; + psDevice->ui32JedecCID |= JEDEC->CID1_b.CID << 8; + psDevice->ui32JedecCID |= JEDEC->CID0_b.CID << 0; +} // device_info_get() + +//***************************************************************************** +// +// mcuctrl_fault_status() +// Gets the fault status and capture registers. +// +//***************************************************************************** +static void +mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault) +{ + uint32_t ui32FaultStat; + + // + // Read the Fault Status Register. + // + ui32FaultStat = MCUCTRL->FAULTSTATUS; + psFault->bICODE = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_ICODEFAULT_Msk); + psFault->bDCODE = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_DCODEFAULT_Msk); + psFault->bSYS = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_SYSFAULT_Msk); + + // + // Read the DCODE fault capture address register. + // + psFault->ui32DCODE = MCUCTRL->DCODEFAULTADDR; + + // + // Read the ICODE fault capture address register. + // + psFault->ui32ICODE |= MCUCTRL->ICODEFAULTADDR; + + // + // Read the ICODE fault capture address register. + // + psFault->ui32SYS |= MCUCTRL->SYSFAULTADDR; +} // mcuctrl_fault_status() + +// **************************************************************************** +// +// am_hal_mcuctrl_control() +// Apply various specific commands/controls on the MCUCTRL module. +// +// **************************************************************************** +uint32_t +am_hal_mcuctrl_control(am_hal_mcuctrl_control_e eControl, void *pArgs) +{ + uint32_t ui32Tbl; + + switch ( eControl ) + { + case AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE: + // + // Enable the Fault Capture registers. + // + MCUCTRL->FAULTCAPTUREEN_b.FAULTCAPTUREEN = 1; + break; + + case AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_DISABLE: + // + // Disable the Fault Capture registers. + // + MCUCTRL->FAULTCAPTUREEN_b.FAULTCAPTUREEN = 0; + break; + + case AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_ENABLE: + // + // Configure the bits in XTALCTRL that enable external 32KHz clock. + // + MCUCTRL->XTALCTRL &= + ~(MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk | + MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk | + MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk | + MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk | + MCUCTRL_XTALCTRL_XTALSWE_Msk); + + MCUCTRL->XTALCTRL |= + _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCMPRXTAL, MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRDNCOMP) | + _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCOREXTAL, MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRDNCORE) | + _VAL2FLD(MCUCTRL_XTALCTRL_BYPCMPRXTAL, MCUCTRL_XTALCTRL_BYPCMPRXTAL_BYPCOMP) | + _VAL2FLD(MCUCTRL_XTALCTRL_FDBKDSBLXTAL, MCUCTRL_XTALCTRL_FDBKDSBLXTAL_DIS) | + _VAL2FLD(MCUCTRL_XTALCTRL_XTALSWE, MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN); + break; + + case AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_DISABLE: + // + // Configure the bits in XTALCTRL that disable external 32KHz + // clock, thus re-configuring for the crystal. + // + MCUCTRL->XTALCTRL &= + ~(MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk | + MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk | + MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk | + MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk | + MCUCTRL_XTALCTRL_XTALSWE_Msk); + + MCUCTRL->XTALCTRL |= + _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCMPRXTAL, MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRUPCOMP) | + _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCOREXTAL, MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRUPCORE) | + _VAL2FLD(MCUCTRL_XTALCTRL_BYPCMPRXTAL, MCUCTRL_XTALCTRL_BYPCMPRXTAL_USECOMP) | + _VAL2FLD(MCUCTRL_XTALCTRL_FDBKDSBLXTAL, MCUCTRL_XTALCTRL_FDBKDSBLXTAL_EN) | + _VAL2FLD(MCUCTRL_XTALCTRL_XTALSWE, MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS); + break; + + case AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH: + { + uint32_t ui32SramPrefetch = *(uint32_t*)pArgs; + uint32_t ui32SetMsk, ui32ClrMsk, ui32SRAMreg; + + // + // Validate the input flags. + // + if ( ui32SramPrefetch & + ~(AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTR | + AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTRCACHE | + AM_HAL_MCUCTRL_SRAM_PREFETCH_DATA | + AM_HAL_MCUCTRL_SRAM_PREFETCH_DATACACHE | + AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTR | + AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTRCACHE | + AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATA | + AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATACACHE) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + + // + // Given the rule that NOxxx overrides xxx, and keeping in mind + // that the cache settings cannot be set unless the regular + // prefetch is also being set or is already set, the following + // truth table results. + + // Note - this same TT also applies to data settings. + // nc=no change. + // I IC NI NIC: I IC + // 0x0: 0 0 0 0 : nc nc + // 0x1: 0 0 0 1 : nc 0 + // 0x2: 0 0 1 0 : 0 0 + // 0x3: 0 0 1 1 : 0 0 + // 0x4: 0 1 0 0 : INVALID + // 0x5: 0 1 0 1 : nc nc + // 0x6: 0 1 1 0 : INVALID + // 0x7: 0 1 1 1 : 0 0 + // 0x8: 1 0 0 0 : 1 0 + // 0x9: 1 0 0 1 : 1 0 + // 0xA: 1 0 1 0 : 0 0 + // 0xB: 1 0 1 1 : 0 0 + // 0xC: 1 1 0 0 : 1 1 + // 0xD: 1 1 0 1 : 1 0 + // 0xE: 1 1 1 0 : INVALID + // 0xF: 1 1 1 1 : 0 0 + // + + ui32Tbl = 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTR) ? (1 << 3) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTRCACHE) ? (1 << 2) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTR) ? (1 << 1) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTRCACHE) ? (1 << 0) : 0; + + // + // Now augment the table entries with current register settings. + // + ui32SRAMreg = MCUCTRL->SRAMMODE; + + ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_IPREFETCH_Msk ? (1 << 3) : 0; + ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk ? (1 << 2) : 0; + + ui32SetMsk = ui32ClrMsk = 0; + switch ( ui32Tbl ) + { + case 0x0: + case 0x5: + break; + case 0x1: + ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk; + break; + case 0x2: + case 0x3: + case 0x7: + case 0xA: + case 0xB: + case 0xF: + ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk | MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk; + break; + case 0x4: + case 0x6: + case 0xE: + return AM_HAL_STATUS_INVALID_OPERATION; + case 0x8: + case 0x9: + case 0xD: + ui32SetMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk; + ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk; + break; + case 0xC: + ui32SetMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk | MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk; + break; + default: + return AM_HAL_STATUS_INVALID_ARG; + } // switch() + + // + // Now, repeat with data settings. + // + ui32Tbl = 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_DATA) ? (1 << 3) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_DATACACHE) ? (1 << 2) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATA) ? (1 << 1) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATACACHE) ? (1 << 0) : 0; + + // + // Now augment the table entries with current register settings. + // + ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_DPREFETCH_Msk ? (1 << 3) : 0; + ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk ? (1 << 2) : 0; + + switch ( ui32Tbl ) + { + case 0x0: + case 0x5: + break; + case 0x1: + ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk; + break; + case 0x2: + case 0x3: + case 0x7: + case 0xA: + case 0xB: + case 0xF: + ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk | MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk; + break; + case 0x4: + case 0x6: + case 0xE: + return AM_HAL_STATUS_INVALID_OPERATION; + case 0x8: + case 0x9: + case 0xD: + ui32SetMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk; + ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk; + break; + case 0xC: + ui32SetMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk | MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk; + break; + default: + return AM_HAL_STATUS_INVALID_ARG; + } // switch() + + + // + // Arrange the register update such that clrmsk will have precedence + // over setmsk. + // + AM_CRITICAL_BEGIN + ui32SRAMreg = MCUCTRL->SRAMMODE; + ui32SRAMreg |= ui32SetMsk; + ui32SRAMreg &= ~ui32ClrMsk; + MCUCTRL->SRAMMODE = ui32SRAMreg; + AM_CRITICAL_END + } // case AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_mcuctrl_control() + +// **************************************************************************** +// +// am_hal_mcuctrl_status_get() +//! This function returns current status of the MCUCTRL as obtained from +//! various registers of the MCUCTRL block. +// +// **************************************************************************** +uint32_t +am_hal_mcuctrl_status_get(am_hal_mcuctrl_status_t *psStatus) +{ + uint32_t ui32Status; + + if ( psStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + ui32Status = MCUCTRL->FEATUREENABLE; + psStatus->bBurstAck = + _FLD2VAL(MCUCTRL_FEATUREENABLE_BURSTACK, ui32Status); + psStatus->bBLEAck = + _FLD2VAL(MCUCTRL_FEATUREENABLE_BLEACK, ui32Status); + + psStatus->bDebuggerLockout = + _FLD2VAL(MCUCTRL_DEBUGGER_LOCKOUT, MCUCTRL->DEBUGGER); + + psStatus->bADCcalibrated = + _FLD2VAL(MCUCTRL_ADCCAL_ADCCALIBRATED, MCUCTRL->ADCCAL); + + psStatus->bBattLoadEnabled = + _FLD2VAL(MCUCTRL_ADCBATTLOAD_BATTLOAD, MCUCTRL->ADCBATTLOAD); + + ui32Status = MCUCTRL->BOOTLOADER; + psStatus->bSecBootOnColdRst = + _FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOT, ui32Status); + psStatus->bSecBootOnWarmRst = + _FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOTONRST, ui32Status); + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_mcuctrl_status_get() + +// **************************************************************************** +// +// am_hal_mcuctrl_info_get() +// Get information of the given MCUCTRL item. +// +// **************************************************************************** +uint32_t +am_hal_mcuctrl_info_get(am_hal_mcuctrl_infoget_e eInfoGet, void *pInfo) +{ + am_hal_mcuctrl_feature_t *psFeature; + uint32_t ui32Feature; + + if ( pInfo == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + switch ( eInfoGet ) + { + case AM_HAL_MCUCTRL_INFO_FEATURES_AVAIL: + psFeature = (am_hal_mcuctrl_feature_t*)pInfo; + ui32Feature = MCUCTRL->FEATUREENABLE; + psFeature->bBurstAvail = + _FLD2VAL(MCUCTRL_FEATUREENABLE_BURSTAVAIL, ui32Feature); + psFeature->bBLEavail = + _FLD2VAL(MCUCTRL_FEATUREENABLE_BLEAVAIL, ui32Feature); + + ui32Feature = MCUCTRL->BOOTLOADER; + psFeature->ui8SecBootFeature = + _FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOTFEATURE, ui32Feature); + + ui32Feature = MCUCTRL->SKU; + psFeature->bBLEFeature = + _FLD2VAL(MCUCTRL_SKU_ALLOWBLE, ui32Feature); + psFeature->bBurstFeature = + _FLD2VAL(MCUCTRL_SKU_ALLOWBURST, ui32Feature); + break; + + case AM_HAL_MCUCTRL_INFO_DEVICEID: + device_info_get((am_hal_mcuctrl_device_t *)pInfo); + break; + + case AM_HAL_MCUCTRL_INFO_FAULT_STATUS: + mcuctrl_fault_status((am_hal_mcuctrl_fault_t*)pInfo); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_mcuctrl_info_get() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.h new file mode 100644 index 0000000..0c04d16 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.h @@ -0,0 +1,368 @@ +//***************************************************************************** +// +// am_hal_mcuctrl.h +//! @file +//! +//! @brief Functions for accessing and configuring the MCUCTRL. +//! +//! @addtogroup mcuctrl3 MCU Control (MCUCTRL) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_MCUCTRL_H +#define AM_HAL_MCUCTRL_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Designate this peripheral. +// +#define AM_APOLLO3_MCUCTRL 1 + +//***************************************************************************** +// +// Chip Revision IDentification. +// +//***************************************************************************** +#define APOLLO3_B0 \ + ((MCUCTRL->CHIPREV & \ + (MCUCTRL_CHIPREV_REVMAJ_Msk | MCUCTRL_CHIPREV_REVMIN_Msk)) == \ + (_VAL2FLD(MCUCTRL_CHIPREV_REVMAJ, MCUCTRL_CHIPREV_REVMAJ_B) | \ + _VAL2FLD(MCUCTRL_CHIPREV_REVMIN, MCUCTRL_CHIPREV_REVMIN_REV0))) + +#define APOLLO3_A1 \ + ((MCUCTRL->CHIPREV & \ + (MCUCTRL_CHIPREV_REVMAJ_Msk | MCUCTRL_CHIPREV_REVMIN_Msk)) == \ + (_VAL2FLD(MCUCTRL_CHIPREV_REVMAJ, MCUCTRL_CHIPREV_REVMAJ_A) | \ + _VAL2FLD(MCUCTRL_CHIPREV_REVMIN, MCUCTRL_CHIPREV_REVMIN_REV1))) + +#define APOLLO3_A0 \ + ((MCUCTRL->CHIPREV & \ + (MCUCTRL_CHIPREV_REVMAJ_Msk | MCUCTRL_CHIPREV_REVMIN_Msk)) == \ + (_VAL2FLD(MCUCTRL_CHIPREV_REVMAJ, MCUCTRL_CHIPREV_REVMAJ_A) | \ + _VAL2FLD(MCUCTRL_CHIPREV_REVMIN, MCUCTRL_CHIPREV_REVMIN_REV0))) + +// +// Determine if >= a given revision level. +// +#define APOLLO3_GE_B0 \ + ((MCUCTRL->CHIPREV & \ + (MCUCTRL_CHIPREV_REVMAJ_Msk | MCUCTRL_CHIPREV_REVMIN_Msk)) >= \ + (_VAL2FLD(MCUCTRL_CHIPREV_REVMAJ, MCUCTRL_CHIPREV_REVMAJ_B) | \ + _VAL2FLD(MCUCTRL_CHIPREV_REVMIN, MCUCTRL_CHIPREV_REVMIN_REV0))) + +#define APOLLO3_GE_A1 \ + ((MCUCTRL->CHIPREV & \ + (MCUCTRL_CHIPREV_REVMAJ_Msk | MCUCTRL_CHIPREV_REVMIN_Msk)) >= \ + (_VAL2FLD(MCUCTRL_CHIPREV_REVMAJ, MCUCTRL_CHIPREV_REVMAJ_A) | \ + _VAL2FLD(MCUCTRL_CHIPREV_REVMIN, MCUCTRL_CHIPREV_REVMIN_REV1))) + + +//***************************************************************************** +// +// MCUCTRL specific definitions. +// +//***************************************************************************** +#define AM_HAL_MCUCTRL_CHIPPN_FLASH_SIZE_N ((MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M >> MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S) + 1) +#define AM_HAL_MCUCTRL_CHIPPN_SRAM_SIZE_N ((MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M >> MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S) + 1) + +//***************************************************************************** +// +// MCUCTRL enumerations +// +//***************************************************************************** +//************************************** +//! MCUCTRL control operations +//************************************** +typedef enum +{ + AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE, + AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_DISABLE, + AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_ENABLE, + AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_DISABLE, + AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH +} am_hal_mcuctrl_control_e; + +//************************************** +//! MCUCTRL info get +//************************************** +typedef enum +{ + AM_HAL_MCUCTRL_INFO_FEATURES_AVAIL, + AM_HAL_MCUCTRL_INFO_DEVICEID, + AM_HAL_MCUCTRL_INFO_FAULT_STATUS +} am_hal_mcuctrl_infoget_e; + +//************************************** +//! MCUCTRL SRAM prefetch settings +//! +//! Prefetch settings are made via a call to: +//! am_hal_mcuctrl_control(AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH, +//! &ui32PrefetchSetting); +//! +//! The settings may be logically ORed together to obtain the desired settings. +//! +//! Notes: +//! - NOPREFETCH settings override PREFETCH settings if both are provided. +//! For example, calling with both PREFETCH_INSTR and NOPREFETCH_INSTR +//! will result in instruction prefetch being disabled. +//! - When executing from SRAM, it is recommended that the PREFETCH_INSTR and +//! PREFETCH_INSTRCACHE bits be set. +//! - It is generally okay to have PREFETCH_INSTR & PREFETCH_INSTRCACHE enabled +//! even if no SRAM execution is expected. +//! - It is generally not recommended that data prefetch be enabled unless the +//! work flow has a large number of sequential accesses. +//! - Setting PREFETCH_INSTRCACHE requires PREFETCH_INSTR. This is enforced by +//! the function and an error is returned if both are not being set or if +//! PREFETCH_INSTR is not already set in the register. +//! - Setting PREFETCH_DATACACHE requires PREFETCH_DATA. This is enforced by +//! the function. An error is returned if both are not being set or if +//! PREFETCH_DATA is not already set in the register. +//************************************** +#define SRAM_NOPREFETCH_Pos 16 +#define AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTR (MCUCTRL_SRAMMODE_IPREFETCH_Msk << 0) +#define AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTRCACHE (MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk << 0) +#define AM_HAL_MCUCTRL_SRAM_PREFETCH_DATA (MCUCTRL_SRAMMODE_DPREFETCH_Msk << 0) +#define AM_HAL_MCUCTRL_SRAM_PREFETCH_DATACACHE (MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk << 0) +#define AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTR (MCUCTRL_SRAMMODE_IPREFETCH_Msk << SRAM_NOPREFETCH_Pos) +#define AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTRCACHE (MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk << SRAM_NOPREFETCH_Pos) +#define AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATA (MCUCTRL_SRAMMODE_DPREFETCH_Msk << SRAM_NOPREFETCH_Pos) +#define AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATACACHE (MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk << SRAM_NOPREFETCH_Pos) + +//***************************************************************************** +// +// MCUCTRL data structures +// +//***************************************************************************** +//************************************** +//! MCUCTRL device structure +//************************************** +typedef struct +{ + // + //! Device part number. (BCD format) + // + uint32_t ui32ChipPN; + + // + //! Unique Chip ID 0. + // + uint32_t ui32ChipID0; + + // + //! Unique Chip ID 1. + // + uint32_t ui32ChipID1; + + // + //! Chip Revision. + // + uint32_t ui32ChipRev; + + // + //! Vendor ID. + // + uint32_t ui32VendorID; + + // + //! SKU (Apollo3). + // + uint32_t ui32SKU; + + // + //! Qualified chip. + // + uint32_t ui32Qualified; + + // + //! Flash Size. + // + uint32_t ui32FlashSize; + + // + //! SRAM Size. + // + uint32_t ui32SRAMSize; + + // + // JEDEC chip info + // + uint32_t ui32JedecPN; + uint32_t ui32JedecJEPID; + uint32_t ui32JedecCHIPREV; + uint32_t ui32JedecCID; +} +am_hal_mcuctrl_device_t; + +//************************************** +//! MCUCTRL fault structure +//************************************** +typedef struct +{ + // + //! ICODE bus fault occurred. + // + bool bICODE; + + // + //! ICODE bus fault address. + // + uint32_t ui32ICODE; + + // + //! DCODE bus fault occurred. + // + bool bDCODE; + + // + //! DCODE bus fault address. + // + uint32_t ui32DCODE; + + // + //! SYS bus fault occurred. + // + bool bSYS; + + // + //! SYS bus fault address. + // + uint32_t ui32SYS; +} +am_hal_mcuctrl_fault_t; + +//************************************** +//! MCUCTRL status structure +//************************************** +typedef struct +{ + bool bBurstAck; // FEATUREENABLE + bool bBLEAck; // " + bool bDebuggerLockout; // DEBUGGER + bool bADCcalibrated; // ADCCAL + bool bBattLoadEnabled; // ADCBATTLOAD + uint8_t bSecBootOnWarmRst; // BOOTLOADER + uint8_t bSecBootOnColdRst; // " +} am_hal_mcuctrl_status_t; + +//************************************** +//! MCUCTRL features available structure +//************************************** +typedef struct +{ + bool bBurstAvail; // FEATUREENABLE + bool bBLEavail; // " + bool bBLEFeature; // SKU + bool bBurstFeature; // " + uint8_t ui8SecBootFeature; // BOOTLOADER +} am_hal_mcuctrl_feature_t; + + +// **************************************************************************** +// +//! @brief Apply various specific commands/controls on the MCUCTRL module. +//! +//! This function is used to apply various controls to MCUCTRL. +//! +//! @param eControl - One of the following: +//! AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE +//! AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_DISABLE +//! AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_ENABLE +//! AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_DISABLE +//! AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_mcuctrl_control(am_hal_mcuctrl_control_e eControl, + void *pArgs); + +// **************************************************************************** +// +//! @brief MCUCTRL status function +//! +//! This function returns current status of the MCUCTRL as obtained from +//! various registers of the MCUCTRL block. +//! +//! @param psStatus - ptr to a status structure to receive the current statuses. +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_mcuctrl_status_get(am_hal_mcuctrl_status_t *psStatus); + +// **************************************************************************** +// +//! @brief Get information of the given MCUCTRL item. +//! +//! This function returns a data structure of information regarding the given +//! MCUCTRL parameter. +//! +//! @param eInfoGet - One of the following: Return structure type: +//! AM_HAL_MCUCTRL_INFO_DEVICEID, psDevice +//! AM_HAL_MCUCTRL_INFO_FAULT_STATUS psFault +//! +//! @param pInfo - A pointer to a structure to receive the return data, +//! the type of which is dependent on the eInfo parameter. +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_mcuctrl_info_get(am_hal_mcuctrl_infoget_e eInfoGet, + void *pInfo); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_MCUCTRL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.c new file mode 100644 index 0000000..d107daa --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.c @@ -0,0 +1,3438 @@ +//***************************************************************************** +// +// am_hal_mspi.c +//! @file +//! +//! @brief Functions for interfacing with the MSPI. +//! +//! @addtogroup mspi3 Multi-bit SPI (MSPI) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Private Types. +// +//***************************************************************************** + +#define AM_HAL_MAGIC_MSPI 0xBEBEBE +#define AM_HAL_MSPI_CHK_HANDLE(h) ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_MSPI)) +#define AM_HAL_MSPI_HW_IDX_MAX (AM_REG_MSPI_CQCURIDX_CQCURIDX_M >> AM_REG_MSPI_CQCURIDX_CQCURIDX_S) // 8 bit value +#define AM_HAL_MSPI_MAX_CQ_ENTRIES (256) + + + +// For MSPI - Need to Set the flag for unpausing +#define AM_HAL_MSPI_SC_PAUSE_CQ AM_HAL_MSPI_SC_PAUSE(AM_HAL_MSPI_PAUSE_FLAG_CQ) +#define AM_HAL_MSPI_SC_PAUSE_SEQLOOP AM_HAL_MSPI_SC_PAUSE(AM_HAL_MSPI_PAUSE_FLAG_SEQLOOP) +#define AM_HAL_MSPI_SC_UNPAUSE_CQ AM_HAL_MSPI_SC_UNPAUSE(AM_HAL_MSPI_PAUSE_FLAG_CQ) +#define AM_HAL_MSPI_SC_UNPAUSE_SEQLOOP AM_HAL_MSPI_SC_UNPAUSE(AM_HAL_MSPI_PAUSE_FLAG_SEQLOOP) +#define AM_HAL_MSPI_SC_PAUSE_BLOCK AM_HAL_MSPI_SC_PAUSE(AM_HAL_MSPI_PAUSE_FLAG_BLOCK) +#define AM_HAL_MSPI_SC_UNPAUSE_BLOCK AM_HAL_MSPI_SC_UNPAUSE(AM_HAL_MSPI_PAUSE_FLAG_BLOCK) + + +// Max time to wait when attempting to pause the command queue +#define AM_HAL_MSPI_MAX_PAUSE_DELAY (100*1000) // 100ms + +// +// MSPI interface mode and chip enable selection. +// This is an internal extension to am_hal_mspi_device_e +// +typedef enum +{ + AM_HAL_MSPI_FLASH_DUAL_CE0_1_1_2 = AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL + 1, + AM_HAL_MSPI_FLASH_DUAL_CE1_1_1_2, + AM_HAL_MSPI_FLASH_DUAL_CE0_1_2_2, + AM_HAL_MSPI_FLASH_DUAL_CE1_1_2_2, + AM_HAL_MSPI_FLASH_QUAD_CE0_1_1_4, + AM_HAL_MSPI_FLASH_QUAD_CE1_1_1_4, + AM_HAL_MSPI_FLASH_QUAD_CE0_1_4_4, + AM_HAL_MSPI_FLASH_QUAD_CE1_1_4_4, + AM_HAL_MSPI_FLASH_SERIAL_CE0_3WIRE, + AM_HAL_MSPI_FLASH_SERIAL_CE1_3WIRE, +} mspi_device_e; + +// +// Command Queue entry structure for DMA transfer. +// +typedef struct +{ +#if MSPI_USE_CQ + uint32_t ui32PAUSENAddr; + uint32_t ui32PAUSEENVal; + uint32_t ui32PAUSEN2Addr; + uint32_t ui32PAUSEEN2Val; +#endif +#if !MSPI_USE_CQ + // Need to disable the DMA before reconfiguring it + uint32_t ui32DMACFG2Addr; + uint32_t ui32DMACFG2Val; +#endif + uint32_t ui32DMATARGADDRAddr; + uint32_t ui32DMATARGADDRVal; + uint32_t ui32DMADEVADDRAddr; + uint32_t ui32DMADEVADDRVal; + uint32_t ui32DMATOTCOUNTAddr; + uint32_t ui32DMATOTCOUNTVal; + uint32_t ui32DMACFG1Addr; + uint32_t ui32DMACFG1Val; +#if MSPI_USE_CQ + // Need to disable the DMA to prepare for next reconfig + // Need to have this following the DMAEN for CMDQ + uint32_t ui32DMACFG2Addr; + uint32_t ui32DMACFG2Val; + uint32_t ui32SETCLRAddr; + uint32_t ui32SETCLRVal; +#endif +} am_hal_mspi_cq_dma_entry_t; + +// +// structure for Hi Prio DMA transfer. +// +typedef struct +{ + uint32_t ui32DMATARGADDRVal; + uint32_t ui32DMADEVADDRVal; + uint32_t ui32DMATOTCOUNTVal; + uint32_t ui32DMACFG1Val; + am_hal_mspi_callback_t pfnCallback; + void *pCallbackCtxt; +} am_hal_mspi_dma_entry_t; + +// +// Command Queue entry structure for Sequence Repeat +// +typedef struct +{ + uint32_t ui32PAUSENAddr; + uint32_t ui32PAUSEENVal; + uint32_t ui32PAUSEN2Addr; + uint32_t ui32PAUSEEN2Val; + uint32_t ui32SETCLRAddr; + uint32_t ui32SETCLRVal; +} am_hal_mspi_cq_loop_entry_t; + +// +// Command Queue entry structure for PIO transfer. +// +typedef struct +{ + uint32_t ui32ADDRAddr; + uint32_t ui32ADDRVal; + uint32_t ui32INSTRAddr; + uint32_t ui32INSTRVal; + uint32_t ui32CTRLAddr; + uint32_t ui32CTRLVal; +} am_hal_mspi_cq_pio_entry_t; + +typedef struct +{ + bool bValid; + uint32_t regCFG; + uint32_t regMSPICFG; + uint32_t regPADCFG; + uint32_t regPADOUTEN; + uint32_t regFLASH; + uint32_t regSCRAMBLING; + uint32_t regCQCFG; + uint32_t regCQADDR; + uint32_t regCQPAUSE; + uint32_t regCQFLAGS; + uint32_t regCQCURIDX; + uint32_t regCQENDIDX; + uint32_t regINTEN; + // TODO: May be no need to preserve these values, as they are constants anyways? + uint32_t regDMABCOUNT; + uint32_t regDMATHRESH; +} am_hal_mspi_register_state_t; + +// +// Command Queue control structure. +// +typedef struct +{ + void *pCmdQHdl; +} am_hal_mspi_CQ_t; + +typedef enum +{ + AM_HAL_MSPI_SEQ_NONE, + AM_HAL_MSPI_SEQ_UNDER_CONSTRUCTION, + AM_HAL_MSPI_SEQ_RUNNING, +} am_hal_mspi_seq_e; + +// +// MSPI State structure. +// +typedef struct +{ + // + // Handle validation prefix. + // + am_hal_handle_prefix_t prefix; + + // + // Physical module number. + // + uint32_t ui32Module; + + // + // Selected flash device configuration. + // + am_hal_mspi_device_e eDeviceConfig; + + // + // Clock frequency + // + am_hal_mspi_clock_e eClockFreq; + + // + // Endianess of the FIFO interface. + // + bool bBigEndian; + + // + // Delay timeout value. + // + uint32_t waitTimeout; + // DMA Transfer Control Buffer size in words. + uint32_t ui32TCBSize; + + // DMA Transfer Control Buffer + uint32_t *pTCB; + + uint32_t ui32LastIdxProcessed; + uint32_t ui32NumCQEntries; + uint32_t ui32TxnInt; + + // + // Stores the CQ callbacks. + // + am_hal_mspi_callback_t pfnCallback[AM_HAL_MSPI_MAX_CQ_ENTRIES]; + + void *pCallbackCtxt[AM_HAL_MSPI_MAX_CQ_ENTRIES]; +#if MSPI_USE_CQ + // + // Command Queue. + // + am_hal_mspi_CQ_t CQ; + // To support sequence + am_hal_mspi_seq_e eSeq; + bool bAutonomous; + uint32_t ui32NumTransactions; + volatile bool bRestart; + uint32_t block; + // To support high priority transactions - out of band + // High Priority DMA transactions + volatile bool bHP; + uint32_t ui32NumHPEntries; + uint32_t ui32NumHPPendingEntries; + uint32_t ui32MaxHPTransactions; + uint32_t ui32NextHPIdx; + uint32_t ui32LastHPIdxProcessed; + am_hal_mspi_dma_entry_t *pHPTransactions; + // Max pending transactions based on NB Buffer size + uint32_t ui32MaxPending; + // Number of back to back transactions with no callbacks + uint32_t ui32NumUnSolicited; +#else + uint32_t ui32MaxTransactions; + uint32_t ui32NextIdx; + am_hal_mspi_cq_dma_entry_t *pTransactions; +#endif + + // + // MSPI Capabilities. + // + am_hal_mspi_capabilities_t capabilities; + + // Power Save-Restore register state + am_hal_mspi_register_state_t registerState; +} am_hal_mspi_state_t; + +//***************************************************************************** +// +// Global Variables. +// +//***************************************************************************** +am_hal_mspi_state_t g_MSPIState[AM_REG_MSPI_NUM_MODULES]; + + +#if !MSPI_USE_CQ +void (*g_pfnDMACallback[AM_REG_MSPI_NUM_MODULES])(void); +void *g_pCallbackCtxt[AM_REG_MSPI_NUM_MODULES]; +#endif //!MSPI_USE_CQ + +//***************************************************************************** +// +// Internal Functions. +// +//***************************************************************************** +static uint32_t +get_pause_val(am_hal_mspi_state_t *pMSPIState, uint32_t pause) +{ + uint32_t retval; + switch (pMSPIState->block) + { + case 1: + // Pause the CQ till the whole block is built + retval = pause | AM_HAL_MSPI_CQP_PAUSE_DEFAULT | AM_HAL_MSPI_PAUSE_FLAG_BLOCK; + pMSPIState->block = 2; + break; + case 2: + // No pausing allowed + retval = AM_HAL_MSPI_PAUSE_DEFAULT; + break; + default: // case 0 + retval = pause | AM_HAL_MSPI_CQP_PAUSE_DEFAULT; + } + return retval; +} + +uint32_t +build_dma_cmdlist(am_hal_mspi_state_t *pMSPIState, + am_hal_mspi_trans_e eMode, + void *pCQEntry, + void *pTransaction) +{ + uint32_t ui32Module = pMSPIState->ui32Module; + + switch(eMode) + { + case AM_HAL_MSPI_TRANS_PIO: + { + am_hal_mspi_cq_pio_entry_t *pPIOEntry = (am_hal_mspi_cq_pio_entry_t*)pCQEntry; + am_hal_mspi_pio_transfer_t *pPIOTrans = (am_hal_mspi_pio_transfer_t*)pTransaction; + + // + // Perform some sanity checks on the transaction. + // + if (pPIOTrans->ui32NumBytes > 65535) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Command to set the CTRL register. + // + pPIOEntry->ui32ADDRAddr = (uint32_t)&MSPIn(ui32Module)->ADDR; + pPIOEntry->ui32ADDRVal = _VAL2FLD(MSPI_ADDR_ADDR, pPIOTrans->ui32DeviceAddr); + pPIOEntry->ui32INSTRAddr = (uint32_t)&MSPIn(ui32Module)->INSTR; + pPIOEntry->ui32INSTRVal = _VAL2FLD(MSPI_INSTR_INSTR, pPIOTrans->ui16DeviceInstr); + pPIOEntry->ui32CTRLAddr = (uint32_t)&MSPIn(ui32Module)->CTRL; + pPIOEntry->ui32CTRLVal = + _VAL2FLD(MSPI_CTRL_XFERBYTES, pPIOTrans->ui32NumBytes) | // Set the number of bytes to transfer. + _VAL2FLD(MSPI_CTRL_PIOSCRAMBLE, pPIOTrans->bScrambling) | // Set the scrambling if selected. + _VAL2FLD(MSPI_CTRL_TXRX, pPIOTrans->eDirection) | // Set transmit or receive operation. + _VAL2FLD(MSPI_CTRL_SENDI, pPIOTrans->bSendInstr) | // Enable sending the instruction. + _VAL2FLD(MSPI_CTRL_SENDA, pPIOTrans->bSendAddr) | // Enable sending the address. + _VAL2FLD(MSPI_CTRL_ENTURN, pPIOTrans->bTurnaround) | // Set the turn-around if needed. + _VAL2FLD(MSPI_CTRL_BIGENDIAN, pMSPIState->bBigEndian) | // Set the FIFO endian format. + _VAL2FLD(MSPI_CTRL_QUADCMD, pPIOTrans->bQuadCmd) | // Set the Quad Command if indicated. + _VAL2FLD(MSPI_CTRL_START, 1); // Start the transfer. + + } + break; + case AM_HAL_MSPI_TRANS_DMA: + { + am_hal_mspi_cq_dma_entry_t *pDMAEntry = (am_hal_mspi_cq_dma_entry_t *)pCQEntry; + am_hal_mspi_dma_transfer_t *pDMATrans = (am_hal_mspi_dma_transfer_t *)pTransaction; + + // + // Perform some sanity checks on the transaction. + // + if (pDMATrans->ui32TransferCount > 65535) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + if (pMSPIState->block && (pDMATrans->ui32PauseCondition != 0)) + { + // Paused operations not allowed in block mode + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Command to set the DMACFG to disable DMA. + // Need to make sure we disable DMA before we can reprogram + // + pDMAEntry->ui32DMACFG2Addr = (uint32_t)&MSPIn(ui32Module)->DMACFG; + pDMAEntry->ui32DMACFG2Val = _VAL2FLD(MSPI_DMACFG_DMAEN, 0); + + // + // Command to set the DMATARGADDR + // + pDMAEntry->ui32DMATARGADDRAddr = (uint32_t)&MSPIn(ui32Module)->DMATARGADDR; + pDMAEntry->ui32DMATARGADDRVal = pDMATrans->ui32SRAMAddress; + + // + // Command to set the DMADEVADDR + // + pDMAEntry->ui32DMADEVADDRAddr = (uint32_t)&MSPIn(ui32Module)->DMADEVADDR; + pDMAEntry->ui32DMADEVADDRVal = pDMATrans->ui32DeviceAddress; + + // + // Command to set the DMATOTALCOUNT + // + pDMAEntry->ui32DMATOTCOUNTAddr = (uint32_t)&MSPIn(ui32Module)->DMATOTCOUNT; + pDMAEntry->ui32DMATOTCOUNTVal = pDMATrans->ui32TransferCount; + + // + // Command to set the DMACFG to start DMA. + // + pDMAEntry->ui32DMACFG1Addr = (uint32_t)&MSPIn(ui32Module)->DMACFG; + pDMAEntry->ui32DMACFG1Val = + _VAL2FLD(MSPI_DMACFG_DMAPWROFF, 0) | // DMA Auto Power-off not supported! + _VAL2FLD(MSPI_DMACFG_DMAPRI, pDMATrans->ui8Priority) | + _VAL2FLD(MSPI_DMACFG_DMADIR, pDMATrans->eDirection) | + _VAL2FLD(MSPI_DMACFG_DMAEN, 3); +#if MSPI_USE_CQ + pDMAEntry->ui32PAUSENAddr = pDMAEntry->ui32PAUSEN2Addr = (uint32_t)&MSPIn(ui32Module)->CQPAUSE; + pDMAEntry->ui32PAUSEENVal = get_pause_val(pMSPIState, pDMATrans->ui32PauseCondition); + pDMAEntry->ui32PAUSEEN2Val = AM_HAL_MSPI_PAUSE_DEFAULT; + pDMAEntry->ui32SETCLRVal = pDMATrans->ui32StatusSetClr; + pDMAEntry->ui32SETCLRAddr = (uint32_t)&MSPIn(ui32Module)->CQSETCLEAR; +#endif + } + break; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Writes data to the MSPI FIFO. +//! +//! @param ui32Module - Selects the MSPI module to use (zero or one). +//! @param pui32Data - Pointer to an array of the data to be written. +//! @param ui32NumBytes - Number of BYTES to copy into the FIFO. +//! +//! This function copies data from the array \e pui32Data into the MSPI FIFO. +//! +//! @return HAL status of the operation. +// +//***************************************************************************** +static uint32_t +mspi_fifo_write(uint32_t ui32Module, uint32_t *pui32Data, + uint32_t ui32NumBytes, uint32_t ui32Timeout) +{ + uint32_t ui32Index; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_MSPI_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Loop over the words in the array until we have the correct number of + // bytes. + // + for ( ui32Index = 0; (4 * ui32Index) < ui32NumBytes; ui32Index++ ) + { + // + // Write the word to the FIFO. + // + MSPIn(ui32Module)->TXFIFO = pui32Data[ui32Index]; + + // + // Wait for the word to go out if there is no room in the FIFO. + // + ui32Status = am_hal_flash_delay_status_check(ui32Timeout, + (uint32_t)&MSPIn(ui32Module)->TXENTRIES, + MSPI_TXENTRIES_TXENTRIES_Msk, + _VAL2FLD(MSPI_TXENTRIES_TXENTRIES, AM_HAL_MSPI_MAX_FIFO_SIZE), + false); + } + + // + // Return the status. + // + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Reads data from the MSPI FIFO. +//! +//! @param ui32Module - Selects the IOM module to use (zero or one). +//! @param pui32Data - Pointer to an array where the FIFO data will be copied. +//! @param ui32NumBytes - Number of bytes to copy into array. +//! +//! This function copies data from the MSPI FIFO into the array \e pui32Data. +//! +//! @return HAL status of the operation. +// +//***************************************************************************** +static uint32_t +mspi_fifo_read(uint32_t ui32Module, uint32_t *pui32Data, + uint32_t ui32NumBytes, uint32_t ui32Timeout) +{ + am_hal_mspi_buffer(4) sTempBuffer; + uint32_t i, ui32NumWords, ui32Leftovers; + uint32_t ui32Status; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_MSPI_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Figure out how many whole words we're reading from the fifo, and how + // many bytes will be left over when we're done. + // + ui32NumWords = ui32NumBytes / 4; + ui32Leftovers = ui32NumBytes - (ui32NumWords * 4); + + // + // Copy out as many full words as we can. + // + for ( i = 0; i < ui32NumWords; i++ ) + { + // + // Wait for additinal entries in the MSPI RX FIFO. + // + ui32Status = am_hal_flash_delay_status_check(ui32Timeout, + (uint32_t)&MSPIn(ui32Module)->RXENTRIES, + MSPI_RXENTRIES_RXENTRIES_Msk, + _VAL2FLD(MSPI_RXENTRIES_RXENTRIES, 0), + false); + + // + // Check for timeout + // + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Copy data out of the FIFO, one word at a time. + // + pui32Data[i] = MSPIn(ui32Module)->RXFIFO; + } + + // + // If there were leftovers, we'll copy them carefully. Pull the last word + // from the fifo (there should only be one) into a temporary buffer. Also, + // create an 8-bit pointer to help us copy the remaining bytes one at a + // time. + // + // Note: If the data buffer we were given was truly a word pointer like the + // definition requests, we wouldn't need to do this. It's possible to call + // this function with a re-cast or packed pointer instead though. If that + // happens, we want to be careful not to overwrite any data that might be + // sitting just past the end of the destination array. + // + if ( ui32Leftovers ) + { + // + // Wait for additinal entries in the MSPI RX FIFO. + // + ui32Status = am_hal_flash_delay_status_check(ui32Timeout, + (uint32_t)&MSPIn(ui32Module)->RXENTRIES, + MSPI_RXENTRIES_RXENTRIES_Msk, + _VAL2FLD(MSPI_RXENTRIES_RXENTRIES, 0), + false); + + // + // Check for timeout + // + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Read the next word from the RX FIFO. + // + sTempBuffer.words[0] = MSPIn(ui32Module)->RXFIFO; + uint8_t *pui8Data; + pui8Data = (uint8_t *) (&pui32Data[i]); + + // + // If we had leftover bytes, copy them out one byte at a time. + // + for ( int j = 0; j < ui32Leftovers; j++ ) + { + pui8Data[j] = sTempBuffer.bytes[j]; + } + } + + return AM_HAL_STATUS_SUCCESS; +} + +#if !MSPI_USE_CQ +static void +run_txn_cmdlist(void *pCQEntry, uint32_t numEntries) +{ + uint32_t ix; + am_hal_cmdq_entry_t *pCmd = (am_hal_cmdq_entry_t *)pCQEntry; + + for ( ix = 0; ix < numEntries; ix++, pCmd++ ) + { + *((uint32_t *)pCmd->address) = pCmd->value; + } +} // run_txn_cmdlist() + +static uint32_t +mspi_dma_add_transaction(void *pHandle, + am_hal_mspi_dma_transfer_t *psTransaction, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + am_hal_mspi_cq_dma_entry_t *pCQEntry; + uint32_t index = pMSPIState->ui32NextIdx % pMSPIState->ui32MaxTransactions; + + // + // Check to see if there is enough room in the queue + // + if ( pMSPIState->ui32NumCQEntries == pMSPIState->ui32MaxTransactions ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pCQEntry = &pMSPIState->pTransactions[index]; + + + if (AM_HAL_STATUS_SUCCESS != build_dma_cmdlist(pMSPIState, AM_HAL_MSPI_TRANS_DMA, pCQEntry, (void *)psTransaction)) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Store the callback function pointer. + // + pMSPIState->pfnCallback[index] = pfnCallback; + pMSPIState->pCallbackCtxt[index] = pCallbackCtxt; + pMSPIState->ui32NextIdx++; + return AM_HAL_STATUS_SUCCESS; +} // am_hal_mspi_DmaAddTransaction() + +#else + + +//***************************************************************************** +// +//! @brief Initializes the MSPI Command Queue. +//! +//! @param handle - handle for the interface. +//! @param ui32Length - length of the SRAM Command Queue buffer in words. +//! @param pTCB - pointer to the SRAM to use for the Command Queue. +//! +//! This function initializes the global command queue structure. +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_cq_init(uint32_t ui32Module, uint32_t ui32Length, + uint32_t *pTCB) +{ + am_hal_cmdq_cfg_t cqCfg; + + cqCfg.pCmdQBuf = pTCB; + cqCfg.cmdQSize = ui32Length / 2; + cqCfg.priority = AM_HAL_CMDQ_PRIO_HI; + return am_hal_cmdq_init((am_hal_cmdq_if_e)(AM_HAL_CMDQ_IF_MSPI + ui32Module), + &cqCfg, &g_MSPIState[ui32Module].CQ.pCmdQHdl); +} + +//***************************************************************************** +// +//! @brief Terminates the MSPI Command Queue. +//! +//! @param ui32Module - MSPI instance. +//! +//! This function resets the global command queue structure. +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_cq_term(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module = pMSPIState->ui32Module; + + if (g_MSPIState[ui32Module].CQ.pCmdQHdl) + { + am_hal_cmdq_term(g_MSPIState[ui32Module].CQ.pCmdQHdl, true); + g_MSPIState[ui32Module].CQ.pCmdQHdl = NULL; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Adds a transaction the MSPI Command Queue. +//! +//! @param handle - handle for the interface. +//! @param pTransaction - transaction to add to the CQ +//! @param pfnCallback - pointer the callback function to be executed when +//! transaction is complete. +//! @param pCallbackCtxt- pointer to the state/context to pass to callback +//! function. +//! +//! This function copies data from the IOM FIFO into the array \e pui32Data. +//! This is how input data from SPI or I2C transactions may be retrieved. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_cq_add_transaction(void *pHandle, + void *pTransaction, + am_hal_mspi_trans_e eMode, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + am_hal_cmdq_entry_t *pCQBlock; + uint32_t index; + uint32_t size = 1; + am_hal_mspi_CQ_t *pCQ = &pMSPIState->CQ; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + + // + // Determine the transfer mode and set up accordingly. + // + switch(eMode) + { + case AM_HAL_MSPI_TRANS_PIO: + size = sizeof(am_hal_mspi_cq_pio_entry_t); + break; + case AM_HAL_MSPI_TRANS_DMA: + size = sizeof(am_hal_mspi_cq_dma_entry_t); + break; + } + + // + // Check to see if there is enough room in the CQ + // + if (pMSPIState->ui32NumCQEntries == AM_HAL_MSPI_MAX_CQ_ENTRIES) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + ui32Status = am_hal_cmdq_alloc_block(pCQ->pCmdQHdl, size / 8, &pCQBlock, &index); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + + ui32Status = build_dma_cmdlist(pMSPIState, eMode, pCQBlock, pTransaction); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + am_hal_cmdq_release_block(pCQ->pCmdQHdl); + return ui32Status; + } + + // + // Because we set AM_HAL_IOM_CQUPD_INT_FLAG, an interrupt will occur once + // we reach this point in the Command Queue. In the service routine, we'll + // look for the appropriate callback. + // + // If ENDIDX has been reached, the CQ will pause here. Otherwise will + // continue with the next CQ entry. + // + + // + // Store the callback function pointer. + // + pMSPIState->pfnCallback[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pfnCallback; + pMSPIState->pCallbackCtxt[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pCallbackCtxt; + + // + // Return the status. + // + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Enable the Command Queue operation. +//! +//! @param handle - handle for the interface. +//! +//! This function enables Command Queue operation. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_cq_enable(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + + // + // Enable the Command Queue operation + // + return am_hal_cmdq_enable(pMSPIState->CQ.pCmdQHdl); +} +//***************************************************************************** +// +//! @brief Disable the Command Queue operation. +//! +//! @param handle - handle for the interface. +//! +//! This function disables the Command Queue operation. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_cq_disable(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + + // + // Disable the Command Queue operation + // + return am_hal_cmdq_disable(pMSPIState->CQ.pCmdQHdl); +} + +static uint32_t +mspi_cq_pause(am_hal_mspi_state_t *pMSPIState) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32usMaxDelay = AM_HAL_MSPI_MAX_PAUSE_DELAY; + + MSPIn(pMSPIState->ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_PAUSE_CQ; + // It is possible that CQ is disabled once the last transaction is processed + while ( MSPIn(pMSPIState->ui32Module)->CQCFG_b.CQEN ) + { + // Need to make sure we're paused at a designated pause point + if ( MSPIn(pMSPIState->ui32Module)->CQSTAT_b.CQPAUSED && (MSPIn(pMSPIState->ui32Module)->CQPAUSE & AM_HAL_MSPI_PAUSE_FLAG_CQ)) + { + break; + } + if ( ui32usMaxDelay-- ) + { + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + return AM_HAL_STATUS_TIMEOUT; + } + } + if (status == AM_HAL_STATUS_SUCCESS) + { + // Now that CQ is guaranteed to not progress further - we need to still wait in case the current CQ entry + // resulted in a DMA state....need to make sure we finish the current DMA + status = am_hal_flash_delay_status_check(AM_HAL_MSPI_MAX_PAUSE_DELAY, + (uint32_t)&MSPIn(pMSPIState->ui32Module)->DMASTAT, + MSPI_DMASTAT_DMATIP_Msk, + _VAL2FLD(MSPI_DMASTAT_DMATIP, 0), + true); + + } + return status; +} + +static void +program_dma(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module = pMSPIState->ui32Module; + uint32_t index = (pMSPIState->ui32LastHPIdxProcessed + 1) % pMSPIState->ui32MaxHPTransactions; + am_hal_mspi_dma_entry_t *pDMAEntry = &pMSPIState->pHPTransactions[index]; + + // Need to make sure we disable DMA before we can reprogram + MSPIn(ui32Module)->DMACFG = _VAL2FLD(MSPI_DMACFG_DMAEN, 0); + // + // set the DMATARGADDR + // + MSPIn(ui32Module)->DMATARGADDR = pDMAEntry->ui32DMATARGADDRVal; + + // + // set the DMADEVADDR + // + MSPIn(ui32Module)->DMADEVADDR = pDMAEntry->ui32DMADEVADDRVal; + + // + // set the DMATOTALCOUNT + // + MSPIn(ui32Module)->DMATOTCOUNT = pDMAEntry->ui32DMATOTCOUNTVal; + + // + // set the DMACFG to start DMA. + // + MSPIn(ui32Module)->DMACFG = pDMAEntry->ui32DMACFG1Val; +} + + +static uint32_t +sched_hiprio(am_hal_mspi_state_t *pMSPIState, uint32_t numTrans) +{ + uint32_t ui32NumPend; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + ui32NumPend = pMSPIState->ui32NumHPEntries; + pMSPIState->ui32NumHPEntries += numTrans; + + // + // End the critical section. + // + AM_CRITICAL_END + + + if (0 == ui32NumPend) + { + // Force CQ to Pause + ui32Status = mspi_cq_pause(pMSPIState); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + pMSPIState->ui32TxnInt = 0; + // Clear DMACMP interrupt + MSPIn(pMSPIState->ui32Module)->INTCLR = AM_HAL_MSPI_INT_DMACMP | AM_HAL_MSPI_INT_CMDCMP; + // Enable DMACMP interrupt + MSPIn(pMSPIState->ui32Module)->INTEN |= AM_HAL_MSPI_INT_DMACMP | AM_HAL_MSPI_INT_CMDCMP; + pMSPIState->bHP = true; + // + // Program the DMA + // + program_dma(pMSPIState); + } + return ui32Status; +} + + +static uint32_t +mspi_add_hp_transaction(void *pHandle, + am_hal_mspi_dma_transfer_t *pDMATrans, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + am_hal_mspi_dma_entry_t *pDMAEntry; + + uint32_t index = pMSPIState->ui32NextHPIdx % pMSPIState->ui32MaxHPTransactions; + + // + // Check to see if there is enough room in the queue + // + if ( pMSPIState->ui32NumHPEntries == pMSPIState->ui32MaxHPTransactions ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pDMAEntry = &pMSPIState->pHPTransactions[index]; + pDMAEntry->ui32DMATARGADDRVal = pDMATrans->ui32SRAMAddress; + pDMAEntry->ui32DMADEVADDRVal = pDMATrans->ui32DeviceAddress; + pDMAEntry->ui32DMATOTCOUNTVal = pDMATrans->ui32TransferCount; + pDMAEntry->ui32DMACFG1Val = + _VAL2FLD(MSPI_DMACFG_DMAPWROFF, 0) | // DMA Auto Power-off not supported! + _VAL2FLD(MSPI_DMACFG_DMAPRI, pDMATrans->ui8Priority) | + _VAL2FLD(MSPI_DMACFG_DMADIR, pDMATrans->eDirection) | + _VAL2FLD(MSPI_DMACFG_DMAEN, 3); + pDMAEntry->pfnCallback = pfnCallback; + pDMAEntry->pCallbackCtxt = pCallbackCtxt; + + pMSPIState->ui32NextHPIdx++; + return AM_HAL_STATUS_SUCCESS; +} // am_hal_mspi_DmaAddTransaction() + +#endif + +//***************************************************************************** +// +//! @brief Determine the virtual device configuration +//! +//! @param handle - handle for the interface. +//! @param eMSPIDevice - external device configuration for MSPI +//! +//! @return virtual device value. +// +// +//***************************************************************************** +// +// MSPI interface mode and chip enable selection. +// This is an internal extension to am_hal_mspi_device_e +// +static uint32_t +mspi_virtual_device(mspi_device_info_t *pMSPIDeviceInfo, uint32_t *pVirtDevice) +{ + // + // Check that the Device Config is in the proper range. + // + if (pMSPIDeviceInfo->eDeviceConfig > AM_HAL_MSPI_FLASH_MAX) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + switch(pMSPIDeviceInfo->eXipMixedMode) + { + case AM_HAL_MSPI_XIPMIXED_NORMAL: + { + // if Serial CE0 or CE1, check for separate I/O. + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + // if serial mode, but not separate I/O , then calculate 3WIRE mode value. + if (!pMSPIDeviceInfo->bSeparateIO) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_SERIAL_CE0_3WIRE - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + // Otherwise return the original eDeviceConfig. + *pVirtDevice = pMSPIDeviceInfo->eDeviceConfig; + return AM_HAL_STATUS_SUCCESS; + } + } + else + { + // Otherwise return the original eDeviceConfig. + *pVirtDevice = pMSPIDeviceInfo->eDeviceConfig; + return AM_HAL_STATUS_SUCCESS; + } + } + break; + + case AM_HAL_MSPI_XIPMIXED_D2: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_DUAL_CE0_1_1_2 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_MSPI_XIPMIXED_AD2: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_DUAL_CE0_1_2_2 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_MSPI_XIPMIXED_D4: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_QUAD_CE0_1_1_4 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_MSPI_XIPMIXED_AD4: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_QUAD_CE0_1_4_4 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } +} + + //***************************************************************************** +// +//! @brief Configure the device config, seperate I/O, mixed mode, and internal +//! PADs based on the virtual device configuration passed in. +//! +//! @param handle - handle for the interface. +//! @param eMSPIDevice - external device configuration for MSPI +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_device_configure(void *pHandle, uint32_t ui32MSPIDevice) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module = pMSPIState->ui32Module; + + switch ( ui32MSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 1; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 1; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_DUAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_DUAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_QUAD0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x10F; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_QUAD1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1F0; + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_OCTAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1FF; + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_OCTAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1FF; + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + return AM_HAL_STATUS_INVALID_ARG; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0_1_1_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 1; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1_1_1_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 1; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0_1_2_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 3; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1_1_2_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 3; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0_1_1_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 5; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x10F; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1_1_1_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 5; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1F0; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0_1_4_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 7; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x10F; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1_1_4_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 7; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1F0; + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE0_3WIRE: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + // Enable both D0 and D1 - as D1 might be getting used for DCX + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1_3WIRE: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + // Enable both D0 and D1 - as D1 might be getting used for DCX + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + default: + break; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +static void mspi_dummy_callback(void *pCallbackCtxt, uint32_t status) +{ + // Dummy - Do nothing +} + +static void mspi_seq_loopback(void *pCallbackCtxt, uint32_t status) +{ + // Reset the state to allow serving callbacks for next set + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pCallbackCtxt; + pMSPIState->ui32NumCQEntries = pMSPIState->ui32NumTransactions + 1; + pMSPIState->ui32LastIdxProcessed = 0; + pMSPIState->bRestart = true; + // Now resume the CQ - to finish loopback + // Resume the CQ + MSPIn(pMSPIState->ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_SEQLOOP; +} + +//***************************************************************************** +// +// External Functions. +// +//***************************************************************************** + +// +// MSPI initialization function +// +uint32_t +am_hal_mspi_initialize(uint32_t ui32Module, void **ppHandle) +{ + // Compile time check to ensure ENTRY_SIZE macros are defined correctly + // incorrect definition will cause divide by 0 error at build time + am_ct_assert((sizeof(am_hal_mspi_cq_dma_entry_t) + 8) == AM_HAL_MSPI_CQ_ENTRY_SIZE); + am_ct_assert(sizeof(am_hal_mspi_dma_entry_t) == AM_HAL_MSPI_HIPRIO_ENTRY_SIZE); + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check that the request module is in range. + // + if (ui32Module >= AM_REG_MSPI_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Check for valid arguements. + // + if (!ppHandle) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if (g_MSPIState[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Initialize the handle. + // + g_MSPIState[ui32Module].prefix.s.bInit = true; + g_MSPIState[ui32Module].prefix.s.magic = AM_HAL_MAGIC_MSPI; + g_MSPIState[ui32Module].ui32Module = ui32Module; + + // + // Return the handle. + // + *ppHandle = (void *)&g_MSPIState[ui32Module]; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI Disable function +// +uint32_t +am_hal_mspi_disable(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Status; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } + +#if MSPI_USE_CQ + + if (pMSPIState->pTCB) + { + // + // Disable the Command Queue. + // + ui32Status = mspi_cq_disable(pHandle); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Reset the Command Queue. + // + mspi_cq_term(pHandle); + } + +#endif // MSPI_USE_CQ + + pMSPIState->prefix.s.bEnable = false; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + + +// +// MSPI Deinitialize function +// +uint32_t +am_hal_mspi_deinitialize(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (pMSPIState->prefix.s.bEnable) + { + am_hal_mspi_disable(pHandle); + } + + // + // Reset the handle. + // + pMSPIState->prefix.s.bInit = false; + pMSPIState->ui32Module = 0; + pMSPIState->eDeviceConfig = (am_hal_mspi_device_e)0; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI device configuration function +// +uint32_t +am_hal_mspi_device_configure(void *pHandle, + am_hal_mspi_dev_config_t *pConfig) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + uint32_t ui32Config = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Configure not allowed in Enabled state + // + if (pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + + // + // Set the clock polarity and phase based on SPI mode. + // + switch(pConfig->eSpiMode) + { + case AM_HAL_MSPI_SPI_MODE_0: // CPOL = 0; CPHA = 0 + ui32Config |= _VAL2FLD(MSPI_CFG_CPOL, 0) | + _VAL2FLD(MSPI_CFG_CPHA, 0); + break; + case AM_HAL_MSPI_SPI_MODE_2: // CPOL = 1; CPHA = 0 + ui32Config |= _VAL2FLD(MSPI_CFG_CPOL, 1) | + _VAL2FLD(MSPI_CFG_CPHA, 0); + break; + case AM_HAL_MSPI_SPI_MODE_1: // CPOL = 0; CPHA = 1 + ui32Config |= _VAL2FLD(MSPI_CFG_CPOL, 0) | + _VAL2FLD(MSPI_CFG_CPHA, 1); + break; + case AM_HAL_MSPI_SPI_MODE_3: // CPOL = 1; CPHA = 1 + ui32Config |= _VAL2FLD(MSPI_CFG_CPOL, 1) | + _VAL2FLD(MSPI_CFG_CPHA, 1); + break; + } + + // + // Set the number of turn-around cycles. + // + ui32Config |= _VAL2FLD(MSPI_CFG_TURNAROUND, pConfig->ui8TurnAround); + + // + // Set the address configuration. + // + ui32Config |= _VAL2FLD(MSPI_CFG_ASIZE, pConfig->eAddrCfg); + + // + // Set the instruction configuration. + // + ui32Config |= _VAL2FLD(MSPI_CFG_ISIZE, pConfig->eInstrCfg); + + // + // Set the configuration in the MSPI peripheral. + // + MSPIn(ui32Module)->CFG = ui32Config; + + // + // Set the clock divisor to get the desired MSPI clock frequency. + // + MSPIn(ui32Module)->MSPICFG_b.CLKDIV = pConfig->eClockFreq; + + // + // Adjust the clock edge configuration depending upon the clock frequency. + // + if ( pConfig->eClockFreq == AM_HAL_MSPI_CLK_48MHZ ) + { + MSPIn(ui32Module)->MSPICFG_b.TXNEG = 1; + MSPIn(ui32Module)->MSPICFG_b.RXNEG = 0; + MSPIn(ui32Module)->MSPICFG_b.RXCAP = 1; + } + else + { + MSPIn(ui32Module)->MSPICFG_b.TXNEG = 0; + MSPIn(ui32Module)->MSPICFG_b.RXNEG = 0; + MSPIn(ui32Module)->MSPICFG_b.RXCAP = 1; + } + + // + // Set the APBCLK for continuous operation. + // + MSPIn(ui32Module)->MSPICFG_b.APBCLK = 1; + + // + // Reset the register storage for next write. + // + ui32Config = 0; + + // + // Set whether to send an instruction. + // + if ( pConfig->bSendInstr ) + { + ui32Config |= _VAL2FLD(MSPI_FLASH_XIPSENDI, 1); + } + + // + // Set whether to send an address. + // + if ( pConfig->bSendAddr ) + { + ui32Config |= _VAL2FLD(MSPI_FLASH_XIPSENDA, 1); + } + + // + // Set whether to enable the TX to RX turnaround. + // + if ( pConfig->bTurnaround ) + { + ui32Config |= _VAL2FLD(MSPI_FLASH_XIPENTURN, 1); + } + + // + // Set to Little Endian mode by default. + // + ui32Config |= _VAL2FLD(MSPI_FLASH_XIPBIGENDIAN, pMSPIState->bBigEndian); + + // + // Set the XIP ACK value to default to 1's during latency period. + // + ui32Config |= _VAL2FLD(MSPI_FLASH_XIPACK, MSPI_FLASH_XIPACK_TERMINATE); + + // + // Set the read instruction. + // + ui32Config |= _VAL2FLD(MSPI_FLASH_READINSTR, pConfig->ui8ReadInstr); + + // + // Set the write instruction. + // + ui32Config |= _VAL2FLD(MSPI_FLASH_WRITEINSTR, pConfig->ui8WriteInstr); + + // + // Set the configuration in the MSPI peripheral. + // + MSPIn(ui32Module)->FLASH = ui32Config; + + g_MSPIState[ui32Module].pTCB = pConfig->pTCB; + g_MSPIState[ui32Module].ui32TCBSize = pConfig->ui32TCBSize; + + if (pConfig->pTCB) + { + // set the DMABCOUNT + MSPIn(ui32Module)->DMABCOUNT = AM_HAL_MSPI_DEFAULT_BURST_COUNT; + + // set the DMATHRESH + MSPIn(ui32Module)->DMATHRESH = AM_HAL_MSPI_DEFAULT_BURST_COUNT >> 2; + // Worst case minimum CQ entries that can be accomodated in provided buffer + // Need to account for the wrap + g_MSPIState[ui32Module].ui32MaxPending = ((pConfig->ui32TCBSize - 8) * 4 / AM_HAL_MSPI_CQ_ENTRY_SIZE); + if (g_MSPIState[ui32Module].ui32MaxPending > AM_HAL_MSPI_MAX_CQ_ENTRIES) + { + g_MSPIState[ui32Module].ui32MaxPending = AM_HAL_MSPI_MAX_CQ_ENTRIES; + } + } + + // + // Reset the register storage for next write. + // + ui32Config = 0; + + // + // Set the scrambling start and end addresses aligned to 64K region. + // + MSPIn(ui32Module)->SCRAMBLING = + _VAL2FLD(MSPI_SCRAMBLING_SCRSTART, pConfig->scramblingStartAddr >> 16) | + _VAL2FLD(MSPI_SCRAMBLING_SCREND, pConfig->scramblingEndAddr >> 16); + + // + // Set the selected IOM to disable. + // + MSPIn(ui32Module)->MSPICFG_b.IOMSEL = 7; + + { + mspi_device_info_t MSPIDeviceInfo; + uint32_t ui32DeviceConfig; + uint32_t ui32Status; + + // + // Determine the virtual device configuration. + // + MSPIDeviceInfo.eDeviceConfig = pConfig->eDeviceConfig; + MSPIDeviceInfo.eXipMixedMode = pConfig->eXipMixedMode; + MSPIDeviceInfo.bSeparateIO = pConfig->bSeparateIO; + ui32Status = mspi_virtual_device(&MSPIDeviceInfo, &ui32DeviceConfig); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Configure the MSPI for a specific device configuration. + // This function sets the following registers/fields: + // CFG.DEVCFG + // CFG.SEPIO + // FLASH.XIPMIXED + // PADCFG + // PADOUTEN + // + mspi_device_configure(pHandle, ui32DeviceConfig); + } + + // + // Set the default endianess for the FIFO. + // + pMSPIState->bBigEndian = false; + + // + // Store the clock frequency for later SW workarounds. + // + pMSPIState->eClockFreq = pConfig->eClockFreq; + + // + // Set the default maximum delay timeout value. + // + pMSPIState->waitTimeout = 10000; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI device configuration function +// +uint32_t +am_hal_mspi_enable(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + + if (pMSPIState->pTCB) + { + pMSPIState->ui32LastIdxProcessed = 0; + pMSPIState->ui32NumCQEntries = 0; + +#if MSPI_USE_CQ + + // + // Initialize the Command Queue service with memory supplied by the application. + // + mspi_cq_init(pMSPIState->ui32Module, pMSPIState->ui32TCBSize, pMSPIState->pTCB); + // Initialize Flags used to force CQ Pause + MSPIn(pMSPIState->ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_CQ | AM_HAL_MSPI_SC_PAUSE_SEQLOOP; + pMSPIState->pHPTransactions = NULL; + pMSPIState->bHP = false; + pMSPIState->ui32NumHPPendingEntries = 0; + pMSPIState->block = 0; + pMSPIState->ui32NumHPEntries = 0; + pMSPIState->eSeq = AM_HAL_MSPI_SEQ_NONE; + pMSPIState->ui32NumTransactions = 0; + pMSPIState->bAutonomous = true; + pMSPIState->ui32NumUnSolicited = 0; + +#else + // Use the buffer for software queuing for DMA + // Determine the maximum number of transactions based on the memory provided + pMSPIState->ui32MaxTransactions = pMSPIState->ui32TCBSize * 4 / sizeof(am_hal_mspi_cq_dma_entry_t); + if (pMSPIState->ui32MaxTransactions > 0) + { + if (pMSPIState->ui32MaxTransactions > AM_HAL_MSPI_MAX_CQ_ENTRIES) + { + pMSPIState->ui32MaxTransactions = AM_HAL_MSPI_MAX_CQ_ENTRIES; + } + pMSPIState->ui32NextIdx = pMSPIState->ui32LastIdxProcessed + 1; + pMSPIState->pTransactions = (am_hal_mspi_cq_dma_entry_t *)pMSPIState->pTCB; + } + +#endif // MSPI_USE_CQ + } + + pMSPIState->prefix.s.bEnable = true; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI device specific control function. +// +uint32_t am_hal_mspi_control(void *pHandle, + am_hal_mspi_request_e eRequest, + void *pConfig) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_MSPI_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if (eRequest > AM_HAL_MSPI_REQ_MAX) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + ui32Module = pMSPIState->ui32Module; + switch(eRequest) + { + case AM_HAL_MSPI_REQ_APBCLK: +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Enable/Disable APBCLK. + // + MSPIn(ui32Module)->MSPICFG_b.APBCLK = *((uint32_t *)pConfig); + break; + + case AM_HAL_MSPI_REQ_FLAG_SETCLR: +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (*((uint32_t *)pConfig) & AM_HAL_MSPI_SC_RESV_MASK) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + MSPIn(ui32Module)->CQSETCLEAR = *((uint32_t *)pConfig); + break; + + case AM_HAL_MSPI_REQ_LINK_IOM: +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (( *((uint32_t *)pConfig) >= AM_REG_IOM_NUM_MODULES ) && ( *((uint32_t *)pConfig) != AM_HAL_MSPI_LINK_IOM_NONE )) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Set the Linked IOM + // + MSPIn(ui32Module)->MSPICFG_b.IOMSEL = *((uint32_t *)pConfig); + break; + + case AM_HAL_MSPI_REQ_SCRAMB_DIS: + // + // Disable scrambling. + // + MSPIn(ui32Module)->SCRAMBLING_b.SCRENABLE = 0; + break; + + case AM_HAL_MSPI_REQ_SCRAMB_EN: + // + // Enable scrambling. + // + MSPIn(ui32Module)->SCRAMBLING_b.SCRENABLE = 1; + break; + + case AM_HAL_MSPI_REQ_XIPACK: +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // + // Enable/Disable XIPACK. + // + MSPIn(ui32Module)->FLASH_b.XIPACK = *((uint32_t *)pConfig); + break; + + case AM_HAL_MSPI_REQ_XIP_DIS: + // + // Disable XIP. + // + MSPIn(ui32Module)->FLASH_b.XIPEN = 0; + break; + + case AM_HAL_MSPI_REQ_XIP_EN: + // + // Enable XIP. + // + MSPIn(ui32Module)->FLASH_b.XIPEN = 1; + break; + + case AM_HAL_MSPI_REQ_DEVICE_CONFIG: +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_IN_USE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + { + uint32_t ui32DeviceConfig; + uint32_t ui32Status; + + // + // Determine the virtual device configuration. + // + ui32Status = mspi_virtual_device((mspi_device_info_t *)pConfig, &ui32DeviceConfig); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Configure the MSPI for a specific device configuration. + // This function sets the following registers/fields: + // CFG.DEVCFG + // CFG.SEPIO + // FLASH.XIPMIXED + // PADCFG + // PADOUTEN + // + ui32Status = mspi_device_configure(pHandle, ui32DeviceConfig); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + break; + + case AM_HAL_MSPI_REQ_PAUSE: + ui32Status = mspi_cq_pause(pMSPIState); + break; + + case AM_HAL_MSPI_REQ_UNPAUSE: + // Resume the CQ + MSPIn(ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_CQ; + break; + + case AM_HAL_MSPI_REQ_SET_SEQMODE: + { + am_hal_mspi_seq_e eSeq; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (!pMSPIState->pTCB) + { + // No space for CMDQ + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + eSeq = *((bool *)pConfig) ? AM_HAL_MSPI_SEQ_UNDER_CONSTRUCTION: AM_HAL_MSPI_SEQ_NONE; + if (eSeq == pMSPIState->eSeq) + { + // Nothing to do + return AM_HAL_STATUS_SUCCESS; + } +#if 0 // We should be able to operate on sequence even if there are HP transactions in progress + // Make sure there is no high priority transaction in progress + if (pMSPIState->ui32NumHPEntries) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif + switch (pMSPIState->eSeq) + { + case AM_HAL_MSPI_SEQ_RUNNING: + { + ui32Status = mspi_cq_pause(pMSPIState); + break; + } + case AM_HAL_MSPI_SEQ_NONE: + { + // Make sure there is no non-blocking transaction in progress + if (pMSPIState->ui32NumCQEntries) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + break; + } + default: + ; + } + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + // Reset the cmdq + am_hal_cmdq_reset(pMSPIState->CQ.pCmdQHdl); + pMSPIState->ui32LastIdxProcessed = 0; + pMSPIState->ui32NumTransactions = 0; + pMSPIState->ui32NumCQEntries = 0; + pMSPIState->eSeq = eSeq; + pMSPIState->bAutonomous = true; + pMSPIState->ui32NumUnSolicited = 0; + } + break; + } + + case AM_HAL_MSPI_REQ_SEQ_END: + { + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + am_hal_cmdq_entry_t *pCQBlock; + uint32_t index; + am_hal_mspi_seq_end_t *pLoop = (am_hal_mspi_seq_end_t *)pConfig; + uint32_t pause = 0; + uint32_t scUnpause = 0; + uint32_t ui32Critical = 0; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pLoop->ui32PauseCondition & AM_HAL_MSPI_PAUSE_FLAG_RESV) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pLoop->ui32StatusSetClr & AM_HAL_MSPI_SC_RESV_MASK) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pMSPIState->eSeq != AM_HAL_MSPI_SEQ_UNDER_CONSTRUCTION) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + if (pMSPIState->block) + { + // End the block if the sequence is ending + pMSPIState->block = 0; + // Unblock the whole batch of commands in this block + MSPIn(ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_BLOCK; + } + if ((pLoop->bLoop) && (!pMSPIState->bAutonomous)) + { + // Need to insert special element in CQ to cause a callback + // This is to reset internal state + ui32Status = am_hal_cmdq_alloc_block(pMSPIState->CQ.pCmdQHdl, 1, &pCQBlock, &index); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + else + { + // + // Store the callback function pointer. + // + pMSPIState->pfnCallback[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = mspi_seq_loopback; + pMSPIState->pCallbackCtxt[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = (void *)pMSPIState; + + // Dummy Entry + pCQBlock->address = (uint32_t)&MSPIn(ui32Module)->CQSETCLEAR; + pCQBlock->value = 0; + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + // + // Post to the CQ. + // + ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, true); + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + + am_hal_cmdq_release_block(pMSPIState->CQ.pCmdQHdl); + return ui32Status; + } + else + { + uint32_t ui32NumPend = pMSPIState->ui32NumCQEntries++; + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + if (ui32NumPend == 0) + { + // + // Enable the Command Queue + // + ui32Status = mspi_cq_enable(pHandle); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } + // Use SWFLAG6 to cause a pause + pause = AM_HAL_MSPI_PAUSE_FLAG_SEQLOOP; + // Revert back the flag after SW callback unpauses it + scUnpause = AM_HAL_MSPI_SC_PAUSE_SEQLOOP; + } + } + // Insert the loopback + ui32Status = am_hal_cmdq_alloc_block(pMSPIState->CQ.pCmdQHdl, sizeof(am_hal_mspi_cq_loop_entry_t) / 8, &pCQBlock, &index); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + else + { + am_hal_mspi_cq_loop_entry_t *pLoopEntry = (am_hal_mspi_cq_loop_entry_t *)pCQBlock; + pLoopEntry->ui32PAUSENAddr = pLoopEntry->ui32PAUSEN2Addr = (uint32_t)&MSPIn(ui32Module)->CQPAUSE; + pLoopEntry->ui32SETCLRAddr = (uint32_t)&MSPIn(ui32Module)->CQSETCLEAR; + pLoopEntry->ui32PAUSEENVal = get_pause_val(pMSPIState, pLoop->ui32PauseCondition | pause); + pLoopEntry->ui32PAUSEEN2Val = AM_HAL_MSPI_PAUSE_DEFAULT; + pLoopEntry->ui32SETCLRVal = pLoop->ui32StatusSetClr | scUnpause; + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Post to the CQ. + // + if (pLoop->bLoop) + { + ui32Status = am_hal_cmdq_post_loop_block(pMSPIState->CQ.pCmdQHdl, false); + } + else + { + ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, false); + } + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + am_hal_cmdq_release_block(pMSPIState->CQ.pCmdQHdl); + } + else + { + uint32_t ui32NumPend = pMSPIState->ui32NumCQEntries++; + pMSPIState->eSeq = (pLoop->bLoop) ? AM_HAL_MSPI_SEQ_RUNNING : AM_HAL_MSPI_SEQ_NONE; + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + if (ui32NumPend == 0) + { + // + // Enable the Command Queue + // + ui32Status = mspi_cq_enable(pHandle); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } + } + return ui32Status; + //break; + } + + case AM_HAL_MSPI_REQ_INIT_HIPRIO: + { + am_hal_mspi_hiprio_cfg_t *pHPCfg = (am_hal_mspi_hiprio_cfg_t *)pConfig; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pMSPIState->pHPTransactions) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + pMSPIState->ui32NumHPEntries = pMSPIState->ui32LastHPIdxProcessed = 0; + pMSPIState->ui32NextHPIdx = pMSPIState->ui32LastHPIdxProcessed + 1; + pMSPIState->pHPTransactions = (am_hal_mspi_dma_entry_t *)pHPCfg->pBuf; + pMSPIState->ui32MaxHPTransactions = pHPCfg->size / sizeof(am_hal_mspi_dma_entry_t); + break; + } + + case AM_HAL_MSPI_REQ_START_BLOCK: + // Pause the next block from proceeding till whole block is finished + MSPIn(ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_PAUSE_BLOCK; + pMSPIState->block = 1; + pMSPIState->ui32NumHPPendingEntries = 0; + break; + + case AM_HAL_MSPI_REQ_END_BLOCK: + // Unblock the whole batch of commands in this block + MSPIn(ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_BLOCK; + pMSPIState->block = 0; + if (pMSPIState->ui32NumHPPendingEntries) + { + // Now it is okay to let go of the block of HiPrio transactions + ui32Status = sched_hiprio(pMSPIState, pMSPIState->ui32NumHPPendingEntries); + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + pMSPIState->ui32NumHPPendingEntries = 0; + } + } + break; + + case AM_HAL_MSPI_REQ_CQ_RAW: + { +#if MSPI_USE_CQ + am_hal_mspi_cq_raw_t *pCqRaw = (am_hal_mspi_cq_raw_t *)pConfig; + am_hal_cmdq_entry_t *pCQBlock; + uint32_t ui32Critical = 0; + uint32_t ui32NumPend; + uint32_t index; + am_hal_mspi_callback_t pfnCallback1; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pCqRaw) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (!pMSPIState->CQ.pCmdQHdl) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // + // Check to see if there is enough room in the CQ + // + if ((pMSPIState->ui32NumCQEntries == AM_HAL_MSPI_MAX_CQ_ENTRIES) || + (am_hal_cmdq_alloc_block(pMSPIState->CQ.pCmdQHdl, pCqRaw->numEntries + 3, &pCQBlock, &index))) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pCQBlock->address = (uint32_t)&MSPIn(ui32Module)->CQPAUSE; + pCQBlock->value = get_pause_val(pMSPIState, pCqRaw->ui32PauseCondition); + pCQBlock++; + // Copy the CQ Entry contents + for (uint32_t i = 0; i < pCqRaw->numEntries; i++, pCQBlock++) + { + pCQBlock->address = pCqRaw->pCQEntry[i].address; + pCQBlock->value = pCqRaw->pCQEntry[i].value; + } + // If there is a need - populate the jump back address + if (pCqRaw->pJmpAddr) + { + *(pCqRaw->pJmpAddr) = (uint32_t)pCQBlock; + } + pCQBlock->address = (uint32_t)&MSPIn(ui32Module)->CQPAUSE; + pCQBlock->value = AM_HAL_MSPI_PAUSE_DEFAULT; + pCQBlock++; + pCQBlock->address = (uint32_t)&MSPIn(ui32Module)->CQSETCLEAR; + pCQBlock->value = pCqRaw->ui32StatusSetClr; + + pfnCallback1 = pCqRaw->pfnCallback; + if ( !pfnCallback1 && !pMSPIState->block && (pMSPIState->eSeq == AM_HAL_MSPI_SEQ_NONE) && + (pMSPIState->ui32NumUnSolicited >= (pMSPIState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumCQEntries get updated in ISR + pfnCallback1 = mspi_dummy_callback; + } + // + // Store the callback function pointer. + // + pMSPIState->pfnCallback[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pfnCallback1; + pMSPIState->pCallbackCtxt[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pCqRaw->pCallbackCtxt; + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Post the transaction to the CQ. + // Register for interrupt only if there is a callback + // + ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, pfnCallback1); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + + am_hal_cmdq_release_block(pMSPIState->CQ.pCmdQHdl); + } + else + { + ui32NumPend = pMSPIState->ui32NumCQEntries++; + pMSPIState->ui32NumTransactions++; + if (pCqRaw->pfnCallback) + { + pMSPIState->bAutonomous = false; + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + pMSPIState->ui32NumUnSolicited++; + } + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + if (ui32NumPend == 0) + { + // + // Enable the Command Queue + // + ui32Status = mspi_cq_enable(pHandle); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } +#else // !AM_HAL_MSPI_CQ + ui32Status = AM_HAL_STATUS_INVALID_ARG; +#endif + break; + } + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return ui32Status; +} + +// +// MSPI get capabilities +// +uint32_t am_hal_mspi_capabilities_get(void *pHandle, + am_hal_mspi_capabilities_t **pCapabilities) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // copy the pointer the MSPI instance capabilities into the passed pointer + // + *pCapabilities = &g_MSPIState[ui32Module].capabilities; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI blocking transfer function +// +uint32_t am_hal_mspi_blocking_transfer(void *pHandle, + am_hal_mspi_pio_transfer_t *pTransaction, + uint32_t ui32Timeout) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + uint32_t ui32Control = 0; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + uint32_t intMask; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + // + // Check that the interface is enabled. + // + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + ui32Module = pMSPIState->ui32Module; + + // Make sure there is no non-blocking transaction in progress + if (pMSPIState->ui32NumCQEntries || pMSPIState->ui32NumHPEntries) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#if MSPI_USE_CQ + if (pMSPIState->eSeq == AM_HAL_MSPI_SEQ_RUNNING) + { + // Dynamic additions to sequence not allowed + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif + + // + // Set the number of bytes to transfer. + // + ui32Control |= _VAL2FLD(MSPI_CTRL_XFERBYTES, pTransaction->ui32NumBytes); + + // + // Set the PIO default to scrambling disabled. + // + ui32Control |= _VAL2FLD(MSPI_CTRL_PIOSCRAMBLE, pTransaction->bScrambling); + + // + // Set transmit or receive operation. + // + ui32Control |= _VAL2FLD(MSPI_CTRL_TXRX, pTransaction->eDirection); + + // + // Set the indication to send an instruction and set the instruction value if + // we have a valid instruction. + // + if ( pTransaction->bSendInstr ) + { + ui32Control |= _VAL2FLD(MSPI_CTRL_SENDI, 1); + MSPIn(ui32Module)->INSTR = + _VAL2FLD(MSPI_INSTR_INSTR, pTransaction->ui16DeviceInstr); + } + + // + // Set the inidication to send an address and set the address value if we have + // a valid address. + // + if ( pTransaction->bSendAddr ) + { + ui32Control |= _VAL2FLD(MSPI_CTRL_SENDA, 1); + MSPIn(ui32Module)->ADDR = + _VAL2FLD(MSPI_ADDR_ADDR, pTransaction->ui32DeviceAddr); + } + + // + // Set the turn-around if needed. + // + if ( pTransaction->bTurnaround ) + { + ui32Control |= _VAL2FLD(MSPI_CTRL_ENTURN, 1); + } + + // + // Set the default FIFO Little Endian format. + // + ui32Control |= _VAL2FLD(MSPI_CTRL_BIGENDIAN, pMSPIState->bBigEndian); + + // + // Set the Quad Command if this is transmit and the device is configured + // for Dual Quad mode. + // + if ( pTransaction->bQuadCmd ) + { + ui32Control |= _VAL2FLD(MSPI_CTRL_QUADCMD, 1); + } + + // + // Start the Transfer. + // + ui32Control |= _VAL2FLD(MSPI_CTRL_START, 1); + + // Disable all interrupts + intMask = MSPIn(ui32Module)->INTEN; + MSPIn(ui32Module)->INTEN = 0; + MSPIn(ui32Module)->INTCLR = AM_HAL_MSPI_INT_ALL; + + // + // Initiate the Transfer. + // + MSPIn(ui32Module)->CTRL = ui32Control; + + // + // Read or Feed the FIFOs. + // + if ( AM_HAL_MSPI_RX == pTransaction->eDirection ) + { + ui32Status = mspi_fifo_read(ui32Module, pTransaction->pui32Buffer, + pTransaction->ui32NumBytes, pMSPIState->waitTimeout); + } + else if ( AM_HAL_MSPI_TX == pTransaction->eDirection ) + { + ui32Status = mspi_fifo_write(ui32Module, pTransaction->pui32Buffer, + pTransaction->ui32NumBytes, pMSPIState->waitTimeout ); + } + + // + // Check status. + // + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + // + // Restore interrupts + // + MSPIn(ui32Module)->INTCLR = AM_HAL_MSPI_INT_ALL; + MSPIn(ui32Module)->INTEN = intMask; + return ui32Status; + } + + // + // Wait for the command to complete. + // + ui32Status = am_hal_flash_delay_status_check(ui32Timeout, + (uint32_t)&MSPIn(ui32Module)->CTRL, + MSPI_CTRL_STATUS_Msk, + _VAL2FLD(MSPI_CTRL_STATUS, 1), + true); + + // + // Restore interrupts + // + MSPIn(ui32Module)->INTCLR = AM_HAL_MSPI_INT_ALL; + MSPIn(ui32Module)->INTEN = intMask; + + // + // Return the status. + // + return ui32Status; + +} + +// +// MSPI Non-Blocking transfer function +// +uint32_t am_hal_mspi_nonblocking_transfer(void *pHandle, + void *pTransfer, + am_hal_mspi_trans_e eMode, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32NumPend; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!pMSPIState->pTCB) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + // + // Check that the interface is enabled. + // + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + +#if MSPI_USE_CQ +#if 0 // We should be able to queue up the CQ even if high priority transaction is in progress + if (pMSPIState->ui32NumHPEntries) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif + if (pMSPIState->eSeq == AM_HAL_MSPI_SEQ_RUNNING) + { + // Dynamic additions to sequence not allowed + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif +#endif // AM_HAL_DISABLE_API_VALIDATION + +#if MSPI_USE_CQ + am_hal_mspi_callback_t pfnCallback1 = pfnCallback; + if ( !pfnCallback1 && !pMSPIState->block && (pMSPIState->eSeq == AM_HAL_MSPI_SEQ_NONE) && + (pMSPIState->ui32NumUnSolicited >= (pMSPIState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumCQEntries get updated in ISR + pfnCallback1 = mspi_dummy_callback; + } + // + // DMA defaults to using the Command Queue + // + ui32Status = mspi_cq_add_transaction(pHandle, pTransfer, eMode, pfnCallback1, pCallbackCtxt); + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + else + { + + uint32_t ui32Critical = 0; + + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Post the transaction to the CQ. + // + ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, pfnCallback1); + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + + am_hal_cmdq_release_block(pMSPIState->CQ.pCmdQHdl); + } + else + { + ui32NumPend = pMSPIState->ui32NumCQEntries++; + pMSPIState->ui32NumTransactions++; + if (pfnCallback) + { + pMSPIState->bAutonomous = false; + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + pMSPIState->ui32NumUnSolicited++; + } + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + if (ui32NumPend == 0) + { + // + // Enable the Command Queue + // + ui32Status = mspi_cq_enable(pHandle); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } + } + +#else + if (pMSPIState->ui32MaxTransactions == 0) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + if (AM_HAL_MSPI_TRANS_DMA != eMode) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + ui32Status = mspi_dma_add_transaction(pHandle, pTransfer, pfnCallback, pCallbackCtxt); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + ui32NumPend = pMSPIState->ui32NumCQEntries++; + + // + // End the critical section. + // + AM_CRITICAL_END + + + if (0 == ui32NumPend) + { + uint32_t index = (pMSPIState->ui32LastIdxProcessed + 1) % pMSPIState->ui32MaxTransactions; + + pMSPIState->ui32TxnInt = 0; + // + // Run the command list + // + run_txn_cmdlist(&pMSPIState->pTransactions[index], sizeof(am_hal_mspi_cq_dma_entry_t) / sizeof(am_hal_cmdq_entry_t)); + } + } + +#endif // !MSPI_USE_CQ + + // + // Return the status. + // + return ui32Status; +} + +// +// MSPI status function +// +uint32_t am_hal_mspi_status_get(void *pHandle, + am_hal_mspi_status_t *pStatus ) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // Get the Command Complete status. + // + // TODO: Need to implement. + + // + // Get the FIFO status. + // + // TODO: Need to implement. + + // + // Get the DMA status. + // + pStatus->bErr = ((MSPIn(ui32Module)->DMASTAT & MSPI_DMASTAT_DMAERR_Msk) > 0); + pStatus->bCmp = ((MSPIn(ui32Module)->DMASTAT & MSPI_DMASTAT_DMACPL_Msk) > 0); + pStatus->bTIP = ((MSPIn(ui32Module)->DMASTAT & MSPI_DMASTAT_DMATIP_Msk) > 0); + + // + // Get the CQ status. + // + // TODO: Need to implement. + pStatus->ui32NumCQEntries = pMSPIState->ui32NumCQEntries; + + // + // Get the scrambling status. + // + // TODO: Need to implement. + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI enable interrupts function +// +uint32_t am_hal_mspi_interrupt_enable(void *pHandle, + uint32_t ui32IntMask) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // Set the interrupt enables according to the mask. + // + MSPIn(ui32Module)->INTEN |= ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI disable interrupts function +// +uint32_t am_hal_mspi_interrupt_disable(void *pHandle, + uint32_t ui32IntMask) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // Clear the interrupt enables according to the mask. + // + MSPIn(ui32Module)->INTEN &= ~ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI interrupt status function +// +uint32_t am_hal_mspi_interrupt_status_get(void *pHandle, + uint32_t *pui32Status, + bool bEnabledOnly) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // if requested, only return the interrupts that are enabled. + // + if ( bEnabledOnly ) + { + uint32_t ui32RetVal = MSPIn(ui32Module)->INTSTAT; + *pui32Status = ui32RetVal & MSPIn(ui32Module)->INTEN; + } + else + { + *pui32Status = MSPIn(ui32Module)->INTSTAT; + } + + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI interrupt clear +// +uint32_t am_hal_mspi_interrupt_clear(void *pHandle, + uint32_t ui32IntMask) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_MSPI_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // clear the requested interrupts. + // + MSPIn(ui32Module)->INTCLR = ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI interrupt service routine +// +uint32_t am_hal_mspi_interrupt_service(void *pHandle, uint32_t ui32IntStatus) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + uint32_t ui32Status; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // Add a delay to help make the service function work. + // TODO - why do we need this? + // +// am_hal_flash_delay(FLASH_CYCLES_US(10)); + +#if MSPI_USE_CQ + if (pMSPIState->bHP) + { +#if 0 + if (ui32IntStatus & AM_HAL_MSPI_INT_CQUPD) + { + while(1); + } +#endif + // + // Accumulate the INTSTAT for this transaction + // + pMSPIState->ui32TxnInt |= ui32IntStatus; + + // + // We need to wait for the DMA complete as well + // + if (pMSPIState->ui32TxnInt & (AM_HAL_MSPI_INT_DMACMP | AM_HAL_MSPI_INT_ERR)) + { + uint32_t index; + + // + // Wait for the command completion + // + if (!(pMSPIState->ui32TxnInt & AM_HAL_MSPI_INT_CMDCMP)) + { + // TODO - We are waiting for CMDCMP indefinetely in the ISR + // May need to re-evaluate + while (!MSPIn(ui32Module)->INTSTAT_b.CMDCMP); + } + pMSPIState->ui32TxnInt |= MSPIn(ui32Module)->INTSTAT; + + // + // Clear the interrupt status + // + MSPIn(ui32Module)->INTCLR = AM_HAL_MSPI_INT_ALL; + + // + // Need to determine the error, call the callback with proper status + // + if (pMSPIState->ui32TxnInt & AM_HAL_MSPI_INT_ERR) + { + ui32Status = AM_HAL_STATUS_FAIL; + + // + // Disable DMA + // + MSPIn(ui32Module)->DMACFG_b.DMAEN = 0; + + // + // Must reset xfer block + // + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 0; // in reset + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 1; // back out -- clears current transfer + } + else + { + ui32Status = AM_HAL_STATUS_SUCCESS; + } + + pMSPIState->ui32LastHPIdxProcessed++; + pMSPIState->ui32NumHPEntries--; + index = pMSPIState->ui32LastHPIdxProcessed % pMSPIState->ui32MaxHPTransactions; + am_hal_mspi_dma_entry_t *pDMAEntry = &pMSPIState->pHPTransactions[index]; + + // + // Call the callback + // + if ( pDMAEntry->pfnCallback != NULL ) + { + pDMAEntry->pfnCallback(pDMAEntry->pCallbackCtxt, ui32Status); + pDMAEntry->pfnCallback = NULL; + } + + // + // Post next transaction if queue is not empty + // + if (pMSPIState->ui32NumHPEntries) + { + pMSPIState->ui32TxnInt = 0; + program_dma(pMSPIState); + } + else + { + pMSPIState->bHP = false; + // Unpause the CQ + // + // Command to set the DMACFG to disable DMA. + // Need to make sure we disable DMA before we can reprogram + // + MSPIn(ui32Module)->DMACFG = _VAL2FLD(MSPI_DMACFG_DMAEN, 0); + // Restore interrupts + MSPIn(ui32Module)->INTEN &= ~(AM_HAL_MSPI_INT_DMACMP | AM_HAL_MSPI_INT_CMDCMP); + // Resume the CQ + MSPIn(ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_CQ; + } + } + return AM_HAL_STATUS_SUCCESS; + } +#endif + // + // Need to check if there is an ongoing transaction + // This is needed because we may get interrupts even for the XIP transactions + // + if (pMSPIState->ui32NumCQEntries) + { +#if MSPI_USE_CQ + am_hal_cmdq_status_t status; + uint32_t index; + am_hal_mspi_CQ_t *pCQ = &g_MSPIState[ui32Module].CQ; + + // + // Get the current and last indexes. + // + if (pCQ->pCmdQHdl) + { + ui32Status = am_hal_cmdq_get_status(pCQ->pCmdQHdl, &status); + + if (AM_HAL_STATUS_SUCCESS == ui32Status) + { + // For Sequence - this can be updated in the callback + pMSPIState->bRestart = false; + // + // Figure out which callbacks need to be handled. + // + while (!pMSPIState->bRestart && (pMSPIState->ui32LastIdxProcessed != status.lastIdxProcessed)) + { + + pMSPIState->ui32LastIdxProcessed++; + pMSPIState->ui32NumCQEntries--; + index = pMSPIState->ui32LastIdxProcessed & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1); + if ( pMSPIState->pfnCallback[index] != NULL ) + { + pMSPIState->pfnCallback[index](pMSPIState->pCallbackCtxt[index], AM_HAL_STATUS_SUCCESS); + if (pMSPIState->eSeq != AM_HAL_MSPI_SEQ_RUNNING) + { + pMSPIState->pfnCallback[index] = NULL; + } + } + } + + // For Sequence - this can be updated in the callback + if (!pMSPIState->bRestart) + { + // + // Process one extra callback if there was an error. + // + if ( (ui32IntStatus & AM_HAL_MSPI_INT_ERR) || (status.bErr) ) + { + pMSPIState->ui32LastIdxProcessed++; + pMSPIState->ui32NumCQEntries--; + index = pMSPIState->ui32LastIdxProcessed & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1); + if ( pMSPIState->pfnCallback[index] != NULL ) + { + pMSPIState->pfnCallback[index](pMSPIState->pCallbackCtxt[index], AM_HAL_STATUS_FAIL); + if (pMSPIState->eSeq != AM_HAL_MSPI_SEQ_RUNNING) + { + pMSPIState->pfnCallback[index] = NULL; + } + } + // Disable CQ + ui32Status = mspi_cq_disable(pMSPIState); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + // Disable DMA + MSPIn(ui32Module)->DMACFG_b.DMAEN = 0; + + // Must reset xfer block + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 0; // in reset + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 1; // back out -- clears current transfer + + // Clear the CQ error. + MSPIn(ui32Module)->CQSTAT |= _VAL2FLD(MSPI_CQSTAT_CQERR, 0); + am_hal_cmdq_error_resume(pCQ->pCmdQHdl); + if (pMSPIState->ui32NumCQEntries) + { + // Re-enable CQ + ui32Status = mspi_cq_enable(pMSPIState); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } + if (pMSPIState->ui32NumCQEntries == 0) + { + // Disable CQ + ui32Status = mspi_cq_disable(pMSPIState); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } + } + } +#else + // + // Accumulate the INTSTAT for this transaction + // + pMSPIState->ui32TxnInt |= ui32IntStatus; + + // + // We need to wait for the DMA complete as well + // + if (pMSPIState->ui32TxnInt & (AM_HAL_MSPI_INT_DMACMP | AM_HAL_MSPI_INT_ERR)) + { + uint32_t index; + + // + // Wait for the command completion + // + if (!(pMSPIState->ui32TxnInt & AM_HAL_MSPI_INT_CMDCMP)) + { + // TODO - We are waiting for CMDCMP indefinetely in the ISR + // May need to re-evaluate + while (!MSPIn(ui32Module)->INTSTAT_b.CMDCMP); + } + pMSPIState->ui32TxnInt |= MSPIn(ui32Module)->INTSTAT; + + // + // Clear the interrupt status + // + MSPIn(ui32Module)->INTCLR = AM_HAL_MSPI_INT_ALL; + + // + // Need to determine the error, call the callback with proper status + // + if (pMSPIState->ui32TxnInt & AM_HAL_MSPI_INT_ERR) + { + ui32Status = AM_HAL_STATUS_FAIL; + + // + // Disable DMA + // + MSPIn(ui32Module)->DMACFG_b.DMAEN = 0; + + // + // Must reset xfer block + // + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 0; // in reset + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 1; // back out -- clears current transfer + } + else + { + ui32Status = AM_HAL_STATUS_SUCCESS; + } + + pMSPIState->ui32LastIdxProcessed++; + pMSPIState->ui32NumCQEntries--; + index = pMSPIState->ui32LastIdxProcessed % pMSPIState->ui32MaxTransactions; + + // + // Call the callback + // + if ( pMSPIState->pfnCallback[index] != NULL ) + { + pMSPIState->pfnCallback[index](pMSPIState->pCallbackCtxt[index], ui32Status); + pMSPIState->pfnCallback[index] = NULL; + } + + // + // Post next transaction if queue is not empty + // + if (pMSPIState->ui32NumCQEntries) + { + index = (pMSPIState->ui32LastIdxProcessed + 1) % pMSPIState->ui32MaxTransactions; + + pMSPIState->ui32TxnInt = 0; + run_txn_cmdlist(&pMSPIState->pTransactions[index], sizeof(am_hal_mspi_cq_dma_entry_t) / sizeof(am_hal_cmdq_entry_t)); + } + } + +#endif // !MSPI_USE_CQ + + if (pMSPIState->ui32NumCQEntries == 0) + { + // Disable DMA + MSPIn(ui32Module)->DMACFG_b.DMAEN = 0; + } + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI power control function +// +uint32_t am_hal_mspi_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Decode the requested power state and update MSPI operation accordingly. + // + switch (ePowerState) + { + case AM_HAL_SYSCTRL_WAKE: + + if (bRetainState && !pMSPIState->registerState.bValid) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_MSPI)); + + if (bRetainState) + { + // + // Restore MSPI registers + // + MSPIn(pMSPIState->ui32Module)->CFG = pMSPIState->registerState.regCFG; + MSPIn(pMSPIState->ui32Module)->MSPICFG = pMSPIState->registerState.regMSPICFG; + MSPIn(pMSPIState->ui32Module)->PADCFG = pMSPIState->registerState.regPADCFG; + MSPIn(pMSPIState->ui32Module)->PADOUTEN = pMSPIState->registerState.regPADOUTEN; + MSPIn(pMSPIState->ui32Module)->FLASH = pMSPIState->registerState.regFLASH; + MSPIn(pMSPIState->ui32Module)->SCRAMBLING = pMSPIState->registerState.regSCRAMBLING; + MSPIn(pMSPIState->ui32Module)->CQADDR = pMSPIState->registerState.regCQADDR; + MSPIn(pMSPIState->ui32Module)->CQPAUSE = pMSPIState->registerState.regCQPAUSE; + MSPIn(pMSPIState->ui32Module)->CQCURIDX = pMSPIState->registerState.regCQCURIDX; + MSPIn(pMSPIState->ui32Module)->CQENDIDX = pMSPIState->registerState.regCQENDIDX; + MSPIn(pMSPIState->ui32Module)->INTEN = pMSPIState->registerState.regINTEN; + + // TODO: May be we can just set these values, as they are constants anyways? + MSPIn(pMSPIState->ui32Module)->DMABCOUNT = pMSPIState->registerState.regDMABCOUNT; + MSPIn(pMSPIState->ui32Module)->DMATHRESH = pMSPIState->registerState.regDMATHRESH; + + // CQFGLAGS are Read-Only and hence can not be directly restored. + // We can try to restore the SWFlags here. Hardware flags depend on external conditions + // and hence can not be restored (assuming the external conditions remain the same, it should be set automatically. + MSPIn(pMSPIState->ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_SET(pMSPIState->registerState.regCQFLAGS & 0xFF); + // + // Set the CQCFG last + // + MSPIn(pMSPIState->ui32Module)->CQCFG = pMSPIState->registerState.regCQCFG; + + pMSPIState->registerState.bValid = false; + } + break; + + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + // Make sure MPSI is not active currently + if (pMSPIState->prefix.s.bEnable && + ((MSPIn(pMSPIState->ui32Module)->DMASTAT_b.DMATIP) || + pMSPIState->ui32NumHPPendingEntries)) + { + return AM_HAL_STATUS_IN_USE; + } + if (bRetainState) + { + // + // Save MSPI Registers + // + pMSPIState->registerState.regCFG = MSPIn(pMSPIState->ui32Module)->CFG; + pMSPIState->registerState.regMSPICFG = MSPIn(pMSPIState->ui32Module)->MSPICFG; + pMSPIState->registerState.regPADCFG = MSPIn(pMSPIState->ui32Module)->PADCFG; + pMSPIState->registerState.regPADOUTEN = MSPIn(pMSPIState->ui32Module)->PADOUTEN; + pMSPIState->registerState.regFLASH = MSPIn(pMSPIState->ui32Module)->FLASH; + pMSPIState->registerState.regSCRAMBLING = MSPIn(pMSPIState->ui32Module)->SCRAMBLING; + pMSPIState->registerState.regCQADDR = MSPIn(pMSPIState->ui32Module)->CQADDR; + pMSPIState->registerState.regCQPAUSE = MSPIn(pMSPIState->ui32Module)->CQPAUSE; + pMSPIState->registerState.regCQFLAGS = MSPIn(pMSPIState->ui32Module)->CQFLAGS; + pMSPIState->registerState.regCQCURIDX = MSPIn(pMSPIState->ui32Module)->CQCURIDX; + pMSPIState->registerState.regCQENDIDX = MSPIn(pMSPIState->ui32Module)->CQENDIDX; + pMSPIState->registerState.regINTEN = MSPIn(pMSPIState->ui32Module)->INTEN; + + // TODO: May be no need to store these values, as they are constants anyways? + pMSPIState->registerState.regDMABCOUNT = MSPIn(pMSPIState->ui32Module)->DMABCOUNT; + pMSPIState->registerState.regDMATHRESH = MSPIn(pMSPIState->ui32Module)->DMATHRESH; + + pMSPIState->registerState.regCQCFG = MSPIn(pMSPIState->ui32Module)->CQCFG; + pMSPIState->registerState.bValid = true; + } + + // + // Disable all the interrupts. + // + am_hal_mspi_interrupt_disable(pHandle, MSPI_INTEN_SCRERR_Msk | + MSPI_INTEN_CQERR_Msk | + MSPI_INTEN_CQPAUSED_Msk | + MSPI_INTEN_CQUPD_Msk | + MSPI_INTEN_CQCMP_Msk | + MSPI_INTEN_DERR_Msk | + MSPI_INTEN_DCMP_Msk | + MSPI_INTEN_RXF_Msk | + MSPI_INTEN_RXO_Msk | + MSPI_INTEN_RXU_Msk | + MSPI_INTEN_TXO_Msk | + MSPI_INTEN_TXE_Msk | + MSPI_INTEN_CMDCMP_Msk); + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_MSPI)); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI High Priority transfer function +// +uint32_t am_hal_mspi_highprio_transfer(void *pHandle, + am_hal_mspi_dma_transfer_t *pTransfer, + am_hal_mspi_trans_e eMode, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!pMSPIState->pTCB) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + if (!pMSPIState->pHPTransactions) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + if (pTransfer->ui32PauseCondition != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pTransfer->ui32StatusSetClr != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } + // + // Check that the interface is enabled. + // + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION +#if MSPI_USE_CQ + + ui32Status = mspi_add_hp_transaction(pHandle, pTransfer, pfnCallback, pCallbackCtxt); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + if (!(pMSPIState->block)) + { + ui32Status = sched_hiprio(pMSPIState, 1); + } + else + { + pMSPIState->ui32NumHPPendingEntries++; + } + } + +#else + ui32Status = AM_HAL_STATUS_INVALID_OPERATION; +#endif // !MSPI_USE_CQ + + // + // Return the status. + // + return ui32Status; +} + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.h new file mode 100644 index 0000000..21b0b7b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.h @@ -0,0 +1,781 @@ +//***************************************************************************** +// +// am_hal_mspi.h +//! @file +//! +//! @brief Functions for accessing and configuring the MSPI. +//! +//! @addtogroup mspi3 Multi-bit SPI (MSPI) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_MSPI_H +#define AM_HAL_MSPI_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! CMSIS-Style macro for handling a variable MSPI module number. +// +//***************************************************************************** +#define MSPIn(n) ((MSPI_Type*)(MSPI_BASE + (n * (MSPI_BASE - MSPI_BASE)))) + +// +// USE_CQ=1 will use the Command Queue in nonblocking transfers. +// 0 uses plain DMA (w/o CQ) in nonblocking transfers. +// +#define MSPI_USE_CQ 1 + +#define AM_HAL_MSPI_MAX_FIFO_SIZE 16 +#define AM_HAL_MSPI_DEFAULT_BURST_COUNT 32 + +// Size guideline for allocation of application supploed buffers +#define AM_HAL_MSPI_CQ_ENTRY_SIZE (18 * sizeof(uint32_t)) +#define AM_HAL_MSPI_HIPRIO_ENTRY_SIZE (6 * sizeof(uint32_t)) + +#define AM_HAL_MSPI_SC_CLEAR(flag) ((flag) << 16) +#define AM_HAL_MSPI_SC_SET(flag) ((flag)) + +// For MSPI - Need to Set the flag for unpausing +#define AM_HAL_MSPI_SC_UNPAUSE(flag) AM_HAL_MSPI_SC_SET(flag) +#define AM_HAL_MSPI_SC_PAUSE(flag) AM_HAL_MSPI_SC_CLEAR(flag) + +// Use this macro to directly control the flags +#define AM_HAL_MSPI_SETCLR(module, scVal) \ + do { \ + MSPIn(module)->CQSETCLEAR = (scVal); \ + } while (0); + +// Flags 5, 7 & 6 are reserved by HAL +#define AM_HAL_MSPI_PAUSE_FLAG_RESV (MSPI_CQFLAGS_CQFLAGS_SWFLAG7 | MSPI_CQFLAGS_CQFLAGS_SWFLAG6 | MSPI_CQFLAGS_CQFLAGS_SWFLAG5) +#define AM_HAL_MSPI_SC_RESV_MASK (AM_HAL_MSPI_PAUSE_FLAG_RESV | (AM_HAL_MSPI_PAUSE_FLAG_RESV << 8) | (AM_HAL_MSPI_PAUSE_FLAG_RESV << 16)) + +// We use SWFLAGEN7 to control SW pausing Command Queue - default unPause +// We use SWFLAGEN6 to pause on the sequece loopback - default Pause +// We use SWFLAGEN5 to pause CQ while a block is building +#define AM_HAL_MSPI_PAUSE_FLAG_IDX (_VAL2FLD(MSPI_CQFLAGS_CQFLAGS, MSPI_CQFLAGS_CQFLAGS_CQIDX)) +#define AM_HAL_MSPI_PAUSE_FLAG_CQ (_VAL2FLD(MSPI_CQFLAGS_CQFLAGS, MSPI_CQFLAGS_CQFLAGS_SWFLAG7)) +#define AM_HAL_MSPI_PAUSE_FLAG_SEQLOOP (_VAL2FLD(MSPI_CQFLAGS_CQFLAGS, MSPI_CQFLAGS_CQFLAGS_SWFLAG6)) +#define AM_HAL_MSPI_PAUSE_FLAG_BLOCK (_VAL2FLD(MSPI_CQFLAGS_CQFLAGS, MSPI_CQFLAGS_CQFLAGS_SWFLAG5)) + +// By default - we Pause CQ for no more entries, or force pause from SW +#define AM_HAL_MSPI_PAUSE_DEFAULT (AM_HAL_MSPI_PAUSE_FLAG_IDX) +#define AM_HAL_MSPI_CQP_PAUSE_DEFAULT (AM_HAL_MSPI_PAUSE_FLAG_IDX | AM_HAL_MSPI_PAUSE_FLAG_CQ) + + //***************************************************************************** + // + //! @name MSPI Interrupts + //! @brief Macro definitions for MSPI interrupt status bits. + //! + //! These macros correspond to the bits in the MSPI interrupt status register. + //! + //! @{ + // + //***************************************************************************** +#define AM_HAL_MSPI_INT_SCRERR MSPI_INTEN_SCRERR_Msk +#define AM_HAL_MSPI_INT_CQERR MSPI_INTEN_CQERR_Msk +#define AM_HAL_MSPI_INT_CQPAUSED MSPI_INTEN_CQPAUSED_Msk +#define AM_HAL_MSPI_INT_CQUPD MSPI_INTEN_CQUPD_Msk +#define AM_HAL_MSPI_INT_CQCMP MSPI_INTEN_CQCMP_Msk +#define AM_HAL_MSPI_INT_DMAERR MSPI_INTEN_DERR_Msk +#define AM_HAL_MSPI_INT_DMACMP MSPI_INTEN_DCMP_Msk +#define AM_HAL_MSPI_INT_RX_FIFO_FULL MSPI_INTEN_RXF_Msk +#define AM_HAL_MSPI_INT_RX_FIFO_OVFL MSPI_INTEN_RXO_Msk +#define AM_HAL_MSPI_INT_RX_FIFO_UNFL MSPI_INTEN_RXU_Msk +#define AM_HAL_MSPI_INT_TX_FIFO_OVFL MSPI_INTEN_TXO_Msk +#define AM_HAL_MSPI_INT_TX_FIFO_EMPTY MSPI_INTEN_TXE_Msk +#define AM_HAL_MSPI_INT_CMDCMP MSPI_INTEN_CMDCMP_Msk +#define AM_HAL_MSPI_INT_ALL 0xFFFFFFFF + +#define AM_HAL_MSPI_INT_ERR (AM_HAL_MSPI_INT_DMAERR | AM_HAL_MSPI_INT_CQERR | AM_HAL_MSPI_INT_SCRERR) + + +#define AM_HAL_MSPI_LINK_IOM_NONE 0x7 + //***************************************************************************** + // + //! @brief Configuration structure for the MSPI. + // + //***************************************************************************** + + // + // Number of bytes in the address + // + typedef enum + { + AM_HAL_MSPI_ADDR_1_BYTE, + AM_HAL_MSPI_ADDR_2_BYTE, + AM_HAL_MSPI_ADDR_3_BYTE, + AM_HAL_MSPI_ADDR_4_BYTE + } am_hal_mspi_addr_e; + + // + // Number of bytes in the instruction + // + typedef enum + { + AM_HAL_MSPI_INSTR_1_BYTE, + AM_HAL_MSPI_INSTR_2_BYTE + } am_hal_mspi_instr_e; + + // + // Transmit or receive + // + typedef enum + { + AM_HAL_MSPI_RX = 0, + AM_HAL_MSPI_TX = 1 + } am_hal_mspi_dir_e; + + // + // Mode of Transfer. + // + typedef enum + { + AM_HAL_MSPI_TRANS_PIO, + AM_HAL_MSPI_TRANS_DMA + } am_hal_mspi_trans_e; + + // + // MSPI interface mode and chip enable selection + // + typedef enum + { + AM_HAL_MSPI_FLASH_SERIAL_CE0, + AM_HAL_MSPI_FLASH_SERIAL_CE1, + AM_HAL_MSPI_FLASH_DUAL_CE0, + AM_HAL_MSPI_FLASH_DUAL_CE1, + AM_HAL_MSPI_FLASH_QUAD_CE0, + AM_HAL_MSPI_FLASH_QUAD_CE1, + AM_HAL_MSPI_FLASH_OCTAL_CE0, + AM_HAL_MSPI_FLASH_OCTAL_CE1, + AM_HAL_MSPI_FLASH_QUADPAIRED, + AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL, + AM_HAL_MSPI_FLASH_MAX = AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL + } am_hal_mspi_device_e; + + // + // Enumerate the SPI modes. Note that these are arranged per the ordering of + // SPHA (bit1) and SPOL (bit0) in the IOM.MSPICFG register. + // + typedef enum + { + AM_HAL_MSPI_SPI_MODE_0, // CPOL = 0; CPHA = 0 + AM_HAL_MSPI_SPI_MODE_2, // CPOL = 1; CPHA = 0 + AM_HAL_MSPI_SPI_MODE_1, // CPOL = 0; CPHA = 1 + AM_HAL_MSPI_SPI_MODE_3, // CPOL = 1; CPHA = 1 + } am_hal_mspi_spi_mode_e; + + typedef enum + { + AM_HAL_MSPI_CLK_48MHZ = 1, + AM_HAL_MSPI_CLK_24MHZ = 2, + AM_HAL_MSPI_CLK_16MHZ = 3, + AM_HAL_MSPI_CLK_12MHZ = 4, + AM_HAL_MSPI_CLK_8MHZ = 6, + AM_HAL_MSPI_CLK_6MHZ = 8, + AM_HAL_MSPI_CLK_4P8MHZ = 10, + AM_HAL_MSPI_CLK_4MHZ = 12, + AM_HAL_MSPI_CLK_3P2MHZ = 15, + AM_HAL_MSPI_CLK_3MHZ = 16, + AM_HAL_MSPI_CLK_1P5MHZ = 32 + } am_hal_mspi_clock_e; + + // + // Transfer callback function prototype + // + typedef void (*am_hal_mspi_callback_t)(void *pCallbackCtxt, uint32_t status); + + typedef struct + { + bool bLoop; + //! Command Queue Transaction Gating + uint32_t ui32PauseCondition; + //! Command Queue Post-Transaction status setting + uint32_t ui32StatusSetClr; + } am_hal_mspi_seq_end_t; + + typedef struct + { + uint8_t *pBuf; // Buffer provided to store the high priority transaction context + uint32_t size; // Size of buffer in bytes + } am_hal_mspi_hiprio_cfg_t; + + typedef struct + { + //! Command Queue Advanced control on gating conditions for transaction to start + uint32_t ui32PauseCondition; + //! Command Queue Advanced Post-Transaction status setting + uint32_t ui32StatusSetClr; + am_hal_cmdq_entry_t *pCQEntry; + uint32_t numEntries; + am_hal_mspi_callback_t pfnCallback; + void *pCallbackCtxt; + uint32_t *pJmpAddr; + } am_hal_mspi_cq_raw_t; + + typedef enum + { + // Pass uint32_t as pConfig + AM_HAL_MSPI_REQ_APBCLK, + // Used to set/clear 8 CQ Pause flags - reserved flags are defined as AM_HAL_MSPI_PAUSE_FLAG_RESV + AM_HAL_MSPI_REQ_FLAG_SETCLR, + // Pass uint32_t as pConfig indicating the IOM# to link to. AM_HAL_MSPI_LINK_IOM_NONE indicates no IOM linked + AM_HAL_MSPI_REQ_LINK_IOM, + // pConfig N/A + AM_HAL_MSPI_REQ_SCRAMB_DIS, + // pConfig N/A + AM_HAL_MSPI_REQ_SCRAMB_EN, + // Pass uint32_t as pConfig + AM_HAL_MSPI_REQ_XIPACK, + // pConfig N/A + AM_HAL_MSPI_REQ_XIP_DIS, + // pConfig N/A + AM_HAL_MSPI_REQ_XIP_EN, + // Pass mspi_device_info_t as pConfig + AM_HAL_MSPI_REQ_DEVICE_CONFIG, + // Pause the CQ gracefully + AM_HAL_MSPI_REQ_PAUSE, + // Unpause the CQ + AM_HAL_MSPI_REQ_UNPAUSE, + // Get in and out of Sequence Mode - which allows building a sequence, which either runs once, or repeats + // Pass in bool as pConfig - true/false + AM_HAL_MSPI_REQ_SET_SEQMODE, + // Pass am_hal_mspi_seq_end_t * as pConfig + AM_HAL_MSPI_REQ_SEQ_END, + // Initialize configuration for high priority trasactions + // These transactions take precedence over existing CQ transactions + // Pass am_hal_mspi_hiprio_cfg_t * as pConfig + AM_HAL_MSPI_REQ_INIT_HIPRIO, + // Create a block of transactions which are not paused in between + // pConfig N/A + AM_HAL_MSPI_REQ_START_BLOCK, + // pConfig N/A + AM_HAL_MSPI_REQ_END_BLOCK, + // Raw CQ transaction + // Pass am_hal_mspi_cq_raw_t * as pConfig + AM_HAL_MSPI_REQ_CQ_RAW, + AM_HAL_MSPI_REQ_MAX + + } am_hal_mspi_request_e; + + typedef enum + { + AM_HAL_MSPI_XIPMIXED_NORMAL = 0, + AM_HAL_MSPI_XIPMIXED_D2 = 1, //1:1:2 timing for Instr:Addr:Data + AM_HAL_MSPI_XIPMIXED_AD2 = 3, //1:2:2 timing for Instr:Addr:Data + AM_HAL_MSPI_XIPMIXED_D4 = 5, //1:1:4 timing for Instr:Addr:Data + AM_HAL_MSPI_XIPMIXED_AD4 = 7 //1:4:4 timing for Instr:Addr:Data + } am_hal_mspi_xipmixed_mode_e; + + // + // Device configuration structure + // + typedef struct + { + // + // MSPI device configuration for Polling I/O (PIO) Operation. + // + + //! Number of turn around cycles between an Address write and Data read. + uint8_t ui8TurnAround; + + //! Address Configuration + am_hal_mspi_addr_e eAddrCfg; + + //! Instruction Configuration + am_hal_mspi_instr_e eInstrCfg; + + //! Read instruction sent to flash device + uint8_t ui8ReadInstr; + + //! Write instruction sent to flash device + uint8_t ui8WriteInstr; + + //! External Flash Device configuration + am_hal_mspi_device_e eDeviceConfig; + + // + // MSPI clock configuration. + // + + //! SPI Mode. + am_hal_mspi_spi_mode_e eSpiMode; + + //! Clock frequency + am_hal_mspi_clock_e eClockFreq; + + //! XIPMIXED configure + am_hal_mspi_xipmixed_mode_e eXipMixedMode; + + // + // MSPI device configuration for XIP/DMA/Scrambling operations. + // + + //! Send Device Address + bool bSendAddr; + + //! Send Device Instruction + bool bSendInstr; + + //! Separate MOSI/MISO + bool bSeparateIO; + + //! Enable Turnaround between Address write and Data read. + bool bTurnaround; + + // + // MSPI DMA TCB/Command Queue memory allocation. + // + + //! DMA Transfer Control Buffer size in words. + uint32_t ui32TCBSize; + + //! DMA Transfer Control Buffer + uint32_t *pTCB; + + // + // MSPI Scrambling configuration. + // + + //! Scrambling Start Address + uint32_t scramblingStartAddr; + + //! Scrambling End Address + uint32_t scramblingEndAddr; + + } am_hal_mspi_dev_config_t; + + // + // MSPI configuration record for determining virtual device configuration. + // + typedef struct + { + //! External Flash Device configuration + am_hal_mspi_device_e eDeviceConfig; + + //! XIPMIXED configure + am_hal_mspi_xipmixed_mode_e eXipMixedMode; + + //! Separate MOSI/MISO + bool bSeparateIO; + + } mspi_device_info_t; + // + // MSPI Capabilities structure + // + typedef struct + { + am_hal_mspi_device_e eDeviceConfig; + } am_hal_mspi_capabilities_t; + + // + // Device PIO transfer structure + // + typedef struct + { + //! Number of bytes to transfer + uint32_t ui32NumBytes; + + //! Enable scrambling. + bool bScrambling; + + //! Transfer Direction (Transmit/Receive) + am_hal_mspi_dir_e eDirection; + + //! Send Device Address + bool bSendAddr; + + //! Device Address + uint32_t ui32DeviceAddr; + + //! Send Device Instruction + bool bSendInstr; + + //! Device Instruction + uint16_t ui16DeviceInstr; + + //! Enable Turnaround between Address write and Data read. + bool bTurnaround; + + //! Paired-Quad + bool bQuadCmd; + + //! Buffer + uint32_t *pui32Buffer; + + } am_hal_mspi_pio_transfer_t; + + // + // DMA transfer structure + // + typedef struct + { + //! Address Configuration + am_hal_mspi_addr_e eAddrCfg; + + //! Priority 0 = Low (best effort); 1 = High (service immediately) + uint8_t ui8Priority; + + //! Direction RX: 0 = Peripheral to Memory; TX: 1 = Memory to Peripheral + am_hal_mspi_dir_e eDirection; + + //! Transfer Count + uint32_t ui32TransferCount; + + //! External Flash Device Address + uint32_t ui32DeviceAddress; + + //! Internal SRAM Address + uint32_t ui32SRAMAddress; + + //! Command Queue Transaction Gating + uint32_t ui32PauseCondition; + //! Command Queue Post-Transaction status setting + uint32_t ui32StatusSetClr; + + } am_hal_mspi_dma_transfer_t; + + + // + // MSPI status structure. + // + typedef struct + { + // + // DMA status. + // + bool bErr; + bool bCmp; + bool bTIP; + uint32_t ui32NumCQEntries; + } am_hal_mspi_status_t; + + +#define am_hal_mspi_buffer(A) \ + union \ + { \ + uint32_t words[(A + 3) >> 2]; \ + uint8_t bytes[A]; \ + } + + //***************************************************************************** + // + //! @brief MSPI initialization function + //! + //! @param ui32Module - module instance. + //! @param handle - returns the handle for the module instance. + //! + //! This function accepts a module instance, allocates the interface and then + //! returns a handle to be used by the remaining interface functions. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_initialize(uint32_t ui32Module, + void **ppHandle); + + //***************************************************************************** + // + //! @brief MSPI deinitialization function + //! + //! @param handle - the handle for the module instance. + //! + //! This function accepts a handle to an instance and de-initializes the + //! interface. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_deinitialize(void *pHandle); + + //***************************************************************************** + // + //! @brief MSPI device configuration function + //! + //! @param handle - handle for the interface. + //! @param pConfig - pointer to the configuration structure. + //! + //! This function configures the MSPI settings for a particular external flash device. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_device_configure(void *pHandle, + am_hal_mspi_dev_config_t *pConfig); + + //***************************************************************************** + // + //! @brief MSPI enable function + //! + //! @param handle - the handle for the module instance. + //! + //! This function accepts a handle to an instance and enables the + //! interface. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_enable(void *pHandle); + + //***************************************************************************** + // + //! @brief MSPI disable function + //! + //! @param handle - the handle for the module instance. + //! + //! This function accepts a handle to an instance and disables the + //! interface. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_disable(void *pHandle); + + //***************************************************************************** + // + //! @brief MSPI device specific control function. + //! + //! @param handle - handle for the interface. + //! @param request - device specific special request code. + //! @param pConfig - pointer to the request specific configuration. + //! + //! This function configures the MSPI settings for XIP or DMA operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_control(void *pHandle, + am_hal_mspi_request_e eRequest, + void *pConfig); + + //***************************************************************************** + // + //! @brief MSPI capability interrogation function + //! + //! @param handle - handle for the interface. + //! @param pCapabilities - pointer to an interface specific structure used to + //! return the capabilities of the interface. + //! + //! This function returns the specific capabilities of the MSPI. In some + //! cases the capabilities may be instance specific (e.g. maximum data rate). + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_capabilities_get(void *pHandle, + am_hal_mspi_capabilities_t **pCapabilities); + + //***************************************************************************** + // + //! @brief MSPI blocking transfer function + //! + //! @param pHandle - handle for the interface. + //! @param pTransaction - pointer to the transaction control structure. + //! @param ui32Timeout - timeout in usecs. + //! + //! This function performs a transaction on the MSPI in PIO mode. It handles + //! half duplex transactions only (TX or RX). + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_blocking_transfer(void *pHandle, + am_hal_mspi_pio_transfer_t *pTransaction, + uint32_t ui32Timeout); + //***************************************************************************** + // + //! @brief MSPI Non-Blocking transfer function + //! + //! @param handle - handle for the interface. + //! @param pTransaction - pointer to the transaction control structure. + //! @param pfnCallback - pointer the callback function to be executed when + //! transaction is complete. + //! + //! This function performs a transaction on the MSPI using either DMA or the + //! Command Queue with DMA. It handles half duplex transactions. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_nonblocking_transfer(void *pHandle, + void *pTransfer, + am_hal_mspi_trans_e eMode, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt); + + //***************************************************************************** + // + //! @brief MSPI status function + //! + //! @param handle - handle for the interface. + //! + //! This function returns the current status of the DMA operation. + //! + //! @return status - DMA status flags. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_status_get(void *pHandle, + am_hal_mspi_status_t *pStatus ); + + //***************************************************************************** + // + //! @brief MSPI enable interrupts function + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - MSPI interrupt mask. + //! + //! This function enables the specific indicated interrupts. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_interrupt_enable(void *pHandle, + uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief MSPI disable interrupts function + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - MSPI interrupt mask. + //! + //! This function disable the specific indicated interrupts. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_interrupt_disable(void *pHandle, + uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief MSPI interrupt status function + //! + //! @param handle - handle for the interface. + //! @param pui32Status - returns the interrupt status value. + //! @param bEnabledOnly - TRUE: only report interrupt status for enalbed ints. + //! FALSE: report all interrupt status values. + //! + //! This function returns the specific indicated interrupt status. + //! + //! @return status - interrupt status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_interrupt_status_get(void *pHandle, + uint32_t *pui32Status, + bool bEnabledOnly); + + //***************************************************************************** + // + //! @brief MSPI interrupt clear + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - uint32_t for interrupts to clear + //! + //! This function clears the interrupts for the given peripheral. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_interrupt_clear(void *pHandle, + uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief MSPI interrupt service routine + //! + //! @param handle - handle for the interface. + //! @param ui32IntStatus - interrupt status. + //! + //! This function is designed to be called from within the user defined ISR + //! in order to service the non-blocking, queued, or DMA processing for a given + //! module instance. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_interrupt_service(void *pHandle, + uint32_t ui32IntStatus); + + //***************************************************************************** + // + //! @brief MSPI power control function + //! + //! @param handle - handle for the interface. + //! @param ePowerState - the desired power state to move the peripheral to. + //! @param bRetainState - flag (if true) to save/restore peripheral state upon + //! power state change. + //! + //! This function updates the peripheral to a given power state. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState); +// +// MSPI High Priority transfer function +// +extern uint32_t am_hal_mspi_highprio_transfer(void *pHandle, + am_hal_mspi_dma_transfer_t *pTransfer, + am_hal_mspi_trans_e eMode, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_MSPI_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.c new file mode 100644 index 0000000..9acb471 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.c @@ -0,0 +1,651 @@ +//***************************************************************************** +// +//! @file am_hal_pdm.c +//! +//! @brief HAL implementation for the PDM module. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// PDM magic number for handle verification. +// +//***************************************************************************** +#define AM_HAL_MAGIC_PDM 0xF956E2 + +#define AM_HAL_PDM_HANDLE_VALID(h) \ + ((h) && \ + ((am_hal_handle_prefix_t *)(h))->s.bInit && \ + (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_PDM)) + +//***************************************************************************** +// +// Convenience macro for passing errors. +// +//***************************************************************************** +#define RETURN_ON_ERROR(x) \ + if ((x) != AM_HAL_STATUS_SUCCESS) \ + { \ + return (x); \ + }; + +//***************************************************************************** +// +// Abbreviation for validating handles and returning errors. +// +//***************************************************************************** +#ifndef AM_HAL_DISABLE_API_VALIDATION + +#define AM_HAL_PDM_HANDLE_CHECK(h) \ + if (!AM_HAL_PDM_HANDLE_VALID(h)) \ + { \ + return AM_HAL_STATUS_INVALID_HANDLE; \ + } + +#else + +#define AM_HAL_PDM_HANDLE_CHECK(h) + +#endif // AM_HAL_DISABLE_API_VALIDATION + +//***************************************************************************** +// +// Helper macros for delays. +// +//***************************************************************************** +#define delay_ms(ms) \ + if (1) \ + { \ + am_hal_clkgen_status_t sClkGenStatus; \ + am_hal_clkgen_status_get(&sClkGenStatus); \ + am_hal_flash_delay((ms) * (sClkGenStatus.ui32SysclkFreq / 3000)); \ + } + +#define delay_us(us) \ + if (1) \ + { \ + am_hal_clkgen_status_t sClkGenStatus; \ + am_hal_clkgen_status_get(&sClkGenStatus); \ + am_hal_flash_delay((us) * (sClkGenStatus.ui32SysclkFreq / 3000000)); \ + } + +//***************************************************************************** +// +// Structure for handling PDM register state information for power up/down +// +//***************************************************************************** +typedef struct +{ + bool bValid; +} +am_hal_pdm_register_state_t; + +//***************************************************************************** +// +// Structure for handling PDM HAL state information. +// +//***************************************************************************** +typedef struct +{ + am_hal_handle_prefix_t prefix; + am_hal_pdm_register_state_t sRegState; + uint32_t ui32Module; +} +am_hal_pdm_state_t; + +//***************************************************************************** +// +// State structure for each module. +// +//***************************************************************************** +am_hal_pdm_state_t g_am_hal_pdm_states[AM_REG_PDM_NUM_MODULES]; + +//***************************************************************************** +// +// Static function definitions. +// +//***************************************************************************** +static uint32_t find_dma_threshold(uint32_t ui32TotalCount); + +//***************************************************************************** +// +// Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_pdm_initialize(uint32_t ui32Module, void **ppHandle) +{ + // + // Check that the request module is in range. + // + if ( ui32Module >= AM_REG_PDM_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Check for valid arguements. + // + if (!ppHandle) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if (g_am_hal_pdm_states[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Initialize the handle. + // + g_am_hal_pdm_states[ui32Module].prefix.s.bInit = true; + g_am_hal_pdm_states[ui32Module].prefix.s.magic = AM_HAL_MAGIC_PDM; + g_am_hal_pdm_states[ui32Module].ui32Module = ui32Module; + g_am_hal_pdm_states[ui32Module].sRegState.bValid = false; + + // + // Return the handle. + // + *ppHandle = (void *)&g_am_hal_pdm_states[ui32Module]; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// De-Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_pdm_deinitialize(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *)pHandle; + + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // Reset the handle. + // + pState->prefix.s.bInit = false; + pState->prefix.s.magic = 0; + pState->ui32Module = 0; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Power control function. +// +//***************************************************************************** +uint32_t +am_hal_pdm_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + am_hal_pwrctrl_periph_e ePDMPowerModule = ((am_hal_pwrctrl_periph_e) + (AM_HAL_PWRCTRL_PERIPH_PDM + + ui32Module)); + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // Decode the requested power state and update PDM operation accordingly. + // + switch (ePowerState) + { + // + // Turn on the PDM. + // + case AM_HAL_SYSCTRL_WAKE: + // + // Make sure we don't try to restore an invalid state. + // + if (bRetainState && !pState->sRegState.bValid) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable(ePDMPowerModule); + + if (bRetainState) + { + // + // Restore PDM registers + // + AM_CRITICAL_BEGIN; + + pState->sRegState.bValid = false; + + AM_CRITICAL_END; + } + break; + + // + // Turn off the PDM. + // + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + if (bRetainState) + { + AM_CRITICAL_BEGIN; + + pState->sRegState.bValid = true; + + AM_CRITICAL_END; + } + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable(ePDMPowerModule); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Configure the PDM. +// +//***************************************************************************** +uint32_t +am_hal_pdm_configure(void *pHandle, am_hal_pdm_config_t *psConfig) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // Apply the config structure settings to the PCFG register. + // + PDMn(ui32Module)->PCFG_b.SOFTMUTE = psConfig->bSoftMute; + PDMn(ui32Module)->PCFG_b.CYCLES = psConfig->ui32GainChangeDelay; + PDMn(ui32Module)->PCFG_b.HPCUTOFF = psConfig->ui32HighPassCutoff; + PDMn(ui32Module)->PCFG_b.ADCHPD = psConfig->bHighPassEnable; + PDMn(ui32Module)->PCFG_b.SINCRATE = psConfig->ui32DecimationRate; + PDMn(ui32Module)->PCFG_b.MCLKDIV = psConfig->eClkDivider; + PDMn(ui32Module)->PCFG_b.PGALEFT = psConfig->eLeftGain; + PDMn(ui32Module)->PCFG_b.PGARIGHT = psConfig->eRightGain; + PDMn(ui32Module)->PCFG_b.LRSWAP = psConfig->bLRSwap; + + // + // Set the PDM Core enable bit to enable PDM to PCM conversions. + // + PDMn(ui32Module)->PCFG_b.PDMCOREEN = PDM_PCFG_PDMCOREEN_EN; + + // + // Program the "voice" registers. + // + PDMn(ui32Module)->VCFG_b.PDMCLKEN = PDM_VCFG_PDMCLKEN_DIS; + PDMn(ui32Module)->VCFG_b.IOCLKEN = PDM_VCFG_IOCLKEN_DIS; + PDMn(ui32Module)->VCFG_b.RSTB = PDM_VCFG_RSTB_RESET; + PDMn(ui32Module)->VCFG_b.CHSET = psConfig->ePCMChannels; + PDMn(ui32Module)->VCFG_b.PCMPACK = psConfig->bDataPacking; + PDMn(ui32Module)->VCFG_b.SELAP = psConfig->ePDMClkSource; + PDMn(ui32Module)->VCFG_b.DMICKDEL = psConfig->bPDMSampleDelay; + PDMn(ui32Module)->VCFG_b.BCLKINV = psConfig->bInvertI2SBCLK; + PDMn(ui32Module)->VCFG_b.I2SEN = psConfig->bI2SEnable; + PDMn(ui32Module)->VCFG_b.PDMCLKSEL = psConfig->ePDMClkSpeed; + + delay_us(100); + + PDMn(ui32Module)->VCFG_b.RSTB = PDM_VCFG_RSTB_NORM; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Enable the PDM. +// +//***************************************************************************** +uint32_t +am_hal_pdm_enable(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->VCFG_b.IOCLKEN = PDM_VCFG_IOCLKEN_EN; + PDMn(ui32Module)->VCFG_b.PDMCLKEN = PDM_VCFG_PDMCLKEN_EN; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Disable the PDM. +// +//***************************************************************************** +uint32_t +am_hal_pdm_disable(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->VCFG_b.IOCLKEN = PDM_VCFG_IOCLKEN_DIS; + PDMn(ui32Module)->VCFG_b.PDMCLKEN = PDM_VCFG_PDMCLKEN_DIS; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Given the total number of bytes in a DMA transaction, find a reasonable +// threshold setting. +// +//***************************************************************************** +static uint32_t +find_dma_threshold(uint32_t ui32TotalCount) +{ + // + // Start with a threshold value of 24, and search downward for values that + // fit our criteria. + // + uint32_t ui32Threshold; + uint32_t ui32Minimum = AM_HAL_PDM_DMA_THRESHOLD_MIN; + + for ( ui32Threshold = 24; ui32Threshold >= ui32Minimum; ui32Threshold -= 4 ) + { + // + // With our loop parameters, we've already guaranteed that the + // threshold will be no higher than 24, and that it will be divisible + // by 4. The only remaining requirement is that ui32TotalCount must + // also be divisible by the threshold. + // + if ((ui32TotalCount % ui32Threshold) == 0) + { + break; + } + } + + // + // If we found an appropriate value, we'll return it here. Otherwise, we + // will return zero. + // + if (ui32Threshold < ui32Minimum) + { + ui32Threshold = 0; + } + + return ui32Threshold; +} + +//***************************************************************************** +// +// Starts a DMA transaction from the PDM directly to SRAM +// +//***************************************************************************** +uint32_t +am_hal_pdm_dma_start(void *pHandle, am_hal_pdm_transfer_t *pDmaCfg) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // Find an appropriate threshold size for this transfer. + // + uint32_t ui32Threshold = find_dma_threshold(pDmaCfg->ui32TotalCount); + + // + // If we didn't find a threshold that will work, throw an error. + // + if (ui32Threshold == 0) + { + return AM_HAL_PDM_STATUS_BAD_TOTALCOUNT; + } + + PDMn(ui32Module)->FIFOTHR = ui32Threshold; + + // + // Configure DMA. + // + PDMn(ui32Module)->DMACFG = 0; + PDMn(ui32Module)->DMACFG_b.DMAPRI = PDM_DMACFG_DMAPRI_LOW; + PDMn(ui32Module)->DMACFG_b.DMADIR = PDM_DMACFG_DMADIR_P2M; + PDMn(ui32Module)->DMATOTCOUNT = pDmaCfg->ui32TotalCount; + PDMn(ui32Module)->DMATARGADDR = pDmaCfg->ui32TargetAddr; + + // + // Make sure the trigger is set for threshold. + // + PDMn(ui32Module)->DMATRIGEN_b.DTHR = 1; + + // + // Enable DMA + // + PDMn(ui32Module)->DMACFG_b.DMAEN = PDM_DMACFG_DMAEN_EN; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Flush the PDM FIFO +// +//***************************************************************************** +uint32_t +am_hal_pdm_fifo_flush(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->FIFOFLUSH = 1; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Enable PDM passthrough to the I2S slave. +// +//***************************************************************************** +uint32_t +am_hal_pdm_i2s_enable(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + uint32_t ui32Module = pState->ui32Module; + + PDMn(ui32Module)->VCFG_b.I2SEN = PDM_VCFG_I2SEN_EN; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Disable PDM passthrough to the I2S slave. +// +//***************************************************************************** +uint32_t +am_hal_pdm_i2s_disable(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + uint32_t ui32Module = pState->ui32Module; + + PDMn(ui32Module)->VCFG_b.I2SEN = PDM_VCFG_I2SEN_DIS; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Interrupt enable. +// +//***************************************************************************** +uint32_t +am_hal_pdm_interrupt_enable(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->INTEN |= ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Interrupt disable. +// +//***************************************************************************** +uint32_t +am_hal_pdm_interrupt_disable(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->INTEN &= ~ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Interrupt clear. +// +//***************************************************************************** +uint32_t +am_hal_pdm_interrupt_clear(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->INTCLR = ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Returns the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_pdm_interrupt_status_get(void *pHandle, uint32_t *pui32Status, bool bEnabledOnly) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // If requested, only return the interrupts that are enabled. + // + if ( bEnabledOnly ) + { + *pui32Status = PDMn(ui32Module)->INTSTAT; + *pui32Status &= PDMn(ui32Module)->INTEN; + } + else + { + *pui32Status = PDMn(ui32Module)->INTSTAT; + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.h new file mode 100644 index 0000000..6968217 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.h @@ -0,0 +1,318 @@ +//***************************************************************************** +// +//! @file am_hal_pdm.h +//! +//! @brief API for the PDM module +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_PDM_H +#define AM_HAL_PDM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable IOS module number. +// +//***************************************************************************** +#define AM_REG_PDM_NUM_MODULES 1 +#define PDMn(n) ((PDM_Type*)(PDM_BASE + (n * (PDM_BASE - PDM_BASE)))) + +//***************************************************************************** +// +// DMA threshold minimum. +// +// The PDM DMA works best if its threshold value is set to a multiple of 4 +// between 16 and 24, but it will technically allow threshold settings between +// 4 and 24. This macro sets the minimum threshold value that the HAL layer +// will allow. +// +//***************************************************************************** +#define AM_HAL_PDM_DMA_THRESHOLD_MIN 16 + +//***************************************************************************** +// +// PDM-specific error conditions. +// +//***************************************************************************** +typedef enum +{ + // + // The PDM HAL will throw this error if it can't find a threshold value to + // match the total-count value passed in by a caller requesting a DMA + // transfer. The PDM hardware requires all DMA transactions to be evenly + // divisible in chunks of one FIFO size or smaller. Try changing your + // ui32TotalCount value to a more evenly divisible number. + // + AM_HAL_PDM_STATUS_BAD_TOTALCOUNT = AM_HAL_STATUS_MODULE_SPECIFIC_START, +} +am_hal_pdm_status_e; + +//***************************************************************************** +// +// Gain settings. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_PDM_GAIN_P405DB = PDM_PCFG_PGALEFT_P405DB, + AM_HAL_PDM_GAIN_P390DB = PDM_PCFG_PGALEFT_P390DB, + AM_HAL_PDM_GAIN_P375DB = PDM_PCFG_PGALEFT_P375DB, + AM_HAL_PDM_GAIN_P360DB = PDM_PCFG_PGALEFT_P360DB, + AM_HAL_PDM_GAIN_P345DB = PDM_PCFG_PGALEFT_P345DB, + AM_HAL_PDM_GAIN_P330DB = PDM_PCFG_PGALEFT_P330DB, + AM_HAL_PDM_GAIN_P315DB = PDM_PCFG_PGALEFT_P315DB, + AM_HAL_PDM_GAIN_P300DB = PDM_PCFG_PGALEFT_P300DB, + AM_HAL_PDM_GAIN_P285DB = PDM_PCFG_PGALEFT_P285DB, + AM_HAL_PDM_GAIN_P270DB = PDM_PCFG_PGALEFT_P270DB, + AM_HAL_PDM_GAIN_P255DB = PDM_PCFG_PGALEFT_P255DB, + AM_HAL_PDM_GAIN_P240DB = PDM_PCFG_PGALEFT_P240DB, + AM_HAL_PDM_GAIN_P225DB = PDM_PCFG_PGALEFT_P225DB, + AM_HAL_PDM_GAIN_P210DB = PDM_PCFG_PGALEFT_P210DB, + AM_HAL_PDM_GAIN_P195DB = PDM_PCFG_PGALEFT_P195DB, + AM_HAL_PDM_GAIN_P180DB = PDM_PCFG_PGALEFT_P180DB, + AM_HAL_PDM_GAIN_P165DB = PDM_PCFG_PGALEFT_P165DB, + AM_HAL_PDM_GAIN_P150DB = PDM_PCFG_PGALEFT_P150DB, + AM_HAL_PDM_GAIN_P135DB = PDM_PCFG_PGALEFT_P135DB, + AM_HAL_PDM_GAIN_P120DB = PDM_PCFG_PGALEFT_P120DB, + AM_HAL_PDM_GAIN_P105DB = PDM_PCFG_PGALEFT_P105DB, + AM_HAL_PDM_GAIN_P90DB = PDM_PCFG_PGALEFT_P90DB, + AM_HAL_PDM_GAIN_P75DB = PDM_PCFG_PGALEFT_P75DB, + AM_HAL_PDM_GAIN_P60DB = PDM_PCFG_PGALEFT_P60DB, + AM_HAL_PDM_GAIN_P45DB = PDM_PCFG_PGALEFT_P45DB, + AM_HAL_PDM_GAIN_P30DB = PDM_PCFG_PGALEFT_P30DB, + AM_HAL_PDM_GAIN_P15DB = PDM_PCFG_PGALEFT_P15DB, + AM_HAL_PDM_GAIN_0DB = PDM_PCFG_PGALEFT_0DB, + AM_HAL_PDM_GAIN_M15DB = PDM_PCFG_PGALEFT_M15DB, + AM_HAL_PDM_GAIN_M300DB = PDM_PCFG_PGALEFT_M300DB, + AM_HAL_PDM_GAIN_M45DB = PDM_PCFG_PGALEFT_M45DB, + AM_HAL_PDM_GAIN_M60DB = PDM_PCFG_PGALEFT_M60DB, +} +am_hal_pdm_gain_e; + +//***************************************************************************** +// +// Clock Source selection. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_PDM_INTERNAL_CLK = PDM_VCFG_SELAP_INTERNAL, + AM_HAL_PDM_I2S_CLK = PDM_VCFG_SELAP_I2S, +} +am_hal_pdm_clksrc_e; + +//***************************************************************************** +// +// PDM internal clock speed selection. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_PDM_CLK_DISABLE = PDM_VCFG_PDMCLKSEL_DISABLE, + AM_HAL_PDM_CLK_12MHZ = PDM_VCFG_PDMCLKSEL_12MHz, + AM_HAL_PDM_CLK_6MHZ = PDM_VCFG_PDMCLKSEL_6MHz, + AM_HAL_PDM_CLK_3MHZ = PDM_VCFG_PDMCLKSEL_3MHz, + AM_HAL_PDM_CLK_1_5MHZ = PDM_VCFG_PDMCLKSEL_1_5MHz, + AM_HAL_PDM_CLK_750KHZ = PDM_VCFG_PDMCLKSEL_750KHz, + AM_HAL_PDM_CLK_375KHZ = PDM_VCFG_PDMCLKSEL_375KHz, + AM_HAL_PDM_CLK_187KHZ = PDM_VCFG_PDMCLKSEL_187KHz, +} +am_hal_pdm_clkspd_e; + +//***************************************************************************** +// +// PDM clock divider setting. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_PDM_MCLKDIV_4 = PDM_PCFG_MCLKDIV_MCKDIV4, + AM_HAL_PDM_MCLKDIV_3 = PDM_PCFG_MCLKDIV_MCKDIV3, + AM_HAL_PDM_MCLKDIV_2 = PDM_PCFG_MCLKDIV_MCKDIV2, + AM_HAL_PDM_MCLKDIV_1 = PDM_PCFG_MCLKDIV_MCKDIV1, +} +am_hal_pdm_mclkdiv_e; + +//***************************************************************************** +// +// PCM Channel Select. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_PDM_CHANNEL_LEFT = PDM_VCFG_CHSET_LEFT, + AM_HAL_PDM_CHANNEL_RIGHT = PDM_VCFG_CHSET_RIGHT, + AM_HAL_PDM_CHANNEL_STEREO = PDM_VCFG_CHSET_STEREO, +} +am_hal_pdm_chset_e; + +//***************************************************************************** +// +// PDM power state settings. +// +//***************************************************************************** +#define AM_HAL_PDM_POWER_ON AM_HAL_SYSCTRL_WAKE +#define AM_HAL_PDM_POWER_OFF AM_HAL_SYSCTRL_NORMALSLEEP + +//***************************************************************************** +// +// PDM interrupts. +// +//***************************************************************************** +#define AM_HAL_PDM_INT_DERR PDM_INTSTAT_DERR_Msk +#define AM_HAL_PDM_INT_DCMP PDM_INTSTAT_DCMP_Msk +#define AM_HAL_PDM_INT_UNDFL PDM_INTSTAT_UNDFL_Msk +#define AM_HAL_PDM_INT_OVF PDM_INTSTAT_OVF_Msk +#define AM_HAL_PDM_INT_THR PDM_INTSTAT_THR_Msk + +//***************************************************************************** +// +// Configuration structure for the PDM +// +//***************************************************************************** +typedef struct +{ + // Clock + am_hal_pdm_mclkdiv_e eClkDivider; + + // Gain + am_hal_pdm_gain_e eLeftGain; + am_hal_pdm_gain_e eRightGain; + + // Decimation Rate + uint32_t ui32DecimationRate; + + // Filters + bool bHighPassEnable; + uint32_t ui32HighPassCutoff; + + // PDMCLKSEL + am_hal_pdm_clkspd_e ePDMClkSpeed; + + // BCLKINV + bool bInvertI2SBCLK; + + // SELAP + am_hal_pdm_clksrc_e ePDMClkSource; + + // DMICKDEL + bool bPDMSampleDelay; + + // PCMPACK + bool bDataPacking; + + // CHSET + am_hal_pdm_chset_e ePCMChannels; + + uint32_t ui32GainChangeDelay; + + bool bI2SEnable; + + bool bSoftMute; + + bool bLRSwap; +} +am_hal_pdm_config_t; + +//***************************************************************************** +// +// DMA transfer structure +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32TargetAddr; + uint32_t ui32TotalCount; +} +am_hal_pdm_transfer_t; + +// Init/De-init. +extern uint32_t am_hal_pdm_initialize(uint32_t ui32Module, void **ppHandle); +extern uint32_t am_hal_pdm_deinitialize(void *pHandle); + +// Power +extern uint32_t am_hal_pdm_power_control(void *pHandle, am_hal_sysctrl_power_state_e ePowerState, bool bRetainState); + +// Config +extern uint32_t am_hal_pdm_configure(void *pHandle, am_hal_pdm_config_t *psConfig); + +// Enable/Disable +extern uint32_t am_hal_pdm_enable(void *pHandle); +extern uint32_t am_hal_pdm_disable(void *pHandle); + +// Gather PDM data. +extern uint32_t am_hal_pdm_dma_start(void *pHandle, am_hal_pdm_transfer_t *pDmaCfg); + +// Flush the PDM FIFO. +extern uint32_t am_hal_pdm_fifo_flush(void *pHandle); + +// I2S Passthrough +extern uint32_t am_hal_pdm_i2s_enable(void *pHandle); +extern uint32_t am_hal_pdm_i2s_disable(void *pHandle); + +// Interrupts. +extern uint32_t am_hal_pdm_interrupt_enable(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_pdm_interrupt_disable(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_pdm_interrupt_clear(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_pdm_interrupt_status_get(void *pHandle, uint32_t *pui32Status, bool bEnabledOnly); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_PDM_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pin.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pin.h new file mode 100644 index 0000000..eb158b8 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pin.h @@ -0,0 +1,495 @@ +//***************************************************************************** +// +// am_hal_pin.h +//! @file +//! @brief Macros for configuring specific pins. +//! +//! @addtogroup pin3 PIN definitions for Apollo3. +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_PIN_H +#define AM_HAL_PIN_H + +//***************************************************************************** +// +// Pin definition macros. +// +//***************************************************************************** +#define AM_HAL_PIN_0_SLSCL (0) +#define AM_HAL_PIN_0_SLSCK (1) +#define AM_HAL_PIN_0_CLKOUT (2) +#define AM_HAL_PIN_0_GPIO (3) +#define AM_HAL_PIN_0_MSPI4 (5) +#define AM_HAL_PIN_0_NCE0 (7) + +#define AM_HAL_PIN_1_SLSDAWIR3 (0) +#define AM_HAL_PIN_1_SLMOSI (1) +#define AM_HAL_PIN_1_UART0TX (2) +#define AM_HAL_PIN_1_GPIO (3) +#define AM_HAL_PIN_1_MSPI5 (5) +#define AM_HAL_PIN_1_NCE1 (7) + +#define AM_HAL_PIN_2_UART1RX (0) +#define AM_HAL_PIN_2_SLMISO (1) +#define AM_HAL_PIN_2_UART0RX (2) +#define AM_HAL_PIN_2_GPIO (3) +#define AM_HAL_PIN_2_MSPI6 (5) +#define AM_HAL_PIN_2_NCE2 (7) + +#define AM_HAL_PIN_3_UART0RTS (0) +#define AM_HAL_PIN_3_SLnCE (1) +#define AM_HAL_PIN_3_NCE3 (2) +#define AM_HAL_PIN_3_GPIO (3) +#define AM_HAL_PIN_3_MSPI7 (5) +#define AM_HAL_PIN_3_TRIG1 (6) +#define AM_HAL_PIN_3_I2S_WCLK (7) +#define AM_HAL_PIN_3_PSOURCE (3) + +#define AM_HAL_PIN_4_UART0CTS (0) +#define AM_HAL_PIN_4_SLINT (1) +#define AM_HAL_PIN_4_NCE4 (2) +#define AM_HAL_PIN_4_GPIO (3) +#define AM_HAL_PIN_4_UART1RX (5) +#define AM_HAL_PIN_4_CTIM17 (6) +#define AM_HAL_PIN_4_MSPI2 (7) + +#define AM_HAL_PIN_5_M0SCL (0) +#define AM_HAL_PIN_5_M0SCK (1) +#define AM_HAL_PIN_5_UART0RTS (2) +#define AM_HAL_PIN_5_GPIO (3) +#define AM_HAL_PIN_5_EXTHFA (5) +#define AM_HAL_PIN_5_CTIM8 (7) + +#define AM_HAL_PIN_6_M0SDAWIR3 (0) +#define AM_HAL_PIN_6_M0MISO (1) +#define AM_HAL_PIN_6_UART0CTS (2) +#define AM_HAL_PIN_6_GPIO (3) +#define AM_HAL_PIN_6_CTIM10 (5) +#define AM_HAL_PIN_6_I2S_DAT (7) + +#define AM_HAL_PIN_7_NCE7 (0) +#define AM_HAL_PIN_7_M0MOSI (1) +#define AM_HAL_PIN_7_CLKOUT (2) +#define AM_HAL_PIN_7_GPIO (3) +#define AM_HAL_PIN_7_TRIG0 (4) +#define AM_HAL_PIN_7_UART0TX (5) +#define AM_HAL_PIN_7_CTIM19 (7) + +#define AM_HAL_PIN_8_M1SCL (0) +#define AM_HAL_PIN_8_M1SCK (1) +#define AM_HAL_PIN_8_NCE8 (2) +#define AM_HAL_PIN_8_GPIO (3) +#define AM_HAL_PIN_8_SCCCLK (4) +#define AM_HAL_PIN_8_UART1TX (6) + +#define AM_HAL_PIN_9_M1SDAWIR3 (0) +#define AM_HAL_PIN_9_M1MISO (1) +#define AM_HAL_PIN_9_NCE9 (2) +#define AM_HAL_PIN_9_GPIO (3) +#define AM_HAL_PIN_9_SCCIO (4) +#define AM_HAL_PIN_9_UART1RX (6) + +#define AM_HAL_PIN_10_UART1TX (0) +#define AM_HAL_PIN_10_M1MOSI (1) +#define AM_HAL_PIN_10_NCE10 (2) +#define AM_HAL_PIN_10_GPIO (3) +#define AM_HAL_PIN_10_PDMCLK (4) +#define AM_HAL_PIN_10_UART1RTS (5) + +#define AM_HAL_PIN_11_ADCSE2 (0) +#define AM_HAL_PIN_11_NCE11 (1) +#define AM_HAL_PIN_11_CTIM31 (2) +#define AM_HAL_PIN_11_GPIO (3) +#define AM_HAL_PIN_11_SLINT (4) +#define AM_HAL_PIN_11_UART1CTS (5) +#define AM_HAL_PIN_11_UART0RX (6) +#define AM_HAL_PIN_11_PDMDATA (7) + +#define AM_HAL_PIN_12_ADCD0NSE9 (0) +#define AM_HAL_PIN_12_NCE12 (1) +#define AM_HAL_PIN_12_CTIM0 (2) +#define AM_HAL_PIN_12_GPIO (3) +#define AM_HAL_PIN_12_SLnCE (4) +#define AM_HAL_PIN_12_PDMCLK (5) +#define AM_HAL_PIN_12_UART0CTS (6) +#define AM_HAL_PIN_12_UART1TX (7) + +#define AM_HAL_PIN_13_ADCD0PSE8 (0) +#define AM_HAL_PIN_13_NCE13 (1) +#define AM_HAL_PIN_13_CTIM2 (2) +#define AM_HAL_PIN_13_GPIO (3) +#define AM_HAL_PIN_13_I2SBCLK (4) +#define AM_HAL_PIN_13_EXTHFB (5) +#define AM_HAL_PIN_13_UART0RTS (6) +#define AM_HAL_PIN_13_UART1RX (7) + +#define AM_HAL_PIN_14_ADCD1P (0) +#define AM_HAL_PIN_14_NCE14 (1) +#define AM_HAL_PIN_14_UART1TX (2) +#define AM_HAL_PIN_14_GPIO (3) +#define AM_HAL_PIN_14_PDMCLK (4) +#define AM_HAL_PIN_14_EXTHFS (5) +#define AM_HAL_PIN_14_SWDCK (6) +#define AM_HAL_PIN_14_32KHZXT (7) + +#define AM_HAL_PIN_15_ADCD1N (0) +#define AM_HAL_PIN_15_NCE15 (1) +#define AM_HAL_PIN_15_UART1RX (2) +#define AM_HAL_PIN_15_GPIO (3) +#define AM_HAL_PIN_15_PDMDATA (4) +#define AM_HAL_PIN_15_EXTXT (5) +#define AM_HAL_PIN_15_SWDIO (6) +#define AM_HAL_PIN_15_SWO (7) + +#define AM_HAL_PIN_16_ADCSE0 (0) +#define AM_HAL_PIN_16_NCE16 (1) +#define AM_HAL_PIN_16_TRIG0 (2) +#define AM_HAL_PIN_16_GPIO (3) +#define AM_HAL_PIN_16_SCCRST (4) +#define AM_HAL_PIN_16_CMPIN0 (5) +#define AM_HAL_PIN_16_UART0TX (6) +#define AM_HAL_PIN_16_UART1RTS (7) + +#define AM_HAL_PIN_17_CMPRF1 (0) +#define AM_HAL_PIN_17_NCE17 (1) +#define AM_HAL_PIN_17_TRIG1 (2) +#define AM_HAL_PIN_17_GPIO (3) +#define AM_HAL_PIN_17_SCCCLK (4) +#define AM_HAL_PIN_17_UART0RX (6) +#define AM_HAL_PIN_17_UART1CTS (7) + +#define AM_HAL_PIN_18_CMPIN1 (0) +#define AM_HAL_PIN_18_NCE18 (1) +#define AM_HAL_PIN_18_CTIM4 (2) +#define AM_HAL_PIN_18_GPIO (3) +#define AM_HAL_PIN_18_UART0RTS (4) +#define AM_HAL_PIN_18_ANATEST2 (5) +#define AM_HAL_PIN_18_UART1TX (6) +#define AM_HAL_PIN_18_SCCIO (7) + +#define AM_HAL_PIN_19_CMPRF0 (0) +#define AM_HAL_PIN_19_NCE19 (1) +#define AM_HAL_PIN_19_CTIM6 (2) +#define AM_HAL_PIN_19_GPIO (3) +#define AM_HAL_PIN_19_SCCCLK (4) +#define AM_HAL_PIN_19_ANATEST1 (5) +#define AM_HAL_PIN_19_UART1RX (6) +#define AM_HAL_PIN_19_I2SBCLK (7) + +#define AM_HAL_PIN_20_SWDCK (0) +#define AM_HAL_PIN_20_NCE20 (1) +#define AM_HAL_PIN_20_GPIO (3) +#define AM_HAL_PIN_20_UART0TX (4) +#define AM_HAL_PIN_20_UART1TX (5) +#define AM_HAL_PIN_20_I2SBCLK (6) +#define AM_HAL_PIN_20_UART1RTS (7) + +#define AM_HAL_PIN_21_SWDIO (0) +#define AM_HAL_PIN_21_NCE21 (1) +#define AM_HAL_PIN_21_GPIO (3) +#define AM_HAL_PIN_21_UART0RX (4) +#define AM_HAL_PIN_21_UART1RX (5) +#define AM_HAL_PIN_21_I2SBCLK (6) +#define AM_HAL_PIN_21_UART1CTS (7) + +#define AM_HAL_PIN_22_UART0TX (0) +#define AM_HAL_PIN_22_NCE22 (1) +#define AM_HAL_PIN_22_CTIM12 (2) +#define AM_HAL_PIN_22_GPIO (3) +#define AM_HAL_PIN_22_PDMCLK (4) +#define AM_HAL_PIN_22_EXTLF (5) +#define AM_HAL_PIN_22_MSPI0 (6) +#define AM_HAL_PIN_22_SWO (7) + +#define AM_HAL_PIN_23_UART0RX (0) +#define AM_HAL_PIN_23_NCE23 (1) +#define AM_HAL_PIN_23_CTIM14 (2) +#define AM_HAL_PIN_23_GPIO (3) +#define AM_HAL_PIN_23_I2SWCLK (4) +#define AM_HAL_PIN_23_CMPOUT (5) +#define AM_HAL_PIN_23_MSPI13 (6) +#define AM_HAL_PIN_23_EXTXT (7) + +#define AM_HAL_PIN_24_UART1TX (0) +#define AM_HAL_PIN_24_NCE24 (1) +#define AM_HAL_PIN_24_MSPI8 (2) +#define AM_HAL_PIN_24_GPIO (3) +#define AM_HAL_PIN_24_UART0CTS (4) +#define AM_HAL_PIN_24_CTIM21 (5) +#define AM_HAL_PIN_24_32KHZXT (6) +#define AM_HAL_PIN_24_SWO (7) + +#define AM_HAL_PIN_25_UART1RX (0) +#define AM_HAL_PIN_25_NCE25 (1) +#define AM_HAL_PIN_25_CTIM1 (2) +#define AM_HAL_PIN_25_GPIO (3) +#define AM_HAL_PIN_25_M2SDAWIR3 (4) +#define AM_HAL_PIN_25_M2MISO (5) + +#define AM_HAL_PIN_26_EXTHF (0) +#define AM_HAL_PIN_26_NCE26 (1) +#define AM_HAL_PIN_26_CTIM3 (2) +#define AM_HAL_PIN_26_GPIO (3) +#define AM_HAL_PIN_26_SCCRST (4) +#define AM_HAL_PIN_26_MSPI1 (5) +#define AM_HAL_PIN_26_UART0TX (6) +#define AM_HAL_PIN_26_UART1CTS (7) + +#define AM_HAL_PIN_27_UART0RX (0) +#define AM_HAL_PIN_27_NCE27 (1) +#define AM_HAL_PIN_27_CTIM5 (2) +#define AM_HAL_PIN_27_GPIO (3) +#define AM_HAL_PIN_27_M2SCL (4) +#define AM_HAL_PIN_27_M2SCK (5) + +#define AM_HAL_PIN_28_I2SWCLK (0) +#define AM_HAL_PIN_28_NCE28 (1) +#define AM_HAL_PIN_28_CTIM7 (2) +#define AM_HAL_PIN_28_GPIO (3) +#define AM_HAL_PIN_28_M2MOSI (5) +#define AM_HAL_PIN_28_UART0TX (6) + +#define AM_HAL_PIN_29_ADCSE1 (0) +#define AM_HAL_PIN_29_NCE29 (1) +#define AM_HAL_PIN_29_CTIM9 (2) +#define AM_HAL_PIN_29_GPIO (3) +#define AM_HAL_PIN_29_UART0CTS (4) +#define AM_HAL_PIN_29_UART1CTS (5) +#define AM_HAL_PIN_29_UART0RX (6) +#define AM_HAL_PIN_29_PDMDATA (7) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_30_ANATEST1 (0) +#define AM_HAL_PIN_30_NCE30 (1) +#define AM_HAL_PIN_30_CTIM11 (2) +#define AM_HAL_PIN_30_GPIO (3) +#define AM_HAL_PIN_30_UART0TX (4) +#define AM_HAL_PIN_30_UART1RTS (5) +#define AM_HAL_PIN_30_I2SDAT (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_31_ADCSE3 (0) +#define AM_HAL_PIN_31_NCE31 (1) +#define AM_HAL_PIN_31_CTIM13 (2) +#define AM_HAL_PIN_31_GPIO (3) +#define AM_HAL_PIN_31_UART0RX (4) +#define AM_HAL_PIN_31_SCCCLK (5) +#define AM_HAL_PIN_31_UART1RTS (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_32_ADCSE4 (0) +#define AM_HAL_PIN_32_NCE32 (1) +#define AM_HAL_PIN_32_CTIM15 (2) +#define AM_HAL_PIN_32_GPIO (3) +#define AM_HAL_PIN_32_SCCIO (4) +#define AM_HAL_PIN_32_EXTLF (5) +#define AM_HAL_PIN_32_UART1CTS (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_33_ADCSE5 (0) +#define AM_HAL_PIN_33_NCE33 (1) +#define AM_HAL_PIN_33_32KHZXT (2) +#define AM_HAL_PIN_33_GPIO (3) +#define AM_HAL_PIN_33_UART0CTS (5) +#define AM_HAL_PIN_33_CTIM23 (6) +#define AM_HAL_PIN_33_SWO (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_34_ADCSE6 (0) +#define AM_HAL_PIN_34_NCE34 (1) +#define AM_HAL_PIN_34_UART1RTS (2) +#define AM_HAL_PIN_34_GPIO (3) +#define AM_HAL_PIN_34_CMPRF2 (4) +#define AM_HAL_PIN_34_UART0RTS (5) +#define AM_HAL_PIN_34_UART0RX (6) +#define AM_HAL_PIN_34_PDMDATA (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_35_ADCSE7 (0) +#define AM_HAL_PIN_35_NCE35 (1) +#define AM_HAL_PIN_35_UART1TX (2) +#define AM_HAL_PIN_35_GPIO (3) +#define AM_HAL_PIN_35_I2SDAT (4) +#define AM_HAL_PIN_35_CTIM27 (5) +#define AM_HAL_PIN_35_UART0RTS (6) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_36_TRIG1 (0) +#define AM_HAL_PIN_36_NCE36 (1) +#define AM_HAL_PIN_36_UART1RX (2) +#define AM_HAL_PIN_36_GPIO (3) +#define AM_HAL_PIN_36_32KHZXT (4) +#define AM_HAL_PIN_36_UART1CTS (5) +#define AM_HAL_PIN_36_UART0CTS (6) +#define AM_HAL_PIN_36_PDMDATA (7) +#define AM_HAL_PIN_36_PSOURCE (3) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_37_TRIG2 (0) +#define AM_HAL_PIN_37_NCE37 (1) +#define AM_HAL_PIN_37_UART0RTS (2) +#define AM_HAL_PIN_37_GPIO (3) +#define AM_HAL_PIN_37_SCCIO (4) +#define AM_HAL_PIN_37_UART1TX (5) +#define AM_HAL_PIN_37_PDMCLK (6) +#define AM_HAL_PIN_37_CTIM29 (7) +#define AM_HAL_PIN_37_PSINK (3) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_38_TRIG3 (0) +#define AM_HAL_PIN_38_NCE38 (1) +#define AM_HAL_PIN_38_UART0CTS (2) +#define AM_HAL_PIN_38_GPIO (3) +#define AM_HAL_PIN_38_M3MOSI (5) +#define AM_HAL_PIN_38_UART1RX (6) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_39_UART0TX (0) +#define AM_HAL_PIN_39_UART1TX (1) +#define AM_HAL_PIN_39_CTIM25 (2) +#define AM_HAL_PIN_39_GPIO (3) +#define AM_HAL_PIN_39_M4SCL (4) +#define AM_HAL_PIN_39_M4SCK (5) + +#define AM_HAL_PIN_40_UART0RX (0) +#define AM_HAL_PIN_40_UART1RX (1) +#define AM_HAL_PIN_40_TRIG0 (2) +#define AM_HAL_PIN_40_GPIO (3) +#define AM_HAL_PIN_40_M4SDAWIR3 (4) +#define AM_HAL_PIN_40_M4MISO (5) + +#define AM_HAL_PIN_41_NCE41 (0) +#define AM_HAL_PIN_41_SWO (2) +#define AM_HAL_PIN_41_GPIO (3) +#define AM_HAL_PIN_41_I2SWCLK (4) +#define AM_HAL_PIN_41_UART1RTS (5) +#define AM_HAL_PIN_41_UART0TX (6) +#define AM_HAL_PIN_41_UART0RTS (7) +#define AM_HAL_PIN_41_PSINK (3) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_42_UART1TX (0) +#define AM_HAL_PIN_42_NCE42 (1) +#define AM_HAL_PIN_42_CTIM16 (2) +#define AM_HAL_PIN_42_GPIO (3) +#define AM_HAL_PIN_42_M3SCL (4) +#define AM_HAL_PIN_42_M3SCK (5) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_43_UART1RX (0) +#define AM_HAL_PIN_43_NCE43 (1) +#define AM_HAL_PIN_43_CTIM18 (2) +#define AM_HAL_PIN_43_GPIO (3) +#define AM_HAL_PIN_43_M3SDAWIR3 (4) +#define AM_HAL_PIN_43_M3MISO (5) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_44_UART1RTS (0) +#define AM_HAL_PIN_44_NCE44 (1) +#define AM_HAL_PIN_44_CTIM20 (2) +#define AM_HAL_PIN_44_GPIO (3) +#define AM_HAL_PIN_44_M4MOSI (5) +#define AM_HAL_PIN_44_UART0TX (6) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_45_UART1CTS (0) +#define AM_HAL_PIN_45_NCE45 (1) +#define AM_HAL_PIN_45_CTIM22 (2) +#define AM_HAL_PIN_45_GPIO (3) +#define AM_HAL_PIN_45_I2SDAT (4) +#define AM_HAL_PIN_45_PDMDATA (5) +#define AM_HAL_PIN_45_UART0RX (6) +#define AM_HAL_PIN_45_SWO (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_46_32KHZXT (0) +#define AM_HAL_PIN_46_NCE46 (1) +#define AM_HAL_PIN_46_CTIM24 (2) +#define AM_HAL_PIN_46_GPIO (3) +#define AM_HAL_PIN_46_SCCRST (4) +#define AM_HAL_PIN_46_PDMCLK (5) +#define AM_HAL_PIN_46_UART1TX (6) +#define AM_HAL_PIN_46_SWO (7) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_47_32KHZXT (0) +#define AM_HAL_PIN_47_NCE47 (1) +#define AM_HAL_PIN_47_CTIM26 (2) +#define AM_HAL_PIN_47_GPIO (3) +#define AM_HAL_PIN_47_M5MOSI (5) +#define AM_HAL_PIN_47_UART1RX (6) + +#define AM_HAL_PIN_48_UART0TX (0) +#define AM_HAL_PIN_48_NCE48 (1) +#define AM_HAL_PIN_48_CTIM28 (2) +#define AM_HAL_PIN_48_GPIO (3) +#define AM_HAL_PIN_48_M5SCL (4) +#define AM_HAL_PIN_48_M5SCK (5) + +#define AM_HAL_PIN_49_UART0RX (0) +#define AM_HAL_PIN_49_NCE49 (1) +#define AM_HAL_PIN_49_CTIM30 (2) +#define AM_HAL_PIN_49_GPIO (3) +#define AM_HAL_PIN_49_M5SDAWIR3 (4) +#define AM_HAL_PIN_49_M5MISO (5) + +#endif // AM_HAL_PIN_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.c new file mode 100644 index 0000000..019a964 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.c @@ -0,0 +1,638 @@ +//***************************************************************************** +// +// am_hal_pwrctrl.c +//! @file +//! +//! @brief Functions for enabling and disabling power domains. +//! +//! @addtogroup pwrctrl3 Power Control +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +// +// Maximum number of checks to memory power status before declaring error. +// +#define AM_HAL_PWRCTRL_MAX_WFE 20 + +// +// Define the peripheral control structure. +// +const struct +{ + uint32_t ui32PeriphEnable; + uint32_t ui32PeriphStatus; + uint32_t ui32PeriphEvent; +} +am_hal_pwrctrl_peripheral_control[AM_HAL_PWRCTRL_PERIPH_MAX] = +{ + {0, 0, 0}, // AM_HAL_PWRCTRL_PERIPH_NONE + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOS, PWRCTRL_DEVPWREN_PWRIOS_EN), + PWRCTRL_DEVPWRSTATUS_HCPA_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOS + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM0, PWRCTRL_DEVPWREN_PWRIOM0_EN), + PWRCTRL_DEVPWRSTATUS_HCPB_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPBEVEN, PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM0 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM1, PWRCTRL_DEVPWREN_PWRIOM1_EN), + PWRCTRL_DEVPWRSTATUS_HCPB_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPBEVEN, PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM1 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM2, PWRCTRL_DEVPWREN_PWRIOM2_EN), + PWRCTRL_DEVPWRSTATUS_HCPB_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPBEVEN, PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM2 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM3, PWRCTRL_DEVPWREN_PWRIOM3_EN), + PWRCTRL_DEVPWRSTATUS_HCPC_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPCEVEN, PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM3 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM4, PWRCTRL_DEVPWREN_PWRIOM4_EN), + PWRCTRL_DEVPWRSTATUS_HCPC_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPCEVEN, PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM4 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM5, PWRCTRL_DEVPWREN_PWRIOM5_EN), + PWRCTRL_DEVPWRSTATUS_HCPC_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPCEVEN, PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM5 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART0, PWRCTRL_DEVPWREN_PWRUART0_EN), + PWRCTRL_DEVPWRSTATUS_HCPA_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_UART0 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART1, PWRCTRL_DEVPWREN_PWRUART1_EN), + PWRCTRL_DEVPWRSTATUS_HCPA_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_UART1 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRADC, PWRCTRL_DEVPWREN_PWRADC_EN), + PWRCTRL_DEVPWRSTATUS_PWRADC_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_ADCEVEN, PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_ADC + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRSCARD, PWRCTRL_DEVPWREN_PWRSCARD_EN), + PWRCTRL_DEVPWRSTATUS_HCPA_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_SCARD + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI, PWRCTRL_DEVPWREN_PWRMSPI_EN), + PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_MSPIEVEN, PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_MSPI + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRPDM, PWRCTRL_DEVPWREN_PWRPDM_EN), + PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_PDMEVEN, PWRCTRL_DEVPWREVENTEN_PDMEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_PDM + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRBLEL, PWRCTRL_DEVPWREN_PWRBLEL_EN), + PWRCTRL_DEVPWRSTATUS_BLEL_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_BLELEVEN, PWRCTRL_DEVPWREVENTEN_BLELEVEN_EN)} // AM_HAL_PWRCTRL_PERIPH_BLEL +}; + + +// +// Define the memory control structure. +// +const struct +{ + uint32_t ui32MemoryEnable; + uint32_t ui32MemoryStatus; + uint32_t ui32MemoryEvent; + uint32_t ui32MemoryMask; + uint32_t ui32StatusMask; + uint32_t ui32PwdSlpEnable; +} +am_hal_pwrctrl_memory_control[AM_HAL_PWRCTRL_MEM_MAX] = +{ + {0, 0, 0, 0, 0, 0}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_8K_DTCM, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_8K_DTCM, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_8K_DTCM}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_32K_DTCM, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_32K_DTCM, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_32K_DTCM}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_64K_DTCM, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_96K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_96K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_96K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_128K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_160K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_160K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_160K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_192K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_224K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_224K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_224K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_256K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_288K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_288K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_288K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_288K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_320K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_352K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_352K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_352K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_352K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_384K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K}, + {AM_HAL_PWRCTRL_MEMEN_FLASH_512K, + AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_512K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_512K, + AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK, + AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_512K}, + {AM_HAL_PWRCTRL_MEMEN_FLASH_1M, + AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M, + AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M, + AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK, + AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_1M}, + {AM_HAL_PWRCTRL_MEMEN_CACHE, + 0, + AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE, + AM_HAL_PWRCTRL_MEM_REGION_CACHE_MASK, + 0, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE}, + {AM_HAL_PWRCTRL_MEMEN_ALL, + AM_HAL_PWRCTRL_PWRONSTATUS_ALL, + AM_HAL_PWRCTRL_MEMPWREVENTEN_ALL, + AM_HAL_PWRCTRL_MEM_REGION_ALL_MASK, + AM_HAL_PWRCTRL_MEM_REGION_ALT_ALL_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_ALL} +}; + +// **************************************************************************** +// +// am_hal_pwrctrl_periph_enable() +// Enable power for a peripheral. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral) +{ + + + // + // Enable power control for the given device. + // + AM_CRITICAL_BEGIN + PWRCTRL->DEVPWREN |= am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnable; + AM_CRITICAL_END + + + + + for (uint32_t wait_usecs = 0; wait_usecs < AM_HAL_PWRCTRL_MAX_WFE; wait_usecs += 10) + { + am_hal_flash_delay(FLASH_CYCLES_US(10)); + + if ( (PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) > 0) + { + break; + } + } + + // + // Check the device status. + // + if ( (PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) > 0 ) + { + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_FAIL; + } + +} + +// **************************************************************************** +// +// am_hal_pwrctrl_periph_disable() +// Disable power for a peripheral. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_periph_disable(am_hal_pwrctrl_periph_e ePeripheral) +{ + + // + // Disable power domain for the given device. + // + AM_CRITICAL_BEGIN + PWRCTRL->DEVPWREN &= ~am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnable; + AM_CRITICAL_END + + + for (uint32_t wait_usecs = 0; wait_usecs < AM_HAL_PWRCTRL_MAX_WFE; wait_usecs += 10) + { + am_hal_flash_delay(FLASH_CYCLES_US(10)); + + if ( (PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) == 0 ) + { + break; + } + } + + // + // Check the device status. + // + if ( ( PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) == 0 ) + { + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_FAIL; + } +} + +//***************************************************************************** +// +//! @brief Determine whether a peripheral is currently enabled. +//! +//! @param ePeripheral - The peripheral to enable. +//! @param pui32Enabled - Pointer to a ui32 that will return as 1 or 0. +//! +//! This function determines to the caller whether a given peripheral is +//! currently enabled or disabled. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_pwrctrl_periph_enabled(am_hal_pwrctrl_periph_e ePeripheral, + uint32_t *pui32Enabled) +{ + uint32_t ui32Mask = 0; + uint32_t ui32Enabled = 0; + + if ( pui32Enabled == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + switch ( ePeripheral ) + { + case AM_HAL_PWRCTRL_PERIPH_NONE: + case AM_HAL_PWRCTRL_PERIPH_SCARD: + break; + case AM_HAL_PWRCTRL_PERIPH_IOS: + case AM_HAL_PWRCTRL_PERIPH_UART0: + case AM_HAL_PWRCTRL_PERIPH_UART1: + ui32Mask = PWRCTRL_DEVPWRSTATUS_HCPA_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_IOM0: + case AM_HAL_PWRCTRL_PERIPH_IOM1: + case AM_HAL_PWRCTRL_PERIPH_IOM2: + ui32Mask = PWRCTRL_DEVPWRSTATUS_HCPB_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_IOM3: + case AM_HAL_PWRCTRL_PERIPH_IOM4: + case AM_HAL_PWRCTRL_PERIPH_IOM5: + ui32Mask = PWRCTRL_DEVPWRSTATUS_HCPC_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_ADC: + ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRADC_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_MSPI: + ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_PDM: + ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_BLEL: + ui32Mask = PWRCTRL_DEVPWRSTATUS_BLEL_Msk; + break; + default: + return AM_HAL_STATUS_FAIL; + } + + if ( ui32Mask != 0 ) + { + ui32Enabled = PWRCTRL->DEVPWRSTATUS & ui32Mask ? 1 : 0; + } + + *pui32Enabled = ui32Enabled; + + return AM_HAL_STATUS_SUCCESS; +} + + + +// **************************************************************************** +// +// am_hal_pwrctrl_memory_enable() +// Enable a configuration of memory. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_memory_enable(am_hal_pwrctrl_mem_e eMemConfig) +{ + uint32_t ui32MemEnMask, ui32MemDisMask, ui32MemRegionMask, ui32MemStatusMask; + + ui32MemEnMask = am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryEnable; + ui32MemDisMask = ~am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryEnable; + ui32MemRegionMask = am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryMask; + ui32MemStatusMask = am_hal_pwrctrl_memory_control[eMemConfig].ui32StatusMask; + + // + // Disable unneeded memory. If nothing to be disabled, skip to save time. + // + // Note that a deliberate disable step using a disable mask is taken here + // for 2 reasons: 1) To only affect the specified type of memory, and 2) + // To avoid inadvertently disabling any memory currently being depended on. + // + if ( ui32MemDisMask != 0 ) + { + PWRCTRL->MEMPWREN &= + ~(ui32MemDisMask & ui32MemRegionMask) | + (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0) | + _VAL2FLD(PWRCTRL_MEMPWREN_FLASH0, PWRCTRL_MEMPWREN_FLASH0_EN)); + am_hal_flash_delay(FLASH_CYCLES_US(1)); + } + + + // + // Enable the required memory. + // + if ( ui32MemEnMask != 0 ) + { + PWRCTRL->MEMPWREN |= ui32MemEnMask; + + for (uint32_t wait_usecs = 0; wait_usecs < AM_HAL_PWRCTRL_MAX_WFE; wait_usecs += 10) + { + am_hal_flash_delay(FLASH_CYCLES_US(10)); + + if ( (PWRCTRL->MEMPWRSTATUS & ui32MemStatusMask) == + am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryStatus ) + { + break; + } + } + } + + // + // Return status based on whether the power control memory status has reached the desired state. + // + if ( ( PWRCTRL->MEMPWRSTATUS & ui32MemStatusMask) == + am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryStatus ) + { + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_FAIL; + } +} + +// **************************************************************************** +// +// am_hal_pwrctrl_memory_deepsleep_powerdown() +// Power down respective memory. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_memory_deepsleep_powerdown(am_hal_pwrctrl_mem_e eMemConfig) +{ + if ( eMemConfig >= AM_HAL_PWRCTRL_MEM_MAX ) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Power down the required memory. + // + PWRCTRL->MEMPWDINSLEEP |= am_hal_pwrctrl_memory_control[eMemConfig].ui32PwdSlpEnable; + + return AM_HAL_STATUS_SUCCESS; +} + +// **************************************************************************** +// +// am_hal_pwrctrl_memory_deepsleep_retain() +// Apply retention voltage to respective memory. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_memory_deepsleep_retain(am_hal_pwrctrl_mem_e eMemConfig) +{ + if ( eMemConfig >= AM_HAL_PWRCTRL_MEM_MAX ) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Retain the required memory. + // + PWRCTRL->MEMPWDINSLEEP &= ~am_hal_pwrctrl_memory_control[eMemConfig].ui32PwdSlpEnable; + + return AM_HAL_STATUS_SUCCESS; +} + +// **************************************************************************** +// +// am_hal_pwrctrl_low_power_init() +// Initialize system for low power configuration. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_low_power_init(void) +{ + uint32_t ui32Status; + + // + // Take a snapshot of the reset status, if not done already + // + if (!gAmHalResetStatus) + { + gAmHalResetStatus = RSTGEN->STAT; + } + + // + // Software workaround for Errata ERR019. + // + if ((APOLLO3_A1) && (1 == PWRCTRL->SUPPLYSTATUS_b.SIMOBUCKON)) + { + ui32Status = am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_PDM); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + + // + // Adjust the SIMOBUCK LP settings. + // + if (APOLLO3_GE_B0) + { + MCUCTRL->SIMOBUCK2_b.SIMOBUCKCORELPHIGHTONTRIM = 2; + MCUCTRL->SIMOBUCK2_b.SIMOBUCKCORELPLOWTONTRIM = 3; + MCUCTRL->SIMOBUCK3_b.SIMOBUCKCORELPHIGHTOFFTRIM = 5; + MCUCTRL->SIMOBUCK3_b.SIMOBUCKCORELPLOWTOFFTRIM = 2; + MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPHIGHTOFFTRIM = 6; + MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPLOWTOFFTRIM = 1; + MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPHIGHTONTRIM = 3; + MCUCTRL->SIMOBUCK4_b.SIMOBUCKMEMLPLOWTONTRIM = 3; + } + + // + // Adjust the SIMOBUCK Timeout settings. + // + if (APOLLO3_GE_A1) + { + MCUCTRL->SIMOBUCK4_b.SIMOBUCKCOMP2TIMEOUTEN = 0; + } + + // + // Configure cache for low power and performance. + // + am_hal_cachectrl_control(AM_HAL_CACHECTRL_CONTROL_LPMMODE_RECOMMENDED, 0); + + // + // Check if the BLE is already enabled. + // + if ( PWRCTRL->DEVPWRSTATUS_b.BLEL == 0) + { + // + // First request the BLE feature and check that it was available and acknowledged. + // + MCUCTRL->FEATUREENABLE_b.BLEREQ = 1; + ui32Status = am_hal_flash_delay_status_check(10000, + (uint32_t)&MCUCTRL->FEATUREENABLE, + (MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk | + MCUCTRL_FEATUREENABLE_BLEACK_Msk | + MCUCTRL_FEATUREENABLE_BLEREQ_Msk), + (MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk | + MCUCTRL_FEATUREENABLE_BLEACK_Msk | + MCUCTRL_FEATUREENABLE_BLEREQ_Msk), + true); + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return AM_HAL_STATUS_TIMEOUT; + } + + // + // Next, enable the BLE Buck. + // + PWRCTRL->SUPPLYSRC |= _VAL2FLD(PWRCTRL_SUPPLYSRC_BLEBUCKEN, + PWRCTRL_SUPPLYSRC_BLEBUCKEN_EN); + + // + // Allow the buck to go to low power mode in BLE sleep. + // + PWRCTRL->MISC |= _VAL2FLD(PWRCTRL_MISC_MEMVRLPBLE, + PWRCTRL_MISC_MEMVRLPBLE_EN); + + // + // Check for Apollo3 A0 Silicon. + // + if ( APOLLO3_A0 ) + { + // Disable SIMO Buck clkdiv because if ble is out of reset then the same bit divides the simobuck clk too aggressively. + MCUCTRL->SIMOBUCK4_b.SIMOBUCKCLKDIVSEL = 0x0; + MCUCTRL->BLEBUCK2_b.BLEBUCKTONHITRIM = 0xF; + MCUCTRL->BLEBUCK2_b.BLEBUCKTONLOWTRIM = 0xF; + } + } + + return AM_HAL_STATUS_SUCCESS; +} + +void am_hal_pwrctrl_blebuck_trim(void) +{ + // + // Enable the BLE buck trim values + // + if ( APOLLO3_GE_A1 ) + { + AM_CRITICAL_BEGIN + MCUCTRL->BLEBUCK2_b.BLEBUCKTONHITRIM = 0x19; + MCUCTRL->BLEBUCK2_b.BLEBUCKTONLOWTRIM = 0xC; + CLKGEN->BLEBUCKTONADJ_b.TONADJUSTEN = CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_DIS; + AM_CRITICAL_END + } + +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.h new file mode 100644 index 0000000..859a3b4 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.h @@ -0,0 +1,261 @@ +//***************************************************************************** +// +// am_hal_pwrctrl.h +//! @file +//! +//! @brief Functions for enabling and disabling power domains. +//! +//! @addtogroup pwrctrl3 Power Control +//! @ingroup apollo3hal +//! @{ + +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_PWRCTRL_H +#define AM_HAL_PWRCTRL_H + +// +// Designate this peripheral. +// +#define AM_APOLLO3_PWRCTRL 1 + +typedef enum +{ + AM_HAL_PWRCTRL_PERIPH_NONE, + AM_HAL_PWRCTRL_PERIPH_IOS, + AM_HAL_PWRCTRL_PERIPH_IOM0, + AM_HAL_PWRCTRL_PERIPH_IOM1, + AM_HAL_PWRCTRL_PERIPH_IOM2, + AM_HAL_PWRCTRL_PERIPH_IOM3, + AM_HAL_PWRCTRL_PERIPH_IOM4, + AM_HAL_PWRCTRL_PERIPH_IOM5, + AM_HAL_PWRCTRL_PERIPH_UART0, + AM_HAL_PWRCTRL_PERIPH_UART1, + AM_HAL_PWRCTRL_PERIPH_ADC, + AM_HAL_PWRCTRL_PERIPH_SCARD, + AM_HAL_PWRCTRL_PERIPH_MSPI, + AM_HAL_PWRCTRL_PERIPH_PDM, + AM_HAL_PWRCTRL_PERIPH_BLEL, + AM_HAL_PWRCTRL_PERIPH_MAX +} am_hal_pwrctrl_periph_e; + +typedef enum +{ + AM_HAL_PWRCTRL_MEM_NONE, + AM_HAL_PWRCTRL_MEM_SRAM_8K_DTCM, + AM_HAL_PWRCTRL_MEM_SRAM_32K_DTCM, + AM_HAL_PWRCTRL_MEM_SRAM_64K_DTCM, + AM_HAL_PWRCTRL_MEM_SRAM_96K, + AM_HAL_PWRCTRL_MEM_SRAM_128K, + AM_HAL_PWRCTRL_MEM_SRAM_160K, + AM_HAL_PWRCTRL_MEM_SRAM_192K, + AM_HAL_PWRCTRL_MEM_SRAM_224K, + AM_HAL_PWRCTRL_MEM_SRAM_256K, + AM_HAL_PWRCTRL_MEM_SRAM_288K, + AM_HAL_PWRCTRL_MEM_SRAM_320K, + AM_HAL_PWRCTRL_MEM_SRAM_352K, + AM_HAL_PWRCTRL_MEM_SRAM_384K, + AM_HAL_PWRCTRL_MEM_FLASH_512K, + AM_HAL_PWRCTRL_MEM_FLASH_1M, + AM_HAL_PWRCTRL_MEM_CACHE, + AM_HAL_PWRCTRL_MEM_ALL, + AM_HAL_PWRCTRL_MEM_MAX +} am_hal_pwrctrl_mem_e; + +#define AM_HAL_PWRCTRL_MEM_FLASH_MIN AM_HAL_PWRCTRL_MEM_FLASH_512K +#define AM_HAL_PWRCTRL_MEM_FLASH_MAX AM_HAL_PWRCTRL_MEM_FLASH_1M + +#define AM_HAL_PWRCTRL_MEM_SRAM_MIN AM_HAL_PWRCTRL_MEM_SRAM_8K_DTCM +#define AM_HAL_PWRCTRL_MEM_SRAM_MAX AM_HAL_PWRCTRL_MEM_SRAM_384K + +//***************************************************************************** +// +// Macros to check whether Apollo3 bucks are enabled. +// +//***************************************************************************** +#define am_hal_pwrctrl_simobuck_enabled_check() \ + (AM_BFR(PWRCTRL, SUPPLYSTATUS, SIMOBUCKON)) + +#define am_hal_pwrctrl_blebuck_enabled_check() \ + (AM_BFR(PWRCTRL, SUPPLYSTATUS, BLEBUCKON)) + +//***************************************************************************** +// +// Function prototypes +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! @brief Enable power to a peripheral. +//! +//! @param ePeripheral - The peripheral to enable. +//! +//! This function enables power to the peripheral and waits for a +//! confirmation from the hardware. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral); + +//***************************************************************************** +// +//! @brief Disable power to a peripheral. +//! +//! @param ePeripheral - The peripheral to disable. +//! +//! This function disables power to the peripheral and waits for a +//! confirmation from the hardware. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_periph_disable(am_hal_pwrctrl_periph_e ePeripheral); + +//***************************************************************************** +// +//! @brief Determine whether a peripheral is currently enabled. +//! +//! @param ePeripheral - The peripheral to enable. +//! @param pui32Enabled - Pointer to a ui32 that will return as 1 or 0. +//! +//! This function determines to the caller whether a given peripheral is +//! currently enabled or disabled. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_periph_enabled( + am_hal_pwrctrl_periph_e ePeripheral, uint32_t *pui32Enabled); + +//***************************************************************************** +// +//! @brief Enable a configuration of memory. +//! +//! @param eMemConfig - The memory configuration. +//! +//! This function establishes the desired configuration of flash, SRAM, ICache, +//! and DCache (DTCM) according to the desired Memory Configuration mask. +//! +//! Only the type of memory specified is affected. Therefore separate calls +//! are required to affect power settings for FLASH, SRAM, or CACHE. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_memory_enable(am_hal_pwrctrl_mem_e eMemConfig); + +//***************************************************************************** +// +//! @brief Power down respective memory. +//! +//! @param eMemPwd - The memory power down enum. +//! +//! This function establishes the desired power down of flash, SRAM, ICache, +//! and DCache (DTCM) according to the desired enum. +//! +//! Only the type of memory specified is affected. Therefore separate calls +//! are required to affect power settings for FLASH, SRAM, or CACHE. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_memory_deepsleep_powerdown(am_hal_pwrctrl_mem_e eMemConfig); + +//***************************************************************************** +// +//! @brief Apply retention voltage to respective memory. +//! +//! @param eMemPwd - The memory power down enum. +//! +//! This function establishes the desired power retain of flash, SRAM, ICache, +//! and DCache (DTCM) according to the desired enum. +//! +//! Only the type of memory specified is affected. Therefore separate calls +//! are required to affect power settings for FLASH, SRAM, or CACHE. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_memory_deepsleep_retain(am_hal_pwrctrl_mem_e eMemConfig); + +//***************************************************************************** +// +//! @brief Initialize system for low power configuration. +//! +//! @param none. +//! +//! This function handles low power initialization. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_low_power_init(void); + +//***************************************************************************** +// +//! @brief Initialize BLE Buck Trims for Lowest Power. +//! +//! @param none. +//! +//! @return none. +// +//***************************************************************************** +extern void am_hal_pwrctrl_blebuck_trim(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_PWRCTRL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl_internal.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl_internal.h new file mode 100644 index 0000000..46ededf --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl_internal.h @@ -0,0 +1,340 @@ +//***************************************************************************** +// +// am_hal_pwrctrl_internal.h +//! @file +//! +//! @brief Internal definitions for Power Control +//! +//! @addtogroup pwrctrl3 Power Control +//! @ingroup apollo3hal +//! @{ + +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_PWRCTRL_INTERNAL_H +#define AM_HAL_PWRCTRL_INTERNAL_H + + +//***************************************************************************** +// +// Peripheral enable bits for am_hal_pwrctrl_periph_enable/disable() +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_IOS (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOS, PWRCTRL_DEVPWREN_PWRIOS_EN)) +#define AM_HAL_PWRCTRL_IOM0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM0, PWRCTRL_DEVPWREN_PWRIOM0_EN)) +#define AM_HAL_PWRCTRL_IOM1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM1, PWRCTRL_DEVPWREN_PWRIOM1_EN)) +#define AM_HAL_PWRCTRL_IOM2 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM2, PWRCTRL_DEVPWREN_PWRIOM2_EN)) +#define AM_HAL_PWRCTRL_IOM3 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM3, PWRCTRL_DEVPWREN_PWRIOM3_EN)) +#define AM_HAL_PWRCTRL_IOM4 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM4, PWRCTRL_DEVPWREN_PWRIOM4_EN)) +#define AM_HAL_PWRCTRL_IOM5 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM5, PWRCTRL_DEVPWREN_PWRIOM5_EN)) +#define AM_HAL_PWRCTRL_UART0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART0, PWRCTRL_DEVPWREN_PWRUART0_EN)) +#define AM_HAL_PWRCTRL_UART1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART1, PWRCTRL_DEVPWREN_PWRUART1_EN)) +#define AM_HAL_PWRCTRL_ADC (_VAL2FLD(PWRCTRL_DEVPWREN_PWRADC, PWRCTRL_DEVPWREN_PWRADC_EN)) +#define AM_HAL_PWRCTRL_SCARD (_VAL2FLD(PWRCTRL_DEVPWREN_PWRSCARD, PWRCTRL_DEVPWREN_PWRSCARD_EN)) +#define AM_HAL_PWRCTRL_MSPI (_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI, PWRCTRL_DEVPWREN_PWRMSPI_EN)) +#define AM_HAL_PWRCTRL_PDM (_VAL2FLD(PWRCTRL_DEVPWREN_PWRPDM, PWRCTRL_DEVPWREN_PWRPDM_EN)) +#define AM_HAL_PWRCTRL_BLEL (_VAL2FLD(PWRCTRL_DEVPWREN_PWRBLEL, PWRCTRL_DEVPWREN_PWRBLEL_EN)) + +#define AM_HAL_PWRCTRL_DEVPWREN_MASK 0x00003FFF +#define AM_HAL_PWRCTRL_DEVPWRSTATUS_MASK 0x000003FC + +//***************************************************************************** +// +// Memory enable values for all defined memory configurations. +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_MEMEN_SRAM_8K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_32K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_ALL)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_96K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP0)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_128K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_96K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP1)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_160K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_128K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP2)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_192K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_160K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP3)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_224K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_192K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP4)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_256K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_224K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP5)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_288K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_256K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP6)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_320K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_288K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP7)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_352K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_320K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP8)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_384K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_352K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP9)) + +#define AM_HAL_PWRCTRL_MEMEN_SRAM_ALL (AM_HAL_PWRCTRL_MEMEN_SRAM_384K) +#define AM_HAL_PWRCTRL_MEMEN_FLASH_512K PWRCTRL_MEMPWREN_FLASH0_Msk +#define AM_HAL_PWRCTRL_MEMEN_FLASH_1M \ + (PWRCTRL_MEMPWREN_FLASH0_Msk | PWRCTRL_MEMPWREN_FLASH1_Msk) +#define AM_HAL_PWRCTRL_MEMEN_CACHE \ + (PWRCTRL_MEMPWREN_CACHEB0_Msk | PWRCTRL_MEMPWREN_CACHEB2_Msk) +#define AM_HAL_PWRCTRL_MEMEN_CACHE_DIS (~AM_HAL_PWRCTRL_MEMEN_CACHE) + +// +// Power up all available memory devices (this is the default power up state) +// +#define AM_HAL_PWRCTRL_MEMEN_ALL \ + (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_ALL) | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_ALL) | \ + _VAL2FLD(PWRCTRL_MEMPWREN_FLASH0, PWRCTRL_MEMPWREN_FLASH0_EN) | \ + _VAL2FLD(PWRCTRL_MEMPWREN_FLASH1, PWRCTRL_MEMPWREN_FLASH1_EN) | \ + _VAL2FLD(PWRCTRL_MEMPWREN_CACHEB0, PWRCTRL_MEMPWREN_CACHEB0_EN) | \ + _VAL2FLD(PWRCTRL_MEMPWREN_CACHEB2, PWRCTRL_MEMPWREN_CACHEB2_EN)) + +//***************************************************************************** +// +// Memory deepsleep powerdown values for all defined memory configurations. +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_8K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_32K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_96K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_96K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_160K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_160K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_224K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_224K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_288K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_288K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_352K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_352K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9)) + +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_ALL (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_512K PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_1M \ + (PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk | PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE (PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE_DIS (~AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE) + +// +// Power down all available memory devices +// +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_ALL \ + (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL) | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL) | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP, PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN) | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP, PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN) | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP, PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN)) + +//***************************************************************************** +// +// Memory status values for all defined memory configurations +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM \ + (PWRCTRL_MEMPWRSTATUS_DTCM00_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM | \ + PWRCTRL_MEMPWRSTATUS_DTCM01_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM | \ + PWRCTRL_MEMPWRSTATUS_DTCM1_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM | \ + PWRCTRL_MEMPWRSTATUS_SRAM0_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K | \ + PWRCTRL_MEMPWRSTATUS_SRAM1_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K | \ + PWRCTRL_MEMPWRSTATUS_SRAM2_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K | \ + PWRCTRL_MEMPWRSTATUS_SRAM3_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K | \ + PWRCTRL_MEMPWRSTATUS_SRAM4_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K | \ + PWRCTRL_MEMPWRSTATUS_SRAM5_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_288K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K | \ + PWRCTRL_MEMPWRSTATUS_SRAM6_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_288K | \ + PWRCTRL_MEMPWRSTATUS_SRAM7_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_352K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K | \ + PWRCTRL_MEMPWRSTATUS_SRAM8_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_352K | \ + PWRCTRL_MEMPWRSTATUS_SRAM9_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K) +#define AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_512K \ + (PWRCTRL_MEMPWRSTATUS_FLASH0_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M \ + (AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_512K | \ + PWRCTRL_MEMPWRSTATUS_FLASH1_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_ALL \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K | \ + AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M) + +//***************************************************************************** +// +// Memory event values for all defined memory configurations +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_8K_DTCM \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN)) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_32K_DTCM \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN)) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_64K_DTCM \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ + PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL)) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_96K \ + ((_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ + PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL)) | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_96K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_160K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_160K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_224K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_224K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_288K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_288K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_352K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_352K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_512K \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_FLASH0EN, \ + PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN)) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_512K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_FLASH1EN, \ + PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE \ + ((_VAL2FLD(PWRCTRL_MEMPWREVENTEN_CACHEB0EN, \ + PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN)) | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_CACHEB2EN, \ + PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_ALL \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K | \ + AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M | \ + AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE) + +//***************************************************************************** +// +// Memory region mask values for all defined memory configurations +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK AM_HAL_PWRCTRL_MEMEN_SRAM_ALL +#define AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK AM_HAL_PWRCTRL_MEMEN_FLASH_1M +#define AM_HAL_PWRCTRL_MEM_REGION_CACHE_MASK AM_HAL_PWRCTRL_MEMEN_CACHE +#define AM_HAL_PWRCTRL_MEM_REGION_ALT_CACHE_MASK AM_HAL_PWRCTRL_PWRONSTATUS_CACHE +#define AM_HAL_PWRCTRL_MEM_REGION_ALL_MASK AM_HAL_PWRCTRL_MEMEN_ALL +#define AM_HAL_PWRCTRL_MEM_REGION_ALT_ALL_MASK AM_HAL_PWRCTRL_PWRONSTATUS_ALL + + +#endif // AM_HAL_PWRCTRL_INTERNAL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.c new file mode 100644 index 0000000..d48850b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.c @@ -0,0 +1,294 @@ +//***************************************************************************** +// +// am_hal_queue.c +//! @file +//! +//! @brief Functions for implementing a queue system. +//! +//! @addtogroup queue3 (QUEUE) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Initializes a queue. +//! +//! @param psQueue - Pointer to a queue structure. +//! @param pvData - Pointer to a memory location to be used for data storage. +//! @param ui32ItemSize - Number of bytes per item in the queue. +//! @param ui32ArraySize - Number of bytes in the data array. +//! +//! This function initializes the members of a queue structure and attaches it +//! to an array of memory that it can use for storage. This function should be +//! called before the queue is used. +//! +//! In this example, we are creating a queue that can hold 1024 32-bit +//! integers. The integers themselves will be stored in the array named +//! pui32WorkingSpace, while information about the queue itself will be stored +//! in sDataQueue. +//! +//! @note The caller should not modify any of the members of am_hal_queue_t +//! structures. The queue API will handle these members in a thread-safe way. +//! +//! @note The queue will remember what size data is in it. Other queue API +//! functions will perform transfers in units of "items" where one "item" is +//! the number of bytes you specify in the \e ui32ItemSize argument upon +//! initialization. +//! +//! Example usage: +//! +//! @code +//! +//! // +//! // Declare a queue structure and an array of bytes we can use to store +//! // data. +//! // +//! am_hal_queue_t sDataQueue; +//! uint32_t pui32WorkingSpace[1024]; +//! +//! // +//! // Attach the queue structure to the working memory. +//! // +//! am_hal_queue_init(&sDataQueue, pui8WorkingSpace, sizeof(uint32_t) +//! sizeof(pui32WorkingSpace)); +//! +//! @endcode +//! +//! The am_hal_queue_from_array macro is a convenient shorthand for this +//! operation. The code below does the same thing as the code above. +//! +//! @code +//! +//! // +//! // Declare a queue structure and an array of bytes we can use to store +//! // data. +//! // +//! am_hal_queue_t sDataQueue; +//! uint32_t pui32WorkingSpace[1024]; +//! +//! // +//! // Attach the queue structure to the working memory. +//! // +//! am_hal_queue_from_array(&sDataQueue, pui8WorkingSpace); +//! +//! @endcode +// +//***************************************************************************** +void +am_hal_queue_init(am_hal_queue_t *psQueue, void *pvData, uint32_t ui32ItemSize, + uint32_t ui32ArraySize) +{ + psQueue->ui32WriteIndex = 0; + psQueue->ui32ReadIndex = 0; + psQueue->ui32Length = 0; + psQueue->ui32Capacity = ui32ArraySize; + psQueue->ui32ItemSize = ui32ItemSize; + psQueue->pui8Data = (uint8_t *) pvData; +} + +//***************************************************************************** +// +//! @brief Adds an item to the Queue +//! +//! @param psQueue - Pointer to a queue structure. +//! @param pvSource - Pointer to the data to be added. +//! @param ui32NumItems - Number of items to be added. +//! +//! This function will copy the data pointed to by pvSource into the queue. The +//! \e ui32NumItems term specifies the number of items to be copied from \e +//! pvSource. The size of an "item" depends on how the queue was initialized. +//! Please see am_hal_queue_init() for more information on this. +//! +//! @return true if the add operation was successful, or false if the queue +//! didn't have enough space. +// +//***************************************************************************** +bool +am_hal_queue_item_add(am_hal_queue_t *psQueue, const void *pvSource, uint32_t ui32NumItems) +{ + uint8_t *pui8Source; + uint32_t ui32Bytes = ui32NumItems * psQueue->ui32ItemSize; + bool bSuccess = false; + + pui8Source = (uint8_t *) pvSource; + + AM_CRITICAL_BEGIN + + // + // Check to make sure that the buffer isn't already full + // + if ( am_hal_queue_space_left(psQueue) >= ui32Bytes ) + { + // + // Loop over the bytes in the source array. + // + for ( uint32_t i = 0; i < ui32Bytes; i++ ) + { + // + // Write the value to the buffer, but only if the source pointer is + // valid. + // + if (pvSource) + { + psQueue->pui8Data[psQueue->ui32WriteIndex] = pui8Source[i]; + } + + // + // Advance the write index, making sure to wrap if necessary. + // + psQueue->ui32WriteIndex = ((psQueue->ui32WriteIndex + 1) % + psQueue->ui32Capacity); + } + + // + // Update the length value appropriately. + // + psQueue->ui32Length += ui32Bytes; + + // + // Report a success. + // + bSuccess = true; + } + else + { + // + // The buffer can't fit the amount of data requested. Return a + // failure. + // + bSuccess = false; + } + + AM_CRITICAL_END + + return bSuccess; +} + +//***************************************************************************** +// +//! @brief Removes an item from the Queue +//! +//! @param psQueue - Pointer to a queue structure. +//! @param pvDest - Pointer to the data to be added. +//! @param ui32NumItems - Number of items to be added. +//! +//! This function will copy the data from the queue into the memory pointed to +//! by pvDest. The \e ui32NumItems term specifies the number of items to be +//! copied from the queue. The size of an "item" depends on how the queue was +//! initialized. Please see am_hal_queue_init() for more information on this. +//! +//! @return true if we were able to pull the requested number of items from the +//! queue, or false if the queue didn't have that many items to pull. +// +//***************************************************************************** +bool +am_hal_queue_item_get(am_hal_queue_t *psQueue, void *pvDest, uint32_t ui32NumItems) +{ + uint8_t *pui8Dest; + uint32_t ui32Bytes = ui32NumItems * psQueue->ui32ItemSize; + bool bSuccess = false; + + pui8Dest = (uint8_t *) pvDest; + + AM_CRITICAL_BEGIN + + // + // Check to make sure that the buffer isn't empty + // + if ( am_hal_queue_data_left(psQueue) >= ui32Bytes ) + { + // + // Loop over the bytes in the destination array. + // + for ( uint32_t i = 0; i < ui32Bytes; i++ ) + { + // + // Grab the next value from the buffer, but only if the + // destination pointer is valid. + // + if (pvDest) + { + pui8Dest[i] = psQueue->pui8Data[psQueue->ui32ReadIndex]; + } + + // + // Advance the read index, wrapping if needed. + // + psQueue->ui32ReadIndex = ((psQueue->ui32ReadIndex + 1) % + psQueue->ui32Capacity); + } + + // + // Adjust the length value to reflect the change. + // + psQueue->ui32Length -= ui32Bytes; + + // + // Report a success. + // + bSuccess = true; + } + else + { + // + // If the buffer didn't have enough data, just return false. + // + bSuccess = false; + } + + AM_CRITICAL_END + + return bSuccess; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.h new file mode 100644 index 0000000..73a8228 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.h @@ -0,0 +1,165 @@ +//***************************************************************************** +// +// am_hal_queue.h +//! @file +//! +//! @brief Functions for implementing a queue system. +//! +//! @addtogroup queue3 (QUEUE) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_QUEUE_H +#define AM_HAL_QUEUE_H + +//***************************************************************************** +// +//! @brief A data structure that will operate as a queue. +//! +//! This data structure holds information necessary for operating a thread-safe +//! queue. When declaring a structure of type am_hal_queue_t, you will also need +//! to provide some working memory for the queue to use. For more information on +//! setting up and using the am_hal_queue_t structure, please see the +//! documentation for am_hal_queue_init(). +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32WriteIndex; + uint32_t ui32ReadIndex; + uint32_t ui32Length; + uint32_t ui32Capacity; + uint32_t ui32ItemSize; + uint8_t *pui8Data; +} +am_hal_queue_t; + +//***************************************************************************** +// +// Function-like macros. +// +//***************************************************************************** + +// +// Returns true if the queue is empty. +// +#define am_hal_queue_empty(psQueue) \ + ((psQueue)->ui32Length == 0) + +// +// Returns true if the queue is full. +// +#define am_hal_queue_full(psQueue) \ + ((psQueue)->ui32Length == (psQueue)->ui32Capacity) + +// +// Returns the amount of space left in the queue (in bytes). +// +#define am_hal_queue_space_left(psQueue) \ + ((psQueue)->ui32Capacity - (psQueue)->ui32Length) + +// +// Returns the number of configured items that will fit in the queue. +// +#define am_hal_queue_slots_left(psQueue) \ + (((psQueue)->ui32Capacity - (psQueue)->ui32Length) \ + / (psQueue)->ui32ItemSize) + +// +// Returns the amount of data in the queue (in bytes). +// +#define am_hal_queue_data_left(psQueue) \ + ((psQueue)->ui32Length) + +// +// Returns the number of configured items left in the queue. +// +#define am_hal_queue_items_left(psQueue) \ + ((psQueue)->ui32Length / (psQueue)->ui32ItemSize) + +// +// Can be used as a pointer to the next item to be read from the queue. +// +#define am_hal_queue_peek(psQueue) \ + ((void *) &((psQueue)->pui8Data[(psQueue)->ui32ReadIndex])) + +// +// Can be used as a pointer to the next available slot in the queue memory. +// +#define am_hal_queue_next_slot(psQueue) \ + ((void *) &((psQueue)->pui8Data[(psQueue)->ui32WriteIndex])) + +//***************************************************************************** +// +// Use this to make sure you get the size parameters right. +// +//***************************************************************************** +#define am_hal_queue_from_array(queue, array) \ + am_hal_queue_init((queue), (array), sizeof((array)[0]), sizeof(array)) + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_hal_queue_init(am_hal_queue_t *psQueue, void *pvData, uint32_t ui32ItemSize, uint32_t ui32ArraySize); +extern bool am_hal_queue_item_add(am_hal_queue_t *psQueue, const void *pvSource, uint32_t ui32NumItems); +extern bool am_hal_queue_item_get(am_hal_queue_t *psQueue, void *pvDest, uint32_t ui32NumItems); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_QUEUE_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.c new file mode 100644 index 0000000..4b45984 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.c @@ -0,0 +1,314 @@ +//***************************************************************************** +// +// am_hal_reset.c +//! @file +//! +//! @brief Hardware abstraction layer for the Reset Generator module. +//! +//! @addtogroup rstgen3 Reset Generator (RSTGEN) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_mcu_apollo.h" + +uint32_t gAmHalResetStatus = 0; + +//***************************************************************************** +// +// am_hal_reset_enable() +// Enable and configure the Reset controller. +// +//***************************************************************************** +uint32_t +am_hal_reset_configure(am_hal_reset_configure_e eConfigure) +{ + uint32_t ui32Val; + bool bEnable; + + switch ( eConfigure ) + { + case AM_HAL_RESET_BROWNOUT_HIGH_ENABLE: + bEnable = true; + ui32Val = RSTGEN_CFG_BODHREN_Msk; + break; + + case AM_HAL_RESET_WDT_RESET_ENABLE: + bEnable = true; + ui32Val = RSTGEN_CFG_WDREN_Msk; + break; + + case AM_HAL_RESET_BROWNOUT_HIGH_DISABLE: + bEnable = false; + ui32Val = RSTGEN_CFG_BODHREN_Msk; + break; + + case AM_HAL_RESET_WDT_RESET_DISABLE: + bEnable = false; + ui32Val = RSTGEN_CFG_WDREN_Msk; + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + AM_CRITICAL_BEGIN + if ( bEnable ) + { + RSTGEN->CFG |= ui32Val; + } + else + { + RSTGEN->CFG &= ~ui32Val; + } + AM_CRITICAL_END + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_configure() + + +//***************************************************************************** +// +// am_hal_reset_control() +// Perform various reset functions including assertion of software resets. +// +//***************************************************************************** +uint32_t +am_hal_reset_control(am_hal_reset_control_e eControl, void *pArgs) +{ + switch ( eControl ) + { + case AM_HAL_RESET_CONTROL_SWPOR: + // + // Perform a Power On Reset level reset. + // Write the POR key to the software POR register. + // + RSTGEN->SWPOR = + _VAL2FLD(RSTGEN_SWPOR_SWPORKEY, RSTGEN_SWPOR_SWPORKEY_KEYVALUE); + break; + + case AM_HAL_RESET_CONTROL_SWPOI: + // + // Perform a Power On Initialization level reset. + // Write the POI key to the software POI register. + // + RSTGEN->SWPOI = + _VAL2FLD(RSTGEN_SWPOI_SWPOIKEY, RSTGEN_SWPOI_SWPOIKEY_KEYVALUE); + break; + + case AM_HAL_RESET_CONTROL_STATUSCLEAR: + // + // Clear ALL of the reset status register bits. + // + RSTGEN->STAT = 0; + break; + + case AM_HAL_RESET_CONTROL_TPIU_RESET: + // + // Reset the TPIU. + // + RSTGEN->TPIURST = _VAL2FLD(RSTGEN_TPIURST_TPIURST, 1); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_control() + + +//***************************************************************************** +// +// am_hal_reset_status_get() +// Return status of the reset generator. +// Application MUST call this API at least once before going to deepsleep +// Otherwise this API will not provide correct reset status +// +//***************************************************************************** +uint32_t +am_hal_reset_status_get(am_hal_reset_status_t *psStatus) +{ + // Need to read the status only the very first time + + if ( psStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Retrieve the reset generator status bits + // + if (!gAmHalResetStatus) + { + gAmHalResetStatus = RSTGEN->STAT; + } + psStatus->eStatus = (am_hal_reset_status_e)gAmHalResetStatus; + psStatus->bEXTStat = _FLD2VAL(RSTGEN_STAT_EXRSTAT, gAmHalResetStatus); + psStatus->bPORStat = _FLD2VAL(RSTGEN_STAT_PORSTAT, gAmHalResetStatus); + psStatus->bBODStat = _FLD2VAL(RSTGEN_STAT_BORSTAT, gAmHalResetStatus); + psStatus->bSWPORStat = _FLD2VAL(RSTGEN_STAT_SWRSTAT, gAmHalResetStatus); + psStatus->bSWPOIStat = _FLD2VAL(RSTGEN_STAT_POIRSTAT, gAmHalResetStatus); + psStatus->bDBGRStat = _FLD2VAL(RSTGEN_STAT_DBGRSTAT, gAmHalResetStatus); + psStatus->bWDTStat = _FLD2VAL(RSTGEN_STAT_WDRSTAT, gAmHalResetStatus); + psStatus->bBOUnregStat = _FLD2VAL(RSTGEN_STAT_BOUSTAT, gAmHalResetStatus); + psStatus->bBOCOREStat = _FLD2VAL(RSTGEN_STAT_BOCSTAT, gAmHalResetStatus); + psStatus->bBOMEMStat = _FLD2VAL(RSTGEN_STAT_BOFSTAT, gAmHalResetStatus); + psStatus->bBOBLEStat = _FLD2VAL(RSTGEN_STAT_BOBSTAT, gAmHalResetStatus); + + // + // Return status. + // If the Reset Status is 0 - this implies application did not capture the snapshot + // before deepsleep, and hence the result is invalid + // + return (gAmHalResetStatus ? AM_HAL_STATUS_SUCCESS : AM_HAL_STATUS_FAIL); + +} // am_hal_reset_status_get() + +//***************************************************************************** +// +//! @brief Enable selected RSTGEN Interrupts. +//! +//! Use this function to enable the reset generator interrupts. +//! +//! @param ui32IntMask - One or more of the following bits, any of which can +//! be ORed together. +//! AM_HAL_RESET_INTERRUPT_BODH +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_reset_interrupt_enable(uint32_t ui32IntMask) +{ + AM_CRITICAL_BEGIN + RSTGEN->INTEN |= ui32IntMask; + AM_CRITICAL_END + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_interrupt_enable() + +//***************************************************************************** +// +// am_hal_reset_interrupt_disable() +// Disable selected RSTGEN Interrupts. +// +//***************************************************************************** +uint32_t +am_hal_reset_interrupt_disable(uint32_t ui32IntMask) +{ + AM_CRITICAL_BEGIN + RSTGEN->INTEN &= ~ui32IntMask; + AM_CRITICAL_END + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_interrupt_disable() + +//***************************************************************************** +// +// am_hal_reset_interrupt_clear() +// Reset generator interrupt clear +// +//***************************************************************************** +uint32_t +am_hal_reset_interrupt_clear(uint32_t ui32IntMask) +{ + RSTGEN->INTEN = ui32IntMask; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_interrupt_clear() + +//***************************************************************************** +// +// am_hal_reset_interrupt_status_get() +// Get interrupt status of reset generator. +// +//***************************************************************************** +uint32_t +am_hal_reset_interrupt_status_get(bool bEnabledOnly, + uint32_t *pui32IntStatus) +{ + if ( pui32IntStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Retrieve the reset generator status bits + // + *pui32IntStatus = RSTGEN->INTSTAT; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_interrupt_status_get() + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.h new file mode 100644 index 0000000..460dc74 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.h @@ -0,0 +1,308 @@ +//***************************************************************************** +// +// am_hal_reset.h +//! @file +//! +//! @brief Hardware abstraction layer for the Reset Generator module. +//! +//! @addtogroup rstgen3 Reset Generator (RSTGEN) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_RSTGEN_H +#define AM_HAL_RSTGEN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Designate this peripheral. +// +#define AM_APOLLO3_RESET 1 + +//***************************************************************************** +// +// RESET specific definitions. +// +//***************************************************************************** +//************************************** +//! Reset Generator configuration values +//************************************** +typedef enum +{ + AM_HAL_RESET_BROWNOUT_HIGH_ENABLE, + AM_HAL_RESET_WDT_RESET_ENABLE, + AM_HAL_RESET_BROWNOUT_HIGH_DISABLE, + AM_HAL_RESET_WDT_RESET_DISABLE +} am_hal_reset_configure_e; + +//************************************** +//! Reset Generator control operations +//************************************** +typedef enum +{ + AM_HAL_RESET_CONTROL_SWPOR, + AM_HAL_RESET_CONTROL_SWPOI, + AM_HAL_RESET_CONTROL_STATUSCLEAR, + AM_HAL_RESET_CONTROL_TPIU_RESET +} am_hal_reset_control_e; + +//************************************** +//! Reset Generator status bits +//************************************** +typedef enum +{ + AM_HAL_RESET_STATUS_EXTERNAL = RSTGEN_STAT_EXRSTAT_Msk, + AM_HAL_RESET_STATUS_POR = RSTGEN_STAT_PORSTAT_Msk, + AM_HAL_RESET_STATUS_BOD = RSTGEN_STAT_BORSTAT_Msk, + AM_HAL_RESET_STATUS_SWPOR = RSTGEN_STAT_SWRSTAT_Msk, + AM_HAL_RESET_STATUS_SWPOI = RSTGEN_STAT_POIRSTAT_Msk, + AM_HAL_RESET_STATUS_DEBUGGER = RSTGEN_STAT_DBGRSTAT_Msk, + AM_HAL_RESET_STATUS_WDT = RSTGEN_STAT_WDRSTAT_Msk, + AM_HAL_RESET_STATUS_BOUNREG = RSTGEN_STAT_BOUSTAT_Msk, + AM_HAL_RESET_STATUS_BOCORE = RSTGEN_STAT_BOCSTAT_Msk, + AM_HAL_RESET_STATUS_BOMEM = RSTGEN_STAT_BOFSTAT_Msk, + AM_HAL_RESET_STATUS_BOBLE = RSTGEN_STAT_BOBSTAT_Msk +} am_hal_reset_status_e; + +//************************************** +//! RESET status structure +//************************************** +typedef struct +{ + am_hal_reset_status_e + eStatus; // Return all status bits from RSTGEN.STAT + bool bEXTStat; // External reset + bool bPORStat; // Power-On reset + bool bBODStat; // Brown-Out reset + bool bSWPORStat; // SW Power-On reset or AIRCR reset + bool bSWPOIStat; // SW Power On Initialization reset + bool bDBGRStat; // Debugger reset + bool bWDTStat; // Watch Dog Timer reset + bool bBOUnregStat; // Unregulated Supply Brownout event + bool bBOCOREStat; // Core Regulator Brownout event + bool bBOMEMStat; // Memory Regulator Brownout event + bool bBOBLEStat; // BLE/Burst Regulator Brownout event +} am_hal_reset_status_t; + +// +// Define interrupt bit(s) +// +#define AM_HAL_RESET_INTERRUPT_BODH RSTGEN_INTEN_BODH_Msk + +// Global variable used to capture the reset status +extern uint32_t gAmHalResetStatus; + +//***************************************************************************** +// +//! @brief Enable and configure the Reset controller. +//! +//! This function will configure the specified reset conditions. +//! +//! @param eConfigure - One of configuration enumerations. +//! AM_HAL_RESET_BROWNOUT_HIGH_ENABLE +//! AM_HAL_RESET_WDT_RESET_ENABLE +//! AM_HAL_RESET_BROWNOUT_HIGH_DISABLE +//! AM_HAL_RESET_WDT_RESET_DISABLE +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_configure(am_hal_reset_configure_e eConfigure); + +//***************************************************************************** +// +//! @brief Reset generator functions. +//! +//! This function will perform various reset functions including assertion +//! of software resets. +//! +//! @param eControl - One of the control enumerations. +//! AM_HAL_RESET_CONTROL_SWPOR - power on reset, which results in a reset of +//! all blocks except for registers in clock gen, RTC, stimer, PMU. +//! Equivalent to the reset state obtained by a hardware reset, use of +//! the ARM AIRCR (Application Interrupt and Reset Control Register) +//! core register, debugger reset, watchdog timer expiration, or +//! brown-out event. +//! AM_HAL_RESET_CONTROL_SWPOI - power on initialization, which results in a +//! reset of all blocks except for registers in clock gen, RTC, stimer. +//! The POI reset level is required in order to enable configuration +//! changes such as memory protection. +//! AM_HAL_RESET_CONTROL_STATUSCLEAR - Clear the entire STATUS register. +//! All reset status register bits are cleared. +//! AM_HAL_RESET_CONTROL_TPIU - Reset the TPIU. +//! +//! @return status - generic or interface specific status. +//! When resetting the chip (SWPOR or SWPOI), the function will obviously +//! not return to the caller. +// +//***************************************************************************** +extern uint32_t am_hal_reset_control(am_hal_reset_control_e eControl, + void *pArgs); + +//***************************************************************************** +// +//! @brief Return status of the reset generator. +//! +//! This function will get the status bits from the reset generator. +//! The status value shows the type of reset(s) that have occurred since power +//! on +//! Application MUST call this API at least once before going to deepsleep +//! Otherwise this API will not provide correct reset status +//! +//! @param psStatus - Pointer to a data structure to receive the status +//! information. Most members of the structure are booleans that receive +//! the status of a particular bit. +//! +//! The eStatus member, however, returns a bitmask of one or more of the +//! following values: +//! AM_HAL_RESET_STATUS_EXTERNAL +//! AM_HAL_RESET_STATUS_POR +//! AM_HAL_RESET_STATUS_BOD +//! AM_HAL_RESET_STATUS_SWPOR +//! AM_HAL_RESET_STATUS_SWPOI +//! AM_HAL_RESET_STATUS_DEBUGGER +//! AM_HAL_RESET_STATUS_WDT +//! AM_HAL_RESET_STATUS_BOUNREG +//! AM_HAL_RESET_STATUS_BOCORE +//! AM_HAL_RESET_STATUS_BOMEM +//! AM_HAL_RESET_STATUS_BOBLE +//! +//! @return status. If the API was never called before a valid reset status +//! could be captured, AM_HAL_STATUS_FAIL is returned. +//! Otherwise AM_HAL_STATUS_SUCCESS implies valid reset status returned +// +//***************************************************************************** +extern uint32_t am_hal_reset_status_get(am_hal_reset_status_t *psStatus); + +//***************************************************************************** +// +//! @brief Static reset of the TPIU. +//! +//! Use this function to reset the TPIU. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_tpiu_reset(void); + +//***************************************************************************** +// +//! @brief Enable selected RSTGEN Interrupts. +//! +//! Use this function to enable the interrupts. +//! +//! @param ui32IntMask - One or more of the following bits, any of which can +//! be ORed together. +//! AM_HAL_RESET_INTERRUPT_BODH +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_interrupt_enable(uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Disable selected RSTGEN Interrupts. +//! +//! Use this function to disable the RSTGEN interrupts. +//! +//! @param ui32IntMask - One or more of the following bits, any of which can +//! be ORed together. +//! AM_HAL_RESET_INTERRUPT_BODH +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_interrupt_disable(uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Reset generator interrupt clear +//! +//! @param ui32IntMask - Interrupt mask. +//! +//! This function clears the reset generator interrupts. +//! +//! @param ui32IntMask - One or more of the following bits, any of which can +//! be ORed together. +//! AM_HAL_RESET_INTERRUPT_BODH +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_interrupt_clear(uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Get interrupt status of reset generator. +//! +//! This function returns the interrupt status for the reset generator. +//! +//! @param pui32IntStatus - ptr to uint32_t to return the interrupt status. +//! +//! The following are valid status bits. +//! AM_HAL_RESET_INTERRUPT_BODH +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_interrupt_status_get(bool bEnabledOnly, + uint32_t *pui32IntStatus); + + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_RSTGEN_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.c new file mode 100644 index 0000000..4117db5 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.c @@ -0,0 +1,651 @@ +//***************************************************************************** +// +// am_hal_rtc.c +//! @file +//! +//! @brief Functions for interfacing with the Real-Time Clock (RTC). +//! +//! @addtogroup rtc3 Real-Time Clock (RTC) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Converts a Binary Coded Decimal (BCD) byte to its Decimal form. +// +//***************************************************************************** +static uint8_t +bcd_to_dec(uint8_t ui8BCDByte) +{ + return (((ui8BCDByte & 0xF0) >> 4) * 10) + (ui8BCDByte & 0x0F); +} + +//***************************************************************************** +// +// Converts a Decimal byte to its Binary Coded Decimal (BCD) form. +// +//***************************************************************************** +static uint8_t +dec_to_bcd(uint8_t ui8DecimalByte) +{ + return (((ui8DecimalByte / 10) << 4) | (ui8DecimalByte % 10)); +} + +//***************************************************************************** +// +//! @brief Selects the clock source for the RTC. +//! +//! @param ui32OSC the clock source for the RTC. +//! +//! This function selects the clock source for the RTC. +//! +//! Valid values for ui32OSC are: +//! +//! AM_HAL_RTC_OSC_XT +//! +//! @return None +//! +//! @note After selection of the RTC oscillator, a 2 second delay occurs before +//! the new setting is reflected in status. Therefore the CLKGEN.STATUS.OMODE +//! bit will not reflect the new status until after the 2s wait period. +//! +// +//***************************************************************************** +void +am_hal_rtc_osc_select(uint32_t ui32OSC) +{ + if ( ui32OSC == AM_HAL_RTC_OSC_XT ) + { + // Clear bit to 0 for XTAL + CLKGEN->OCTRL &= ~CLKGEN_OCTRL_OSEL_Msk; + } +} + +//***************************************************************************** +// +//! @brief Enable/Start the RTC oscillator. +//! +//! Starts the RTC oscillator. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_osc_enable(void) +{ + // + // Start the RTC Oscillator. + // + RTC->RTCCTL_b.RSTOP = 0; + +} + +//***************************************************************************** +// +//! @brief Disable/Stop the RTC oscillator. +//! +//! Stops the RTC oscillator. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_osc_disable(void) +{ + // + // Stop the RTC Oscillator. + // + RTC->RTCCTL_b.RSTOP = 1; +} + +//***************************************************************************** +// +//! @brief Configures the RTC for 12 or 24 hour time keeping. +//! +//! @param b12Hour - A 'true' configures the RTC for 12 hour time keeping. +//! +//! Configures the RTC for 12 (true) or 24 (false) hour time keeping. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_time_12hour(bool b12Hour) +{ + // + // Set the 12/24 hour bit. + // + RTC->RTCCTL_b.HR1224 = b12Hour; +} + +//***************************************************************************** +// +//! @brief Enable selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Enables the RTC interrupts. +//! +//! ui32Interrupt should be the following: +//! +//! AM_HAL_RTC_INT_ALM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_enable(uint32_t ui32Interrupt) +{ + // + // Enable the interrupts. + // + RTC->INTEN |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return the enabled RTC interrupts. +//! +//! Returns the enabled RTC interrupts. +//! +//! @return enabled RTC interrupts. Return is 0 or: +//! +//! AM_HAL_RTC_INT_ALM +// +//***************************************************************************** +uint32_t +am_hal_rtc_int_enable_get(void) +{ + // + // Read the RTC interrupt enable register, and return its contents. + // + return RTC->INTEN; +} + +//***************************************************************************** +// +//! @brief Disable selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Disables the RTC interrupts. +//! +//! ui32Interrupt should be the following: +//! +//! AM_HAL_RTC_INT_ALM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_disable(uint32_t ui32Interrupt) +{ + // + // Disable the interrupts. + // + RTC->INTEN &= ~ui32Interrupt; + +} + +//***************************************************************************** +// +//! @brief Sets the selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Sets the RTC interrupts causing them to immediately trigger. +//! +//! ui32Interrupt should be the following: +//! +//! AM_HAL_RTC_INT_ALM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_set(uint32_t ui32Interrupt) +{ + // + // Set the interrupts. + // + RTC->INTSET = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Clear selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Clears the RTC interrupts. +//! +//! ui32Interrupt should be the following: +//! +//! AM_HAL_RTC_INT_ALM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_clear(uint32_t ui32Interrupt) +{ + // + // Clear the interrupts. + // + RTC->INTCLR = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Returns the RTC interrupt status. +//! +//! @param bEnabledOnly - return the status of only the enabled interrupts. +//! +//! Returns the RTC interrupt status. +//! +//! @return Bitwise representation of the current interrupt status. +//! +//! The return value will be 0 or the following: +//! +//! AM_HAL_RTC_INT_ALM +// +//***************************************************************************** +uint32_t +am_hal_rtc_int_status_get(bool bEnabledOnly) +{ + // + // Get the interrupt status. + // + if ( bEnabledOnly ) + { + uint32_t u32RetVal; + u32RetVal = RTC->INTSTAT; + u32RetVal &= RTC->INTEN; + return u32RetVal & (AM_HAL_RTC_INT_ALM); + } + else + { + return RTC->INTSTAT & (AM_HAL_RTC_INT_ALM); + } +} + +//***************************************************************************** +// +//! @brief Set the Real Time Clock counter registers. +//! +//! @param *pTime - A pointer to the time structure. +//! +//! Sets the RTC counter registers to the supplied values. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_time_set(am_hal_rtc_time_t *pTime) +{ + // + // Enable writing to the counters. + // + RTC->RTCCTL_b.WRTC = RTC_RTCCTL_WRTC_EN; + + // + // Write the RTCLOW register. + // + RTC->CTRLOW = + _VAL2FLD(RTC_CTRLOW_CTRHR, dec_to_bcd(pTime->ui32Hour)) | + _VAL2FLD(RTC_CTRLOW_CTRMIN, dec_to_bcd(pTime->ui32Minute)) | + _VAL2FLD(RTC_CTRLOW_CTRSEC, dec_to_bcd(pTime->ui32Second)) | + _VAL2FLD(RTC_CTRLOW_CTR100, dec_to_bcd(pTime->ui32Hundredths)); + + // + // Write the RTCUP register. + // + RTC->CTRUP = + _VAL2FLD(RTC_CTRUP_CEB, (pTime->ui32CenturyEnable)) | + _VAL2FLD(RTC_CTRUP_CB, (pTime->ui32Century)) | + _VAL2FLD(RTC_CTRUP_CTRWKDY, (pTime->ui32Weekday)) | + _VAL2FLD(RTC_CTRUP_CTRYR, dec_to_bcd((pTime->ui32Year))) | + _VAL2FLD(RTC_CTRUP_CTRMO, dec_to_bcd((pTime->ui32Month))) | + _VAL2FLD(RTC_CTRUP_CTRDATE, dec_to_bcd((pTime->ui32DayOfMonth))); + + // + // Disable writing to the counters. + // + RTC->RTCCTL_b.WRTC = RTC_RTCCTL_WRTC_DIS; +} + +//***************************************************************************** +// +//! @brief Get the Real Time Clock current time. +//! +//! @param *pTime - A pointer to the time structure to store the current time. +//! +//! Gets the RTC's current time +//! +//! @return 0 for success and 1 for error. +// +//***************************************************************************** +uint32_t +am_hal_rtc_time_get(am_hal_rtc_time_t *pTime) +{ + uint32_t ui32RTCLow, ui32RTCUp, ui32Value; + + // + // Read the upper and lower RTC registers. + // + ui32RTCLow = RTC->CTRLOW; + ui32RTCUp = RTC->CTRUP; + + // + // Break out the lower word. + // + ui32Value = + ((ui32RTCLow & RTC_CTRLOW_CTRHR_Msk) >> RTC_CTRLOW_CTRHR_Pos); + pTime->ui32Hour = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCLow & RTC_CTRLOW_CTRMIN_Msk) >> RTC_CTRLOW_CTRMIN_Pos); + pTime->ui32Minute = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCLow & RTC_CTRLOW_CTRSEC_Msk) >> RTC_CTRLOW_CTRSEC_Pos); + pTime->ui32Second = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCLow & RTC_CTRLOW_CTR100_Msk) >> RTC_CTRLOW_CTR100_Pos); + pTime->ui32Hundredths = bcd_to_dec(ui32Value); + + // + // Break out the upper word. + // + pTime->ui32ReadError = + ((ui32RTCUp & RTC_CTRUP_CTERR_Msk) >> RTC_CTRUP_CTERR_Pos); + + pTime->ui32CenturyEnable = + ((ui32RTCUp & RTC_CTRUP_CEB_Msk) >> RTC_CTRUP_CEB_Pos); + + pTime->ui32Century = + ((ui32RTCUp & RTC_CTRUP_CB_Msk) >> RTC_CTRUP_CB_Pos); + + ui32Value = + ((ui32RTCUp & RTC_CTRUP_CTRWKDY_Msk) >> RTC_CTRUP_CTRWKDY_Pos); + pTime->ui32Weekday = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCUp & RTC_CTRUP_CTRYR_Msk) >> RTC_CTRUP_CTRYR_Pos); + pTime->ui32Year = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCUp & RTC_CTRUP_CTRMO_Msk) >> RTC_CTRUP_CTRMO_Pos); + pTime->ui32Month = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCUp & RTC_CTRUP_CTRDATE_Msk) >> RTC_CTRUP_CTRDATE_Pos); + + pTime->ui32DayOfMonth = bcd_to_dec(ui32Value); + + // + // Was there a read error? + // + if (pTime->ui32ReadError) + { + return 1; + } + else + { + return 0; + } +} + +//***************************************************************************** +// +//! @brief Sets the alarm repeat interval. +//! +//! @param ui32RepeatInterval the desired repeat interval. +//! +//! Sets the alarm repeat interval. +//! +//! Valid values for ui32RepeatInterval: +//! +//! AM_HAL_RTC_ALM_RPT_DIS +//! AM_HAL_RTC_ALM_RPT_YR +//! AM_HAL_RTC_ALM_RPT_MTH +//! AM_HAL_RTC_ALM_RPT_WK +//! AM_HAL_RTC_ALM_RPT_DAY +//! AM_HAL_RTC_ALM_RPT_HR +//! AM_HAL_RTC_ALM_RPT_MIN +//! AM_HAL_RTC_ALM_RPT_SEC +//! AM_HAL_RTC_ALM_RPT_10TH +//! AM_HAL_RTC_ALM_RPT_100TH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_alarm_interval_set(uint32_t ui32RepeatInterval) +{ + uint32_t ui32RptInt, ui32Alm100, ui32Value; + + switch(ui32RepeatInterval) + { + // + // If repeat every 10th set RPT and ALM100 field accordinly + // + case AM_HAL_RTC_ALM_RPT_10TH: + ui32RptInt = AM_HAL_RTC_ALM_RPT_SEC; + ui32Alm100 = AM_HAL_RTC_ALM100_10TH; + break; + // + // If repeat every 100th set RPT and ALM100 field accordinly + // + case AM_HAL_RTC_ALM_RPT_100TH: + ui32RptInt = AM_HAL_RTC_ALM_RPT_SEC; + ui32Alm100 = AM_HAL_RTC_ALM100_100TH; + break; + // + // Otherwise set RPT as value passed. ALM100 values need to be 0xnn + // in this setting where n = 0-9. + // + default: + // + // Get the current value of the ALM100 field. + // + ui32Value = RTC->ALMLOW_b.ALM100; + + // + // If ALM100 was previous EVERY_10TH or EVERY_100TH reset to zero + // otherwise keep previous setting. + // + ui32Alm100 = ui32Value >= 0xF0 ? 0 : ui32Value; + + // + // Set RPT value to value passed. + // + ui32RptInt = ui32RepeatInterval; + break; + } + + + // + // Write the interval to the register. + // + RTC->RTCCTL_b.RPT = ui32RptInt; + + // + // Write the Alarm 100 bits in the ALM100 register. + // + RTC->ALMLOW_b.ALM100 = ui32Alm100; +} + +//***************************************************************************** +// +//! @brief Sets the RTC's Alarm. +//! +//! @param *pTime - A pointer to the time structure. +//! @param ui32RepeatInterval - the desired alarm repeat interval. +//! +//! Set the Real Time Clock Alarm Parameters. +//! +//! Valid values for ui32RepeatInterval: +//! +//! AM_HAL_RTC_ALM_RPT_DIS +//! AM_HAL_RTC_ALM_RPT_YR +//! AM_HAL_RTC_ALM_RPT_MTH +//! AM_HAL_RTC_ALM_RPT_WK +//! AM_HAL_RTC_ALM_RPT_DAY +//! AM_HAL_RTC_ALM_RPT_HR +//! AM_HAL_RTC_ALM_RPT_MIN +//! AM_HAL_RTC_ALM_RPT_SEC +//! AM_HAL_RTC_ALM_RPT_10TH +//! AM_HAL_RTC_ALM_RPT_EVERY_100TH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_alarm_set(am_hal_rtc_time_t *pTime, uint32_t ui32RepeatInterval) +{ + uint8_t ui8Value = 0; + + // + // Write the interval to the register. + // + RTC->RTCCTL |= _VAL2FLD(RTC_RTCCTL_RPT, (ui32RepeatInterval > 0x7 ? 0x7 : ui32RepeatInterval)); + + // + // Check if the interval is 10th or every 100th and track it in ui8Value. + // + if (ui32RepeatInterval == AM_HAL_RTC_ALM_RPT_10TH) + { + ui8Value = 0xF0; + } + else if (ui32RepeatInterval == AM_HAL_RTC_ALM_RPT_100TH) + { + ui8Value = 0xFF; + } + + // + // Write the ALMUP register. + // + RTC->ALMUP = + _VAL2FLD(RTC_ALMUP_ALMWKDY, (pTime->ui32Weekday)) | + _VAL2FLD(RTC_ALMUP_ALMMO, dec_to_bcd((pTime->ui32Month))) | + _VAL2FLD(RTC_ALMUP_ALMDATE, dec_to_bcd((pTime->ui32DayOfMonth))); + + // + // Write the ALMLOW register. + // + RTC->ALMLOW = + _VAL2FLD(RTC_ALMLOW_ALMHR, dec_to_bcd(pTime->ui32Hour)) | + _VAL2FLD(RTC_ALMLOW_ALMMIN, dec_to_bcd(pTime->ui32Minute)) | + _VAL2FLD(RTC_ALMLOW_ALMSEC, dec_to_bcd(pTime->ui32Second)) | + _VAL2FLD(RTC_ALMLOW_ALM100, dec_to_bcd(pTime->ui32Hundredths) | ui8Value); +} + +//***************************************************************************** +// +//! @brief Get the Real Time Clock Alarm Parameters +//! +//! @param *pTime - A pointer to the time structure to store the current alarm. +//! +//! Gets the RTC's Alarm time +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_alarm_get(am_hal_rtc_time_t *pTime) +{ + uint32_t ui32ALMLow, ui32ALMUp, ui32Value; + + // + // Read the upper and lower RTC registers. + // + ui32ALMLow = RTC->ALMLOW; + ui32ALMUp = RTC->ALMUP; + + // + // Break out the lower word. + // + ui32Value = ((ui32ALMLow & RTC_ALMLOW_ALMHR_Msk) >> RTC_ALMLOW_ALMHR_Pos); + pTime->ui32Hour = bcd_to_dec(ui32Value); + + ui32Value = ((ui32ALMLow & RTC_ALMLOW_ALMMIN_Msk) >> RTC_ALMLOW_ALMMIN_Pos); + pTime->ui32Minute = bcd_to_dec(ui32Value); + + ui32Value = ((ui32ALMLow & RTC_ALMLOW_ALMSEC_Msk) >> RTC_ALMLOW_ALMSEC_Pos); + pTime->ui32Second = bcd_to_dec(ui32Value); + + ui32Value = ((ui32ALMLow & RTC_ALMLOW_ALM100_Msk) >> RTC_ALMLOW_ALM100_Pos); + pTime->ui32Hundredths = bcd_to_dec(ui32Value); + + // + // Break out the upper word. + // + pTime->ui32ReadError = 0; + pTime->ui32CenturyEnable = 0; + pTime->ui32Century = 0; + + ui32Value = ((ui32ALMUp & RTC_ALMUP_ALMWKDY_Msk) >> RTC_ALMUP_ALMWKDY_Pos); + pTime->ui32Weekday = bcd_to_dec(ui32Value); + + pTime->ui32Year = 0; + + ui32Value = ((ui32ALMUp & RTC_ALMUP_ALMMO_Msk) >> RTC_ALMUP_ALMMO_Pos); + pTime->ui32Month = bcd_to_dec(ui32Value); + + ui32Value = ((ui32ALMUp & RTC_ALMUP_ALMDATE_Msk) >> RTC_ALMUP_ALMDATE_Pos); + pTime->ui32DayOfMonth = bcd_to_dec(ui32Value); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.h new file mode 100644 index 0000000..3458112 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.h @@ -0,0 +1,185 @@ +//***************************************************************************** +// +// am_hal_rtc.h +//! @file +//! +//! @brief Functions for interfacing and accessing the Real-Time Clock (RTC). +//! +//! @addtogroup rtc3 Real-Time Clock (RTC) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_RTC_H +#define AM_HAL_RTC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! @name OSC Start and Stop +//! @brief OSC Start and Stop defines. +//! +//! OSC Start and Stop defines to be used with \e am_hal_clkgen_osc_x(). +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_OSC_XT 0x0 +//! @} + +//***************************************************************************** +// +//! @name RTC Interrupts +//! @brief Macro definitions for RTC interrupt status bits. +//! +//! These macros correspond to the bits in the RTC interrupt status register. +//! They may be used with any of the \e am_hal_rtc_int_x() functions. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_INT_ALM RTC_INTEN_ALM_Msk +//! @} + +//***************************************************************************** +// +//! @name RTC Alarm Repeat Interval. +//! @brief Macro definitions for the RTC alarm repeat interval. +//! +//! These macros correspond to the RPT bits in the RTCCTL register. +//! They may be used with the \e am_hal_rtc_alarm_interval_set() function. +//! +//! Note: AM_HAL_RTC_ALM_RPT_10TH and AM_HAL_RTC_ALM_RPT_100TH do not +//! correspond to the RPT bits but are used in conjunction with setting the +//! ALM100 bits in the ALMLOW register. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_ALM_RPT_DIS 0x0 +#define AM_HAL_RTC_ALM_RPT_YR 0x1 +#define AM_HAL_RTC_ALM_RPT_MTH 0x2 +#define AM_HAL_RTC_ALM_RPT_WK 0x3 +#define AM_HAL_RTC_ALM_RPT_DAY 0x4 +#define AM_HAL_RTC_ALM_RPT_HR 0x5 +#define AM_HAL_RTC_ALM_RPT_MIN 0x6 +#define AM_HAL_RTC_ALM_RPT_SEC 0x7 +#define AM_HAL_RTC_ALM_RPT_10TH 0x8 +#define AM_HAL_RTC_ALM_RPT_100TH 0x9 +//! @} + +//***************************************************************************** +// +//! @name RTC Alarm 100 Interval. +//! @brief Macro definitions for the RTC alarm ms intervals. +//! +//! These macros are used inside the #am_hal_rtc_alarm_interval_set function +//! when 10ms and 100ms repeated alarm intervals are desired. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_ALM100_DEFAULT 0x00 +#define AM_HAL_RTC_ALM100_10TH 0xF0 +#define AM_HAL_RTC_ALM100_100TH 0xFF +//! @} + +//***************************************************************************** +// +//! @brief The basic time structure used by the HAL for RTC interaction. +//! +//! All values are positive whole numbers. The HAL routines convert back and +//! forth to BCD. +// +//***************************************************************************** +typedef struct am_hal_rtc_time_struct +{ + uint32_t ui32ReadError; + uint32_t ui32CenturyEnable; + uint32_t ui32Weekday; + uint32_t ui32Century; + uint32_t ui32Year; + uint32_t ui32Month; + uint32_t ui32DayOfMonth; + uint32_t ui32Hour; + uint32_t ui32Minute; + uint32_t ui32Second; + uint32_t ui32Hundredths; +}am_hal_rtc_time_t; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_rtc_osc_select(uint32_t ui32OSC); +extern void am_hal_rtc_osc_enable(void); +extern void am_hal_rtc_osc_disable(void); +extern void am_hal_rtc_time_12hour(bool b12Hour); +extern void am_hal_rtc_time_set(am_hal_rtc_time_t *pTime); +extern uint32_t am_hal_rtc_time_get(am_hal_rtc_time_t *pTime); +extern void am_hal_rtc_alarm_interval_set(uint32_t ui32RepeatInterval); +extern void am_hal_rtc_alarm_set(am_hal_rtc_time_t *pTime, + uint32_t ui32RepeatInterval); +extern void am_hal_rtc_alarm_get(am_hal_rtc_time_t *pTime); +extern void am_hal_rtc_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_rtc_int_enable_get(void); +extern void am_hal_rtc_int_disable(uint32_t ui32Interrupt); +extern void am_hal_rtc_int_clear(uint32_t ui32Interrupt); +extern void am_hal_rtc_int_set(uint32_t ui32Interrupt); +extern uint32_t am_hal_rtc_int_status_get(bool bEnabledOnly); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_RTC_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.c new file mode 100644 index 0000000..5f1e9e3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.c @@ -0,0 +1,1575 @@ +//***************************************************************************** +// +// am_hal_scard.c +//! @file +//! +//! @brief Functions for interfacing with the SCARD. +//! +//! @addtogroup scard3 +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// SCARD magic number for handle verification. +// +//***************************************************************************** +#define AM_HAL_MAGIC_SCARD 0xEA9E06 + +#define AM_HAL_SCARD_CHK_HANDLE(h) \ + ((h) && \ + ((am_hal_handle_prefix_t *)(h))->s.bInit && \ + (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_SCARD)) + +//***************************************************************************** +// +// Convenience macro for passing errors. +// +//***************************************************************************** +#define RETURN_ON_ERROR(x) \ + if ((x) != AM_HAL_STATUS_SUCCESS) \ + { \ + return (x); \ + }; + +//***************************************************************************** +// +// Baudrate to byte-time in microseconds with a little extra margin. +// +//***************************************************************************** +#define ONE_BIT_US(baudrate) (AM_HAL_SCARD_CLK_FREQ/(baudrate)) +#define ONE_BIT_DELAY(handle) \ + am_hal_flash_delay(FLASH_CYCLES_US(ONE_BIT_US((handle)->ui32BaudRate))) + +#define SCARD_MAX_SYNC_TIME_MS 10 + +#define delay_ms(ms) am_hal_flash_delay(FLASH_CYCLES_US(1000 * (ms))) +#define delay_us(us) am_hal_flash_delay(FLASH_CYCLES_US(us)) + +#define SCARD_WHILE_TIMEOUT_MS(expr, timeout, error) \ +{ \ + uint32_t ui32Timeout = 0; \ + while ( expr ) \ + { \ + if ( ui32Timeout == (timeout * 1000) ) \ + { \ + return error; \ + } \ + \ + delay_us(1); \ + ui32Timeout++; \ + } \ +} + +#define SCARD_SYNC_OPER(module, operation) do{\ + SCARDn(module)->SR1_b.SYNCEND = 1;\ + operation;\ + SCARD_WHILE_TIMEOUT_MS(!SCARDn(module)->SR1_b.SYNCEND, SCARD_MAX_SYNC_TIME_MS, AM_HAL_SCARD_STATUS_BUS_ERROR) ;\ + } while ( 0 ) + +//***************************************************************************** +// +// Transmission parameters F and D look-up tables +// Per the ETU 7816-3 protocol ETU is computed from 2 parameters, FI and DI. +// ETU: Elementary Time Unit +// FI: Clock rate conversion factor +// DI: Bit rate adjustment factor +// +//***************************************************************************** +static uint16_t g_F_Integer[16][2] = +{ + // FI { F, f(max)} + /*0000*/{ 372, 4}, + /*0001*/{ 372, 5}, + /*0010*/{ 558, 6}, + /*0011*/{ 744, 8}, + /*0100*/{1116, 12}, + /*0101*/{1488, 16}, + /*0110*/{1860, 20}, + /*0111*/{ 0, 0}, + /*1000*/{ 0, 0}, + /*1001*/{ 512, 5}, + /*1010*/{ 768, 7}, //7.5 + /*1011*/{1024, 10}, + /*1100*/{1536, 15}, + /*1101*/{2048, 20}, + /*1110*/{ 0, 0}, + /*1111*/{ 0, 0} +}; +static uint8_t g_D_Integer[16] = +{ + //DI 0000 0001 0010 0011 0100 0101 0110 0111 + /*D*/ 0, 1, 2, 4, 8, 16, 32, 64, + //DI 1000 1001 1010 1011 1100 1101 1110 1111 + /*D*/ 12, 20, 0, 0, 0, 0, 0, 0 +}; + +static uint16_t g_WaitTime = AM_HAL_SCARD_WAIT_MAX_TIME; //Set to max + +//***************************************************************************** +// +// Structure for handling SCARD register state information for power up/down +// +//***************************************************************************** +typedef struct +{ + bool bValid; + uint32_t regIER; + uint32_t regTCR; + uint32_t regUCR; + uint32_t regBPRL; + uint32_t regBPRH; + uint32_t regUCR1; + uint32_t regIER1; + uint32_t regGTR; + uint32_t regRETXCNT; + uint32_t regCLKCTRL; +} +am_hal_scard_register_state_t; + +//***************************************************************************** +// +// Structure for handling SCARD instance state information. +// +//***************************************************************************** +typedef struct +{ + am_hal_handle_prefix_t prefix; + am_hal_scard_register_state_t sRegState; + + uint32_t ui32Module; + + bool bEnableTxQueue; + am_hal_queue_t sTxQueue; + + bool bEnableRxQueue; + am_hal_queue_t sRxQueue; + + uint32_t ui32BaudRate; +} +am_hal_scard_state_t; + +//***************************************************************************** +// +// State structure for each module. +// +//***************************************************************************** +am_hal_scard_state_t g_am_hal_scard_states[AM_REG_SCARD_NUM_MODULES]; + +//***************************************************************************** +// +// Allows the SCARD HAL to use extra space to store TX and RX data. +// +//***************************************************************************** +static uint32_t +buffer_configure(void *pHandle, uint8_t *pui8TxBuffer, uint32_t ui32TxBufferSize, + uint8_t *pui8RxBuffer, uint32_t ui32RxBufferSize) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32ErrorStatus; + + // + // Check to make sure this is a valid handle. + // + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check to see if we have a TX buffer. + // + if ( pui8TxBuffer && ui32TxBufferSize ) + { + // + // If so, initialzie the transmit queue, and enable the TX FIFO + // interrupt. + // + pState->bEnableTxQueue = true; + am_hal_queue_init(&pState->sTxQueue, pui8TxBuffer, 1, ui32TxBufferSize); + ui32ErrorStatus = am_hal_scard_interrupt_enable(pHandle, 0, AM_HAL_SCARD_INT_TBERBFEN); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + // + // If not, make sure the TX FIFO interrupt is disabled. + // + pState->bEnableTxQueue = false; + ui32ErrorStatus = am_hal_scard_interrupt_disable(pHandle, 0, AM_HAL_SCARD_INT_TBERBFEN); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // Check to see if we have an RX buffer. + // + if ( pui8RxBuffer && ui32RxBufferSize ) + { + // + // If so, initialize the receive queue and the associated interupts. + // + pState->bEnableRxQueue = true; + am_hal_queue_init(&pState->sRxQueue, pui8RxBuffer, 1, ui32RxBufferSize); + ui32ErrorStatus = am_hal_scard_interrupt_enable(pHandle, 0, (AM_HAL_SCARD_INT_FHFEN | + AM_HAL_SCARD_INT_FNEEN)); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + pState->bEnableRxQueue = false; + ui32ErrorStatus = am_hal_scard_interrupt_disable(pHandle, 0, (AM_HAL_SCARD_INT_FHFEN | + AM_HAL_SCARD_INT_FNEEN)); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + return AM_HAL_STATUS_SUCCESS; +} // buffer_configure() + +//***************************************************************************** +// +// Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_scard_initialize(uint32_t ui32Module, void **ppHandle) +{ + // + // Check that the request module is in range. + // +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( ui32Module >= AM_REG_SCARD_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Check for valid arguements. + // + if ( !ppHandle ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if ( g_am_hal_scard_states[ui32Module].prefix.s.bInit ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Initialize the handle. + // + g_am_hal_scard_states[ui32Module].prefix.s.bInit = true; + g_am_hal_scard_states[ui32Module].prefix.s.magic = AM_HAL_MAGIC_SCARD; + g_am_hal_scard_states[ui32Module].ui32Module = ui32Module; + g_am_hal_scard_states[ui32Module].sRegState.bValid = false; + g_am_hal_scard_states[ui32Module].ui32BaudRate = 0; + + // + // Return the handle. + // + *ppHandle = (void *)&g_am_hal_scard_states[ui32Module]; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_initialize() + +//***************************************************************************** +// +// De-Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_scard_deinitialize(void *pHandle) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *)pHandle; + + // + // Check the handle. + // +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Reset the handle. + // + pState->prefix.s.bInit = false; + pState->ui32Module = 0; + pState->sRegState.bValid = false; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_deinitialize() + +//***************************************************************************** +// +// Power control functions. +// +//***************************************************************************** +uint32_t +am_hal_scard_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( ui32Module >= AM_REG_SCARD_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + am_hal_pwrctrl_periph_e eSCCPowerModule = ((am_hal_pwrctrl_periph_e) + (AM_HAL_PWRCTRL_PERIPH_SCARD + + ui32Module)); + + // + // Check to make sure this is a valid handle. + // + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Decode the requested power state and update SCARD operation accordingly. + // + switch (ePowerState) + { + // + // Turn on the SCC. + // + case AM_HAL_SYSCTRL_WAKE: + // + // Make sure we don't try to restore an invalid state. + // + if ( bRetainState && !pState->sRegState.bValid ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable(eSCCPowerModule); + + if ( bRetainState ) + { + // + // Restore SCC registers + // + AM_CRITICAL_BEGIN + + SCARDn(ui32Module)->IER = pState->sRegState.regIER; + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR = pState->sRegState.regTCR); + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR = pState->sRegState.regUCR); + SCARDn(ui32Module)->BPRL = pState->sRegState.regBPRL; + SCARDn(ui32Module)->BPRH = pState->sRegState.regBPRH; + SCARDn(ui32Module)->UCR1 = pState->sRegState.regUCR1; + SCARDn(ui32Module)->IER1 = pState->sRegState.regIER1; + SCARDn(ui32Module)->GTR = pState->sRegState.regGTR; + SCARDn(ui32Module)->RETXCNT = pState->sRegState.regRETXCNT; + SCARDn(ui32Module)->CLKCTRL = pState->sRegState.regCLKCTRL; + pState->sRegState.bValid = false; + + AM_CRITICAL_END + } + break; + + // + // Turn off the SCARD. + // + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + if ( bRetainState ) + { + AM_CRITICAL_BEGIN + + pState->sRegState.regIER = SCARDn(ui32Module)->IER; + pState->sRegState.regTCR = SCARDn(ui32Module)->TCR; + pState->sRegState.regUCR = SCARDn(ui32Module)->UCR; + pState->sRegState.regBPRL = SCARDn(ui32Module)->BPRL; + pState->sRegState.regBPRH = SCARDn(ui32Module)->BPRH; + pState->sRegState.regUCR1 = SCARDn(ui32Module)->UCR1; + pState->sRegState.regIER1 = SCARDn(ui32Module)->IER1; + pState->sRegState.regGTR = SCARDn(ui32Module)->GTR; + pState->sRegState.regRETXCNT = SCARDn(ui32Module)->RETXCNT; + pState->sRegState.regCLKCTRL = SCARDn(ui32Module)->CLKCTRL; + pState->sRegState.bValid = true; + + AM_CRITICAL_END + } + + // + // Clear all interrupts before sleeping as having a pending SCARD + // interrupt burns power. + // + am_hal_scard_interrupt_clear(pState, 0, AM_HAL_SCARD_INT_ALL); + am_hal_scard_interrupt_clear(pState, 1, AM_HAL_SCARD_INT_ALL); + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable(eSCCPowerModule); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_power_control() + +//***************************************************************************** +// +// SCARD configuration. +// +//***************************************************************************** +uint32_t +am_hal_scard_configure(void *pHandle, am_hal_scard_config_t *psConfig) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check to make sure this is a valid handle. + // +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // + // Start by enabling the clocks, which needs to happen in a critical + // section. + // + AM_CRITICAL_BEGIN + + SCARDn(ui32Module)->CLKCTRL_b.APBCLKEN = 1; + SCARDn(ui32Module)->CLKCTRL_b.CLKEN = 1; + + AM_CRITICAL_END + // + // Set the baud rate. + // + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_BAUDRATE, &psConfig->ui32Fidi); + + //RETURN_ON_ERROR(ui32ErrorStatus); + // + // Copy the configuration options into the appropriate registers. + // + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_PROTOCOL, &psConfig->ui32Protocol); + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_CARD_FORMAT, &psConfig->ui32Direction); + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_PARITY, &psConfig->ui32Parity); + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_GUARDTIME, &psConfig->ui32GuardTime); + SCARDn(ui32Module)->UCR1_b.CLKIOV = psConfig->ui32ClkLevel; + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_CLK_STOP, NULL); + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR_b.RIU = 1); + if ( AM_HAL_STATUS_SUCCESS != status ) + { + return AM_HAL_STATUS_FAIL; + } + // + // Set up any buffers that might exist. + // + buffer_configure(pHandle, + psConfig->pui8TxBuffer, + psConfig->ui32TxBufferSize, + psConfig->pui8RxBuffer, + psConfig->ui32RxBufferSize); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_configure() + +//***************************************************************************** +// +// Set Baud Rate Register based on the parameters F and D. +// +//***************************************************************************** +static void +config_baudrate(void *pHandle, uint32_t ui32Fidi) +{ + uint16_t bpr; + uint32_t ui32ActualBaud; + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // F is the clock rate conversion integer + // D is the baud rate adjustment integer + // 1 ETU = (F/D)*(1/f) s + // The default values of these parameters are: + // F = 372 ; D = 1; f (max.) = 5 MHz + + // + // BPRL and BPRH are used for counting ETU + // + bpr = ((g_F_Integer[AM_HAL_SCARD_FI(ui32Fidi)][0] != 0) && (g_D_Integer[AM_HAL_SCARD_DI(ui32Fidi)] != 0)) ? \ + g_F_Integer[AM_HAL_SCARD_FI(ui32Fidi)][0] / g_D_Integer[AM_HAL_SCARD_DI(ui32Fidi)] : \ + g_F_Integer[AM_HAL_SCARD_FI(AM_HAL_SCARD_FI_DI_DEFAULT)][0] / g_D_Integer[AM_HAL_SCARD_DI(AM_HAL_SCARD_FI_DI_DEFAULT)]; + + SCARDn(ui32Module)->BPRL = bpr & 0xFF; + SCARDn(ui32Module)->BPRH = (SCARDn(ui32Module)->BPRH & (~SCARD_BPRH_BPRH_Msk)) | ((bpr >> 8) & SCARD_BPRH_BPRH_Msk) ; + ui32ActualBaud = (uint32_t)(AM_HAL_SCARD_CLK_FREQ / bpr); + pState->ui32BaudRate = ui32ActualBaud; +} // config_baudrate() + +//***************************************************************************** +// +// Set card format, direct convention or inverse convention +// +//***************************************************************************** +static uint32_t +config_cardformat(uint32_t ui32Module, uint32_t ui32Format) +{ + switch(ui32Format) + { + // + // Inverse convention + // + case AM_HAL_SCARD_CONV_MSB_0X3F: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.AUTOCONV = 1); + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.CONV = 1); + break; + // + // Direct convention + // + case AM_HAL_SCARD_CONV_LSB_0X3B: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.AUTOCONV = 1); + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.CONV = 0); + break; + // + // Not set by software, configured by the first received byte + // + case AM_HAL_SCARD_CONV_AUTO: + default: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.AUTOCONV = 0); + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.SS = 1); + break; + } + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Enable/disbale parity and set it to odd/even +// +//***************************************************************************** +static uint32_t +config_parity(uint32_t ui32Module, uint32_t ui32Parity) +{ + // + // T1 protocol + // + if ( SCARDn(ui32Module)->TCR_b.PROT ) + { + // + // Enable parity + // + if ( ui32Parity & 0xF0 ) + { + SCARDn(ui32Module)->UCR1_b.T1PAREN = 1; + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.FIP = ui32Parity & 0xF); + } + // + // Disbale parity + // + else + { + SCARDn(ui32Module)->UCR1_b.T1PAREN = 0; + } + } + // + // T0 protocol, always enable parity + // + else + { + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.FIP = ui32Parity & 0xF); + } + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Set protocol, T0 or T1 +// +//***************************************************************************** +static uint32_t +config_protocol(uint32_t ui32Module, uint32_t ui32Protocol) +{ + if ( 1 == ui32Protocol ) + { + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.PROT = AM_HAL_SCARD_PROTOCOL_T1); + } + else if ( 0 == ui32Protocol ) + { + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.PROT = AM_HAL_SCARD_PROTOCOL_T0); + } + else + { + return AM_HAL_SCARD_STATUS_PROTOCAL_NOT_SUPPORT; + } + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Set and start ETU counter +// +//***************************************************************************** +static uint32_t +config_etucounter(uint32_t ui32Module, uint16_t ui16Etu) +{ + // + // Set low-8bit first, then set high-8bit, after software writes ECNTH, ETU counter starts counting + // + SCARD_WHILE_TIMEOUT_MS(!SCARDn(ui32Module)->SR1_b.IDLE, 100, AM_HAL_SCARD_STATUS_BUS_ERROR); + SCARDn(ui32Module)->SR1_b.SYNCEND = 1; + SCARDn(ui32Module)->ECNTL = (ui16Etu) & 0xFF; + SCARD_WHILE_TIMEOUT_MS(!SCARDn(ui32Module)->SR1_b.SYNCEND, 100, AM_HAL_SCARD_STATUS_BUS_ERROR); + SCARDn(ui32Module)->ECNTH = ((ui16Etu) >> 8); + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Read as much data from the SCARD FIFO as possible, up to ui32NumBytes +// +//***************************************************************************** +uint32_t scard_fifo_read(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, uint32_t *pui32NumBytesRead) +{ + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + uint32_t i = 0; + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + uint8_t ui8Index = 0; + + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.TR = 0); + + while ( ui32NumBytes ) + { + config_etucounter(ui32Module, g_WaitTime); + while ( (!SCARDn(ui32Module)->SR_b.FNE) && (!SCARDn(ui32Module)->SR1_b.ECNTOVER) && (!SCARDn(ui32Module)->SR_b.PE) && (!SCARDn(ui32Module)->SR_b.FER) ); + // + // Read times out + // + if ( SCARDn(ui32Module)->SR1_b.ECNTOVER ) + { + break; + } + // + // Parity error or Frame error + // + else if ( (SCARDn(ui32Module)->SR_b.PE) || (SCARDn(ui32Module)->SR_b.FER) ) + { + SCARDn(ui32Module)->SR_b.PE = 0; + SCARDn(ui32Module)->SR_b.FER = 0; + ui32ErrorStatus = AM_HAL_STATUS_FAIL; + break; + } + // + // RX FIFO is full, read 8 bytes out + // + else if ( SCARDn(ui32Module)->SR_b.TBERBF ) + { + for ( ui8Index = 0; ui8Index < AM_HAL_SCARD_FIFO_MAX; ui8Index++ ) + { + pui8Data[i++] = SCARDn(ui32Module)->DR_b.DR; + } + ui32NumBytes -= AM_HAL_SCARD_FIFO_MAX; + } + // + // RX FIFO is half full, read 4 bytes out + // + else if ( SCARDn(ui32Module)->SR_b.FHF ) + { + for ( ui8Index = 0; ui8Index < AM_HAL_SCARD_FIFO_MAX / 2; ui8Index++ ) + { + pui8Data[i++] = SCARDn(ui32Module)->DR_b.DR; + } + ui32NumBytes -= AM_HAL_SCARD_FIFO_MAX / 2; + } + // + // RX FIFO is not empty, read as much as we can + // + else if ( SCARDn(ui32Module)->SR_b.FNE ) + { + pui8Data[i++] = SCARDn(ui32Module)->DR_b.DR; + ui32NumBytes--; + } + } + if ( pui32NumBytesRead ) + { + *pui32NumBytesRead = i; + } + return ui32ErrorStatus; +} + +//***************************************************************************** +// +// Read as much data from the SCARD FIFO as possible, up to ui32NumBytes +// +//***************************************************************************** +uint32_t scard_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, uint32_t *pui32NumBytesWritten) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + uint32_t i = 0; + + if ( ui32NumBytes ) + { + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.TR = 1); + + while ( 1 != ui32NumBytes-- ) + { + // + // Write 1 byte into DR + // + SCARDn(ui32Module)->DR_b.DR = pui8Data[i++]; + SCARD_WHILE_TIMEOUT_MS((!SCARDn(ui32Module)->SR_b.TBERBF) && (!SCARDn(ui32Module)->SR_b.PE) && (!SCARDn(ui32Module)->SR_b.FER), 100, AM_HAL_SCARD_STATUS_BUS_ERROR); + // + // Parity error or Frame error + // + if ( (SCARDn(ui32Module)->SR_b.PE) || (SCARDn(ui32Module)->SR_b.FER) ) + { + SCARDn(ui32Module)->SR_b.PE = 0; + SCARDn(ui32Module)->SR_b.FER = 0; + return AM_HAL_STATUS_FAIL; + } + } + + // + // Enable fast TX to RX function before the last byte + // + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.LCT = 1); + SCARDn(ui32Module)->DR_b.DR = pui8Data[i++]; + // + // SCC should switch back to RX after all data sent out + // + SCARD_WHILE_TIMEOUT_MS((!SCARDn(ui32Module)->SR_b.FT2REND) && (!SCARDn(ui32Module)->SR_b.PE) && (!SCARDn(ui32Module)->SR_b.FER), 100, AM_HAL_SCARD_STATUS_BUS_ERROR); + // + // Parity error or Frame error + // + if ( (SCARDn(ui32Module)->SR_b.PE) || (SCARDn(ui32Module)->SR_b.FER) ) + { + SCARDn(ui32Module)->SR_b.PE = 0; + SCARDn(ui32Module)->SR_b.FER = 0; + return AM_HAL_STATUS_FAIL; + } + + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.TR = 0); + } + if ( pui32NumBytesWritten ) + { + *pui32NumBytesWritten = i; + } + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Empty the SCARD RX FIFO, and place the data into the RX queue. +// +//***************************************************************************** +static uint32_t +rx_queue_update(void *pHandle) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + + uint8_t pui8Data[AM_HAL_SCARD_FIFO_MAX]; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus; + + AM_CRITICAL_BEGIN + + // + // Read as much of the FIFO as we can. + // + ui32ErrorStatus = scard_fifo_read(pHandle, pui8Data, AM_HAL_SCARD_FIFO_MAX, + &ui32BytesTransferred); + // + // If we were successful, go ahead and transfer the data along to the + // buffer. + // + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS ) + { + if ( !am_hal_queue_item_add(&pState->sRxQueue, pui8Data, + ui32BytesTransferred) ) + { + ui32ErrorStatus = AM_HAL_SCARD_STATUS_RX_QUEUE_FULL; + } + } + + AM_CRITICAL_END + + return ui32ErrorStatus; +} // rx_queue_update() + +//***************************************************************************** +// +// Transfer as much data as possible from the TX queue to the TX FIFO. +// +//***************************************************************************** +static uint32_t +tx_queue_update(void *pHandle) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + + uint8_t pui8Data; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + + AM_CRITICAL_BEGIN + + // + // Attempt to grab an item from the queue, and add it to the fifo. + // + while ( 1 ) + { + if ( am_hal_queue_item_get(&pState->sTxQueue, &pui8Data, 1) ) + { + ui32ErrorStatus = scard_fifo_write(pHandle, &pui8Data, 1, &ui32BytesTransferred); + } + else + { + // + // If we didn't get anything from the queue, we can just return. + // + break; + } + } + + AM_CRITICAL_END + + return ui32ErrorStatus; +} // tx_queue_update() + +//***************************************************************************** +// +// Attempt to read N bytes from the FIFO, but give up if they aren't there. +// +//***************************************************************************** +static uint32_t +read_nonblocking(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead) +{ + uint32_t ui32BufferData; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + + // + // Check to make sure this is a valid handle. + // +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (!AM_HAL_SCARD_CHK_HANDLE(pHandle)) || (NULL == pui8Data) || (NULL == pui32NumBytesRead) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Start by setting the number of bytes read to 0. + // + *pui32NumBytesRead = 0; + + if ( ui32NumBytes == 0 ) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Check to see if the circular receive buffer has been enabled. + // + if ( pState->bEnableRxQueue ) + { + // + // If it is, update it, and then try to read the requested number of + // bytes, giving up if fewer were actually found. + // + ui32ErrorStatus = rx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + + ui32BufferData = am_hal_queue_data_left(&pState->sRxQueue); + + ui32BytesTransferred = (ui32NumBytes < ui32BufferData ? + ui32NumBytes : ui32BufferData); + + am_hal_queue_item_get(&pState->sRxQueue, pui8Data, ui32BytesTransferred); + } + else + { + // + // If the buffer isn't enabled, just read straight from the FIFO. + // + ui32ErrorStatus = scard_fifo_read(pHandle, pui8Data, ui32NumBytes, + &ui32BytesTransferred); + } + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + *pui32NumBytesRead = ui32BytesTransferred; + + return ui32ErrorStatus; +} // read_nonblocking() + +//***************************************************************************** +// +// Attempt to write N bytes to the FIFO, but give up if there's no space. +// +//***************************************************************************** +static uint32_t +write_nonblocking(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten) +{ + uint32_t ui32ErrorStatus; + uint32_t ui32BufferSpace; + uint32_t ui32BytesTransferred; + + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + + // + // Check to make sure this is a valid handle. + // +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (!AM_HAL_SCARD_CHK_HANDLE(pHandle)) || (NULL == pui8Data) || (NULL == pui32NumBytesWritten) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + *pui32NumBytesWritten = 0; + + if ( ui32NumBytes == 0 ) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Check to see if the circular transmit buffer has been enabled. + // + if ( pState->bEnableTxQueue ) + { + // + // If it has, been enabled, write as much data to it as we can, and let + // the caller know how much that was. + // + ui32BufferSpace = am_hal_queue_space_left(&pState->sTxQueue); + + ui32BytesTransferred = (ui32NumBytes < ui32BufferSpace ? + ui32NumBytes : ui32BufferSpace); + + am_hal_queue_item_add(&pState->sTxQueue, pui8Data, ui32BytesTransferred); + + // + // Transfer as much data as possible from the queue to the fifo. + // + ui32ErrorStatus = tx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + // + // If the buffer isn't enabled, just write straight to the FIFO. + // + scard_fifo_write(pHandle, pui8Data, ui32NumBytes, + &ui32BytesTransferred); + } + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + *pui32NumBytesWritten = ui32BytesTransferred; + + return AM_HAL_STATUS_SUCCESS; +} // write_nonblocking() + +//***************************************************************************** +// +// This function will keep reading bytes until it either gets N bytes or runs +// into an error. +// +//***************************************************************************** +static uint32_t +read_timeout(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead, uint32_t ui32TimeoutMs) +{ + uint32_t ui32Status, ui32BytesRead, ui32RemainingBytes, + ui32TimeSpent, i; + + // + // If we don't have a timeout, just pass this directly to the nonblocking + // call. + // + if ( ui32TimeoutMs == 0 ) + { + return read_nonblocking(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesRead); + } + + i = 0; + ui32RemainingBytes = ui32NumBytes; + ui32TimeSpent = 0; + + // + // Loop until we're done reading. This will either be because we hit a + // timeout, or we got the right number of bytes. If the caller specified + // "wait forever", then don't check the timeout. + // + while ( ui32RemainingBytes && (ui32TimeSpent < ui32TimeoutMs) ) + { + // + // Read as much as we can. + // + ui32BytesRead = 0; + ui32Status = read_nonblocking(pHandle, &pui8Data[i], + ui32RemainingBytes, + &ui32BytesRead); + // + // Update the tracking variables. + // + i += ui32BytesRead; + ui32RemainingBytes -= ui32BytesRead; + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + if ( pui32NumBytesRead ) + { + *pui32NumBytesRead = i; + } + + return ui32Status; + } + + // + // Update the timeout. + // + if ( ui32RemainingBytes ) + { + delay_us(1); + + if ( ui32TimeoutMs != AM_HAL_SCARD_WAIT_FOREVER ) + { + ui32TimeSpent++; + } + } + } + + if ( pui32NumBytesRead ) + { + *pui32NumBytesRead = i; + } + + return AM_HAL_STATUS_SUCCESS; +} // read_timeout() + +//***************************************************************************** +// +// This function will keep writing bytes until it either sends N bytes or runs +// into an error. +// +//***************************************************************************** +static uint32_t +write_timeout(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten, uint32_t ui32TimeoutMs) +{ + uint32_t ui32Status, ui32BytesWritten, ui32RemainingBytes, + ui32TimeSpent, i; + + i = 0; + ui32RemainingBytes = ui32NumBytes; + ui32TimeSpent = 0; + + // + // If we don't have a timeout, just pass this directly to the nonblocking + // call. + // + if ( ui32TimeoutMs == 0 ) + { + return write_nonblocking(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesWritten); + } + + // + // Loop until we're done write. This will either be because we hit a + // timeout, or we sent the right number of bytes. If the caller specified + // "wait forever", then don't check the timeout. + // + while ( ui32RemainingBytes && (ui32TimeSpent < ui32TimeoutMs) ) + { + // + // Write as much as we can. + // + ui32BytesWritten = 0; + ui32Status = write_nonblocking(pHandle, &pui8Data[i], + ui32RemainingBytes, + &ui32BytesWritten); + // + // Update the tracking variables. + // + i += ui32BytesWritten; + ui32RemainingBytes -= ui32BytesWritten; + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + if ( pui32NumBytesWritten ) + { + *pui32NumBytesWritten = i; + } + + return ui32Status; + } + + // + // Update the timeout. + // + if ( ui32RemainingBytes ) + { + delay_us(1); + + if ( ui32TimeoutMs != AM_HAL_SCARD_WAIT_FOREVER ) + { + ui32TimeSpent++; + } + } + } + + if ( pui32NumBytesWritten ) + { + *pui32NumBytesWritten = i; + } + + return AM_HAL_STATUS_SUCCESS; +} // write_timeout() + +//***************************************************************************** +// +// Send or receive bytes. +// +//***************************************************************************** +uint32_t +am_hal_scard_transfer(void *pHandle, const am_hal_scard_transfer_t *pTransfer) +{ + // + // Pick the right function to use based on the transfer structure. + // + if ( pTransfer->ui32Direction == AM_HAL_SCARD_WRITE ) + { + return write_timeout(pHandle, + pTransfer->pui8Data, + pTransfer->ui32NumBytes, + pTransfer->pui32BytesTransferred, + pTransfer->ui32TimeoutMs); + } + else if ( pTransfer->ui32Direction == AM_HAL_SCARD_READ ) + { + return read_timeout(pHandle, + pTransfer->pui8Data, + pTransfer->ui32NumBytes, + pTransfer->pui32BytesTransferred, + pTransfer->ui32TimeoutMs); + } + + return AM_HAL_STATUS_INVALID_OPERATION; +} // am_hal_scard_transfer() + +//***************************************************************************** +// +// Wait for all of the traffic in the TX pipeline to be sent. +// +//***************************************************************************** +uint32_t +am_hal_scard_tx_flush(void *pHandle) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // If we have a TX queue, we should wait for it to empty. + // + if ( pState->bEnableTxQueue ) + { + while ( am_hal_queue_data_left(&(pState->sTxQueue)) ) + { + ONE_BIT_DELAY(pState); + } + } + + // + // Wait for the IDLE bit to go high. + // + while ( SCARDn(ui32Module)->SR1_b.IDLE != 1 ) + { + ONE_BIT_DELAY(pState); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_tx_flush() + +//***************************************************************************** +// +// Interrupt service +// +//***************************************************************************** +uint32_t +am_hal_scard_interrupt_service(void *pHandle, uint32_t ui32Status, uint32_t *pui32ScardTxIdle) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + uint32_t ui32ErrorStatus; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Check to see if we have filled the Rx FIFO past the configured limit, or + // if we have an 'old' character or two sitting in the FIFO. + // + if ( (ui32Status & (SCARD_SR_TBERBF_Msk | SCARD_SR_FHF_Msk | SCARD_SR_FNE_Msk) ) && + pState->bEnableRxQueue) + { + ui32ErrorStatus = rx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // Check to see if our TX buffer has been recently emptied. If so, we + // should refill it from the TX ring buffer. + // + if ( (ui32Status & SCARD_SR_TBERBF_Msk) && pState->bEnableTxQueue ) + { + ui32ErrorStatus = tx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // If this pointer is null, we can just return success now. There is no + // need to figure out if the SCC is idle. + // + if ( pui32ScardTxIdle == 0 ) + { + return AM_HAL_STATUS_SUCCESS; + } + + if ( SCARDn(ui32Module)->SR1_b.IDLE == 1 ) + { + *pui32ScardTxIdle = true; + } + else + { + *pui32ScardTxIdle = false; + } + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Interrupt enable. +// +//***************************************************************************** +uint32_t +am_hal_scard_interrupt_enable(void *pHandle, uint32_t ui32Index, uint32_t ui32IntMask) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (!AM_HAL_SCARD_CHK_HANDLE(pHandle)) || (ui32Index > 1) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if ( 0 == ui32Index ) + { + SCARDn(ui32Module)->IER |= ui32IntMask; + } + else + { + SCARDn(ui32Module)->IER1 |= ui32IntMask; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_interrupt_enable() + +//***************************************************************************** +// +// Interrupt disable. +// +//***************************************************************************** +uint32_t +am_hal_scard_interrupt_disable(void *pHandle, uint32_t ui32Index, uint32_t ui32IntMask) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (!AM_HAL_SCARD_CHK_HANDLE(pHandle)) || (ui32Index > 1) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if ( 0 == ui32Index ) + { + SCARDn(ui32Module)->IER &= ~ui32IntMask; + } + else + { + SCARDn(ui32Module)->IER1 &= ~ui32IntMask; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_interrupt_disable() + +//***************************************************************************** +// +// Interrupt clear. +// +//***************************************************************************** +uint32_t +am_hal_scard_interrupt_clear(void *pHandle, uint32_t ui32Index, uint32_t ui32IntMask) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (!AM_HAL_SCARD_CHK_HANDLE(pHandle)) || (ui32Index > 1) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if ( 0 == ui32Index ) + { + SCARDn(ui32Module)->SR = ui32IntMask; + } + else + { + SCARDn(ui32Module)->SR1 = ui32IntMask; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_interrupt_clear() + +//***************************************************************************** +// +// Returns the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_scard_interrupt_status_get(void *pHandle, uint32_t ui32Index, uint32_t *pui32Status) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // If requested, only return the interrupts that are enabled. + // + *pui32Status = ui32Index ? SCARDn(ui32Module)->SR1 : SCARDn(ui32Module)->SR; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_interrupt_status_get() + + +//***************************************************************************** +// +//! @brief SCARD control function +//! +//! @param handle - handle for the SCARD. +//! @param eReq - device specific special request code. +//! @param pArgs - pointer to the request specific arguments. +//! +//! This function allows advanced settings +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_scard_control(void *pHandle, am_hal_scard_request_e eReq, void *pArgs) +{ + am_hal_scard_state_t *pSCCState = (am_hal_scard_state_t*)pHandle; + uint32_t status = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if ( eReq >= AM_HAL_SCARD_REQ_MAX ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + uint32_t ui32Module = pSCCState->ui32Module; + switch (eReq) + { + case AM_HAL_SCARD_REQ_ACTIVATE: + { + uint16_t etu; + etu = ((SCARDn(ui32Module)->BPRH & SCARD_BPRH_BPRH_Msk) << 8); + etu = etu | SCARDn(ui32Module)->BPRL; + etu = (SCARD_RST_LOW_TIME / etu) + 1; + + config_etucounter(ui32Module, etu); + SCARD_WHILE_TIMEOUT_MS(!SCARDn(ui32Module)->SR1_b.ECNTOVER, 1000, AM_HAL_SCARD_STATUS_BUS_ERROR); + SCARDn(ui32Module)->SR1_b.ECNTOVER = 1; + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR_b.RSTIN = 1); + } + break; + case AM_HAL_SCARD_REQ_DEACTIVATE: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR_b.RSTIN = 0); + break; + case AM_HAL_SCARD_REQ_BAUDRATE: + if ( pArgs ) + { + config_baudrate(pHandle, *(uint32_t*)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_SCARD_REQ_CARD_FORMAT: + if ( pArgs ) + { + config_cardformat(ui32Module, *(uint32_t*)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_SCARD_REQ_PARITY: + if ( pArgs ) + { + config_parity(ui32Module, *(uint32_t*)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_SCARD_REQ_PROTOCOL: + if ( pArgs ) + { + if ( AM_HAL_STATUS_SUCCESS != config_protocol(ui32Module, *(uint32_t*)pArgs) ) + { + status = AM_HAL_STATUS_INVALID_ARG; + } + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_SCARD_REQ_GUARDTIME: + if ( pArgs ) + { + SCARDn(ui32Module)->GTR = *(uint32_t*)pArgs; + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_SCARD_REQ_CLK_START: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR_b.CST = 0); + break; + case AM_HAL_SCARD_REQ_CLK_STOP: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR_b.CST = 1); + break; + default: + status = AM_HAL_STATUS_INVALID_ARG; + } + + return status; +} + + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.h new file mode 100644 index 0000000..fb9ca19 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.h @@ -0,0 +1,660 @@ +//***************************************************************************** +// +// am_hal_scard.h +//! @file +//! +//! @brief Functions for accessing and configuring the SCARD. +//! +//! @addtogroup scard3 +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_SCARD_H +#define AM_HAL_SCARD_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable SCARD module number. +// +//***************************************************************************** +#define SCARDn(n) ((SCARD_Type*)(SCARD_BASE + (n * (SCARD_BASE - SCARD_BASE)))) + +//***************************************************************************** +// +// Initial character TS +// +//***************************************************************************** +#define AM_HAL_SCARD_DIR_MSB 0x3F //(H)LHHL LLL LLH, state L encodes value 1, msb +#define AM_HAL_SCARD_DIR_LSB 0x3B //(H)LHHL HHH LLH, state H encodes value 1, lsb + +//***************************************************************************** +// +// Informations provided by T0 +// +//***************************************************************************** +#define AM_HAL_SCARD_T0_BIT_TA1_MASK (1 << 4) +#define AM_HAL_SCARD_T0_BIT_TB1_MASK (1 << 5) +#define AM_HAL_SCARD_T0_BIT_TC1_MASK (1 << 6) +#define AM_HAL_SCARD_T0_BIT_TD1_MASK (1 << 7) + +#define AM_HAL_SCARD_TA1_PRESENCE(T0) (((T0) & AM_HAL_SCARD_T0_BIT_TA1_MASK) == AM_HAL_SCARD_T0_BIT_TA1_MASK) +#define AM_HAL_SCARD_TB1_PRESENCE(T0) (((T0) & AM_HAL_SCARD_T0_BIT_TB1_MASK) == AM_HAL_SCARD_T0_BIT_TB1_MASK) +#define AM_HAL_SCARD_TC1_PRESENCE(T0) (((T0) & AM_HAL_SCARD_T0_BIT_TC1_MASK) == AM_HAL_SCARD_T0_BIT_TC1_MASK) +#define AM_HAL_SCARD_TD1_PRESENCE(T0) (((T0) & AM_HAL_SCARD_T0_BIT_TD1_MASK) == AM_HAL_SCARD_T0_BIT_TD1_MASK) + +#define AM_HAL_SCARD_HISTORY_LEN(T0) ((T0)&0x0F) + +//***************************************************************************** +// +// Protocol type T +// +//***************************************************************************** +#define AM_HAL_SCARD_PROTOCOL_T0 0 +#define AM_HAL_SCARD_PROTOCOL_T1 1 +#define AM_HAL_SCARD_PROTOCOL_T15 15 + +#define AM_HAL_SCARD_PROTOCOL_DEFAULT AM_HAL_SCARD_PROTOCOL_T0 + +//***************************************************************************** +// +// Structure and content of PPS request and PPS confirm +// +//***************************************************************************** +#define AM_HAL_SCARD_CLA_PPS 0xFF + +#define AM_HAL_SCARD_PPS1_PRESENCE(PPS0) (((PPS0) & (1 << 4)) == (1 << 4)) +#define AM_HAL_SCARD_PPS2_PRESENCE(PPS0) (((PPS0) & (1 << 5)) == (1 << 5)) +#define AM_HAL_SCARD_PPS3_PRESENCE(PPS0) (((PPS0) & (1 << 6)) == (1 << 6)) + +//***************************************************************************** +// +// Informations provided by TA1 +// +//***************************************************************************** +#define AM_HAL_SCARD_FI(TA1) (((TA1) >> 4) & 0x0F) +#define AM_HAL_SCARD_DI(TA1) (((TA1) >> 0) & 0x0F) + +#define AM_HAL_SCARD_FI_DI_DEFAULT 0x11 + +//***************************************************************************** +// +// Informations provided by TDi +// +//***************************************************************************** +#define AM_HAL_SCARD_TDi_BIT_TAiP1_MASK (1 << 4) +#define AM_HAL_SCARD_TDi_BIT_TBiP1_MASK (1 << 5) +#define AM_HAL_SCARD_TDi_BIT_TCiP1_MASK (1 << 6) +#define AM_HAL_SCARD_TDi_BIT_TDiP1_MASK (1 << 7) + +#define AM_HAL_SCARD_TAiP1_PRESENCE(TDi) (((TDi) & AM_HAL_SCARD_TDi_BIT_TAiP1_MASK) == AM_HAL_SCARD_TDi_BIT_TAiP1_MASK) +#define AM_HAL_SCARD_TBiP1_PRESENCE(TDi) (((TDi) & AM_HAL_SCARD_TDi_BIT_TBiP1_MASK) == AM_HAL_SCARD_TDi_BIT_TBiP1_MASK) +#define AM_HAL_SCARD_TCiP1_PRESENCE(TDi) (((TDi) & AM_HAL_SCARD_TDi_BIT_TCiP1_MASK) == AM_HAL_SCARD_TDi_BIT_TCiP1_MASK) +#define AM_HAL_SCARD_TDiP1_PRESENCE(TDi) (((TDi) & AM_HAL_SCARD_TDi_BIT_TDiP1_MASK) == AM_HAL_SCARD_TDi_BIT_TDiP1_MASK) + +#define AM_HAL_SCARD_PROTOCOL_TYPE(TDi) ((TDi) & 0x0F) + +#define AM_HAL_SCARD_MAX_ATR_LENGTH 33 //1+32 +#define AM_HAL_SCARD_MAX_PPS_LENGTH 6 +#define AM_HAL_SCARD_APDU_HEADER_LENGTH 5 +#define AM_HAL_SCARD_SW_LENGTH 2 + +//***************************************************************************** +// +// TypeDefs +// +//***************************************************************************** +typedef struct +{ + uint8_t pps0; + uint8_t pps1; + uint8_t pps2; + uint8_t pps3; +}am_hal_scard_pps_t; + +typedef struct +{ + uint8_t cla; + uint8_t ins; + uint8_t p1; + uint8_t p2; + uint8_t p3; +}am_hal_scard_header_t; + +typedef struct +{ + am_hal_scard_header_t header; + uint8_t data[256]; +}am_hal_scard_tpdu_t; + +typedef union +{ + struct + { + uint8_t s0; + uint8_t s1; + }element; + + uint16_t entirety; +}am_hal_scard_sw_t; + +typedef enum +{ + AM_HAL_SCARD_CONV_AUTO, + AM_HAL_SCARD_CONV_LSB_0X3B, + AM_HAL_SCARD_CONV_MSB_0X3F +}am_hal_scard_cardformat_e; + +typedef enum +{ + AM_HAL_SCARD_EVEN, + AM_HAL_SCARD_ODD +}am_hal_scard_parity_e; + +typedef enum +{ + AM_HAL_SCARD_APDU_CLA, + AM_HAL_SCARD_APDU_INS, + AM_HAL_SCARD_APDU_P1, + AM_HAL_SCARD_APDU_P2, + AM_HAL_SCARD_APDU_LC +}am_hal_scard_apdu_header_e; + +//***************************************************************************** +// +// Definitions +// +//***************************************************************************** +#define SCARD_RST_LOW_TIME 42000 + +#define AM_HAL_SCARD_PARITY_ENABLE 0x10 + +//***************************************************************************** +// +// SCARD configuration options. +// +//***************************************************************************** +typedef struct +{ + // + // Standard SCARD options. + // + uint32_t ui32Fidi; + uint32_t ui32Protocol; + uint32_t ui32Direction; + uint32_t ui32Parity; + uint32_t ui32GuardTime; + uint32_t ui32ClkLevel; + + // + // Timeouts + // + uint32_t ui32TxTimeout; + uint32_t ui32RxTimeout; + + // + // Buffers + // + uint8_t *pui8TxBuffer; + uint32_t ui32TxBufferSize; + uint8_t *pui8RxBuffer; + uint32_t ui32RxBufferSize; +} +am_hal_scard_config_t; + +typedef enum +{ + AM_HAL_SCARD_REQ_ACTIVATE = 0, + AM_HAL_SCARD_REQ_DEACTIVATE, + AM_HAL_SCARD_REQ_BAUDRATE, + AM_HAL_SCARD_REQ_CARD_FORMAT, + AM_HAL_SCARD_REQ_PARITY, + AM_HAL_SCARD_REQ_PROTOCOL, + AM_HAL_SCARD_REQ_GUARDTIME, + AM_HAL_SCARD_REQ_CLK_START, + AM_HAL_SCARD_REQ_CLK_STOP, + AM_HAL_SCARD_REQ_MAX +}am_hal_scard_request_e; + +//***************************************************************************** +// +// @brief SCARD transfer structure. +// +// This structure describes a SCARD transaction that can be performed by \e +// am_hal_scard_transfer() +// +//***************************************************************************** +typedef struct +{ + //! Determines whether data should be read or written. + //! + //! Should be either AM_HAL_SCARD_WRITE or AM_HAL_SCARD_READ + uint32_t ui32Direction; + + //! Pointer to data to be sent, or space to fill with received data. + uint8_t *pui8Data; + + //! Number of bytes to send or receive. + uint32_t ui32NumBytes; + + //! Timeout in milliseconds. + //! + //! Given a timeout value, the \e am_hal_scard_transfer() function will keep + //! trying to transfer data until either the number of bytes is satisfied, + //! or the time runs out. If provided with a value of zero, the transfer + //! function will only send as much data as it can immediately deal with. + //! If provided with a timeout value of \e AM_HAL_SCARD_WAIT_FOREVER, the + //! function will block until either the final "read" byte is received or + //! the final "write" byte is placed in the output buffer. + uint32_t ui32TimeoutMs; + + //! Number of bytes successfully transferred. + uint32_t *pui32BytesTransferred; +} +am_hal_scard_transfer_t; + +//***************************************************************************** +// +// Scard transfer options. +// +//***************************************************************************** +#define AM_HAL_SCARD_WRITE 1 +#define AM_HAL_SCARD_READ 0 +#define AM_HAL_SCARD_WAIT_MAX_TIME 0xFFFF +#define AM_HAL_SCARD_WAIT_FOREVER 0xFFFFFFFF +#define AM_HAL_SCARD_CLK_FREQ 3000000 + +//***************************************************************************** +// +// SCARD interrupts. +// +//***************************************************************************** +#define AM_HAL_SCARD_INT_FHFEN SCARD_IER_FHFEN_Msk +#define AM_HAL_SCARD_INT_FT2RENDEN SCARD_IER_FT2RENDEN_Msk +#define AM_HAL_SCARD_INT_PEEN SCARD_IER_PEEN_Msk +#define AM_HAL_SCARD_INT_OVREN SCARD_IER_OVREN_Msk +#define AM_HAL_SCARD_INT_FEREN SCARD_IER_FEREN_Msk +#define AM_HAL_SCARD_INT_TBERBFEN SCARD_IER_TBERBFEN_Msk +#define AM_HAL_SCARD_INT_FNEEN SCARD_IER_FNEEN_Msk +#define AM_HAL_SCARD_INT_SYNCENDEN SCARD_IER1_SYNCENDEN_Msk +#define AM_HAL_SCARD_INT_PRLEN SCARD_IER1_PRLEN_Msk +#define AM_HAL_SCARD_INT_ECNTOVEREN SCARD_IER1_ECNTOVEREN_Msk +#define AM_HAL_SCARD_INT_ALL 0xFFFFFFFF + +//***************************************************************************** +// +//! @name SCARD Status Register +//! @brief Macro definitions for SCARD Status Register Bits. +// +//***************************************************************************** +#define AM_HAL_SCARD_SR_TX_EMPTY (_VAL2FLD(SCARD_SR_TBERBF, 1)) +#define AM_HAL_SCARD_SR_RX_FULL (_VAL2FLD(SCARD_SR_TBERBF, 1)) +#define AM_HAL_SCARD_SR_RX_HALF_FULL (_VAL2FLD(SCARD_SR_FHF, 1)) +#define AM_HAL_SCARD_SR_RX_NOT_EMPTY (_VAL2FLD(SCARD_SR_FNE, 1)) +#define AM_HAL_SCARD_SR_FT2REND (_VAL2FLD(SCARD_SR_FT2REND, 1)) +#define AM_HAL_SCARD_SR_IDLE (_VAL2FLD(SCARD_SR1_IDLE, 1)) + +//***************************************************************************** +// +// SCC FIFO size for Apollo3. +// +//***************************************************************************** +#define AM_HAL_SCARD_FIFO_MAX 8 + +//***************************************************************************** +// +//! @brief Initialize the SCARD interface. +//! +//! @param ui32Module is the module number for the SCARD to initialize. +//! @param ppHandle is the location to write the SCARD handle. +//! +//! This function sets internal tracking variables associated with a specific +//! SCARD module. It should be the first SCARD API called for each SCARD module in +//! use. The handle can be used to interact with the SCARD +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_initialize(uint32_t ui32Module, void **ppHandle); + +//***************************************************************************** +// +//! @brief Deinitialize the SCARD interface. +//! +//! @param pHandle is a previously initialized SCARD handle. +//! +//! This function effectively disables future calls to interact with the SCARD +//! refered to by \e pHandle. The user may call this function if SCARD operation +//! is no longer desired. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_deinitialize(void *pHandle); + +//***************************************************************************** +// +//! @brief Change the power state of the SCARD module. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param ePowerstate is the desired power state of the SCARD. +//! @parame bRetainState is a flag to ask the HAL to save SCARD registers. +//! +//! This function can be used to switch the power to the SCARD on or off. If \e +//! bRetainState is true during a powerdown operation, it will store the SCARD +//! configuration registers to SRAM, so it can restore them on power-up. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState); + +//***************************************************************************** +// +//! @brief Used to configure basic SCARD settings. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param psConfig is a structure of SCARD configuration options. +//! +//! This function takes the options from an \e am_hal_scard_config_t structure, +//! and applies them to the SCARD referred to by \e pHandle. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_configure(void *pHandle, + am_hal_scard_config_t *psConfig); + +//***************************************************************************** +// +//! @brief Transfer data through the SCARD interface. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param am_hal_scard_transfer_t is a structure describing the operation. +//! +//! This function executes a transaction as described by the \e +//! am_hal_scard_transfer_t structure. It can either read or write, and it will +//! take advantage of any buffer space provided by the \e +//! am_hal_scard_configure() function. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_transfer(void *pHandle, + const am_hal_scard_transfer_t *pTransfer); + + +//***************************************************************************** +// +//! @brief Wait for the SCARD TX to become idle +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! +//! This function waits (polling) for all data in the SCARD TX FIFO and SCARD TX +//! buffer (if configured) to be fully sent on the physical SCARD interface. +//! This is not the most power-efficient way to wait for SCARD idle, but it can be +//! useful in simpler applications, or where power-efficiency is less important. +//! +//! Once this function returns, the SCARD can be safely disabled without +//! interfering with any previous transmissions. +//! +//! For a more power-efficient way to shut down the SCARD, check the +//! \e am_hal_scard_interrupt_service() function. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_tx_flush(void *pHandle); + +//***************************************************************************** +// +//! @brief This function handles the SCARD buffers during SCARD interrupts. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param ui32Status is the interrupt status at the time of ISR entry. +//! @param pui32ScardTxIdle can be used to store the SCARD idle status. +//! +//! The main purpose of this function is to manage the SCARD buffer system. Any +//! buffers configured by \e am_hal_scard_buffer_configure will be managed by +//! this service routine. Data queued for transmit will be added to the SCARD TX +//! FIFO as space allows, and data stored in the SCARD RX FIFO will be copied +//! out and stored in the RX buffer. This function will skip this transfer for +//! any buffer that has not been configured. +//! +//! In addition, this function can be used to alert the caller when the SCARD +//! becomes idle via the optional \e pui32ScardTxIdle argument. This function +//! will set this variable any time it completes its operation and the SCARD TX +//! channel is no longer in use (including both the FIFO and any configured +//! buffer). +//! +//! For RTOS-enabled cases, this function does not necessarily need to be +//! called inside the actual ISR for the SCARD, but it should be called promptly +//! in response to the receipt of a SCARD TX, RX, or RX timeout interrupt. If +//! the service routine is not called quickly enough, the caller risks an RX +//! FIFO overflow (data can be lost here), or a TX FIFO underflow (usually not +//! harmful). +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_interrupt_service(void *pHandle, + uint32_t ui32Status, + uint32_t *pui32ScardTxIdle); + +//***************************************************************************** +// +//! @brief Enable interrupts. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param ui32IntMask is the bitmask of interrupts to enable. +//! +//! This function enables the SCARD interrupt(s) given by ui32IntMask. If +//! multiple interrupts are desired, they can be OR'ed together. +//! +//! @note This function need not be called for SCARD FIFO interrupts if the SCARD +//! buffer service provided by \e am_hal_scard_buffer_configure() and \e +//! am_hal_scard_interrupt_service() is already in use. Non-FIFO-related +//! interrupts do require the use of this function. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_SCARD_INT_FHFEN +//! AM_HAL_SCARD_INT_FT2RENDEN +//! AM_HAL_SCARD_INT_PEEN +//! AM_HAL_SCARD_INT_OVREN +//! AM_HAL_SCARD_INT_FEREN +//! AM_HAL_SCARD_INT_TBERBFEN +//! AM_HAL_SCARD_INT_FNEEN +//! AM_HAL_SCARD_INT_SYNCENDEN +//! AM_HAL_SCARD_INT_PRLEN +//! AM_HAL_SCARD_INT_ECNTOVEREN +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_interrupt_enable(void *pHandle, uint32_t ui32Index, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Disable interrupts. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param ui32IntMask is the bitmask of interrupts to disable. +//! +//! This function disables the SCARD interrupt(s) given by ui32IntMask. If +//! multiple interrupts need to be disabled, they can be OR'ed together. +//! +//! @note This function need not be called for SCARD FIFO interrupts if the SCARD +//! buffer service provided by \e am_hal_scard_buffer_configure() and \e +//! am_hal_scard_interrupt_service() is already in use. Non-FIFO-related +//! interrupts do require the use of this function. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_SCARD_INT_FHFEN +//! AM_HAL_SCARD_INT_FT2RENDEN +//! AM_HAL_SCARD_INT_PEEN +//! AM_HAL_SCARD_INT_OVREN +//! AM_HAL_SCARD_INT_FEREN +//! AM_HAL_SCARD_INT_TBERBFEN +//! AM_HAL_SCARD_INT_FNEEN +//! AM_HAL_SCARD_INT_SYNCENDEN +//! AM_HAL_SCARD_INT_PRLEN +//! AM_HAL_SCARD_INT_ECNTOVEREN +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_interrupt_disable(void *pHandle, uint32_t ui32Index, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Clear interrupt status. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param ui32IntMask is the bitmask of interrupts to clear. +//! +//! This function clears the SCARD interrupt(s) given by ui32IntMask. If +//! multiple interrupts need to be cleared, they can be OR'ed together. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_SCARD_INT_FHFEN +//! AM_HAL_SCARD_INT_FT2RENDEN +//! AM_HAL_SCARD_INT_PEEN +//! AM_HAL_SCARD_INT_OVREN +//! AM_HAL_SCARD_INT_FEREN +//! AM_HAL_SCARD_INT_TBERBFEN +//! AM_HAL_SCARD_INT_FNEEN +//! AM_HAL_SCARD_INT_SYNCENDEN +//! AM_HAL_SCARD_INT_PRLEN +//! AM_HAL_SCARD_INT_ECNTOVEREN +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_interrupt_clear(void *pHandle, uint32_t ui32Index, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Read interrupt status. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! +//! @param pui32Status is the returned interrupt status (all bits OR'ed +//! together) +//! +//! @param bEnabled determines whether to read interrupts that were not +//! enabled. +//! +//! This function reads the status the SCARD interrupt(s) if \e bEnabled is +//! true, it will only return the status of the enabled interrupts. Otherwise, +//! it will return the status of all interrupts, enabled or disabled. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_SCARD_INT_FHFEN +//! AM_HAL_SCARD_INT_FT2RENDEN +//! AM_HAL_SCARD_INT_PEEN +//! AM_HAL_SCARD_INT_OVREN +//! AM_HAL_SCARD_INT_FEREN +//! AM_HAL_SCARD_INT_TBERBFEN +//! AM_HAL_SCARD_INT_FNEEN +//! AM_HAL_SCARD_INT_SYNCENDEN +//! AM_HAL_SCARD_INT_PRLEN +//! AM_HAL_SCARD_INT_ECNTOVEREN +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. + +// +//***************************************************************************** +extern uint32_t am_hal_scard_interrupt_status_get(void *pHandle, uint32_t ui32Index, + uint32_t *pui32Status); + +extern uint32_t am_hal_scard_control(void *pHandle, am_hal_scard_request_e eReq, void *pArgs); + +typedef enum +{ + AM_HAL_SCARD_STATUS_BUS_ERROR = AM_HAL_STATUS_MODULE_SPECIFIC_START, + AM_HAL_SCARD_STATUS_RX_QUEUE_FULL, + AM_HAL_SCARD_STATUS_PROTOCAL_NOT_SUPPORT, +} +am_hal_scard_errors_t; + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_SCARD_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.c new file mode 100644 index 0000000..8a28c3e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.c @@ -0,0 +1,222 @@ +//***************************************************************************** +// +// am_hal_secure_ota.c +//! @file +//! +//! @brief Functions for secure over-the-air. +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include "am_mcu_apollo.h" + +// Local defines +#define FLASH_INVALID 0xFFFFFFFF + +// Internal OTA state information +typedef struct +{ + uint32_t flashSize; + uint32_t otaDescAddr; + uint32_t numOta; +} am_hal_secure_ota_state_t; + +static am_hal_secure_ota_state_t gSOtaState; + +// Erase a flash page +static void +erase_flash_page(uint32_t ui32ProgamKey, uint32_t ui32Addr) +{ + uint32_t ui32CurrentPage, ui32CurrentBlock; + + // + // Figure out what page and block we're working on. + // + ui32CurrentPage = AM_HAL_FLASH_ADDR2PAGE(ui32Addr); + ui32CurrentBlock = AM_HAL_FLASH_ADDR2INST(ui32Addr); + + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + am_hal_flash_page_erase(ui32ProgamKey, + ui32CurrentBlock, ui32CurrentPage); + // + // Exit the critical section. + // + AM_CRITICAL_END +} + + +//***************************************************************************** +// +//! @brief Initialize OTA state +//! +//! Initializes the OTA state. This should be called before doing any other operation +//! +//! @param ui32ProgamKey - The Flash programming key +//! @param pOtaDesc should be start of a flash page designated for OTA Descriptor +//! +//! This call will erase the flash page, which will then be incrementally +//! populated as OTA's are added. It will also initialize the OTAPOINTER to point +//! to this descriptor, marking it as invalid at the same time +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_ota_init(uint32_t ui32ProgamKey, uint32_t *pOtaDesc) +{ + am_hal_mcuctrl_device_t sDevice; + uint32_t otaDescAddr = (uint32_t)pOtaDesc; + + // + // Get chip specific info + // + am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_DEVICEID, &sDevice); + gSOtaState.flashSize = sDevice.ui32FlashSize; + + // Validate the flash page + if ((otaDescAddr >= gSOtaState.flashSize) || + (otaDescAddr & (AM_HAL_FLASH_PAGE_SIZE - 1))) + { + return AM_HAL_STATUS_INVALID_ARG; + } + // TODO - check against protected pages + // Erase the page + erase_flash_page(ui32ProgamKey, otaDescAddr); + // Initialize the OTA Pointer + MCUCTRL->OTAPOINTER = otaDescAddr; + gSOtaState.numOta = 0; + gSOtaState.otaDescAddr = otaDescAddr; + + return AM_HAL_STATUS_SUCCESS; +} + +// Add a new OTA to descriptor +//***************************************************************************** +// +//! @brief Add a new image for OTA +//! +//! Adds a new image to the OTA Descriptor. +//! +//! @param ui32ProgamKey - The Flash programming key +//! @param imageMagic image magic# identifying type of image being added to OTA descr +//! @param pImage should point to the start of new image to be added to descr +//! +//! This will program the next available entry in OTA descriptor. It will also set +//! appropriate state in the OTA pointer register +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_ota_add(uint32_t ui32ProgamKey, uint8_t imageMagic, uint32_t *pImage) +{ + uint32_t imageAddr = (uint32_t)pImage; + // Validate the Image Pointer + if ((imageAddr >= gSOtaState.flashSize) || + (imageAddr & (AM_HAL_FLASH_PAGE_SIZE - 1))) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (gSOtaState.numOta == AM_HAL_SECURE_OTA_MAX_OTA) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + imageAddr |= AM_HAL_OTA_STATUS_PENDING; + // Program the OTA Descriptor word + am_hal_flash_program_main(ui32ProgamKey, + &imageAddr, + ((uint32_t *)gSOtaState.otaDescAddr + gSOtaState.numOta++), + 1); + + // Set appropriate OTA Pointer bits + MCUCTRL->OTAPOINTER_b.OTAVALID = 1; + if (imageMagic == AM_IMAGE_MAGIC_SBL) + { + MCUCTRL->OTAPOINTER_b.OTASBLUPDATE = 1; + } + + return AM_HAL_STATUS_SUCCESS; +} + +// Get OTA Status +// Can be called anytime (generally after coming back from reset to check the status of OTA +// Will be also used by sbl_main to identify list of OTA's left for it (would show up as PENDING) +//***************************************************************************** +// +//! @brief Get Current OTA Descriptor state +//! +//! @param pOtaDesc should be start of a flash page designated for OTA Descriptor +//! @param maxOta Determines the size of the following buffer +//! @param pStatus - Return Parameter - populated by this function indicating the OTA +//! status of various OTA's +//! +//! This will retrieve the current OTA status of various images added to the OTA descr +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_get_ota_status(uint32_t *pOtaDesc, uint32_t maxOta, am_hal_ota_status_t *pStatus) +{ + uint32_t numOta = 0; + // Fill up the return structure + while (maxOta--) + { + if (pOtaDesc[numOta] == FLASH_INVALID) + { + pStatus[numOta].pImage = (uint32_t *)pOtaDesc[numOta]; + break; + } + else + { + pStatus[numOta].pImage = (uint32_t *)(pOtaDesc[numOta] & ~0x3); + pStatus[numOta].status = (am_hal_ota_status_e)(pOtaDesc[numOta] & 0x3); + } + numOta++; + } + return AM_HAL_STATUS_SUCCESS; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.h new file mode 100644 index 0000000..400ccbd --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.h @@ -0,0 +1,228 @@ +//***************************************************************************** +// +// am_hal_secure_ota.h +//! @file +//! +//! @brief Functions for secure over-the-air. +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_SECURE_OTA_H +#define AM_HAL_SECURE_OTA_H +// Ambiq Standard Image Format related definitions +// Magic Numbers +#define AM_IMAGE_MAGIC_SBL 0xA3 +#define AM_IMAGE_MAGIC_AM3P 0x3A +#define AM_IMAGE_MAGIC_PATCH 0xAF +#define AM_IMAGE_MAGIC_MAIN 0xC0 +#define AM_IMAGE_MAGIC_CHILD 0xCC +#define AM_IMAGE_MAGIC_NONSECURE 0xCB +#define AM_IMAGE_MAGIC_INFO0 0xCF + +// First 30 words of the image headers follow similar pattern +typedef struct +{ + union + { + uint32_t ui32; + struct + { + uint32_t blobSize : 20; + uint32_t resvd : 3; + uint32_t encrypted : 1; + uint32_t magicNum : 8; + } s; + } w0; + uint32_t crc; + union + { + uint32_t ui32; + struct + { + uint32_t authAlgo : 4; + uint32_t authKeyIdx : 4; + uint32_t encAlgo : 4; + uint32_t keyIdx : 4; + uint32_t resvd3 : 8; + uint32_t crcBoot : 1; + uint32_t authBoot : 1; + uint32_t resvd2 : 2; + uint32_t crcInstall : 1; + uint32_t authInstall : 1; + uint32_t resvd1 : 2; + } s; + } w2; + uint32_t w3; + uint32_t signature[8]; // w4-11 + uint32_t iv[4]; // w12-w15 + uint32_t kek[4]; // w16-w19 + uint32_t signatureClear[8]; // w20-w27 + union + { + uint32_t ui32; + struct + { + uint32_t offsetWords : 16; + uint32_t sizeWords : 16; + } info0; + struct + { + uint32_t encap : 1; + uint32_t resvd : 1; + uint32_t loadAddrMsb : 30; + } s1; + struct + { + uint32_t writeProtect : 1; + uint32_t copyProtect : 1; + uint32_t loadAddrMsb : 30; + } s; + } addrWord; // w28 + union + { + uint32_t ui32; + uint32_t resv; + uint32_t key; // For info + struct + { + uint32_t version : 15; + uint32_t erasePrev : 1; + uint32_t resv : 16; + } s; + } versionKeyWord; // w29 +} am_image_hdr_common_t; + +// Bitmask used to clear encrypted status in flash +#define AM_IMAGE_BITMASK_ENCRYPTED 0x00800000 +// Number of most significant bits in w28 used for load address +#define AM_IMAGE_LOAD_ADDR_MSB_BITS 30 + +#define AM_IMAGE_GET_LOADADDR(common) (((am_image_hdr_common_t *)(common))->addrWord.s.loadAddrMsb << (32 - AM_IMAGE_LOAD_ADDR_MSB_BITS)) + +#define AM_IMAGE_NUM_TRAILING_WORDS_TO_256 ((256 - sizeof(am_image_hdr_common_t))/4) +#define AM_IMAGE_MAX_CHILD_IMAGE AM_IMAGE_NUM_TRAILING_WORDS_TO_256 + +typedef struct +{ + am_image_hdr_common_t common; + uint32_t childPtr[AM_IMAGE_MAX_CHILD_IMAGE]; +} am_main_image_hdr_t; + +typedef struct +{ + am_image_hdr_common_t common; + uint32_t featureKey; + uint32_t resvd[1]; +} am_thirdparty_image_hdr_t; + +typedef struct +{ + am_image_hdr_common_t common; + uint32_t resvd[AM_IMAGE_NUM_TRAILING_WORDS_TO_256]; +} am_sbl_image_hdr_t; + +// Reserved magic numbers allowed to be used by customer's own bootloader +#define AM_IMAGE_MAGIC_CUST(x) ((((x) & 0xF0) == 0xC0) && ((x) != 0xC0) && ((x) != 0xCC) && ((x) != 0xCB) && ((x) != 0xCF)) + +// OTA Upgrade related definitions + +// Maximum number of OTAs +#define AM_HAL_SECURE_OTA_MAX_OTA 8 + +// OTA Protocol between OTA application and SecureBoot +// OTAPOINTER will be initialized as follows: +// Most significant 30 bits will correspond to most significant 30 bits of OTA Descriptor +// Least Significant bit (bit 0) should be initialized to 1 to indicate a valid OTA Descriptor +// bit 1 should be initialized to 1 to indicate that the list contains an SBL OTA +// OTA Descriptor points to a list of entries, each corresponding to an OTA blob, list terminating in 0xFFFFFFFF +// Each list entry word comprises of following: +// Most significant 30 bits will correspond to most significant 30 bits of OTA blob pointer +// Blob pointer needs to be aligned to Flash Page boundary (8K) +// Least Significant 2 bits should be initialized to 1 to indicate a valid OTA Pending +// After Secboot processes an OTA, it clears the least significant bit (bit 0) +// bit 1 indicates the status of the OTA - 0 for Success, 1 for Failure +#define AM_HAL_SECURE_OTA_OTA_VALID_MASK 0x3 +#define AM_HAL_SECURE_OTA_OTA_GET_BLOB_PTR(ptr) ((uint32_t)(ptr) & ~AM_HAL_SECURE_OTA_OTA_VALID_MASK) +#define AM_HAL_SECURE_OTA_OTA_IS_VALID(ptr) (((uint32_t)(ptr) & AM_HAL_SECURE_OTA_OTA_VALID_MASK) == AM_HAL_SECURE_OTA_OTA_VALID_MASK) +#define AM_HAL_SECURE_OTA_OTA_LIST_END_MARKER 0xFFFFFFFF + +// Bitmasks signifying the bit to be cleared for OTA success/failure +#define AM_HAL_SECURE_OTA_OTA_DONE_FAILURE_CLRMASK 0x1 +#define AM_HAL_SECURE_OTA_OTA_DONE_SUCCESS_CLRMASK 0x3 + + +// OTA Status +typedef enum +{ + AM_HAL_OTA_STATUS_SUCCESS = 0x0, + AM_HAL_OTA_STATUS_ERROR = 0x1, // This should never happen + AM_HAL_OTA_STATUS_FAILURE = 0x2, + AM_HAL_OTA_STATUS_PENDING = 0x3, +} am_hal_ota_status_e; + +// Per Image OTA Status information +typedef struct +{ + uint32_t *pImage; + am_hal_ota_status_e status; +} am_hal_ota_status_t; + +// pOtaDesc should be start of a flash page designated for OTA Descriptor +// This call will erase the flash page, which will then be incrementally populated as OTA's are added +// It will also initialize the OTAPOINTER to point to this descriptor, with LSB indicating it as invalid +uint32_t am_hal_ota_init(uint32_t ui32ProgamKey, uint32_t *pOtaDesc); + +// Add a new OTA to descriptor +// This will program the next available entry in OTA descriptor +// Will also set the valid/sbl flags in OTA pointer register +uint32_t am_hal_ota_add(uint32_t ui32ProgamKey, uint8_t imageMagic, uint32_t *pImage); + +// Get OTA Status +// Can be called anytime (generally after coming back from reset to check the status of OTA +// Will be also used by sbl_main to identify list of OTA's left for it (would show up as PENDING) +uint32_t am_hal_get_ota_status(uint32_t *pOtaDesc, uint32_t maxOta, am_hal_ota_status_t *pStatus); + +#endif // AM_HAL_SECURE_OTA_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.c new file mode 100644 index 0000000..adc71cb --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.c @@ -0,0 +1,573 @@ +//***************************************************************************** +// +// am_hal_security.c +//! @file +//! +//! @brief Functions for on-chip security features +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// Local defines. +//***************************************************************************** +// +// ENABLE_EXTMEM_CRC +// By default, the CRC engine can only operate on data located in internal +// memory (i.e. flash or SRAM). This define enables am_hal_crc() to support +// external memories, but requires a small amount of global SRAM allocated for +// that purpose. If it is not desired to support this feature, set to 0. +// +#define ENABLE_EXTMEM_CRC 1 + +// +// Maximum iterations for hardware CRC to finish +// +#define MAX_CRC_WAIT 100000 + +#define AM_HAL_SECURITY_LOCKSTAT_CUSTOMER 0x1 +#define AM_HAL_SECURITY_LOCKSTAT_RECOVERY 0x40000000 + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +#if ENABLE_EXTMEM_CRC +// +// Set up a small global buffer that can be used am_hal_crc32() when +// computing CRCs on external memory. +// +#define CRC_XFERBUF_SZ (512) // Reserve 512 bytes for the buffer +static uint32_t g_CRC_buffer[CRC_XFERBUF_SZ / 4]; +#endif // ENABLE_EXTMEM_CRC + +// +// Assign ptr variables to avoid an issue with GCC reading from location 0x0. +// +const volatile uint32_t *g_pFlash0 = (uint32_t*)(AM_HAL_SBL_ADDRESS + 0); +const volatile uint32_t *g_pFlash4 = (uint32_t*)(AM_HAL_SBL_ADDRESS + 4); + +//***************************************************************************** +// +//! @brief Hardcoded function - to Run supplied main program +//! +//! @param r0 = vtor - address of the vector table +//! +//! @return Returns None +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +static __asm void +bl_run_main(uint32_t *vtor) +{ + // + // Store the vector table pointer of the new image into VTOR. + // + movw r3, #0xED08 + movt r3, #0xE000 + str r0, [r3, #0] + + // + // Load the new stack pointer into R1 and the new reset vector into R2. + // + ldr r3, [r0, #0] + ldr r2, [r0, #4] + + // + // Set the stack pointer for the new image. + // + mov sp, r3 + + // + // Jump to the new reset vector. + // + bx r2 +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +__attribute__((naked)) +static void +bl_run_main(uint32_t *vtor) +{ + __asm + ( + " movw r3, #0xED08\n\t" // Store the vector table pointer of the new image into VTOR. + " movt r3, #0xE000\n\t" + " str r0, [r3, #0]\n\t" + " ldr r3, [r0, #0]\n\t" // Load the new stack pointer into R1 and the new reset vector into R2. + " ldr r2, [r0, #4]\n\t" + " mov sp, r3\n\t" // Set the stack pointer for the new image. + " bx r2\n\t" // Jump to the new reset vector. + ); +} +#elif defined(__GNUC_STDC_INLINE__) +__attribute__((naked)) +static void +bl_run_main(uint32_t *vtor) +{ + __asm + ( + " movw r3, #0xED08\n\t" // Store the vector table pointer of the new image into VTOR. + " movt r3, #0xE000\n\t" + " str r0, [r3, #0]\n\t" + " ldr r3, [r0, #0]\n\t" // Load the new stack pointer into R1 and the new reset vector into R2. + " ldr r2, [r0, #4]\n\t" + " mov sp, r3\n\t" // Set the stack pointer for the new image. + " bx r2\n\t" // Jump to the new reset vector. + ); +} +#elif defined(__IAR_SYSTEMS_ICC__) +__stackless static inline void +bl_run_main(uint32_t *vtor) +{ + __asm volatile ( + " movw r3, #0xED08\n" // Store the vector table pointer of the new image into VTOR. + " movt r3, #0xE000\n" + " str r0, [r3, #0]\n" + " ldr r3, [r0, #0]\n" // Load the new stack pointer into R1 and the new reset vector into R2. + " ldr r2, [r0, #4]\n" + " mov sp, r3\n" // Set the stack pointer for the new image. + " bx r2\n" // Jump to the new reset vector. + ); +} +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +// Pre- SBLv2 known versions that do not support callback +static uint32_t sblPreV2[][4] = { + // flash0, flash4, sblVersion, sblVersionAddInfo + {0xA3007860, 0x2E2638FB, 0 , 0}, + {0xA3007E14, 0x5EE4E461, 1 , 0}, + {0xA3008290, 0xB49CECD5, 2 , 0}, +}; + +//***************************************************************************** +// +//! @brief Get Device Security Info +//! +//! @param pSecInfo - Pointer to structure for returned security info +//! +//! This will retrieve the security information for the device +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_get_info(am_hal_security_info_t *pSecInfo) +{ + uint32_t flash0; + uint32_t flash4; + uint32_t i; + bool bSbl; + if (!pSecInfo) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + pSecInfo->info0Version = AM_REGVAL(0x50020040); + pSecInfo->bInfo0Valid = MCUCTRL->SHADOWVALID_b.INFO0_VALID; + bSbl = MCUCTRL->BOOTLOADER_b.SECBOOTFEATURE; + + if (bSbl) + { + // Check if we're running pre-SBLv2 + flash0 = *g_pFlash0; + flash4 = *g_pFlash4; + // Check if SBL is installed + if ((flash0 >> 24) != AM_IMAGE_MAGIC_SBL) + { + return AM_HAL_STATUS_FAIL; + } + for ( i = 0; i < sizeof(sblPreV2) / sizeof(sblPreV2[0]); i++ ) + { + if ((sblPreV2[i][0] == flash0) && (sblPreV2[i][1] == flash4)) + { + // This is a device prior to SBLv2 + pSecInfo->sblVersion = sblPreV2[i][2]; + pSecInfo->sblVersionAddInfo = sblPreV2[i][3]; + break; + } + } + + if ( i == sizeof(sblPreV2) / sizeof(sblPreV2[0]) ) + { + // SBLv2 or beyond + // Use SBL jump table function + uint32_t status; + uint32_t sblVersion; + uint32_t (*pFuncVersion)(uint32_t *) = (uint32_t (*)(uint32_t *))(AM_HAL_SBL_ADDRESS + 0x1D1); + status = pFuncVersion(&sblVersion); + if (status != AM_HAL_STATUS_SUCCESS) + { + return status; + } + pSecInfo->sblVersion = sblVersion & 0x7FFF; + pSecInfo->sblVersionAddInfo = sblVersion >> 15; + } + } + else + { + return AM_HAL_STATUS_FAIL; + } + return AM_HAL_STATUS_SUCCESS; +} // am_hal_security_get_info() + +//***************************************************************************** +// +//! @brief Set the key for specified lock +//! +//! @param lockType - The lock type to be operated upon +//! @param pKey - Pointer to 128b key value +//! +//! This will program the lock registers for the specified lock and key +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_set_key(am_hal_security_locktype_t lockType, am_hal_security_128bkey_t *pKey) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (pKey == NULL) + { + return AM_HAL_STATUS_INVALID_ARG; + } + switch (lockType) + { + case AM_HAL_SECURITY_LOCKTYPE_CUSTOMER: + case AM_HAL_SECURITY_LOCKTYPE_RECOVERY: + break; + default: + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + SECURITY->LOCKCTRL = lockType; + SECURITY->KEY0 = pKey->keys.key0; + SECURITY->KEY1 = pKey->keys.key1; + SECURITY->KEY2 = pKey->keys.key2; + SECURITY->KEY3 = pKey->keys.key3; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_security_set_key() + +//***************************************************************************** +// +//! @brief Get the current status of the specified lock +//! +//! @param lockType - The lock type to be operated upon +//! @param pbUnlockStatus - Pointer to return variable with lock status +//! +//! This will get the lock status for specified lock - true implies unlocked +//! Note that except for customer lock, other locks are self-locking on status read +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_get_lock_status(am_hal_security_locktype_t lockType, bool *pbUnlockStatus) +{ + uint32_t unlockMask; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (pbUnlockStatus == NULL) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + switch (lockType) + { + case AM_HAL_SECURITY_LOCKTYPE_CUSTOMER: + unlockMask = AM_HAL_SECURITY_LOCKSTAT_CUSTOMER; + break; + case AM_HAL_SECURITY_LOCKTYPE_RECOVERY: + unlockMask = AM_HAL_SECURITY_LOCKSTAT_RECOVERY; + break; + default: + return AM_HAL_STATUS_INVALID_ARG; + } + *pbUnlockStatus = SECURITY->LOCKSTAT & unlockMask; + return AM_HAL_STATUS_SUCCESS; +} // am_hal_security_get_lock_status() + +//***************************************************************************** +// +//! @brief Compute CRC32 for a specified payload +//! +//! @param ui32StartAddr - The start address of the payload. +//! @param ui32SizeBytes - The length of payload in bytes. +//! @param pui32Crc - Pointer to variable to return the computed CRC. +//! +//! This function uses the hardware engine to compute CRC32 on an arbitrary data +//! payload. The payload can reside in any contiguous memory including external +//! memory. +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t +am_hal_crc32(uint32_t ui32StartAddr, uint32_t ui32SizeBytes, uint32_t *pui32Crc) +{ + uint32_t status, ui32CRC32; + bool bInternal; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (pui32Crc == NULL) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Make sure size is multiple of 4 bytes + // + if (ui32SizeBytes & 0x3) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + status = AM_HAL_STATUS_OUT_OF_RANGE; // Default status + + // + // Determine whether the startaddr is in internal flash or SRAM. + // + bInternal = ISADDRFLASH(ui32StartAddr) || ISADDRSRAM(ui32StartAddr); + + if ( bInternal ) + { + // + // Program the CRC engine to compute the crc + // + ui32CRC32 = 0xFFFFFFFF; + SECURITY->RESULT = ui32CRC32; + SECURITY->SRCADDR = ui32StartAddr; + SECURITY->LEN = ui32SizeBytes; + SECURITY->CTRL_b.FUNCTION = SECURITY_CTRL_FUNCTION_CRC32; + + // + // Start the CRC + // + SECURITY->CTRL_b.ENABLE = 1; + + // + // Wait for CRC to finish + // + status = am_hal_flash_delay_status_change(MAX_CRC_WAIT, + (uint32_t)&SECURITY->CTRL, SECURITY_CTRL_ENABLE_Msk, 0); + + if (status == AM_HAL_STATUS_SUCCESS) + { + *pui32Crc = SECURITY->RESULT; + } + + return status; + } + +#if ENABLE_EXTMEM_CRC + uint32_t ui32XferSize, ui32cnt; + uint32_t *pui32Buf, *pui32Data; + + // + // If we're here, the source data resides in non-internal memory (that is, + // not flash or SRAM). + // + // Begin the loop for computing the CRC of the external memory. The data + // will first be copied to the SRAM buffer. + // + // Program the parts of the CRC engine that will not need to change + // inside the loop: SRCADDR, FUNCTION, initial seed in RESULT. + // While inside the loop, only the LEN will need to be provided. + // + SECURITY->SRCADDR = (uint32_t)&g_CRC_buffer[0]; + SECURITY->CTRL_b.FUNCTION = SECURITY_CTRL_FUNCTION_CRC32; + + // + // During the loop the RESULT register must not be rewritten, even if the + // value written on each pass is identical. Rewriting it appears to reset + // a state machine such that an incorrect CRC value is computed. + // + ui32CRC32 = 0xFFFFFFFF; + SECURITY->RESULT = ui32CRC32; + + pui32Data = (uint32_t*)ui32StartAddr; + while ( ui32SizeBytes ) + { + // + // First copy a chunk of payload data to SRAM where the CRC engine + // can operate on it. + // + ui32XferSize = (ui32SizeBytes >= CRC_XFERBUF_SZ) ? + CRC_XFERBUF_SZ : ui32SizeBytes; + ui32SizeBytes -= ui32XferSize; + ui32cnt = ui32XferSize / 4; + pui32Buf = &g_CRC_buffer[0]; + while ( ui32cnt-- ) + { + *pui32Buf++ = *pui32Data++; + } + + // + // Program the CRC engine's LEN parameter. + // All other parameters were preprogrammed: SRCADDR, FUNCTION, RESULT. + // + SECURITY->LEN = ui32XferSize; + + // + // Start the CRC + // + SECURITY->CTRL_b.ENABLE = 1; + + // + // Wait for CRC to finish + // + status = am_hal_flash_delay_status_change(MAX_CRC_WAIT, + (uint32_t)&SECURITY->CTRL, SECURITY_CTRL_ENABLE_Msk, 0); + + if ( (status == AM_HAL_STATUS_SUCCESS) && !SECURITY->CTRL_b.CRCERROR ) + { + ui32CRC32 = SECURITY->RESULT; + } + else if ( SECURITY->CTRL_b.CRCERROR ) + { + return AM_HAL_STATUS_HW_ERR; + } + else + { + // + // Error from status_change function. + // Return the CRC value we do have, but return an error. + // + //return status; + break; + } + } + + // + // Return result to caller + // + *pui32Crc = ui32CRC32; +#endif // ENABLE_EXTMEM_CRC + + return status; + +} // am_hal_crc32() + +//***************************************************************************** +// +//! @brief Helper function to Perform exit operations for a secondary bootloader +//! +//! @param pImage - The address of the image to give control to +//! +//! This function does the necessary security operations while exiting from a +//! a secondary bootloader program. If still open, it locks the info0 key region, +//! as well as further updates to the flash protection register. +//! It also checks if it needs to halt to honor a debugger request. +//! If an image address is specified, control is transferred to the same on exit. +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success, if no image address specified +//! If an image address is provided, a successful execution results in transfer to +//! the image - and this function does not return. +// +//***************************************************************************** +uint32_t am_hal_bootloader_exit(uint32_t *pImage) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + + // + // Lock the assets + // + if ( MCUCTRL->SHADOWVALID_b.INFO0_VALID && + MCUCTRL->BOOTLOADER_b.PROTLOCK ) + { + am_hal_security_128bkey_t keyVal; + uint32_t *pCustKey = (uint32_t *)0x50021A00; + bool bLockStatus; + + // + // PROTLOCK Open + // This should also mean that Customer key is accessible + // Now lock the key by writing an incorrect value + // + keyVal.keyword[0] = ~pCustKey[0]; + am_hal_security_set_key(AM_HAL_SECURITY_LOCKTYPE_CUSTOMER, &keyVal); + + status = am_hal_security_get_lock_status(AM_HAL_SECURITY_LOCKTYPE_CUSTOMER, &bLockStatus); + + if ((status != AM_HAL_STATUS_SUCCESS) || (bLockStatus)) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Lock the protection register to prevent further region locking + // CAUTION!!! - Can not do AM_BFW on BOOTLOADER register as all writable bits in this register are Write 1 to clear + // + MCUCTRL->BOOTLOADER = _VAL2FLD(MCUCTRL_BOOTLOADER_PROTLOCK, 1); + + // + // Check if we need to halt (debugger request) + // + if (MCUCTRL->SCRATCH0 & 0x1) + { + // Debugger wants to halt + uint32_t dhcsr = AM_REGVAL(0xE000EDF0); + // Clear the flag in Scratch register + MCUCTRL->SCRATCH0 &= ~0x1; + // Halt the core + dhcsr = ((uint32_t)0xA05F << 16) | (dhcsr & 0xFFFF) | 0x3; + AM_REGVAL(0xE000EDF0) = dhcsr; + // Resume from halt + } + } + + // Give control to supplied image + if (pImage) + { + bl_run_main(pImage); + // Does not return + } + + return status; +} // am_hal_bootloader_exit() diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.h new file mode 100644 index 0000000..207cade --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.h @@ -0,0 +1,185 @@ +//***************************************************************************** +// +// am_hal_security.h +//! @file +//! +//! @brief Functions for security functions +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_SECURITY_H +#define AM_HAL_SECURITY_H + +// +// Location of SBL install address for this device +// +// Important Note: +// Some caution should be observed when using AM_HAL_SBL_ADDRESS as an address. +// GCC considers use of this address to be a NULL pointer. When compiled with +// high optimization (-O3) and used to read the location with, for example, +// code such as *((volatile uint32_t *)(AM_HAL_SBL_ADDRESS)), GCC will insert +// an instruction it calls "UDF" (undefined), op-code 0xDEFF, which will cause +// a fault on execution to trap the "invalid" null-ptr usage. +// This does not appear to be an issue with IAR and Keil ARM5. +// It is likely an issue with Keil ARM6. +// +#define AM_HAL_SBL_ADDRESS 0x00000000 + + + +typedef struct +{ + bool bInfo0Valid; + uint32_t info0Version; + uint32_t sblVersion; + uint32_t sblVersionAddInfo; +} am_hal_security_info_t; + +// LOCK Definitions +typedef enum +{ + AM_HAL_SECURITY_LOCKTYPE_CUSTOMER = 0x1, + AM_HAL_SECURITY_LOCKTYPE_RECOVERY = 0x9D, +} am_hal_security_locktype_t; + +typedef union +{ + uint32_t keyword[4]; + struct + { + uint32_t key0; + uint32_t key1; + uint32_t key2; + uint32_t key3; + } keys; +} am_hal_security_128bkey_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! @brief Get Device Security Info +//! +//! @param pSecInfo - Pointer to structure for returned security info +//! +//! This will retrieve the security information for the device +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_get_info(am_hal_security_info_t *pSecInfo); + +//***************************************************************************** +// +//! @brief Set the key for specified lock +//! +//! @param lockType - The lock type to be operated upon +//! @param pKey - Pointer to 128b key value +//! +//! This will program the lock registers for the specified lock and key +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_set_key(am_hal_security_locktype_t lockType, am_hal_security_128bkey_t *pKey); + +//***************************************************************************** +// +//! @brief Get the current status of the specified lock +//! +//! @param lockType - The lock type to be operated upon +//! @param pbUnlockStatus - Pointer to return variable with lock status +//! +//! This will get the lock status for specified lock +//! Note that except for customer lock, other locks are self-locking on status read +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_get_lock_status(am_hal_security_locktype_t lockType, bool *pbUnlockStatus); + +//***************************************************************************** +// +//! @brief Compute CRC32 for a specified payload +//! +//! @param startAddr - The start address of the payload +//! @param sizeBytes - The length of payload in bytes +//! @param pCrc - Pointer to return computed CRC +//! +//! This will use the hardware engine to compute CRC32 on an arbitrary data payload +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_crc32(uint32_t startAddr, uint32_t sizeBytes, uint32_t *pCrc); + +//***************************************************************************** +// +//! @brief Helper function to Perform exit operations for a secondary bootloader +//! +//! @param pImage - The address of the image to give control to +//! +//! This function does the necessary security operations while exiting from a +//! a secondary bootloader program. If still open, it locks the info0 key region, +//! as well as further updates to the flash protection register. +//! It also checks if it needs to halt to honor a debugger request. +//! If an image address is specified, control is transferred to the same on exit. +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success, if no image address specified +//! If an image address is provided, a successful execution results in transfer to +//! the image - and this function does not return. +// +//***************************************************************************** +uint32_t am_hal_bootloader_exit(uint32_t *pImage); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_SECURITY_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_status.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_status.h new file mode 100644 index 0000000..4bb0498 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_status.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// am_hal_status.h +//! @file +//! +//! @brief Global status return codes for HAL interface. +//! +//! @addtogroup status3 Global Status Return Codes. +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_STATUS_H +#define AM_HAL_STATUS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + // + // Global Status Returns + // + typedef enum + { + AM_HAL_STATUS_SUCCESS, + AM_HAL_STATUS_FAIL, + AM_HAL_STATUS_INVALID_HANDLE, + AM_HAL_STATUS_IN_USE, + AM_HAL_STATUS_TIMEOUT, + AM_HAL_STATUS_OUT_OF_RANGE, + AM_HAL_STATUS_INVALID_ARG, + AM_HAL_STATUS_INVALID_OPERATION, + AM_HAL_STATUS_MEM_ERR, + AM_HAL_STATUS_HW_ERR, + AM_HAL_STATUS_MODULE_SPECIFIC_START = 0x08000000, + } am_hal_status_e; + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_STATUS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.c new file mode 100644 index 0000000..cba38f8 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.c @@ -0,0 +1,642 @@ +//***************************************************************************** +// +// am_hal_stimer.c +//! @file +//! +//! @brief Functions for interfacing with the system timer (STIMER). +//! +//! @addtogroup stimer3 System Timer (STIMER) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +//! @brief Set up the stimer. +//! +//! @param ui32STimerConfig is the value to load into the configuration reg. +//! +//! This function should be used to perform the initial set-up of the +//! stimer. +//! +//! @return The 32-bit current config of the STimer Config register +// +//***************************************************************************** +uint32_t +am_hal_stimer_config(uint32_t ui32STimerConfig) +{ + uint32_t ui32CurrVal; + + // + // Read the current config + // + ui32CurrVal = CTIMER->STCFG; + + // + // Write our configuration value. + // + CTIMER->STCFG = ui32STimerConfig; + +#if AM_PART_APOLLO2 + // + // If all of the clock sources are not HFRC, disable LDO when sleeping if timers are enabled. + // + if ( (CTIMER->STCFG_b.CLKSELCTIMER->STCFG_b.CLKSEL == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16) || + (CTIMER->STCFG_b.CLKSELCTIMER->STCFG_b.CLKSEL == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256) ) + { + PWRCTRL->MISC_b.FORCEMEMVRLPTIMERS = 0; + } + else + { + PWRCTRL->MISC_b.FORCEMEMVRLPTIMERS = 1; + } +#endif + + return ui32CurrVal; +} + +//***************************************************************************** +// +//! @brief Get the current stimer value. +//! +//! This function can be used to read, uninvasively, the value in the stimer. +//! +//! @return The 32-bit value from the STimer counter register. +// +//***************************************************************************** +uint32_t +am_hal_stimer_counter_get(void) +{ + return CTIMER->STTMR; +} + +//***************************************************************************** +// +//! @brief Clear the stimer counter. +//! +//! This function clears the STimer Counter and leaves the stimer running. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_counter_clear(void) +{ + // + // Set the clear bit + // + CTIMER->STCFG |= CTIMER_STCFG_CLEAR_Msk; + + // + // Reset the clear bit + // + CTIMER->STCFG &= ~CTIMER_STCFG_CLEAR_Msk; +} + +//***************************************************************************** +// +//! @brief Set the compare value. +//! +//! @param ui32CmprInstance is the compare register instance number (0-7). +//! @param ui32Delta is the value to add to the STimer counter and load into +//! the comparator register. +//! +//! NOTE: There is no way to set an absolute value into a comparator register. +//! Only deltas added to the STimer counter can be written to the compare +//! registers. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, uint32_t ui32Delta) +{ + uint32_t cfgVal; + uint32_t numTries = 0; + + if ( ui32CmprInstance > 7 ) + { + return; + } + + // We need to disable the compare temporarily while setting the delta value + // That leaves a corner case where we could miss the trigger if setting a very + // small delta. To avoid this, we take critical section, and we should ensure + // that delta value is at least > 1 + + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + // + // Get current CFG value + // + cfgVal = CTIMER->STCFG; + + // + // Disable the compare if already enabled, when setting the new value + // + CTIMER->STCFG &= ~((AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance)); + + // In rare case the delta might not be effective + // We retry if that is the case. + // Allow for some variability in the value owing to execution latency + while (numTries++ < 4) + { + uint32_t expVal; + uint32_t expMax; + uint32_t cmpVal; + + // Expected value + expVal = CTIMER->STTMR + ui32Delta; + + // Max allowed - taking care of latency + expMax = expVal + 10; + + // + // Set the delta + // + AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta; + + // Read back the compare value + cmpVal = AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)); + + // Make sure the value is in expected range + if (!AM_HAL_U32_SMALLER(cmpVal, expVal) && !AM_HAL_U32_GREATER(cmpVal, expMax)) + { + break; + } + } + + + // + // Restore Compare Enable bit + // + CTIMER->STCFG |= cfgVal & (AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance); + + // + // End the critical section. + // + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Get the current stimer compare register value. +//! +//! @param ui32CmprInstance is the compare register instance number (0-7). +//! +//! This function can be used to read the value in an stimer compare register. +//! +//! +//! @return None. +// +//***************************************************************************** +uint32_t +am_hal_stimer_compare_get(uint32_t ui32CmprInstance) +{ + if ( ui32CmprInstance > 7 ) + { + return 0; + } + + return AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)); +} + +//***************************************************************************** +// +//! @brief Start capturing data with the specified capture register. +//! +//! @param ui32CaptureNum is the Capture Register Number to read (0-3). +//! @param ui32GPIONumber is the pin number. +//! @param bPolarity: false (0) = Capture on low to high transition. +//! true (1) = Capture on high to low transition. +//! +//! Use this function to start capturing. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_capture_start(uint32_t ui32CaptureNum, + uint32_t ui32GPIONumber, + bool bPolarity) +{ + uint32_t ui32CapCtrl; + + if ( ui32GPIONumber > (AM_HAL_GPIO_MAX_PADS-1) ) + { + return; + } + + // + // Set the polarity and pin selection in the GPIO block. + // + switch (ui32CaptureNum) + { + case 0: + GPIO->STMRCAP_b.STPOL0 = bPolarity; + GPIO->STMRCAP_b.STSEL0 = ui32GPIONumber; + ui32CapCtrl = CTIMER_CAPTURECONTROL_CAPTURE0_Msk; + break; + case 1: + GPIO->STMRCAP_b.STPOL1 = bPolarity; + GPIO->STMRCAP_b.STSEL1 = ui32GPIONumber; + ui32CapCtrl = CTIMER_CAPTURECONTROL_CAPTURE1_Msk; + break; + case 2: + GPIO->STMRCAP_b.STPOL2 = bPolarity; + GPIO->STMRCAP_b.STSEL2 = ui32GPIONumber; + ui32CapCtrl = CTIMER_CAPTURECONTROL_CAPTURE2_Msk; + break; + case 3: + GPIO->STMRCAP_b.STPOL3 = bPolarity; + GPIO->STMRCAP_b.STSEL3 = ui32GPIONumber; + ui32CapCtrl = CTIMER_CAPTURECONTROL_CAPTURE3_Msk; + break; + default: + return; // error concealment. + } + + // + // Enable it in the CTIMER Block + // + CTIMER->CAPTURECONTROL |= ui32CapCtrl; +} + +//***************************************************************************** +// +//! @brief Start capturing data with the specified capture register. +//! +//! @param ui32CaptureNum is the Capture Register Number to read. +//! +//! Use this function to start capturing. +//! +//! @return None. +// +//***************************************************************************** +void am_hal_stimer_capture_stop(uint32_t ui32CaptureNum) +{ + // + // Disable it in the CTIMER block. + // + CTIMER->CAPTURECONTROL &= + ~(CTIMER_CAPTURECONTROL_CAPTURE0_Msk << + ((CTIMER_CAPTURECONTROL_CAPTURE1_Pos - + CTIMER_CAPTURECONTROL_CAPTURE0_Pos) * ui32CaptureNum)); +} + +//***************************************************************************** +// +//! @brief Get the current stimer nvram register value. +//! +//! @param ui32NvramNum is the NVRAM Register Number to read. +//! @param ui32NvramVal is the value to write to NVRAM. +//! +//! This function can be used to read the value in an stimer NVRAM register. +//! +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_nvram_set(uint32_t ui32NvramNum, uint32_t ui32NvramVal) +{ + if ( ui32NvramNum > 3 ) + { + return; + } + + //AM_REGn(CTIMER, 0, SNVR) + //AM_REG_STIMER_NVRAM(0, ui32NvramNum) = ui32NvramVal; +} + +//***************************************************************************** +// +//! @brief Get the current stimer nvram register value. +//! +//! @param ui32NvramNum is the NVRAM Register Number to read. +//! +//! This function can be used to read the value in an stimer NVRAM register. +//! +//! +//! @return None. +// +//***************************************************************************** +uint32_t am_hal_stimer_nvram_get(uint32_t ui32NvramNum) +{ + if ( ui32NvramNum > 3 ) + { + return 0; + } + + return AM_REGVAL(AM_REG_STIMER_NVRAM(0, ui32NvramNum)); +} + +//***************************************************************************** +// +//! @brief Get the current stimer capture register value. +//! +//! @param ui32CaptureNum is the Capture Register Number to read. +//! +//! This function can be used to read the value in an stimer capture register. +//! +//! +//! @return None. +// +//***************************************************************************** +uint32_t am_hal_stimer_capture_get(uint32_t ui32CaptureNum) +{ + if ( ui32CaptureNum > 3 ) + { + return 0; + } + + return AM_REGVAL(AM_REG_STIMER_CAPTURE(0, ui32CaptureNum)); +} + +//***************************************************************************** +// +//! @brief Enables the selected system timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will enable the selected interrupts in the STIMER interrupt +//! enable register. In order to receive an interrupt from an stimer component, +//! you will need to enable the interrupt for that component in this main +//! register, as well as in the stimer configuration register (accessible though +//! am_hal_stimer_config()), and in the NVIC. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_enable(uint32_t ui32Interrupt) +{ + // + // Enable the interrupt at the module level. + // + CTIMERn(0)->STMINTEN |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return the enabled stimer interrupts. +//! +//! This function will return all enabled interrupts in the STIMER +//! interrupt enable register. +//! +//! @return return enabled interrupts. This will be a logical or of: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return Return the enabled timer interrupts. +// +//***************************************************************************** +uint32_t +am_hal_stimer_int_enable_get(void) +{ + // + // Return enabled interrupts. + // + return CTIMERn(0)->STMINTEN; +} + +//***************************************************************************** +// +//! @brief Disables the selected stimer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will disable the selected interrupts in the STIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_disable(uint32_t ui32Interrupt) +{ + // + // Disable the interrupt at the module level. + // + CTIMERn(0)->STMINTEN &= ~ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Sets the selected stimer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will set the selected interrupts in the STIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_set(uint32_t ui32Interrupt) +{ + // + // Set the interrupts. + // + CTIMERn(0)->STMINTSET = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Clears the selected stimer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will clear the selected interrupts in the STIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_clear(uint32_t ui32Interrupt) +{ + // + // Disable the interrupt at the module level. + // + CTIMERn(0)->STMINTCLR = ui32Interrupt; +} + + +//***************************************************************************** +// +//! @brief Returns either the enabled or raw stimer interrupt status. +//! +//! This function will return the stimer interrupt status. +//! +//! @param bEnabledOnly if true returns the status of the enabled interrupts +//! only. +//! +//! The return value will be the logical OR of one or more of the following +//! values: +//! +//! +//! @return Returns the stimer interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_stimer_int_status_get(bool bEnabledOnly) +{ + // + // Return the desired status. + // + uint32_t ui32RetVal = CTIMERn(0)->STMINTSTAT; + + if ( bEnabledOnly ) + { + ui32RetVal &= CTIMERn(0)->STMINTEN; + } + + return ui32RetVal; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.h new file mode 100644 index 0000000..24cbefd --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.h @@ -0,0 +1,218 @@ +//***************************************************************************** +// +// am_hal_stimer.h +//! @file +//! +//! @brief Functions for interfacing with the system timer (STIMER). +//! +//! @addtogroup stimer3 System Timer (STIMER) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_STIMER_H +#define AM_HAL_STIMER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +//! Compute address of a given COMPARE register. +//! @note - The parameter n should be 0 (as only 1 stimer module exists). +//! For Apollo3, the parameter r should be 0-7 (compare) or 0-3 (capture). +// +#define AM_REG_STIMER_COMPARE(n, r) (CTIMERADDRn(CTIMER, n, SCMPR0) + \ + (r * (offsetof(CTIMER_Type, SCMPR1) - offsetof(CTIMER_Type, SCMPR0)))) + +//! Compute address of a given CAPTURE register. r should be 0-3. +#define AM_REG_STIMER_CAPTURE(n, r) (CTIMERADDRn(CTIMER, n, SCAPT0) + \ + (r * (offsetof(CTIMER_Type, SCAPT1) - offsetof(CTIMER_Type, SCAPT0)))) + +//! Compute address of a given NVRAM register. r should be 0-3. +#define AM_REG_STIMER_NVRAM(n, r) (CTIMERADDRn(CTIMER, n, SNVR0) + \ + (r * (offsetof(CTIMER_Type, SNVR1) - offsetof(CTIMER_Type, SNVR0)))) + + +//***************************************************************************** +// +//! @name Interrupt Status Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_INT_COMPAREA CTIMER_STMINTSTAT_COMPAREA_Msk +#define AM_HAL_STIMER_INT_COMPAREB CTIMER_STMINTSTAT_COMPAREB_Msk +#define AM_HAL_STIMER_INT_COMPAREC CTIMER_STMINTSTAT_COMPAREC_Msk +#define AM_HAL_STIMER_INT_COMPARED CTIMER_STMINTSTAT_COMPARED_Msk +#define AM_HAL_STIMER_INT_COMPAREE CTIMER_STMINTSTAT_COMPAREE_Msk +#define AM_HAL_STIMER_INT_COMPAREF CTIMER_STMINTSTAT_COMPAREF_Msk +#define AM_HAL_STIMER_INT_COMPAREG CTIMER_STMINTSTAT_COMPAREG_Msk +#define AM_HAL_STIMER_INT_COMPAREH CTIMER_STMINTSTAT_COMPAREH_Msk + +#define AM_HAL_STIMER_INT_OVERFLOW CTIMER_STMINTSTAT_OVERFLOW_Msk + +#define AM_HAL_STIMER_INT_CAPTUREA CTIMER_STMINTSTAT_CAPTUREA_Msk +#define AM_HAL_STIMER_INT_CAPTUREB CTIMER_STMINTSTAT_CAPTUREB_Msk +#define AM_HAL_STIMER_INT_CAPTUREC CTIMER_STMINTSTAT_CAPTUREC_Msk +#define AM_HAL_STIMER_INT_CAPTURED CTIMER_STMINTSTAT_CAPTURED_Msk + +//! @} + +//***************************************************************************** +// +//! @name STimer Configuration Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_CFG_THAW _VAL2FLD(CTIMER_STCFG_FREEZE, CTIMER_STCFG_FREEZE_THAW) +#define AM_HAL_STIMER_CFG_FREEZE _VAL2FLD(CTIMER_STCFG_FREEZE, CTIMER_STCFG_FREEZE_FREEZE) +#define AM_HAL_STIMER_CFG_RUN _VAL2FLD(CTIMER_STCFG_CLEAR, CTIMER_STCFG_CLEAR_RUN) +#define AM_HAL_STIMER_CFG_CLEAR _VAL2FLD(CTIMER_STCFG_CLEAR, CTIMER_STCFG_CLEAR_CLEAR) +#define AM_HAL_STIMER_CFG_COMPARE_A_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_A_EN, CTIMER_STCFG_COMPARE_A_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_B_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_B_EN, CTIMER_STCFG_COMPARE_B_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_C_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_C_EN, CTIMER_STCFG_COMPARE_C_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_D_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_D_EN, CTIMER_STCFG_COMPARE_D_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_E_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_E_EN, CTIMER_STCFG_COMPARE_E_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_F_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_F_EN, CTIMER_STCFG_COMPARE_F_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_G_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_G_EN, CTIMER_STCFG_COMPARE_G_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_H_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_H_EN, CTIMER_STCFG_COMPARE_H_EN_ENABLE) + +//! @} + +//***************************************************************************** +// +//! @name Clock Configuration options +//! @brief STimer Configuration register options. +//! +//! These options are to be used with the am_hal_stimer_config() function. +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_NO_CLK _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_NOCLK) +#define AM_HAL_STIMER_HFRC_3MHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_HFRC_DIV16) +#define AM_HAL_STIMER_HFRC_187_5KHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_HFRC_DIV256) +#define AM_HAL_STIMER_XTAL_32KHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_XTAL_DIV1) +#define AM_HAL_STIMER_XTAL_16KHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_XTAL_DIV2) +#define AM_HAL_STIMER_XTAL_1KHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_XTAL_DIV32) +#define AM_HAL_STIMER_LFRC_1KHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_LFRC_DIV1) +#define AM_HAL_STIMER_HFRC_CTIMER0A _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_CTIMER0A) +#define AM_HAL_STIMER_HFRC_CTIMER0B _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_CTIMER0B) +//! @} + + + +//***************************************************************************** +// +//! @name Capture Control Register options. +//! @brief Configuration options for capture control register. +//! +//! These options are to be used with the am_hal_stimer_capture_control_set +//! function. +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_CAPTURE0_ENABLE _VAL2FLD(CTIMER_CAPTURECONTROL_CAPTURE0, CTIMER_CAPTURECONTROL_CAPTURE0_ENABLE) +#define AM_HAL_STIMER_CAPTURE1_ENABLE _VAL2FLD(CTIMER_CAPTURECONTROL_CAPTURE1, CTIMER_CAPTURECONTROL_CAPTURE1_ENABLE) +#define AM_HAL_STIMER_CAPTURE2_ENABLE _VAL2FLD(CTIMER_CAPTURECONTROL_CAPTURE2, CTIMER_CAPTURECONTROL_CAPTURE2_ENABLE) +#define AM_HAL_STIMER_CAPTURE3_ENABLE _VAL2FLD(CTIMER_CAPTURECONTROL_CAPTURE3, CTIMER_CAPTURECONTROL_CAPTURE3_ENABLE) + +//! @} + +//***************************************************************************** +// +//! Stimer configuration structure +// +//***************************************************************************** +typedef struct +{ + // + //! Configuration options for the STIMER + // + uint32_t ui32STimerConfig; +} +am_hal_stimer_config_t; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern uint32_t am_hal_stimer_config(uint32_t ui32STimerConfig); +extern uint32_t am_hal_stimer_counter_get(void); +extern void am_hal_stimer_counter_clear(void); +extern void am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, + uint32_t ui32Delta); +extern uint32_t am_hal_stimer_compare_get(uint32_t ui32CmprInstance); +extern void am_hal_stimer_capture_start(uint32_t ui32CaptureNum, + uint32_t ui32GPIONumber, + bool bPolarity); +extern void am_hal_stimer_capture_stop(uint32_t ui32CaptureNum); +extern uint32_t am_hal_stimer_capture_get(uint32_t ui32CaptureNum); +extern void am_hal_stimer_nvram_set(uint32_t ui32NvramNum, uint32_t ui32NvramVal); +extern uint32_t am_hal_stimer_nvram_get(uint32_t ui32NvramNum); +extern void am_hal_stimer_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_stimer_int_enable_get(void); +extern void am_hal_stimer_int_disable(uint32_t ui32Interrupt); +extern void am_hal_stimer_int_set(uint32_t ui32Interrupt); +extern void am_hal_stimer_int_clear(uint32_t ui32Interrupt); +extern uint32_t am_hal_stimer_int_status_get(bool bEnabledOnly); + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_STIMER_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.c new file mode 100644 index 0000000..57386de --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.c @@ -0,0 +1,279 @@ +//***************************************************************************** +// +// am_hal_sysctrl.c +//! @file +//! +//! @brief Functions for interfacing with the M4F system control registers +//! +//! @addtogroup sysctrl3 System Control (SYSCTRL) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +// +// g_ui32BusWriteFlush is used by the macro, am_hal_sysctrl_bus_write_flush(). +// It is made global here to avoid compiler 'set but not used' warnings. +// +static volatile uint32_t g_ui32BusWriteFlush; + +//***************************************************************************** +// +//! @brief Place the core into sleep or deepsleep. +//! +//! @param bSleepDeep - False for Normal or True Deep sleep. +//! +//! This function puts the MCU to sleep or deepsleep depending on bSleepDeep. +//! +//! Valid values for bSleepDeep are: +//! +//! AM_HAL_SYSCTRL_SLEEP_NORMAL +//! AM_HAL_SYSCTRL_SLEEP_DEEP +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_sleep(bool bSleepDeep) +{ + // + // Disable interrupts and save the previous interrupt state. + // + AM_CRITICAL_BEGIN + + // + // If the user selected DEEPSLEEP and the TPIU is off, attempt to enter + // DEEP SLEEP. + // + if ( (bSleepDeep == AM_HAL_SYSCTRL_SLEEP_DEEP) && + (MCUCTRL->TPIUCTRL_b.ENABLE == MCUCTRL_TPIUCTRL_ENABLE_DIS) ) + { + + // + // Retrieve the reset generator status bits + // This gets reset on Deep Sleep, so we take a snapshot here + // + if (!gAmHalResetStatus) + { + gAmHalResetStatus = RSTGEN->STAT; + } + // + // Prepare the core for deepsleep (write 1 to the DEEPSLEEP bit). + // + SCB->SCR |= _VAL2FLD(SCB_SCR_SLEEPDEEP, 1); + } + else + { + // + // Prepare the core for normal sleep (write 0 to the DEEPSLEEP bit). + // + SCB->SCR &= ~_VAL2FLD(SCB_SCR_SLEEPDEEP, 1); + } + + // + // Before executing WFI, flush any buffered core and peripheral writes. + // + __DSB(); + am_hal_sysctrl_bus_write_flush(); + + // + // Execute the sleep instruction. + // + __WFI(); + + // + // Upon wake, execute the Instruction Sync Barrier instruction. + // + __ISB(); + + // + // Restore the interrupt state. + // + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Enable the floating point module. +//! +//! Call this function to enable the ARM hardware floating point module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_enable(void) +{ + // + // Enable access to the FPU in both privileged and user modes. + // NOTE: Write 0s to all reserved fields in this register. + // + SCB->CPACR = _VAL2FLD(SCB_CPACR_CP11, 0x3) | + _VAL2FLD(SCB_CPACR_CP10, 0x3); +} + +//***************************************************************************** +// +//! @brief Disable the floating point module. +//! +//! Call this function to disable the ARM hardware floating point module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_disable(void) +{ + // + // Disable access to the FPU in both privileged and user modes. + // NOTE: Write 0s to all reserved fields in this register. + // + SCB->CPACR = 0x00000000 & + ~(_VAL2FLD(SCB_CPACR_CP11, 0x3) | + _VAL2FLD(SCB_CPACR_CP10, 0x3)); +} + +//***************************************************************************** +// +//! @brief Enable stacking of FPU registers on exception entry. +//! +//! @param bLazy - Set to "true" to enable "lazy stacking". +//! +//! This function allows the core to save floating-point information to the +//! stack on exception entry. Setting the bLazy option enables "lazy stacking" +//! for interrupt handlers. Normally, mixing floating-point code and interrupt +//! driven routines causes increased interrupt latency, because the core must +//! save extra information to the stack upon exception entry. With the lazy +//! stacking option enabled, the core will skip the saving of floating-point +//! registers when possible, reducing average interrupt latency. +//! +//! @note At reset of the Cortex M4, the ASPEN and LSPEN bits are set to 1, +//! enabling Lazy mode by default. Therefore this function will generally +//! only have an affect when setting for full-context save (or when switching +//! from full-context to lazy mode). +//! +//! @note See also: +//! infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0298a/DAFGGBJD.html +//! +//! @note Three valid FPU context saving modes are possible. +//! 1. Lazy ASPEN=1 LSPEN=1 am_hal_sysctrl_fpu_stacking_enable(true) +//! and default. +//! 2. Full-context ASPEN=1 LSPEN=0 am_hal_sysctrl_fpu_stacking_enable(false) +//! 3. No FPU state ASPEN=0 LSPEN=0 am_hal_sysctrl_fpu_stacking_disable() +//! 4. Invalid ASPEN=0 LSPEN=1 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_stacking_enable(bool bLazy) +{ + uint32_t ui32fpccr; + + // + // Set the requested FPU stacking mode in ISRs. + // + AM_CRITICAL_BEGIN +#define SYSCTRL_FPCCR_LAZY (FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk) + ui32fpccr = FPU->FPCCR; + ui32fpccr &= ~SYSCTRL_FPCCR_LAZY; + ui32fpccr |= (bLazy ? SYSCTRL_FPCCR_LAZY : FPU_FPCCR_ASPEN_Msk); + FPU->FPCCR = ui32fpccr; + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Disable FPU register stacking on exception entry. +//! +//! This function disables all stacking of floating point registers for +//! interrupt handlers. This mode should only be used when it is absolutely +//! known that no FPU instructions will be executed in an ISR. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_stacking_disable(void) +{ + // + // Completely disable FPU context save on entry to ISRs. + // + AM_CRITICAL_BEGIN + FPU->FPCCR &= ~SYSCTRL_FPCCR_LAZY; + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Issue a system wide reset using the AIRCR bit in the M4 system ctrl. +//! +//! This function issues a system wide reset (Apollo POR level reset). +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_aircr_reset(void) +{ + // + // Set the system reset bit in the AIRCR register + // + __NVIC_SystemReset(); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.h new file mode 100644 index 0000000..4e4910f --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// am_hal_sysctrl.h +//! @file +//! +//! @brief Functions for interfacing with the M4F system control registers +//! +//! @addtogroup sysctrl3 System Control (SYSCTRL) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_SYSCTRL_H +#define AM_HAL_SYSCTRL_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Definitions for sleep mode parameter +// +//***************************************************************************** +#define AM_HAL_SYSCTRL_SLEEP_DEEP true +#define AM_HAL_SYSCTRL_SLEEP_NORMAL false + +//***************************************************************************** +// +// Definition of Global Power State enumeration +// +//***************************************************************************** +typedef enum +{ + AM_HAL_SYSCTRL_WAKE, + AM_HAL_SYSCTRL_NORMALSLEEP, + AM_HAL_SYSCTRL_DEEPSLEEP +} am_hal_sysctrl_power_state_e; + +//***************************************************************************** +// +// Write flush - This function will hold the bus until all queued write +// operations have completed, thereby guaranteeing that all writes have +// been flushed. +// +//***************************************************************************** +#define SYNC_READ 0x5FFF0000 +#define am_hal_sysctrl_bus_write_flush() \ + if ( 1 ) \ + { \ + uint32_t *pui32Flush = (uint32_t*)SYNC_READ; \ + g_ui32BusWriteFlush = *pui32Flush; \ + } + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_sysctrl_sleep(bool bSleepDeep); +extern void am_hal_sysctrl_fpu_enable(void); +extern void am_hal_sysctrl_fpu_disable(void); +extern void am_hal_sysctrl_fpu_stacking_enable(bool bLazy); +extern void am_hal_sysctrl_fpu_stacking_disable(void); +extern void am_hal_sysctrl_aircr_reset(void); +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_SYSCTRL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.c new file mode 100644 index 0000000..d03ddc8 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.c @@ -0,0 +1,351 @@ +//***************************************************************************** +// +// am_hal_systick.c +//! @file +//! +//! @brief Functions for interfacing with the SYSTICK +//! +//! @addtogroup systick3 System Timer (SYSTICK) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** +#define SYSTICK_MAX_TICKS ((1 << 24)-1) +#define MAX_U32 (0xffffffff) + +//***************************************************************************** +// +//! @brief Start the SYSTICK. +//! +//! This function starts the systick timer. +//! +//! @note This timer does not run in deep-sleep mode as it runs from the core +//! clock, which is gated in deep-sleep. If a timer is needed in deep-sleep use +//! one of the ctimers instead. Also to note is this timer will consume higher +//! power than the ctimers. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_start(void) +{ + // + // Start the systick timer. + // + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +//***************************************************************************** +// +//! @brief Stop the SYSTICK. +//! +//! This function stops the systick timer. +//! +//! @note This timer does not run in deep-sleep mode as it runs from the core +//! clock, which is gated in deep-sleep. If a timer is needed in deep-sleep use +//! one of the ctimers instead. Also to note is this timer will consume higher +//! power than the ctimers. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_stop(void) +{ + // + // Stop the systick timer. + // + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + +//***************************************************************************** +// +//! @brief Enable the interrupt in the SYSTICK. +//! +//! This function enables the interupt in the systick timer. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_int_enable(void) +{ + // + // Enable the systick timer interrupt. + // + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +//***************************************************************************** +// +//! @brief Disable the interrupt in the SYSTICK. +//! +//! This function disables the interupt in the systick timer. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_int_disable(void) +{ + // + // Disable the systick timer interrupt. + // + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +//***************************************************************************** +// +//! @brief Reads the interrupt status. +//! +//! This function reads the interrupt status in the systick timer. +//! +//! @return the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_systick_int_status_get(void) +{ + // + // Return the systick timer interrupt status. + // + return SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk; +} + +//***************************************************************************** +// +//! @brief Reset the interrupt in the SYSTICK. +//! +//! This function resets the systick timer by clearing out the configuration +//! register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_reset(void) +{ + // + // Reset the systick timer interrupt. + // + SysTick->CTRL = 0x0; +} + +//***************************************************************************** +// +//! @brief Load the value into the SYSTICK. +//! +//! @param ui32LoadVal the desired load value for the systick. Maximum value is +//! 0x00FF.FFFF. +//! +//! This function loads the desired value into the systick timer. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_load(uint32_t ui32LoadVal) +{ + // + // The proper SysTick initialization sequence is: (p 4-36 of the M4 UG). + // 1. Program reload value + // 2. Clear current value + // 3. Program CSR + // Write the given value to the reload register. + // Write the Current Value Register to clear it to 0. + // + SysTick->LOAD = ui32LoadVal; + SysTick->VAL = 0; +} + +//***************************************************************************** +// +//! @brief Get the current count value in the SYSTICK. +//! +//! This function gets the current count value in the systick timer. +//! +//! @return Current count value. +// +//***************************************************************************** +uint32_t +am_hal_systick_count(void) +{ + // + // Return the current systick timer count value. + // + return SysTick->VAL; +} + +//***************************************************************************** +// +//! @brief Wait the specified number of ticks. +//! +//! This function delays for the given number of SysTick ticks. +//! +//! @note If the SysTick timer is being used elsewhere, it will be corrupted +//! by calling this function. +//! +//! @return 0 if successful. +// +//***************************************************************************** +uint32_t +am_hal_systick_wait_ticks(uint32_t ui32Ticks) +{ + + if ( ui32Ticks == 0 ) + { + ui32Ticks++; // Make sure we get the COUNTFLAG + } + + // + // The proper SysTick initialization sequence is: (p 4-36 of the M4 UG). + // 1. Program reload value + // 2. Clear current value + // 3. Program CSR + // + // Set the reload value to the required number of ticks. + // + SysTick->LOAD = ui32Ticks; + + // + // Clear the current count. + // + SysTick->VAL = 0x0; + + // + // Set to use the processor clock, but don't cause an exception (we'll poll). + // + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; + + // + // Poll till done + // + while ( !(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) ); + + // + // And disable systick before exiting. + // + SysTick->CTRL = 0x0; + + return 0; +} + +//***************************************************************************** +// +//! @brief Delay the specified number of microseconds. +//! +//! This function will use the SysTick timer to delay until the specified +//! number of microseconds have elapsed. It uses the processor clocks and +//! takes into account the current CORESEL setting. +//! +//! @note If the SysTick timer is being used elsewhere, it will be corrupted +//! by calling this function. +//! +//! @return Total number of SysTick ticks delayed. +// +//***************************************************************************** +uint32_t +am_hal_systick_delay_us(uint32_t ui32NumUs) +{ + uint32_t ui32nLoops, ui32Ticks, uRet; + uint32_t ui32ClkFreq, ui32TicksPerMHz; + uint32_t ui32CoreSel = CLKGEN->CCTRL_b.CORESEL; + + ui32nLoops = 0; + if ( (ui32CoreSel <= AM_HAL_CLKGEN_CORESEL_MAXDIV) && (ui32NumUs >= 2) ) + { + // + // Determine clock freq, then whether we need more than 1 iteration. + // + ui32ClkFreq = AM_HAL_CLKGEN_FREQ_MAX_MHZ >> ui32CoreSel; + ui32ClkFreq <<= (am_hal_burst_mode_status() == AM_HAL_BURST_MODE)? 1 : 0; + + ui32TicksPerMHz = SYSTICK_MAX_TICKS / ui32ClkFreq; + if ( ui32NumUs > ui32TicksPerMHz ) + { + // + // Get number of required loops, as well as additional ticks. + // + ui32nLoops = ui32NumUs / ui32TicksPerMHz; + ui32NumUs = ui32NumUs % ui32TicksPerMHz; + } + + // + // Compute the number of ticks required. + // Allow for about 2us of call overhead. + // + ui32Ticks = (ui32NumUs - 2) * ui32ClkFreq; + } + else + { + ui32Ticks = 1; + } + + uRet = (ui32nLoops * SYSTICK_MAX_TICKS) + ui32Ticks; + while ( ui32nLoops ) + { + am_hal_systick_wait_ticks(SYSTICK_MAX_TICKS); + ui32nLoops--; + } + am_hal_systick_wait_ticks(ui32Ticks); + + return uRet; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.h new file mode 100644 index 0000000..0896e51 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.h @@ -0,0 +1,87 @@ +//***************************************************************************** +// +// am_hal_systick.h +//! @file +//! +//! @brief Functions for accessing and configuring the SYSTICK. +//! +//! @addtogroup systick3 System Timer (SYSTICK) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_SYSTICK_H +#define AM_HAL_SYSTICK_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_systick_start(void); +extern void am_hal_systick_stop(void); +extern void am_hal_systick_int_enable(void); +extern void am_hal_systick_int_disable(void); +extern uint32_t am_hal_systick_int_status_get(void); +extern void am_hal_systick_reset(void); +extern void am_hal_systick_load(uint32_t ui32LoadVal); +extern uint32_t am_hal_systick_count(void); +extern uint32_t am_hal_systick_wait_ticks(uint32_t u32Ticks); +extern uint32_t am_hal_systick_delay_us(uint32_t u32NumUs); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_SYSTICK_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.c new file mode 100644 index 0000000..deb2532 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.c @@ -0,0 +1,394 @@ +//***************************************************************************** +// +// am_hal_tpiu.c +//! @file +//! +//! @brief Support functions for the ARM TPIU module +//! +//! Provides support functions for configuring the ARM TPIU module +//! +//! @addtogroup tpiu3 Trace Port Interface Unit (TPIU) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Enable the clock to the TPIU module. +//! +//! This function enables the clock to the TPIU module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_clock_enable(void) +{ + // + // Enable the TPIU clock + // + MCUCTRL->TPIUCTRL |= MCUCTRL_TPIUCTRL_ENABLE_Msk; +} + +//***************************************************************************** +// +//! @brief Disable the clock to the TPIU module. +//! +//! This function disables the clock to the TPIU module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_clock_disable(void) +{ + // + // Disable the TPIU clock + // + MCUCTRL->TPIUCTRL &= ~MCUCTRL_TPIUCTRL_ENABLE_Msk; +} + +//***************************************************************************** +// +//! @brief Set the output port width of the TPIU +//! +//! @param ui32PortWidth - The desired port width (in bits) +//! +//! This function uses the TPIU_CSPSR register to set the desired output port +//! width of the TPIU. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_port_width_set(uint32_t ui32PortWidth) +{ + TPI->CSPSR = 1 << (ui32PortWidth - 1); +} + +//***************************************************************************** +// +//! @brief Read the supported_output port width of the TPIU +//! +//! This function uses the \e TPIU_SSPSR register to set the supported output +//! port widths of the TPIU. +//! +//! @return Current width of the TPIU output port +// +//***************************************************************************** +uint32_t +am_hal_tpiu_supported_port_width_get(void) +{ + uint32_t i, ui32WidthValue; + + // + // Read the supported width register. + // + ui32WidthValue = TPI->SSPSR; + + // + // The register value is encoded in a one-hot format, so the position of + // the single set bit determines the actual width of the port. + // + for (i = 1; i < 32; i++) + { + // + // Check each bit for a '1'. When we find it, our current loop index + // will be equal to the port width. + // + if (ui32WidthValue == (0x1 << (i - 1))) + { + return i; + } + } + + // + // We should never get here, but if we do, just return the smallest + // possible value for a supported trace port width. + // + return 1; +} + +//***************************************************************************** +// +//! @brief Read the output port width of the TPIU +//! +//! This function uses the \e TPIU_CSPSR register to set the desired output +//! port width of the TPIU. +//! +//! @return Current width of the TPIU output port +// +//***************************************************************************** +uint32_t +am_hal_tpiu_port_width_get(void) +{ + uint32_t ui32Temp; + uint32_t ui32Width; + + ui32Width = 1; + ui32Temp = TPI->CSPSR; + + while ( !(ui32Temp & 1) ) + { + ui32Temp = ui32Temp >> 1; + ui32Width++; + + if (ui32Width > 32) + { + ui32Width = 0; + break; + } + } + + // + // Current width of the TPIU output port. + // + return ui32Width; +} + +//***************************************************************************** +// +//! @brief Configure the TPIU based on the values in the configuration struct. +//! +//! @param psConfig - pointer to an am_hal_tpiu_config_t structure containing +//! the desired configuration information. +//! +//! This function reads the provided configuration structure, and sets the +//! relevant TPIU registers to achieve the desired configuration. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig) +{ + // + // Set the clock freq in the MCUCTRL register. + // + MCUCTRL->TPIUCTRL |= psConfig->ui32TraceClkIn; + + // + // Set the desired protocol. + // + TPI->SPPR = psConfig->ui32PinProtocol; + + // + // Set the parallel port width. This may be redundant if the user has + // selected a serial protocol, but we'll set it anyway. + // + TPI->CSPSR = (1 << (psConfig->ui32ParallelPortSize - 1)); + + // + // Set the clock prescaler. + // + TPI->ACPR = psConfig->ui32ClockPrescaler; +} + +//***************************************************************************** +// +//! @brief Enables the TPIU +//! +//! This function enables the ARM TPIU by setting the TPIU registers and then +//! enabling the TPIU clock source in MCU control register. +//! +//! @param psConfig - structure for configuration. +//! If ui32SetItmBaud, the other structure members are used to set the +//! TPIU configuration. +//! But for simplicity, ui32SetItmBaud can be set to one of the +//! following, in which case all other structure members are ignored. +//! In this case, the given BAUD rate is based on a div-by-8 HFRC clock. +//! AM_HAL_TPIU_BAUD_57600 +//! AM_HAL_TPIU_BAUD_115200 +//! AM_HAL_TPIU_BAUD_230400 +//! AM_HAL_TPIU_BAUD_460800 +//! AM_HAL_TPIU_BAUD_500000 +//! AM_HAL_TPIU_BAUD_1M +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig) +{ + am_hal_clkgen_status_t sClkGenStatus; + uint32_t ui32HFRC, ui32SWOscaler, ui32ITMbitrate; + + ui32ITMbitrate = psConfig->ui32SetItmBaud; + + // + // TPIU formatter & flush control register. + // + TPI->FFCR = 0; + + if ( ui32ITMbitrate ) + { + // + // Set the Current Parallel Port Size (note - only 1 bit can be set). + // + TPI->CSPSR = TPI_CSPSR_CWIDTH_1BIT; + + // + // Use some default assumptions to set the ITM frequency. + // + if ( (ui32ITMbitrate < AM_HAL_TPIU_BAUD_57600 ) || + (ui32ITMbitrate > AM_HAL_TPIU_BAUD_2M ) ) + { + ui32ITMbitrate = AM_HAL_TPIU_BAUD_DEFAULT; + } + + // + // Get the current HFRC frequency. + // + am_hal_clkgen_status_get(&sClkGenStatus); + ui32HFRC = sClkGenStatus.ui32SysclkFreq; + + // + // Compute the SWO scaler value. + // + if ( ui32HFRC != 0xFFFFFFFF ) + { + ui32SWOscaler = ((ui32HFRC / 8) / ui32ITMbitrate) - 1; + } + else + { + ui32SWOscaler = ( (AM_HAL_CLKGEN_FREQ_MAX_HZ / 8) / + AM_HAL_TPIU_BAUD_DEFAULT ) - 1; + } + + // + // Set the scaler value. + // + TPI->ACPR = _VAL2FLD(TPI_ACPR_SWOSCALER, ui32SWOscaler); + + // + // Set for UART mode + // + TPI->SPPR = _VAL2FLD( TPI_SPPR_TXMODE, TPI_SPPR_TXMODE_UART); + + // + // Make sure we are not in test mode (important for proper deep sleep + // operation). + // + TPI->ITCTRL = _VAL2FLD(TPI_ITCTRL_Mode, TPI_ITCTRL_Mode_NORMAL); + + // + // Enable the TPIU clock source in MCU control. + // Set TPIU clock for HFRC/8 (6MHz) operation. + // + MCUCTRL->TPIUCTRL = + _VAL2FLD(MCUCTRL_TPIUCTRL_CLKSEL, MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV8) | + _VAL2FLD(MCUCTRL_TPIUCTRL_ENABLE, MCUCTRL_TPIUCTRL_ENABLE_EN); + } + else + { + // + // Set the configuration according to the structure values. + // + + // + // Set the Asynchronous Clock Prescaler Register. + // + TPI->ACPR = psConfig->ui32ClockPrescaler; + + // + // Set the Selected Pin Protocol Register. + // e.g. AM_REG_TPIU_SPPR_TXMODE_UART + // + TPI->SPPR = psConfig->ui32PinProtocol; + + // + // Set the Current Parallel Port Size (note - only 1 bit can be set). + // This may be redundant if the user has selected a serial protocol, + // but we'll set it anyway. + // + TPI->CSPSR = (1 << (psConfig->ui32ParallelPortSize - 1)); + + // + // Make sure we are not in test mode (important for proper deep sleep + // operation). + // + TPI->ITCTRL = _VAL2FLD(TPI_ITCTRL_Mode, TPI_ITCTRL_Mode_NORMAL); + + // + // Set the clock freq and enable fields in the MCUCTRL register. + // + MCUCTRL->TPIUCTRL = psConfig->ui32TraceClkIn; + } + + // + // Wait for 50us for the data to flush out. + // + am_hal_flash_delay(FLASH_CYCLES_US(50)); +} + +//***************************************************************************** +// +//! @brief Disables the TPIU +//! +//! This function disables the ARM TPIU by disabling the TPIU clock source +//! in MCU control register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_disable(void) +{ + // + // Disable the TPIU clock source in MCU control. + // + MCUCTRL->TPIUCTRL = + _VAL2FLD(MCUCTRL_TPIUCTRL_CLKSEL, MCUCTRL_TPIUCTRL_CLKSEL_LOWPWR) | + _VAL2FLD(MCUCTRL_TPIUCTRL_ENABLE, MCUCTRL_TPIUCTRL_ENABLE_DIS); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.h new file mode 100644 index 0000000..d3a9f37 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.h @@ -0,0 +1,198 @@ +//***************************************************************************** +// +// am_hal_tpiu.h +//! @file +//! +//! @brief Definitions and structures for working with the TPIU. +//! +//! @addtogroup tpiu3 Trace Port Interface Unit (TPIU) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_TPIU_H +#define AM_HAL_TPIU_H + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// TPIU bit rate defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_BAUD_57600 (115200 / 2) +#define AM_HAL_TPIU_BAUD_115200 (115200 * 1) +#define AM_HAL_TPIU_BAUD_230400 (115200 * 2) +#define AM_HAL_TPIU_BAUD_460800 (115200 * 4) +#define AM_HAL_TPIU_BAUD_250000 (1000000 / 4) +#define AM_HAL_TPIU_BAUD_500000 (1000000 / 2) +#define AM_HAL_TPIU_BAUD_1M (1000000 * 1) +#define AM_HAL_TPIU_BAUD_2M (1000000 * 2) +#define AM_HAL_TPIU_BAUD_DEFAULT (AM_HAL_TPIU_BAUD_1M) + +//***************************************************************************** +// +// TPIU register defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_SSPSR 0xE0040000 //! Supported Parallel Port Sizes +#define AM_HAL_TPIU_CSPSR 0xE0040004 //! Current Parallel Port Size +#define AM_HAL_TPIU_ACPR 0xE0040010 //! Asynchronous Clock Prescaler +#define AM_HAL_TPIU_SPPR 0xE00400F0 //! Selected Pin Protocol +#define AM_HAL_TPIU_TYPE 0xE0040FC8 //! TPIU Type + +//***************************************************************************** +// +// TPIU ACPR defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_ACPR_SWOSCALER_M 0x0000FFFF //! SWO baud rate prescalar + +//***************************************************************************** +// +// TPIU_SPPR TXMODE defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_SPPR_PARALLEL 0x00000000 +#define AM_HAL_TPIU_SPPR_MANCHESTER 0x00000001 +#define AM_HAL_TPIU_SPPR_NRZ 0x00000002 + +//***************************************************************************** +// +// TPIU Type defines +// +//***************************************************************************** +#define AM_HAL_TPIU_TYPE_NRZVALID 0x00000800 +#define AM_HAL_TPIU_TYPE_MANCVALID 0x00000400 +#define AM_HAL_TPIU_TYPE_PTINVALID 0x00000200 +#define AM_HAL_TPIU_TYPE_FIFOSZ_M 0x000001C0 + +//***************************************************************************** +// +// TPIU Clock defines +// +//***************************************************************************** +#define AM_HAL_TPIU_TRACECLKIN_6MHZ AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(0) +#define AM_HAL_TPIU_TRACECLKIN_3MHZ AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(1) +#define AM_HAL_TPIU_TRACECLKIN_1_5MHZ AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(2) +#define AM_HAL_TPIU_TRACECLKIN_750KHZ AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(3) + +//***************************************************************************** +// +//! @brief Structure used for configuring the TPIU +// +//***************************************************************************** +typedef struct +{ + // + // If ui32SetItmBaud is non-zero, the ITM frequency is set to the given + // frequency, and is based on a divide-by-8 HFRC TPIU clock. + // If zero, other structure members are used to set the TPIU configuration. + // + uint32_t ui32SetItmBaud; + + // + //! MCU Control TRACECLKIN clock freq. + //! + //! Valid values for ui32TraceClkIn are: + //! + //! AM_HAL_TPIU_TRACECLKIN_6MHZ + //! AM_HAL_TPIU_TRACECLKIN_3MHZ + //! AM_HAL_TPIU_TRACECLKIN_1_5MHZ + //! AM_HAL_TPIU_TRACECLKIN_750KHZ + // + uint32_t ui32TraceClkIn; + + // + //! Protocol to use for the TPIU + //! + //! Valid values for ui32PinProtocol are: + //! + //! AM_HAL_TPIU_SPPR_PARALLEL + //! AM_HAL_TPIU_SPPR_MANCHESTER + //! AM_HAL_TPIU_SPPR_NRZ + // + uint32_t ui32PinProtocol; + + // + //! Desired width of the TPIU parallel port + // + uint32_t ui32ParallelPortSize; + + // + //! Desired Clock prescaler value + // + uint32_t ui32ClockPrescaler; +} +am_hal_tpiu_config_t; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_tpiu_clock_enable(void); +extern void am_hal_tpiu_clock_disable(void); +extern void am_hal_tpiu_port_width_set(uint32_t ui32PortWidth); +extern uint32_t am_hal_tpiu_supported_port_width_get(void); +extern uint32_t am_hal_tpiu_port_width_get(void); +extern void am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig); +extern void am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig); +extern void am_hal_tpiu_disable(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_TPIU_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.c new file mode 100644 index 0000000..c141f36 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.c @@ -0,0 +1,1516 @@ +//***************************************************************************** +// +// am_hal_uart.c +//! @file +//! +//! @brief Functions for interfacing with the UART. +//! +//! @addtogroup uart3 UART +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// UART magic number for handle verification. +// +//***************************************************************************** +#define AM_HAL_MAGIC_UART 0xEA9E06 + +#define AM_HAL_UART_CHK_HANDLE(h) \ + ((h) && \ + ((am_hal_handle_prefix_t *)(h))->s.bInit && \ + (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_UART)) + +//***************************************************************************** +// +// Convenience macro for passing errors. +// +//***************************************************************************** +#define RETURN_ON_ERROR(x) \ + if ((x) != AM_HAL_STATUS_SUCCESS) \ + { \ + return (x); \ + }; + +//***************************************************************************** +// +// Baudrate to byte-time in microseconds with a little extra margin. +// +//***************************************************************************** +#define ONE_BYTE_US(baudrate) (12000000/(baudrate)) +#define ONE_BYTE_DELAY(handle) \ + am_hal_flash_delay(FLASH_CYCLES_US(ONE_BYTE_US((handle)->ui32BaudRate))) + +//***************************************************************************** +// +// Structure for handling UART register state information for power up/down +// +//***************************************************************************** +typedef struct +{ + bool bValid; + uint32_t regILPR; + uint32_t regIBRD; + uint32_t regFBRD; + uint32_t regLCRH; + uint32_t regCR; + uint32_t regIFLS; + uint32_t regIER; +} +am_hal_uart_register_state_t; + +//***************************************************************************** +// +// Structure for handling UART HAL state information. +// +//***************************************************************************** +typedef struct +{ + am_hal_handle_prefix_t prefix; + am_hal_uart_register_state_t sRegState; + + uint32_t ui32Module; + + bool bEnableTxQueue; + am_hal_queue_t sTxQueue; + + bool bEnableRxQueue; + am_hal_queue_t sRxQueue; + + uint32_t ui32BaudRate; +} +am_hal_uart_state_t; + +//***************************************************************************** +// +// State structure for each module. +// +//***************************************************************************** +am_hal_uart_state_t g_am_hal_uart_states[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// Prototypes for static functions. +// +//***************************************************************************** +static uint32_t config_baudrate(uint32_t ui32Module, uint32_t ui32Baudrate, uint32_t *ui32UartClkFreq); + +static uint32_t buffer_configure(void *pHandle, + uint8_t *pui8TxBuffer, + uint32_t ui32TxBufferSize, + uint8_t *pui8RxBuffer, + uint32_t ui32RxBufferSize); + +static uint32_t tx_queue_update(void *pHandle); +static uint32_t rx_queue_update(void *pHandle); + +static uint32_t uart_fifo_read(void *pHandle, + uint8_t *pui8Data, + uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead); + +static uint32_t uart_fifo_write(void *pHandle, + uint8_t *pui8Data, + uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten); + +//***************************************************************************** +// +// Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_uart_initialize(uint32_t ui32Module, void **ppHandle) +{ + // + // Check that the request module is in range. + // + if (ui32Module >= AM_REG_UART_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Check for valid arguements. + // + if (!ppHandle) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if (g_am_hal_uart_states[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Initialize the handle. + // + g_am_hal_uart_states[ui32Module].prefix.s.bInit = true; + g_am_hal_uart_states[ui32Module].prefix.s.magic = AM_HAL_MAGIC_UART; + g_am_hal_uart_states[ui32Module].ui32Module = ui32Module; + g_am_hal_uart_states[ui32Module].sRegState.bValid = false; + g_am_hal_uart_states[ui32Module].ui32BaudRate = 0; + + // + // Return the handle. + // + *ppHandle = (void *)&g_am_hal_uart_states[ui32Module]; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_initialize() + +//***************************************************************************** +// +// De-Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_uart_deinitialize(void *pHandle) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *)pHandle; + + // + // Check the handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Reset the handle. + // + pState->prefix.s.bInit = false; + pState->ui32Module = 0; + pState->sRegState.bValid = false; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_deinitialize() + +//***************************************************************************** +// +// Power control functions. +// +//***************************************************************************** +uint32_t +am_hal_uart_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + am_hal_pwrctrl_periph_e eUARTPowerModule = ((am_hal_pwrctrl_periph_e) + (AM_HAL_PWRCTRL_PERIPH_UART0 + + ui32Module)); + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Decode the requested power state and update UART operation accordingly. + // + switch (ePowerState) + { + // + // Turn on the UART. + // + case AM_HAL_SYSCTRL_WAKE: + // + // Make sure we don't try to restore an invalid state. + // + if (bRetainState && !pState->sRegState.bValid) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable(eUARTPowerModule); + + if (bRetainState) + { + // + // Restore UART registers + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->ILPR = pState->sRegState.regILPR; + UARTn(ui32Module)->IBRD = pState->sRegState.regIBRD; + UARTn(ui32Module)->FBRD = pState->sRegState.regFBRD; + UARTn(ui32Module)->LCRH = pState->sRegState.regLCRH; + UARTn(ui32Module)->CR = pState->sRegState.regCR; + UARTn(ui32Module)->IFLS = pState->sRegState.regIFLS; + UARTn(ui32Module)->IER = pState->sRegState.regIER; + + pState->sRegState.bValid = false; + + AM_CRITICAL_END + } + break; + + // + // Turn off the UART. + // + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + if (bRetainState) + { + AM_CRITICAL_BEGIN + + pState->sRegState.regILPR = UARTn(ui32Module)->ILPR; + pState->sRegState.regIBRD = UARTn(ui32Module)->IBRD; + pState->sRegState.regFBRD = UARTn(ui32Module)->FBRD; + pState->sRegState.regLCRH = UARTn(ui32Module)->LCRH; + pState->sRegState.regCR = UARTn(ui32Module)->CR; + pState->sRegState.regIFLS = UARTn(ui32Module)->IFLS; + pState->sRegState.regIER = UARTn(ui32Module)->IER; + pState->sRegState.bValid = true; + + AM_CRITICAL_END + } + + // + // Clear all interrupts before sleeping as having a pending UART + // interrupt burns power. + // + am_hal_uart_interrupt_clear(pState, 0xFFFFFFFF); + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable(eUARTPowerModule); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_power_control() + +//***************************************************************************** +// +// UART configuration. +// +//***************************************************************************** +uint32_t +am_hal_uart_configure(void *pHandle, const am_hal_uart_config_t *psConfig) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + uint32_t ui32ErrorStatus; + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Reset the CR register to a known value. + // + UARTn(ui32Module)->CR = 0; + + // + // Start by enabling the clocks, which needs to happen in a critical + // section. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.CLKEN = 1; + UARTn(ui32Module)->CR_b.CLKSEL = UART0_CR_CLKSEL_24MHZ; + + AM_CRITICAL_END + + // + // Disable the UART. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.UARTEN = 0; + UARTn(ui32Module)->CR_b.RXE = 0; + UARTn(ui32Module)->CR_b.TXE = 0; + + AM_CRITICAL_END + + // + // Set the baud rate. + // + ui32ErrorStatus = config_baudrate(ui32Module, psConfig->ui32BaudRate, + &(pState->ui32BaudRate)); + + RETURN_ON_ERROR(ui32ErrorStatus); + + // + // Copy the configuration options into the appropriate registers. + // + UARTn(ui32Module)->CR_b.RTSEN = 0; + UARTn(ui32Module)->CR_b.CTSEN = 0; + UARTn(ui32Module)->CR |= psConfig->ui32FlowControl; + + UARTn(ui32Module)->IFLS = psConfig->ui32FifoLevels; + + UARTn(ui32Module)->LCRH = (psConfig->ui32DataBits | + psConfig->ui32Parity | + psConfig->ui32StopBits | + AM_HAL_UART_FIFO_ENABLE); + + // + // Enable the UART, RX, and TX. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.UARTEN = 1; + UARTn(ui32Module)->CR_b.RXE = 1; + UARTn(ui32Module)->CR_b.TXE = 1; + + AM_CRITICAL_END + + // + // Set up any buffers that might exist. + // + buffer_configure(pHandle, + psConfig->pui8TxBuffer, + psConfig->ui32TxBufferSize, + psConfig->pui8RxBuffer, + psConfig->ui32RxBufferSize); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_configure() + +uint32_t +am_hal_uart_configure_fifo(void *pHandle, const am_hal_uart_config_t *psConfig, bool bEnableFIFO) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + uint32_t ui32ErrorStatus; + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Reset the CR register to a known value. + // + UARTn(ui32Module)->CR = 0; + + // + // Start by enabling the clocks, which needs to happen in a critical + // section. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.CLKEN = 1; + UARTn(ui32Module)->CR_b.CLKSEL = UART0_CR_CLKSEL_24MHZ; + + AM_CRITICAL_END + + // + // Disable the UART. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.UARTEN = 0; + UARTn(ui32Module)->CR_b.RXE = 0; + UARTn(ui32Module)->CR_b.TXE = 0; + + AM_CRITICAL_END + + // + // Set the baud rate. + // + ui32ErrorStatus = config_baudrate(ui32Module, psConfig->ui32BaudRate, + &(pState->ui32BaudRate)); + + RETURN_ON_ERROR(ui32ErrorStatus); + + // + // Copy the configuration options into the appropriate registers. + // + UARTn(ui32Module)->CR_b.RTSEN = 0; + UARTn(ui32Module)->CR_b.CTSEN = 0; + UARTn(ui32Module)->CR |= psConfig->ui32FlowControl; + + UARTn(ui32Module)->IFLS = psConfig->ui32FifoLevels; + + UARTn(ui32Module)->LCRH = (psConfig->ui32DataBits | + psConfig->ui32Parity | + psConfig->ui32StopBits | + ((bEnableFIFO) ? AM_HAL_UART_FIFO_ENABLE : AM_HAL_UART_FIFO_DISABLE)); + + // + // Enable the UART, RX, and TX. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.UARTEN = 1; + UARTn(ui32Module)->CR_b.RXE = 1; + UARTn(ui32Module)->CR_b.TXE = 1; + + AM_CRITICAL_END + + if(bEnableFIFO){ + // + // Set up any buffers that might exist. + // + buffer_configure(pHandle, + psConfig->pui8TxBuffer, + psConfig->ui32TxBufferSize, + psConfig->pui8RxBuffer, + psConfig->ui32RxBufferSize); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_configure_fifo() + +//***************************************************************************** +// +// Allows the UART HAL to use extra space to store TX and RX data. +// +//***************************************************************************** +static uint32_t +buffer_configure(void *pHandle, uint8_t *pui8TxBuffer, uint32_t ui32TxBufferSize, + uint8_t *pui8RxBuffer, uint32_t ui32RxBufferSize) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32ErrorStatus; + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check to see if we have a TX buffer. + // + if (pui8TxBuffer && ui32TxBufferSize) + { + // + // If so, initialzie the transmit queue, and enable the TX FIFO + // interrupt. + // + pState->bEnableTxQueue = true; + am_hal_queue_init(&pState->sTxQueue, pui8TxBuffer, 1, ui32TxBufferSize); + ui32ErrorStatus = am_hal_uart_interrupt_enable(pHandle, AM_HAL_UART_INT_TX); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + // + // If not, make sure the TX FIFO interrupt is disabled. + // + pState->bEnableTxQueue = false; + ui32ErrorStatus = am_hal_uart_interrupt_disable(pHandle, AM_HAL_UART_INT_TX); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // Check to see if we have an RX buffer. + // + if (pui8RxBuffer && ui32RxBufferSize) + { + // + // If so, initialize the receive queue and the associated interupts. + // + pState->bEnableRxQueue = true; + am_hal_queue_init(&pState->sRxQueue, pui8RxBuffer, 1, ui32RxBufferSize); + ui32ErrorStatus = am_hal_uart_interrupt_enable(pHandle, (AM_HAL_UART_INT_RX | + AM_HAL_UART_INT_RX_TMOUT)); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + pState->bEnableRxQueue = false; + ui32ErrorStatus = am_hal_uart_interrupt_disable(pHandle, (AM_HAL_UART_INT_RX | + AM_HAL_UART_INT_RX_TMOUT)); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + return AM_HAL_STATUS_SUCCESS; +} // buffer_configure() + +//***************************************************************************** +// +// Set Baud Rate based on the UART clock frequency. +// +//***************************************************************************** +#define BAUDCLK (16) // Number of UART clocks needed per bit. +static uint32_t +config_baudrate(uint32_t ui32Module, uint32_t ui32DesiredBaudrate, uint32_t *pui32ActualBaud) +{ + uint64_t ui64FractionDivisorLong; + uint64_t ui64IntermediateLong; + uint32_t ui32IntegerDivisor; + uint32_t ui32FractionDivisor; + uint32_t ui32BaudClk; + uint32_t ui32UartClkFreq; + + // + // Check that the baudrate is in range. + // + if (APOLLO3_A1) + { + if (ui32DesiredBaudrate > AM_HAL_UART_MAXIMUM_BAUDRATE_A1) + { + return AM_HAL_UART_STATUS_BAUDRATE_NOT_POSSIBLE; + } + } + if (APOLLO3_GE_B0) + { + if (ui32DesiredBaudrate > AM_HAL_UART_MAXIMUM_BAUDRATE_B0) + { + return AM_HAL_UART_STATUS_BAUDRATE_NOT_POSSIBLE; + } + } + + switch ( UARTn(ui32Module)->CR_b.CLKSEL ) + { + case UART0_CR_CLKSEL_24MHZ: + ui32UartClkFreq = 24000000; + break; + + case UART0_CR_CLKSEL_12MHZ: + ui32UartClkFreq = 12000000; + break; + + case UART0_CR_CLKSEL_6MHZ: + ui32UartClkFreq = 6000000; + break; + + case UART0_CR_CLKSEL_3MHZ: + ui32UartClkFreq = 3000000; + break; + + default: + *pui32ActualBaud = 0; + return AM_HAL_UART_STATUS_CLOCK_NOT_CONFIGURED; + } + + // + // Calculate register values. + // + ui32BaudClk = BAUDCLK * ui32DesiredBaudrate; + ui32IntegerDivisor = (uint32_t)(ui32UartClkFreq / ui32BaudClk); + ui64IntermediateLong = (ui32UartClkFreq * 64) / ui32BaudClk; + ui64FractionDivisorLong = ui64IntermediateLong - (ui32IntegerDivisor * 64); + ui32FractionDivisor = (uint32_t)ui64FractionDivisorLong; + + // + // Check the result. + // + if (ui32IntegerDivisor == 0) + { + *pui32ActualBaud = 0; + return AM_HAL_UART_STATUS_BAUDRATE_NOT_POSSIBLE; + } + + // + // Write the UART regs. + // + // TODO: Is this double-write of IBRD really intended? + UARTn(ui32Module)->IBRD = ui32IntegerDivisor; + UARTn(ui32Module)->IBRD = ui32IntegerDivisor; + UARTn(ui32Module)->FBRD = ui32FractionDivisor; + + // + // Return the actual baud rate. + // + *pui32ActualBaud = (ui32UartClkFreq / ((BAUDCLK * ui32IntegerDivisor) + ui32FractionDivisor / 4)); + return AM_HAL_STATUS_SUCCESS; +} // config_baudrate() + +//***************************************************************************** +// +// Read as much data from the UART FIFO as possible, up to ui32NumBytes +// +//***************************************************************************** +static uint32_t +uart_fifo_read(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead) +{ + uint32_t i = 0; + uint32_t ui32ReadData; + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Start a loop where we attempt to read everything requested. + // + while (i < ui32NumBytes) + { + // + // If the fifo is empty, return with the number of bytes we read. + // Otherwise, read the data into the provided buffer. + // + if ( UARTn(ui32Module)->FR_b.RXFE ) + { + break; + } + else + { + ui32ReadData = UARTn(ui32Module)->DR; + + // + // If error bits are set, we need to alert the caller. + // + if (ui32ReadData & (_VAL2FLD(UART0_DR_OEDATA, UART0_DR_OEDATA_ERR) | + _VAL2FLD(UART0_DR_BEDATA, UART0_DR_BEDATA_ERR) | + _VAL2FLD(UART0_DR_PEDATA, UART0_DR_PEDATA_ERR) | + _VAL2FLD(UART0_DR_FEDATA, UART0_DR_FEDATA_ERR)) ) + { + ui32ErrorStatus = AM_HAL_UART_STATUS_BUS_ERROR; + break; + } + else + { + pui8Data[i++] = ui32ReadData & 0xFF; + } + } + } + + if (pui32NumBytesRead) + { + *pui32NumBytesRead = i; + } + + return ui32ErrorStatus; +} // uart_fifo_read() + +//***************************************************************************** +// +// Read as much data from the UART FIFO as possible, up to ui32NumBytes +// +//***************************************************************************** +static uint32_t +uart_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten) +{ + uint32_t i = 0; + + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Start a loop where we attempt to write everything requested. + // + while (i < ui32NumBytes) + { + // + // If the TX FIFO is full, break out of the loop. We've sent everything + // we can. + // + if ( UARTn(ui32Module)->FR_b.TXFF ) + { + break; + } + else + { + UARTn(ui32Module)->DR = pui8Data[i++]; + } + } + + // + // Let the caller know how much we sent. + // + if (pui32NumBytesWritten) + { + *pui32NumBytesWritten = i; + } + + return AM_HAL_STATUS_SUCCESS; +} // uart_fifo_write() + +//***************************************************************************** +// +// Attempt to read N bytes from the FIFO, but give up if they aren't there. +// +//***************************************************************************** +static uint32_t +read_nonblocking(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead) +{ + uint32_t ui32BufferData; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Start by setting the number of bytes read to 0. + // + if (pui32NumBytesRead) + { + *pui32NumBytesRead = 0; + } + + if (ui32NumBytes == 0) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Check to see if the circular receive buffer has been enabled. + // + if (pState->bEnableRxQueue) + { + // + // If it is, update it, and then try to read the requested number of + // bytes, giving up if fewer were actually found. + // + ui32ErrorStatus = rx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + + ui32BufferData = am_hal_queue_data_left(&pState->sRxQueue); + + ui32BytesTransferred = (ui32NumBytes < ui32BufferData ? + ui32NumBytes : ui32BufferData); + + am_hal_queue_item_get(&pState->sRxQueue, pui8Data, ui32BytesTransferred); + } + else + { + // + // If the buffer isn't enabled, just read straight from the FIFO. + // + ui32ErrorStatus = uart_fifo_read(pHandle, pui8Data, ui32NumBytes, + &ui32BytesTransferred); + } + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + if (pui32NumBytesRead) + { + *pui32NumBytesRead = ui32BytesTransferred; + } + + return ui32ErrorStatus; +} // read_nonblocking() + +//***************************************************************************** +// +// Attempt to write N bytes to the FIFO, but give up if there's no space. +// +//***************************************************************************** +static uint32_t +write_nonblocking(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten) +{ + uint32_t ui32ErrorStatus; + uint32_t ui32BufferSpace; + uint32_t ui32BytesTransferred; + + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + if (pui32NumBytesWritten) + { + *pui32NumBytesWritten = 0; + } + + if (ui32NumBytes == 0) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Check to see if the circular transmit buffer has been enabled. + // + if (pState->bEnableTxQueue) + { + // + // If it has, been enabled, write as much data to it as we can, and let + // the caller know how much that was. + // + ui32BufferSpace = am_hal_queue_space_left(&pState->sTxQueue); + + ui32BytesTransferred = (ui32NumBytes < ui32BufferSpace ? + ui32NumBytes : ui32BufferSpace); + + am_hal_queue_item_add(&pState->sTxQueue, pui8Data, ui32BytesTransferred); + + // + // Transfer as much data as possible from the queue to the fifo. + // + ui32ErrorStatus = tx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + // + // If the buffer isn't enabled, just write straight to the FIFO. + // + uart_fifo_write(pHandle, pui8Data, ui32NumBytes, + &ui32BytesTransferred); + } + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + if (pui32NumBytesWritten) + { + *pui32NumBytesWritten = ui32BytesTransferred; + } + + return AM_HAL_STATUS_SUCCESS; +} // write_nonblocking() + +//***************************************************************************** +// +// This function will keep reading bytes until it either gets N bytes or runs +// into an error. +// +//***************************************************************************** +static uint32_t +read_timeout(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead, uint32_t ui32TimeoutMs) +{ + uint32_t ui32Status, ui32BytesRead, ui32RemainingBytes, + ui32TimeSpent, i; + + // + // If we don't have a timeout, just pass this directly to the nonblocking + // call. + // + if (ui32TimeoutMs == 0) + { + return read_nonblocking(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesRead); + } + + i = 0; + ui32RemainingBytes = ui32NumBytes; + ui32TimeSpent = 0; + + // + // Loop until we're done reading. This will either be because we hit a + // timeout, or we got the right number of bytes. If the caller specified + // "wait forever", then don't check the timeout. + // + while (ui32RemainingBytes && (ui32TimeSpent < ui32TimeoutMs)) + { + // + // Read as much as we can. + // + ui32BytesRead = 0; + ui32Status = read_nonblocking(pHandle, &pui8Data[i], + ui32RemainingBytes, + &ui32BytesRead); + // + // Update the tracking variables. + // + i += ui32BytesRead; + ui32RemainingBytes -= ui32BytesRead; + + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + if (pui32NumBytesRead) + { + *pui32NumBytesRead = i; + } + + return ui32Status; + } + + // + // Update the timeout. + // + if (ui32RemainingBytes) + { + am_hal_flash_delay(FLASH_CYCLES_US(1)); + + if (ui32TimeoutMs != AM_HAL_UART_WAIT_FOREVER) + { + ui32TimeSpent++; + } + } + } + + if (pui32NumBytesRead) + { + *pui32NumBytesRead = i; + } + + return AM_HAL_STATUS_SUCCESS; +} // read_timeout() + +//***************************************************************************** +// +// This function will keep writing bytes until it either sends N bytes or runs +// into an error. +// +//***************************************************************************** +static uint32_t +write_timeout(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten, uint32_t ui32TimeoutMs) +{ + uint32_t ui32Status, ui32BytesWritten, ui32RemainingBytes, + ui32TimeSpent, i; + + i = 0; + ui32RemainingBytes = ui32NumBytes; + ui32TimeSpent = 0; + + // + // If we don't have a timeout, just pass this directly to the nonblocking + // call. + // + if (ui32TimeoutMs == 0) + { + return write_nonblocking(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesWritten); + } + + // + // Loop until we're done write. This will either be because we hit a + // timeout, or we sent the right number of bytes. If the caller specified + // "wait forever", then don't check the timeout. + // + while (ui32RemainingBytes && (ui32TimeSpent < ui32TimeoutMs)) + { + // + // Write as much as we can. + // + ui32BytesWritten = 0; + ui32Status = write_nonblocking(pHandle, &pui8Data[i], + ui32RemainingBytes, + &ui32BytesWritten); + // + // Update the tracking variables. + // + i += ui32BytesWritten; + ui32RemainingBytes -= ui32BytesWritten; + + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + if (pui32NumBytesWritten) + { + *pui32NumBytesWritten = i; + } + + return ui32Status; + } + + // + // Update the timeout. + // + if (ui32RemainingBytes) + { + am_hal_flash_delay(FLASH_CYCLES_US(1)); + + if (ui32TimeoutMs != AM_HAL_UART_WAIT_FOREVER) + { + ui32TimeSpent++; + } + } + } + + if (pui32NumBytesWritten) + { + *pui32NumBytesWritten = i; + } + + return AM_HAL_STATUS_SUCCESS; +} // write_timeout() + +//***************************************************************************** +// +// Send or receive bytes. +// +//***************************************************************************** +uint32_t +am_hal_uart_transfer(void *pHandle, const am_hal_uart_transfer_t *pTransfer) +{ + // + // Pick the right function to use based on the transfer structure. + // + if (pTransfer->ui32Direction == AM_HAL_UART_WRITE) + { + return write_timeout(pHandle, + pTransfer->pui8Data, + pTransfer->ui32NumBytes, + pTransfer->pui32BytesTransferred, + pTransfer->ui32TimeoutMs); + } + else if (pTransfer->ui32Direction == AM_HAL_UART_READ) + { + return read_timeout(pHandle, + pTransfer->pui8Data, + pTransfer->ui32NumBytes, + pTransfer->pui32BytesTransferred, + pTransfer->ui32TimeoutMs); + } + + return AM_HAL_STATUS_INVALID_OPERATION; +} // am_hal_uart_transfer() + +//***************************************************************************** +// +// Wait for all of the traffic in the TX pipeline to be sent. +// +//***************************************************************************** +uint32_t +am_hal_uart_tx_flush(void *pHandle) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // If we have a TX queue, we should wait for it to empty. + // + if (pState->bEnableTxQueue) + { + while (am_hal_queue_data_left(&(pState->sTxQueue))) + { + ONE_BYTE_DELAY(pState); + } + } + + // + // Wait for the TX busy bit to go low. + // + while ( UARTn(ui32Module)->FR_b.BUSY ) + { + ONE_BYTE_DELAY(pState); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_tx_flush() + +//***************************************************************************** +// +// Return the most recent set of UART flags. +// +//***************************************************************************** +uint32_t +am_hal_uart_flags_get(void *pHandle, uint32_t *pui32Flags) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check to make sure this is a valid handle. + // + if ( !AM_HAL_UART_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( pui32Flags ) + { + // + // Set the flags value, then return success. + // + *pui32Flags = UARTn(ui32Module)->FR; + + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + +} // am_hal_uart_flags_get() + +//***************************************************************************** +// +// Empty the UART RX FIFO, and place the data into the RX queue. +// +//***************************************************************************** +static uint32_t +rx_queue_update(void *pHandle) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + + uint8_t pui8Data[AM_HAL_UART_FIFO_MAX]; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus; + + AM_CRITICAL_BEGIN + + // + // Read as much of the FIFO as we can. + // + ui32ErrorStatus = uart_fifo_read(pHandle, pui8Data, AM_HAL_UART_FIFO_MAX, + &ui32BytesTransferred); + // + // If we were successful, go ahead and transfer the data along to the + // buffer. + // + if (ui32ErrorStatus == AM_HAL_STATUS_SUCCESS) + { + if (!am_hal_queue_item_add(&pState->sRxQueue, pui8Data, + ui32BytesTransferred)) + { + ui32ErrorStatus = AM_HAL_UART_STATUS_RX_QUEUE_FULL; + } + } + + AM_CRITICAL_END + + return ui32ErrorStatus; +} // rx_queue_update() + +//***************************************************************************** +// +// Transfer as much data as possible from the TX queue to the TX FIFO. +// +//***************************************************************************** +static uint32_t +tx_queue_update(void *pHandle) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + uint8_t pui8Data; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + + AM_CRITICAL_BEGIN + + // + // Loop as long as the TX fifo isn't full yet. + // + while ( !UARTn(ui32Module)->FR_b.TXFF ) + { + // + // Attempt to grab an item from the queue, and add it to the fifo. + // + if (am_hal_queue_item_get(&pState->sTxQueue, &pui8Data, 1)) + { + ui32ErrorStatus = uart_fifo_write(pHandle, &pui8Data, 1, + &ui32BytesTransferred); + + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + break; + } + } + else + { + // + // If we didn't get anything from the FIFO, we can just return. + // + break; + } + } + + AM_CRITICAL_END + + return ui32ErrorStatus; +} // tx_queue_update() + +//***************************************************************************** +// +// UART FIFO Read. +// +//***************************************************************************** +uint32_t +am_hal_uart_fifo_read(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead) +{ + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + return uart_fifo_read(pHandle, pui8Data, ui32NumBytes, pui32NumBytesRead); +} + +//***************************************************************************** +// +// UART FIFO Write. +// +//***************************************************************************** +uint32_t +am_hal_uart_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten) +{ + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + return uart_fifo_write(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesWritten); +} + +//***************************************************************************** +// +// Interrupt service +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_service(void *pHandle, uint32_t ui32Status, + uint32_t *pui32UartTxIdle) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + uint32_t ui32ErrorStatus; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check to see if we have filled the Rx FIFO past the configured limit, or + // if we have an 'old' character or two sitting in the FIFO. + // + if ((ui32Status & (UART0_IES_RXRIS_Msk | UART0_IES_RTRIS_Msk)) && + pState->bEnableRxQueue) + { + ui32ErrorStatus = rx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // Check to see if our TX buffer has been recently emptied. If so, we + // should refill it from the TX ring buffer. + // + if ((ui32Status & UART0_IES_TXRIS_Msk) && pState->bEnableTxQueue) + { + ui32ErrorStatus = tx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // If this pointer is null, we can just return success now. There is no + // need to figure out if the UARt is idle. + // + if (pui32UartTxIdle == 0) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Check to see if we should report the UART TX-side idle. This is true if + // the queue is empty and the BUSY bit is low. The check is complicated + // because we don't want to check the queue status unless queues have been + // configured. + // + if (pState->bEnableTxQueue) + { + if ( am_hal_queue_empty(&(pState->sTxQueue) ) && + ( UARTn(ui32Module)->FR_b.BUSY == false ) ) + { + *pui32UartTxIdle = true; + } + } + else if ( UARTn(ui32Module)->FR_b.BUSY == false ) + { + *pui32UartTxIdle = true; + } + else + { + *pui32UartTxIdle = false; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_service() + +//***************************************************************************** +// +// Interrupt enable. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_enable(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + UARTn(ui32Module)->IER |= ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_enable() + +//***************************************************************************** +// +// Interrupt disable. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_disable(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + UARTn(ui32Module)->IER &= ~ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_disable() + +//***************************************************************************** +// +// Interrupt clear. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_clear(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + UARTn(ui32Module)->IEC = ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_clear() + +//***************************************************************************** +// +// Returns the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_status_get(void *pHandle, uint32_t *pui32Status, bool bEnabledOnly) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // If requested, only return the interrupts that are enabled. + // + *pui32Status = bEnabledOnly ? UARTn(ui32Module)->MIS : UARTn(ui32Module)->IES; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_status_get() + +//***************************************************************************** +// +// Return the set of enabled interrupts. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_enable_get(void *pHandle, uint32_t *pui32IntMask) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + *pui32IntMask = UARTn(ui32Module)->IER; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_enable_get() diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.h new file mode 100644 index 0000000..519a89b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.h @@ -0,0 +1,724 @@ +//***************************************************************************** +// +// am_hal_uart.h +//! @file +//! +//! @brief Functions for accessing and configuring the UART. +//! +//! @addtogroup uart3 UART +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_UART_H +#define AM_HAL_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable MSPI module number. +// +#define UARTn(n) ((UART0_Type*)(UART0_BASE + (n * (UART1_BASE - UART0_BASE)))) +//***************************************************************************** + +//***************************************************************************** +// +// UART configuration options. +// +//***************************************************************************** +typedef struct +{ + // + // Standard UART options. + // + uint32_t ui32BaudRate; + uint32_t ui32DataBits; + uint32_t ui32Parity; + uint32_t ui32StopBits; + uint32_t ui32FlowControl; + + // + // Additional options. + // + uint32_t ui32FifoLevels; + + // + // Buffers + // + uint8_t *pui8TxBuffer; + uint32_t ui32TxBufferSize; + uint8_t *pui8RxBuffer; + uint32_t ui32RxBufferSize; +} +am_hal_uart_config_t; + +//***************************************************************************** +// +// @brief UART transfer structure. +// +// This structure describes a UART transaction that can be performed by \e +// am_hal_uart_transfer() +// +//***************************************************************************** +typedef struct +{ + //! Determines whether data should be read or written. + //! + //! Should be either AM_HAL_UART_WRITE or AM_HAL_UART_READ + uint32_t ui32Direction; + + //! Pointer to data to be sent, or space to fill with received data. + uint8_t *pui8Data; + + //! Number of bytes to send or receive. + uint32_t ui32NumBytes; + + //! Timeout in milliseconds. + //! + //! Given a timeout value, the \e am_hal_uart_transfer() function will keep + //! trying to transfer data until either the number of bytes is satisfied, + //! or the time runs out. If provided with a value of zero, the transfer + //! function will only send as much data as it can immediately deal with. + //! If provided with a timeout value of \e AM_HAL_UART_WAIT_FOREVER, the + //! function will block until either the final "read" byte is received or + //! the final "write" byte is placed in the output buffer. + uint32_t ui32TimeoutMs; + + //! Number of bytes successfully transferred. + uint32_t *pui32BytesTransferred; +} +am_hal_uart_transfer_t; + +//***************************************************************************** +// +// Maximum baudrate supported is 921600 for Apollo3-A1 and 1.5Mbaud for +// Apollo3-B0. +// +//***************************************************************************** +#define AM_HAL_UART_MAXIMUM_BAUDRATE_A1 921600 +#define AM_HAL_UART_MAXIMUM_BAUDRATE_B0 1500000 + +//***************************************************************************** +// +// Uart transfer options. +// +//***************************************************************************** +#define AM_HAL_UART_WRITE 0 +#define AM_HAL_UART_READ 1 +#define AM_HAL_UART_WAIT_FOREVER 0xFFFFFFFF + +//***************************************************************************** +// +// UART conficuration option values. +// +//***************************************************************************** + +// Data bits. +#define AM_HAL_UART_DATA_BITS_8 (_VAL2FLD(UART0_LCRH_WLEN, 3)) +#define AM_HAL_UART_DATA_BITS_7 (_VAL2FLD(UART0_LCRH_WLEN, 2)) +#define AM_HAL_UART_DATA_BITS_6 (_VAL2FLD(UART0_LCRH_WLEN, 1)) +#define AM_HAL_UART_DATA_BITS_5 (_VAL2FLD(UART0_LCRH_WLEN, 0)) + +// Parity. +#define AM_HAL_UART_PARITY_NONE 0 +#define AM_HAL_UART_PARITY_ODD UART0_LCRH_PEN_Msk +#define AM_HAL_UART_PARITY_EVEN (UART0_LCRH_PEN_Msk | \ + UART0_LCRH_EPS_Msk) +// Stop Bits +#define AM_HAL_UART_ONE_STOP_BIT (_VAL2FLD(UART0_LCRH_STP2, 0)) +#define AM_HAL_UART_TWO_STOP_BITS (_VAL2FLD(UART0_LCRH_STP2, 1)) + +// Flow control +#define AM_HAL_UART_FLOW_CTRL_NONE 0 +#define AM_HAL_UART_FLOW_CTRL_CTS_ONLY UART0_CR_CTSEN_Msk +#define AM_HAL_UART_FLOW_CTRL_RTS_ONLY UART0_CR_RTSEN_Msk +#define AM_HAL_UART_FLOW_CTRL_RTS_CTS (UART0_CR_CTSEN_Msk | \ + UART0_CR_RTSEN_Msk) +// FIFO enable/disable. +#define AM_HAL_UART_FIFO_ENABLE (_VAL2FLD(UART0_LCRH_FEN, 1)) +#define AM_HAL_UART_FIFO_DISABLE (_VAL2FLD(UART0_LCRH_FEN, 0)) + +// TX FIFO interrupt level settings. +#define AM_HAL_UART_TX_FIFO_1_8 (_VAL2FLD(UART0_IFLS_TXIFLSEL, 0)) +#define AM_HAL_UART_TX_FIFO_1_4 (_VAL2FLD(UART0_IFLS_TXIFLSEL, 1)) +#define AM_HAL_UART_TX_FIFO_1_2 (_VAL2FLD(UART0_IFLS_TXIFLSEL, 2)) +#define AM_HAL_UART_TX_FIFO_3_4 (_VAL2FLD(UART0_IFLS_TXIFLSEL, 3)) +#define AM_HAL_UART_TX_FIFO_7_8 (_VAL2FLD(UART0_IFLS_TXIFLSEL, 4)) + +// RX FIFO interrupt level settings. +#define AM_HAL_UART_RX_FIFO_1_8 (_VAL2FLD(UART0_IFLS_RXIFLSEL, 0)) +#define AM_HAL_UART_RX_FIFO_1_4 (_VAL2FLD(UART0_IFLS_RXIFLSEL, 1)) +#define AM_HAL_UART_RX_FIFO_1_2 (_VAL2FLD(UART0_IFLS_RXIFLSEL, 2)) +#define AM_HAL_UART_RX_FIFO_3_4 (_VAL2FLD(UART0_IFLS_RXIFLSEL, 3)) +#define AM_HAL_UART_RX_FIFO_7_8 (_VAL2FLD(UART0_IFLS_RXIFLSEL, 4)) + +//***************************************************************************** +// +// UART interrupts. +// +//***************************************************************************** +#define AM_HAL_UART_INT_OVER_RUN UART0_IER_OEIM_Msk +#define AM_HAL_UART_INT_BREAK_ERR UART0_IER_BEIM_Msk +#define AM_HAL_UART_INT_PARITY_ERR UART0_IER_PEIM_Msk +#define AM_HAL_UART_INT_FRAME_ERR UART0_IER_FEIM_Msk +#define AM_HAL_UART_INT_RX_TMOUT UART0_IER_RTIM_Msk +#define AM_HAL_UART_INT_TX UART0_IER_TXIM_Msk +#define AM_HAL_UART_INT_RX UART0_IER_RXIM_Msk +#define AM_HAL_UART_INT_DSRM UART0_IER_DSRMIM_Msk +#define AM_HAL_UART_INT_DCDM UART0_IER_DCDMIM_Msk +#define AM_HAL_UART_INT_CTSM UART0_IER_CTSMIM_Msk +#define AM_HAL_UART_INT_TXCMP UART0_IER_TXCMPMIM_Msk + +//***************************************************************************** +// +//! @name UART Flag Register +//! @brief Macro definitions for UART Flag Register Bits. +//! +//! They may be used with the \e am_hal_uart_flags_get() function. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_UART_FR_TX_EMPTY (_VAL2FLD(UART0_FR_TXFE, UART0_FR_TXFE_XMTFIFO_EMPTY)) +#define AM_HAL_UART_FR_RX_FULL (_VAL2FLD(UART0_FR_RXFF, UART0_FR_RXFF_RCVFIFO_FULL)) +#define AM_HAL_UART_FR_TX_FULL (_VAL2FLD(UART0_FR_TXFF, UART0_FR_TXFF_XMTFIFO_FULL)) +#define AM_HAL_UART_FR_RX_EMPTY (_VAL2FLD(UART0_FR_RXFE, UART0_FR_RXFE_RCVFIFO_EMPTY)) +#define AM_HAL_UART_FR_BUSY (_VAL2FLD(UART0_FR_BUSY, UART0_FR_BUSY_BUSY)) +#define AM_HAL_UART_FR_DCD_DETECTED (_VAL2FLD(UART0_FR_DCD, UART0_FR_DCD_DETECTED)) +#define AM_HAL_UART_FR_DSR_READY (_VAL2FLD(UART0_FR_DSR, UART0_FR_DSR_READY)) +#define AM_HAL_UART_FR_CTS UART0_FR_CTS_Msk + +//! @} + +//***************************************************************************** +// +// UART FIFO size for Apollo3. +// +//***************************************************************************** +#define AM_HAL_UART_FIFO_MAX 32 + +//***************************************************************************** +// +// Turn timeouts into indefinite waits. +// +//***************************************************************************** +#define AM_HAL_UART_WAIT_FOREVER 0xFFFFFFFF + +//***************************************************************************** +// +//! @brief Initialize the UART interface. +//! +//! @param ui32Module is the module number for the UART to initialize. +//! @param ppHandle is the location to write the UART handle. +//! +//! This function sets internal tracking variables associated with a specific +//! UART module. It should be the first UART API called for each UART module in +//! use. The handle can be used to interact with the UART +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_initialize(uint32_t ui32Module, void **ppHandle); + +//***************************************************************************** +// +//! @brief Deinitialize the UART interface. +//! +//! @param pHandle is a previously initialized UART handle. +//! +//! This function effectively disables future calls to interact with the UART +//! refered to by \e pHandle. The user may call this function if UART operation +//! is no longer desired. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_deinitialize(void *pHandle); + +//***************************************************************************** +// +//! @brief Change the power state of the UART module. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param ePowerstate is the desired power state of the UART. +//! @parame bRetainState is a flag to ask the HAL to save UART registers. +//! +//! This function can be used to switch the power to the UART on or off. If \e +//! bRetainState is true during a powerdown operation, it will store the UART +//! configuration registers to SRAM, so it can restore them on power-up. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState); + +//***************************************************************************** +// +//! @brief Used to configure basic UART settings. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param psConfig is a structure of UART configuration options. +//! +//! This function takes the options from an \e am_hal_uart_config_t structure, +//! and applies them to the UART referred to by \e pHandle. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_configure(void *pHandle, + const am_hal_uart_config_t *psConfig); + +extern uint32_t am_hal_uart_configure_fifo(void *pHandle, + const am_hal_uart_config_t *psConfig, + bool bEnableFIFO); + +//***************************************************************************** +// +//! @brief Transfer data through the UART interface. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param am_hal_uart_transfer_t is a structure describing the operation. +//! +//! This function executes a transaction as described by the \e +//! am_hal_uart_transfer_t structure. It can either read or write, and it will +//! take advantage of any buffer space provided by the \e +//! am_hal_uart_configure() function. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_transfer(void *pHandle, + const am_hal_uart_transfer_t *pTransfer); + +//***************************************************************************** +// +//! @brief Wait for the UART TX to become idle +//! +//! @param pHandle is the handle for the UART to operate on. +//! +//! This function waits (polling) for all data in the UART TX FIFO and UART TX +//! buffer (if configured) to be fully sent on the physical UART interface. +//! This is not the most power-efficient way to wait for UART idle, but it can be +//! useful in simpler applications, or where power-efficiency is less important. +//! +//! Once this function returns, the UART can be safely disabled without +//! interfering with any previous transmissions. +//! +//! For a more power-efficient way to shut down the UART, check the +//! \e am_hal_uart_interrupt_service() function. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_tx_flush(void *pHandle); + +//***************************************************************************** +// +//! @brief Read the UART flags. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param pui32Flags is the destination pointer for the UART flags. +//! +//! The UART hardware provides some information about the state of the physical +//! interface at all times. This function provides a way to read that data +//! directly. Below is a list of all possible UART flags. +//! +//! These correspond directly to the bits in the UART_FR register. +//! +//! @code +//! +//! AM_HAL_UART_FR_TX_EMPTY +//! AM_HAL_UART_FR_RX_FULL +//! AM_HAL_UART_FR_TX_FULL +//! AM_HAL_UART_FR_RX_EMPTY +//! AM_HAL_UART_FR_BUSY +//! AM_HAL_UART_FR_DCD_DETECTED +//! AM_HAL_UART_FR_DSR_READY +//! AM_HAL_UART_FR_CTS +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_flags_get(void *pHandle, uint32_t *pui32Flags); + +//***************************************************************************** +// +//! @brief Read the UART FIFO directly. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param pui8Data is a pointer where the UART data should be written. +//! @param ui32NumBytes is the number of bytes to transfer. +//! @param pui32NumBytesRead is the nubmer of bytes actually transferred. +//! +//! This function reads the UART FIFO directly, and writes the resulting bytes +//! to pui8Data. Since the UART FIFO hardware has no direct size indicator, the +//! caller can only specify the maximum number of bytes they can handle. This +//! function will try to read as many bytes as possible. At the end of the +//! transfer, the number of bytes actually transferred will be written to the +//! pui32NumBytesRead parameter. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART error. +// +//***************************************************************************** +extern uint32_t am_hal_uart_fifo_read(void *pHandle, + uint8_t *pui8Data, + uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead); + +//***************************************************************************** +// +//! @brief Write the UART FIFO directly. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param pui8Data is a pointer where the UART data should be written. +//! @param ui32NumBytes is the number of bytes to transfer. +//! @param pui32NumBytesWritten is the nubmer of bytes actually transferred. +//! +//! This function reads from pui8Data, and writes the requested number of bytes +//! directly to the UART FIFO. Since the UART FIFO hardware has no register to +//! tell us how much free space it has, the caller can only specify the number +//! of bytes they would like to send. This function will try to write as many +//! bytes as possible up to the requested number. At the end of the transfer, +//! the number of bytes actually transferred will be written to the +//! pui32NumBytesWritten parameter. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART error. +// +//***************************************************************************** +extern uint32_t am_hal_uart_fifo_write(void *pHandle, + uint8_t *pui8Data, + uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten); + +//***************************************************************************** +// +//! @brief This function handles the UART buffers during UART interrupts. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param ui32Status is the interrupt status at the time of ISR entry. +//! @param pui32UartTxIdle can be used to store the UART idle status. +//! +//! The main purpose of this function is to manage the UART buffer system. Any +//! buffers configured by \e am_hal_uart_buffer_configure will be managed by +//! this service routine. Data queued for transmit will be added to the UART TX +//! FIFO as space allows, and data stored in the UART RX FIFO will be copied +//! out and stored in the RX buffer. This function will skip this transfer for +//! any buffer that has not been configured. +//! +//! In addition, this function can be used to alert the caller when the UART +//! becomes idle via the optional \e pui32UartTxIdle argument. This function +//! will set this variable any time it completes its operation and the UART TX +//! channel is no longer in use (including both the FIFO and any configured +//! buffer). To make sure this happens as early as possible, the user may +//! enable the UART_TXCMP interrupt as shown below. +//! +//! For RTOS-enabled cases, this function does not necessarily need to be +//! called inside the actual ISR for the UART, but it should be called promptly +//! in response to the receipt of a UART TX, RX, or RX timeout interrupt. If +//! the service routine is not called quickly enough, the caller risks an RX +//! FIFO overflow (data can be lost here), or a TX FIFO underflow (usually not +//! harmful). +//! +//! @code +//! +//! void +//! am_uart_isr(void) +//! { +//! // +//! // Service the FIFOs as necessary, and clear the interrupts. +//! // +//! uint32_t ui32Status; +//! uint32_t ui32UartIdle; +//! +//! am_hal_uart_interrupt_status_get(UART, &ui32Status, true); +//! am_hal_uart_interrupt_clear(UART, ui32Status); +//! am_hal_uart_interrupt_service(UART, ui32Status, &ui32UartIdle); +//! +//! ui32TXDoneFlag = ui32UartIdle; +//! } +//! +//! int +//! main(void) +//! { +//! ... +//! +//! // Initialize, power up, and configure the UART. +//! am_hal_uart_initialize(0, &UART); +//! am_hal_uart_power_control(UART, AM_HAL_SYSCTRL_WAKE, false); +//! am_hal_uart_configure(UART, &sUartConfig); +//! +//! ... +//! +//! // Enable the UART0 interrupt vector. +//! am_hal_uart_interrupt_enable(UART, AM_REG_UART_IER_TXCMPMIM_M); +//! am_hal_interrupt_enable(AM_HAL_INTERRUPT_UART0); +//! am_hal_interrupt_master_enable(); +//! } +//! +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_service(void *pHandle, + uint32_t ui32Status, + uint32_t *pui32UartTxIdle); + +//***************************************************************************** +// +//! @brief Enable interrupts. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param ui32IntMask is the bitmask of interrupts to enable. +//! +//! This function enables the UART interrupt(s) given by ui32IntMask. If +//! multiple interrupts are desired, they can be OR'ed together. +//! +//! @note This function need not be called for UART FIFO interrupts if the UART +//! buffer service provided by \e am_hal_uart_buffer_configure() and \e +//! am_hal_uart_interrupt_service() is already in use. Non-FIFO-related +//! interrupts do require the use of this function. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_enable(void *pHandle, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Disable interrupts. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param ui32IntMask is the bitmask of interrupts to disable. +//! +//! This function disables the UART interrupt(s) given by ui32IntMask. If +//! multiple interrupts need to be disabled, they can be OR'ed together. +//! +//! @note This function need not be called for UART FIFO interrupts if the UART +//! buffer service provided by \e am_hal_uart_buffer_configure() and \e +//! am_hal_uart_interrupt_service() is already in use. Non-FIFO-related +//! interrupts do require the use of this function. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_disable(void *pHandle, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Clear interrupt status. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param ui32IntMask is the bitmask of interrupts to clear. +//! +//! This function clears the UART interrupt(s) given by ui32IntMask. If +//! multiple interrupts need to be cleared, they can be OR'ed together. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_clear(void *pHandle, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Read interrupt status. +//! +//! @param pHandle is the handle for the UART to operate on. +//! +//! @param pui32Status is the returned interrupt status (all bits OR'ed +//! together) +//! +//! @param bEnabled determines whether to read interrupts that were not +//! enabled. +//! +//! This function reads the status the UART interrupt(s) if \e bEnabled is +//! true, it will only return the status of the enabled interrupts. Otherwise, +//! it will return the status of all interrupts, enabled or disabled. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_status_get(void *pHandle, + uint32_t *pui32Status, + bool bEnabledOnly); + +typedef enum +{ + AM_HAL_UART_STATUS_BUS_ERROR = AM_HAL_STATUS_MODULE_SPECIFIC_START, + AM_HAL_UART_STATUS_RX_QUEUE_FULL, + AM_HAL_UART_STATUS_CLOCK_NOT_CONFIGURED, + AM_HAL_UART_STATUS_BAUDRATE_NOT_POSSIBLE, +} +am_hal_uart_errors_t; + +//***************************************************************************** +// +//! @brief Check to see which interrupts are enabled. +//! +//! @param pHandle is the handle for the UART to operate on. +//! +//! @param pui32IntMask is the current set of interrupt enable bits (all bits +//! OR'ed together) +//! +//! This function checks the UART Interrupt Enable Register to see which UART +//! interrupts are currently enabled. The result will be an interrupt mask with +//! one bit set for each of the currently enabled UART interrupts. +//! +//! The full set of UART interrupt bits is given by the list below: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_enable_get(void *pHandle, uint32_t *pui32IntMask); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_UART_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.c new file mode 100644 index 0000000..d93aad5 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.c @@ -0,0 +1,417 @@ +//***************************************************************************** +// +// am_hal_wdt.c +//! @file +//! +//! @brief Hardware abstraction layer for the Watchdog Timer module. +//! +//! @addtogroup wdt3 Watchdog Timer (WDT) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Adjacency check +// +// This is related to the timer read workaround. This macro checks to see if +// the two supplied count values are within one "tick" of eachother. It should +// still pass in the event of a timer rollover. The "B" read is assumed to +// follow the "A" read. The macro returns "TRUE" when the adjacent timer reads +// can be used. +// +//***************************************************************************** +#define adjacent(A, B) (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0)) + +//***************************************************************************** +// +//! @brief Configure the watchdog timer. +//! +//! @param psConfig - pointer to a configuration structure containing the +//! desired watchdog settings. +//! +//! This function will set the watchdog configuration register based on the +//! user's desired settings listed in the structure referenced by psConfig. If +//! the structure indicates that watchdog interrupts are desired, this function +//! will also set the interrupt enable bit in the configuration register. +//! +//! @note In order to actually receive watchdog interrupt and/or watchdog reset +//! events, the caller will also need to make sure that the watchdog interrupt +//! vector is enabled in the ARM NVIC, and that watchdog resets are enabled in +//! the reset generator module. Otherwise, the watchdog-generated interrupt and +//! reset events will have no effect. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_init(const am_hal_wdt_config_t *psConfig) +{ + uint32_t ui32ConfigVal; + uint16_t ui16IntCount, ui16ResetCount; + bool bResetEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_RESET; + bool bInterruptEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_INTERRUPT; + + // + // Read the desired settings from the psConfig structure. + // + ui16IntCount = psConfig->ui16InterruptCount; + ui16ResetCount = psConfig->ui16ResetCount; + + // + // Write the interrupt and reset count values to a temporary variable. + // + // Accept the passed Config value, but clear the Counts that we are about to set. + ui32ConfigVal = psConfig->ui32Config & ~(WDT_CFG_INTVAL_Msk | WDT_CFG_RESVAL_Msk); + ui32ConfigVal |= _VAL2FLD(WDT_CFG_INTVAL, ui16IntCount); + ui32ConfigVal |= _VAL2FLD(WDT_CFG_RESVAL, ui16ResetCount); + + // + // If interrupts should be enabled, set the appropriate bit in the + // temporary variable. Also, enable the interrupt in INTEN register in the + // watchdog module. + // + if ( bInterruptEnabled ) + { + // + // Enable the watchdog interrupt if the configuration calls for them. + // + WDT->INTEN |= WDT_INTEN_WDTINT_Msk; + } + else + { + // + // Disable the watchdog interrupt if the configuration doesn't call for + // watchdog interrupts. + // + WDT->INTEN &= ~WDT_INTEN_WDTINT_Msk; + } + + // + // If resets should be enabled, set the appropriate bit in the temporary + // variable. + // + if ( bResetEnabled ) + { + // + // Also enable watchdog resets in the reset module. + // + RSTGEN->CFG |= RSTGEN_CFG_WDREN_Msk; + } + else + { + // + // Disable watchdog resets in the reset module. + // + RSTGEN->CFG &= ~RSTGEN_CFG_WDREN_Msk; + } + + // + // Check for a user specified clock select. If none specified then + // set 128Hz. + // + if ( !(psConfig->ui32Config & WDT_CFG_CLKSEL_Msk) ) + { + ui32ConfigVal |= _VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_128HZ); + } + + // + // Write the saved value to the watchdog configuration register. + // + WDT->CFG = ui32ConfigVal; +} // am_hal_wdt_init() + +//***************************************************************************** +// +//! @brief Starts the watchdog timer. +//! +//! Enables the watchdog timer tick using the 'enable' bit in the watchdog +//! configuration register. This function does not perform any locking of the +//! watchdog timer, so it can be disabled or reconfigured later. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_start(void) +{ + // + // Make sure the watchdog timer is in the "reset" state, and then set the + // enable bit to start counting. + // + WDT->CFG |= WDT_CFG_WDTEN_Msk; + WDT->RSTRT = WDT_RSTRT_RSTRT_KEYVALUE; +} // am_hal_wdt_start() + +//***************************************************************************** +// +//! @brief Stops the watchdog timer. +//! +//! Disables the watchdog timer tick by clearing the 'enable' bit in the +//! watchdog configuration register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_halt(void) +{ + // + // Clear the watchdog enable bit. + // + WDT->CFG &= ~WDT_CFG_WDTEN_Msk; +} // am_hal_wdt_halt() + +//***************************************************************************** +// +//! @brief Locks the watchdog configuration and starts the watchdog timer. +//! +//! This function sets the watchdog "lock" register, which prevents software +//! from re-configuring the watchdog. This action will also set the enable bit +//! for the watchdog timer, so it will start counting immediately. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_lock_and_start(void) +{ + // + // Write the 'key' value to the watchdog lock register. + // + WDT->LOCK = WDT_LOCK_LOCK_KEYVALUE; +} // am_hal_wdt_lock_and_start() + +//***************************************************************************** +// +//! @brief Read the state of the wdt interrupt status. +//! +//! @param bEnabledOnly - return the status of only the enabled interrupts. +//! +//! This function extracts the interrupt status bits and returns the enabled or +//! raw based on bEnabledOnly. +//! +//! @return WDT interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_wdt_int_status_get(bool bEnabledOnly) +{ + if ( bEnabledOnly ) + { + uint32_t ui32RetVal; + AM_CRITICAL_BEGIN + ui32RetVal = WDT->INTSTAT; + ui32RetVal &= WDT->INTEN; + AM_CRITICAL_END + return ui32RetVal; + } + else + { + return WDT->INTSTAT; + } +} // am_hal_wdt_int_status_get() + +//***************************************************************************** +// +//! @brief Set the state of the wdt interrupt status bit. +//! +//! This function sets the interrupt bit. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_set(void) +{ + WDT->INTSET = WDT_INTSET_WDTINT_Msk; +} // am_hal_wdt_int_set() + +//***************************************************************************** +// +//! @brief Clear the state of the wdt interrupt status bit. +//! +//! This function clear the interrupt bit. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_clear(void) +{ + WDT->INTCLR = WDT_INTCLR_WDTINT_Msk; +} // am_hal_wdt_int_clear() + +//***************************************************************************** +// +//! @brief Enable the wdt interrupt. +//! +//! This function enable the interrupt. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_enable(void) +{ + WDT->INTEN |= WDT_INTEN_WDTINT_Msk; +} // am_hal_wdt_int_enable() + +//***************************************************************************** +// +//! @brief Return the enabled WDT interrupts. +//! +//! This function returns the enabled WDT interrupts. +//! +//! @return enabled WDT interrupts. +// +//***************************************************************************** +uint32_t +am_hal_wdt_int_enable_get(void) +{ + return WDT->INTEN; +} // am_hal_wdt_int_enable_get() + +//***************************************************************************** +// +//! @brief Disable the wdt interrupt. +//! +//! This function disablee the interrupt. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_disable(void) +{ + WDT->INTEN &= ~WDT_INTEN_WDTINT_Msk; +} // am_hal_wdt_int_disable() + +//***************************************************************************** +// +//! @brief Get the wdt counter value. +//! +//! This function reads the current value of watch dog timer counter register. +//! +//! @return None +// +//***************************************************************************** +uint32_t +am_hal_wdt_counter_get(void) +{ + uint32_t ui32Values[3] = {0}; + uint32_t ui32Value; + + // + // Start a critical section. + // + uint32_t ui32InterruptState = am_hal_interrupt_master_disable(); + + // + // First, go read the value from the counter register 3 times + // back to back in assembly language. + // + am_hal_triple_read( AM_REGADDR(WDT, COUNT), ui32Values ); + + // + // Mask out the COUNT field from the 3 read values. + // + ui32Values[0] = _VAL2FLD(WDT_COUNT_COUNT, ui32Values[0]); + ui32Values[1] = _VAL2FLD(WDT_COUNT_COUNT, ui32Values[1]); + ui32Values[2] = _VAL2FLD(WDT_COUNT_COUNT, ui32Values[2]); + + // + // Now, we'll figure out which of the three values is the correct time. + // + if (ui32Values[0] == ui32Values[1]) + { + // + // If the first two values match, then neither one was a bad read. + // We'll take this as the current time. + // + ui32Value = ui32Values[1]; + } + else + { + // + // If the first two values didn't match, then one of them might be bad. + // If one of the first two values is bad, then the third one should + // always be correct. We'll take the third value as the correct count. + // + ui32Value = ui32Values[2]; + + // + // If all of the statements about the architecture are true, the third + // value should be correct, and it should always be within one count of + // either the first or the second value. + // + // Just in case, we'll check against the previous two values to make + // sure that our final answer was reasonable. If it isn't, we will + // flag it as a "bad read", and fail this assert statement. + // + // This shouldn't ever happen, and it hasn't ever happened in any of + // our tests so far. + // + am_hal_debug_assert_msg((adjacent(ui32Values[1], ui32Values[2]) || + adjacent(ui32Values[0], ui32Values[2])), + "Bad CDT read"); + } + + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32InterruptState); + + return ui32Value; +} // am_hal_wdt_counter_get() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.h new file mode 100644 index 0000000..ea9019b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.h @@ -0,0 +1,188 @@ +//***************************************************************************** +// +// am_hal_wdt.h +//! @file +//! +//! @brief Hardware abstraction layer for the Watchdog Timer module. +//! +//! @addtogroup wdt3 Watchdog Timer (WDT) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_WDT_H +#define AM_HAL_WDT_H + +#include +#include + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** + +//***************************************************************************** +// +//! @name WDT Clock Divider Selections. +//! @brief Macro definitions for WDT clock frequencies. +//! +//! These macros may be used with the am_hal_wdt_config_t structure to set the +//! clock frequency of the watch dog timer. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_WDT_LFRC_CLK_DEFAULT (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_128HZ)) +#define AM_HAL_WDT_LFRC_CLK_128HZ (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_128HZ)) +#define AM_HAL_WDT_LFRC_CLK_16HZ (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_16HZ)) +#define AM_HAL_WDT_LFRC_CLK_1HZ (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_1HZ)) +#define AM_HAL_WDT_LFRC_CLK_1_16HZ (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_1_16HZ)) +#define AM_HAL_WDT_LFRC_CLK_OFF (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_OFF)) +//! @} + +//***************************************************************************** +// +//! @name WDT Enable Reset in the WDT Configuration. +//! @brief Macro definitions for WDT Reset Enable. +//! +//! These macros may be used with the am_hal_wdt_config_t structure to enable +//! the watch dog timer to generate resets to the chip. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_WDT_ENABLE_RESET (_VAL2FLD(WDT_CFG_RESEN, 1)) +#define AM_HAL_WDT_DISABLE_RESET (_VAL2FLD(WDT_CFG_RESEN, 0)) +//! @} + +//***************************************************************************** +// +//! @name WDT Enable Interrupt Generation from the WDT Configuration. +//! @brief Macro definitions for WDT Interrupt Enable. +//! +//! These macros may be used with the am_hal_wdt_config_t structure to enable +//! the watch dog timer to generate generate WDT interrupts. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_WDT_ENABLE_INTERRUPT (_VAL2FLD(WDT_CFG_INTEN, 1)) +#define AM_HAL_WDT_DISABLE_INTERRUPT (_VAL2FLD(WDT_CFG_INTEN, 0)) +//! @} + +//***************************************************************************** +// +//! @brief Watchdog timer configuration structure. +//! +//! This structure is made to be used with the am_hal_wdt_init() function. It +//! describes the configuration of the watchdog timer. +// +//***************************************************************************** +typedef struct +{ + //! Configuration Values for watchdog timer + //! event is generated. + uint32_t ui32Config; + + //! Number of watchdog timer ticks allowed before a watchdog interrupt + //! event is generated. + uint16_t ui16InterruptCount; + + //! Number of watchdog timer ticks allowed before the watchdog will issue a + //! system reset. + uint16_t ui16ResetCount; + +} +am_hal_wdt_config_t; + +//***************************************************************************** +// +//! @brief Restarts the watchdog timer ("Pets" the dog) +//! +//! This function restarts the watchdog timer from the beginning, preventing +//! any interrupt or reset even from occuring until the next time the watchdog +//! timer expires. +//! +//! @return None. +// +//***************************************************************************** +#define am_hal_wdt_restart() \ + do \ + { \ + WDT->RSTRT = WDT_RSTRT_RSTRT_KEYVALUE; \ + (void)(WDT->RSTRT); \ + } \ + while (0) + +#ifdef __cplusplus +extern "C" +{ +#endif +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_wdt_init(const am_hal_wdt_config_t *psConfig); +extern void am_hal_wdt_start(void); +extern void am_hal_wdt_halt(void); +extern void am_hal_wdt_lock_and_start(void); +extern uint32_t am_hal_wdt_counter_get(void); +extern void am_hal_wdt_int_enable(void); +extern uint32_t am_hal_wdt_int_enable_get(void); +extern void am_hal_wdt_int_disable(void); +extern void am_hal_wdt_int_clear(void); +extern void am_hal_wdt_int_set(void); +extern uint32_t am_hal_wdt_int_status_get(bool bEnabledOnly); +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_WDT_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg.h new file mode 100644 index 0000000..4c96cc8 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg.h @@ -0,0 +1,282 @@ +//***************************************************************************** +// +// am_reg.h +//! @file +//! +//! @brief Apollo4 register macros +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_REG_H +#define AM_REG_H + +//***************************************************************************** +// +// ADC +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_ADC_NUM_MODULES 1 +#define AM_REG_ADCn(n) \ + (REG_ADC_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// APBDMA +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_APBDMA_NUM_MODULES 1 +#define AM_REG_APBDMAn(n) \ + (REG_APBDMA_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// BLEIF +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_BLEIF_NUM_MODULES 1 +#define AM_REG_BLEIFn(n) \ + (REG_BLEIF_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// CACHECTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_CACHECTRL_NUM_MODULES 1 +#define AM_REG_CACHECTRLn(n) \ + (REG_CACHECTRL_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// CLKGEN +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_CLKGEN_NUM_MODULES 1 +#define AM_REG_CLKGENn(n) \ + (REG_CLKGEN_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// CTIMER +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_CTIMER_NUM_MODULES 1 +#define AM_REG_CTIMERn(n) \ + (REG_CTIMER_BASEADDR + 0x00000020 * n) + + +//***************************************************************************** +// +// FLASHCTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_FLASHCTRL_NUM_MODULES 1 +#define AM_REG_FLASHCTRLn(n) \ + (REG_FLASHCTRL_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// GPIO +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_GPIO_NUM_MODULES 1 +#define AM_REG_GPIOn(n) \ + (REG_GPIO_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// IOM +// Instance finder. (6 instance(s) available) +// +//***************************************************************************** +#define AM_REG_IOM_NUM_MODULES 6 +#define AM_REG_IOMn(n) \ + (REG_IOM_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// IOSLAVE +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_IOSLAVE_NUM_MODULES 1 +#define AM_REG_IOSLAVEn(n) \ + (REG_IOSLAVE_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// MCUCTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_MCUCTRL_NUM_MODULES 1 +#define AM_REG_MCUCTRLn(n) \ + (REG_MCUCTRL_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// MSPI +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_MSPI_NUM_MODULES 1 +#define AM_REG_MSPIn(n) \ + (REG_MSPI_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// PDM +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_PDM_NUM_MODULES 1 +#define AM_REG_PDMn(n) \ + (REG_PDM_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// PWRCTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_PWRCTRL_NUM_MODULES 1 +#define AM_REG_PWRCTRLn(n) \ + (REG_PWRCTRL_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// RSTGEN +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_RSTGEN_NUM_MODULES 1 +#define AM_REG_RSTGENn(n) \ + (REG_RSTGEN_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// RTC +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_RTC_NUM_MODULES 1 +#define AM_REG_RTCn(n) \ + (REG_RTC_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// SCARD +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_SCARD_NUM_MODULES 1 +#define AM_REG_SCARDn(n) \ + (REG_SCARD_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// SECURITY +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_SECURITY_NUM_MODULES 1 +#define AM_REG_SECURITYn(n) \ + (REG_SECURITY_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// UART +// Instance finder. (2 instance(s) available) +// +//***************************************************************************** +#define AM_REG_UART_NUM_MODULES 2 +#define AM_REG_UARTn(n) \ + (REG_UART_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// VCOMP +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_VCOMP_NUM_MODULES 1 +#define AM_REG_VCOMPn(n) \ + (REG_VCOMP_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// WDT +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_WDT_NUM_MODULES 1 +#define AM_REG_WDTn(n) \ + (REG_WDT_BASEADDR + 0x00000000 * n) + + +#endif // AM_REG_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_base_addresses.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_base_addresses.h new file mode 100644 index 0000000..bd62110 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_base_addresses.h @@ -0,0 +1,99 @@ +//***************************************************************************** +// +// am_reg_base_addresses.h +//! @file +//! +//! @brief Register defines for all module base addresses +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_REG_BASE_ADDRESSES_H +#define AM_REG_BASE_ADDRESSES_H + +#include "stdint.h" + +// +// ARM standard register space (needed for macros) +// +#define REG_ITM_BASEADDR (0x00000000UL) +#define REG_JEDEC_BASEADDR (0x00000000UL) +#define REG_NVIC_BASEADDR (0x00000000UL) +#define REG_SYSCTRL_BASEADDR (0x00000000UL) +#define REG_SYSTICK_BASEADDR (0x00000000UL) +#define REG_TPIU_BASEADDR (0x00000000UL) + +// +// Peripheral register space +// +#define REG_ADC_BASEADDR (0x50010000UL) +#define REG_APBDMA_BASEADDR (0x40011000UL) +#define REG_BLEIF_BASEADDR (0x5000C000UL) +#define REG_CACHECTRL_BASEADDR (0x40018000UL) +#define REG_CLKGEN_BASEADDR (0x40004000UL) +#define REG_CTIMER_BASEADDR (0x40008000UL) +#define REG_GPIO_BASEADDR (0x40010000UL) +//#define REG_IOMSTR_BASEADDR (0x50004000UL) +#define REG_IOM_BASEADDR (0x50004000UL) +#define REG_IOSLAVE_BASEADDR (0x50000000UL) +#define REG_MCUCTRL_BASEADDR (0x40020000UL) +#define REG_MSPI_BASEADDR (0x50014000UL) +#define REG_PDM_BASEADDR (0x50011000UL) +#define REG_PWRCTRL_BASEADDR (0x40021000UL) +#define REG_RSTGEN_BASEADDR (0x40000000UL) +#define REG_RTC_BASEADDR (0x40004200UL) +#define REG_SCARD_BASEADDR (0x40080000UL) +#define REG_SECURITY_BASEADDR (0x40030000UL) +#define REG_UART_BASEADDR (0x4001C000UL) +#define REG_VCOMP_BASEADDR (0x4000C000UL) +#define REG_WDT_BASEADDR (0x40024000UL) + +// +// SRAM address space +// +#define SRAM_BASEADDR (0x10000000UL) + +// +// Flash address space +// +#define FLASH_BASEADDR (0x00000000UL) + +#endif // AM_REG_BASE_ADDRESSES_H + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_iomstr_cmd.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_iomstr_cmd.h new file mode 100644 index 0000000..500b47b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_iomstr_cmd.h @@ -0,0 +1,77 @@ +//***************************************************************************** +// +// am_reg_iomstr_cmd.h +//! @file +//! +//! @brief Register macros for the IOMSTR module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_REG_IOMSTR_CMD_H +#define AM_REG_IOMSTR_CMD_H + +#if AM_PART_APOLLO2 +//***************************************************************************** +// +// IOMSTR_CMD - Command Register +// +//***************************************************************************** +#define AM_REG_IOMSTR_CMD_CMD_POS_LENGTH 0x00000000 +#define AM_REG_IOMSTR_CMD_CMD_POS_OFFSET 0x00000008 +#define AM_REG_IOMSTR_CMD_CMD_POS_ADDRESS 0x00000010 +#define AM_REG_IOMSTR_CMD_CMD_POS_CHNL 0x00000010 +#define AM_REG_IOMSTR_CMD_CMD_POS_UPLNGTH 0x00000017 +#define AM_REG_IOMSTR_CMD_CMD_POS_10BIT 0x0000001A +#define AM_REG_IOMSTR_CMD_CMD_POS_LSB 0x0000001B +#define AM_REG_IOMSTR_CMD_CMD_POS_CONT 0x0000001C +#define AM_REG_IOMSTR_CMD_CMD_POS_OPER 0x0000001D +#define AM_REG_IOMSTR_CMD_CMD_MSK_LENGTH 0x000000FF +#define AM_REG_IOMSTR_CMD_CMD_MSK_OFFSET 0x0000FF00 +#define AM_REG_IOMSTR_CMD_CMD_MSK_ADDRESS 0x00FF0000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_CHNL 0x00070000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_UPLNGTH 0x07800000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_10BIT 0x04000000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_LSB 0x08000000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_CONT 0x10000000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_OPER 0xE0000000 +#endif // AM_PART_APOLLO2 + +#endif // AM_REG_IOMSTR_CMD_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_jedec.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_jedec.h new file mode 100644 index 0000000..d7f6518 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_jedec.h @@ -0,0 +1,370 @@ +//***************************************************************************** +// +// am_reg_jedec.h +//! @file +//! +//! @brief Register macros for the ARM JEDEC module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_REG_JEDEC_H +#define AM_REG_JEDEC_H + +//***************************************************************************** +// +// JEDEC +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_JEDEC_NUM_MODULES 1 +#define AM_REG_JEDECn(n) \ + (REG_JEDEC_BASEADDR + 0x00000000 * n) + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language = extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + \brief Structure type to access the Apollo CM4 JEDEC registers. + */ +typedef struct +{ + uint32_t RESERVED0[52U]; /* 0xF00 - 0xFCF */ + + union + { + __IM uint32_t PID4; /*!< 0xF0000FD0 (R/ ) PID4 Register */ + + struct + { + __IM uint32_t JEPCONT : 4; /* [3..0] Contains the JEP Continuation bits. */ + } PID4_b; + }; + + union + { + __IM uint32_t PID5; /*!< 0xF0000FD4 (R/ ) PID5 Register */ + + struct + { + __IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */ + } PID5_b; + }; + + union + { + __IM uint32_t PID6; /*!< 0xF0000FD8 (R/ ) PID6 Register */ + + struct + { + __IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */ + } PID6_b; + }; + + union + { + __IM uint32_t PID7; /*!< 0xF0000FDC (R/ ) PID7 Register */ + + struct + { + __IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */ + } PID7_b; + }; + + union + { + __IM uint32_t PID0; /*!< 0xF0000FE0 (R/ ) PID0 Register */ + + struct + { + __IM uint32_t PNL8 : 8; /* [7..0] Contains the low 8 bits of the Ambiq Micro device part number. */ + } PID0_b; + }; + + union + { + __IM uint32_t PID1; /*!< 0xF0000FE4 (R/ ) PID1 Register */ + + struct + { + __IM uint32_t PNH4 : 4; /* [3..0] Contains the high 4 bits of the Ambiq Micro device part number. */ + __IM uint32_t JEPIDL : 4; /* [7..4] Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID is therefore 0x9B. */ + } PID1_b; + }; + + union + { + __IM uint32_t PID2; /*!< 0xF0000FE8 (R/ ) PID2 Register */ + + struct + { + __IM uint32_t JEPIDH : 4; /* [3..0] Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this field is hard-coded to 1. The full JEPID is therefore 0x9B. */ + __IM uint32_t CHIPREVH4 : 4; /* [7..4] Contains the high 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip. */ + } PID2_b; + }; + + union + { + __IM uint32_t PID3; /*!< 0xF0000FEC (R/ ) PID3 Register */ + + struct + { + __IM uint32_t ZERO : 4; /* [3..0] This field is hard-coded to 0x0. */ + __IM uint32_t CHIPREVL4 : 4; /* [7..0] Contains the low 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip. */ + } PID3_b; + }; + + union + { + __IM uint32_t CID0; /*!< 0xF0000FE0 (R/ ) CID0 Register */ + + struct + { + __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID0. */ + } CID0_b; + }; + + union + { + __IM uint32_t CID1; /*!< 0xF0000FE4 (R/ ) CID1 Register */ + + struct + { + __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID1. */ + } CID1_b; + }; + + union + { + __IM uint32_t CID2; /*!< 0xF0000FE8 (R/ ) CID2 Register */ + + struct + { + __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID2. */ + } CID2_b; + }; + + union + { + __IM uint32_t CID3; /*!< 0xF0000FEC (R/ ) CID3 Register */ + + struct + { + __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID3. */ + } CID3_b; + }; +} JEDEC_Type; + + +//***************************************************************************** +// +// JEDEC_PID4 - JEP Continuation Register +// +//***************************************************************************** +// Contains the JEP Continuation bits. +#define JEDEC_PID4_JEPCONT_Pos 0U +#define JEDEC_PID4_JEPCONT_Msk (0x0000000FUL) + +//***************************************************************************** +// +// JEDEC_PID5 - JEP reserved Register +// +//***************************************************************************** +// Contains the value of 0x00000000. +#define JEDEC_PID5_VALUE_Pos 0U +#define JEDEC_PID5_VALUE_Msk (0xFFFFFFFFUL) + +//***************************************************************************** +// +// JEDEC_PID6 - JEP reserved Register +// +//***************************************************************************** +// Contains the value of 0x00000000. +#define JEDEC_PID6_VALUE_Pos 0U +#define JEDEC_PID6_VALUE_Msk (0xFFFFFFFFUL) + +//***************************************************************************** +// +// JEDEC_PID7 - JEP reserved Register +// +//***************************************************************************** +// Contains the value of 0x00000000. +#define JEDEC_PID7_VALUE_Pos 0U +#define JEDEC_PID7_VALUE_Msk (0xFFFFFFFFUL) + +//***************************************************************************** +// +// JEDEC_PID0 - Ambiq Partnum low byte +// +//***************************************************************************** +// Contains the low 8 bits of the Ambiq Micro device part number. +#define JEDEC_PID0_PNL8_Pos 0U +#define JEDEC_PID0_PNL8_Msk (0x000000FFUL) + +//***************************************************************************** +// +// JEDEC_PID1 - Ambiq part number high-nibble, JEPID low-nibble. +// +//***************************************************************************** +// Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID +// is therefore 0x9B. +#define JEDEC_PID1_JEPIDL_Pos 4U +#define JEDEC_PID1_JEPIDL_Msk (0x000000F0UL) + +// Contains the high 4 bits of the Ambiq Micro device part number. +#define JEDEC_PID1_PNH4_Pos 0U +#define JEDEC_PID1_PNH4_Msk (0x0000000FUL) + +//***************************************************************************** +// +// JEDEC_PID2 - Ambiq chip revision low-nibble, JEPID high-nibble +// +//***************************************************************************** +// Contains the high 4 bits of the Ambiq Micro CHIPREV (see also +// MCUCTRL.CHIPREV). Note that this field will change with each revision of the +// chip. +#define JEDEC_PID2_CHIPREVH4_Pos 4U +#define JEDEC_PID2_CHIPREVH4_Msk (0x000000F0UL) + +// Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this +// field is hard-coded to 1. The full JEPID is therefore 0x9B. +#define JEDEC_PID2_JEPIDH_Pos 0U +#define JEDEC_PID2_JEPIDH_Msk (0x0000000FUL) + +//***************************************************************************** +// +// JEDEC_PID3 - Ambiq chip revision high-nibble. +// +//***************************************************************************** +// Contains the low 4 bits of the Ambiq Micro CHIPREV (see also +// MCUCTRL.CHIPREV). Note that this field will change with each revision of the +// chip. +#define JEDEC_PID3_CHIPREVL4_Pos 4U +#define JEDEC_PID3_CHIPREVL4_Msk (0x000000F0UL) + +// This field is hard-coded to 0x0. +#define JEDEC_PID3_ZERO_Pos 0U +#define JEDEC_PID3_ZERO_Msk (0x0000000FUL) + +//***************************************************************************** +// +// JEDEC_CID0 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID0. +#define JEDEC_CID0_CID_Pos 0U +#define JEDEC_CID0_CID_Msk (0x000000FFUL) + +//***************************************************************************** +// +// JEDEC_CID1 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID1. +#define JEDEC_CID1_CID_Pos 0U +#define JEDEC_CID1_CID_Msk (0x000000FFUL) + +//***************************************************************************** +// +// JEDEC_CID2 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID2. +#define JEDEC_CID2_CID_Pos 0U +#define JEDEC_CID2_CID_Msk (0x000000FFUL) + +//***************************************************************************** +// +// JEDEC_CID3 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID3. +#define JEDEC_CID3_CID_Pos 0U +#define JEDEC_CID3_CID_Msk (0x000000FFUL) + + + + +#define JEDEC_BASE (0xF0000F00UL) /*!< JEDEC Base Address */ + +#define JEDEC ((JEDEC_Type *) JEDEC_BASE ) /*!< JEDEC configuration struct */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + + +#endif // AM_REG_JEDEC_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_m4.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_m4.h new file mode 100644 index 0000000..307fd79 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_m4.h @@ -0,0 +1,93 @@ +//***************************************************************************** +// +// am_reg_m4.h +//! @file +//! +//! @brief A collection of a few CMSIS-style macros that are not automatically +//! generated in their respective core files. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_REG_CM4_H +#define AM_REG_CM4_H + +//***************************************************************************** +// +// am_reg_itm.h +// CMSIS-style defines. +// +//***************************************************************************** +#define ITM_LAR_KEYVAL 0xC5ACCE55 + +//***************************************************************************** +// +// am_reg_sysctrl.h +// CMSIS-style defines. +// +//***************************************************************************** +#define SCB_CPACR_CP11_Pos 22 +#define SCB_CPACR_CP11_Msk 0x00C00000 +#define SCB_CPACR_CP10_Pos 20 +#define SCB_CPACR_CP10_Msk 0x00300000 + +//***************************************************************************** +// +// am_reg_tpiu.h +// CMSIS-style defines. +// +//***************************************************************************** +#define TPI_CSPSR_CWIDTH_1BIT 1 +#define TPI_SPPR_TXMODE_UART 2 +#define TPI_ITCTRL_Mode_NORMAL 0 + +#ifndef TPI_ACPR_SWOSCALER_Pos +// +// In the CMSIS 5.6.0 version of core_cm4.h, the SWOSCALER field was no longer +// defined, while the PRESCALER field was left intact even though previous CMSIS +// versions PRESCALER as deprecated. On the off chance that future versions +// make a correction and remove PRESCALER, define SWOSCALER here (per 5.3.0). +// +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ +#endif + +#endif // AM_REG_CM4_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros.h new file mode 100644 index 0000000..89b6942 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros.h @@ -0,0 +1,111 @@ +//***************************************************************************** +// +// am_reg_macros.h +//! @file +//! +//! @brief Helper macros for using hardware registers. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_REG_MACROS_H +#define AM_REG_MACROS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// For direct 32-bit access to a register or memory location, use AM_REGVAL: +// AM_REGVAL(0x1234567) |= 0xDEADBEEF; +// +//***************************************************************************** +#define AM_REGVAL(x) (*((volatile uint32_t *)(x))) +#define AM_REGVAL_FLOAT(x) (*((volatile float *)(x))) + +//***************************************************************************** +// +// AM_REGADDR() +// One thing CMSIS does not do well natively is to provide for static register +// address computation. The address-of operator (e.g. &periph->reg) is helpful, +// but does run into problems, such as when attempting to cast the resulting +// pointer to a uint32_t. The standard C macro, offsetof() can help. +// +// Use AM_REGADDR() for single-module peripherals. +// Use AM_REGADDRn() for multi-module peripherals (e.g. IOM, UART). +// +//***************************************************************************** +#define AM_REGADDR(periph, reg) ( periph##_BASE + offsetof(periph##_Type, reg) ) + +#define AM_REGADDRn(periph, n, reg) ( periph##0_BASE + \ + offsetof(periph##0_Type, reg) + \ + (n * (periph##1_BASE - periph##0_BASE)) ) + +//***************************************************************************** +// +// Critical section assembly macros +// +// These macros implement critical section protection using inline assembly +// for various compilers. They are intended to be used in other register +// macros or directly in sections of code. +// +// Important usage note: These macros create a local scope and therefore MUST +// be used in pairs. +// +//***************************************************************************** +#define AM_CRITICAL_BEGIN \ + if ( 1 ) \ + { \ + volatile uint32_t ui32Primask_04172010; \ + ui32Primask_04172010 = am_hal_interrupt_master_disable(); + +#define AM_CRITICAL_END \ + am_hal_interrupt_master_set(ui32Primask_04172010); \ + } + +#ifdef __cplusplus +} +#endif + +#endif // AM_REG_MACROS_H + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros_asm.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros_asm.h new file mode 100644 index 0000000..b711935 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros_asm.h @@ -0,0 +1,64 @@ +//***************************************************************************** +// +// am_reg_macros_asm.h +//! @file +//! +//! @brief Inline assembly macros. Initially for critical section handling in +//! protecting hardware registers. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_REG_MACROS_ASM_H +#define AM_REG_MACROS_ASM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // AM_REG_MACROS_ASM_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices.h b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices.h new file mode 100644 index 0000000..f8416f4 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices.h @@ -0,0 +1,82 @@ +//***************************************************************************** +// +//! @file am_devices.h +//! +//! @brief Includes for all devices. +//! +//! @addtogroup devices External Device Control Library +//! @ingroup devices +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_DEVICES_H +#define AM_DEVICES_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// All DEVICES includes +// +//***************************************************************************** +#include "am_devices_button.h" +#include "am_devices_da14581.h" +#include "am_devices_em9304.h" +#include "am_devices_led.h" +#include "am_devices_spiflash.h" + +#ifdef __cplusplus +} +#endif + +#endif // AM_DEVICES_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.c b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.c new file mode 100644 index 0000000..728beee --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.c @@ -0,0 +1,226 @@ +//***************************************************************************** +// +//! @file am_devices_button.c +//! +//! @brief Functions for controlling an array of LEDs +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" +#include "am_devices_button.h" + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of buttons. +//! +//! @param psButton is a pointer to a button structure. +//! +//! This function configures a GPIO to read a button in a low-power way. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_button_init(am_devices_button_t *psButton) +{ + // + // Disable the pin to save power. + // +#if AM_APOLLO3_GPIO + am_hal_gpio_pinconfig(psButton->ui32GPIONumber, g_AM_HAL_GPIO_DISABLE); +#else // AM_APOLLO3_GPIO + am_hal_gpio_pin_config(psButton->ui32GPIONumber, AM_HAL_PIN_DISABLE); +#endif // AM_APOLLO3_GPIO + + + // + // Initialize the state variables. + // + psButton->ui32Count = 0; + psButton->bPressed = false; + psButton->bChanged = false; +} + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of buttons. +//! +//! @param psButtons is an array of button structures. +//! @param ui32NumButtons is the total number of buttons in the array. +//! +//! This function configures the GPIOs for an array of buttons. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_button_array_init(am_devices_button_t *psButtons, + uint32_t ui32NumButtons) +{ + uint32_t i; + + // + // Loop through the list of buttons, configuring each one individually. + // + for ( i = 0; i < ui32NumButtons; i++ ) + { + am_devices_button_init(psButtons + i); + } +} + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of buttons. +//! +//! @param psButtons is an array of button structures. +//! @param ui32NumButtons is the total number of buttons in the array. +//! +//! This function configures the GPIOs for an array of buttons. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_button_tick(am_devices_button_t *psButton) +{ + uint32_t ui32PinState; + bool bRawButtonPressed; + + // + // Enable the button pin. + // +#if AM_APOLLO3_GPIO + am_hal_gpio_pinconfig(psButton->ui32GPIONumber, g_AM_HAL_GPIO_INPUT); +#else // AM_APOLLO3_GPIO + am_hal_gpio_pin_config(psButton->ui32GPIONumber, AM_HAL_PIN_INPUT); +#endif // AM_APOLLO3_GPIO + + // + // Read the pin state. If the pin is in its normal (unpressed) state, set + // its "state" counter to zero. + // +#if AM_APOLLO3_GPIO + am_hal_gpio_state_read(psButton->ui32GPIONumber, AM_HAL_GPIO_INPUT_READ, &ui32PinState); +#else // AM_APOLLO3_GPIO + ui32PinState = am_hal_gpio_input_bit_read(psButton->ui32GPIONumber); +#endif // AM_APOLLO3_GPIO + + // + // Check to see if the button is "pressed" according to our GPIO reading. + // + bRawButtonPressed = (ui32PinState != psButton->ui32Polarity); + + // + // Is this button state different from the last saved state? + // + if ( bRawButtonPressed != psButton->bPressed ) + { + // + // If so, increase the debounce count. + // + psButton->ui32Count++; + } + else + { + // + // Otherwise, set the count back to zero. + // + psButton->ui32Count = 0; + } + + // + // If we hit the button debounce delay, record a button press to the + // structure, and reset the count. + // + if ( psButton->ui32Count >= AM_DEVICES_BUTTON_DEBOUNCE_DELAY ) + { + psButton->bPressed = bRawButtonPressed; + psButton->bChanged = true; + psButton->ui32Count = 0; + } + else + { + // + // If we didn't just record a press/release event, update the structure + // to say that the current state isn't new. + // + psButton->bChanged = false; + } + + // + // Disable the button pin to save power. + // +#if AM_APOLLO3_GPIO + am_hal_gpio_pinconfig(psButton->ui32GPIONumber, g_AM_HAL_GPIO_DISABLE); +#else // AM_APOLLO3_GPIO + am_hal_gpio_pin_config(psButton->ui32GPIONumber, AM_HAL_PIN_DISABLE); +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of buttons. +//! +//! @param psButtons is an array of button structures. +//! @param ui32NumButtons is the total number of buttons in the array. +//! +//! This function configures the GPIOs for an array of buttons. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_button_array_tick(am_devices_button_t *psButtons, + uint32_t ui32NumButtons) +{ + uint32_t i; + + // + // Run the "tick" function for each button in the list. + // + for ( i = 0; i < ui32NumButtons; i++ ) + { + am_devices_button_tick(psButtons + i); + } +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.h b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.h new file mode 100644 index 0000000..a51dc1b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.h @@ -0,0 +1,129 @@ +//***************************************************************************** +// +//! @file am_devices_button.h +//! +//! @brief Functions for controlling an array of buttons. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_DEVICES_BUTTON_H +#define AM_DEVICES_BUTTON_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Number of "ticks" to delay before registering a button press or release. +// +//***************************************************************************** +#define AM_DEVICES_BUTTON_DEBOUNCE_DELAY 0x4 + +//***************************************************************************** +// +// Button polarity macros +// +//***************************************************************************** +#define AM_DEVICES_BUTTON_NORMAL_HIGH 0x1 +#define AM_DEVICES_BUTTON_NORMAL_LOW 0x0 + +//***************************************************************************** +// +// Structure for keeping track of buttons. +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32GPIONumber; + uint32_t ui32Polarity; + uint32_t ui32Count; + bool bPressed; + bool bChanged; +} +am_devices_button_t; + +//***************************************************************************** +// +// Macro for declaring a button structure. +// +//***************************************************************************** +#define AM_DEVICES_BUTTON(ui32GPIONumber, ui32Polarity) \ + {ui32GPIONumber, ui32Polarity, 0, 0, 0} + +//***************************************************************************** +// +// Macros for checking button state. +// +//***************************************************************************** +#define am_devices_button_is_up(button) \ + ((button).bPressed == false) + +#define am_devices_button_is_down(button) \ + ((button).bPressed == true) + +#define am_devices_button_pressed(button) \ + (((button).bPressed == true) && ((button).bChanged == true)) + +#define am_devices_button_released(button) \ + (((button).bPressed == false) && ((button).bChanged == true)) + + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_devices_button_init(am_devices_button_t *psButton); + +extern void am_devices_button_array_init(am_devices_button_t *psButtons, + uint32_t ui32NumButtons); +extern void am_devices_button_tick(am_devices_button_t *psButton); + +extern void am_devices_button_array_tick(am_devices_button_t *psButtons, + uint32_t ui32NumButtons); +#ifdef __cplusplus +} +#endif + +#endif // AM_DEVICES_BUTTON_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.c b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.c new file mode 100644 index 0000000..98226f3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.c @@ -0,0 +1,556 @@ +//***************************************************************************** +// +//! @file am_devices_led.c +//! +//! @brief Functions for controlling an array of LEDs +//! +//! @addtogroup devices External Device Control Library +//! @addtogroup LED SPI Device Control for programmable LEDs. +//! @ingroup devices +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" +#include "am_devices_led.h" + +// +// Define a somewhat arbitrary maximum number of LEDs. No board is actually +// expected to have this many LEDs, the value is used for parameter validation. +// +#define MAX_LEDS 31 + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of LEDs +//! +//! @param psLED is a pointer to an LED structure. +//! +//! This function configures a GPIO to drive an LED in a low-power way. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_init(am_devices_led_t *psLED) +{ + if ( (psLED == NULL) || + (psLED->ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS) ) + { + return; + } + +#if AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLED->ui32Polarity ) + { + // + // Configure the pin as a push-pull GPIO output. + // + am_hal_gpio_pinconfig(psLED->ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Disable the output driver, and set the output value to the LEDs "ON" + // state. Note that for Apollo3 GPIOs in push-pull mode, the output + // enable, normally a tri-state control, instead functions as an enable + // for Fast GPIO. Its state does not matter on previous chips, so for + // normal GPIO usage on Apollo3, it must be disabled. + // + am_hal_gpio_state_write(psLED->ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(psLED->ui32GPIONumber, + psLED->ui32Polarity & AM_DEVICES_LED_POL_POLARITY_M ? + AM_HAL_GPIO_OUTPUT_SET : AM_HAL_GPIO_OUTPUT_CLEAR); + } + else + { + // + // Configure the pin as a tri-state GPIO. + // + am_hal_gpio_pinconfig(psLED->ui32GPIONumber, g_AM_HAL_GPIO_TRISTATE); + + // + // Disable the output driver, and set the output value to the LEDs "ON" + // state. + // + am_hal_gpio_state_write(psLED->ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(psLED->ui32GPIONumber, + psLED->ui32Polarity & AM_DEVICES_LED_POL_POLARITY_M ? + AM_HAL_GPIO_OUTPUT_SET : AM_HAL_GPIO_OUTPUT_CLEAR); + } +#else // AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLED->ui32Polarity ) + { + // + // Configure the pin as a push-pull GPIO output. + // + am_hal_gpio_pin_config(psLED->ui32GPIONumber, AM_HAL_GPIO_OUTPUT); + + // + // Disable the output driver, and set the output value to the LEDs "ON" + // state. + // + am_hal_gpio_out_enable_bit_clear(psLED->ui32GPIONumber); + am_hal_gpio_out_bit_replace(psLED->ui32GPIONumber, + psLED->ui32Polarity & + AM_DEVICES_LED_POL_POLARITY_M); + } + else + { + // + // Configure the pin as a tri-state GPIO. + // + am_hal_gpio_pin_config(psLED->ui32GPIONumber, AM_HAL_GPIO_3STATE); + + // + // Disable the output driver, and set the output value to the LEDs "ON" + // state. + // + am_hal_gpio_out_enable_bit_clear(psLED->ui32GPIONumber); + am_hal_gpio_out_bit_replace(psLED->ui32GPIONumber, + psLED->ui32Polarity & + AM_DEVICES_LED_POL_POLARITY_M ); + } +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Disables an array of LEDs +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32NumLEDs is the total number of LEDs in the array. +//! +//! This function disables the GPIOs for an array of LEDs. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_array_disable(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs) +{ + if ( (psLEDs == NULL) || + (ui32NumLEDs > MAX_LEDS) ) + { + return; + } + + // + // Loop through the list of LEDs, configuring each one individually. + // + for ( uint32_t i = 0; i < ui32NumLEDs; i++ ) + { + if ( psLEDs[i].ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS ) + { + continue; + } + +#if AM_APOLLO3_GPIO + am_hal_gpio_pinconfig((psLEDs + i)->ui32GPIONumber, g_AM_HAL_GPIO_DISABLE); +#else // AM_APOLLO3_GPIO + am_hal_gpio_pin_config((psLEDs + i)->ui32GPIONumber, AM_HAL_GPIO_DISABLE); +#endif // AM_APOLLO3_GPIO + } +} + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of LEDs +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32NumLEDs is the total number of LEDs in the array. +//! +//! This function configures the GPIOs for an array of LEDs. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_array_init(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs) +{ + uint32_t i; + + if ( (psLEDs == NULL) || + (ui32NumLEDs > MAX_LEDS) ) + { + return; + } + + // + // Loop through the list of LEDs, configuring each one individually. + // + for ( i = 0; i < ui32NumLEDs; i++ ) + { + am_devices_led_init(psLEDs + i); + } +} + +//***************************************************************************** +// +//! @brief Turns on the requested LED. +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32LEDNum is the LED number for the light to turn on. +//! +//! This function turns on a single LED. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_on(am_devices_led_t *psLEDs, uint32_t ui32LEDNum) +{ + if ( (psLEDs == NULL) || + (ui32LEDNum >= MAX_LEDS) || + (psLEDs[ui32LEDNum].ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS) ) + { + return; + } + +#if AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + // + // Set the output to the correct state for the LED. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + psLEDs[ui32LEDNum].ui32Polarity & AM_DEVICES_LED_POL_POLARITY_M ? + AM_HAL_GPIO_OUTPUT_SET : AM_HAL_GPIO_OUTPUT_CLEAR); + } + else + { + // + // Turn on the output driver for the LED. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE); + } +#else // AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + // + // Set the output to the correct state for the LED. + // + am_hal_gpio_out_bit_replace(psLEDs[ui32LEDNum].ui32GPIONumber, + psLEDs[ui32LEDNum].ui32Polarity & + AM_DEVICES_LED_POL_POLARITY_M ); + } + else + { + // + // Turn on the output driver for the LED. + // + am_hal_gpio_out_enable_bit_set(psLEDs[ui32LEDNum].ui32GPIONumber); + } +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Turns off the requested LED. +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32LEDNum is the LED number for the light to turn off. +//! +//! This function turns off a single LED. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_off(am_devices_led_t *psLEDs, uint32_t ui32LEDNum) +{ + if ( (psLEDs == NULL) || + (ui32LEDNum >= MAX_LEDS) || + (psLEDs[ui32LEDNum].ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS) ) + { + return; + } + +#if AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + // + // Set the output to the correct state for the LED. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + psLEDs[ui32LEDNum].ui32Polarity & AM_DEVICES_LED_POL_POLARITY_M ? + AM_HAL_GPIO_OUTPUT_CLEAR : AM_HAL_GPIO_OUTPUT_SET); + } + else + { + // + // Turn off the output driver for the LED. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + } +#else // AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + // + // Set the output to the correct state for the LED. + // + am_hal_gpio_out_bit_replace(psLEDs[ui32LEDNum].ui32GPIONumber, + !(psLEDs[ui32LEDNum].ui32Polarity & + AM_DEVICES_LED_POL_POLARITY_M) ); + } + else + { + // + // Turn off the output driver for the LED. + // + am_hal_gpio_out_enable_bit_clear(psLEDs[ui32LEDNum].ui32GPIONumber); + } +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Toggles the requested LED. +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32LEDNum is the LED number for the light to toggle. +//! +//! This function toggles a single LED. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_toggle(am_devices_led_t *psLEDs, uint32_t ui32LEDNum) +{ + if ( (psLEDs == NULL) || + (ui32LEDNum >= MAX_LEDS) || + (psLEDs[ui32LEDNum].ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS) ) + { + return; + } + +#if AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_OUTPUT_TOGGLE); + } + else + { + uint32_t ui32Ret, ui32Value; + + // + // Check to see if the LED pin is enabled. + // + ui32Ret = am_hal_gpio_state_read(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_ENABLE_READ, &ui32Value); + + if ( ui32Ret == AM_HAL_STATUS_SUCCESS ) + { + if ( ui32Value ) + { + // + // If it was enabled, turn if off. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + } + else + { + // + // If it was not enabled, turn it on. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE); + } + } + } +#else // AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + am_hal_gpio_out_bit_toggle(psLEDs[ui32LEDNum].ui32GPIONumber); + } + else + { + // + // Check to see if the LED pin is enabled. + // + if ( am_hal_gpio_out_enable_bit_get(psLEDs[ui32LEDNum].ui32GPIONumber) ) + { + // + // If it was enabled, turn if off. + // + am_hal_gpio_out_enable_bit_clear(psLEDs[ui32LEDNum].ui32GPIONumber); + } + else + { + // + // If it was not enabled, turn if on. + // + am_hal_gpio_out_enable_bit_set(psLEDs[ui32LEDNum].ui32GPIONumber); + } + } +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Gets the state of the requested LED. +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32LEDNum is the LED to check. +//! +//! This function checks the state of a single LED. +//! +//! @return true if the LED is on. +// +//***************************************************************************** +bool +am_devices_led_get(am_devices_led_t *psLEDs, uint32_t ui32LEDNum) +{ + if ( (psLEDs == NULL) || + (ui32LEDNum >= MAX_LEDS) || + (psLEDs[ui32LEDNum].ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS) ) + { + return false; // No error return, so return as off + } + +#if AM_APOLLO3_GPIO + uint32_t ui32Ret, ui32Value; + am_hal_gpio_read_type_e eReadType; + + eReadType = AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ? + AM_HAL_GPIO_OUTPUT_READ : AM_HAL_GPIO_ENABLE_READ; + + ui32Ret = am_hal_gpio_state_read(psLEDs[ui32LEDNum].ui32GPIONumber, + eReadType, &ui32Value); + + if ( ui32Ret == AM_HAL_STATUS_SUCCESS ) + { + return (bool)ui32Value; + } + else + { + return false; + } +#else // AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + // + // Mask to the GPIO bit position for this GPIO number. + // + uint64_t ui64Mask = ((uint64_t)0x01l) << psLEDs[ui32LEDNum].ui32GPIONumber; + + // + // Extract the state of this bit and return it. + // + return !!(am_hal_gpio_out_read() & ui64Mask); + } + else + { + return am_hal_gpio_out_enable_bit_get(psLEDs[ui32LEDNum].ui32GPIONumber); + } +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Display a binary value using LEDs. +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32NumLEDs is the number of LEDs in the array. +//! @param ui32Value is the value to display on the LEDs. +//! +//! This function displays a value in binary across an array of LEDs. +//! +//! @return true if the LED is on. +// +//***************************************************************************** +void +am_devices_led_array_out(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs, + uint32_t ui32Value) +{ + uint32_t i; + + for ( i = 0; i < ui32NumLEDs; i++ ) + { + if ( ui32Value & (1 << i) ) + { + am_devices_led_on(psLEDs, i); + } + else + { + am_devices_led_off(psLEDs, i); + } + } +} +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.h b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.h new file mode 100644 index 0000000..1a518f0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.h @@ -0,0 +1,115 @@ +//***************************************************************************** +// +//! @file am_devices_led.h +//! +//! @brief Functions for controlling an array of LEDs +//! +//! @addtogroup devices External Device Control Library +//! @addtogroup LED SPI Device Control for programmable LEDs. +//! @ingroup devices +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_DEVICES_LED_H +#define AM_DEVICES_LED_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// LED polarity macros +// +//***************************************************************************** +#define AM_DEVICES_LED_POL_POLARITY_M 0x1 +#define AM_DEVICES_LED_ON_HIGH 0x1 +#define AM_DEVICES_LED_ON_LOW 0x0 + +//***************************************************************************** +// +// LED direct drive indicator macro +// Or this in with the polarity value to use the GPIO DATA register instead of +// the GPIO DATA ENABLE register to directly drive an LED buffer. +// +//***************************************************************************** +#define AM_DEVICES_LED_POL_DIRECT_DRIVE_M 0x2 + +//***************************************************************************** +// +// Structure for keeping track of LEDs +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32GPIONumber; + uint32_t ui32Polarity; +} +am_devices_led_t; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_devices_led_init(am_devices_led_t *psLED); +extern void am_devices_led_array_init(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs); +extern void am_devices_led_array_disable(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs); +extern void am_devices_led_on(am_devices_led_t *psLEDs, uint32_t ui32LEDNum); +extern void am_devices_led_off(am_devices_led_t *psLEDs, uint32_t ui32LEDNum); +extern void am_devices_led_toggle(am_devices_led_t *psLEDs, uint32_t ui32LEDNum); +extern bool am_devices_led_get(am_devices_led_t *psLEDs, uint32_t ui32LEDNum); +extern void am_devices_led_array_out(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs, + uint32_t ui32Value); +#ifdef __cplusplus +} +#endif + +#endif // AM_DEVICES_LED_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util.h new file mode 100644 index 0000000..35e8941 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util.h @@ -0,0 +1,77 @@ +//***************************************************************************** +// +//! @file am_util.h +//! +//! @brief Top Include for all of the utilities +//! +//! This file provides all the includes necessary to use the utilities. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_H +#define AM_UTIL_H + +//***************************************************************************** +// +// C99 +// +//***************************************************************************** +#include +#include + +//***************************************************************************** +// +// Utilities +// +//***************************************************************************** +#include "am_util_debug.h" +#include "am_util_delay.h" +#include "am_util_id.h" +#include "am_util_regdump.h" +#include "am_util_stdio.h" +#include "am_util_string.h" +#include "am_util_time.h" + +#if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P) +#include "am_util_ble.h" +#endif + +#endif // AM_UTIL_H diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.c new file mode 100644 index 0000000..691fda6 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.c @@ -0,0 +1,632 @@ +//***************************************************************************** +// +//! @file am_util_apollo3_ble.c +//! +//! @brief Useful BLE functions not covered by the HAL. +//! +//! This file contains functions for interacting with the Apollo3 BLE hardware +//! that are not already covered by the HAL. Most of these commands either +//! adjust RF settings or facilitate RF testing operations. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include +#include "am_util_delay.h" +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** + +//***************************************************************************** +// +// In DTM mode, set TX to constant trans mode for SRRC/FCC/CE +//set enable as 'true' to constant trans mode, 'false' back to normal +//***************************************************************************** +uint32_t +am_util_ble_set_constant_transmission(void *pHandle, bool enable) +{ + am_hal_ble_state_t *pBLE = pHandle; + + am_hal_ble_sleep_set(pBLE, false); + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + if ( enable ) + { + am_hal_ble_plf_reg_write(pBLE, 0x508000E0, 0x00008000); + } + else + { + am_hal_ble_plf_reg_write(pBLE, 0x508000E0, 0x00000000); + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Manually enable/disable transmitter +// set ui8TxCtrl as 1 to manually enable transmitter, 0 back to default +// +//***************************************************************************** +uint32_t +am_util_ble_transmitter_control(void *pHandle, uint8_t ui8TxCtrl) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t RegValueTRX; + + am_hal_ble_sleep_set(pBLE, false); + if (ui8TxCtrl) + { + RegValueTRX = 0x2000A; + } + else + { + RegValueTRX = 0x8; + } + + // + // Unlock the BLE registers. + // + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + am_hal_ble_plf_reg_write(pBLE, 0x52400000, RegValueTRX); + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//to fix the channel 1 bug in DTM mode +// +//***************************************************************************** + +uint32_t +am_util_ble_init_rf_channel(void *pHandle) +{ + if (!APOLLO3_GE_B0) + { + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + uint32_t ui32Module = pBLE->ui32Module; + am_hal_ble_sleep_set(pBLE, false); + + //issue the HCI command with to init for the channel 1 + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1d; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x01; + sWriteCommand.bytes[4] = 0x00; + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + // reserved packet_payload + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 5); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + while ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0 ); + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + am_util_delay_ms(10); + + // issue the HCI command with to stop test for the channel 1 + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1f; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x00; + // reserved packet_payload + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 4); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + while ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0 ); + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// BLE init for BQB test +//set enable as 'true' to init as BQB test mode, 'false' back to default +//***************************************************************************** +uint32_t +am_util_ble_BQB_test_init(void *pHandle, bool enable) +{ + am_hal_ble_state_t *pBLE = pHandle; + + am_hal_ble_sleep_set(pBLE, false); + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + + if ( enable ) + { + am_hal_ble_plf_reg_write(pBLE, 0x51800028, 0x0000209c); + } + else + { + am_hal_ble_plf_reg_write(pBLE, 0x51800028, 0x00003ff6); + } + + am_hal_ble_plf_reg_write(pBLE, 0x45800070, 0x100); + am_hal_ble_plf_reg_write(pBLE, 0x45800070, 0); + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Set the 32M crystal frequency +// based on the tested values at customer side. +// set trim value smaller in case of negative frequency offset +// ui32TrimValue: default is 0x400 +//***************************************************************************** +uint32_t +am_util_ble_crystal_trim_set(void *pHandle, uint32_t ui32TrimValue) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t RegValueMCGR; + + ui32TrimValue &= 0x7FF; + + am_hal_ble_plf_reg_read(pBLE, 0x43000004, &RegValueMCGR); + // + // Unlock the BLE registers. + // + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + am_hal_ble_plf_reg_write(pBLE, 0x43800004, ui32TrimValue); + am_hal_ble_plf_reg_write(pBLE, 0x43000004, RegValueMCGR); + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Manually enable/disable transmitter to output carrier signal +// set ui8TxChannel as 0 to 0x27 for each transmit channel, 0xFF back to normal modulate mode +// +//***************************************************************************** +uint32_t +am_util_ble_hci_reset(void *pHandle) +{ + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + am_hal_ble_sleep_set(pBLE, false); + uint32_t ui32Module = pBLE->ui32Module; + + // issue the HCI command with to reset hci + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x03; + sWriteCommand.bytes[2] = 0x0c; + sWriteCommand.bytes[3] = 0x00; + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 4); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + for (uint32_t i = 0; i < 1000; i++) + { + if ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ != 0 ) + { + break; + } + else if (i == (1000 - 1)) + { + return AM_HAL_BLE_NO_HCI_RESPONSE; + } + else + { + am_util_delay_ms(1); + } + } + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//to do directly output modulation signal. change channel ranges from 0 to 0x27, pattern from 0 to 7. +// +//***************************************************************************** +uint32_t +am_util_ble_trasmitter_test_ex(void *pHandle, uint8_t channel, uint8_t pattern) +{ + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + am_hal_ble_sleep_set(pBLE, false); + uint32_t ui32Module = pBLE->ui32Module; + + // issue the HCI command with to TX carrier wave + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1E; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x03; + sWriteCommand.bytes[4] = channel; + sWriteCommand.bytes[5] = 0x25; + sWriteCommand.bytes[6] = pattern; + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 7); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + for (uint32_t i = 0; i < 100; i++) + { + if (BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ != 0) + { + break; + } + else if (i == (100 - 1)) + { + return AM_HAL_BLE_NO_HCI_RESPONSE; + } + else + { + am_util_delay_ms(1); + } + } + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//to do directly receiver test. change channel ranges from 0 to 0x27, return received packets in 100ms. +// +//***************************************************************************** + +uint32_t +am_util_ble_receiver_test_ex(void *pHandle, uint8_t channel, uint32_t *recvpackets) +{ + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + uint32_t ui32Module = pBLE->ui32Module; + am_hal_ble_sleep_set(pBLE, false); + + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1d; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x01; + sWriteCommand.bytes[4] = channel; + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + // reserved packet_payload + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 5); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + while ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0 ); + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + am_util_delay_ms(100); + +// issue the HCI command with to stop test for the channel 1 + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1f; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x00; + // reserved packet_payload + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 4); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + while ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0 ); + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + *recvpackets = (sResponse.bytes[8] << 8) + sResponse.bytes[7]; + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//to directly output carrier wave. change channel ranges from 0 to 0x27. +// +//***************************************************************************** +uint32_t +am_util_ble_set_carrier_wave_ex(void *pHandle, uint8_t channel) +{ + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + // channel 0xFF to disable the constant transmission + if ( channel == 0xFF ) + { + am_util_ble_transmitter_control(pBLE, false); + return AM_HAL_STATUS_SUCCESS; + } + + am_hal_ble_sleep_set(pBLE, false); + uint32_t ui32Module = pBLE->ui32Module; + + // issue the HCI command with to TX carrier wave + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1E; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x03; + sWriteCommand.bytes[4] = channel; + sWriteCommand.bytes[5] = 0x25; + sWriteCommand.bytes[6] = 0x00; + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 7); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + for (uint32_t i = 0; i < 100; i++) + { + if (BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ != 0) + { + break; + } + else if (i == (100 - 1)) + { + return AM_HAL_BLE_NO_HCI_RESPONSE; + } + else + { + am_util_delay_ms(1); + } + } + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + am_util_ble_transmitter_control(pBLE, true); + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Manually enable/disable transmitter to output carrier wave signal +// set ui8TxChannel as 0 to 0x27 for each transmit channel, 0xFF back to normal modulate mode +// +//***************************************************************************** +uint32_t +am_util_ble_transmitter_control_ex(void *pHandle, uint8_t ui8TxChannel) +{ + return am_util_ble_set_carrier_wave_ex(pHandle, ui8TxChannel); +} + +//***************************************************************************** +// +//to directly output constant modulation signal. change channel from 0 to 0x27. +// +//***************************************************************************** +uint32_t +am_util_ble_set_constant_transmission_ex(void *pHandle, uint8_t channel) +{ + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + // channel 0xFF to disable the constant transmission + if ( channel == 0xFF ) + { + am_util_ble_set_constant_transmission(pBLE, false); + return AM_HAL_STATUS_SUCCESS; + } + + uint32_t ui32Module = pBLE->ui32Module; + am_util_ble_set_constant_transmission(pBLE, true); + + // issue the HCI command with to TX constant transmission + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1E; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x03; + sWriteCommand.bytes[4] = channel; + sWriteCommand.bytes[5] = 0x25; + sWriteCommand.bytes[6] = 0x00; + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 7); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + for (uint32_t i = 0; i < 100; i++) + { + if (BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ != 0) + { + break; + } + else if (i == (100 - 1)) + { + return AM_HAL_BLE_NO_HCI_RESPONSE; + } + else + { + am_util_delay_ms(1); + } + } + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// read current modex value from BLEIP +//***************************************************************************** +uint32_t +am_util_ble_read_modex_value(void *pHandle) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t temp = 0; + if (APOLLO3_GE_B0) + { + // for B0 Chip,the modex value address is changed to 0x20006874 + am_hal_ble_plf_reg_read(pBLE, 0x20006874, &temp); + } + else + { + am_hal_ble_plf_reg_read(pBLE, 0x20006070, &temp); + } + return temp; +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.h new file mode 100644 index 0000000..41b7bf3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.h @@ -0,0 +1,82 @@ +//***************************************************************************** +// +//! @file am_util_apollo3_ble.h +//! +//! @brief Useful BLE functions not covered by the HAL. +//! +//! This file contains functions for interacting with the Apollo3 BLE hardware +//! that are not already covered by the HAL. Most of these commands either +//! adjust RF settings or facilitate RF testing operations. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_UTIL_BLE_H +#define AM_UTIL_BLE_H + +//***************************************************************************** +// +// External function declarations. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +extern uint32_t am_util_ble_set_constant_transmission(void *pHandle, bool enable); +extern uint32_t am_util_ble_transmitter_control(void *pHandle, uint8_t ui8TxCtrl); +extern uint32_t am_util_ble_init_rf_channel(void *pHandle); +extern uint32_t am_util_ble_BQB_test_init(void *pHandle, bool enable); +extern uint32_t am_util_ble_crystal_trim_set(void *pHandle, uint32_t ui32TrimValue); +extern uint32_t am_util_ble_hci_reset(void *pHandle); +extern uint32_t am_util_ble_trasmitter_test_ex(void *pHandle, uint8_t channel, uint8_t pattern); +extern uint32_t am_util_ble_receiver_test_ex(void *pHandle, uint8_t channel, uint32_t *recvpackets); +extern uint32_t am_util_ble_set_carrier_wave_ex(void *pHandle, uint8_t channel); +extern uint32_t am_util_ble_transmitter_control_ex(void *pHandle, uint8_t ui8TxChannel); +extern uint32_t am_util_ble_set_constant_transmission_ex(void *pHandle, uint8_t channel); +extern uint32_t am_util_ble_read_modex_value(void *pHandle); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_BLE_H diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.c new file mode 100644 index 0000000..2975ff3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.c @@ -0,0 +1,52 @@ +//***************************************************************************** +// +//! @file am_util_debug.c +//! +//! @brief Useful functions for debugging. +//! +//! These functions and macros were created to assist with debugging. They are +//! intended to be as unintrusive as possible and designed to be removed from +//! the compilation of a project when they are no longer needed. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_util_debug.h" diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.h new file mode 100644 index 0000000..8ca2a3c --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.h @@ -0,0 +1,115 @@ +//***************************************************************************** +// +//! @file am_util_debug.h +//! +//! @brief Useful functions for debugging. +//! +//! These functions and macros were created to assist with debugging. They are +//! intended to be as unintrusive as possible and designed to be removed from +//! the compilation of a project when they are no longer needed. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_DEBUG_H +#define AM_UTIL_DEBUG_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Debug printf macros. +// +//***************************************************************************** +#ifdef AM_DEBUG_PRINTF + +#define am_util_debug_printf_init(x) \ + am_util_stdio_printf_init(x); + +#define am_util_debug_printf(...) \ + am_util_stdio_printf(__VA_ARGS__); + +#else + +#define am_util_debug_printf_init(...) +#define am_util_debug_printf(...) + +#endif // AM_DEBUG_PRINTF + +//***************************************************************************** +// +// Debug trace macros. +// +//***************************************************************************** +#ifdef AM_DEBUG_TRACE + +#define am_util_debug_trace_init(PinNumber) \ + do \ + { \ + am_hal_gpio_out_bit_clear(PinNumber); \ + am_hal_gpio_pin_config(PinNumber, AM_HAL_GPIO_OUTPUT); \ + } \ + while(0) + + +#define am_util_debug_trace_start(PinNumber) \ + am_hal_gpio_out_bit_set(PinNumber) + +#define am_util_debug_trace_end(PinNumber) \ + am_hal_gpio_out_bit_clear(PinNumber) + +#else + +#define am_util_debug_trace_init(PinNumber) +#define am_util_debug_trace_start(PinNumber) +#define am_util_debug_trace_end(PinNumber) + +#endif // AM_DEBUG_TRACE + + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_DEBUG_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.c new file mode 100644 index 0000000..7eba513 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.c @@ -0,0 +1,138 @@ +//***************************************************************************** +// +//! @file am_util_delay.c +//! +//! @brief A few useful delay functions. +//! +//! Functions for fixed delays. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include "am_mcu_apollo.h" +#include "am_util_delay.h" + +//***************************************************************************** +// +//! @brief Delays for a desired amount of loops. +//! +//! @param ui32CycleLoops - Desired number of cycle loops to delay for. +//! +//! This function will delay for a number of cycle loops. +//! +//! @note - the number of cycles each loops takes to execute is approximately 3. +//! Therefore the actual number of cycles executed will be ~3x ui32CycleLoops. +//! +//! For example, a ui32CycleLoops value of 100 will delay for 300 cycles. +//! +//! @returns None +// +//***************************************************************************** +void +am_util_delay_cycles(uint32_t ui32Iterations) +{ + // + // Call the BOOTROM cycle delay function + // + am_hal_flash_delay(ui32Iterations); +} + +//***************************************************************************** +// +//! @brief Delays for a desired amount of milliseconds. +//! +//! @param ui32MilliSeconds - number of milliseconds to delay for. +//! +//! This function will delay for a number of milliseconds. +//! +//! @returns None +// +//***************************************************************************** +void +am_util_delay_ms(uint32_t ui32MilliSeconds) +{ + uint32_t ui32Loops, ui32HFRC; +#if AM_APOLLO3_CLKGEN + am_hal_clkgen_status_t sClkgenStatus; + am_hal_clkgen_status_get(&sClkgenStatus); + ui32HFRC = sClkgenStatus.ui32SysclkFreq; +#else // AM_APOLLO3_CLKGEN + ui32HFRC = am_hal_clkgen_sysclk_get(); +#endif // AM_APOLLO3_CLKGEN + ui32Loops = ui32MilliSeconds * (ui32HFRC / 3000); + + // + // Call the BOOTROM cycle delay function + // + am_hal_flash_delay(ui32Loops); +} + +//***************************************************************************** +// +//! @brief Delays for a desired amount of microseconds. +//! +//! @param ui32MicroSeconds - number of microseconds to delay for. +//! +//! This function will delay for a number of microseconds. +//! +//! @returns None +// +//***************************************************************************** +void +am_util_delay_us(uint32_t ui32MicroSeconds) +{ + uint32_t ui32Loops, ui32HFRC; + +#if AM_APOLLO3_CLKGEN + am_hal_clkgen_status_t sClkgenStatus; + am_hal_clkgen_status_get(&sClkgenStatus); + ui32HFRC = sClkgenStatus.ui32SysclkFreq; +#else // AM_APOLLO3_CLKGEN + ui32HFRC = am_hal_clkgen_sysclk_get(); +#endif // AM_APOLLO3_CLKGEN + ui32Loops = ui32MicroSeconds * (ui32HFRC / 3000000); + + // + // Call the BOOTROM cycle delay function + // + am_hal_flash_delay(ui32Loops); +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.h new file mode 100644 index 0000000..034d378 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.h @@ -0,0 +1,69 @@ +//***************************************************************************** +// +//! @file am_util_delay.h +//! +//! @brief A few useful delay functions +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_DELAY_H +#define AM_UTIL_DELAY_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_util_delay_cycles(uint32_t ui32Iterations); +extern void am_util_delay_ms(uint32_t ui32MilliSeconds); +extern void am_util_delay_us(uint32_t ui32MicroSeconds); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_DELAY_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.c new file mode 100644 index 0000000..8ee0435 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.c @@ -0,0 +1,220 @@ +//***************************************************************************** +// +//! @file am_util_id.c +//! +//! @brief Identification of the Ambiq Micro device. +//! +//! This module contains functions for run time identification of Ambiq Micro +//! devices. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include "am_util_id.h" + + +//***************************************************************************** +// +// Globals. +// +//***************************************************************************** +// +// Strings for use with pui8VendorName. +// +static const uint8_t g_DeviceNameApollo[] = "Apollo"; +static const uint8_t g_DeviceNameApollo2[] = "Apollo2"; +static const uint8_t g_DeviceNameApollo3[] = "Apollo3 Blue"; +static const uint8_t g_DeviceNameApollo3p[] = "Apollo3 Blue Plus"; +static const uint8_t g_ui8VendorNameAmbq[] = "AMBQ"; +static const uint8_t g_ui8VendorNameUnknown[] = "????"; +static const uint8_t g_ui8DeviceNameUnknown[] = "Unknown device"; + +//***************************************************************************** +// Return the major version of the chip rev. +// Returns: 'A', 'B', 'C', ... +//***************************************************************************** +static uint32_t +revmaj_get(uint32_t ui32ChipRev) +{ + uint32_t ui32ret; + +#ifdef _FLD2VAL + ui32ret = _FLD2VAL(MCUCTRL_CHIPREV_REVMAJ, ui32ChipRev); +#else + ui32ret = (ui32ChipRev & 0xF0) >> 4; +#endif + + // + // Major revision is 1=A, 2=B, 3=C, ... + // Convert to the expected return value. + // + return ui32ret + 'A' - 1; + +} // revmaj_get() + +//***************************************************************************** +// Update the ID structure with the appropriate ChipRev letter. +// ui32minrevbase should be 0 for Apollo or Apollo2, 1 for Apollo3. +//***************************************************************************** +static void +chiprev_set(am_util_id_t *psIDDevice, uint32_t ui32minrevbase) +{ + uint32_t ui32maj, ui32min; + + ui32maj = ((psIDDevice->sMcuCtrlDevice.ui32ChipRev & 0xF0) >> 4); + psIDDevice->ui8ChipRevMaj = (uint8_t)('A' - 1 + ui32maj); + + // + // For Apollo and Apollo2: rev0=0, rev1=1, ... (0-based) + // For Apollo3: rev0=1, rev1=2, ... (1-based) + // + ui32min = ((psIDDevice->sMcuCtrlDevice.ui32ChipRev & 0x0F) >> 0); + psIDDevice->ui8ChipRevMin = (uint8_t)('0' + ui32min - ui32minrevbase); + +} // chiprev_set() + +//***************************************************************************** +// +//! @brief Device identification. +//! +//! @param psIDDevice - ptr to a device ID structure (am_util_id_t*) to be +//! filled in by the function. +//! +//! This function provides additional information about the currently running +//! Ambiq Micro MCU device. +//! +//! @returns The ui32Device value, which is a value corresponding to the +//! device type. +// +//***************************************************************************** +uint32_t +am_util_id_device(am_util_id_t *psIDDevice) +{ + uint32_t ui32PN, ui32ChipRev; + + // + // Go get all the device (hardware) info from the HAL + // +#if AM_APOLLO3_MCUCTRL + am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_DEVICEID, &psIDDevice->sMcuCtrlDevice); +#else // AM_APOLLO3_MCUCTRL + am_hal_mcuctrl_device_info_get(&psIDDevice->sMcuCtrlDevice); +#endif // AM_APOLLO3_MCUCTRL + + // + // Device identification + // + ui32PN = psIDDevice->sMcuCtrlDevice.ui32ChipPN & + AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_PN_M; + ui32ChipRev = psIDDevice->sMcuCtrlDevice.ui32ChipRev; + + if ( (psIDDevice->sMcuCtrlDevice.ui32JedecCID == 0xB105100D) && + (psIDDevice->sMcuCtrlDevice.ui32JedecJEPID == 0x0000009B) && + ((psIDDevice->sMcuCtrlDevice.ui32JedecPN & 0xF00) != 0xE00) ) + { + // + // It's Ambiq Micro, set up the VENDORID. + // + psIDDevice->pui8VendorName = g_ui8VendorNameAmbq; + } + else + { + // + // For now, set it as unknown vendor, but we may change it later. + // + psIDDevice->pui8VendorName = g_ui8VendorNameUnknown; + } + + if ( psIDDevice->sMcuCtrlDevice.ui32VendorID == + (('A' << 24) | ('M' << 16) | ('B' << 8) | ('Q' << 0)) ) + { + // + // VENDORID is AMBQ, so set the string pointer. + // + psIDDevice->pui8VendorName = g_ui8VendorNameAmbq; + } + + if ( ( ui32PN == AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO ) && + ((psIDDevice->sMcuCtrlDevice.ui32JedecPN & 0x0F0) == 0x0E0) ) + { + psIDDevice->ui32Device = AM_UTIL_ID_APOLLO; + psIDDevice->pui8DeviceName = g_DeviceNameApollo; + chiprev_set(psIDDevice, 0); + + // + // Force the vendor name for Apollo, which did not support VENDORID. + // + psIDDevice->pui8VendorName = g_ui8VendorNameAmbq; + } + else if ( ( ui32PN == AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO2 ) && + ((psIDDevice->sMcuCtrlDevice.ui32JedecPN & 0x0F0) == 0x0D0) ) + { + psIDDevice->ui32Device = AM_UTIL_ID_APOLLO2; + psIDDevice->pui8DeviceName = g_DeviceNameApollo2; + chiprev_set(psIDDevice, 0); + } + else if ( ( ui32PN == AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO3 ) && + ((psIDDevice->sMcuCtrlDevice.ui32JedecPN & 0x0F0) == 0x0C0) && + ( revmaj_get(ui32ChipRev) <= 'B' ) ) + { + psIDDevice->ui32Device = AM_UTIL_ID_APOLLO3; + psIDDevice->pui8DeviceName = g_DeviceNameApollo3; + chiprev_set(psIDDevice, 1); + } + else if ( ( ui32PN == AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO3P) && + ((psIDDevice->sMcuCtrlDevice.ui32JedecPN & 0x0F0) == 0x0C0) && + ( revmaj_get(ui32ChipRev) == 'C' ) ) + { + psIDDevice->ui32Device = AM_UTIL_ID_APOLLO3P; + psIDDevice->pui8DeviceName = g_DeviceNameApollo3p; + chiprev_set(psIDDevice, 1); + } + else + { + psIDDevice->ui32Device = AM_UTIL_ID_UNKNOWN; + psIDDevice->pui8DeviceName = g_ui8DeviceNameUnknown; + psIDDevice->ui8ChipRevMaj = (uint8_t)'?'; + psIDDevice->ui8ChipRevMin = (uint8_t)' '; + } + + return psIDDevice->ui32Device; +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.h new file mode 100644 index 0000000..bddf98f --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.h @@ -0,0 +1,133 @@ +//***************************************************************************** +// +//! @file am_util_id.h +//! +//! @brief Identification of the Ambiq Micro device. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_ID_H +#define AM_UTIL_ID_H + +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! ID structure +// +//***************************************************************************** +typedef struct +{ + // + //! Contains the HAL hardware information about the device. + // + am_hal_mcuctrl_device_t sMcuCtrlDevice; + + // + //! Device type (derived value, not a hardware value) + // + uint32_t ui32Device; + + // + //! Vendor name from the MCUCTRL VENDORID register and stringized here. + // + const uint8_t *pui8VendorName; + + // + //! Device name (derived value, not a hardware value) + // + const uint8_t *pui8DeviceName; + + // + // Major chip revision (e.g. char 'A' or 'B') + // + uint8_t ui8ChipRevMaj; + + // + // Minor chip revision (e.g. char '0', '1', ' ') + // + uint8_t ui8ChipRevMin; +} +am_util_id_t; + +//***************************************************************************** +// +// Macros for MCUCTRL CHIP_INFO field. +// Note - these macros are derived from the Apollo2 auto-generated register +// definitions. +// +//***************************************************************************** +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO3P 0x07000000 +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO3 0x06000000 +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLOBL 0x05000000 +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO2 0x03000000 +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO 0x01000000 +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_PN_M 0xFF000000 + +//***************************************************************************** +// +// Macros for silicon identification +// +//***************************************************************************** +#define AM_UTIL_ID_UNKNOWN 0 +#define AM_UTIL_ID_APOLLO 0x0001 +#define AM_UTIL_ID_APOLLO2 0x0002 +#define AM_UTIL_ID_APOLLO3 0x0003 // Apollo3 Blue +#define AM_UTIL_ID_APOLLO3P 0x0103 // Apollo3 Blue Plus + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern uint32_t am_util_id_device(am_util_id_t *psIDDevice); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_ID_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_regdump.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_regdump.h new file mode 100644 index 0000000..9b50aeb --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_regdump.h @@ -0,0 +1,185 @@ +//***************************************************************************** +// +//! @file am_util_regdump.h +//! +//! @brief Dump specified registers for debug purposes. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_REGDUMP_H +#define AM_UTIL_REGDUMP_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "am_mcu_apollo.h" + +// +// Apollo peripherals +// +#define AM_UTIL_REGDUMP_ADC (1 << 0) +#define AM_UTIL_REGDUMP_CLKGEN (1 << 1) +#define AM_UTIL_REGDUMP_CTIMER (1 << 2) +#define AM_UTIL_REGDUMP_GPIO (1 << 3) +#define AM_UTIL_REGDUMP_IOM (1 << 4) +#define AM_UTIL_REGDUMP_IOS (1 << 5) +#define AM_UTIL_REGDUMP_MCUCTRL (1 << 6) +#define AM_UTIL_REGDUMP_RSTGEN (1 << 7) +#define AM_UTIL_REGDUMP_RTC (1 << 8) +#define AM_UTIL_REGDUMP_UART (1 << 9) +#define AM_UTIL_REGDUMP_VCOMP (1 << 10) +#define AM_UTIL_REGDUMP_WDT (1 << 11) + +// +// Apollo2 new peripherals +// +#define AM_UTIL_REGDUMP_CACHE (1 << 12) +#define AM_UTIL_REGDUMP_PDM (1 << 13) +#define AM_UTIL_REGDUMP_PWRCTRL (1 << 14) + +// +// Apollo3 new peripherals +// +#define AM_UTIL_REGDUMP_BLE (1 << 15) +#define AM_UTIL_REGDUMP_MSPI (1 << 16) + + +#define AM_UTIL_REGDUMP_INFO0 (1 << 24) + +// +// ARM Core blocks +// +#define AM_UTIL_REGDUMP_ITM (1 << 25) +#define AM_UTIL_REGDUMP_NVIC (1 << 26) +#define AM_UTIL_REGDUMP_SYSCTRL (1 << 27) +#define AM_UTIL_REGDUMP_SYSTICK (1 << 28) +#define AM_UTIL_REGDUMP_TPIU (1 << 29) + + + +//***************************************************************************** +// +// Module mask definitions +// +//***************************************************************************** +#define AM_UTIL_REGDUMP_APOLLO \ + ( AM_UTIL_REGDUMP_ADC | \ + AM_UTIL_REGDUMP_CLKGEN | \ + AM_UTIL_REGDUMP_CTIMER | \ + AM_UTIL_REGDUMP_GPIO | \ + AM_UTIL_REGDUMP_IOM | \ + AM_UTIL_REGDUMP_IOS | \ + AM_UTIL_REGDUMP_MCUCTRL | \ + AM_UTIL_REGDUMP_RSTGEN | \ + AM_UTIL_REGDUMP_RTC | \ + AM_UTIL_REGDUMP_UART | \ + AM_UTIL_REGDUMP_VCOMP | \ + AM_UTIL_REGDUMP_WDT ) + +#define AM_UTIL_REGDUMP_APOLLO2 \ + ( AM_UTIL_REGDUMP_CACHE | \ + AM_UTIL_REGDUMP_PDM | \ + AM_UTIL_REGDUMP_PWRCTRL ) + +#define AM_UTIL_REGDUMP_CORE \ + ( AM_UTIL_REGDUMP_ITM | \ + AM_UTIL_REGDUMP_NVIC | \ + AM_UTIL_REGDUMP_SYSCTRL | \ + AM_UTIL_REGDUMP_SYSTICK | \ + AM_UTIL_REGDUMP_TPIU ) + +// +// Get a register dump of ALL modules in a block. +// +#ifdef AM_PART_APOLLO +#define AM_UTIL_REGDUMP_ALL \ + ( AM_UTIL_REGDUMP_APOLLO | \ + AM_UTIL_REGDUMP_CORE ) +#endif // PART_APOLLO + +#if defined(AM_PART_APOLLO2) || defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P) +#define AM_UTIL_REGDUMP_ALL \ + ( AM_UTIL_REGDUMP_APOLLO | \ + AM_UTIL_REGDUMP_APOLLO2 | \ + AM_UTIL_REGDUMP_CORE ) +#endif // PART_APOLLO + +// +// Get a register dump of ALL modules in a block. +// +#define AM_UTIL_REGDUMP_MOD_ALL 0xFFFFFFFF + +// +// This macro determines a mask given the first and last modules desired. e.g. +// REGDUMP_MOD_MASK(2,4) // Dump regs for modules 2, 3, and 4 +// +#define REGDUMP_MOD_MASK(modfirst, modlast) \ + (((1 << (modlast - modfirst + 1)) - 1) << modfirst) + +// +// These macros determine a single module. e.g. +// REGDUMP_MOD2 | REGDUMP_MOD4 // Dump regs for modules 2 and 4 (skip 3) +// +#define REGDUMP_MOD(n) (1 << n) +#define REGDUMP_MOD0 (REGDUMP_MOD(0)) +#define REGDUMP_MOD1 (REGDUMP_MOD(1)) +#define REGDUMP_MOD2 (REGDUMP_MOD(2)) +#define REGDUMP_MOD3 (REGDUMP_MOD(3)) +#define REGDUMP_MOD4 (REGDUMP_MOD(4)) +#define REGDUMP_MOD5 (REGDUMP_MOD(5)) +#define REGDUMP_MOD6 (REGDUMP_MOD(6)) +#define REGDUMP_MOD7 (REGDUMP_MOD(7)) + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_util_regdump_print(uint32_t ui32PeriphMask, uint32_t ui32ModuleMask); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_REGDUMP_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.c new file mode 100644 index 0000000..2352e72 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.c @@ -0,0 +1,1258 @@ +//***************************************************************************** +// +//! @file am_util_stdio.c +//! +//! @brief A few printf-style functions for use with Ambiq products +//! +//! Functions for performing printf-style operations without dynamic memory +//! allocation. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include +#include "am_util_stdio.h" + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** + +// function pointer for printf +am_util_stdio_print_char_t g_pfnCharPrint; + +// buffer for printf +static char g_prfbuf[AM_PRINTF_BUFSIZE]; + +// Flag to do conversion of '\n' to '\n\r' in sprintf() +static bool g_bTxtXlate = false; + +//***************************************************************************** +// +//! @brief Sets the interface for printf calls. +//! +//! @param pfnCharPrint - Function pointer to be used to print to interface +//! +//! This function initializes the global print function which is used for +//! printf. This allows users to define their own printf interface and pass it +//! in as a am_util_stdio_print_char_t type. +//! +//! @return None. +// +//***************************************************************************** +void +am_util_stdio_printf_init(am_util_stdio_print_char_t pfnCharPrint) +{ + g_pfnCharPrint = pfnCharPrint; +} + +//***************************************************************************** +// +//! @brief Converts strings to 32-bit unsigned integers. +//! +//! @param *str - Pointer to the string to convert +//! @param **endptr - strtoul will set this to the char after the converted num +//! @param base - Base of the number as written in the input string. +//! +//! This function was implemented in a way similar to the strtoul function +//! found in the C standard library. It will attempt to extract a numerical +//! value from the input string, and return it to the caller. Invalid input +//! strings will return a value of zero. +//! +//! @return uint32_t representing the numerical value from the string. +// +//***************************************************************************** +uint32_t +am_util_stdio_strtoul(const char *str, char **endptr, int base) +{ + char *pos; + uint32_t ui32BaseVal; + uint32_t ui32RetVal; + + // + // Prepare a pointer to start advancing through the string. + // + pos = (char *)str; + + // + // Determine what base we are using. Default to '16', but change to other + // values as specified by the user. If the user didn't specify anything, + // try to guess the base value from looking at the first few characters of + // the input + // + ui32BaseVal = 16; + + // + // Switch to octal for a leading zero + // + if (*pos == '0') + { + ui32BaseVal = 8; + pos++; + + // + // Switch back to hex for a leading '0x' + // + if (*pos == 'x') + { + ui32BaseVal = 16; + pos++; + } + } + + // + // No matter what, if the user specified a base value, use that as the real + // base value. + // + if (base) + { + ui32BaseVal = base; + } + + // + // Start accumulating the converted integer value + // + ui32RetVal = 0; + + // + // Loop through the digits, one character at a time. End the loop if the + // number is out of range + // + while ((*pos >= 'a' && *pos <= 'f' && ui32BaseVal == 16) || + (*pos >= 'A' && *pos <= 'F' && ui32BaseVal == 16) || + (*pos >= '0' && *pos <= '9')) + { + // + // Make sure to stop if we hit a NULL byte. + // + if (*pos == 0) + { + break; + } + + // + // Multiply by the base value to move up one 'digit' + // + ui32RetVal *= ui32BaseVal; + + // + // Add the value of the next character. + // + if (*pos >= '0' && *pos <= '9') + { + ui32RetVal += *pos - '0'; + } + else if (*pos >= 'A' && *pos <= 'F') + { + ui32RetVal += (*pos - 'A') + 10; + } + else + { + ui32RetVal += (*pos - 'a') + 10; + } + + // + // Grab the next character. + // + pos++; + } + + // + // If we get here, hopefully it means that we have parsed a number + // correctly. The 'pos' pointer should already be pointing at the character + // right after the last valid number, so set the enptr appropriately, and + // return the calculated numerical value of the string. + // + if (endptr) + { + *endptr = pos; + } + + return ui32RetVal; +} + +//***************************************************************************** +// +// Divide an unsigned 32-bit value by 10. +// +// Note: Adapted from Ch10 of Hackers Delight (hackersdelight.org). +// +//***************************************************************************** +static uint64_t +divu64_10(uint64_t ui64Val) +{ + uint64_t q64, r64; + uint32_t q32, r32, ui32Val; + + // + // If a 32-bit value, use the more optimal 32-bit routine. + // + if ( ui64Val >> 32 ) + { + q64 = (ui64Val>>1) + (ui64Val>>2); + q64 += (q64 >> 4); + q64 += (q64 >> 8); + q64 += (q64 >> 16); + q64 += (q64 >> 32); + q64 >>= 3; + r64 = ui64Val - q64*10; + return q64 + ((r64 + 6) >> 4); + } + else + { + ui32Val = (uint32_t)(ui64Val & 0xffffffff); + q32 = (ui32Val>>1) + (ui32Val>>2); + q32 += (q32 >> 4); + q32 += (q32 >> 8); + q32 += (q32 >> 16); + q32 >>= 3; + r32 = ui32Val - q32*10; + return (uint64_t)(q32 + ((r32 + 6) >> 4)); + } +} + +//***************************************************************************** +// +// Return the number of decimal digits in an uint64_t. +// +// example: 10000 return 5, 123 returns 3. +// +//***************************************************************************** +static int +ndigits_in_u64(uint64_t ui64Val) +{ + int iNDigits = ui64Val ? 0 : 1; + + while ( ui64Val ) + { + // + // ui32Val /= 10; + // + ui64Val = divu64_10(ui64Val); + ++iNDigits; + } + + return iNDigits; +} + +//***************************************************************************** +// +// Return the number of decimal digits in a 64-bit integer. +// +// Note: Does not include the '-' sign. +// +// example: -3 returns 1, 3 returns 1, 15 returns 2, -15 returns 2, ... +// +//***************************************************************************** +static int +ndigits_in_i64(int64_t i64Val) +{ + if ( i64Val < 0 ) + { + // + // Get absolute value + // + i64Val = -i64Val; + } + + return ndigits_in_u64((uint64_t) i64Val); +} + +//***************************************************************************** +// +// Return the number of hex digits in an uint64_t. +// +//***************************************************************************** +static int +ndigits_in_hex(uint64_t ui64Val) +{ + int iDigits = ui64Val ? 0 : 1; + + while ( ui64Val ) + { + ui64Val >>= 4; + ++iDigits; + } + + return iDigits; +} + +//***************************************************************************** +// +// Converts a string representing a decimal value to an int32_t. +// +// Returns the int32_t integer value. +// +// Note: If a count of the number of chars is desired, then provide +// pui32CharCnt. +// +//***************************************************************************** +static uint32_t +decstr_to_int(const char *pcStr, uint32_t *pui32CharCnt) +{ + bool bNeg = false; + uint32_t ui32Val = 0, uCnt = 0; + + if ( *pcStr == '-') + { + bNeg = true; + pcStr++; + uCnt++; + } + + while ( *pcStr >= '0' && *pcStr <= '9' ) + { + ++uCnt; + + // + // Multiply accumulated value by 10. + // + ui32Val *= 10; + + // + // Add in the new low digit. + // + ui32Val += (*pcStr - '0'); + pcStr++; + } + + if ( pui32CharCnt ) + { + *pui32CharCnt = uCnt; + } + + return bNeg ? -ui32Val : ui32Val; +} + +//***************************************************************************** +// +// Converts ui64Val to a string. +// Note: pcBuf[] must be sized for a minimum of 21 characters. +// +// Returns the number of decimal digits in the string. +// +// NOTE: If pcBuf is NULL, will compute a return ui64Val only (no chars +// written). +// +//***************************************************************************** +static int +uint64_to_str(uint64_t ui64Val, char *pcBuf) +{ + char tbuf[25]; + int ix = 0, iNumDig = 0; + unsigned uMod; + uint64_t u64Tmp; + + do + { + // + // Divide by 10 + // + u64Tmp = divu64_10(ui64Val); + + // + // Get modulus + // + uMod = ui64Val - (u64Tmp * 10); + + tbuf[ix++] = uMod + '0'; + ui64Val = u64Tmp; + } while ( ui64Val ); + + // + // Save the total number of digits + // + iNumDig = ix; + + // + // Now, reverse the buffer when saving to the caller's buffer. + // + if ( pcBuf ) + { + while ( ix-- ) + { + *pcBuf++ = tbuf[ix]; + } + + // + // Terminate the caller's buffer + // + *pcBuf = 0x00; + } + + return iNumDig; +} + +//***************************************************************************** +// +// Converts ui64Val to a hex string. Alpha chars are lower case. +// Input: +// ui64Val = Value to be converted. +// pcBuf[] must be sized for a minimum of 17 characters. +// +// Returns the number of hex digits required for ui64Val (does not +// include the terminating NULL char in the string). +// +// NOTE: If pcBuf is NULL, will compute a return value only (no chars +// written). +// +//***************************************************************************** +static int +uint64_to_hexstr(uint64_t ui64Val, char *pcBuf, bool bLower) +{ + int iNumDig, ix = 0; + char cCh, tbuf[20]; + + if ( ui64Val == 0 ) + { + tbuf[ix++] = '0'; // Print a '0' + } + + while ( ui64Val ) + { + cCh = ui64Val & 0xf; + + // + // Alpha character + // + if ( cCh > 9 ) + { + cCh += bLower ? 0x27 : 0x7; + } + + tbuf[ix++] = cCh + '0'; + ui64Val >>= 4; + } + + // + // Save the total number of digits + // + iNumDig = ix; + + // + // Now, reverse the buffer when saving to the callers buffer. + // + if (pcBuf) + { + while (ix--) + { + *pcBuf++ = tbuf[ix]; + } + + // + // Terminate the caller's buffer + // + *pcBuf = 0; + } + + return iNumDig; +} + +//***************************************************************************** +// +// Return length of the given string. +// +//***************************************************************************** +static uint32_t +simple_strlen(char *pcBuf) +{ + uint32_t ui32RetVal = 0; + if ( !pcBuf ) + { + return ui32RetVal; + } + + while ( *pcBuf++ ) + { + ui32RetVal++; + } + return ui32RetVal; +} + +//***************************************************************************** +// +// Pad a string buffer with pad characters. +// +//***************************************************************************** +static int32_t +padbuffer(char *pcBuf, uint8_t cPadChar, int32_t i32NumChars) +{ + int32_t i32Cnt = 0; + + if ( i32NumChars <= 0 ) + { + return i32Cnt; + } + + while ( i32NumChars-- ) + { + if ( pcBuf ) + { + *pcBuf++ = cPadChar; + } + i32Cnt++; + } + + return i32Cnt; +} + +//***************************************************************************** +// +//! @brief Text mode translates linefeed (\n) characters to carriage return/ +//! linefeed (CR/LF) combinations in printf() and sprintf() functions. +//! +//! @param bSetTextTranslationMode - true: Do LF to CR/LF translation. +//! false: Don't do the text mode translation. +//! +//! This function causes the printf() and sprintf() functions to translate +//! newline characters (\\n) into CR/LF (\\r\\n) combinations. +//! +//! @return Previous mode. +// +//***************************************************************************** +bool +am_util_stdio_textmode_set(bool bSetTextTranslationMode) +{ + bool bRet = g_bTxtXlate; + + // + // true=cvt LF chars to CR/LF + // + g_bTxtXlate = bSetTextTranslationMode; + + // + // return previous mode. + // + return bRet; +} + +//***************************************************************************** +// +// Float to ASCII text. A basic implementation for providing support for +// single-precision %f. +// +// param +// fValue = Float value to be converted. +// pcBuf = Buffer to place string AND input of buffer size. +// iPrecision = Desired number of decimal places. +// IMPORTANT: On entry, the first 32-bit word of pcBuf must +// contain the size (in bytes) of the buffer! +// The recommended size is at least 16 bytes. +// +// This function performs a basic translation of a floating point single +// precision value to a string. +// +// return Number of chars printed to the buffer. +// +//***************************************************************************** +#define AM_FTOA_ERR_VAL_TOO_SMALL -1 +#define AM_FTOA_ERR_VAL_TOO_LARGE -2 +#define AM_FTOA_ERR_BUFSIZE -3 + +typedef union +{ + int32_t I32; + float F; +} i32fl_t; + +static int ftoa(float fValue, char *pcBuf, int iPrecision) +{ + i32fl_t unFloatValue; + int iExp2, iBufSize; + int32_t i32Significand, i32IntPart, i32FracPart; + char *pcBufInitial, *pcBuftmp; + + iBufSize = *(uint32_t*)pcBuf; + if (iBufSize < 4) + { + return AM_FTOA_ERR_BUFSIZE; + } + + if (fValue == 0.0f) + { + // "0.0" + *(uint32_t*)pcBuf = 0x00 << 24 | ('0' << 16) | ('.' << 8) | ('0' << 0); + return 3; + } + + pcBufInitial = pcBuf; + + unFloatValue.F = fValue; + + iExp2 = ((unFloatValue.I32 >> 23) & 0x000000FF) - 127; + i32Significand = (unFloatValue.I32 & 0x00FFFFFF) | 0x00800000; + i32FracPart = 0; + i32IntPart = 0; + + if (iExp2 >= 31) + { + return AM_FTOA_ERR_VAL_TOO_LARGE; + } + else if (iExp2 < -23) + { + return AM_FTOA_ERR_VAL_TOO_SMALL; + } + else if (iExp2 >= 23) + { + i32IntPart = i32Significand << (iExp2 - 23); + } + else if (iExp2 >= 0) + { + i32IntPart = i32Significand >> (23 - iExp2); + i32FracPart = (i32Significand << (iExp2 + 1)) & 0x00FFFFFF; + } + else // if (iExp2 < 0) + { + i32FracPart = (i32Significand & 0x00FFFFFF) >> -(iExp2 + 1); + } + + if (unFloatValue.I32 < 0) + { + *pcBuf++ = '-'; + } + + if (i32IntPart == 0) + { + *pcBuf++ = '0'; + } + else + { + if (i32IntPart > 0) + { + uint64_to_str(i32IntPart, pcBuf); + } + else + { + *pcBuf++ = '-'; + uint64_to_str(-i32IntPart, pcBuf); + } + while (*pcBuf) // Get to end of new string + { + pcBuf++; + } + } + + // + // Now, begin the fractional part + // + *pcBuf++ = '.'; + + if (i32FracPart == 0) + { + *pcBuf++ = '0'; + } + else + { + int jx, iMax; + + iMax = iBufSize - (pcBuf - pcBufInitial) - 1; + iMax = (iMax > iPrecision) ? iPrecision : iMax; + + for (jx = 0; jx < iMax; jx++) + { + i32FracPart *= 10; + *pcBuf++ = (i32FracPart >> 24) + '0'; + i32FracPart &= 0x00FFFFFF; + } + + // + // Per the printf spec, the number of digits printed to the right of the + // decimal point (i.e. iPrecision) should be rounded. + // Some examples: + // Value iPrecision Formatted value + // 1.36399 Unspecified (6) 1.363990 + // 1.36399 3 1.364 + // 1.36399 4 1.3640 + // 1.36399 5 1.36399 + // 1.363994 Unspecified (6) 1.363994 + // 1.363994 3 1.364 + // 1.363994 4 1.3640 + // 1.363994 5 1.36399 + // 1.363995 Unspecified (6) 1.363995 + // 1.363995 3 1.364 + // 1.363995 4 1.3640 + // 1.363995 5 1.36400 + // 1.996 Unspecified (6) 1.996000 + // 1.996 2 2.00 + // 1.996 3 1.996 + // 1.996 4 1.9960 + // + // To determine whether to round up, we'll look at what the next + // decimal value would have been. + // + if ( ((i32FracPart * 10) >> 24) >= 5 ) + { + // + // Yes, we need to round up. + // Go back through the string and make adjustments as necessary. + // + pcBuftmp = pcBuf - 1; + while ( pcBuftmp >= pcBufInitial ) + { + if ( *pcBuftmp == '.' ) + { + } + else if ( *pcBuftmp == '9' ) + { + *pcBuftmp = '0'; + } + else + { + *pcBuftmp += 1; + break; + } + pcBuftmp--; + } + } + } + + // + // Terminate the string and we're done + // + *pcBuf = 0x00; + + return (pcBuf - pcBufInitial); +} // ftoa() + +//****************************************************************************** +// +//! @brief Format data into string. (va_list implementation) +//! +//! @param *pcBuf - Pointer to the buffer to store the string +//! @param *pcFmt - Pointer to formatter string +//! +//! A lite version of vsprintf(). +//! Currently handles the following specifiers: +//! %c +//! %s +//! %[0][width]d (also %i) +//! %[0][width]u +//! %[0][width]x +//! %[.precision]f +//! +//! Note than any unrecognized or unhandled format specifier character is +//! simply printed. For example, "%%" will print a '%' character. +//! +//! @return uint32_t representing the number of characters printed. +// +//****************************************************************************** +uint32_t +am_util_stdio_vsprintf(char *pcBuf, const char *pcFmt, va_list pArgs) +{ + char *pcStr; + uint64_t ui64Val; + int64_t i64Val; + uint32_t ui32NumChars, ui32CharCnt = 0; + int iWidth, iVal, iPrecision; + uint8_t ui8CharSpecifier, ui8PadChar; + bool bLower, bLongLong, bNeg; + uint32_t ui32strlen = 0; + + while ( *pcFmt != 0x0 ) + { + iPrecision = 6; // printf() default precision for %f is 6 + + if ( *pcFmt != '%' ) + { + // + // Accumulate the string portion of the format specification. + // + if ( pcBuf ) + { + // If '\n', convert to '\r\n' + if ( *pcFmt == '\n' && g_bTxtXlate ) + { + *pcBuf++ = '\r'; + ++ui32CharCnt; + } + *pcBuf++ = *pcFmt; + } + + ++pcFmt; + ++ui32CharCnt; + continue; + } + + // + // Handle the specifier. + // + ++pcFmt; + bLower = bLongLong = false; + + // + // Default to space as ui8PadChar + // + ui8PadChar = ' '; + + if ( *pcFmt == '0' ) + { + ui8PadChar = '0'; + ++pcFmt; + } + + // + // Width specifier + // + iWidth = decstr_to_int(pcFmt, &ui32NumChars); + pcFmt += ui32NumChars; + + // + // For now, only support a negative width specifier for %s + // + if ( ( *pcFmt != 's' ) && ( iWidth < 0 ) ) + { + iWidth = -iWidth; + } + + // + // Check for precision specifier + // + if (*pcFmt == '.') + { + ++pcFmt; + iPrecision = decstr_to_int(pcFmt, &ui32NumChars); + pcFmt += ui32NumChars; + } + + // + // Check for the long or long long length field sub-specifiers, 'l' or + // 'll', which must be a modifier for either 'd', 'i', 'u', 'x', or 'X' + // (or even 'o', which is not currently supported). Other sub-specifiers + // like 'hh','h', etc. are not currently handled. + // Note - 'l' is used in Coremark, a primary reason it's supported here. + // + if ( *pcFmt == 'l' ) + { + pcFmt++; + if ( *pcFmt == 'l' ) // "ll" (long long) + { + pcFmt++; + bLongLong = true; + } + } + + switch ( *pcFmt ) + { + case 'c': + ui8CharSpecifier = va_arg(pArgs, uint32_t); + + if ( pcBuf ) + { + *pcBuf++ = ui8CharSpecifier; + } + + ++ui32CharCnt; + break; + + case 's': + pcStr = va_arg(pArgs, char *); + + // + // For %s, we support the width specifier. If iWidth is negative + // the string is left-aligned (padding on the right). Otherwise + // the string is padded at the beginning with spaces. + // + ui32strlen = simple_strlen(pcStr); + if ( iWidth > 0 ) + { + // Pad the beginning of the string (right-aligned). + if ( ui32strlen < iWidth ) + { + // String needs some padding. + iWidth -= ui32strlen; + iWidth = padbuffer(pcBuf, ui8PadChar, iWidth); + pcBuf += pcBuf ? iWidth : 0; + ui32CharCnt += iWidth; + iWidth = 0; + } + } + + while (*pcStr != 0x0) + { + if ( pcBuf ) + { + *pcBuf++ = *pcStr; + } + + ++pcStr; + ++ui32CharCnt; + } + + if ( iWidth ) + { + iWidth = -iWidth; + + // Pad the end of the string (left-aligned). + if ( ui32strlen < iWidth ) + { + // String needs some padding. + iWidth -= ui32strlen; + iWidth = padbuffer(pcBuf, ui8PadChar, iWidth); + pcBuf += pcBuf ? iWidth : 0; + ui32CharCnt += iWidth; + iWidth = 0; + } + } + break; + + case 'x': + bLower = true; + case 'X': + ui64Val = bLongLong ? va_arg(pArgs, uint64_t) : + va_arg(pArgs, uint32_t); + + if ( iWidth ) + { + // + // Compute # of leading chars + // + iWidth -= ndigits_in_hex(ui64Val); + + iWidth = padbuffer(pcBuf, ui8PadChar, iWidth); + pcBuf += pcBuf ? iWidth : 0; + ui32CharCnt += iWidth; + iWidth = 0; + } + + iVal = uint64_to_hexstr(ui64Val, pcBuf, bLower); + + if ( pcBuf ) + { + pcBuf += iVal; + } + + ui32CharCnt += iVal; + break; + + case 'u': + ui64Val = bLongLong ? va_arg(pArgs, uint64_t) : + va_arg(pArgs, uint32_t); + + if ( iWidth ) + { + // + // We need to pad the beginning of the value. + // Compute # of leading chars + // + iWidth -= ndigits_in_u64(ui64Val); + + iWidth = padbuffer(pcBuf, ui8PadChar, iWidth); + pcBuf += pcBuf ? iWidth : 0; + ui32CharCnt += iWidth; + iWidth = 0; + } + + iVal = uint64_to_str(ui64Val, pcBuf); + + if ( pcBuf ) + { + pcBuf += iVal; + } + + ui32CharCnt += iVal; + break; + + case 'd': + case 'i': + // + // Output for a negative number, for example, -5: + // %d:-5 + // %5d: -5 + // %05d:-0005 + // + i64Val = bLongLong ? va_arg(pArgs, int64_t) : + va_arg(pArgs, int32_t); + + // + // Get absolute value + // + if ( i64Val < 0 ) + { + ui64Val = -i64Val; // Get absolute value + bNeg = true; + } + else + { + ui64Val = i64Val; + bNeg = false; + } + + if ( iWidth ) + { + // + // We need to pad the beginning of the value. + // Compute # of leading chars + // + iWidth -= ndigits_in_i64(ui64Val); + + if ( bNeg ) + { + --iWidth; + + // + // Allow for the negative sign + // + if ( ui8PadChar == '0' ) + { + // + // Print the neg sign BEFORE the leading zeros + // + if ( pcBuf ) + { + *pcBuf++ = '-'; + } + + ++ui32CharCnt; + } + } + + iWidth = padbuffer(pcBuf, ui8PadChar, iWidth); + pcBuf += pcBuf ? iWidth : 0; + ui32CharCnt += iWidth; + iWidth = 0; + + if ( bNeg && (ui8PadChar == ' ') ) + { + // + // Print the neg sign AFTER the leading blanks + // + if ( pcBuf ) + { + *pcBuf++ = '-'; + } + + ++ui32CharCnt; + } + } + else + { + if ( bNeg ) + { + if ( pcBuf ) + { + *pcBuf++ = '-'; + } + ++ui32CharCnt; + } + } + + iVal = uint64_to_str(ui64Val, pcBuf); + + if ( pcBuf ) + { + pcBuf += iVal; + } + + ui32CharCnt += iVal; + break; + + + case 'f': + case 'F': + if ( pcBuf ) + { + float fValue = va_arg(pArgs, double); + + // + // pcBuf is an input (size of buffer) and also an output of ftoa() + // + *(uint32_t*)pcBuf = 20; + + iVal = ftoa(fValue, pcBuf, iPrecision); + if ( iVal < 0 ) + { + uint32_t u32PrntErrVal; + if ( iVal == AM_FTOA_ERR_VAL_TOO_SMALL ) + { + u32PrntErrVal = (0x00 << 24) | ('0' << 16) | + ('.' << 8) | ('0' << 0); // "0.0" + } + else if ( iVal == AM_FTOA_ERR_VAL_TOO_LARGE ) + { + u32PrntErrVal = (0x00 << 24) | ('#' << 16) | + ('.' << 8) | ('#' << 0); // "#.#" + } + else + { + u32PrntErrVal = (0x00 << 24) | ('?' << 16) | + ('.' << 8) | ('?' << 0); // "?.?" + } + *(uint32_t*)pcBuf = u32PrntErrVal; + iVal = 3; + } + ui32CharCnt += iVal; + pcBuf += iVal; + } + break; + + // + // Invalid specifier character + // For non-handled specifiers, we'll just print the character. + // e.g. this will allow the normal printing of a '%' using + // "%%". + // + default: + if ( pcBuf ) + { + *pcBuf++ = *pcFmt; + } + + ++ui32CharCnt; + break; + + } // switch() + + // + // Bump the format specification to the next character + // + ++pcFmt; + + } // while () + + // + // Terminate the string + // + if ( pcBuf ) + { + *pcBuf = 0x0; + } + + return (ui32CharCnt); +} + +//****************************************************************************** +// +//! @brief Format data into string. +//! +//! @param *pcBuf - Pointer to the buffer to store the string +//! @param *pcFmt - Pointer to formater string +//! +//! A lite version of vsprintf(). +//! Currently handles the following specifiers: +//! %c +//! %s +//! %[0][width]d (also %i) +//! %[0][width]u +//! %[0][width]x +//! +//! Note than any unrecognized or unhandled format specifier character is +//! simply printed. For example, "%%" will print a '%' character. +//! +//! @return uint32_t representing the number of characters printed. +// +//****************************************************************************** +uint32_t +am_util_stdio_sprintf(char *pcBuf, const char *pcFmt, ...) +{ + uint32_t ui32CharCnt; + + va_list pArgs; + va_start(pArgs, pcFmt); + ui32CharCnt = am_util_stdio_vsprintf(pcBuf, pcFmt, pArgs); + va_end(pArgs); + + return ui32CharCnt; +} + +//***************************************************************************** +// +//! @brief A lite version of printf() +//! +//! @param *pcFmt - Pointer to formatter string +//! +//! See am_util_stdio_sprintf() for more details. +//! +//! @return uint32_t representing the number of characters printed. +// +// ***************************************************************************** +uint32_t +am_util_stdio_printf(const char *pcFmt, ...) +{ + uint32_t ui32NumChars; + + if (!g_pfnCharPrint) + { + return 0; + } + + // + // Convert to the desired string. + // + va_list pArgs; + va_start(pArgs, pcFmt); + ui32NumChars = am_util_stdio_vsprintf(g_prfbuf, pcFmt, pArgs); + va_end(pArgs); + + // + // This is where we print the buffer to the configured interface. + // + g_pfnCharPrint(g_prfbuf); + + // + // return the number of characters printed. + // + return ui32NumChars; +} + +//***************************************************************************** +// +//! @brief Clear the terminal screen +//! +//! This function clears a standard terminal screen. +//! +//! @return None. +// +//***************************************************************************** +void +am_util_stdio_terminal_clear(void) +{ + // + // Escape codes to clear a terminal screen and put the cursor in the top + // left corner. + // We'll first print a number of spaces, which helps get the ITM in sync + // with AM Flash, especially after a reset event or a system clock + // frequency change. + // + am_util_stdio_printf("\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n"); +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.h new file mode 100644 index 0000000..da046dc --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.h @@ -0,0 +1,88 @@ +//***************************************************************************** +// +//! @file am_util_stdio.h +//! +//! @brief A few printf-style functions for use with Ambiq products +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_STDIO_H +#define AM_UTIL_STDIO_H + +/* get va_list from compiler. */ +#include + +#ifdef __cplusplus +extern "C" +{ +#endif +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** + +// buffer size for printf +#ifndef AM_PRINTF_BUFSIZE +#define AM_PRINTF_BUFSIZE 256 +#endif + +typedef void (*am_util_stdio_print_char_t)(char *pcStr); + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_util_stdio_printf_init(am_util_stdio_print_char_t pfnCharPrint); +extern uint32_t am_util_stdio_strtoul(const char *str, char **endptr, int base); +extern bool am_util_stdio_textmode_set(bool bSetTextTranslationMode); +extern uint32_t am_util_stdio_vsprintf(char *pcBuf, const char *pcFmt, va_list pArgs); +extern uint32_t am_util_stdio_sprintf(char *pui8Buf, const char *pui8Fmt, ...); +extern uint32_t am_util_stdio_printf(const char *pui8Fmt, ...); +extern void am_util_stdio_terminal_clear(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_STDIO_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.c new file mode 100644 index 0000000..d173f0c --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.c @@ -0,0 +1,614 @@ +//***************************************************************************** +// +//! @file am_util_string.c +//! +//! @brief A subset of the functions provided in the C standard string library. +//! +//! The functions here are reimplementation of some of the standard "string" +//! functions. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_util_string.h" + + +//***************************************************************************** +// +//! @brief Table for quick lookup of character attributes. +// +//***************************************************************************** +#if MINIMIZE_CATTR_TABLE +#define CATTR_TBL_SIZE 128 +#else +#define CATTR_TBL_SIZE 256 +#endif + +const uint8_t am_cattr[CATTR_TBL_SIZE] = +{ + AM_CATTR_NONE, /* 0x00 */ + AM_CATTR_NONE, /* 0x01 */ + AM_CATTR_NONE, /* 0x02 */ + AM_CATTR_NONE, /* 0x03 */ + AM_CATTR_NONE, /* 0x04 */ + AM_CATTR_NONE, /* 0x05 */ + AM_CATTR_NONE, /* 0x06 */ + AM_CATTR_NONE, /* 0x07 */ + AM_CATTR_NONE, /* 0x08 */ + AM_CATTR_WHSPACE, /* 0x09 */ + AM_CATTR_WHSPACE, /* 0x0A */ + AM_CATTR_WHSPACE, /* 0x0B */ + AM_CATTR_WHSPACE, /* 0x0C */ + AM_CATTR_WHSPACE, /* 0x0D */ + AM_CATTR_NONE, /* 0x0E */ + AM_CATTR_NONE, /* 0x0F */ + AM_CATTR_NONE, /* 0x00 */ + AM_CATTR_NONE, /* 0x11 */ + AM_CATTR_NONE, /* 0x12 */ + AM_CATTR_NONE, /* 0x13 */ + AM_CATTR_NONE, /* 0x14 */ + AM_CATTR_NONE, /* 0x15 */ + AM_CATTR_NONE, /* 0x16 */ + AM_CATTR_NONE, /* 0x17 */ + AM_CATTR_NONE, /* 0x18 */ + AM_CATTR_NONE, /* 0x19 */ + AM_CATTR_NONE, /* 0x1A */ + AM_CATTR_NONE, /* 0x1B */ + AM_CATTR_NONE, /* 0x1C */ + AM_CATTR_NONE, /* 0x1D */ + AM_CATTR_NONE, /* 0x1E */ + AM_CATTR_NONE, /* 0x1F */ + AM_CATTR_WHSPACE, /* 0x20, space */ + AM_CATTR_FILENM83, /* 0x21, ! */ + AM_CATTR_NONE, /* 0x22, " */ + AM_CATTR_FILENM83, /* 0x23, # */ + AM_CATTR_FILENM83, /* 0x24, $ */ + AM_CATTR_FILENM83, /* 0x25, % */ + AM_CATTR_FILENM83, /* 0x26, & */ + AM_CATTR_FILENM83, /* 0x27, ' */ + AM_CATTR_FILENM83, /* 0x28, ( */ + AM_CATTR_FILENM83, /* 0x29, ) */ + AM_CATTR_NONE, /* 0x2A, * */ + AM_CATTR_NONE, /* 0x2B, + */ + AM_CATTR_NONE, /* 0x2C, , */ + AM_CATTR_FILENM83, /* 0x2D, - */ + AM_CATTR_FILENM83, /* 0x2E, . */ + AM_CATTR_NONE, /* 0x2F, / */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x30, 0 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x31, 1 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x32, 2 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x33, 3 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x34, 4 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x35, 5 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x36, 6 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x37, 7 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x38, 8 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x39, 9 */ + AM_CATTR_NONE, /* 0x3A, : */ + AM_CATTR_NONE, /* 0x3B, ; */ + AM_CATTR_NONE, /* 0x3C, < */ + AM_CATTR_NONE, /* 0x3D, = */ + AM_CATTR_NONE, /* 0x3E, > */ + AM_CATTR_NONE, /* 0x3F, ? */ + AM_CATTR_FILENM83, /* 0x40, @ */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x41, A */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x42, B */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x43, C */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x44, D */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x45, E */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x46, F */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x47, G */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x48, H */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x49, I */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4A, J */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4B, K */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4C, L */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4D, M */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4E, N */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4F, O */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x50, P */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x51, Q */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x52, R */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x53, S */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x54, T */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x55, U */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x56, V */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x57, W */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x58, X */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x59, Y */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x5A, Z */ + AM_CATTR_NONE, /* 0x5B, [ */ + AM_CATTR_NONE, /* 0x5C, \ */ + AM_CATTR_NONE, /* 0x5D, ] */ + AM_CATTR_FILENM83, /* 0x5E, ^ */ + AM_CATTR_FILENM83, /* 0x5F, _ */ + AM_CATTR_FILENM83, /* 0x60, ` */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x61, a */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x62, b */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x63, c */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x64, d */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x65, e */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x66, f */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x67, g */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x68, h */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x69, i */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6A, j */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6B, k */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6C, l */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6D, m */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6E, n */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6F, o */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x70, p */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x71, q */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x72, r */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x73, s */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x74, t */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x75, u */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x76, v */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x77, w */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x78, x */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x79, y */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x7A, z */ + AM_CATTR_FILENM83, /* 0x7B, { */ + AM_CATTR_NONE, /* 0x7C, | */ + AM_CATTR_FILENM83, /* 0x7D, } */ + AM_CATTR_FILENM83, /* 0x7E, ~ */ + AM_CATTR_NONE /* 0x7F, delete */ + + // + // All bit7 chars are AM_CATTR_NONE. + // +}; + +//***************************************************************************** +// +//! @brief Character "is" functions +//! +//! This family of functions tests a given integer value in order to determine +//! whether the integer satisfies the test condition. +//! These functions are generally based on the C99 standard functions. +//! +//! By default all of the "is" functions are implemented as macros. To implement +//! as functions rather than macros, use a global compiler command line (-D) +//! option to define AM_UTIL_STRING_CTYPE_DISABLE_MACROS. +//! +//! Standard functions currently implemented include: +//! isalnum(), isalpha(), islower(), isupper(), isdigit(), isxdigit(), +//! isspace(). +//! +//! Standard functions not currently implemented include: +//! iscntrl(), isgraph(), isprint(), ispunct(), isblank() (new for C99). +//! +//! Non-standard functions currently implemented include: +//! isfilenm83(). +//! +//! @return Each function returns a nonzero value if the integer satisfies +//! the test condition and 0 if it does not. +// +//***************************************************************************** + +#ifdef AM_UTIL_STRING_CTYPE_DISABLE_MACROS +int +am_util_string_isalnum(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & (AM_CATTR_ALPHA | AM_CATTR_DIGIT)) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & (AM_CATTR_ALPHA | AM_CATTR_DIGIT)) ? 1 : 0; +#endif +} + +int +am_util_string_isalpha(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_ALPHA) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_ALPHA) ? 1 : 0; +#endif +} + +int +am_util_string_isdigit(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_DIGIT) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_DIGIT) ? 1 : 0; +#endif +} + +int am_util_string_islower(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_LOWER) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_LOWER) ? 1 : 0; +#endif +} + +int +am_util_string_isspace(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_WHSPACE) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_WHSPACE) ? 1 : 0; +#endif +} + +int +am_util_string_isupper(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_UPPER) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_UPPER) ? 1 : 0; +#endif +} + +int +am_util_string_isxdigit(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_XDIGIT) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_XDIGIT) ? 1 : 0; +#endif +} + +int am_util_string_tolower(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (am_cattr[c & 0x7f] & AM_CATTR_UPPER) ? c | 0x20 : c; +#else + return (am_cattr[c & 0xff] & AM_CATTR_UPPER) ? c | 0x20 : c; +#endif +} + +int am_util_string_toupper(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (am_cattr[c & 0x7f] & AM_CATTR_LOWER) ? c & ~0x20 : c; +#else + return (am_cattr[c & 0xff] & AM_CATTR_LOWER) ? c & ~0x20 : c; +#endif +} + + +// +// Non-standard "is" Functions +// +int +am_util_string_isfilenm83(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_FILENM83) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_FILENM83) ? 1 : 0; +#endif +} +#endif // AM_UTIL_STRING_CTYPE_DISABLE_MACROS + + +//***************************************************************************** +// +//! @brief Compare two strings. +//! +//! @param str1 is the first string to compare. +//! @param str2 is the second string to compare +//! +//! This function steps through a pair of strings, character by character, to +//! determine if the strings contain the same characters. If the strings match, +//! this function will return a zero. If str1 is alphabetically earlier than +//! str2, the return value will be negative. Otherwise, the return value will +//! be positive. +//! +//! @return 0 for a perfect match, negative value if str1str2. +// +//***************************************************************************** +int32_t +am_util_string_strcmp(const char *str1, const char *str2) +{ + return am_util_string_strncmp(str1, str2, 0xffffffff); +} + +//***************************************************************************** +// +//! @brief Compare two strings with a specified count. +//! +//! @param str1 is the first string to compare. +//! @param str2 is the second string to compare +//! @param num is the maximum number of characters to compare. +//! +//! This function steps through a pair of strings, character by character, to +//! determine if the strings contain the same characters. If the strings match, +//! this function will return a zero. If str1 is alphabetically earlier than +//! str2, the return value will be negative. Otherwise, the return value will +//! be positive. +//! +//! @return 0 for a perfect match, negative value if str1str2. +// +//***************************************************************************** +int32_t +am_util_string_strncmp(const char *str1, const char *str2, uint32_t num) +{ + while ( num-- ) + { + // Check for inequality OR end of string + if ( *str1 != *str2 || *str1 == '\0' ) + { + return *str1 - *str2; + } + + str1++; + str2++; + } + + // + // Since we made it here, the strings must be equal to n characters. + // + return 0; +} + +//***************************************************************************** +// +//! @brief Compare two strings with a specified count and without regard to +//! letter case in the strings. +//! +//! @param str1 is the first string to compare. +//! @param str2 is the second string to compare +//! @param num is the maximum number of characters to compare. +//! +//! This function steps through a pair of strings, character by character, to +//! determine if the strings contain the same characters. If the strings match, +//! this function will return a zero. If str1 is alphabetically earlier than +//! str2, the return value will be negative. Otherwise, the return value will +//! be positive. +//! +//! @return 0 for a perfect match, negative value if str1str2. +// +//***************************************************************************** +int32_t +am_util_string_strnicmp(const char *str1, const char *str2, int num) +{ + uint8_t cChar1, cChar2; + + while ( *str1 && *str2 && num ) + { + cChar1 = *str1; + cChar2 = *str2; + + cChar1 |= ( am_cattr[cChar1] & AM_CATTR_UPPER ) ? 0x20 : 0x00; + cChar2 |= ( am_cattr[cChar2] & AM_CATTR_UPPER ) ? 0x20 : 0x00; + + if ( cChar1 != cChar2 ) + { + return cChar1 - cChar2; + } + + str1++; + str2++; + num--; + } + + // + // Since we made it here, the strings must be equal to n characters. + // + return 0; +} + +//***************************************************************************** +// +//! @brief Compare two strings with case-insensitivity. +//! +//! @param str1 is the first string to compare. +//! @param str2 is the second string to compare +//! +//! This function compares each character in the 2 strings, converting all +//! alpha characters to lower-case to make the comparison. +//! +//! To illustrate a possible unexpected outcome due to comparing the strings +//! as lower case, consider the example strings "AMBIQ_MICRO" and "AMBIQMICRO". +//! For these strings, stricmp() will return a negative value (indicating the +//! first as before the second), whereas strcmp() will return a positive value. +//! +//! @return 0 for a case-insensitive match, negative value if str1str2. +// +//***************************************************************************** +int32_t +am_util_string_stricmp(const char *str1, const char *str2) +{ + uint8_t cChar1, cChar2; + + while ( *str1 && *str2 ) + { + cChar1 = *str1++; + cChar2 = *str2++; + + cChar1 |= ( am_cattr[cChar1] & AM_CATTR_UPPER ) ? 0x20 : 0x00; + cChar2 |= ( am_cattr[cChar2] & AM_CATTR_UPPER ) ? 0x20 : 0x00; + + if ( cChar1 != cChar2 ) + { + return cChar1 - cChar2; + } + } + + return *str1 - *str2; +} + +//***************************************************************************** +// +//! @brief Return the length of a string. +//! +//! @param pcStr pointer to the string. +//! +//! This function returns the length of the string at pcStr. +//! +//! @return length of the string pcStr. +// +//***************************************************************************** +uint32_t +am_util_string_strlen(const char *pcStr) +{ + const char *pcS; + + // + // Loop through the string. + // + for (pcS = pcStr; *pcS; ++pcS); + + // + // Return the length. + // + return(pcS - pcStr); +} + +//***************************************************************************** +// +//! @brief Copies a string. +//! +//! @param pcDst pointer to the destination string. +//! @param pcSrc pointer to the source string to be copied to pcDst. +//! +//! This function copies pcSrc to the location specified by pcDst. +//! +//! @return pcDst (the location of the destination string). +// +//***************************************************************************** +char * +am_util_string_strcpy(char *pcDst, const char *pcSrc) +{ + char *pcRet = pcDst; + + // + // Blindly copy the string until we hit a terminating NULL char. + // + do + { + *pcDst++ = *pcSrc; + } while ( *pcSrc++ ); + + return pcRet; +} + +//***************************************************************************** +// +//! @brief Copies a specified number of characters of a string. +//! +//! @param pcDst pointer to the destination string. +//! @param pcSrc pointer to the source string to be copied to pcDst. +//! +//! This function copies uNum characters of pcSrc to the location specified +//! by pcDst. +//! If uNum is less than the length of pcSrc, a NULL terminating character +//! is not appended to the copied string. Thus the resultant string will be +//! exactly uNum chars in length and not terminated. +//! If uNum is greater than the length of pcSrc, then pcDst is padded with +//! NULL characters up to the uNum length. +//! Behavior is undefined if the addresses ranges overlap. +//! +//! @return pcDst (the location of the destination string). +// +//***************************************************************************** +char * +am_util_string_strncpy(char *pcDst, const char *pcSrc, uint32_t uNum) +{ + char *pcRet = pcDst; + + while (uNum > 0) + { + if ( *pcSrc ) + { + *pcDst++ = *pcSrc++; + } + else + { + *pcDst++ = 0x00; + } + uNum--; + } + + return pcRet; +} + +//***************************************************************************** +// +//! @brief Concatenate a string. +//! +//! @param pcDst pointer to the destination string. +//! @param pcSrc pointer to the source string to be copied to pcDst. +//! +//! This function concatenates the string at pcSrc to the existing string +//! at pcDst. +//! +//! Both strings, pcDst and pcSrc, must be NULL-terminated. +//! No overflow checking is performed. +//! pcDst and pcSrc shall not overlap. +//! +//! @return pcDst (the location of the destination string). +// +//***************************************************************************** +char * +am_util_string_strcat(char *pcDst, const char *pcSrc) +{ + char *pcRet = pcDst; + + // + // Find the end of the existing string. + // + while ( *pcDst++ ); + pcDst--; + + // + // Now, copy the new string. + // + am_util_string_strcpy(pcDst, pcSrc); + + return pcRet; +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.h new file mode 100644 index 0000000..b39ceb4 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.h @@ -0,0 +1,162 @@ +//***************************************************************************** +// +//! @file am_util_string.h +//! +//! @brief A subset of the functions provided in the C standard string library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_STRING_H +#define AM_UTIL_STRING_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +// Character attributes lookup table defines. +// +//***************************************************************************** +#define AM_CATTR_NONE 0x00 +#define AM_CATTR_ALPHA 0x01 +#define AM_CATTR_LOWER 0x02 +#define AM_CATTR_UPPER 0x04 +#define AM_CATTR_DIGIT 0x08 +#define AM_CATTR_XDIGIT 0x10 +#define AM_CATTR_WHSPACE 0x20 +#define AM_CATTR_FILENM83 0x80 + +// +// Set MINIMIZE_CATTR_TABLE to 1 to configure for minimal CATTR table size, +// (256 instead of 512 bytes) but at a cost of slightly larger code size. +// However, setting this option also provides an additional level of checking +// of the argument; if the argument is not a uint8_t, the functions are +// guaranteed to return 0. +// +#define MINIMIZE_CATTR_TABLE 0 + + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +extern const uint8_t am_cattr[]; + + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern int32_t am_util_string_strcmp(const char *str1, const char *str2); +extern int32_t am_util_string_stricmp(const char *str1, const char *str2); +extern int32_t am_util_string_strncmp(const char *str1, const char *str2, + uint32_t num); +extern int32_t am_util_string_strnicmp(const char *str1, const char *str2, + int num); +extern uint32_t am_util_string_strlen(const char *pcStr); +extern char *am_util_string_strcpy(char *pcDst, const char *pcSrc); +extern char *am_util_string_strncpy(char *pcDst, const char *pcSrc, uint32_t uNum); +extern char *am_util_string_strcat(char *pcDst, const char *pcSrc); + + +//***************************************************************************** +// +// Character "is" macros and functions +// +//***************************************************************************** +// +// By default all of the "is" functions are implemented as macros. To implement +// as functions rather than macros, use a global compiler command line (-D) +// option to define AM_UTIL_STRING_CTYPE_DISABLE_MACROS. +// +#ifdef AM_UTIL_STRING_CTYPE_DISABLE_MACROS +extern int am_util_string_isalnum(int c); +extern int am_util_string_isalpha(int c); +extern int am_util_string_isdigit(int c); +extern int am_util_string_islower(int c); +extern int am_util_string_isspace(int c); +extern int am_util_string_isupper(int c); +extern int am_util_string_isxdigit(int c); +extern int am_util_string_tolower(int c); +extern int am_util_string_toupper(int c); + +// Non-standard "is" Functions +extern int am_util_string_isfilenm83(int c); +#else +#if MINIMIZE_CATTR_TABLE +#define am_util_string_isalnum(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & (AM_CATTR_ALPHA | AM_CATTR_DIGIT)) ? 1 : 0) +#define am_util_string_isalpha(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_ALPHA) ? 1 : 0) +#define am_util_string_isdigit(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_DIGIT) ? 1 : 0) +#define am_util_string_islower(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_LOWER) ? 1 : 0) +#define am_util_string_isspace(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_WHSPACE) ? 1 : 0) +#define am_util_string_isupper(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_UPPER) ? 1 : 0) +#define am_util_string_isxdigit(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_XDIGIT) ? 1 : 0) +#define am_util_string_tolower(c) ((am_cattr[c & 0x7f] & AM_CATTR_UPPER) ? c | 0x20 : c) +#define am_util_string_toupper(c) ((am_cattr[c & 0x7f] & AM_CATTR_LOWER) ? c & ~0x20 : c) +#else +#define am_util_string_isalnum(c) (am_cattr[c & 0xff] & (AM_CATTR_ALPHA | AM_CATTR_DIGIT)) +#define am_util_string_isalpha(c) (am_cattr[c & 0xff] & AM_CATTR_ALPHA) +#define am_util_string_isdigit(c) (am_cattr[c & 0xff] & AM_CATTR_DIGIT) +#define am_util_string_islower(c) (am_cattr[c & 0xff] & AM_CATTR_LOWER) +#define am_util_string_isspace(c) (am_cattr[c & 0xff] & AM_CATTR_WHSPACE) +#define am_util_string_isupper(c) (am_cattr[c & 0xff] & AM_CATTR_UPPER) +#define am_util_string_isxdigit(c) (am_cattr[c & 0xff] & AM_CATTR_XDIGIT) +#define am_util_string_tolower(c) ((am_cattr[c & 0xff] & AM_CATTR_UPPER) ? c | 0x20 : c) +#define am_util_string_toupper(c) ((am_cattr[c & 0xff] & AM_CATTR_LOWER) ? c & ~0x20 : c) +#endif // MINIMIZE_CATTR_TABLE + +// +// Non-standard "is" Functions +// +#define am_util_string_isfilenm83(c) (am_cattr[c & 0xff] & AM_CATTR_FILENM83) +#endif // AM_UTIL_STRING_CTYPE_DISABLE_MACROS + + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_STRING_H diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.c new file mode 100644 index 0000000..c815212 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.c @@ -0,0 +1,146 @@ +//***************************************************************************** +// +//! @file am_util_time.h +//! +//! @brief Functions useful for RTC, calendar, time, etc. computations. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include "am_util_time.h" + +//***************************************************************************** +// +// Macro definitions. +// +//***************************************************************************** +#define AM_UTIL_TIME_IS_LEAP_YEAR(year) \ + (year % 4 == 0 && ((year % 100 != 0) || (year % 400 != 0))) + +//***************************************************************************** +// +// Local variables. +// +//***************************************************************************** + +// +// Numer of days in each month in a standard year. +// +const static uint32_t g_iDaysPerMonth[] = + {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + +// +// Weekday drift numbers for each month. +// +const static int g_iMonthOffsets[] = + {4, 0, 0, 3, 5, 1, 3, 6, 2, 4, 0, 2}; + +//***************************************************************************** +// +//! @brief Compute the day of the week given the month, day, and year. +//! +//! @param iYear - The year of the desired date (e.g. 2016). +//! @param iMonth - The month of the desired date (1-12). +//! @param iDay - The day of the month of the desired date (1-31). +//! +//! This function is general in nature, but is designed to be used with the RTC. +//! +//! @returns An index value indicating the day of the week. +//! 0-6 indicate Sun, Mon, Tue, Wed, Thu, Fri, Sat, respectively. +//! 7 indicates that the given date is invalid (e.g. 2/29/2015). +// +//***************************************************************************** +int +am_util_time_computeDayofWeek(int iYear, int iMonth, int iDay) +{ + bool bInvalidDay; + int iYearOffset; + int iMonthOffset; + int iWeekday; + + int iLeapYearOffset = 0; + + // + // Validate inputs. Return 7 if any are out-of-bounds. + // + if ( (iMonth < 1) || (iMonth > 12) || (iYear < 0) || (iDay < 1) ) + { + return 7; + } + + // + // Make sure this day actually exists in this month. Make sure to include + // an exception for leap years. + // + if (iDay > g_iDaysPerMonth[iMonth - 1]) + { + if (iMonth == 2 && AM_UTIL_TIME_IS_LEAP_YEAR(iYear) && iDay == 29) + { + bInvalidDay = false; + } + else + { + bInvalidDay = true; + } + } + else + { + bInvalidDay = false; + } + + if (bInvalidDay) + { + return 7; + } + + iYearOffset = 2 + iYear + iYear / 4 - iYear / 100 + iYear / 400; + iMonthOffset = g_iMonthOffsets[iMonth - 1]; + + if (AM_UTIL_TIME_IS_LEAP_YEAR(iYear) && (iMonth < 3)) + { + iLeapYearOffset = -1; + } + + iWeekday = iDay + iYearOffset + iMonthOffset + iLeapYearOffset; + + return iWeekday % 7; +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.h new file mode 100644 index 0000000..23f3625 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +//! @file am_util_time.h +//! +//! @brief Functions useful for RTC, calendar, time, etc. computations. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_TIME_H +#define AM_UTIL_TIME_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern int am_util_time_computeDayofWeek(int iYear, int iMonth, int iDay); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_TIME_H + diff --git a/targets/targets.json b/targets/targets.json index 67b8099..86a1350 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -6802,6 +6802,71 @@ "release_versions": ["5"], "detect_code": ["3703"] }, + "FAMILY_Apollo3": { + "inherits": ["Target"], + "core": "Cortex-M4F", + "features": ["BLE"], + "default_toolchain": "GCC_ARM", + "supported_toolchains": [ + "GCC_ARM", + "ARMC6" + ], + "public": false, + "extra_labels": [ + "Ambiq_Micro", + "Apollo3", + "CORDIO" + ], + "device_has": [ + "MPU", + "USTICKER", + "SERIAL", + "INTERRUPTIN", + "LPTICKER", + "STDIO_MESSAGES", + "FLASH", + "SPI", + "I2C" + ], + "components": [ + "FLASHIAP" + ], + "macros": ["CORDIO_ZERO_COPY_HCI", + "USE_AMBIQ_DRIVER" + ] + }, + "AMA3B1KK": { + "public": false, + "inherits": ["FAMILY_Apollo3"], + "macros_add": ["AM_PACKAGE_BGA"] + }, + "SFE_ARTEMIS": { + "inherits": ["AMA3B1KK"] + }, + "SFE_ARTEMIS_ATP": { + "inherits": ["AMA3B1KK"] + }, + "SFE_ARTEMIS_DK": { + "inherits": ["AMA3B1KK"], + "components_add": ["lis2dh12", "hm01b0"] + }, + "SFE_ARTEMIS_MODULE": { + "inherits": ["AMA3B1KK"] + }, + "SFE_ARTEMIS_NANO": { + "inherits": ["AMA3B1KK"] + }, + "SFE_ARTEMIS_THING_PLUS": { + "inherits": ["AMA3B1KK"] + }, + "SFE_EDGE": { + "inherits": ["AMA3B1KK"], + "components_add": ["lis2dh12", "hm01b0"] + }, + "SFE_EDGE2": { + "inherits": ["AMA3B1KK"], + "components_add": ["lis2dh12", "hm01b0"] + }, "__build_tools_metadata__": { "version": "1", "public": false