diff --git a/cmsis/RTE_Components.h b/cmsis/RTE_Components.h index 1104e86..4f377cf 100644 --- a/cmsis/RTE_Components.h +++ b/cmsis/RTE_Components.h @@ -18,16 +18,7 @@ #define CMSIS_device_header -#ifndef MBED_CONF_TZ_PROCESS_STACK_SIZE -#define MBED_CONF_TZ_PROCESS_STACK_SIZE 512 -#endif -#ifndef MBED_CONF_TZ_PROCESS_STACK_SLOTS -#define MBED_CONF_TZ_PROCESS_STACK_SLOTS 8 -#endif - -#define TZ_PROCESS_STACK_SLOTS MBED_CONF_TZ_PROCESS_STACK_SLOTS -#define TZ_PROCESS_STACK_SIZE MBED_CONF_TZ_PROCESS_STACK_SIZE +#include "mbed_rtx_conf.h" +#include "mbed_cmsis_conf.h" #endif - - diff --git a/cmsis/TARGET_CORTEX_A/cmsis_armcc.h b/cmsis/TARGET_CORTEX_A/cmsis_armcc.h index cef7694..7c4c948 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_armcc.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_armcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.0.1 - * @date 07. Sep 2017 + * @version V1.0.2 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,7 +26,7 @@ #define __CMSIS_ARMCC_H #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" #endif /* CMSIS compiler control architecture macros */ diff --git a/cmsis/TARGET_CORTEX_A/cmsis_armclang.h b/cmsis/TARGET_CORTEX_A/cmsis_armclang.h index 8853836..5883364 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_armclang.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_armclang.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.0.1 - * @date 07. Sep 2017 + * @version V1.0.2 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ #pragma clang system_header /* treat file as system include file */ #ifndef __ARM_COMPAT_H -#include /* Compatibility header for ARM Compiler 5 intrinsics */ +#include /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ diff --git a/cmsis/TARGET_CORTEX_A/cmsis_compiler.h b/cmsis/TARGET_CORTEX_A/cmsis_compiler.h index d1ef182..b00c6ba 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_compiler.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_compiler.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.0.1 - * @date 01. December 2017 + * @version V1.0.2 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -28,14 +28,14 @@ #include /* - * ARM Compiler 4/5 + * Arm Compiler 4/5 */ #if defined ( __CC_ARM ) #include "cmsis_armcc.h" /* - * ARM Compiler 6 (armclang) + * Arm Compiler 6 (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #include "cmsis_armclang.h" @@ -56,7 +56,7 @@ /* - * TI ARM Compiler + * TI Arm Compiler */ #elif defined ( __TI_ARM__ ) #include diff --git a/cmsis/TARGET_CORTEX_A/cmsis_cp15.h b/cmsis/TARGET_CORTEX_A/cmsis_cp15.h index 69c991e..891bec2 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_cp15.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_cp15.h @@ -223,7 +223,7 @@ return result; } - /** \brief Get VBAR +/** \brief Get VBAR This function returns the value of the Vector Base Address Register. @@ -244,7 +244,31 @@ */ __STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) { - __set_CP(15, 0, vbar, 12, 0, 1); + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); } #if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ @@ -413,15 +437,34 @@ __set_CP(15, 0, value, 7, 14, 1); } - -/** \brief Set CCSIDR +/** \brief Set CSSELR */ -__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) { // __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); __set_CP(15, 2, value, 0, 0, 0); } +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CCSIDR + \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. + */ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +{ + __set_CSSELR(value); +} + /** \brief Get CCSIDR \return CCSIDR Register value */ diff --git a/cmsis/TARGET_CORTEX_A/cmsis_gcc.h b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h index 7f42293..5ac93d1 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_gcc.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h @@ -642,7 +642,7 @@ " VMOV D14,R2,R2 \n" " VMOV D15,R2,R2 \n" -#if __ARM_NEON == 1 +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) //Initialise D32 registers to 0 " VMOV D16,R2,R2 \n" " VMOV D17,R2,R2 \n" diff --git a/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h index beddfe8..a441e2d 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR compiler) header file - * @version V5.0.4 - * @date 01. December 2017 + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 ******************************************************************************/ //------------------------------------------------------------------------------ // -// Copyright (c) 2017 IAR Systems +// Copyright (c) 2017-2018 IAR Systems // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. diff --git a/cmsis/TARGET_CORTEX_A/core_ca.h b/cmsis/TARGET_CORTEX_A/core_ca.h index 4757a04..c7c4b51 100644 --- a/cmsis/TARGET_CORTEX_A/core_ca.h +++ b/cmsis/TARGET_CORTEX_A/core_ca.h @@ -950,8 +950,8 @@ */ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) { - register volatile uint32_t Dummy; - register volatile uint32_t ccsidr; + uint32_t Dummy; + uint32_t ccsidr; uint32_t num_sets; uint32_t num_ways; uint32_t shift_way; @@ -960,7 +960,7 @@ Dummy = level << 1U; /* set csselr, select ccsidr register */ - __set_CCSIDR(Dummy); + __set_CSSELR(Dummy); /* get current ccsidr register */ ccsidr = __get_CCSIDR(); num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; @@ -992,7 +992,7 @@ * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean */ __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { - register volatile uint32_t clidr; + uint32_t clidr; uint32_t cache_type; clidr = __get_CLIDR(); for(uint32_t i = 0U; i<7U; i++) diff --git a/cmsis/TARGET_CORTEX_A/irq_ctrl.h b/cmsis/TARGET_CORTEX_A/irq_ctrl.h index 4299c28..b171ef0 100644 --- a/cmsis/TARGET_CORTEX_A/irq_ctrl.h +++ b/cmsis/TARGET_CORTEX_A/irq_ctrl.h @@ -22,6 +22,12 @@ * limitations under the License. */ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + #ifndef IRQ_CTRL_H_ #define IRQ_CTRL_H_ diff --git a/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c b/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c index 39be23e..5fbe9dc 100644 --- a/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c +++ b/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c @@ -24,7 +24,8 @@ #include -#include +#include "RTE_Components.h" +#include CMSIS_device_header #include "irq_ctrl.h" @@ -125,13 +126,11 @@ /// Configure interrupt request mode. __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) { - int32_t status; uint32_t val; uint8_t cfg; uint8_t secure; uint8_t cpu; - - status = 0; + int32_t status = 0; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { // Check triggering mode @@ -142,6 +141,7 @@ } else if (val == IRQ_MODE_TRIG_EDGE) { cfg = 0x02U; } else { + cfg = 0x00U; status = -1; } @@ -156,15 +156,16 @@ val = mode & IRQ_MODE_DOMAIN_Msk; if (val == IRQ_MODE_DOMAIN_NONSECURE) { - secure = 0; + secure = 0U; } else { // Check security extensions support val = GIC_DistributorInfo() & (1UL << 10U); if (val != 0U) { // Security extensions are supported - secure = 1; + secure = 1U; } else { + secure = 0U; status = -1; } } @@ -173,7 +174,7 @@ val = mode & IRQ_MODE_CPU_Msk; if (val == IRQ_MODE_CPU_ALL) { - cpu = 0xFF; + cpu = 0xFFU; } else { cpu = val >> IRQ_MODE_CPU_Pos; } diff --git a/cmsis/TARGET_CORTEX_M/cmsis_armcc.h b/cmsis/TARGET_CORTEX_M/cmsis_armcc.h index c2ef0a5..093d35b 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_armcc.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_armcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (ARM compiler V5) header file - * @version V5.0.2 - * @date 13. February 2017 + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" #endif /* CMSIS compiler control architecture macros */ @@ -58,6 +58,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif @@ -445,9 +448,10 @@ __schedule_barrier();\ } while (0U) + /** \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ @@ -456,12 +460,12 @@ /** \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint16_t __REV16(uint16_t value) +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr @@ -470,8 +474,8 @@ /** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ @@ -736,12 +740,16 @@ */ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) { + if ((sat >= 1U) && (sat <= 32U)) + { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; - if (val > max) { + if (val > max) + { return max; - } else if (val < min) { + } + else if (val < min) + { return min; } } @@ -757,11 +765,15 @@ */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) { + if (sat <= 31U) + { const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) { + if (val > (int32_t)max) + { return max; - } else if (val < 0) { + } + else if (val < 0) + { return 0U; } } diff --git a/cmsis/TARGET_CORTEX_M/cmsis_armclang.h b/cmsis/TARGET_CORTEX_M/cmsis_armclang.h index f13bb17..5c4c20e 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_armclang.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_armclang.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armclang.h - * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file - * @version V5.0.3 - * @date 27. March 2017 + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -27,8 +27,10 @@ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H +#pragma clang system_header /* treat file as system include file */ + #ifndef __ARM_COMPAT_H -#include /* Compatibility header for ARM Compiler 5 intrinsics */ +#include /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ @@ -41,8 +43,11 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) + #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) @@ -134,7 +139,7 @@ \details Returns the content of the Control Register. \return Control Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; @@ -149,7 +154,7 @@ \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; @@ -164,7 +169,7 @@ \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } @@ -176,7 +181,7 @@ \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } @@ -188,7 +193,7 @@ \details Returns the content of the IPSR Register. \return IPSR Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; @@ -202,7 +207,7 @@ \details Returns the content of the APSR Register. \return APSR Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +__STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; @@ -216,7 +221,7 @@ \details Returns the content of the xPSR Register. \return xPSR Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; @@ -230,7 +235,7 @@ \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +__STATIC_FORCEINLINE uint32_t __get_PSP(void) { register uint32_t result; @@ -245,7 +250,7 @@ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { register uint32_t result; @@ -260,7 +265,7 @@ \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } @@ -272,7 +277,7 @@ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } @@ -284,7 +289,7 @@ \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +__STATIC_FORCEINLINE uint32_t __get_MSP(void) { register uint32_t result; @@ -299,7 +304,7 @@ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { register uint32_t result; @@ -314,7 +319,7 @@ \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } @@ -326,7 +331,7 @@ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } @@ -339,7 +344,7 @@ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { register uint32_t result; @@ -353,7 +358,7 @@ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack) +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } @@ -365,7 +370,7 @@ \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; @@ -380,7 +385,7 @@ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; @@ -395,7 +400,7 @@ \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } @@ -407,7 +412,7 @@ \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } @@ -438,7 +443,7 @@ \details Returns the current value of the Base Priority register. \return Base Priority register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; @@ -453,7 +458,7 @@ \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; @@ -468,7 +473,7 @@ \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } @@ -480,7 +485,7 @@ \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } @@ -493,7 +498,7 @@ or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } @@ -504,7 +509,7 @@ \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; @@ -519,7 +524,7 @@ \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; @@ -534,7 +539,7 @@ \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } @@ -546,7 +551,7 @@ \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } @@ -562,113 +567,175 @@ /** \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else register uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); + return result; +#endif } - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else register uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); + return result; +#endif } #endif /** \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif } -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif } #endif /** \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else register uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); + return result; +#endif } -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else register uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); + return result; +#endif } #endif /** \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif } -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif } #endif @@ -782,36 +849,29 @@ /** \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ -#define __REV (uint32_t)__builtin_bswap32 +#define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ -#define __REV16 (uint16_t)__builtin_bswap16 +#define __REV16(value) __ROR(__REV(value), 16) /** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value) -{ - int16_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - - return result; -} +#define __REVSH(value) (int16_t)__builtin_bswap16(value) /** @@ -821,8 +881,13 @@ \param [in] op2 Number of Bits to rotate \return Rotated value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } return (op1 >> op2) | (op1 << (32U - op2)); } @@ -843,7 +908,7 @@ \param [in] value Value to reverse \return Reversed value */ -#define __RBIT (uint32_t)__builtin_arm_rbit +#define __RBIT __builtin_arm_rbit /** \brief Count leading zeros @@ -851,7 +916,7 @@ \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ __builtin_clz +#define __CLZ (uint8_t)__builtin_clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -961,7 +1026,7 @@ \param [in] value Value to rotate \return Rotated value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; @@ -976,7 +1041,7 @@ \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; @@ -991,7 +1056,7 @@ \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; @@ -1006,7 +1071,7 @@ \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; @@ -1021,7 +1086,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1033,7 +1098,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1045,7 +1110,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } @@ -1061,14 +1126,18 @@ \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) { + if ((sat >= 1U) && (sat <= 32U)) + { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; - if (val > max) { + if (val > max) + { return max; - } else if (val < min) { + } + else if (val < min) + { return min; } } @@ -1082,13 +1151,17 @@ \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) { + if (sat <= 31U) + { const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) { + if (val > (int32_t)max) + { return max; - } else if (val < 0) { + } + else if (val < 0) + { return 0U; } } @@ -1108,7 +1181,7 @@ \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; @@ -1123,7 +1196,7 @@ \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; @@ -1138,7 +1211,7 @@ \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; @@ -1153,7 +1226,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1165,7 +1238,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1177,7 +1250,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1256,7 +1329,7 @@ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1264,7 +1337,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1272,7 +1345,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1280,7 +1353,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1288,7 +1361,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1296,7 +1369,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1305,7 +1378,7 @@ } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1313,7 +1386,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1321,7 +1394,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1329,7 +1402,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1337,7 +1410,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1345,7 +1418,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1354,7 +1427,7 @@ } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1362,7 +1435,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1370,7 +1443,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1378,7 +1451,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1386,7 +1459,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1394,7 +1467,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1402,7 +1475,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1410,7 +1483,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1418,7 +1491,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1426,7 +1499,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1434,7 +1507,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1442,7 +1515,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1450,7 +1523,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1458,7 +1531,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1466,7 +1539,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1474,7 +1547,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1482,7 +1555,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1490,7 +1563,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1498,7 +1571,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1506,7 +1579,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1514,7 +1587,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1522,7 +1595,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1530,7 +1603,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1538,7 +1611,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1546,7 +1619,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1554,7 +1627,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1576,7 +1649,7 @@ __RES; \ }) -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; @@ -1584,7 +1657,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1592,7 +1665,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; @@ -1600,7 +1673,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1608,7 +1681,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1616,7 +1689,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1624,7 +1697,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1632,7 +1705,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1640,7 +1713,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1657,7 +1730,7 @@ return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1674,7 +1747,7 @@ return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1682,7 +1755,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1690,7 +1763,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1698,7 +1771,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1706,7 +1779,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1723,7 +1796,7 @@ return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1740,7 +1813,7 @@ return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1748,7 +1821,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; @@ -1756,7 +1829,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; @@ -1789,7 +1862,7 @@ #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; diff --git a/cmsis/TARGET_CORTEX_M/cmsis_compiler.h b/cmsis/TARGET_CORTEX_M/cmsis_compiler.h index 5a9a222..94212eb 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_compiler.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_compiler.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file - * @version V5.0.2 - * @date 13. February 2017 + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -28,14 +28,14 @@ #include /* - * ARM Compiler 4/5 + * Arm Compiler 4/5 */ #if defined ( __CC_ARM ) #include "cmsis_armcc.h" /* - * ARM Compiler 6 (armclang) + * Arm Compiler 6 (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #include "cmsis_armclang.h" @@ -54,9 +54,9 @@ #elif defined ( __ICCARM__ ) #include - + /* - * TI ARM Compiler + * TI Arm Compiler */ #elif defined ( __TI_ARM__ ) #include @@ -70,6 +70,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif @@ -136,6 +139,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif @@ -198,6 +204,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif #ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN diff --git a/cmsis/TARGET_CORTEX_M/cmsis_gcc.h b/cmsis/TARGET_CORTEX_M/cmsis_gcc.h index 4aef7af..5d0f07e 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_gcc.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_gcc.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file - * @version V5.0.2 - * @date 13. February 2017 + * @version V5.0.3 + * @date 16. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -46,8 +46,11 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) + #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) @@ -123,7 +126,7 @@ \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +__STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } @@ -134,7 +137,7 @@ \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +__STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } @@ -145,7 +148,7 @@ \details Returns the content of the Control Register. \return Control Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; @@ -160,7 +163,7 @@ \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; @@ -175,7 +178,7 @@ \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } @@ -187,7 +190,7 @@ \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } @@ -199,7 +202,7 @@ \details Returns the content of the IPSR Register. \return IPSR Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; @@ -213,7 +216,7 @@ \details Returns the content of the APSR Register. \return APSR Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +__STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; @@ -227,7 +230,7 @@ \details Returns the content of the xPSR Register. \return xPSR Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; @@ -241,7 +244,7 @@ \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +__STATIC_FORCEINLINE uint32_t __get_PSP(void) { register uint32_t result; @@ -256,7 +259,7 @@ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { register uint32_t result; @@ -271,7 +274,7 @@ \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } @@ -283,7 +286,7 @@ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } @@ -295,7 +298,7 @@ \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +__STATIC_FORCEINLINE uint32_t __get_MSP(void) { register uint32_t result; @@ -310,7 +313,7 @@ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { register uint32_t result; @@ -325,7 +328,7 @@ \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } @@ -337,7 +340,7 @@ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } @@ -350,7 +353,7 @@ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { register uint32_t result; @@ -364,7 +367,7 @@ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack) +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } @@ -376,11 +379,11 @@ \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; - __ASM volatile ("MRS %0, primask" : "=r" (result) ); + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); return(result); } @@ -391,11 +394,11 @@ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); return(result); } #endif @@ -406,7 +409,7 @@ \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } @@ -418,7 +421,7 @@ \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } @@ -433,7 +436,7 @@ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +__STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } @@ -444,7 +447,7 @@ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +__STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } @@ -455,7 +458,7 @@ \details Returns the current value of the Base Priority register. \return Base Priority register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; @@ -470,7 +473,7 @@ \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; @@ -485,7 +488,7 @@ \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } @@ -497,7 +500,7 @@ \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } @@ -510,7 +513,7 @@ or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } @@ -521,7 +524,7 @@ \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; @@ -536,7 +539,7 @@ \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; @@ -551,7 +554,7 @@ \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } @@ -563,7 +566,7 @@ \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } @@ -579,113 +582,175 @@ /** \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else register uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); + return result; +#endif } - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else register uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); + return result; +#endif } #endif /** \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif } -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif } #endif /** \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else register uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); + return result; +#endif } -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else register uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); + return result; +#endif } #endif /** \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif } -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif } #endif @@ -701,7 +766,7 @@ \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) @@ -725,7 +790,7 @@ \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) @@ -771,21 +836,13 @@ \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ -//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -//{ -// __ASM volatile ("nop"); -//} -#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ +#define __NOP() __ASM volatile ("nop") /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -//{ -// __ASM volatile ("wfi"); -//} -#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ +#define __WFI() __ASM volatile ("wfi") /** @@ -793,22 +850,14 @@ \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -//{ -// __ASM volatile ("wfe"); -//} -#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ +#define __WFE() __ASM volatile ("wfe") /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -//{ -// __ASM volatile ("sev"); -//} -#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ +#define __SEV() __ASM volatile ("sev") /** @@ -817,7 +866,7 @@ so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +__STATIC_FORCEINLINE void __ISB(void) { __ASM volatile ("isb 0xF":::"memory"); } @@ -828,7 +877,7 @@ \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +__STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); } @@ -839,7 +888,7 @@ \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +__STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); } @@ -847,11 +896,11 @@ /** \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); @@ -859,33 +908,33 @@ uint32_t result; __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + return result; #endif } /** \brief Reverse byte order (16 bit) - \details Reverses the byte order in unsigned short value. + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __REV16(uint16_t value) +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { - uint16_t result; + uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + return result; } /** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value) +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (int16_t)__builtin_bswap16(value); @@ -905,8 +954,13 @@ \param [in] op2 Number of Bits to rotate \return Rotated value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } return (op1 >> op2) | (op1 << (32U - op2)); } @@ -927,7 +981,7 @@ \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; @@ -957,7 +1011,7 @@ \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ __builtin_clz +#define __CLZ (uint8_t)__builtin_clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -970,7 +1024,7 @@ \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; @@ -992,7 +1046,7 @@ \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; @@ -1014,7 +1068,7 @@ \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; @@ -1031,7 +1085,7 @@ \return 0 Function succeeded \return 1 Function failed */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; @@ -1048,7 +1102,7 @@ \return 0 Function succeeded \return 1 Function failed */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; @@ -1065,7 +1119,7 @@ \return 0 Function succeeded \return 1 Function failed */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; @@ -1078,7 +1132,7 @@ \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +__STATIC_FORCEINLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } @@ -1131,7 +1185,7 @@ \param [in] value Value to rotate \return Rotated value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; @@ -1146,7 +1200,7 @@ \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; @@ -1168,7 +1222,7 @@ \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; @@ -1190,7 +1244,7 @@ \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; @@ -1205,7 +1259,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1217,7 +1271,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1229,7 +1283,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } @@ -1245,14 +1299,18 @@ \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) { + if ((sat >= 1U) && (sat <= 32U)) + { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; - if (val > max) { + if (val > max) + { return max; - } else if (val < min) { + } + else if (val < min) + { return min; } } @@ -1266,13 +1324,17 @@ \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) { + if (sat <= 31U) + { const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) { + if (val > (int32_t)max) + { return max; - } else if (val < 0) { + } + else if (val < 0) + { return 0U; } } @@ -1292,7 +1354,7 @@ \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; @@ -1307,7 +1369,7 @@ \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; @@ -1322,7 +1384,7 @@ \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; @@ -1337,7 +1399,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1349,7 +1411,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1361,7 +1423,7 @@ \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1373,7 +1435,7 @@ \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t result; @@ -1388,7 +1450,7 @@ \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t result; @@ -1403,7 +1465,7 @@ \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t result; @@ -1420,7 +1482,7 @@ \return 0 Function succeeded \return 1 Function failed */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t result; @@ -1437,7 +1499,7 @@ \return 0 Function succeeded \return 1 Function failed */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t result; @@ -1454,7 +1516,7 @@ \return 0 Function succeeded \return 1 Function failed */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t result; @@ -1474,9 +1536,9 @@ @{ */ -#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1484,7 +1546,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1492,7 +1554,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1500,7 +1562,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1508,7 +1570,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1516,7 +1578,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1525,7 +1587,7 @@ } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1533,7 +1595,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1541,7 +1603,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1549,7 +1611,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1557,7 +1619,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1565,7 +1627,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1574,7 +1636,7 @@ } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1582,7 +1644,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1590,7 +1652,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1598,7 +1660,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1606,7 +1668,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1614,7 +1676,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1622,7 +1684,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1630,7 +1692,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1638,7 +1700,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1646,7 +1708,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1654,7 +1716,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1662,7 +1724,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1670,7 +1732,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1678,7 +1740,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1686,7 +1748,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1694,7 +1756,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1702,7 +1764,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1710,7 +1772,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1718,7 +1780,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1726,7 +1788,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1734,7 +1796,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1742,7 +1804,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1750,7 +1812,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1758,7 +1820,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1766,7 +1828,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1774,7 +1836,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1796,7 +1858,7 @@ __RES; \ }) -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; @@ -1804,7 +1866,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1812,7 +1874,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; @@ -1820,7 +1882,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1828,7 +1890,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1836,7 +1898,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1844,7 +1906,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1852,7 +1914,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1860,7 +1922,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1877,7 +1939,7 @@ return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1894,7 +1956,7 @@ return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1902,7 +1964,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1910,7 +1972,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1918,7 +1980,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1926,7 +1988,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1943,7 +2005,7 @@ return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1960,7 +2022,7 @@ return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1968,7 +2030,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; @@ -1976,7 +2038,7 @@ return(result); } -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; @@ -2009,7 +2071,7 @@ #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; diff --git a/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h b/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h index 0161285..edcaee3 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR compiler) header file - * @version V5.0.3 - * @date 29. August 2017 + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 ******************************************************************************/ //------------------------------------------------------------------------------ // -// Copyright (c) 2017 IAR Systems +// Copyright (c) 2017-2018 IAR Systems // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. @@ -116,7 +116,7 @@ #ifndef __NO_RETURN #if __ICCARM_V8 - #define __NO_RETURN __attribute__((noreturn)) + #define __NO_RETURN __attribute__((__noreturn__)) #else #define __NO_RETURN _Pragma("object_attribute=__noreturn") #endif @@ -150,18 +150,26 @@ #endif #ifndef __RESTRICT - #define __RESTRICT restrict + #define __RESTRICT restrict #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE #endif #ifndef __UNALIGNED_UINT16_READ #pragma language=save #pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) { +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ return *(__packed uint16_t*)(ptr); } #pragma language=restore @@ -172,7 +180,8 @@ #ifndef __UNALIGNED_UINT16_WRITE #pragma language=save #pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ *(__packed uint16_t*)(ptr) = val;; } #pragma language=restore @@ -182,7 +191,8 @@ #ifndef __UNALIGNED_UINT32_READ #pragma language=save #pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) { +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ return *(__packed uint32_t*)(ptr); } #pragma language=restore @@ -192,7 +202,8 @@ #ifndef __UNALIGNED_UINT32_WRITE #pragma language=save #pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ *(__packed uint32_t*)(ptr) = val;; } #pragma language=restore @@ -252,8 +263,8 @@ #define __disable_irq __iar_builtin_disable_interrupt #define __enable_fault_irq __iar_builtin_enable_fiq #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr #define __get_APSR() (__arm_rsr("APSR")) @@ -272,10 +283,24 @@ #define __get_IPSR() (__arm_rsr("IPSR")) #define __get_MSP() (__arm_rsr("MSP")) - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif #define __get_PRIMASK() (__arm_rsr("PRIMASK")) #define __get_PSP() (__arm_rsr("PSP")) - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + #define __get_xPSR() (__arm_rsr("xPSR")) #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) @@ -283,10 +308,23 @@ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) @@ -307,17 +345,14 @@ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - #define __NOP __iar_builtin_no_operation + #define __NOP __iar_builtin_no_operation - __IAR_FT uint8_t __CLZ(uint32_t val) { - return __iar_builtin_CLZ(val); - } + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB #define __LDREXB __iar_builtin_LDREXB #define __LDREXH __iar_builtin_LDREXH @@ -327,8 +362,9 @@ #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 - __IAR_FT int32_t __REVSH(int32_t val) { - return __iar_builtin_REVSH((int16_t)val); + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); } #define __ROR __iar_builtin_ROR @@ -434,6 +470,10 @@ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active #endif + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + #include #if __IAR_M0_FAMILY @@ -444,22 +484,24 @@ #undef __RBIT #undef __get_APSR - __STATIC_INLINE uint8_t __CLZ(uint32_t data) { - if (data == 0u) { return 32u; } + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } - uint32_t count = 0; - uint32_t mask = 0x80000000; + uint32_t count = 0U; + uint32_t mask = 0x80000000U; - while ((data & mask) == 0) + while ((data & mask) == 0U) { - count += 1u; - mask = mask >> 1u; + count += 1U; + mask = mask >> 1U; } - return (count); + return count; } - __STATIC_INLINE uint32_t __RBIT(uint32_t v) { - uint8_t sc = 31; + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; uint32_t r = v; for (v >>= 1U; v; v >>= 1U) { @@ -470,7 +512,8 @@ return (r << sc); } - __STATIC_INLINE uint32_t __get_APSR(void) { + __STATIC_INLINE uint32_t __get_APSR(void) + { uint32_t res; __asm("MRS %0,APSR" : "=r" (res)); return res; @@ -497,11 +540,13 @@ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { return __LDREX((unsigned long *)ptr); } - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { return __STREX(value, (unsigned long *)ptr); } #endif @@ -510,115 +555,184 @@ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ #if (__CORTEX_M >= 0x03) - __IAR_FT uint32_t __RRX(uint32_t value) { + __IAR_FT uint32_t __RRX(uint32_t value) + { uint32_t result; __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); return(result); } - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) { + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); } - #define __enable_fault_irq __enable_fiq + #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #endif /* (__CORTEX_M >= 0x03) */ - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); } #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) { + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { uint32_t res; __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_PSP_NS(void) { + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { uint32_t res; __asm volatile("MRS %0,PSP_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) { + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { __asm volatile("MSR PSP_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_MSP_NS(void) { + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { uint32_t res; __asm volatile("MRS %0,MSP_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) { + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { __asm volatile("MSR MSP_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_SP_NS(void) { + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { uint32_t res; __asm volatile("MRS %0,SP_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) { + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { __asm volatile("MSR SP_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) { + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { uint32_t res; __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) { + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { uint32_t res; __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) { + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { uint32_t res; __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { uint32_t res; __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) { + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { uint32_t res; __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); } @@ -629,25 +743,35 @@ #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) #if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) { + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; - if (val > max) { + if (val > max) + { return max; - } else if (val < min) { + } + else if (val < min) + { return min; } } return val; } - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) { + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) { + if (val > (int32_t)max) + { return max; - } else if (val < 0) { + } + else if (val < 0) + { return 0U; } } @@ -657,33 +781,39 @@ #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) { + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { uint32_t res; __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint8_t)res); } - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) { + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { uint32_t res; __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint16_t)res); } - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) { + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { uint32_t res; __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return res; } - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); } @@ -693,67 +823,79 @@ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { uint32_t res; __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint8_t)res); } - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { uint32_t res; __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint16_t)res); } - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { uint32_t res; __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return res; } - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); } - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); } - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); } - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { uint32_t res; __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint8_t)res); } - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { uint32_t res; __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint16_t)res); } - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { uint32_t res; __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return res; } - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { uint32_t res; __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); return res; } - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { uint32_t res; __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); return res; } - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { uint32_t res; __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); return res; diff --git a/cmsis/TARGET_CORTEX_M/cmsis_version.h b/cmsis/TARGET_CORTEX_M/cmsis_version.h index d458a6c..660f612 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_version.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_version.h @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -33,7 +33,7 @@ /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ #endif diff --git a/cmsis/TARGET_CORTEX_M/core_armv8mbl.h b/cmsis/TARGET_CORTEX_M/core_armv8mbl.h index 917b16e..47a3989 100644 --- a/cmsis/TARGET_CORTEX_M/core_armv8mbl.h +++ b/cmsis/TARGET_CORTEX_M/core_armv8mbl.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_armv8mbl.h - * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 09. August 2017 + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -1239,8 +1239,8 @@ #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */ +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ @@ -1266,7 +1266,7 @@ #define NVIC_USER_IRQ_OFFSET 16 -/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) @@ -1283,7 +1283,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1300,7 +1300,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1319,7 +1319,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -1338,7 +1338,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1357,7 +1357,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1372,7 +1372,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1389,7 +1389,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1411,7 +1411,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1432,8 +1432,8 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1454,8 +1454,8 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1581,7 +1581,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1598,7 +1598,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1617,7 +1617,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1634,7 +1634,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1653,7 +1653,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1668,7 +1668,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1685,7 +1685,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { diff --git a/cmsis/TARGET_CORTEX_M/core_armv8mml.h b/cmsis/TARGET_CORTEX_M/core_armv8mml.h index afea758..0951a1f 100644 --- a/cmsis/TARGET_CORTEX_M/core_armv8mml.h +++ b/cmsis/TARGET_CORTEX_M/core_armv8mml.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_armv8mml.h - * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 09. August 2017 + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -62,7 +62,7 @@ #include "cmsis_version.h" -/* CMSIS ARMv8MML definitions */ +/* CMSIS Armv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ @@ -2181,7 +2181,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2198,7 +2198,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2217,7 +2217,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -2236,7 +2236,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2255,7 +2255,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2270,7 +2270,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2287,7 +2287,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2309,7 +2309,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2330,8 +2330,8 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2352,8 +2352,8 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2376,11 +2376,11 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } @@ -2399,11 +2399,11 @@ if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } @@ -2555,7 +2555,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2572,7 +2572,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2591,7 +2591,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2608,7 +2608,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2627,7 +2627,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2642,7 +2642,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2659,7 +2659,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2681,11 +2681,11 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } @@ -2703,11 +2703,11 @@ if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm0.h b/cmsis/TARGET_CORTEX_M/core_cm0.h index 2f63b68..a3f1b9a 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm0.h +++ b/cmsis/TARGET_CORTEX_M/core_cm0.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 + * @version V5.0.3 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -599,7 +599,7 @@ #define NVIC_USER_IRQ_OFFSET 16 -/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) @@ -616,7 +616,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -633,7 +633,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -652,7 +652,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -671,7 +671,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -690,7 +690,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -705,7 +705,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } diff --git a/cmsis/TARGET_CORTEX_M/core_cm0plus.h b/cmsis/TARGET_CORTEX_M/core_cm0plus.h index 84f3281..f8f30c3 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm0plus.h +++ b/cmsis/TARGET_CORTEX_M/core_cm0plus.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 09. August 2017 + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -717,7 +717,7 @@ #define NVIC_USER_IRQ_OFFSET 16 -/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) @@ -734,7 +734,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -751,7 +751,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -770,7 +770,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -789,7 +789,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -808,7 +808,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -823,7 +823,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } diff --git a/cmsis/TARGET_CORTEX_M/core_cm23.h b/cmsis/TARGET_CORTEX_M/core_cm23.h index 1852efb..7d1d478 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm23.h +++ b/cmsis/TARGET_CORTEX_M/core_cm23.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 09. August 2017 + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -748,8 +748,11 @@ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1266,7 +1269,7 @@ #define NVIC_USER_IRQ_OFFSET 16 -/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) @@ -1283,7 +1286,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1300,7 +1303,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1319,7 +1322,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -1338,7 +1341,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1357,7 +1360,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1372,7 +1375,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1389,7 +1392,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1411,7 +1414,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1432,8 +1435,8 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1454,8 +1457,8 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1581,7 +1584,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1598,7 +1601,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1617,7 +1620,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1634,7 +1637,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1653,7 +1656,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1668,7 +1671,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1685,7 +1688,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { diff --git a/cmsis/TARGET_CORTEX_M/core_cm3.h b/cmsis/TARGET_CORTEX_M/core_cm3.h index 3809f71..a2c0d08 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm3.h +++ b/cmsis/TARGET_CORTEX_M/core_cm3.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 09. August 2017 + * @version V5.0.5 + * @date 08. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -781,7 +781,7 @@ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ @@ -1022,8 +1022,11 @@ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1475,7 +1478,7 @@ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -1501,7 +1504,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1518,7 +1521,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1537,7 +1540,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -1556,7 +1559,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1575,7 +1578,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1590,7 +1593,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1607,7 +1610,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1629,11 +1632,11 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } @@ -1652,11 +1655,11 @@ if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } diff --git a/cmsis/TARGET_CORTEX_M/core_cm33.h b/cmsis/TARGET_CORTEX_M/core_cm33.h index ef0b7c7..b1efbca 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm33.h +++ b/cmsis/TARGET_CORTEX_M/core_cm33.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 09. August 2017 + * @version V5.0.5 + * @date 08. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -74,7 +74,7 @@ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP + #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -85,8 +85,8 @@ #define __FPU_USED 0U #endif - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" @@ -97,7 +97,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined (__ARM_PCS_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -108,8 +108,8 @@ #define __FPU_USED 0U #endif - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" @@ -131,8 +131,8 @@ #define __FPU_USED 0U #endif - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" @@ -143,7 +143,7 @@ #endif #elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ + #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -154,8 +154,8 @@ #define __FPU_USED 0U #endif - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" @@ -166,7 +166,7 @@ #endif #elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ + #if defined (__TI_VFP_SUPPORT__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -178,7 +178,7 @@ #endif #elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ + #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -1127,7 +1127,7 @@ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ @@ -1410,8 +1410,11 @@ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -2155,7 +2158,7 @@ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -2181,7 +2184,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2198,7 +2201,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2217,7 +2220,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -2236,7 +2239,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2255,7 +2258,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2270,7 +2273,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2287,7 +2290,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2309,7 +2312,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2330,8 +2333,8 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2352,8 +2355,8 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2376,11 +2379,11 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } @@ -2399,11 +2402,11 @@ if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } @@ -2525,11 +2528,11 @@ uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } @@ -2555,7 +2558,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2572,7 +2575,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2591,7 +2594,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2608,7 +2611,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2627,7 +2630,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2642,7 +2645,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -2659,7 +2662,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2681,11 +2684,11 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } @@ -2703,11 +2706,11 @@ if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm4.h b/cmsis/TARGET_CORTEX_M/core_cm4.h index 1c12d4e..a11a381 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm4.h +++ b/cmsis/TARGET_CORTEX_M/core_cm4.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 09. August 2017 + * @version V5.0.5 + * @date 08. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -846,7 +846,7 @@ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ @@ -1087,8 +1087,11 @@ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1649,7 +1652,7 @@ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -1675,7 +1678,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1692,7 +1695,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1711,7 +1714,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -1730,7 +1733,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1749,7 +1752,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1764,7 +1767,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1781,7 +1784,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1803,11 +1806,11 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } @@ -1826,11 +1829,11 @@ if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } diff --git a/cmsis/TARGET_CORTEX_M/core_cm7.h b/cmsis/TARGET_CORTEX_M/core_cm7.h index 65fa60fc..1fe53bf 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm7.h +++ b/cmsis/TARGET_CORTEX_M/core_cm7.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 09. August 2017 + * @version V5.0.5 + * @date 08. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -1048,7 +1048,7 @@ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ @@ -1292,8 +1292,11 @@ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1857,7 +1860,7 @@ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -1883,7 +1886,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1900,7 +1903,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1919,7 +1922,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -1938,7 +1941,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1957,7 +1960,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1972,7 +1975,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1989,7 +1992,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -2011,11 +2014,11 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } @@ -2034,11 +2037,11 @@ if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } diff --git a/cmsis/TARGET_CORTEX_M/core_sc000.h b/cmsis/TARGET_CORTEX_M/core_sc000.h index bd26eaa..9aab5e5 100644 --- a/cmsis/TARGET_CORTEX_M/core_sc000.h +++ b/cmsis/TARGET_CORTEX_M/core_sc000.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 + * @version V5.0.3 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -727,7 +727,7 @@ #define NVIC_USER_IRQ_OFFSET 16 -/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) @@ -744,7 +744,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -761,7 +761,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -780,7 +780,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -799,7 +799,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -818,7 +818,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -833,7 +833,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } diff --git a/cmsis/TARGET_CORTEX_M/core_sc300.h b/cmsis/TARGET_CORTEX_M/core_sc300.h index 780372a3..a569ef2 100644 --- a/cmsis/TARGET_CORTEX_M/core_sc300.h +++ b/cmsis/TARGET_CORTEX_M/core_sc300.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 + * @version V5.0.3 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -1481,7 +1481,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1498,7 +1498,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1517,7 +1517,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -1536,7 +1536,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1555,7 +1555,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1570,7 +1570,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -1587,7 +1587,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -1609,11 +1609,11 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } @@ -1632,11 +1632,11 @@ if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } diff --git a/cmsis/TARGET_CORTEX_M/mbed_tz_context.c b/cmsis/TARGET_CORTEX_M/mbed_tz_context.c index 434422c..66acb44 100644 --- a/cmsis/TARGET_CORTEX_M/mbed_tz_context.c +++ b/cmsis/TARGET_CORTEX_M/mbed_tz_context.c @@ -1,5 +1,11 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ /* - * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/cmsis/TARGET_CORTEX_M/mpu_armv7.h b/cmsis/TARGET_CORTEX_M/mpu_armv7.h index 44d0930..aa180c9 100644 --- a/cmsis/TARGET_CORTEX_M/mpu_armv7.h +++ b/cmsis/TARGET_CORTEX_M/mpu_armv7.h @@ -1,11 +1,11 @@ /****************************************************************************** * @file mpu_armv7.h - * @brief CMSIS MPU API for ARMv7 MPU - * @version V5.0.3 - * @date 09. August 2017 + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2017 ARM Limited. All rights reserved. + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,6 +22,12 @@ * limitations under the License. */ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H @@ -72,7 +78,7 @@ (MPU_RBAR_VALID_Msk)) /** -* MPU Region Attribut and Size Register Value +* MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. @@ -98,7 +104,7 @@ /** * Struct for a single MPU Region */ -typedef struct _ARM_MPU_Region_t { +typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; @@ -179,13 +185,13 @@ */ __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { - static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt > MPU_TYPE_RALIASES) { + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - ARM_MPU_Load(table+MPU_TYPE_RALIASES, cnt-MPU_TYPE_RALIASES); - } else { - orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); } #endif diff --git a/cmsis/TARGET_CORTEX_M/mpu_armv8.h b/cmsis/TARGET_CORTEX_M/mpu_armv8.h index 69452e0..0ccfc74 100644 --- a/cmsis/TARGET_CORTEX_M/mpu_armv8.h +++ b/cmsis/TARGET_CORTEX_M/mpu_armv8.h @@ -1,11 +1,11 @@ /****************************************************************************** * @file mpu_armv8.h - * @brief CMSIS MPU API for ARMv8 MPU - * @version V5.0.3 - * @date 09. August 2017 + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2017 ARM Limited. All rights reserved. + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -21,7 +21,13 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + #ifndef ARM_MPU_ARMV8_H #define ARM_MPU_ARMV8_H @@ -98,7 +104,7 @@ /** * Struct for a single MPU Region */ -typedef struct _ARM_MPU_Region_t { +typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; @@ -166,11 +172,11 @@ const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; - if (reg >= (sizeof(MPU->MAIR) / sizeof(MPU->MAIR[0]))) { + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } - MPU->MAIR[reg] = ((MPU->MAIR[reg] & ~mask) | ((attr << pos) & mask)); + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } /** Set the memory attribute encoding. @@ -199,8 +205,8 @@ */ __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) { - MPU->RNR = rnr; - MPU->RLAR = 0U; + mpu->RNR = rnr; + mpu->RLAR = 0U; } /** Clear and disable the given MPU region. @@ -229,9 +235,9 @@ */ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RLAR = rlar; + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; } /** Configure the given MPU region. @@ -278,7 +284,7 @@ */ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { - static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { mpu->RNR = rnr; orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); @@ -287,13 +293,17 @@ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; mpu->RNR = rnrBase; - if ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - ARM_MPU_LoadEx(mpu, rnr + c, table + c, cnt - c); - } else { - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } diff --git a/cmsis/TARGET_CORTEX_M/tz_context.h b/cmsis/TARGET_CORTEX_M/tz_context.h index 0784d26..0d09749 100644 --- a/cmsis/TARGET_CORTEX_M/tz_context.h +++ b/cmsis/TARGET_CORTEX_M/tz_context.h @@ -1,5 +1,11 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ /* - * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,19 +20,14 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - * - * ---------------------------------------------------------------------------- - * - * $Date: 21. September 2016 - * $Revision: V1.0 - * - * Project: TrustZone for ARMv8-M - * Title: Context Management for ARMv8-M TrustZone - * - * Version 1.0 - * Initial Release - *---------------------------------------------------------------------------*/ - + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H diff --git a/cmsis/mbed_cmsis_conf.h b/cmsis/mbed_cmsis_conf.h new file mode 100644 index 0000000..d5ba37c --- /dev/null +++ b/cmsis/mbed_cmsis_conf.h @@ -0,0 +1,35 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2012 ARM Limited + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_CMSIS_CONF_H +#define MBED_CMSIS_CONF_H + +#ifndef MBED_CONF_TZ_PROCESS_STACK_SIZE +#define MBED_CONF_TZ_PROCESS_STACK_SIZE 512 +#endif +#ifndef MBED_CONF_TZ_PROCESS_STACK_SLOTS +#define MBED_CONF_TZ_PROCESS_STACK_SLOTS 8 +#endif + +#define TZ_PROCESS_STACK_SLOTS MBED_CONF_TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SIZE MBED_CONF_TZ_PROCESS_STACK_SIZE + +#endif /* MBED_CMSIS_CONF_H */ diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/generic/wsf_types.h b/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/generic/wsf_types.h index 0347086..af0dcfa 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/generic/wsf_types.h +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/generic/wsf_types.h @@ -26,22 +26,6 @@ #define WSF_TYPES_H /************************************************************************************************** - Macros -**************************************************************************************************/ - -#ifndef NULL -#define NULL 0 -#endif - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -/************************************************************************************************** Data Types **************************************************************************************************/ @@ -60,7 +44,6 @@ typedef unsigned long long uint64_t; #endif -/* Boolean data type */ -typedef uint8_t bool_t; +#include #endif /* WSF_TYPES_H */ diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_types.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_types.h index 143ec28..5031084 100644 --- a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_types.h +++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_types.h @@ -22,42 +22,6 @@ #ifndef WSF_TYPES_H #define WSF_TYPES_H -/************************************************************************************************** - Macros -**************************************************************************************************/ - -#ifndef NULL -#define NULL 0 -#endif - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -/************************************************************************************************** - Data Types -**************************************************************************************************/ - -/* Integer data types */ -#if ((defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)) && \ - (__ICC8051__ == 0)) || defined(__CC_ARM) || \ - (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ - defined(__IAR_SYSTEMS_ICC__) -#include -#else -typedef signed char int8_t; -typedef unsigned char uint8_t; -typedef signed short int16_t; -typedef unsigned short uint16_t; -typedef signed long int32_t; -typedef unsigned long uint32_t; -#endif - -/* Boolean data type */ -typedef uint8_t bool_t; +#include #endif /* WSF_TYPES_H */ diff --git a/features/FEATURE_UVISOR/uvisor-tests.txt b/features/FEATURE_UVISOR/uvisor-tests.txt index fbf3b0d..94b6724 100644 --- a/features/FEATURE_UVISOR/uvisor-tests.txt +++ b/features/FEATURE_UVISOR/uvisor-tests.txt @@ -1 +1 @@ -70a8b3b546ebfde84cde7f14525a7b754c819e69 +6d61583c3fae7f2b3f96cc5c5ca9b0107b981e6d diff --git a/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c b/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c index 1404d4d..ebdad9e 100644 --- a/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c +++ b/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c @@ -19,7 +19,7 @@ #include "mbed_critical.h" #include "mbed_toolchain.h" -#ifndef __DOMAIN_NS +#ifndef DOMAIN_NS #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include @@ -260,4 +260,4 @@ return obj->target_config->flash_size; } -#endif // #ifndef __DOMAIN_NS +#endif // #ifndef DOMAIN_NS diff --git a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S index 036663c..71607bf 100644 --- a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S +++ b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S @@ -23,8 +23,8 @@ ; */ #ifndef MBED_FAULT_HANDLER_DISABLED -#ifndef __DOMAIN_NS -#define __DOMAIN_NS 1 +#ifndef DOMAIN_NS +#define DOMAIN_NS 1 #endif FAULT_TYPE_HARD_FAULT EQU 0x10 @@ -67,7 +67,7 @@ Fault_Handler PROC EXPORT Fault_Handler -#if (__DOMAIN_NS == 1) +#if (DOMAIN_NS == 1) IMPORT osRtxInfo IMPORT mbed_fault_handler IMPORT mbed_fault_context diff --git a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S index 9493738..2266d07 100644 --- a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S +++ b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S @@ -26,8 +26,8 @@ .file "except.S" .syntax unified -#ifndef __DOMAIN_NS -#define __DOMAIN_NS 1 +#ifndef DOMAIN_NS +#define DOMAIN_NS 1 #endif .equ FAULT_TYPE_HARD_FAULT, 0x10 @@ -103,7 +103,7 @@ .cantunwind Fault_Handler: -#if (__DOMAIN_NS == 1) +#if (DOMAIN_NS == 1) MRS R0,MSP LDR R1,=0x4 MOV R2,LR diff --git a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_IAR/except.S b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_IAR/except.S index 7b85e25..d76fb47 100644 --- a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_IAR/except.S +++ b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_IAR/except.S @@ -31,8 +31,8 @@ #ifndef MBED_FAULT_HANDLER_DISABLED -#ifndef __DOMAIN_NS -#define __DOMAIN_NS 1 +#ifndef DOMAIN_NS +#define DOMAIN_NS 1 #endif PRESERVE8 SECTION .rodata:DATA:NOROOT(2) @@ -62,7 +62,7 @@ Fault_Handler EXPORT Fault_Handler -#if (__DOMAIN_NS == 1) +#if (DOMAIN_NS == 1) IMPORT osRtxInfo IMPORT mbed_fault_context IMPORT mbed_fault_handler diff --git a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp index a4a003f..3d0e6a1 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp +++ b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp @@ -42,7 +42,7 @@ static uint64_t os_timer_data[sizeof(rtos::internal::SysTimer) / 8]; /// Enable System Timer. -int32_t OS_Tick_Enable (void) +void OS_Tick_Enable (void) { // Do not use SingletonPtr since this relies on the RTOS if (NULL == os_timer) { @@ -52,24 +52,18 @@ // set to fire interrupt on next tick os_timer->schedule_tick(); - - return 0; } /// Disable System Timer. -int32_t OS_Tick_Disable (void) +void OS_Tick_Disable (void) { os_timer->cancel_tick(); - - return 0; } /// Acknowledge System Timer IRQ. -int32_t OS_Tick_AcknowledgeIRQ (void) +void OS_Tick_AcknowledgeIRQ (void) { os_timer->schedule_tick(); - - return 0; } /// Get System Timer count. diff --git a/rtos/TARGET_CORTEX/rtx4/cmsis_os.h b/rtos/TARGET_CORTEX/rtx4/cmsis_os.h index af78fd3..59a9e33 100644 --- a/rtos/TARGET_CORTEX/rtx4/cmsis_os.h +++ b/rtos/TARGET_CORTEX/rtx4/cmsis_os.h @@ -17,8 +17,8 @@ * * ---------------------------------------------------------------------- * - * $Date: 9. June 2017 - * $Revision: V2.1.1 + * $Date: 30. October 2017 + * $Revision: V2.1.2 * * Project: CMSIS-RTOS API * Title: cmsis_os.h RTX header file @@ -123,6 +123,9 @@ * - osKernelGetTickCount, osKernelGetTickFreq * Changed Kernel Tick type to uint32_t: * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState *---------------------------------------------------------------------------*/ #ifndef CMSIS_OS_H_ @@ -130,9 +133,9 @@ #define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) -#define osCMSIS_RTX 0x50001U ///< RTOS identification and version (main[31:16].sub[15:0]) +#define osCMSIS_RTX 0x50003U ///< RTOS identification and version (main[31:16].sub[15:0]) -#define osKernelSystemId "RTX V5.1" ///< RTOS identification string +#define osKernelSystemId "RTX V5.3" ///< RTOS identification string #define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available #define osFeature_Signals 31U ///< maximum number of Signal Flags available per thread diff --git a/rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h b/rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h index 2cbb293..295499f 100644 --- a/rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h +++ b/rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h @@ -17,12 +17,15 @@ * * ---------------------------------------------------------------------- * - * $Date: 9. June 2017 - * $Revision: V2.1.1 + * $Date: 30. October 2017 + * $Revision: V2.1.2 * * Project: CMSIS-RTOS2 API * Title: cmsis_os2.h header file * + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState * Version 2.1.1 * Additional functions allowed to be called from Interrupt Service Routines: * - osKernelGetTickCount, osKernelGetTickFreq @@ -45,9 +48,9 @@ #if defined(__CC_ARM) #define __NO_RETURN __declspec(noreturn) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#define __NO_RETURN __attribute__((noreturn)) +#define __NO_RETURN __attribute__((__noreturn__)) #elif defined(__GNUC__) -#define __NO_RETURN __attribute__((noreturn)) +#define __NO_RETURN __attribute__((__noreturn__)) #elif defined(__ICCARM__) #define __NO_RETURN __noreturn #else diff --git a/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h b/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h index 391f729..f78dd5c 100644 --- a/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h +++ b/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file os_tick.h * @brief CMSIS OS Tick header file - * @version V1.0.0 - * @date 05. June 2017 + * @version V1.0.1 + * @date 24. November 2017 ******************************************************************************/ /* * Copyright (c) 2017-2017 ARM Limited. All rights reserved. @@ -40,16 +40,13 @@ int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler); /// Enable OS Tick. -/// \return 0 on success, -1 on error. -int32_t OS_Tick_Enable (void); +void OS_Tick_Enable (void); /// Disable OS Tick. -/// \return 0 on success, -1 on error. -int32_t OS_Tick_Disable (void); +void OS_Tick_Disable (void); /// Acknowledge OS Tick IRQ. -/// \return 0 on success, -1 on error. -int32_t OS_Tick_AcknowledgeIRQ (void); +void OS_Tick_AcknowledgeIRQ (void); /// Get OS Tick IRQ number. /// \return OS Tick IRQ number. diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.c b/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.c index 69c8179..e487101 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -41,7 +41,7 @@ switch (code) { case osRtxErrorStackUnderflow: - // Stack underflow detected for thread (thread_id=object_id) + // Stack overflow detected for thread (thread_id=object_id) break; case osRtxErrorISRQueueOverflow: // ISR Queue overflow detected when inserting object (object_id) @@ -56,6 +56,7 @@ // Standard C/C++ library mutex initialization failed break; default: + // Reserved break; } for (;;) {} diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h b/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h index ea5c50b..4ba2de8 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ * * ----------------------------------------------------------------------------- * - * $Revision: V5.2.0 + * $Revision: V5.3.0 * * Project: CMSIS-RTOS RTX * Title: RTX Configuration definitions @@ -27,9 +27,14 @@ #ifndef RTX_CONFIG_H_ #define RTX_CONFIG_H_ - -#include "mbed_rtx_conf.h" - + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- // System Configuration @@ -64,7 +69,18 @@ // +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + // Event Recording +// Configures events recording. // Memory Management // Enables Memory Management events recording. @@ -122,14 +138,10 @@ // -// ISR FIFO Queue -// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries -// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries -// RTOS Functions called from ISR store requests to this buffer. -// Default: 16 entries -#ifndef OS_ISR_FIFO_QUEUE -#define OS_ISR_FIFO_QUEUE 16 +// Object Memory usage counters +// Enables object memory usage counters. +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 #endif // @@ -169,16 +181,16 @@ // Default Thread Stack size [bytes] <96-1073741824:8> // Defines stack size for threads with zero stack size specified. -// Default: 200 +// Default: 256 #ifndef OS_STACK_SIZE -#define OS_STACK_SIZE 200 +#define OS_STACK_SIZE 256 #endif // Idle Thread Stack size [bytes] <72-1073741824:8> // Defines stack size for Idle thread. -// Default: 200 +// Default: 256 #ifndef OS_IDLE_THREAD_STACK_SIZE -#define OS_IDLE_THREAD_STACK_SIZE 200 +#define OS_IDLE_THREAD_STACK_SIZE 256 #endif // Idle Thread TrustZone Module Identifier @@ -245,9 +257,9 @@ // Timer Thread Stack size [bytes] <0-1073741824:8> // Defines stack size for Timer thread. // May be set to 0 when timers are not used. -// Default: 200 +// Default: 256 #ifndef OS_TIMER_THREAD_STACK_SIZE -#define OS_TIMER_THREAD_STACK_SIZE 200 +#define OS_TIMER_THREAD_STACK_SIZE 256 #endif // Timer Thread TrustZone Module Identifier diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Config/TARGET_CORTEX_A/handlers.c b/rtos/TARGET_CORTEX/rtx5/RTX/Config/TARGET_CORTEX_A/handlers.c index 861ab05..1cc56d7 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Config/TARGET_CORTEX_A/handlers.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Config/TARGET_CORTEX_A/handlers.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,8 +22,9 @@ * * ----------------------------------------------------------------------------- */ +#include "RTE_Components.h" +#include CMSIS_device_header -#include //Fault Status Register (IFSR/DFSR) definitions #define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup @@ -50,8 +51,10 @@ #define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { - uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status - + uint32_t FS = (DFSR & (1U << 10U)) >> 6U | (DFSR & 0x0FU); //Store Fault Status + (void)DFAR; + (void)LR; + switch(FS) { //Synchronous parity errors - retry case FSR_SYNC_PARITY_ERROR: @@ -85,8 +88,10 @@ } void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { - uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status - + uint32_t FS = (IFSR & (1U << 10U)) >> 6U | (IFSR & 0x0FU); //Store Fault Status + (void)IFAR; + (void)LR; + switch(FS) { //Synchronous parity errors - retry case FSR_SYNC_PARITY_ERROR: @@ -119,30 +124,31 @@ //returns amount to decrement lr by //this will be 0 when we have emulated the instruction and want to execute the next instruction //this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2) -//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4) +//this will be 4 when we have performed some maintenance and want to retry the instruction in Arm (state == 4) uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { - const int THUMB = 2; - const int ARM = 4; + const uint32_t THUMB = 2U; + const uint32_t ARM = 4U; + (void)LR; //Lazy VFP/NEON initialisation and switching - // (ARM ARM section A7.5) VFP data processing instruction? - // (ARM ARM section A7.6) VFP/NEON register load/store instruction? - // (ARM ARM section A7.8) VFP/NEON register data transfer instruction? - // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction? - if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) || - (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) { - if (((opcode & 0x00000E00) >> 9) == 5) { + // (Arm Architecture Reference Manual section A7.5) VFP data processing instruction? + // (Arm Architecture Reference Manual section A7.6) VFP/NEON register load/store instruction? + // (Arm Architecture Reference Manual section A7.8) VFP/NEON register data transfer instruction? + // (Arm Architecture Reference Manual section A7.9) VFP/NEON 64-bit register data transfer instruction? + if ((state == ARM && ((opcode & 0x0C000000U) >> 26U == 0x03U)) || + (state == THUMB && ((opcode & 0xEC000000U) >> 26U == 0x3BU))) { + if (((opcode & 0x00000E00U) >> 9U) == 5U) { __FPU_Enable(); return state; } } - // (ARM ARM section A7.4) NEON data processing instruction? - if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) || - (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) || - // (ARM ARM section A7.7) NEON load/store instruction? - (state == ARM && ((opcode >> 24) == 0xF4)) || - (state == THUMB && ((opcode >> 24) == 0xF9))) { + // (Arm Architecture Reference Manual section A7.4) NEON data processing instruction? + if ((state == ARM && ((opcode & 0xFE000000U) >> 24U == 0xF2U)) || + (state == THUMB && ((opcode & 0xEF000000U) >> 24U == 0xEFU)) || + // (Arm Architecture Reference Manual section A7.7) NEON load/store instruction? + (state == ARM && ((opcode >> 24U) == 0xF4U)) || + (state == THUMB && ((opcode >> 24U) == 0xF9U))) { __FPU_Enable(); return state; } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h index 897d4de..b70991e 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -27,8 +27,8 @@ #define RTX_EVR_H_ #include "cmsis_os2.h" // CMSIS RTOS API +#include "RTX_Config.h" // RTX Configuration #include "rtx_os.h" // RTX OS definitions -#include "RTX_Config.h" /// Extended Status codes @@ -68,7 +68,7 @@ \brief Event on memory allocate (Op) \param[in] mem pointer to memory pool. \param[in] size size of a memory block in bytes. - \param[in] type memory block type: 0 - generic, 1 - control block + \param[in] type memory block type: 0 - generic, 1 - control block. \param[in] block pointer to allocated memory block or NULL in case of no memory is available. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE)) @@ -372,17 +372,18 @@ /** \brief Event on successful thread create (Op) \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] thread_addr thread entry address. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE)) -extern void EvrRtxThreadCreated (osThreadId_t thread_id); +extern void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr); #else -#define EvrRtxThreadCreated(thread_id) +#define EvrRtxThreadCreated(thread_id, thread_addr) #endif /** \brief Event on thread name retrieve (API) \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. - \param[in] name pointer to thread object name + \param[in] name pointer to thread object name. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE)) extern void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name); @@ -566,7 +567,7 @@ #endif /** - \brief Event on blocked thread release (Op) + \brief Event on thread execution unblock (Op) \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. \param[in] ret_val extended execution status of the thread. */ @@ -577,13 +578,23 @@ #endif /** - \brief Event on current running thread switch (Op) + \brief Event on running thread pre-emption (Op) \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. */ -#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCH_DISABLE)) -extern void EvrRtxThreadSwitch (osThreadId_t thread_id); +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PREEMPTED_DISABLE)) +extern void EvrRtxThreadPreempted (osThreadId_t thread_id); #else -#define EvrRtxThreadSwitch(thread_id) +#define EvrRtxThreadPreempted(thread_id) +#endif + +/** + \brief Event on running thread switch (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCHED_DISABLE)) +extern void EvrRtxThreadSwitched (osThreadId_t thread_id); +#else +#define EvrRtxThreadSwitched(thread_id) #endif /** @@ -651,7 +662,7 @@ /** \brief Event on successful thread flags set (Op) \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. - \param[in] thread_flags thread flags after setting + \param[in] thread_flags thread flags after setting. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE)) extern void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags); @@ -671,7 +682,7 @@ /** \brief Event on successful thread flags clear (Op) - \param[in] thread_flags thread flags before clearing + \param[in] thread_flags thread flags before clearing. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE)) extern void EvrRtxThreadFlagsClearDone (uint32_t thread_flags); @@ -726,7 +737,7 @@ \brief Event on successful wait for thread flags (Op) \param[in] flags flags to wait for. \param[in] options flags options (osFlagsXxxx). - \param[in] thread_flags thread flags before clearing + \param[in] thread_flags thread flags before clearing. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE)) extern void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags); @@ -747,7 +758,7 @@ /** \brief Event on wait for timeout (API) - \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value + \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_DISABLE)) extern void EvrRtxThreadDelay (uint32_t ticks); @@ -757,7 +768,7 @@ /** \brief Event on wait until specified time (API) - \param[in] ticks absolute time in ticks + \param[in] ticks absolute time in ticks. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_UNTIL_DISABLE)) extern void EvrRtxThreadDelayUntil (uint32_t ticks); @@ -815,17 +826,18 @@ /** \brief Event on successful timer create (Op) - \param[in] timer_id timer ID obtained by \ref osTimerNew + \param[in] timer_id timer ID obtained by \ref osTimerNew. + \param[in] name pointer to timer object name. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE)) -extern void EvrRtxTimerCreated (osTimerId_t timer_id); +extern void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name); #else -#define EvrRtxTimerCreated(timer_id); +#define EvrRtxTimerCreated(timer_id, name); #endif /** \brief Event on timer name retrieve (API) - \param[in] timer_id timer ID obtained by \ref osTimerNew + \param[in] timer_id timer ID obtained by \ref osTimerNew. \param[in] name pointer to timer object name. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE)) @@ -836,7 +848,7 @@ /** \brief Event on timer start (API) - \param[in] timer_id timer ID obtained by \ref osTimerNew + \param[in] timer_id timer ID obtained by \ref osTimerNew. \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE)) @@ -847,7 +859,7 @@ /** \brief Event on successful timer start (Op) - \param[in] timer_id timer ID obtained by \ref osTimerNew + \param[in] timer_id timer ID obtained by \ref osTimerNew. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE)) extern void EvrRtxTimerStarted (osTimerId_t timer_id); @@ -857,7 +869,7 @@ /** \brief Event on timer stop (API) - \param[in] timer_id timer ID obtained by \ref osTimerNew + \param[in] timer_id timer ID obtained by \ref osTimerNew. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE)) extern void EvrRtxTimerStop (osTimerId_t timer_id); @@ -867,7 +879,7 @@ /** \brief Event on successful timer stop (Op) - \param[in] timer_id timer ID obtained by \ref osTimerNew + \param[in] timer_id timer ID obtained by \ref osTimerNew. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE)) extern void EvrRtxTimerStopped (osTimerId_t timer_id); @@ -877,8 +889,8 @@ /** \brief Event on timer running state check (API) - \param[in] timer_id timer ID obtained by \ref osTimerNew - \param[in] running running state: 0 not running, 1 running + \param[in] timer_id timer ID obtained by \ref osTimerNew. + \param[in] running running state: 0 not running, 1 running. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE)) extern void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running); @@ -888,7 +900,7 @@ /** \brief Event on timer delete (API) - \param[in] timer_id timer ID obtained by \ref osTimerNew + \param[in] timer_id timer ID obtained by \ref osTimerNew. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE)) extern void EvrRtxTimerDelete (osTimerId_t timer_id); @@ -898,7 +910,7 @@ /** \brief Event on successful timer delete (Op) - \param[in] timer_id timer ID obtained by \ref osTimerNew + \param[in] timer_id timer ID obtained by \ref osTimerNew. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE)) extern void EvrRtxTimerDestroyed (osTimerId_t timer_id); @@ -922,7 +934,7 @@ /** \brief Event on event flags create and initialize (API) - \param[in] attr event flags attributes + \param[in] attr event flags attributes. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE)) extern void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr); @@ -933,11 +945,12 @@ /** \brief Event on successful event flags create (Op) \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] name pointer to event flags object name. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE)) -extern void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id); +extern void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name); #else -#define EvrRtxEventFlagsCreated(ef_id) +#define EvrRtxEventFlagsCreated(ef_id, name) #endif /** @@ -965,7 +978,7 @@ /** \brief Event on successful event flags set (Op) \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. - \param[in] event_flags event flags after setting + \param[in] event_flags event flags after setting. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE)) extern void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags); @@ -987,7 +1000,7 @@ /** \brief Event on successful event flags clear (Op) \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. - \param[in] event_flags event flags before clearing + \param[in] event_flags event flags before clearing. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE)) extern void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags); @@ -1103,7 +1116,7 @@ /** \brief Event on mutex create and initialize (API) - \param[in] attr mutex attributes + \param[in] attr mutex attributes. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE)) extern void EvrRtxMutexNew (const osMutexAttr_t *attr); @@ -1114,17 +1127,18 @@ /** \brief Event on successful mutex create (Op) \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] name pointer to mutex object name. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE)) -extern void EvrRtxMutexCreated (osMutexId_t mutex_id); +extern void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name); #else -#define EvrRtxMutexCreated(mutex_id) +#define EvrRtxMutexCreated(mutex_id, name) #endif /** \brief Event on mutex name retrieve (API) \param[in] mutex_id mutex ID obtained by \ref osMutexNew. - \param[in] name pointer to mutex object name + \param[in] name pointer to mutex object name. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE)) extern void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name); @@ -1167,7 +1181,7 @@ /** \brief Event on successful mutex acquire (Op) \param[in] mutex_id mutex ID obtained by \ref osMutexNew. - \param[in] lock current number of times mutex object is locked + \param[in] lock current number of times mutex object is locked. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE)) extern void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock); @@ -1198,7 +1212,7 @@ /** \brief Event on successful mutex release (Op) \param[in] mutex_id mutex ID obtained by \ref osMutexNew. - \param[in] lock current number of times mutex object is locked + \param[in] lock current number of times mutex object is locked. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE)) extern void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock); @@ -1266,11 +1280,12 @@ /** \brief Event on successful semaphore create (Op) \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] name pointer to semaphore object name. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE)) -extern void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id); +extern void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *name); #else -#define EvrRtxSemaphoreCreated(semaphore_id) +#define EvrRtxSemaphoreCreated(semaphore_id, name) #endif /** @@ -1416,11 +1431,12 @@ /** \brief Event on successful memory pool create (Op) \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] name pointer to memory pool object name. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE)) -extern void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id); +extern void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name); #else -#define EvrRtxMemoryPoolCreated(mp_id) +#define EvrRtxMemoryPoolCreated(mp_id, name) #endif /** @@ -1613,11 +1629,12 @@ /** \brief Event on successful message queue create (Op) \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] name pointer to message queue object name. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE)) -extern void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id); +extern void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *name); #else -#define EvrRtxMessageQueueCreated(mq_id) +#define EvrRtxMessageQueueCreated(mq_id, name) #endif /** diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h index 0c2df7e..d173917 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -37,9 +37,9 @@ /// Kernel Information -#define osRtxVersionAPI 20010001 ///< API version (2.1.1) -#define osRtxVersionKernel 50020002 ///< Kernel version (5.2.2) -#define osRtxKernelId "RTX V5.2.2" ///< Kernel identification string +#define osRtxVersionAPI 20010002 ///< API version (2.1.2) +#define osRtxVersionKernel 50030000 ///< Kernel version (5.3.0) +#define osRtxKernelId "RTX V5.3.0" ///< Kernel identification string // ==== Common definitions ==== @@ -85,15 +85,15 @@ #define osRtxThreadBlocked ((uint8_t)osThreadBlocked) #define osRtxThreadTerminated ((uint8_t)osThreadTerminated) -#define osRtxThreadWaitingDelay (osRtxThreadBlocked | 0x10U) -#define osRtxThreadWaitingJoin (osRtxThreadBlocked | 0x20U) -#define osRtxThreadWaitingThreadFlags (osRtxThreadBlocked | 0x30U) -#define osRtxThreadWaitingEventFlags (osRtxThreadBlocked | 0x40U) -#define osRtxThreadWaitingMutex (osRtxThreadBlocked | 0x50U) -#define osRtxThreadWaitingSemaphore (osRtxThreadBlocked | 0x60U) -#define osRtxThreadWaitingMemoryPool (osRtxThreadBlocked | 0x70U) -#define osRtxThreadWaitingMessageGet (osRtxThreadBlocked | 0x80U) -#define osRtxThreadWaitingMessagePut (osRtxThreadBlocked | 0x90U) +#define osRtxThreadWaitingDelay ((uint8_t)(osRtxThreadBlocked | 0x10U)) +#define osRtxThreadWaitingJoin ((uint8_t)(osRtxThreadBlocked | 0x20U)) +#define osRtxThreadWaitingThreadFlags ((uint8_t)(osRtxThreadBlocked | 0x30U)) +#define osRtxThreadWaitingEventFlags ((uint8_t)(osRtxThreadBlocked | 0x40U)) +#define osRtxThreadWaitingMutex ((uint8_t)(osRtxThreadBlocked | 0x50U)) +#define osRtxThreadWaitingSemaphore ((uint8_t)(osRtxThreadBlocked | 0x60U)) +#define osRtxThreadWaitingMemoryPool ((uint8_t)(osRtxThreadBlocked | 0x70U)) +#define osRtxThreadWaitingMessageGet ((uint8_t)(osRtxThreadBlocked | 0x80U)) +#define osRtxThreadWaitingMessagePut ((uint8_t)(osRtxThreadBlocked | 0x90U)) /// Thread Flags definitions #define osRtxThreadFlagDefStack 0x10U ///< Default Stack flag @@ -143,7 +143,7 @@ /// Timer Function Information typedef struct { - void *fp; ///< Function Pointer + osTimerFunc_t func; ///< Function Pointer void *arg; ///< Function Argument } osRtxTimerFinfo_t; @@ -165,7 +165,7 @@ // ==== Event Flags definitions ==== /// Event Flags Control Block -typedef struct osRtxEventFlags_s { +typedef struct { uint8_t id; ///< Object Identifier uint8_t state; ///< Object State uint8_t flags; ///< Object Flags @@ -197,7 +197,7 @@ // ==== Semaphore definitions ==== /// Semaphore Control Block -typedef struct osRtxSemaphore_s { +typedef struct { uint8_t id; ///< Object Identifier uint8_t state; ///< Object State uint8_t flags; ///< Object Flags @@ -212,7 +212,7 @@ // ==== Memory Pool definitions ==== /// Memory Pool Information -typedef struct osRtxMpInfo_s { +typedef struct { uint32_t max_blocks; ///< Maximum number of Blocks uint32_t used_blocks; ///< Number of used Blocks uint32_t block_size; ///< Block Size @@ -222,7 +222,7 @@ } osRtxMpInfo_t; /// Memory Pool Control Block -typedef struct osRtxMemoryPool_s { +typedef struct { uint8_t id; ///< Object Identifier uint8_t state; ///< Object State uint8_t flags; ///< Object Flags @@ -246,7 +246,7 @@ } osRtxMessage_t; /// Message Queue Control Block -typedef struct osRtxMessageQueue_s { +typedef struct { uint8_t id; ///< Object Identifier uint8_t state; ///< Object State uint8_t flags; ///< Object Flags @@ -264,7 +264,7 @@ // ==== Generic Object definitions ==== /// Generic Object Control Block -typedef struct osRtxObject_s { +typedef struct { uint8_t id; ///< Object Identifier uint8_t state; ///< Object State uint8_t flags; ///< Object Flags @@ -293,7 +293,7 @@ osRtxThread_t *curr; ///< Current running Thread osRtxThread_t *next; ///< Next Thread to Run } run; - volatile osRtxObject_t ready; ///< Ready List Object + osRtxObject_t ready; ///< Ready List Object osRtxThread_t *idle; ///< Idle Thread osRtxThread_t *delay_list; ///< Delay List osRtxThread_t *wait_list; ///< Wait List (no Timeout) @@ -322,7 +322,7 @@ void (*event_flags)(osRtxEventFlags_t*); ///< Event Flags Post Processing function void (*semaphore)(osRtxSemaphore_t*); ///< Semaphore Post Processing function void (*memory_pool)(osRtxMemoryPool_t*); ///< Memory Pool Post Processing function - void (*message_queue)(osRtxMessage_t*); ///< Message Queue Post Processing function + void (*message)(osRtxMessage_t*); ///< Message Post Processing function } post_process; struct { ///< Memory Pools (Variable Block Size) void *stack; ///< Stack Memory @@ -344,16 +344,32 @@ extern osRtxInfo_t osRtxInfo; ///< OS Runtime Information +/// OS Runtime Object Memory Usage structure +typedef struct { + uint32_t cnt_alloc; ///< Counter for alloc + uint32_t cnt_free; ///< Counter for free + uint32_t max_used; ///< Maximum used +} osRtxObjectMemUsage_t; + +/// OS Runtime Object Memory Usage variables +extern osRtxObjectMemUsage_t osRtxThreadMemUsage; +extern osRtxObjectMemUsage_t osRtxTimerMemUsage; +extern osRtxObjectMemUsage_t osRtxEventFlagsMemUsage; +extern osRtxObjectMemUsage_t osRtxMutexMemUsage; +extern osRtxObjectMemUsage_t osRtxSemaphoreMemUsage; +extern osRtxObjectMemUsage_t osRtxMemoryPoolMemUsage; +extern osRtxObjectMemUsage_t osRtxMessageQueueMemUsage; + // ==== OS API definitions ==== -/// Object Limits definitions +// Object Limits definitions #define osRtxThreadFlagsLimit 31U ///< number of Thread Flags available per thread #define osRtxEventFlagsLimit 31U ///< number of Event Flags available per object #define osRtxMutexLockLimit 255U ///< maximum number of recursive mutex locks #define osRtxSemaphoreTokenLimit 65535U ///< maximum number of tokens per semaphore -/// Control Block sizes +// Control Block sizes #define osRtxThreadCbSize sizeof(osRtxThread_t) #define osRtxTimerCbSize sizeof(osRtxTimer_t) #define osRtxEventFlagsCbSize sizeof(osRtxEventFlags_t) @@ -377,12 +393,12 @@ // ==== OS External Functions ==== -/// OS Error Codes -#define osRtxErrorStackUnderflow 1U -#define osRtxErrorISRQueueOverflow 2U -#define osRtxErrorTimerQueueOverflow 3U -#define osRtxErrorClibSpace 4U -#define osRtxErrorClibMutex 5U +// OS Error Codes +#define osRtxErrorStackUnderflow 1U ///< Stack overflow, i.e. stack pointer below its lower memory limit for descending stacks. +#define osRtxErrorISRQueueOverflow 2U ///< ISR Queue overflow detected when inserting object. +#define osRtxErrorTimerQueueOverflow 3U ///< User Timer Callback Queue overflow detected for timer. +#define osRtxErrorClibSpace 4U ///< Standard C/C++ library libspace not available: increase \c OS_THREAD_LIBSPACE_NUM. +#define osRtxErrorClibMutex 5U ///< Standard C/C++ library mutex initialization failed. /// OS Error Callback function extern uint32_t osRtxErrorNotify (uint32_t code, void *object_id); diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S index 97b43d8..a21d7ca 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0/irq_cm0.S index 8fab32a..c5146b3 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0/irq_cm0.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -44,18 +44,26 @@ EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + MOV R0,LR + LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP ; Branch if return stack is MSP MRS R0,PSP ; Get PSP + +SVC_Number LDR R1,[R0,#24] ; Load saved PC from stack SUBS R1,R1,#2 ; Point to SVC instruction LDRB R1,[R1] ; Load SVC number CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDMIA R0,{R0-R3} ; Load function parameters from stack BLX R7 ; Call service function - POP {R2,R3} ; Restore PSP and EXC_RETURN + POP {R2,R3} ; Restore SP and EXC_RETURN STMIA R2!,{R0-R1} ; Store function return values MOV LR,R3 ; Set EXC_RETURN @@ -70,7 +78,7 @@ SVC_ContextSave MRS R0,PSP ; Get PSP - SUBS R0,R0,#32 ; Adjust address + SUBS R0,R0,#32 ; Calculate SP STR R0,[R1,#TCB_SP_OFS] ; Store SP STMIA R0!,{R4-R7} ; Save R4..R7 MOV R4,R8 @@ -80,9 +88,16 @@ STMIA R0!,{R4-R7} ; Save R8..R11 SVC_ContextSwitch - SUBS R3,R3,#8 + SUBS R3,R3,#8 ; Adjust address STR R2,[R3] ; osRtxInfo.thread.run: curr = next + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + SVC_ContextRestore LDR R0,[R2,#TCB_SP_OFS] ; Load SP ADDS R0,R0,#16 ; Adjust address @@ -99,26 +114,30 @@ MVNS R0,R0 ; Set EXC_RETURN value BX R0 ; Exit from handler +SVC_MSP + MRS R0,MSP ; Get MSP + B SVC_Number + SVC_Exit BX LR ; Exit from handler SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range + PUSH {R0,LR} ; Save SP and EXC_RETURN LSLS R1,R1,#2 - LDR R4,[R2,R1] ; Load address of SVC function - + LDR R3,[R2,R1] ; Load address of SVC function + MOV R12,R3 LDMIA R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STMIA R4!,{R0-R3} ; Store function return values + BLX R12 ; Call service function + POP {R2,R3} ; Restore SP and EXC_RETURN + STR R0,[R2] ; Store function return value + MOV LR,R3 ; Set EXC_RETURN -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler ALIGN ENDP diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0P/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0P/irq_cm0.S index 8fab32a..c5146b3 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0P/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0P/irq_cm0.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -44,18 +44,26 @@ EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + MOV R0,LR + LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP ; Branch if return stack is MSP MRS R0,PSP ; Get PSP + +SVC_Number LDR R1,[R0,#24] ; Load saved PC from stack SUBS R1,R1,#2 ; Point to SVC instruction LDRB R1,[R1] ; Load SVC number CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDMIA R0,{R0-R3} ; Load function parameters from stack BLX R7 ; Call service function - POP {R2,R3} ; Restore PSP and EXC_RETURN + POP {R2,R3} ; Restore SP and EXC_RETURN STMIA R2!,{R0-R1} ; Store function return values MOV LR,R3 ; Set EXC_RETURN @@ -70,7 +78,7 @@ SVC_ContextSave MRS R0,PSP ; Get PSP - SUBS R0,R0,#32 ; Adjust address + SUBS R0,R0,#32 ; Calculate SP STR R0,[R1,#TCB_SP_OFS] ; Store SP STMIA R0!,{R4-R7} ; Save R4..R7 MOV R4,R8 @@ -80,9 +88,16 @@ STMIA R0!,{R4-R7} ; Save R8..R11 SVC_ContextSwitch - SUBS R3,R3,#8 + SUBS R3,R3,#8 ; Adjust address STR R2,[R3] ; osRtxInfo.thread.run: curr = next + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + SVC_ContextRestore LDR R0,[R2,#TCB_SP_OFS] ; Load SP ADDS R0,R0,#16 ; Adjust address @@ -99,26 +114,30 @@ MVNS R0,R0 ; Set EXC_RETURN value BX R0 ; Exit from handler +SVC_MSP + MRS R0,MSP ; Get MSP + B SVC_Number + SVC_Exit BX LR ; Exit from handler SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range + PUSH {R0,LR} ; Save SP and EXC_RETURN LSLS R1,R1,#2 - LDR R4,[R2,R1] ; Load address of SVC function - + LDR R3,[R2,R1] ; Load address of SVC function + MOV R12,R3 LDMIA R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STMIA R4!,{R0-R3} ; Store function return values + BLX R12 ; Call service function + POP {R2,R3} ; Restore SP and EXC_RETURN + STR R0,[R2] ; Store function return value + MOV LR,R3 ; Set EXC_RETURN -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler ALIGN ENDP diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S index d81d242..4caf963 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2016-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -24,8 +24,8 @@ ; */ -#ifndef __DOMAIN_NS -__DOMAIN_NS EQU 0 +#ifndef DOMAIN_NS +DOMAIN_NS EQU 0 #endif I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset @@ -51,22 +51,30 @@ EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo - IF __DOMAIN_NS = 1 + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + IF DOMAIN_NS = 1 IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S ENDIF + MOV R0,LR + LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP ; Branch if return stack is MSP MRS R0,PSP ; Get PSP + +SVC_Number LDR R1,[R0,#24] ; Load saved PC from stack SUBS R1,R1,#2 ; Point to SVC instruction LDRB R1,[R1] ; Load SVC number CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDM R0,{R0-R3} ; Load function parameters from stack BLX R7 ; Call service function - POP {R2,R3} ; Restore PSP and EXC_RETURN + POP {R2,R3} ; Restore SP and EXC_RETURN STMIA R2!,{R0-R1} ; Store function return values MOV LR,R3 ; Set EXC_RETURN @@ -79,7 +87,7 @@ CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted SVC_ContextSave - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,R7} ; Save registers @@ -91,7 +99,7 @@ SVC_ContextSave1 MRS R0,PSP ; Get PSP - SUBS R0,R0,#32 ; Adjust PSP + SUBS R0,R0,#32 ; Calculate SP STR R0,[R1,#TCB_SP_OFS] ; Store SP STMIA R0!,{R4-R7} ; Save R4..R7 MOV R4,R8 @@ -109,8 +117,15 @@ SUBS R3,R3,#8 ; Adjust address STR R2,[R3] ; osRtxInfo.thread.run: curr = next + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + SVC_ContextRestore - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers @@ -127,7 +142,7 @@ ORRS R0,R1 MOV LR,R0 ; Set EXC_RETURN - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 LSLS R0,R0,#25 ; Check domain of interrupted thread BPL SVC_ContextRestore2 ; Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] ; Load SP @@ -153,23 +168,27 @@ SVC_Exit BX LR ; Exit from handler +SVC_MSP + MRS R0,MSP ; Get MSP + B SVC_Number + SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range + PUSH {R0,LR} ; Save SP and EXC_RETURN LSLS R1,R1,#2 - LDR R4,[R2,R1] ; Load address of SVC function + LDR R3,[R2,R1] ; Load address of SVC function + MOV R12,R3 + LDMIA R0,{R0-R3} ; Load function parameters from stack + BLX R12 ; Call service function + POP {R2,R3} ; Restore SP and EXC_RETURN + STR R0,[R2] ; Store function return value + MOV LR,R3 ; Set EXC_RETURN - LDM R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STR R0,[R4] ; Store function return value - -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler ALIGN ENDP @@ -206,7 +225,10 @@ Sys_Context PROC EXPORT Sys_Context IMPORT osRtxInfo - IF __DOMAIN_NS = 1 + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + IF DOMAIN_NS = 1 IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S ENDIF @@ -217,7 +239,7 @@ BEQ Sys_ContextExit ; Branch when threads are the same Sys_ContextSave - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,R7} ; Save registers @@ -253,8 +275,15 @@ SUBS R3,R3,#8 ; Adjust address STR R2,[R3] ; osRtxInfo.run: curr = next + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + Sys_ContextRestore - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers @@ -271,7 +300,7 @@ ORRS R0,R1 MOV LR,R0 ; Set EXC_RETURN - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 LSLS R0,R0,#25 ; Check domain of interrupted thread BPL Sys_ContextRestore2 ; Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] ; Load SP diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M3/irq_cm3.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M3/irq_cm3.S index 2fd6618..0a5ed34 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M3/irq_cm3.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M3/irq_cm3.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -44,22 +44,30 @@ EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF - MRS R0,PSP ; Get PSP + TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP ; Get MSP if return stack is MSP + MRSNE R0,PSP ; Get PSP if return stack is PSP + LDR R1,[R0,#24] ; Load saved PC from stack LDRB R1,[R1,#-2] ; Load SVC number CBNZ R1,SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDM R0,{R0-R3,R12} ; Load function parameters and address from stack BLX R12 ; Call service function - POP {R12,LR} ; Restore PSP and EXC_RETURN + POP {R12,LR} ; Restore SP and EXC_RETURN STM R12,{R0-R1} ; Store function return values SVC_Context LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next CMP R1,R2 ; Check if thread switch is required + IT EQ BXEQ LR ; Exit when threads are the same CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted @@ -71,6 +79,13 @@ SVC_ContextSwitch STR R2,[R3] ; osRtxInfo.thread.run: curr = next + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + SVC_ContextRestore LDR R0,[R2,#TCB_SP_OFS] ; Load SP LDMIA R0!,{R4-R11} ; Restore R4..R11 @@ -82,21 +97,19 @@ BX LR ; Exit from handler SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range - LDR R4,[R2,R1,LSL #2] ; Load address of SVC function - + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] ; Load address of SVC function LDM R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STR R0,[R4] ; Store function return value + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STR R0,[R12] ; Store function return value -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler ALIGN ENDP @@ -106,9 +119,9 @@ EXPORT PendSV_Handler IMPORT osRtxPendSV_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN MRS R12,PSP B SVC_Context @@ -120,9 +133,9 @@ EXPORT SysTick_Handler IMPORT osRtxTick_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxTick_Handler ; Call osRtxTick_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN MRS R12,PSP B SVC_Context diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S index 20a5705..75a0683 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2016-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -24,8 +24,8 @@ ; */ -#ifndef __DOMAIN_NS -__DOMAIN_NS EQU 0 +#ifndef DOMAIN_NS +DOMAIN_NS EQU 0 #endif #ifndef __FPU_USED @@ -55,27 +55,35 @@ EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo - IF __DOMAIN_NS = 1 + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + IF DOMAIN_NS = 1 IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S ENDIF - MRS R0,PSP ; Get PSP + TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP ; Get MSP if return stack is MSP + MRSNE R0,PSP ; Get PSP if return stack is PSP + LDR R1,[R0,#24] ; Load saved PC from stack LDRB R1,[R1,#-2] ; Load SVC number CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDM R0,{R0-R3,R12} ; Load function parameters and address from stack BLX R12 ; Call service function - POP {R12,LR} ; Restore PSP and EXC_RETURN + POP {R12,LR} ; Restore SP and EXC_RETURN STM R12,{R0-R1} ; Store function return values SVC_Context LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next CMP R1,R2 ; Check if thread switch is required + IT EQ BXEQ LR ; Exit when threads are the same IF __FPU_USED = 1 @@ -84,7 +92,7 @@ BNE SVC_ContextSwitch LDR R1,=0xE000EF34 ; FPCCR Address LDR R0,[R1] ; Load FPCCR - BIC R0,#1 ; Clear LSPACT (Lazy state) + BIC R0,R0,#1 ; Clear LSPACT (Lazy state) STR R0,[R1] ; Store FPCCR B SVC_ContextSwitch ELSE @@ -92,7 +100,7 @@ ENDIF SVC_ContextSave - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN @@ -105,6 +113,7 @@ STMDB R0!,{R4-R11} ; Save R4..R11 IF __FPU_USED = 1 TST LR,#0x10 ; Check if extended stack frame + IT EQ VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 ENDIF @@ -115,8 +124,15 @@ SVC_ContextSwitch STR R2,[R3] ; osRtxInfo.thread.run: curr = next + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + SVC_ContextRestore - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers @@ -131,13 +147,14 @@ LDR R0,[R2,#TCB_SP_OFS] ; Load SP ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 TST LR,#0x40 ; Check domain of interrupted thread BNE SVC_ContextRestore2 ; Branch if secure ENDIF IF __FPU_USED = 1 TST LR,#0x10 ; Check if extended stack frame + IT EQ VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 ENDIF LDMIA R0!,{R4-R11} ; Restore R4..R11 @@ -149,21 +166,19 @@ BX LR ; Exit from handler SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range - LDR R4,[R2,R1,LSL #2] ; Load address of SVC function - + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] ; Load address of SVC function LDM R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STR R0,[R4] ; Store function return value + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STR R0,[R12] ; Store function return value -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler ALIGN ENDP @@ -173,9 +188,9 @@ EXPORT PendSV_Handler IMPORT osRtxPendSV_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN B Sys_Context ALIGN @@ -186,9 +201,9 @@ EXPORT SysTick_Handler IMPORT osRtxTick_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxTick_Handler ; Call osRtxTick_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN B Sys_Context ALIGN @@ -198,7 +213,10 @@ Sys_Context PROC EXPORT Sys_Context IMPORT osRtxInfo - IF __DOMAIN_NS = 1 + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + IF DOMAIN_NS = 1 IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S ENDIF @@ -206,16 +224,18 @@ LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next CMP R1,R2 ; Check if thread switch is required + IT EQ BXEQ LR ; Exit when threads are the same Sys_ContextSave - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN BL TZ_StoreContext_S ; Store secure context POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN TST LR,#0x40 ; Check domain of interrupted thread + IT NE MRSNE R0,PSP ; Get PSP BNE Sys_ContextSave2 ; Branch if secure ENDIF @@ -225,6 +245,7 @@ STMDB R0!,{R4-R11} ; Save R4..R11 IF __FPU_USED = 1 TST LR,#0x10 ; Check if extended stack frame + IT EQ VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 ENDIF @@ -235,8 +256,15 @@ Sys_ContextSwitch STR R2,[R3] ; osRtxInfo.run: curr = next + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + Sys_ContextRestore - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers @@ -251,13 +279,14 @@ LDR R0,[R2,#TCB_SP_OFS] ; Load SP ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN - IF __DOMAIN_NS = 1 + IF DOMAIN_NS = 1 TST LR,#0x40 ; Check domain of interrupted thread BNE Sys_ContextRestore2 ; Branch if secure ENDIF IF __FPU_USED = 1 TST LR,#0x10 ; Check if extended stack frame + IT EQ VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 ENDIF LDMIA R0!,{R4-R11} ; Restore R4..R11 diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S index 44d0c7c..803c7c3 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -45,22 +45,30 @@ EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF - MRS R0,PSP ; Get PSP + TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP ; Get MSP if return stack is MSP + MRSNE R0,PSP ; Get PSP if return stack is PSP + LDR R1,[R0,#24] ; Load saved PC from stack LDRB R1,[R1,#-2] ; Load SVC number CBNZ R1,SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDM R0,{R0-R3,R12} ; Load function parameters and address from stack BLX R12 ; Call service function - POP {R12,LR} ; Restore PSP and EXC_RETURN + POP {R12,LR} ; Restore SP and EXC_RETURN STM R12,{R0-R1} ; Store function return values SVC_Context LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next CMP R1,R2 ; Check if thread switch is required + IT EQ BXEQ LR ; Exit when threads are the same CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted @@ -69,7 +77,7 @@ #ifdef __FPU_PRESENT LDR R1,=0xE000EF34 ; FPCCR Address LDR R0,[R1] ; Load FPCCR - BIC R0,#1 ; Clear LSPACT (Lazy state) + BIC R0,R0,#1 ; Clear LSPACT (Lazy state) STR R0,[R1] ; Store FPCCR B SVC_ContextSwitch #endif @@ -78,6 +86,7 @@ STMDB R12!,{R4-R11} ; Save R4..R11 #ifdef __FPU_PRESENT TST LR,#0x10 ; Check if extended stack frame + IT EQ VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 #endif @@ -87,6 +96,13 @@ SVC_ContextSwitch STR R2,[R3] ; osRtxInfo.thread.run: curr = next + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + SVC_ContextRestore LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information LDR R0,[R2,#TCB_SP_OFS] ; Load SP @@ -94,6 +110,7 @@ #ifdef __FPU_PRESENT TST LR,#0x10 ; Check if extended stack frame + IT EQ VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 #endif LDMIA R0!,{R4-R11} ; Restore R4..R11 @@ -103,21 +120,19 @@ BX LR ; Exit from handler SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range - LDR R4,[R2,R1,LSL #2] ; Load address of SVC function - + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] ; Load address of SVC function LDM R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STR R0,[R4] ; Store function return value + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STR R0,[R12] ; Store function return value -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler ALIGN ENDP @@ -127,9 +142,9 @@ EXPORT PendSV_Handler IMPORT osRtxPendSV_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN MRS R12,PSP B SVC_Context @@ -141,9 +156,9 @@ EXPORT SysTick_Handler IMPORT osRtxTick_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxTick_Handler ; Call osRtxTick_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN MRS R12,PSP B SVC_Context diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S index 72d20c0..92a527e 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S index 59288e2..f166d2d 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -48,17 +48,22 @@ .cantunwind SVC_Handler: + MOV R0,LR + LSRS R0,R0,#3 // Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP // Branch if return stack is MSP MRS R0,PSP // Get PSP + +SVC_Number: LDR R1,[R0,#24] // Load saved PC from stack SUBS R1,R1,#2 // Point to SVC instruction LDRB R1,[R1] // Load SVC number CMP R1,#0 BNE SVC_User // Branch if not SVC 0 - PUSH {R0,LR} // Save PSP and EXC_RETURN + PUSH {R0,LR} // Save SP and EXC_RETURN LDMIA R0,{R0-R3} // Load function parameters from stack BLX R7 // Call service function - POP {R2,R3} // Restore PSP and EXC_RETURN + POP {R2,R3} // Restore SP and EXC_RETURN STMIA R2!,{R0-R1} // Store function return values MOV LR,R3 // Set EXC_RETURN @@ -73,8 +78,8 @@ SVC_ContextSave: MRS R0,PSP // Get PSP - SUBS R0,R0,#32 // Adjust address - STR R0,[R1,#TCB_SP_OFS]; // Store SP + SUBS R0,R0,#32 // Calculate SP + STR R0,[R1,#TCB_SP_OFS] // Store SP STMIA R0!,{R4-R7} // Save R4..R7 MOV R4,R8 MOV R5,R9 @@ -83,7 +88,7 @@ STMIA R0!,{R4-R7} // Save R8..R11 SVC_ContextSwitch: - SUBS R3,R3,#8 + SUBS R3,R3,#8 // Adjust address STR R2,[R3] // osRtxInfo.thread.run: curr = next SVC_ContextRestore: @@ -102,26 +107,30 @@ MVNS R0,R0 // Set EXC_RETURN value BX R0 // Exit from handler +SVC_MSP: + MRS R0,MSP // Get MSP + B SVC_Number + SVC_Exit: BX LR // Exit from handler SVC_User: - PUSH {R4,LR} // Save registers LDR R2,=osRtxUserSVC // Load address of SVC table LDR R3,[R2] // Load SVC maximum number CMP R1,R3 // Check SVC number range - BHI SVC_Done // Branch if out of range + BHI SVC_Exit // Branch if out of range + PUSH {R0,LR} // Save SP and EXC_RETURN LSLS R1,R1,#2 - LDR R4,[R2,R1] // Load address of SVC function - + LDR R3,[R2,R1] // Load address of SVC function + MOV R12,R3 LDMIA R0,{R0-R3} // Load function parameters from stack - BLX R4 // Call service function - MRS R4,PSP // Get PSP - STMIA R4!,{R0-R3} // Store function return values + BLX R12 // Call service function + POP {R2,R3} // Restore SP and EXC_RETURN + STR R0,[R2] // Store function return value + MOV LR,R3 // Set EXC_RETURN -SVC_Done: - POP {R4,PC} // Return from handler + BX LR // Return from handler .fnend .size SVC_Handler, .-SVC_Handler diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S index 59288e2..f166d2d 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -48,17 +48,22 @@ .cantunwind SVC_Handler: + MOV R0,LR + LSRS R0,R0,#3 // Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP // Branch if return stack is MSP MRS R0,PSP // Get PSP + +SVC_Number: LDR R1,[R0,#24] // Load saved PC from stack SUBS R1,R1,#2 // Point to SVC instruction LDRB R1,[R1] // Load SVC number CMP R1,#0 BNE SVC_User // Branch if not SVC 0 - PUSH {R0,LR} // Save PSP and EXC_RETURN + PUSH {R0,LR} // Save SP and EXC_RETURN LDMIA R0,{R0-R3} // Load function parameters from stack BLX R7 // Call service function - POP {R2,R3} // Restore PSP and EXC_RETURN + POP {R2,R3} // Restore SP and EXC_RETURN STMIA R2!,{R0-R1} // Store function return values MOV LR,R3 // Set EXC_RETURN @@ -73,8 +78,8 @@ SVC_ContextSave: MRS R0,PSP // Get PSP - SUBS R0,R0,#32 // Adjust address - STR R0,[R1,#TCB_SP_OFS]; // Store SP + SUBS R0,R0,#32 // Calculate SP + STR R0,[R1,#TCB_SP_OFS] // Store SP STMIA R0!,{R4-R7} // Save R4..R7 MOV R4,R8 MOV R5,R9 @@ -83,7 +88,7 @@ STMIA R0!,{R4-R7} // Save R8..R11 SVC_ContextSwitch: - SUBS R3,R3,#8 + SUBS R3,R3,#8 // Adjust address STR R2,[R3] // osRtxInfo.thread.run: curr = next SVC_ContextRestore: @@ -102,26 +107,30 @@ MVNS R0,R0 // Set EXC_RETURN value BX R0 // Exit from handler +SVC_MSP: + MRS R0,MSP // Get MSP + B SVC_Number + SVC_Exit: BX LR // Exit from handler SVC_User: - PUSH {R4,LR} // Save registers LDR R2,=osRtxUserSVC // Load address of SVC table LDR R3,[R2] // Load SVC maximum number CMP R1,R3 // Check SVC number range - BHI SVC_Done // Branch if out of range + BHI SVC_Exit // Branch if out of range + PUSH {R0,LR} // Save SP and EXC_RETURN LSLS R1,R1,#2 - LDR R4,[R2,R1] // Load address of SVC function - + LDR R3,[R2,R1] // Load address of SVC function + MOV R12,R3 LDMIA R0,{R0-R3} // Load function parameters from stack - BLX R4 // Call service function - MRS R4,PSP // Get PSP - STMIA R4!,{R0-R3} // Store function return values + BLX R12 // Call service function + POP {R2,R3} // Restore SP and EXC_RETURN + STR R0,[R2] // Store function return value + MOV LR,R3 // Set EXC_RETURN -SVC_Done: - POP {R4,PC} // Return from handler + BX LR // Return from handler .fnend .size SVC_Handler, .-SVC_Handler diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S index ec927db..bbd071f 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2016-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -27,8 +27,8 @@ .file "irq_armv8mbl.S" .syntax unified -#ifndef __DOMAIN_NS - .equ __DOMAIN_NS, 0 +#ifndef DOMAIN_NS + .equ DOMAIN_NS, 0 #endif .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset @@ -55,17 +55,22 @@ .cantunwind SVC_Handler: + MOV R0,LR + LSRS R0,R0,#3 // Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP // Branch if return stack is MSP MRS R0,PSP // Get PSP + +SVC_Number: LDR R1,[R0,#24] // Load saved PC from stack SUBS R1,R1,#2 // Point to SVC instruction LDRB R1,[R1] // Load SVC number CMP R1,#0 BNE SVC_User // Branch if not SVC 0 - PUSH {R0,LR} // Save PSP and EXC_RETURN + PUSH {R0,LR} // Save SP and EXC_RETURN LDM R0,{R0-R3} // Load function parameters from stack BLX R7 // Call service function - POP {R2,R3} // Restore PSP and EXC_RETURN + POP {R2,R3} // Restore SP and EXC_RETURN STMIA R2!,{R0-R1} // Store function return values MOV LR,R3 // Set EXC_RETURN @@ -78,7 +83,7 @@ CBZ R1,SVC_ContextSwitch // Branch if running thread is deleted SVC_ContextSave: - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,SVC_ContextSave1 // Branch if there is no secure context PUSH {R1,R2,R3,R7} // Save registers @@ -90,7 +95,7 @@ SVC_ContextSave1: MRS R0,PSP // Get PSP - SUBS R0,R0,#32 // Adjust PSP + SUBS R0,R0,#32 // Calculate SP STR R0,[R1,#TCB_SP_OFS] // Store SP STMIA R0!,{R4-R7} // Save R4..R7 MOV R4,R8 @@ -109,7 +114,7 @@ STR R2,[R3] // osRtxInfo.thread.run: curr = next SVC_ContextRestore: - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,SVC_ContextRestore1 // Branch if there is no secure context PUSH {R2,R3} // Save registers @@ -126,7 +131,7 @@ ORRS R0,R1 MOV LR,R0 // Set EXC_RETURN - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 LSLS R0,R0,#25 // Check domain of interrupted thread BPL SVC_ContextRestore2 // Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] // Load SP @@ -152,23 +157,27 @@ SVC_Exit: BX LR // Exit from handler +SVC_MSP: + MRS R0,MSP // Get MSP + B SVC_Number + SVC_User: - PUSH {R4,LR} // Save registers LDR R2,=osRtxUserSVC // Load address of SVC table LDR R3,[R2] // Load SVC maximum number CMP R1,R3 // Check SVC number range - BHI SVC_Done // Branch if out of range + BHI SVC_Exit // Branch if out of range + PUSH {R0,LR} // Save SP and EXC_RETURN LSLS R1,R1,#2 - LDR R4,[R2,R1] // Load address of SVC function + LDR R3,[R2,R1] // Load address of SVC function + MOV R12,R3 + LDMIA R0,{R0-R3} // Load function parameters from stack + BLX R12 // Call service function + POP {R2,R3} // Restore SP and EXC_RETURN + STR R0,[R2] // Store function return value + MOV LR,R3 // Set EXC_RETURN - LDM R0,{R0-R3} // Load function parameters from stack - BLX R4 // Call service function - MRS R4,PSP // Get PSP - STR R0,[R4] // Store function return value - -SVC_Done: - POP {R4,PC} // Return from handler + BX LR // Return from handler .fnend .size SVC_Handler, .-SVC_Handler @@ -221,7 +230,7 @@ BEQ Sys_ContextExit // Branch when threads are the same Sys_ContextSave: - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,Sys_ContextSave1 // Branch if there is no secure context PUSH {R1,R2,R3,R7} // Save registers @@ -231,7 +240,7 @@ POP {R1,R2,R3,R7} // Restore registers MOV R0,LR // Get EXC_RETURN LSLS R0,R0,#25 // Check domain of interrupted thread - BPL Sys_ContextSave1 // Branch if not secure + BPL Sys_ContextSave1 // Branch if non-secure MRS R0,PSP // Get PSP STR R0,[R1,#TCB_SP_OFS] // Store SP B Sys_ContextSave2 @@ -258,7 +267,7 @@ STR R2,[R3] // osRtxInfo.run: curr = next Sys_ContextRestore: - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,Sys_ContextRestore1 // Branch if there is no secure context PUSH {R2,R3} // Save registers @@ -275,7 +284,7 @@ ORRS R0,R1 MOV LR,R0 // Set EXC_RETURN - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 LSLS R0,R0,#25 // Check domain of interrupted thread BPL Sys_ContextRestore2 // Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] // Load SP diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S index 875b03b..6367f59 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -48,15 +48,19 @@ .cantunwind SVC_Handler: - MRS R0,PSP // Get PSP + TST LR,#0x04 // Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP // Get MSP if return stack is MSP + MRSNE R0,PSP // Get PSP if return stack is PSP + LDR R1,[R0,#24] // Load saved PC from stack LDRB R1,[R1,#-2] // Load SVC number CBNZ R1,SVC_User // Branch if not SVC 0 - PUSH {R0,LR} // Save PSP and EXC_RETURN + PUSH {R0,LR} // Save SP and EXC_RETURN LDM R0,{R0-R3,R12} // Load function parameters and address from stack BLX R12 // Call service function - POP {R12,LR} // Restore PSP and EXC_RETURN + POP {R12,LR} // Restore SP and EXC_RETURN STM R12,{R0-R1} // Store function return values SVC_Context: @@ -100,21 +104,19 @@ BX LR // Exit from handler SVC_User: - PUSH {R4,LR} // Save registers LDR R2,=osRtxUserSVC // Load address of SVC table LDR R3,[R2] // Load SVC maximum number CMP R1,R3 // Check SVC number range - BHI SVC_Done // Branch if out of range + BHI SVC_Exit // Branch if out of range - LDR R4,[R2,R1,LSL #2] // Load address of SVC function - + PUSH {R0,LR} // Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] // Load address of SVC function LDM R0,{R0-R3} // Load function parameters from stack - BLX R4 // Call service function - MRS R4,PSP // Get PSP - STR R0,[R4] // Store function return value + BLX R12 // Call service function + POP {R12,LR} // Restore SP and EXC_RETURN + STR R0,[R12] // Store function return value -SVC_Done: - POP {R4,PC} // Return from handler + BX LR // Return from handler .fnend .size SVC_Handler, .-SVC_Handler @@ -127,9 +129,9 @@ .cantunwind PendSV_Handler: - PUSH {R4,LR} // Save EXC_RETURN + PUSH {R0,LR} // Save EXC_RETURN BL osRtxPendSV_Handler // Call osRtxPendSV_Handler - POP {R4,LR} // Restore EXC_RETURN + POP {R0,LR} // Restore EXC_RETURN MRS R12,PSP B SVC_Context @@ -144,9 +146,9 @@ .cantunwind SysTick_Handler: - PUSH {R4,LR} // Save EXC_RETURN + PUSH {R0,LR} // Save EXC_RETURN BL osRtxTick_Handler // Call osRtxTick_Handler - POP {R4,LR} // Restore EXC_RETURN + POP {R0,LR} // Restore EXC_RETURN MRS R12,PSP B SVC_Context diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S index 3cbab2a..a727728 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017 ARM Limited. All rights reserved. + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -27,8 +27,8 @@ .file "irq_armv8mml.S" .syntax unified -#ifndef __DOMAIN_NS - .equ __DOMAIN_NS, 0 +#ifndef DOMAIN_NS + .equ DOMAIN_NS, 0 #endif #ifndef __FPU_USED @@ -59,16 +59,20 @@ .cantunwind SVC_Handler: - MRS R0,PSP // Get PSP + TST LR,#0x04 // Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP // Get MSP if return stack is MSP + MRSNE R0,PSP // Get PSP if return stack is PSP + LDR R1,[R0,#24] // Load saved PC from stack LDRB R1,[R1,#-2] // Load SVC number CMP R1,#0 BNE SVC_User // Branch if not SVC 0 - PUSH {R0,LR} // Save PSP and EXC_RETURN + PUSH {R0,LR} // Save SP and EXC_RETURN LDM R0,{R0-R3,R12} // Load function parameters and address from stack BLX R12 // Call service function - POP {R12,LR} // Restore PSP and EXC_RETURN + POP {R12,LR} // Restore SP and EXC_RETURN STM R12,{R0-R1} // Store function return values SVC_Context: @@ -84,7 +88,7 @@ BNE SVC_ContextSwitch LDR R1,=0xE000EF34 // FPCCR Address LDR R0,[R1] // Load FPCCR - BIC R0,#1 // Clear LSPACT (Lazy state) + BIC R0,R0,#1 // Clear LSPACT (Lazy state) STR R0,[R1] // Store FPCCR B SVC_ContextSwitch .else @@ -92,7 +96,7 @@ .endif SVC_ContextSave: - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,SVC_ContextSave1 // Branch if there is no secure context PUSH {R1,R2,R3,LR} // Save registers and EXC_RETURN @@ -117,7 +121,7 @@ STR R2,[R3] // osRtxInfo.thread.run: curr = next SVC_ContextRestore: - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,SVC_ContextRestore1 // Branch if there is no secure context PUSH {R2,R3} // Save registers @@ -132,7 +136,7 @@ LDR R0,[R2,#TCB_SP_OFS] // Load SP ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 TST LR,#0x40 // Check domain of interrupted thread BNE SVC_ContextRestore2 // Branch if secure .endif @@ -151,21 +155,19 @@ BX LR // Exit from handler SVC_User: - PUSH {R4,LR} // Save registers LDR R2,=osRtxUserSVC // Load address of SVC table LDR R3,[R2] // Load SVC maximum number CMP R1,R3 // Check SVC number range - BHI SVC_Done // Branch if out of range + BHI SVC_Exit // Branch if out of range - LDR R4,[R2,R1,LSL #2] // Load address of SVC function - + PUSH {R0,LR} // Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] // Load address of SVC function LDM R0,{R0-R3} // Load function parameters from stack - BLX R4 // Call service function - MRS R4,PSP // Get PSP - STR R0,[R4] // Store function return value + BLX R12 // Call service function + POP {R12,LR} // Restore SP and EXC_RETURN + STR R0,[R12] // Store function return value -SVC_Done: - POP {R4,PC} // Return from handler + BX LR // Return from handler .fnend .size SVC_Handler, .-SVC_Handler @@ -178,9 +180,9 @@ .cantunwind PendSV_Handler: - PUSH {R4,LR} // Save EXC_RETURN + PUSH {R0,LR} // Save EXC_RETURN BL osRtxPendSV_Handler // Call osRtxPendSV_Handler - POP {R4,LR} // Restore EXC_RETURN + POP {R0,LR} // Restore EXC_RETURN B Sys_Context .fnend @@ -194,9 +196,9 @@ .cantunwind SysTick_Handler: - PUSH {R4,LR} // Save EXC_RETURN + PUSH {R0,LR} // Save EXC_RETURN BL osRtxTick_Handler // Call osRtxTick_Handler - POP {R4,LR} // Restore EXC_RETURN + POP {R0,LR} // Restore EXC_RETURN B Sys_Context .fnend @@ -217,7 +219,7 @@ BXEQ LR // Exit when threads are the same Sys_ContextSave: - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,Sys_ContextSave1 // Branch if there is no secure context PUSH {R1,R2,R3,LR} // Save registers and EXC_RETURN @@ -246,7 +248,7 @@ STR R2,[R3] // osRtxInfo.run: curr = next Sys_ContextRestore: - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,Sys_ContextRestore1 // Branch if there is no secure context PUSH {R2,R3} // Save registers @@ -261,7 +263,7 @@ LDR R0,[R2,#TCB_SP_OFS] // Load SP ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN - .if __DOMAIN_NS == 1 + .if DOMAIN_NS == 1 TST LR,#0x40 // Check domain of interrupted thread BNE Sys_ContextRestore2 // Branch if secure .endif diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S index b38f9d5..118f9ea 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -49,15 +49,19 @@ .cantunwind SVC_Handler: - MRS R0,PSP // Get PSP + TST LR,#0x04 // Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP // Get MSP if return stack is MSP + MRSNE R0,PSP // Get PSP if return stack is PSP + LDR R1,[R0,#24] // Load saved PC from stack LDRB R1,[R1,#-2] // Load SVC number CBNZ R1,SVC_User // Branch if not SVC 0 - PUSH {R0,LR} // Save PSP and EXC_RETURN + PUSH {R0,LR} // Save SP and EXC_RETURN LDM R0,{R0-R3,R12} // Load function parameters and address from stack BLX R12 // Call service function - POP {R12,LR} // Restore PSP and EXC_RETURN + POP {R12,LR} // Restore SP and EXC_RETURN STM R12,{R0-R1} // Store function return values SVC_Context: @@ -73,7 +77,7 @@ #ifdef __FPU_PRESENT LDR R1,=0xE000EF34 // FPCCR Address LDR R0,[R1] // Load FPCCR - BIC R0,#1 // Clear LSPACT (Lazy state) + BIC R0,R0,#1 // Clear LSPACT (Lazy state) STR R0,[R1] // Store FPCCR B SVC_ContextSwitch #endif @@ -124,21 +128,19 @@ BX LR // Exit from handler SVC_User: - PUSH {R4,LR} // Save registers LDR R2,=osRtxUserSVC // Load address of SVC table LDR R3,[R2] // Load SVC maximum number CMP R1,R3 // Check SVC number range - BHI SVC_Done // Branch if out of range + BHI SVC_Exit // Branch if out of range - LDR R4,[R2,R1,LSL #2] // Load address of SVC function - + PUSH {R0,LR} // Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] // Load address of SVC function LDM R0,{R0-R3} // Load function parameters from stack - BLX R4 // Call service function - MRS R4,PSP // Get PSP - STR R0,[R4] // Store function return value + BLX R12 // Call service function + POP {R12,LR} // Restore SP and EXC_RETURN + STR R0,[R12] // Store function return value -SVC_Done: - POP {R4,PC} // Return from handler + BX LR // Return from handler .fnend .size SVC_Handler, .-SVC_Handler @@ -151,9 +153,9 @@ .cantunwind PendSV_Handler: - PUSH {R4,LR} // Save EXC_RETURN + PUSH {R0,LR} // Save EXC_RETURN BL osRtxPendSV_Handler // Call osRtxPendSV_Handler - POP {R4,LR} // Restore EXC_RETURN + POP {R0,LR} // Restore EXC_RETURN MRS R12,PSP B SVC_Context @@ -168,9 +170,9 @@ .cantunwind SysTick_Handler: - PUSH {R4,LR} // Save EXC_RETURN + PUSH {R0,LR} // Save EXC_RETURN BL osRtxTick_Handler // Call osRtxTick_Handler - POP {R4,LR} // Restore EXC_RETURN + POP {R0,LR} // Restore EXC_RETURN MRS R12,PSP B SVC_Context diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S index 5379a36..cf1487a 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S index 9d11699..3ca51f6 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -43,22 +43,27 @@ SECTION .text:CODE:NOROOT(2) -SVC_Handler +SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo + MOV R0,LR + LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP ; Branch if return stack is MSP MRS R0,PSP ; Get PSP + +SVC_Number LDR R1,[R0,#24] ; Load saved PC from stack SUBS R1,R1,#2 ; Point to SVC instruction LDRB R1,[R1] ; Load SVC number CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDMIA R0,{R0-R3} ; Load function parameters from stack BLX R7 ; Call service function - POP {R2,R3} ; Restore PSP and EXC_RETURN + POP {R2,R3} ; Restore SP and EXC_RETURN STMIA R2!,{R0-R1} ; Store function return values MOV LR,R3 ; Set EXC_RETURN @@ -73,7 +78,7 @@ SVC_ContextSave MRS R0,PSP ; Get PSP - SUBS R0,R0,#32 ; Adjust address + SUBS R0,R0,#32 ; Calculate SP STR R0,[R1,#TCB_SP_OFS] ; Store SP STMIA R0!,{R4-R7} ; Save R4..R7 MOV R4,R8 @@ -83,7 +88,7 @@ STMIA R0!,{R4-R7} ; Save R8..R11 SVC_ContextSwitch - SUBS R3,R3,#8 + SUBS R3,R3,#8 ; Adjust address STR R2,[R3] ; osRtxInfo.thread.run: curr = next SVC_ContextRestore @@ -102,29 +107,33 @@ MVNS R0,R0 ; Set EXC_RETURN value BX R0 ; Exit from handler +SVC_MSP + MRS R0,MSP ; Get MSP + B SVC_Number + SVC_Exit BX LR ; Exit from handler SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range + PUSH {R0,LR} ; Save SP and EXC_RETURN LSLS R1,R1,#2 - LDR R4,[R2,R1] ; Load address of SVC function - + LDR R3,[R2,R1] ; Load address of SVC function + MOV R12,R3 LDMIA R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STMIA R4!,{R0-R3} ; Store function return values + BLX R12 ; Call service function + POP {R2,R3} ; Restore SP and EXC_RETURN + STR R0,[R2] ; Store function return value + MOV LR,R3 ; Set EXC_RETURN -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler -PendSV_Handler +PendSV_Handler EXPORT PendSV_Handler IMPORT osRtxPendSV_Handler @@ -135,7 +144,7 @@ B SVC_Context -SysTick_Handler +SysTick_Handler EXPORT SysTick_Handler IMPORT osRtxTick_Handler diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S index 9d11699..3ca51f6 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -43,22 +43,27 @@ SECTION .text:CODE:NOROOT(2) -SVC_Handler +SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo + MOV R0,LR + LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP ; Branch if return stack is MSP MRS R0,PSP ; Get PSP + +SVC_Number LDR R1,[R0,#24] ; Load saved PC from stack SUBS R1,R1,#2 ; Point to SVC instruction LDRB R1,[R1] ; Load SVC number CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDMIA R0,{R0-R3} ; Load function parameters from stack BLX R7 ; Call service function - POP {R2,R3} ; Restore PSP and EXC_RETURN + POP {R2,R3} ; Restore SP and EXC_RETURN STMIA R2!,{R0-R1} ; Store function return values MOV LR,R3 ; Set EXC_RETURN @@ -73,7 +78,7 @@ SVC_ContextSave MRS R0,PSP ; Get PSP - SUBS R0,R0,#32 ; Adjust address + SUBS R0,R0,#32 ; Calculate SP STR R0,[R1,#TCB_SP_OFS] ; Store SP STMIA R0!,{R4-R7} ; Save R4..R7 MOV R4,R8 @@ -83,7 +88,7 @@ STMIA R0!,{R4-R7} ; Save R8..R11 SVC_ContextSwitch - SUBS R3,R3,#8 + SUBS R3,R3,#8 ; Adjust address STR R2,[R3] ; osRtxInfo.thread.run: curr = next SVC_ContextRestore @@ -102,29 +107,33 @@ MVNS R0,R0 ; Set EXC_RETURN value BX R0 ; Exit from handler +SVC_MSP + MRS R0,MSP ; Get MSP + B SVC_Number + SVC_Exit BX LR ; Exit from handler SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range + PUSH {R0,LR} ; Save SP and EXC_RETURN LSLS R1,R1,#2 - LDR R4,[R2,R1] ; Load address of SVC function - + LDR R3,[R2,R1] ; Load address of SVC function + MOV R12,R3 LDMIA R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STMIA R4!,{R0-R3} ; Store function return values + BLX R12 ; Call service function + POP {R2,R3} ; Restore SP and EXC_RETURN + STR R0,[R2] ; Store function return value + MOV LR,R3 ; Set EXC_RETURN -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler -PendSV_Handler +PendSV_Handler EXPORT PendSV_Handler IMPORT osRtxPendSV_Handler @@ -135,7 +144,7 @@ B SVC_Context -SysTick_Handler +SysTick_Handler EXPORT SysTick_Handler IMPORT osRtxTick_Handler diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S index a10f20e..ec38438 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2016-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -24,8 +24,8 @@ ; */ -#ifndef __DOMAIN_NS -#define __DOMAIN_NS 0 +#ifndef DOMAIN_NS +#define DOMAIN_NS 0 #endif I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset @@ -43,8 +43,7 @@ irqRtxLib DCB 0 ; Non weak library reference - SECTION .text:CODE:NOROOT(2) - + SECTION .text:CODE:NOROOT(2) THUMB @@ -52,22 +51,27 @@ EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S -#endif + #endif + MOV R0,LR + LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP ; Branch if return stack is MSP MRS R0,PSP ; Get PSP + +SVC_Number LDR R1,[R0,#24] ; Load saved PC from stack SUBS R1,R1,#2 ; Point to SVC instruction LDRB R1,[R1] ; Load SVC number CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDM R0,{R0-R3} ; Load function parameters from stack BLX R7 ; Call service function - POP {R2,R3} ; Restore PSP and EXC_RETURN + POP {R2,R3} ; Restore SP and EXC_RETURN STMIA R2!,{R0-R1} ; Store function return values MOV LR,R3 ; Set EXC_RETURN @@ -80,7 +84,7 @@ CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted SVC_ContextSave -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,R7} ; Save registers @@ -88,11 +92,11 @@ BL TZ_StoreContext_S ; Store secure context MOV LR,R7 ; Set EXC_RETURN POP {R1,R2,R3,R7} ; Restore registers -#endif + #endif SVC_ContextSave1 MRS R0,PSP ; Get PSP - SUBS R0,R0,#32 ; Adjust PSP + SUBS R0,R0,#32 ; Calculate SP STR R0,[R1,#TCB_SP_OFS] ; Store SP STMIA R0!,{R4-R7} ; Save R4..R7 MOV R4,R8 @@ -111,13 +115,13 @@ STR R2,[R3] ; osRtxInfo.thread.run: curr = next SVC_ContextRestore -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers BL TZ_LoadContext_S ; Load secure context POP {R2,R3} ; Restore registers -#endif + #endif SVC_ContextRestore1 MOV R1,R2 @@ -128,16 +132,16 @@ ORRS R0,R1 MOV LR,R0 ; Set EXC_RETURN -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) LSLS R0,R0,#25 ; Check domain of interrupted thread BPL SVC_ContextRestore2 ; Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] ; Load SP MSR PSP,R0 ; Set PSP BX LR ; Exit from handler -#else + #else LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base MSR PSPLIM,R0 ; Set PSPLIM -#endif + #endif SVC_ContextRestore2 LDR R0,[R2,#TCB_SP_OFS] ; Load SP @@ -154,23 +158,27 @@ SVC_Exit BX LR ; Exit from handler +SVC_MSP + MRS R0,MSP ; Get MSP + B SVC_Number + SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range + PUSH {R0,LR} ; Save SP and EXC_RETURN LSLS R1,R1,#2 - LDR R4,[R2,R1] ; Load address of SVC function + LDR R3,[R2,R1] ; Load address of SVC function + MOV R12,R3 + LDMIA R0,{R0-R3} ; Load function parameters from stack + BLX R12 ; Call service function + POP {R2,R3} ; Restore SP and EXC_RETURN + STR R0,[R2] ; Store function return value + MOV LR,R3 ; Set EXC_RETURN - LDM R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STR R0,[R4] ; Store function return value - -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler PendSV_Handler @@ -199,10 +207,10 @@ Sys_Context EXPORT Sys_Context IMPORT osRtxInfo -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S -#endif + #endif LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDM R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next @@ -210,7 +218,7 @@ BEQ Sys_ContextExit ; Branch when threads are the same Sys_ContextSave -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,R7} ; Save registers @@ -220,11 +228,11 @@ POP {R1,R2,R3,R7} ; Restore registers MOV R0,LR ; Get EXC_RETURN LSLS R0,R0,#25 ; Check domain of interrupted thread - BPL Sys_ContextSave1 ; Branch if not secure + BPL Sys_ContextSave1 ; Branch if non-secure MRS R0,PSP ; Get PSP STR R0,[R1,#TCB_SP_OFS] ; Store SP B Sys_ContextSave2 -#endif + #endif Sys_ContextSave1 MRS R0,PSP ; Get PSP @@ -247,13 +255,13 @@ STR R2,[R3] ; osRtxInfo.run: curr = next Sys_ContextRestore -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers BL TZ_LoadContext_S ; Load secure context POP {R2,R3} ; Restore registers -#endif + #endif Sys_ContextRestore1 MOV R1,R2 @@ -264,16 +272,16 @@ ORRS R0,R1 MOV LR,R0 ; Set EXC_RETURN -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) LSLS R0,R0,#25 ; Check domain of interrupted thread BPL Sys_ContextRestore2 ; Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] ; Load SP MSR PSP,R0 ; Set PSP BX LR ; Exit from handler -#else + #else LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base MSR PSPLIM,R0 ; Set PSPLIM -#endif + #endif Sys_ContextRestore2 LDR R0,[R2,#TCB_SP_OFS] ; Load SP diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S index 0bffcb3..29fe1b7 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -43,20 +43,24 @@ SECTION .text:CODE:NOROOT(2) -SVC_Handler +SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo - MRS R0,PSP ; Get PSP + TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP ; Get MSP if return stack is MSP + MRSNE R0,PSP ; Get PSP if return stack is PSP + LDR R1,[R0,#24] ; Load saved PC from stack LDRB R1,[R1,#-2] ; Load SVC number CBNZ R1,SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDM R0,{R0-R3,R12} ; Load function parameters and address from stack BLX R12 ; Call service function - POP {R12,LR} ; Restore PSP and EXC_RETURN + POP {R12,LR} ; Restore SP and EXC_RETURN STM R12,{R0-R1} ; Store function return values SVC_Context @@ -86,41 +90,39 @@ BX LR ; Exit from handler SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range - LDR R4,[R2,R1,LSL #2] ; Load address of SVC function - + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] ; Load address of SVC function LDM R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STR R0,[R4] ; Store function return value + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STR R0,[R12] ; Store function return value -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler -PendSV_Handler +PendSV_Handler EXPORT PendSV_Handler IMPORT osRtxPendSV_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN MRS R12,PSP B SVC_Context -SysTick_Handler +SysTick_Handler EXPORT SysTick_Handler IMPORT osRtxTick_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxTick_Handler ; Call osRtxTick_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN MRS R12,PSP B SVC_Context diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S index 5edbf07..629bfe9 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2016-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -24,9 +24,8 @@ ; */ - -#ifndef __DOMAIN_NS -#define __DOMAIN_NS 0 +#ifndef DOMAIN_NS +#define DOMAIN_NS 0 #endif #ifdef __ARMVFP__ @@ -45,12 +44,12 @@ PRESERVE8 - SECTION .rodata:DATA:NOROOT(2) + SECTION .rodata:DATA:NOROOT(2) EXPORT irqRtxLib irqRtxLib DCB 0 ; Non weak library reference - SECTION .text:CODE:NOROOT(2) + SECTION .text:CODE:NOROOT(2) THUMB @@ -58,21 +57,25 @@ EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S -#endif + #endif - MRS R0,PSP ; Get PSP + TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP ; Get MSP if return stack is MSP + MRSNE R0,PSP ; Get PSP if return stack is PSP + LDR R1,[R0,#24] ; Load saved PC from stack LDRB R1,[R1,#-2] ; Load SVC number CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDM R0,{R0-R3,R12} ; Load function parameters and address from stack BLX R12 ; Call service function - POP {R12,LR} ; Restore PSP and EXC_RETURN + POP {R12,LR} ; Restore SP and EXC_RETURN STM R12,{R0-R1} ; Store function return values SVC_Context @@ -82,35 +85,36 @@ IT EQ BXEQ LR ; Exit when threads are the same -#if (__FPU_USED == 1) + #if (__FPU_USED == 1) CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted TST LR,#0x10 ; Check if extended stack frame BNE SVC_ContextSwitch LDR R1,=0xE000EF34 ; FPCCR Address LDR R0,[R1] ; Load FPCCR - BIC R0,#1 ; Clear LSPACT (Lazy state) + BIC R0,R0,#1 ; Clear LSPACT (Lazy state) STR R0,[R1] ; Store FPCCR B SVC_ContextSwitch -#else + #else CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted -#endif + #endif SVC_ContextSave -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN BL TZ_StoreContext_S ; Store secure context POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN -#endif + #endif SVC_ContextSave1 MRS R0,PSP ; Get PSP STMDB R0!,{R4-R11} ; Save R4..R11 -#if (__FPU_USED == 1) + #if (__FPU_USED == 1) TST LR,#0x10 ; Check if extended stack frame + IT EQ VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 -#endif + #endif SVC_ContextSave2 STR R0,[R1,#TCB_SP_OFS] ; Store SP @@ -120,13 +124,13 @@ STR R2,[R3] ; osRtxInfo.thread.run: curr = next SVC_ContextRestore -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers BL TZ_LoadContext_S ; Load secure context POP {R2,R3} ; Restore registers -#endif + #endif SVC_ContextRestore1 LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base @@ -135,15 +139,16 @@ LDR R0,[R2,#TCB_SP_OFS] ; Load SP ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) TST LR,#0x40 ; Check domain of interrupted thread BNE SVC_ContextRestore2 ; Branch if secure -#endif + #endif -#if (__FPU_USED == 1) + #if (__FPU_USED == 1) TST LR,#0x10 ; Check if extended stack frame + IT EQ VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 -#endif + #endif LDMIA R0!,{R4-R11} ; Restore R4..R11 SVC_ContextRestore2 @@ -153,30 +158,28 @@ BX LR ; Exit from handler SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range - LDR R4,[R2,R1,LSL #2] ; Load address of SVC function - + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] ; Load address of SVC function LDM R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STR R0,[R4] ; Store function return value + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STR R0,[R12] ; Store function return value -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler PendSV_Handler EXPORT PendSV_Handler IMPORT osRtxPendSV_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN B Sys_Context @@ -184,9 +187,9 @@ EXPORT SysTick_Handler IMPORT osRtxTick_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxTick_Handler ; Call osRtxTick_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN B Sys_Context @@ -194,10 +197,10 @@ Sys_Context EXPORT Sys_Context IMPORT osRtxInfo -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S -#endif + #endif LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next @@ -206,7 +209,7 @@ BXEQ LR ; Exit when threads are the same Sys_ContextSave -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN @@ -216,15 +219,16 @@ IT NE MRSNE R0,PSP ; Get PSP BNE Sys_ContextSave2 ; Branch if secure -#endif + #endif Sys_ContextSave1 MRS R0,PSP ; Get PSP STMDB R0!,{R4-R11} ; Save R4..R11 -#if (__FPU_USED == 1) + #if (__FPU_USED == 1) TST LR,#0x10 ; Check if extended stack frame + IT EQ VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 -#endif + #endif Sys_ContextSave2 STR R0,[R1,#TCB_SP_OFS] ; Store SP @@ -234,13 +238,13 @@ STR R2,[R3] ; osRtxInfo.run: curr = next Sys_ContextRestore -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers BL TZ_LoadContext_S ; Load secure context POP {R2,R3} ; Restore registers -#endif + #endif Sys_ContextRestore1 LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base @@ -249,15 +253,16 @@ LDR R0,[R2,#TCB_SP_OFS] ; Load SP ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN -#if (__DOMAIN_NS == 1) + #if (DOMAIN_NS == 1) TST LR,#0x40 ; Check domain of interrupted thread BNE Sys_ContextRestore2 ; Branch if secure -#endif + #endif -#if (__FPU_USED == 1) + #if (__FPU_USED == 1) TST LR,#0x10 ; Check if extended stack frame + IT EQ VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 -#endif + #endif LDMIA R0!,{R4-R11} ; Restore R4..R11 Sys_ContextRestore2 diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S index d44f401..4f8f3d4 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -43,20 +43,25 @@ THUMB SECTION .text:CODE:NOROOT(2) + SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo - MRS R0,PSP ; Get PSP + TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP ; Get MSP if return stack is MSP + MRSNE R0,PSP ; Get PSP if return stack is PSP + LDR R1,[R0,#24] ; Load saved PC from stack LDRB R1,[R1,#-2] ; Load SVC number CBNZ R1,SVC_User ; Branch if not SVC 0 - PUSH {R0,LR} ; Save PSP and EXC_RETURN + PUSH {R0,LR} ; Save SP and EXC_RETURN LDM R0,{R0-R3,R12} ; Load function parameters and address from stack BLX R12 ; Call service function - POP {R12,LR} ; Restore PSP and EXC_RETURN + POP {R12,LR} ; Restore SP and EXC_RETURN STM R12,{R0-R1} ; Store function return values SVC_Context @@ -108,41 +113,39 @@ BX LR ; Exit from handler SVC_User - PUSH {R4,LR} ; Save registers LDR R2,=osRtxUserSVC ; Load address of SVC table LDR R3,[R2] ; Load SVC maximum number CMP R1,R3 ; Check SVC number range - BHI SVC_Done ; Branch if out of range + BHI SVC_Exit ; Branch if out of range - LDR R4,[R2,R1,LSL #2] ; Load address of SVC function - + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] ; Load address of SVC function LDM R0,{R0-R3} ; Load function parameters from stack - BLX R4 ; Call service function - MRS R4,PSP ; Get PSP - STR R0,[R4] ; Store function return value + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STR R0,[R12] ; Store function return value -SVC_Done - POP {R4,PC} ; Return from handler + BX LR ; Return from handler -PendSV_Handler +PendSV_Handler EXPORT PendSV_Handler IMPORT osRtxPendSV_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN MRS R12,PSP B SVC_Context -SysTick_Handler +SysTick_Handler EXPORT SysTick_Handler IMPORT osRtxTick_Handler - PUSH {R4,LR} ; Save EXC_RETURN + PUSH {R0,LR} ; Save EXC_RETURN BL osRtxTick_Handler ; Call osRtxTick_Handler - POP {R4,LR} ; Restore EXC_RETURN + POP {R0,LR} ; Restore EXC_RETURN MRS R12,PSP B SVC_Context diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_c.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_c.h index 8b95bc3..343f316 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_c.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,37 +26,20 @@ #ifndef RTX_CORE_C_H_ #define RTX_CORE_C_H_ -#include +//lint -emacro((923,9078),SCB) "cast from unsigned long to pointer" [MISRA Note 9] +#include "RTE_Components.h" +#include CMSIS_device_header -#ifndef __ARM_ARCH_6M__ -#define __ARM_ARCH_6M__ 0U -#endif -#ifndef __ARM_ARCH_7A__ -#define __ARM_ARCH_7A__ 0U -#endif -#ifndef __ARM_ARCH_7M__ -#define __ARM_ARCH_7M__ 0U -#endif -#ifndef __ARM_ARCH_7EM__ -#define __ARM_ARCH_7EM__ 0U -#endif -#ifndef __ARM_ARCH_8M_BASE__ -#define __ARM_ARCH_8M_BASE__ 0U -#endif -#ifndef __ARM_ARCH_8M_MAIN__ -#define __ARM_ARCH_8M_MAIN__ 0U +#if ((!defined(__ARM_ARCH_6M__)) && \ + (!defined(__ARM_ARCH_7A__)) && \ + (!defined(__ARM_ARCH_7M__)) && \ + (!defined(__ARM_ARCH_7EM__)) && \ + (!defined(__ARM_ARCH_8M_BASE__)) && \ + (!defined(__ARM_ARCH_8M_MAIN__))) +#error "Unknown Arm Architecture!" #endif -#if ((__ARM_ARCH_6M__ + \ - __ARM_ARCH_7A__ + \ - __ARM_ARCH_7M__ + \ - __ARM_ARCH_7EM__ + \ - __ARM_ARCH_8M_BASE__ + \ - __ARM_ARCH_8M_MAIN__) != 1U) -#error "Unknown ARM Architecture!" -#endif - -#if (__ARM_ARCH_7A__ != 0U) +#if (defined(__ARM_ARCH_7A__) && (__ARM_ARCH_7A__ != 0)) #include "rtx_core_ca.h" #else #include "rtx_core_cm.h" diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h index 91d0179..c30dac7 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,43 +26,83 @@ #ifndef RTX_CORE_CA_H_ #define RTX_CORE_CA_H_ -#include +#ifndef RTX_CORE_C_H_ +#include "RTE_Components.h" +#include CMSIS_device_header +#endif -#define __DOMAIN_NS 0U -#define __EXCLUSIVE_ACCESS 1U +#include +typedef bool bool_t; +#define FALSE ((bool_t)0) +#define TRUE ((bool_t)1) -/* CPSR bit definitions */ +#define DOMAIN_NS 0 +#define EXCLUSIVE_ACCESS 1 + +#define OS_TICK_HANDLER osRtxTick_Handler + +// CPSR bit definitions #define CPSR_T_BIT 0x20U #define CPSR_I_BIT 0x80U #define CPSR_F_BIT 0x40U -/* CPSR mode bitmasks */ +// CPSR mode bitmasks #define CPSR_MODE_USER 0x10U #define CPSR_MODE_SYSTEM 0x1FU -/* Determine privilege level */ -#define IS_PRIVILEGED() (__get_mode() != CPSR_MODE_USER) -#define IS_IRQ_MODE() ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM)) -#define IS_IRQ_MASKED() (0U) +/// xPSR_Initialization Value +/// \param[in] privileged true=privileged, false=unprivileged +/// \param[in] thumb true=Thumb, false=Arm +/// \return xPSR Init Value +__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) { + uint32_t psr; -#define xPSR_INIT(privileged, thumb) \ - ((privileged) != 0U) ? (CPSR_MODE_SYSTEM | (((thumb) != 0U) ? CPSR_T_BIT : 0U)) : \ - (CPSR_MODE_USER | (((thumb) != 0U) ? CPSR_T_BIT : 0U)) - -#define STACK_FRAME_INIT 0x00U + if (privileged) { + if (thumb) { + psr = CPSR_MODE_SYSTEM | CPSR_T_BIT; + } else { + psr = CPSR_MODE_SYSTEM; + } + } else { + if (thumb) { + psr = CPSR_MODE_USER | CPSR_T_BIT; + } else { + psr = CPSR_MODE_USER; + } + } + + return psr; +} // Stack Frame: // - VFP-D32: D16-31, D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR // - VFP-D16: D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR // - Basic: R4-R11, R0-R3, R12, LR, PC, CPSR -#define STACK_OFFSET_R0(stack_frame) \ - ((((stack_frame) & 0x04U) != 0U) ? ((32U*8U) + (2U*4U) + (8U*4U)) : \ - (((stack_frame) & 0x02U) != 0U) ? ((16U*8U) + (2U*4U) + (8U*4U)) : \ - (8U*4U)) -#define OS_TICK_HANDLER osRtxTick_Handler +/// Stack Frame Initialization Value +#define STACK_FRAME_INIT_VAL 0x00U -/* Emulate M profile get_PSP: SP_usr - (8*4) */ +/// Stack Offset of Register R0 +/// \param[in] stack_frame Stack Frame +/// \return R0 Offset +__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) { + uint32_t offset; + + if ((stack_frame & 0x04U) != 0U) { + offset = (32U*8U) + (2U*4U) + (8U*4U); + } else if ((stack_frame & 0x02U) != 0U) { + offset = (16U*8U) + (2U*4U) + (8U*4U); + } else { + offset = (8U*4U); + } + return offset; +} + + +// ==== Emulated Cortex-M functions ==== + +/// Get xPSR Register - emulate M profile: SP_usr - (8*4) +/// \return xPSR Register value #if defined(__CC_ARM) static __asm uint32_t __get_PSP (void) { arm @@ -97,7 +137,56 @@ } #endif +/// Set Control Register - not needed for A profile +/// \param[in] control Control Register value to set __STATIC_INLINE void __set_CONTROL(uint32_t control) { + (void)control; +} + + +// ==== Core functions ==== + +/// Check if running Privileged +/// \return true=privileged, false=unprivileged +__STATIC_INLINE bool_t IsPrivileged (void) { + return (__get_mode() != CPSR_MODE_USER); +} + +/// Check if in IRQ Mode +/// \return true=IRQ, false=thread +__STATIC_INLINE bool_t IsIrqMode (void) { + return ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM)); +} + +/// Check if IRQ is Masked +/// \return true=masked, false=not masked +__STATIC_INLINE bool_t IsIrqMasked (void) { + return FALSE; +} + + +// ==== Core Peripherals functions ==== + +extern uint8_t IRQ_PendSV; + +/// Setup SVC and PendSV System Service Calls (not needed on Cortex-A) +__STATIC_INLINE void SVC_Setup (void) { +} + +/// Get Pending SV (Service Call) Flag +/// \return Pending SV Flag +__STATIC_INLINE uint8_t GetPendSV (void) { + return (IRQ_PendSV); +} + +/// Clear Pending SV (Service Call) Flag +__STATIC_INLINE void ClrPendSV (void) { + IRQ_PendSV = 0U; +} + +/// Set Pending SV (Service Call) Flag +__STATIC_INLINE void SetPendSV (void) { + IRQ_PendSV = 1U; } @@ -109,7 +198,6 @@ #define SVC0_0N(f,t) \ __SVC_INDIRECT(0) t svc##f (t(*)()); \ - t svcRtx##f (void); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (void) { \ svc##f(svcRtx##f); \ @@ -117,7 +205,6 @@ #define SVC0_0(f,t) \ __SVC_INDIRECT(0) t svc##f (t(*)()); \ - t svcRtx##f (void); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (void) { \ return svc##f(svcRtx##f); \ @@ -125,7 +212,6 @@ #define SVC0_1N(f,t,t1) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ - t svcRtx##f (t1 a1); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1) { \ svc##f(svcRtx##f,a1); \ @@ -133,7 +219,6 @@ #define SVC0_1(f,t,t1) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ - t svcRtx##f (t1 a1); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1) { \ return svc##f(svcRtx##f,a1); \ @@ -141,7 +226,6 @@ #define SVC0_2(f,t,t1,t2) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \ - t svcRtx##f (t1 a1, t2 a2); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ return svc##f(svcRtx##f,a1,a2); \ @@ -149,7 +233,6 @@ #define SVC0_3(f,t,t1,t2,t3) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ return svc##f(svcRtx##f,a1,a2,a3); \ @@ -157,21 +240,14 @@ #define SVC0_4(f,t,t1,t2,t3,t4) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ return svc##f(svcRtx##f,a1,a2,a3,a4); \ } -#define SVC0_0M SVC0_0 -#define SVC0_1M SVC0_1 -#define SVC0_2M SVC0_2 -#define SVC0_3M SVC0_3 -#define SVC0_4M SVC0_4 - #elif defined(__ICCARM__) -#define SVC_Setup(f) \ +#define SVC_ArgF(f) \ __asm( \ "mov r12,%0\n" \ :: "r"(&f): "r12" \ @@ -182,73 +258,60 @@ #define SVC0_0N(f,t) \ __SVC_INDIRECT(0) t svc##f (); \ - t svcRtx##f (void); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (void) { \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ svc##f(); \ } #define SVC0_0(f,t) \ __SVC_INDIRECT(0) t svc##f (); \ - t svcRtx##f (void); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (void) { \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ return svc##f(); \ } #define SVC0_1N(f,t,t1) \ __SVC_INDIRECT(0) t svc##f (t1 a1); \ - t svcRtx##f (t1 a1); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1) { \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ svc##f(a1); \ } #define SVC0_1(f,t,t1) \ __SVC_INDIRECT(0) t svc##f (t1 a1); \ - t svcRtx##f (t1 a1); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1) { \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ return svc##f(a1); \ } #define SVC0_2(f,t,t1,t2) \ __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \ - t svcRtx##f (t1 a1, t2 a2); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ return svc##f(a1,a2); \ } #define SVC0_3(f,t,t1,t2,t3) \ __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ return svc##f(a1,a2,a3); \ } #define SVC0_4(f,t,t1,t2,t3,t4) \ __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ return svc##f(a1,a2,a3,a4); \ } -#define SVC0_0M SVC0_0 -#define SVC0_1M SVC0_1 -#define SVC0_2M SVC0_2 -#define SVC0_3M SVC0_3 -#define SVC0_4M SVC0_4 - #else // !(defined(__CC_ARM) || defined(__ICCARM__)) #define SVC_RegF "r12" @@ -270,7 +333,6 @@ #define SVC_Out0 #define SVC_Out1 "=r"(__r0) -#define SVC_Out2 "=r"(__r0),"=r"(__r1) #define SVC_CL0 #define SVC_CL1 "r1" @@ -345,43 +407,12 @@ return (t) __r0; \ } -#define SVC0_0M SVC0_0 -#define SVC0_1M SVC0_1 -#define SVC0_2M SVC0_2 -#define SVC0_3M SVC0_3 -#define SVC0_4M SVC0_4 - #endif -// ==== Core Peripherals functions ==== - -extern uint8_t IRQ_PendSV; - -/// Initialize SVC and PendSV System Service Calls (not needed on Cortex-A) -__STATIC_INLINE void SVC_Initialize (void) { -} - -/// Get Pending SV (Service Call) Flag -/// \return Pending SV Flag -__STATIC_INLINE uint8_t GetPendSV (void) { - return (IRQ_PendSV); -} - -/// Clear Pending SV (Service Call) Flag -__STATIC_INLINE void ClrPendSV (void) { - IRQ_PendSV = 0U; -} - -/// Set Pending SV (Service Call) Flag -__STATIC_INLINE void SetPendSV (void) { - IRQ_PendSV = 1U; -} - - // ==== Exclusive Access Operation ==== -#if (__EXCLUSIVE_ACCESS == 1U) +#if (EXCLUSIVE_ACCESS == 1) /// Atomic Access Operation: Write (8-bit) /// \param[in] mem Memory address @@ -1098,7 +1129,7 @@ } #endif -#endif // (__EXCLUSIVE_ACCESS == 1U) +#endif // (EXCLUSIVE_ACCESS == 1) #endif // RTX_CORE_CA_H_ diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h index fafe098..f0b4dc1 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,96 +26,188 @@ #ifndef RTX_CORE_CM_H_ #define RTX_CORE_CM_H_ -#include - -#ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS -#define __DOMAIN_NS 1U +#ifndef RTX_CORE_C_H_ +#include "RTE_Components.h" +#include CMSIS_device_header #endif -#ifndef __DOMAIN_NS -#define __DOMAIN_NS 0U -#elif ((__DOMAIN_NS == 1U) && \ - ((__ARM_ARCH_6M__ == 1U) || \ - (__ARM_ARCH_7M__ == 1U) || \ - (__ARM_ARCH_7EM__ == 1U))) +#include +typedef bool bool_t; +#define FALSE (0) +#define TRUE (1) + +#ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS +#define DOMAIN_NS 1 +#endif + +#ifndef DOMAIN_NS +#define DOMAIN_NS 0 +#endif + +#if (DOMAIN_NS == 1) +#if ((!defined(__ARM_ARCH_8M_BASE__) || (__ARM_ARCH_8M_BASE__ == 0)) && \ + (!defined(__ARM_ARCH_8M_MAIN__) || (__ARM_ARCH_8M_MAIN__ == 0))) #error "Non-secure domain requires ARMv8-M Architecture!" #endif - -#ifndef __EXCLUSIVE_ACCESS -#if ((__ARM_ARCH_7M__ == 1U) || \ - (__ARM_ARCH_7EM__ == 1U) || \ - (__ARM_ARCH_8M_BASE__ == 1U) || \ - (__ARM_ARCH_8M_MAIN__ == 1U)) -#define __EXCLUSIVE_ACCESS 1U -#else -#define __EXCLUSIVE_ACCESS 0U -#endif #endif -#define IS_PRIVILEGED() ((__get_CONTROL() & 1U) == 0U) - -#define IS_IRQ_MODE() (__get_IPSR() != 0U) - -#if ((__ARM_ARCH_7M__ == 1U) || \ - (__ARM_ARCH_7EM__ == 1U) || \ - (__ARM_ARCH_8M_MAIN__ == 1U)) -#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U)) +#ifndef EXCLUSIVE_ACCESS +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0))) +#define EXCLUSIVE_ACCESS 1 #else -#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) +#define EXCLUSIVE_ACCESS 0 #endif - -#define xPSR_INIT(...) 0x01000000U - -#if (__DOMAIN_NS == 1U) -#define STACK_FRAME_INIT 0xBCU -#else -#define STACK_FRAME_INIT 0xFDU -#endif - -// Stack Frame: -// - Extended: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR -// - Basic: R4-R11, R0-R3, R12, LR, PC, xPSR -#if (__FPU_USED == 1U) -#define STACK_OFFSET_R0(stack_frame) \ - ((((stack_frame) & 0x10U) == 0U) ? ((16U+8U)*4U) : \ - (8U *4U)) -#else -#define STACK_OFFSET_R0(stack_frame) (8U *4U) #endif #define OS_TICK_HANDLER SysTick_Handler +/// xPSR_Initialization Value +/// \param[in] privileged true=privileged, false=unprivileged +/// \param[in] thumb true=Thumb, false=ARM +/// \return xPSR Init Value +__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) { + (void)privileged; + (void)thumb; + return (0x01000000U); +} + +// Stack Frame: +// - Extended: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR +// - Basic: R4-R11, R0-R3, R12, LR, PC, xPSR + +/// Stack Frame Initialization Value (EXC_RETURN[7..0]) +#if (DOMAIN_NS == 1) +#define STACK_FRAME_INIT_VAL 0xBCU +#else +#define STACK_FRAME_INIT_VAL 0xFDU +#endif + +/// Stack Offset of Register R0 +/// \param[in] stack_frame Stack Frame (EXC_RETURN[7..0]) +/// \return R0 Offset +__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) { +#if (__FPU_USED == 1U) + return (((stack_frame & 0x10U) == 0U) ? ((16U+8U)*4U) : (8U*4U)); +#else + (void)stack_frame; + return (8U*4U); +#endif +} + + +// ==== Core functions ==== + +//lint -sem(__get_CONTROL, pure) +//lint -sem(__get_IPSR, pure) +//lint -sem(__get_PRIMASK, pure) +//lint -sem(__get_BASEPRI, pure) + +/// Check if running Privileged +/// \return true=privileged, false=unprivileged +__STATIC_INLINE bool_t IsPrivileged (void) { + return ((__get_CONTROL() & 1U) == 0U); +} + +/// Check if in IRQ Mode +/// \return true=IRQ, false=thread +__STATIC_INLINE bool_t IsIrqMode (void) { + return (__get_IPSR() != 0U); +} + +/// Check if IRQ is Masked +/// \return true=masked, false=not masked +__STATIC_INLINE bool_t IsIrqMasked (void) { +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0))) + return ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U)); +#else + return (__get_PRIMASK() != 0U); +#endif +} + + +// ==== Core Peripherals functions ==== + +/// Setup SVC and PendSV System Service Calls +__STATIC_INLINE void SVC_Setup (void) { +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__CORTEX_M) && (__CORTEX_M == 7U))) + uint32_t p, n; + + SCB->SHPR[10] = 0xFFU; + n = 32U - (uint32_t)__CLZ(~(SCB->SHPR[10] | 0xFFFFFF00U)); + p = NVIC_GetPriorityGrouping(); + if (p >= n) { + n = p + 1U; + } + SCB->SHPR[7] = (uint8_t)(0xFEU << n); +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + uint32_t n; + + SCB->SHPR[1] |= 0x00FF0000U; + n = SCB->SHPR[1]; + SCB->SHPR[0] |= (n << (8+1)) & 0xFC000000U; +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0))) + uint32_t p, n; + + SCB->SHP[10] = 0xFFU; + n = 32U - (uint32_t)__CLZ(~(SCB->SHP[10] | 0xFFFFFF00U)); + p = NVIC_GetPriorityGrouping(); + if (p >= n) { + n = p + 1U; + } + /* Only change the SVCall priority if uVisor is not present. */ + #if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) + SCB->SHP[7] = (uint8_t)(0xFEU << n); + #endif +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) + uint32_t n; + + SCB->SHP[1] |= 0x00FF0000U; + n = SCB->SHP[1]; + SCB->SHP[0] |= (n << (8+1)) & 0xFC000000U; +#endif +} + +/// Get Pending SV (Service Call) Flag +/// \return Pending SV Flag +__STATIC_INLINE uint8_t GetPendSV (void) { + return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24)); +} + +/// Clear Pending SV (Service Call) Flag +__STATIC_INLINE void ClrPendSV (void) { + SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk; +} + +/// Set Pending SV (Service Call) Flag +__STATIC_INLINE void SetPendSV (void) { + SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; +} + // ==== Service Calls definitions ==== +//lint -save -e9023 -e9024 -e9026 "Function-like macros using '#/##'" [MISRA Note 10] + #if defined(__CC_ARM) -#if ((__ARM_ARCH_7M__ == 1U) || \ - (__ARM_ARCH_7EM__ == 1U) || \ - (__ARM_ARCH_8M_MAIN__ == 1U)) +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0))) #define __SVC_INDIRECT(n) __svc_indirect(n) -#elif ((__ARM_ARCH_6M__ == 1U) || \ - (__ARM_ARCH_8M_BASE__ == 1U)) +#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))) #define __SVC_INDIRECT(n) __svc_indirect_r7(n) #endif -#if (__FPU_USED == 1U) -#define SVC_SETUP_PSP \ - uint32_t control = __get_CONTROL(); \ - if ((control & 2U) == 0U) { \ - __set_PSP((__get_MSP() - ((control & 4U) ? 104U : 32U)) & ~7U); \ - } -#else -#define SVC_SETUP_PSP \ - uint32_t control = __get_CONTROL(); \ - if ((control & 2U) == 0U) { \ - __set_PSP((__get_MSP() - 32U) & ~7U); \ - } -#endif - #define SVC0_0N(f,t) \ __SVC_INDIRECT(0) t svc##f (t(*)()); \ - t svcRtx##f (void); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (void) { \ svc##f(svcRtx##f); \ @@ -123,24 +215,13 @@ #define SVC0_0(f,t) \ __SVC_INDIRECT(0) t svc##f (t(*)()); \ - t svcRtx##f (void); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (void) { \ return svc##f(svcRtx##f); \ } -#define SVC0_0M(f,t) \ -__SVC_INDIRECT(0) t svc##f (t(*)()); \ - t svcRtx##f (void); \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (void) { \ - SVC_SETUP_PSP \ - return svc##f(svcRtx##f); \ -} - #define SVC0_1N(f,t,t1) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ - t svcRtx##f (t1 a1); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1) { \ svc##f(svcRtx##f,a1); \ @@ -148,85 +229,45 @@ #define SVC0_1(f,t,t1) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ - t svcRtx##f (t1 a1); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1) { \ return svc##f(svcRtx##f,a1); \ } -#define SVC0_1M(f,t,t1) \ -__SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ - t svcRtx##f (t1 a1); \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1) { \ - SVC_SETUP_PSP \ - return svc##f(svcRtx##f,a1); \ -} - #define SVC0_2(f,t,t1,t2) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \ - t svcRtx##f (t1 a1, t2 a2); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ return svc##f(svcRtx##f,a1,a2); \ } -#define SVC0_2M(f,t,t1,t2) \ -__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \ - t svcRtx##f (t1 a1, t2 a2); \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ - SVC_SETUP_PSP \ - return svc##f(svcRtx##f,a1,a2); \ -} - #define SVC0_3(f,t,t1,t2,t3) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ return svc##f(svcRtx##f,a1,a2,a3); \ } -#define SVC0_3M(f,t,t1,t2,t3) \ -__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3); \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ - SVC_SETUP_PSP \ - return svc##f(svcRtx##f,a1,a2,a3); \ -} - #define SVC0_4(f,t,t1,t2,t3,t4) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ return svc##f(svcRtx##f,a1,a2,a3,a4); \ } -#define SVC0_4M(f,t,t1,t2,t3,t4) \ -__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ - SVC_SETUP_PSP \ - return svc##f(svcRtx##f,a1,a2,a3,a4); \ -} - #elif defined(__ICCARM__) -#if ((__ARM_ARCH_7M__ == 1U) || \ - (__ARM_ARCH_7EM__ == 1U) || \ - (__ARM_ARCH_8M_MAIN__ == 1U)) -#define SVC_Setup(f) \ +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0))) +#define SVC_ArgF(f) \ __asm( \ "mov r12,%0\n" \ :: "r"(&f): "r12" \ ); -#elif ((__ARM_ARCH_6M__ == 1U) || \ - (__ARM_ARCH_8M_BASE__ == 1U)) -#define SVC_Setup(f) \ +#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))) +#define SVC_ArgF(f) \ __asm( \ "mov r7,%0\n" \ :: "r"(&f): "r7" \ @@ -236,141 +277,72 @@ #define STRINGIFY(a) #a #define __SVC_INDIRECT(n) _Pragma(STRINGIFY(swi_number = n)) __swi -#if (__FPU_USED == 1U) -#define SVC_SETUP_PSP \ - uint32_t control = __get_CONTROL(); \ - if ((control & 2U) == 0U) { \ - __set_PSP((__get_MSP() - ((control & 4U) ? 104U : 32U)) & ~7U); \ - } -#else -#define SVC_SETUP_PSP \ - uint32_t control = __get_CONTROL(); \ - if ((control & 2U) == 0U) { \ - __set_PSP((__get_MSP() - 32U) & ~7U); \ - } -#endif - #define SVC0_0N(f,t) \ __SVC_INDIRECT(0) t svc##f (); \ - t svcRtx##f (void); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (void) { \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ svc##f(); \ } #define SVC0_0(f,t) \ __SVC_INDIRECT(0) t svc##f (); \ - t svcRtx##f (void); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (void) { \ - SVC_Setup(svcRtx##f); \ - return svc##f(); \ -} - -#define SVC0_0M(f,t) \ -__SVC_INDIRECT(0) t svc##f (); \ - t svcRtx##f (void); \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (void) { \ - SVC_SETUP_PSP \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ return svc##f(); \ } #define SVC0_1N(f,t,t1) \ __SVC_INDIRECT(0) t svc##f (t1 a1); \ - t svcRtx##f (t1 a1); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1) { \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ svc##f(a1); \ } #define SVC0_1(f,t,t1) \ __SVC_INDIRECT(0) t svc##f (t1 a1); \ - t svcRtx##f (t1 a1); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1) { \ - SVC_Setup(svcRtx##f); \ - return svc##f(a1); \ -} - -#define SVC0_1M(f,t,t1) \ -__SVC_INDIRECT(0) t svc##f (t1 a1); \ - t svcRtx##f (t1 a1); \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1) { \ - SVC_SETUP_PSP \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ return svc##f(a1); \ } #define SVC0_2(f,t,t1,t2) \ __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \ - t svcRtx##f (t1 a1, t2 a2); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ - SVC_Setup(svcRtx##f); \ - return svc##f(a1,a2); \ -} - -#define SVC0_2M(f,t,t1,t2) \ -__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \ - t svcRtx##f (t1 a1, t2 a2); \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ - SVC_SETUP_PSP \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ return svc##f(a1,a2); \ } #define SVC0_3(f,t,t1,t2,t3) \ __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ - SVC_Setup(svcRtx##f); \ - return svc##f(a1,a2,a3); \ -} - -#define SVC0_3M(f,t,t1,t2,t3) \ -__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3); \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ - SVC_SETUP_PSP \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ return svc##f(a1,a2,a3); \ } #define SVC0_4(f,t,t1,t2,t3,t4) \ __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ - SVC_Setup(svcRtx##f); \ - return svc##f(a1,a2,a3,a4); \ -} - -#define SVC0_4M(f,t,t1,t2,t3,t4) \ -__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \ - t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ - SVC_SETUP_PSP \ - SVC_Setup(svcRtx##f); \ + SVC_ArgF(svcRtx##f); \ return svc##f(a1,a2,a3,a4); \ } #else // !(defined(__CC_ARM) || defined(__ICCARM__)) -#if ((__ARM_ARCH_7M__ == 1U) || \ - (__ARM_ARCH_7EM__ == 1U) || \ - (__ARM_ARCH_8M_MAIN__ == 1U)) +//lint -esym(522,__svc*) "Functions '__svc*' are impure (side-effects)" + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0))) #define SVC_RegF "r12" -#elif ((__ARM_ARCH_6M__ == 1U) || \ - (__ARM_ARCH_8M_BASE__ == 1U)) +#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))) #define SVC_RegF "r7" #endif @@ -391,7 +363,6 @@ #define SVC_Out0 #define SVC_Out1 "=r"(__r0) -#define SVC_Out2 "=r"(__r0),"=r"(__r1) #define SVC_CL0 #define SVC_CL1 "r1" @@ -400,62 +371,6 @@ #define SVC_Call0(in, out, cl) \ __ASM volatile ("svc 0" : out : in : cl) -#if ((__ARM_ARCH_7M__ == 1U) || \ - (__ARM_ARCH_7EM__ == 1U) || \ - (__ARM_ARCH_8M_MAIN__ == 1U)) -#if (__FPU_USED == 1U) -#define SVC_Call0M(in, out, cl) \ - register uint32_t val; \ - __ASM volatile ( \ - ".syntax unified\n\t" \ - "mrs %[val],control\n\t" \ - "tst %[val],#2\n\t" \ - "bne 0f\n\t" \ - "tst %[val],#4\n\t" \ - "mrs %[val],msp\n\t" \ - "ite eq\n\t" \ - "subeq %[val],#32\n\t" \ - "subne %[val],#104\n\t" \ - "bic %[val],#7\n\t" \ - "msr psp,%[val]\n\t" \ - "0:\n\t" \ - "svc 0" \ - : out, [val] "=&l" (val) : in : cl) -#else -#define SVC_Call0M(in, out, cl) \ - register uint32_t val; \ - __ASM volatile ( \ - ".syntax unified\n\t" \ - "mrs %[val],control\n\t" \ - "tst %[val],#2\n\t" \ - "bne 0f\n\t" \ - "mrs %[val],msp\n\t" \ - "subs %[val],#32\n\t" \ - "bic %[val],#7\n\t" \ - "msr psp,%[val]\n\t" \ - "0:\n\t" \ - "svc 0" \ - : out, [val] "=&l" (val) : in : cl) -#endif -#elif ((__ARM_ARCH_6M__ == 1U) || \ - (__ARM_ARCH_8M_BASE__ == 1U)) -#define SVC_Call0M(in, out, cl) \ - register uint32_t val; \ - __ASM volatile ( \ - ".syntax unified\n\t" \ - "mrs %[val],control\n\t" \ - "lsls %[val],#30\n\t" \ - "bmi 0f\n\t" \ - "mrs %[val],msp\n\t" \ - "subs %[val],#32\n\t" \ - "lsrs %[val],#3\n\t" \ - "lsls %[val],#3\n\t" \ - "msr psp,%[val]\n\t" \ - "0:\n\t" \ - "svc 0" \ - : out, [val] "=&l" (val) : in : cl) -#endif - #define SVC0_0N(f,t) \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (void) { \ @@ -472,15 +387,6 @@ return (t) __r0; \ } -#define SVC0_0M(f,t) \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (void) { \ - SVC_ArgN(0); \ - SVC_ArgF(svcRtx##f); \ - SVC_Call0M(SVC_In0, SVC_Out1, SVC_CL1); \ - return (t) __r0; \ -} - #define SVC0_1N(f,t,t1) \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1) { \ @@ -498,15 +404,6 @@ return (t) __r0; \ } -#define SVC0_1M(f,t,t1) \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1) { \ - SVC_ArgR(0,a1); \ - SVC_ArgF(svcRtx##f); \ - SVC_Call0M(SVC_In1, SVC_Out1, SVC_CL1); \ - return (t) __r0; \ -} - #define SVC0_2(f,t,t1,t2) \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ @@ -517,16 +414,6 @@ return (t) __r0; \ } -#define SVC0_2M(f,t,t1,t2) \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ - SVC_ArgR(0,a1); \ - SVC_ArgR(1,a2); \ - SVC_ArgF(svcRtx##f); \ - SVC_Call0M(SVC_In2, SVC_Out1, SVC_CL0); \ - return (t) __r0; \ -} - #define SVC0_3(f,t,t1,t2,t3) \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ @@ -538,17 +425,6 @@ return (t) __r0; \ } -#define SVC0_3M(f,t,t1,t2,t3) \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ - SVC_ArgR(0,a1); \ - SVC_ArgR(1,a2); \ - SVC_ArgR(2,a3); \ - SVC_ArgF(svcRtx##f); \ - SVC_Call0M(SVC_In3, SVC_Out1, SVC_CL0); \ - return (t) __r0; \ -} - #define SVC0_4(f,t,t1,t2,t3,t4) \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ @@ -561,85 +437,16 @@ return (t) __r0; \ } -#define SVC0_4M(f,t,t1,t2,t3,t4) \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ - SVC_ArgR(0,a1); \ - SVC_ArgR(1,a2); \ - SVC_ArgR(2,a3); \ - SVC_ArgR(3,a4); \ - SVC_ArgF(svcRtx##f); \ - SVC_Call0M(SVC_In4, SVC_Out1, SVC_CL0); \ - return (t) __r0; \ -} - #endif - -// ==== Core Peripherals functions ==== - -/// Initialize SVC and PendSV System Service Calls -__STATIC_INLINE void SVC_Initialize (void) { -#if ((__ARM_ARCH_8M_MAIN__ == 1U) || (defined(__CORTEX_M) && (__CORTEX_M == 7U))) - uint32_t p, n; - - SCB->SHPR[10] = 0xFFU; - n = 32U - (uint32_t)__CLZ(~(SCB->SHPR[10] | 0xFFFFFF00U)); - p = NVIC_GetPriorityGrouping(); - if (p >= n) { - n = p + 1U; - } - SCB->SHPR[7] = (uint8_t)(0xFEU << n); -#elif (__ARM_ARCH_8M_BASE__ == 1U) - uint32_t n; - - SCB->SHPR[1] |= 0x00FF0000U; - n = SCB->SHPR[1]; - SCB->SHPR[0] |= (n << (8+1)) & 0xFC000000U; -#elif ((__ARM_ARCH_7M__ == 1U) || \ - (__ARM_ARCH_7EM__ == 1U)) - uint32_t p, n; - - SCB->SHP[10] = 0xFFU; - n = 32U - (uint32_t)__CLZ(~(SCB->SHP[10] | 0xFFFFFF00U)); - p = NVIC_GetPriorityGrouping(); - if (p >= n) { - n = p + 1U; - } - - /* Only change the SVCall priority if uVisor is not present. */ - #if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) - SCB->SHP[7] = (uint8_t)(0xFEU << n); - #endif -#elif (__ARM_ARCH_6M__ == 1U) - uint32_t n; - - SCB->SHP[1] |= 0x00FF0000U; - n = SCB->SHP[1]; - SCB->SHP[0] |= (n << (8+1)) & 0xFC000000U; -#endif -} - -/// Get Pending SV (Service Call) Flag -/// \return Pending SV Flag -__STATIC_INLINE uint8_t GetPendSV (void) { - return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24)); -} - -/// Clear Pending SV (Service Call) Flag -__STATIC_INLINE void ClrPendSV (void) { - SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk; -} - -/// Set Pending SV (Service Call) Flag -__STATIC_INLINE void SetPendSV (void) { - SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; -} +//lint -restore [MISRA Note 10] // ==== Exclusive Access Operation ==== -#if (__EXCLUSIVE_ACCESS == 1U) +#if (EXCLUSIVE_ACCESS == 1) + +//lint ++flb "Library Begin" [MISRA Note 12] /// Atomic Access Operation: Write (8-bit) /// \param[in] mem Memory address @@ -721,7 +528,7 @@ #endif "1:\n\t" "ldrex %[val],[%[mem]]\n\t" -#if (__ARM_ARCH_8M_BASE__ == 1U) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) "mov %[ret],%[val]\n\t" "orrs %[ret],%[bits]\n\t" #else @@ -736,7 +543,7 @@ [res] "=&l" (res) : [mem] "l" (mem), [bits] "l" (bits) -#if (__ARM_ARCH_8M_BASE__ == 1U) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) : "memory", "cc" #else : "memory" @@ -781,7 +588,7 @@ #endif "1:\n\t" "ldrex %[ret],[%[mem]]\n\t" -#if (__ARM_ARCH_8M_BASE__ == 1U) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) "mov %[val],%[ret]\n\t" "bics %[val],%[bits]\n\t" #else @@ -796,7 +603,7 @@ [res] "=&l" (res) : [mem] "l" (mem), [bits] "l" (bits) -#if (__ARM_ARCH_8M_BASE__ == 1U) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) : "memory", "cc" #else : "memory" @@ -848,7 +655,7 @@ #endif "1:\n\t" "ldrex %[ret],[%[mem]]\n\t" -#if (__ARM_ARCH_8M_BASE__ == 1U) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) "mov %[val],%[ret]\n\t" "ands %[val],%[bits]\n\t" #else @@ -860,7 +667,7 @@ "movs %[ret],#0\n\t" "b 3f\n" "2:\n\t" -#if (__ARM_ARCH_8M_BASE__ == 1U) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) "mov %[val],%[ret]\n\t" "bics %[val],%[bits]\n\t" #else @@ -928,7 +735,7 @@ "movs %[ret],#0\n\t" "b 3f\n" "2:\n\t" -#if (__ARM_ARCH_8M_BASE__ == 1U) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) "mov %[val],%[ret]\n\t" "bics %[val],%[bits]\n\t" #else @@ -1402,7 +1209,9 @@ } #endif -#endif // (__EXCLUSIVE_ACCESS == 1U) +//lint --flb "Library End" [MISRA Note 12] + +#endif // (EXCLUSIVE_ACCESS == 1) #endif // RTX_CORE_CM_H_ diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c index 17e90c2..ada82ac 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -28,60 +28,72 @@ // ==== Service Calls ==== -// Service Calls definitions -SVC0_1(Delay, osStatus_t, uint32_t) -SVC0_1(DelayUntil, osStatus_t, uint32_t) - /// Wait for Timeout (Time Delay). /// \note API identical to osDelay -osStatus_t svcRtxDelay (uint32_t ticks) { +static osStatus_t svcRtxDelay (uint32_t ticks) { - if (ticks == 0U) { - return osOK; + if (ticks != 0U) { + if (!osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks)) { + EvrRtxThreadDelayCompleted(); + } } - osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks); - return osOK; } /// Wait until specified time. /// \note API identical to osDelayUntil -osStatus_t svcRtxDelayUntil (uint32_t ticks) { +static osStatus_t svcRtxDelayUntil (uint32_t ticks) { ticks -= osRtxInfo.kernel.tick; if (ticks == 0xFFFFFFFFU) { - EvrRtxThreadError(NULL, osErrorParameter); + EvrRtxThreadError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } - if (ticks == 0U) { - return osOK; - } - osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks); + if (ticks != 0U) { + if (!osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks)) { + EvrRtxThreadDelayCompleted(); + } + } return osOK; } +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_1(Delay, osStatus_t, uint32_t) +SVC0_1(DelayUntil, osStatus_t, uint32_t) +//lint --flb "Library End" + // ==== Public API ==== /// Wait for Timeout (Time Delay). osStatus_t osDelay (uint32_t ticks) { + osStatus_t status; + EvrRtxThreadDelay(ticks); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(NULL, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(NULL, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcDelay(ticks); } - return __svcDelay(ticks); + return status; } /// Wait until specified time. osStatus_t osDelayUntil (uint32_t ticks) { + osStatus_t status; + EvrRtxThreadDelayUntil(ticks); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(NULL, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(NULL, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcDelayUntil(ticks); } - return __svcDelayUntil(ticks); + return status; } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evflags.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evflags.c index 1c534d5..e02560a 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evflags.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evflags.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,6 +26,14 @@ #include "rtx_lib.h" +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxEventFlagsMemUsage \ +__attribute__((section(".data.os.evflags.obj"))) = +{ 0U, 0U, 0U }; +#endif + + // ==== Helper functions ==== /// Set Event Flags. @@ -33,12 +41,12 @@ /// \param[in] flags specifies the flags to set. /// \return event flags after setting. static uint32_t EventFlagsSet (os_event_flags_t *ef, uint32_t flags) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif uint32_t event_flags; -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); ef->event_flags |= flags; @@ -59,12 +67,12 @@ /// \param[in] flags specifies the flags to clear. /// \return event flags before clearing. static uint32_t EventFlagsClear (os_event_flags_t *ef, uint32_t flags) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif uint32_t event_flags; -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); event_flags = ef->event_flags; @@ -86,13 +94,13 @@ /// \param[in] options specifies flags options (osFlagsXxxx). /// \return event flags before clearing or 0 if specified flags have not been set. static uint32_t EventFlagsCheck (os_event_flags_t *ef, uint32_t flags, uint32_t options) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask; #endif uint32_t event_flags; if ((options & osFlagsNoClear) == 0U) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) primask = __get_PRIMASK(); __disable_irq(); @@ -126,16 +134,17 @@ } -// ==== Library functions ==== +// ==== Post ISR processing ==== /// Event Flags post ISR processing. /// \param[in] ef event flags object. -void osRtxEventFlagsPostProcess (os_event_flags_t *ef) { +static void osRtxEventFlagsPostProcess (os_event_flags_t *ef) { os_thread_t *thread; os_thread_t *thread_next; uint32_t event_flags; if (ef->state == osRtxObjectInactive) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } @@ -146,7 +155,7 @@ event_flags = EventFlagsCheck(ef, thread->wait_flags, thread->flags_options); if (event_flags != 0U) { osRtxThreadListRemove(thread); - osRtxThreadWaitExit(thread, event_flags, false); + osRtxThreadWaitExit(thread, event_flags, FALSE); EvrRtxEventFlagsWaitCompleted(ef, thread->wait_flags, thread->flags_options, event_flags); } thread = thread_next; @@ -156,18 +165,9 @@ // ==== Service Calls ==== -// Service Calls definitions -SVC0_1M(EventFlagsNew, osEventFlagsId_t, const osEventFlagsAttr_t *) -SVC0_1 (EventFlagsGetName, const char *, osEventFlagsId_t) -SVC0_2 (EventFlagsSet, uint32_t, osEventFlagsId_t, uint32_t) -SVC0_2 (EventFlagsClear, uint32_t, osEventFlagsId_t, uint32_t) -SVC0_1 (EventFlagsGet, uint32_t, osEventFlagsId_t) -SVC0_4 (EventFlagsWait, uint32_t, osEventFlagsId_t, uint32_t, uint32_t, uint32_t) -SVC0_1 (EventFlagsDelete, osStatus_t, osEventFlagsId_t) - /// Create and Initialize an Event Flags object. /// \note API identical to osEventFlagsNew -osEventFlagsId_t svcRtxEventFlagsNew (const osEventFlagsAttr_t *attr) { +static osEventFlagsId_t svcRtxEventFlagsNew (const osEventFlagsAttr_t *attr) { os_event_flags_t *ef; uint8_t flags; const char *name; @@ -175,15 +175,19 @@ // Process attributes if (attr != NULL) { name = attr->name; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] ef = attr->cb_mem; if (ef != NULL) { - if (((uint32_t)ef & 3U) || (attr->cb_size < sizeof(os_event_flags_t))) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)ef & 3U) != 0U) || (attr->cb_size < sizeof(os_event_flags_t))) { EvrRtxEventFlagsError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } else { if (attr->cb_size != 0U) { EvrRtxEventFlagsError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } @@ -195,49 +199,63 @@ // Allocate object memory if not provided if (ef == NULL) { if (osRtxInfo.mpi.event_flags != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] ef = osRtxMemoryPoolAlloc(osRtxInfo.mpi.event_flags); } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] ef = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_event_flags_t), 1U); } - if (ef == NULL) { - EvrRtxEventFlagsError(NULL, osErrorNoMemory); - return NULL; +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (ef != NULL) { + uint32_t used; + osRtxEventFlagsMemUsage.cnt_alloc++; + used = osRtxEventFlagsMemUsage.cnt_alloc - osRtxEventFlagsMemUsage.cnt_free; + if (osRtxEventFlagsMemUsage.max_used < used) { + osRtxEventFlagsMemUsage.max_used = used; + } } +#endif flags = osRtxFlagSystemObject; } else { flags = 0U; } - // Initialize control block - ef->id = osRtxIdEventFlags; - ef->state = osRtxObjectActive; - ef->flags = flags; - ef->name = name; - ef->thread_list = NULL; - ef->event_flags = 0U; + if (ef != NULL) { + // Initialize control block + ef->id = osRtxIdEventFlags; + ef->state = osRtxObjectActive; + ef->flags = flags; + ef->name = name; + ef->thread_list = NULL; + ef->event_flags = 0U; - // Register post ISR processing function - osRtxInfo.post_process.event_flags = osRtxEventFlagsPostProcess; + // Register post ISR processing function + osRtxInfo.post_process.event_flags = osRtxEventFlagsPostProcess; - EvrRtxEventFlagsCreated(ef); + EvrRtxEventFlagsCreated(ef, ef->name); + } else { + EvrRtxEventFlagsError(NULL, (int32_t)osErrorNoMemory); + } return ef; } /// Get name of an Event Flags object. /// \note API identical to osEventFlagsGetName -const char *svcRtxEventFlagsGetName (osEventFlagsId_t ef_id) { - os_event_flags_t *ef = (os_event_flags_t *)ef_id; +static const char *svcRtxEventFlagsGetName (osEventFlagsId_t ef_id) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); // Check parameters if ((ef == NULL) || (ef->id != osRtxIdEventFlags)) { EvrRtxEventFlagsGetName(ef, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check object state if (ef->state == osRtxObjectInactive) { EvrRtxEventFlagsGetName(ef, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -248,8 +266,8 @@ /// Set the specified Event Flags. /// \note API identical to osEventFlagsSet -uint32_t svcRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { - os_event_flags_t *ef = (os_event_flags_t *)ef_id; +static uint32_t svcRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); os_thread_t *thread; os_thread_t *thread_next; uint32_t event_flags; @@ -257,14 +275,16 @@ // Check parameters if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || - (flags & ~((1U << osRtxEventFlagsLimit) - 1U))) { - EvrRtxEventFlagsError(ef, osErrorParameter); + ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorParameter); } // Check object state if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, osErrorResource); + EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorResource); } @@ -283,7 +303,7 @@ event_flags = event_flags0; } osRtxThreadListRemove(thread); - osRtxThreadWaitExit(thread, event_flags0, false); + osRtxThreadWaitExit(thread, event_flags0, FALSE); EvrRtxEventFlagsWaitCompleted(ef, thread->wait_flags, thread->flags_options, event_flags0); } thread = thread_next; @@ -297,20 +317,22 @@ /// Clear the specified Event Flags. /// \note API identical to osEventFlagsClear -uint32_t svcRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { - os_event_flags_t *ef = (os_event_flags_t *)ef_id; +static uint32_t svcRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); uint32_t event_flags; // Check parameters if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || - (flags & ~((1U << osRtxEventFlagsLimit) - 1U))) { - EvrRtxEventFlagsError(ef, osErrorParameter); + ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorParameter); } // Check object state if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, osErrorResource); + EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorResource); } @@ -324,18 +346,20 @@ /// Get the current Event Flags. /// \note API identical to osEventFlagsGet -uint32_t svcRtxEventFlagsGet (osEventFlagsId_t ef_id) { - os_event_flags_t *ef = (os_event_flags_t *)ef_id; +static uint32_t svcRtxEventFlagsGet (osEventFlagsId_t ef_id) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); // Check parameters if ((ef == NULL) || (ef->id != osRtxIdEventFlags)) { EvrRtxEventFlagsGet(ef, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (ef->state == osRtxObjectInactive) { EvrRtxEventFlagsGet(ef, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -346,27 +370,31 @@ /// Wait for one or more Event Flags to become signaled. /// \note API identical to osEventFlagsWait -uint32_t svcRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { - os_event_flags_t *ef = (os_event_flags_t *)ef_id; +static uint32_t svcRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); os_thread_t *running_thread; uint32_t event_flags; + // Check running thread running_thread = osRtxThreadGetRunning(); if (running_thread == NULL) { EvrRtxEventFlagsError(ef, osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osError); } // Check parameters if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || - (flags & ~((1U << osRtxEventFlagsLimit) - 1U))) { - EvrRtxEventFlagsError(ef, osErrorParameter); + ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorParameter); } // Check object state if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, osErrorResource); + EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorResource); } @@ -374,41 +402,46 @@ event_flags = EventFlagsCheck(ef, flags, options); if (event_flags != 0U) { EvrRtxEventFlagsWaitCompleted(ef, flags, options, event_flags); - return event_flags; + } else { + // Check if timeout is specified + if (timeout != 0U) { + EvrRtxEventFlagsWaitPending(ef, flags, options, timeout); + // Store waiting flags and options + running_thread->wait_flags = flags; + running_thread->flags_options = (uint8_t)options; + // Suspend current Thread + if (osRtxThreadWaitEnter(osRtxThreadWaitingEventFlags, timeout)) { + osRtxThreadListPut(osRtxObject(ef), running_thread); + } else { + EvrRtxEventFlagsWaitTimeout(ef); + } + event_flags = (uint32_t)osErrorTimeout; + } else { + EvrRtxEventFlagsWaitNotCompleted(ef, flags, options); + event_flags = (uint32_t)osErrorResource; + } } - // Check if timeout is specified - if (timeout != 0U) { - EvrRtxEventFlagsWaitPending(ef, flags, options, timeout); - // Store waiting flags and options - running_thread->wait_flags = flags; - running_thread->flags_options = (uint8_t)options; - // Suspend current Thread - osRtxThreadListPut((os_object_t*)ef, running_thread); - osRtxThreadWaitEnter(osRtxThreadWaitingEventFlags, timeout); - return ((uint32_t)osErrorTimeout); - } - - EvrRtxEventFlagsWaitNotCompleted(ef, flags, options); - - return ((uint32_t)osErrorResource); + return event_flags; } /// Delete an Event Flags object. /// \note API identical to osEventFlagsDelete -osStatus_t svcRtxEventFlagsDelete (osEventFlagsId_t ef_id) { - os_event_flags_t *ef = (os_event_flags_t *)ef_id; +static osStatus_t svcRtxEventFlagsDelete (osEventFlagsId_t ef_id) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); os_thread_t *thread; // Check parameters if ((ef == NULL) || (ef->id != osRtxIdEventFlags)) { - EvrRtxEventFlagsError(ef, osErrorParameter); + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, osErrorResource); + EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -418,19 +451,22 @@ // Unblock waiting threads if (ef->thread_list != NULL) { do { - thread = osRtxThreadListGet((os_object_t*)ef); - osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, false); + thread = osRtxThreadListGet(osRtxObject(ef)); + osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE); } while (ef->thread_list != NULL); osRtxThreadDispatch(NULL); } // Free object memory - if (ef->flags & osRtxFlagSystemObject) { + if ((ef->flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.event_flags != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.event_flags, ef); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.event_flags, ef); } else { - osRtxMemoryFree(osRtxInfo.mem.common, ef); + (void)osRtxMemoryFree(osRtxInfo.mem.common, ef); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxEventFlagsMemUsage.cnt_free++; +#endif } EvrRtxEventFlagsDestroyed(ef); @@ -438,6 +474,17 @@ return osOK; } +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_1(EventFlagsNew, osEventFlagsId_t, const osEventFlagsAttr_t *) +SVC0_1(EventFlagsGetName, const char *, osEventFlagsId_t) +SVC0_2(EventFlagsSet, uint32_t, osEventFlagsId_t, uint32_t) +SVC0_2(EventFlagsClear, uint32_t, osEventFlagsId_t, uint32_t) +SVC0_1(EventFlagsGet, uint32_t, osEventFlagsId_t) +SVC0_4(EventFlagsWait, uint32_t, osEventFlagsId_t, uint32_t, uint32_t, uint32_t) +SVC0_1(EventFlagsDelete, osStatus_t, osEventFlagsId_t) +//lint --flb "Library End" + // ==== ISR Calls ==== @@ -445,19 +492,21 @@ /// \note API identical to osEventFlagsSet __STATIC_INLINE uint32_t isrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { - os_event_flags_t *ef = (os_event_flags_t *)ef_id; + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); uint32_t event_flags; // Check parameters if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || - (flags & ~((1U << osRtxEventFlagsLimit) - 1U))) { - EvrRtxEventFlagsError(ef, osErrorParameter); + ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorParameter); } // Check object state if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, osErrorResource); + EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorResource); } @@ -465,7 +514,7 @@ event_flags = EventFlagsSet(ef, flags); // Register post ISR processing - osRtxPostProcess((os_object_t *)ef); + osRtxPostProcess(osRtxObject(ef)); EvrRtxEventFlagsSetDone(ef, event_flags); @@ -476,19 +525,21 @@ /// \note API identical to osEventFlagsWait __STATIC_INLINE uint32_t isrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { - os_event_flags_t *ef = (os_event_flags_t *)ef_id; + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); uint32_t event_flags; // Check parameters if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || (timeout != 0U) || - (flags & ~((1U << osRtxEventFlagsLimit) - 1U))) { - EvrRtxEventFlagsError(ef, osErrorParameter); + ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorParameter); } // Check object state if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, osErrorResource); + EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorResource); } @@ -496,12 +547,12 @@ event_flags = EventFlagsCheck(ef, flags, options); if (event_flags != 0U) { EvrRtxEventFlagsWaitCompleted(ef, flags, options, event_flags); - return ((uint32_t)event_flags); + } else { + EvrRtxEventFlagsWaitNotCompleted(ef, flags, options); + event_flags = (uint32_t)osErrorResource; } - EvrRtxEventFlagsWaitNotCompleted(ef, flags, options); - - return ((uint32_t)osErrorResource); + return event_flags; } @@ -509,68 +560,92 @@ /// Create and Initialize an Event Flags object. osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) { + osEventFlagsId_t ef_id; + EvrRtxEventFlagsNew(attr); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxEventFlagsError(NULL, osErrorISR); - return NULL; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxEventFlagsError(NULL, (int32_t)osErrorISR); + ef_id = NULL; + } else { + ef_id = __svcEventFlagsNew(attr); } - return __svcEventFlagsNew(attr); + return ef_id; } /// Get name of an Event Flags object. const char *osEventFlagsGetName (osEventFlagsId_t ef_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxEventFlagsGetName(ef_id, NULL); - return NULL; + name = NULL; + } else { + name = __svcEventFlagsGetName(ef_id); } - return __svcEventFlagsGetName(ef_id); + return name; } /// Set the specified Event Flags. uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { + uint32_t event_flags; + EvrRtxEventFlagsSet(ef_id, flags); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return isrRtxEventFlagsSet(ef_id, flags); + if (IsIrqMode() || IsIrqMasked()) { + event_flags = isrRtxEventFlagsSet(ef_id, flags); } else { - return __svcEventFlagsSet(ef_id, flags); + event_flags = __svcEventFlagsSet(ef_id, flags); } + return event_flags; } /// Clear the specified Event Flags. uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { + uint32_t event_flags; + EvrRtxEventFlagsClear(ef_id, flags); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxEventFlagsClear(ef_id, flags); + if (IsIrqMode() || IsIrqMasked()) { + event_flags = svcRtxEventFlagsClear(ef_id, flags); } else { - return __svcEventFlagsClear(ef_id, flags); + event_flags = __svcEventFlagsClear(ef_id, flags); } + return event_flags; } /// Get the current Event Flags. uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxEventFlagsGet(ef_id); + uint32_t event_flags; + + if (IsIrqMode() || IsIrqMasked()) { + event_flags = svcRtxEventFlagsGet(ef_id); } else { - return __svcEventFlagsGet(ef_id); + event_flags = __svcEventFlagsGet(ef_id); } + return event_flags; } /// Wait for one or more Event Flags to become signaled. uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { + uint32_t event_flags; + EvrRtxEventFlagsWait(ef_id, flags, options, timeout); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return isrRtxEventFlagsWait(ef_id, flags, options, timeout); + if (IsIrqMode() || IsIrqMasked()) { + event_flags = isrRtxEventFlagsWait(ef_id, flags, options, timeout); } else { - return __svcEventFlagsWait(ef_id, flags, options, timeout); + event_flags = __svcEventFlagsWait(ef_id, flags, options, timeout); } + return event_flags; } /// Delete an Event Flags object. osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) { + osStatus_t status; + EvrRtxEventFlagsDelete(ef_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxEventFlagsError(ef_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxEventFlagsError(ef_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcEventFlagsDelete(ef_id); } - return __svcEventFlagsDelete(ef_id); + return status; } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c index 2507d30..4148efa 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,13 @@ #include "cmsis_compiler.h" #include "rtx_evr.h" // RTX Event Recorder definitions -#ifdef RTE_Compiler_EventRecorder +#ifndef RTE_COMPONENTS_H +#include "RTE_Components.h" +#endif + +#ifdef RTE_Compiler_EventRecorder + +//lint -e923 -e9074 -e9078 -emacro((835,845),EventID) [MISRA Note 13] #include "EventRecorder.h" // Keil::Compiler:Event Recorder @@ -100,25 +106,26 @@ #define EvtRtxThreadJoined EventID(EventLevelOp, EvtRtxThreadNo, 0x15U) #define EvtRtxThreadBlocked EventID(EventLevelOp, EvtRtxThreadNo, 0x16U) #define EvtRtxThreadUnblocked EventID(EventLevelOp, EvtRtxThreadNo, 0x17U) -#define EvtRtxThreadSwitch EventID(EventLevelOp, EvtRtxThreadNo, 0x18U) -#define EvtRtxThreadExit EventID(EventLevelAPI, EvtRtxThreadNo, 0x19U) -#define EvtRtxThreadTerminate EventID(EventLevelAPI, EvtRtxThreadNo, 0x1AU) -#define EvtRtxThreadDestroyed EventID(EventLevelOp, EvtRtxThreadNo, 0x1BU) -#define EvtRtxThreadGetCount EventID(EventLevelAPI, EvtRtxThreadNo, 0x1CU) -#define EvtRtxThreadEnumerate EventID(EventLevelAPI, EvtRtxThreadNo, 0x1DU) -#define EvtRtxThreadFlagsSet EventID(EventLevelAPI, EvtRtxThreadNo, 0x1EU) -#define EvtRtxThreadFlagsSetDone EventID(EventLevelOp, EvtRtxThreadNo, 0x1FU) -#define EvtRtxThreadFlagsClear EventID(EventLevelAPI, EvtRtxThreadNo, 0x20U) -#define EvtRtxThreadFlagsClearDone EventID(EventLevelOp, EvtRtxThreadNo, 0x21U) -#define EvtRtxThreadFlagsGet EventID(EventLevelAPI, EvtRtxThreadNo, 0x22U) -#define EvtRtxThreadFlagsWait EventID(EventLevelAPI, EvtRtxThreadNo, 0x23U) -#define EvtRtxThreadFlagsWaitPending EventID(EventLevelOp, EvtRtxThreadNo, 0x24U) -#define EvtRtxThreadFlagsWaitTimeout EventID(EventLevelOp, EvtRtxThreadNo, 0x25U) -#define EvtRtxThreadFlagsWaitCompleted EventID(EventLevelOp, EvtRtxThreadNo, 0x26U) -#define EvtRtxThreadFlagsWaitNotCompleted EventID(EventLevelOp, EvtRtxThreadNo, 0x27U) -#define EvtRtxThreadDelay EventID(EventLevelAPI, EvtRtxThreadNo, 0x28U) -#define EvtRtxThreadDelayUntil EventID(EventLevelAPI, EvtRtxThreadNo, 0x29U) -#define EvtRtxThreadDelayCompleted EventID(EventLevelOp, EvtRtxThreadNo, 0x2AU) +#define EvtRtxThreadPreempted EventID(EventLevelOp, EvtRtxThreadNo, 0x18U) +#define EvtRtxThreadSwitched EventID(EventLevelOp, EvtRtxThreadNo, 0x19U) +#define EvtRtxThreadExit EventID(EventLevelAPI, EvtRtxThreadNo, 0x1AU) +#define EvtRtxThreadTerminate EventID(EventLevelAPI, EvtRtxThreadNo, 0x1BU) +#define EvtRtxThreadDestroyed EventID(EventLevelOp, EvtRtxThreadNo, 0x1CU) +#define EvtRtxThreadGetCount EventID(EventLevelAPI, EvtRtxThreadNo, 0x1DU) +#define EvtRtxThreadEnumerate EventID(EventLevelAPI, EvtRtxThreadNo, 0x1EU) +#define EvtRtxThreadFlagsSet EventID(EventLevelAPI, EvtRtxThreadNo, 0x1FU) +#define EvtRtxThreadFlagsSetDone EventID(EventLevelOp, EvtRtxThreadNo, 0x20U) +#define EvtRtxThreadFlagsClear EventID(EventLevelAPI, EvtRtxThreadNo, 0x21U) +#define EvtRtxThreadFlagsClearDone EventID(EventLevelOp, EvtRtxThreadNo, 0x22U) +#define EvtRtxThreadFlagsGet EventID(EventLevelAPI, EvtRtxThreadNo, 0x23U) +#define EvtRtxThreadFlagsWait EventID(EventLevelAPI, EvtRtxThreadNo, 0x24U) +#define EvtRtxThreadFlagsWaitPending EventID(EventLevelOp, EvtRtxThreadNo, 0x25U) +#define EvtRtxThreadFlagsWaitTimeout EventID(EventLevelOp, EvtRtxThreadNo, 0x26U) +#define EvtRtxThreadFlagsWaitCompleted EventID(EventLevelOp, EvtRtxThreadNo, 0x27U) +#define EvtRtxThreadFlagsWaitNotCompleted EventID(EventLevelOp, EvtRtxThreadNo, 0x28U) +#define EvtRtxThreadDelay EventID(EventLevelAPI, EvtRtxThreadNo, 0x29U) +#define EvtRtxThreadDelayUntil EventID(EventLevelAPI, EvtRtxThreadNo, 0x2AU) +#define EvtRtxThreadDelayCompleted EventID(EventLevelOp, EvtRtxThreadNo, 0x2BU) /// Event IDs for "RTX Timer" #define EvtRtxTimerError EventID(EventLevelError, EvtRtxTimerNo, 0x00U) @@ -243,13 +250,15 @@ #endif // RTE_Compiler_EventRecorder +//lint -esym(522, EvrRtx*) "Functions 'EvrRtx*' can be overridden (do not lack side-effects)" + // ==== Memory Events ==== #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_INIT_DISABLE)) __WEAK void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMemoryInit, (uint32_t)mem, size, result, 0U); + (void)EventRecord4(EvtRtxMemoryInit, (uint32_t)mem, size, result, 0U); #else (void)mem; (void)size; @@ -261,7 +270,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE)) __WEAK void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMemoryAlloc, (uint32_t)mem, size, type, (uint32_t)block); + (void)EventRecord4(EvtRtxMemoryAlloc, (uint32_t)mem, size, type, (uint32_t)block); #else (void)mem; (void)size; @@ -274,7 +283,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_FREE_DISABLE)) __WEAK void EvrRtxMemoryFree (void *mem, void *block, uint32_t result) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMemoryFree, (uint32_t)mem, (uint32_t)block, result, 0U); + (void)EventRecord4(EvtRtxMemoryFree, (uint32_t)mem, (uint32_t)block, result, 0U); #else (void)mem; (void)block; @@ -286,7 +295,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_INIT_DISABLE)) __WEAK void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMemoryBlockInit, (uint32_t)mp_info, block_count, block_size, (uint32_t)block_mem); + (void)EventRecord4(EvtRtxMemoryBlockInit, (uint32_t)mp_info, block_count, block_size, (uint32_t)block_mem); #else (void)mp_info; (void)block_count; @@ -299,7 +308,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE)) __WEAK void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryBlockAlloc, (uint32_t)mp_info, (uint32_t)block); + (void)EventRecord2(EvtRtxMemoryBlockAlloc, (uint32_t)mp_info, (uint32_t)block); #else (void)mp_info; (void)block; @@ -310,7 +319,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_FREE_DISABLE)) __WEAK void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMemoryBlockFree, (uint32_t)mp_info, (uint32_t)block, (uint32_t)status, 0U); + (void)EventRecord4(EvtRtxMemoryBlockFree, (uint32_t)mp_info, (uint32_t)block, (uint32_t)status, 0U); #else (void)mp_info; (void)block; @@ -325,7 +334,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_DISABLE)) __WEAK void EvrRtxKernelError (int32_t status) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelError, (uint32_t)status, 0U); + (void)EventRecord2(EvtRtxKernelError, (uint32_t)status, 0U); #else (void)status; #endif @@ -335,7 +344,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_DISABLE)) __WEAK void EvrRtxKernelInitialize (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelInitialize, 0U, 0U); + (void)EventRecord2(EvtRtxKernelInitialize, 0U, 0U); #else #endif } @@ -344,7 +353,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_COMPLETED_DISABLE)) __WEAK void EvrRtxKernelInitializeCompleted (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelInitializeCompleted, 0U, 0U); + (void)EventRecord2(EvtRtxKernelInitializeCompleted, 0U, 0U); #else #endif } @@ -353,7 +362,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_INFO_DISABLE)) __WEAK void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxKernelGetInfo, (uint32_t)version, (uint32_t)id_buf, id_size, 0U); + (void)EventRecord4(EvtRtxKernelGetInfo, (uint32_t)version, (uint32_t)id_buf, id_size, 0U); #else (void)version; (void)id_buf; @@ -365,9 +374,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE)) __WEAK void EvrRtxKernelInfoRetrieved (osVersion_t *version, char *id_buf) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelInfoRetrieved, (uint32_t)version, (uint32_t)id_buf); + (void)EventRecord2(EvtRtxKernelInfoRetrieved, (uint32_t)version, (uint32_t)id_buf); if (id_buf != NULL) { - EventRecordData(EvtRtxKernelInfoRetrieved_Detail, id_buf, strlen(id_buf)); + (void)EventRecordData(EvtRtxKernelInfoRetrieved_Detail, id_buf, strlen(id_buf)); } #else (void)version; @@ -379,7 +388,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_STATE_DISABLE)) __WEAK void EvrRtxKernelGetState (osKernelState_t state) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelGetState, (uint32_t)state, 0U); + (void)EventRecord2(EvtRtxKernelGetState, (uint32_t)state, 0U); #else (void)state; #endif @@ -389,7 +398,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_START_DISABLE)) __WEAK void EvrRtxKernelStart (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelStart, 0U, 0U); + (void)EventRecord2(EvtRtxKernelStart, 0U, 0U); #else #endif } @@ -398,7 +407,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_STARTED_DISABLE)) __WEAK void EvrRtxKernelStarted (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelStarted, 0U, 0U); + (void)EventRecord2(EvtRtxKernelStarted, 0U, 0U); #else #endif } @@ -407,7 +416,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_DISABLE)) __WEAK void EvrRtxKernelLock (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelLock, 0U, 0U); + (void)EventRecord2(EvtRtxKernelLock, 0U, 0U); #else #endif } @@ -416,7 +425,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCKED_DISABLE)) __WEAK void EvrRtxKernelLocked (int32_t lock) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelLocked, (uint32_t)lock, 0U); + (void)EventRecord2(EvtRtxKernelLocked, (uint32_t)lock, 0U); #else (void)lock; #endif @@ -426,7 +435,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCK_DISABLE)) __WEAK void EvrRtxKernelUnlock (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelUnlock, 0U, 0U); + (void)EventRecord2(EvtRtxKernelUnlock, 0U, 0U); #else #endif } @@ -435,7 +444,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCKED_DISABLE)) __WEAK void EvrRtxKernelUnlocked (int32_t lock) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelUnlocked, (uint32_t)lock, 0U); + (void)EventRecord2(EvtRtxKernelUnlocked, (uint32_t)lock, 0U); #else (void)lock; #endif @@ -445,7 +454,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE)) __WEAK void EvrRtxKernelRestoreLock (int32_t lock) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelRestoreLock, (uint32_t)lock, 0U); + (void)EventRecord2(EvtRtxKernelRestoreLock, (uint32_t)lock, 0U); #else (void)lock; #endif @@ -455,7 +464,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE)) __WEAK void EvrRtxKernelLockRestored (int32_t lock) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelLockRestored, (uint32_t)lock, 0U); + (void)EventRecord2(EvtRtxKernelLockRestored, (uint32_t)lock, 0U); #else (void)lock; #endif @@ -465,7 +474,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPEND_DISABLE)) __WEAK void EvrRtxKernelSuspend (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelSuspend, 0U, 0U); + (void)EventRecord2(EvtRtxKernelSuspend, 0U, 0U); #else #endif } @@ -474,7 +483,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPENDED_DISABLE)) __WEAK void EvrRtxKernelSuspended (uint32_t sleep_ticks) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelSuspended, sleep_ticks, 0U); + (void)EventRecord2(EvtRtxKernelSuspended, sleep_ticks, 0U); #else (void)sleep_ticks; #endif @@ -484,7 +493,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUME_DISABLE)) __WEAK void EvrRtxKernelResume (uint32_t sleep_ticks) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelResume, sleep_ticks, 0U); + (void)EventRecord2(EvtRtxKernelResume, sleep_ticks, 0U); #else (void)sleep_ticks; #endif @@ -494,7 +503,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUMED_DISABLE)) __WEAK void EvrRtxKernelResumed (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelResumed, 0U, 0U); + (void)EventRecord2(EvtRtxKernelResumed, 0U, 0U); #else #endif } @@ -503,7 +512,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE)) __WEAK void EvrRtxKernelGetTickCount (uint32_t count) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelGetTickCount, count, 0U); + (void)EventRecord2(EvtRtxKernelGetTickCount, count, 0U); #else (void)count; #endif @@ -513,7 +522,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE)) __WEAK void EvrRtxKernelGetTickFreq (uint32_t freq) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelGetTickFreq, freq, 0U); + (void)EventRecord2(EvtRtxKernelGetTickFreq, freq, 0U); #else (void)freq; #endif @@ -523,7 +532,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE)) __WEAK void EvrRtxKernelGetSysTimerCount (uint32_t count) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelGetSysTimerCount, count, 0U); + (void)EventRecord2(EvtRtxKernelGetSysTimerCount, count, 0U); #else (void)count; #endif @@ -533,7 +542,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE)) __WEAK void EvrRtxKernelGetSysTimerFreq (uint32_t freq) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelGetSysTimerFreq, freq, 0U); + (void)EventRecord2(EvtRtxKernelGetSysTimerFreq, freq, 0U); #else (void)freq; #endif @@ -546,7 +555,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ERROR_DISABLE)) __WEAK void EvrRtxThreadError (osThreadId_t thread_id, int32_t status) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadError, (uint32_t)thread_id, (uint32_t)status); + (void)EventRecord2(EvtRtxThreadError, (uint32_t)thread_id, (uint32_t)status); #else (void)thread_id; (void)status; @@ -557,9 +566,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_NEW_DISABLE)) __WEAK void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxThreadNew, (uint32_t)func, (uint32_t)argument, (uint32_t)attr, 0U); + (void)EventRecord4(EvtRtxThreadNew, (uint32_t)func, (uint32_t)argument, (uint32_t)attr, 0U); if (attr != NULL) { - EventRecordData(EvtRtxThreadNew_Detail, attr, sizeof (osThreadAttr_t)); + (void)EventRecordData(EvtRtxThreadNew_Detail, attr, sizeof (osThreadAttr_t)); } #else (void)func; @@ -570,11 +579,12 @@ #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE)) -__WEAK void EvrRtxThreadCreated (osThreadId_t thread_id) { +__WEAK void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadCreated, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadCreated, (uint32_t)thread_id, thread_addr); #else (void)thread_id; + (void)thread_addr; #endif } #endif @@ -582,9 +592,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE)) __WEAK void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadGetName, (uint32_t)thread_id, (uint32_t)name); + (void)EventRecord2(EvtRtxThreadGetName, (uint32_t)thread_id, (uint32_t)name); if (name != NULL) { - EventRecordData(EvtRtxThreadGetName_Detail, name, strlen(name)); + (void)EventRecordData(EvtRtxThreadGetName_Detail, name, strlen(name)); } #else (void)thread_id; @@ -596,7 +606,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ID_DISABLE)) __WEAK void EvrRtxThreadGetId (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadGetId, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadGetId, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -606,7 +616,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STATE_DISABLE)) __WEAK void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadGetState, (uint32_t)thread_id, (uint32_t)state); + (void)EventRecord2(EvtRtxThreadGetState, (uint32_t)thread_id, (uint32_t)state); #else (void)thread_id; (void)state; @@ -617,7 +627,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE)) __WEAK void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadGetStackSize, (uint32_t)thread_id, stack_size); + (void)EventRecord2(EvtRtxThreadGetStackSize, (uint32_t)thread_id, stack_size); #else (void)thread_id; (void)stack_size; @@ -628,7 +638,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE)) __WEAK void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadGetStackSpace, (uint32_t)thread_id, stack_space); + (void)EventRecord2(EvtRtxThreadGetStackSpace, (uint32_t)thread_id, stack_space); #else (void)thread_id; (void)stack_space; @@ -639,7 +649,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SET_PRIORITY_DISABLE)) __WEAK void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadSetPriority, (uint32_t)thread_id, (uint32_t)priority); + (void)EventRecord2(EvtRtxThreadSetPriority, (uint32_t)thread_id, (uint32_t)priority); #else (void)thread_id; (void)priority; @@ -650,7 +660,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_PRIORITY_DISABLE)) __WEAK void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadGetPriority, (uint32_t)thread_id, (uint32_t)priority); + (void)EventRecord2(EvtRtxThreadGetPriority, (uint32_t)thread_id, (uint32_t)priority); #else (void)thread_id; (void)priority; @@ -661,7 +671,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_YIELD_DISABLE)) __WEAK void EvrRtxThreadYield (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadYield, 0U, 0U); + (void)EventRecord2(EvtRtxThreadYield, 0U, 0U); #else #endif } @@ -670,7 +680,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_DISABLE)) __WEAK void EvrRtxThreadSuspend (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadSuspend, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadSuspend, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -680,7 +690,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPENDED_DISABLE)) __WEAK void EvrRtxThreadSuspended (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadSuspended, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadSuspended, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -690,7 +700,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_DISABLE)) __WEAK void EvrRtxThreadResume (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadResume, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadResume, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -700,7 +710,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUMED_DISABLE)) __WEAK void EvrRtxThreadResumed (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadResumed, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadResumed, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -710,7 +720,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACH_DISABLE)) __WEAK void EvrRtxThreadDetach (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadDetach, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadDetach, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -720,7 +730,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACHED_DISABLE)) __WEAK void EvrRtxThreadDetached (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadDetached, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadDetached, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -730,7 +740,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_DISABLE)) __WEAK void EvrRtxThreadJoin (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadJoin, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadJoin, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -740,7 +750,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_PENDING_DISABLE)) __WEAK void EvrRtxThreadJoinPending (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadJoinPending, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadJoinPending, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -750,7 +760,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOINED_DISABLE)) __WEAK void EvrRtxThreadJoined (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadJoined, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadJoined, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -760,7 +770,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_BLOCKED_DISABLE)) __WEAK void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadBlocked, (uint32_t)thread_id, timeout); + (void)EventRecord2(EvtRtxThreadBlocked, (uint32_t)thread_id, timeout); #else (void)thread_id; (void)timeout; @@ -771,7 +781,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_UNBLOCKED_DISABLE)) __WEAK void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadUnblocked, (uint32_t)thread_id, ret_val); + (void)EventRecord2(EvtRtxThreadUnblocked, (uint32_t)thread_id, ret_val); #else (void)thread_id; (void)ret_val; @@ -779,10 +789,20 @@ } #endif -#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCH_DISABLE)) -__WEAK void EvrRtxThreadSwitch (osThreadId_t thread_id) { +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PREEMPTED_DISABLE)) +__WEAK void EvrRtxThreadPreempted (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadSwitch, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadPreempted, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCHED_DISABLE)) +__WEAK void EvrRtxThreadSwitched (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadSwitched, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -792,7 +812,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE)) __WEAK void EvrRtxThreadExit (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadExit, 0U, 0U); + (void)EventRecord2(EvtRtxThreadExit, 0U, 0U); #else #endif } @@ -801,7 +821,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE)) __WEAK void EvrRtxThreadTerminate (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadTerminate, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadTerminate, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -811,7 +831,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DESTROYED_DISABLE)) __WEAK void EvrRtxThreadDestroyed (osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadDestroyed, (uint32_t)thread_id, 0U); + (void)EventRecord2(EvtRtxThreadDestroyed, (uint32_t)thread_id, 0U); #else (void)thread_id; #endif @@ -821,7 +841,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_COUNT_DISABLE)) __WEAK void EvrRtxThreadGetCount (uint32_t count) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadGetCount, count, 0U); + (void)EventRecord2(EvtRtxThreadGetCount, count, 0U); #else (void)count; #endif @@ -831,7 +851,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ENUMERATE_DISABLE)) __WEAK void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxThreadEnumerate, (uint32_t)thread_array, array_items, count, 0U); + (void)EventRecord4(EvtRtxThreadEnumerate, (uint32_t)thread_array, array_items, count, 0U); #else (void)thread_array; (void)array_items; @@ -843,7 +863,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DISABLE)) __WEAK void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadFlagsSet, (uint32_t)thread_id, flags); + (void)EventRecord2(EvtRtxThreadFlagsSet, (uint32_t)thread_id, flags); #else (void)thread_id; (void)flags; @@ -854,7 +874,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE)) __WEAK void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadFlagsSetDone, (uint32_t)thread_id, thread_flags); + (void)EventRecord2(EvtRtxThreadFlagsSetDone, (uint32_t)thread_id, thread_flags); #else (void)thread_id; (void)thread_flags; @@ -865,7 +885,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE)) __WEAK void EvrRtxThreadFlagsClear (uint32_t flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadFlagsClear, flags, 0U); + (void)EventRecord2(EvtRtxThreadFlagsClear, flags, 0U); #else (void)flags; #endif @@ -875,7 +895,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE)) __WEAK void EvrRtxThreadFlagsClearDone (uint32_t thread_flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadFlagsClearDone, thread_flags, 0U); + (void)EventRecord2(EvtRtxThreadFlagsClearDone, thread_flags, 0U); #else (void)thread_flags; #endif @@ -885,7 +905,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_GET_DISABLE)) __WEAK void EvrRtxThreadFlagsGet (uint32_t thread_flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadFlagsGet, thread_flags, 0U); + (void)EventRecord2(EvtRtxThreadFlagsGet, thread_flags, 0U); #else (void)thread_flags; #endif @@ -895,7 +915,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_DISABLE)) __WEAK void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxThreadFlagsWait, flags, options, timeout, 0U); + (void)EventRecord4(EvtRtxThreadFlagsWait, flags, options, timeout, 0U); #else (void)flags; (void)options; @@ -907,7 +927,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE)) __WEAK void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxThreadFlagsWaitPending, flags, options, timeout, 0U); + (void)EventRecord4(EvtRtxThreadFlagsWaitPending, flags, options, timeout, 0U); #else (void)flags; (void)options; @@ -919,7 +939,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE)) __WEAK void EvrRtxThreadFlagsWaitTimeout (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadFlagsWaitTimeout, 0U, 0U); + (void)EventRecord2(EvtRtxThreadFlagsWaitTimeout, 0U, 0U); #endif } #endif @@ -927,7 +947,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE)) __WEAK void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxThreadFlagsWaitCompleted, flags, options, thread_flags, 0U); + (void)EventRecord4(EvtRtxThreadFlagsWaitCompleted, flags, options, thread_flags, 0U); #else (void)flags; (void)options; @@ -939,7 +959,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE)) __WEAK void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadFlagsWaitNotCompleted, flags, options); + (void)EventRecord2(EvtRtxThreadFlagsWaitNotCompleted, flags, options); #else (void)flags; (void)options; @@ -950,7 +970,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_DISABLE)) __WEAK void EvrRtxThreadDelay (uint32_t ticks) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadDelay, ticks, 0U); + (void)EventRecord2(EvtRtxThreadDelay, ticks, 0U); #else (void)ticks; #endif @@ -960,7 +980,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_UNTIL_DISABLE)) __WEAK void EvrRtxThreadDelayUntil (uint32_t ticks) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadDelayUntil, ticks, 0U); + (void)EventRecord2(EvtRtxThreadDelayUntil, ticks, 0U); #else (void)ticks; #endif @@ -970,7 +990,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_COMPLETED_DISABLE)) __WEAK void EvrRtxThreadDelayCompleted (void) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadDelayCompleted, 0U, 0U); + (void)EventRecord2(EvtRtxThreadDelayCompleted, 0U, 0U); #endif } #endif @@ -981,7 +1001,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_ERROR_DISABLE)) __WEAK void EvrRtxTimerError (osTimerId_t timer_id, int32_t status) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerError, (uint32_t)timer_id, (uint32_t)status); + (void)EventRecord2(EvtRtxTimerError, (uint32_t)timer_id, (uint32_t)status); #else (void)timer_id; (void)status; @@ -992,7 +1012,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CALLBACK_DISABLE)) __WEAK void EvrRtxTimerCallback (osTimerFunc_t func, void *argument) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerCallback, (uint32_t)func, (uint32_t)argument); + (void)EventRecord2(EvtRtxTimerCallback, (uint32_t)func, (uint32_t)argument); #else (void)func; (void)argument; @@ -1003,9 +1023,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_NEW_DISABLE)) __WEAK void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxTimerNew, (uint32_t)func, (uint32_t)type, (uint32_t)argument, (uint32_t)attr); + (void)EventRecord4(EvtRtxTimerNew, (uint32_t)func, (uint32_t)type, (uint32_t)argument, (uint32_t)attr); if (attr != NULL) { - EventRecordData(EvtRtxTimerNew_Detail, attr, sizeof (osTimerAttr_t)); + (void)EventRecordData(EvtRtxTimerNew_Detail, attr, sizeof (osTimerAttr_t)); } #else (void)func; @@ -1017,11 +1037,12 @@ #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE)) -__WEAK void EvrRtxTimerCreated (osTimerId_t timer_id) { +__WEAK void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerCreated, (uint32_t)timer_id, 0U); + (void)EventRecord2(EvtRtxTimerCreated, (uint32_t)timer_id, (uint32_t)name); #else (void)timer_id; + (void)name; #endif } #endif @@ -1029,9 +1050,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE)) __WEAK void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerGetName, (uint32_t)timer_id, (uint32_t)name); + (void)EventRecord2(EvtRtxTimerGetName, (uint32_t)timer_id, (uint32_t)name); if (name != NULL) { - EventRecordData(EvtRtxTimerGetName_Detail, name, strlen(name)); + (void)EventRecordData(EvtRtxTimerGetName_Detail, name, strlen(name)); } #else (void)timer_id; @@ -1043,7 +1064,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE)) __WEAK void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerStart, (uint32_t)timer_id, ticks); + (void)EventRecord2(EvtRtxTimerStart, (uint32_t)timer_id, ticks); #else (void)timer_id; (void)ticks; @@ -1054,7 +1075,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE)) __WEAK void EvrRtxTimerStarted (osTimerId_t timer_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerStarted, (uint32_t)timer_id, 0U); + (void)EventRecord2(EvtRtxTimerStarted, (uint32_t)timer_id, 0U); #else (void)timer_id; #endif @@ -1064,7 +1085,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE)) __WEAK void EvrRtxTimerStop (osTimerId_t timer_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerStop, (uint32_t)timer_id, 0U); + (void)EventRecord2(EvtRtxTimerStop, (uint32_t)timer_id, 0U); #else (void)timer_id; #endif @@ -1074,7 +1095,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE)) __WEAK void EvrRtxTimerStopped (osTimerId_t timer_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerStopped, (uint32_t)timer_id, 0U); + (void)EventRecord2(EvtRtxTimerStopped, (uint32_t)timer_id, 0U); #else (void)timer_id; #endif @@ -1084,7 +1105,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE)) __WEAK void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerIsRunning, (uint32_t)timer_id, running); + (void)EventRecord2(EvtRtxTimerIsRunning, (uint32_t)timer_id, running); #else (void)timer_id; (void)running; @@ -1095,7 +1116,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE)) __WEAK void EvrRtxTimerDelete (osTimerId_t timer_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerDelete, (uint32_t)timer_id, 0U); + (void)EventRecord2(EvtRtxTimerDelete, (uint32_t)timer_id, 0U); #else (void)timer_id; #endif @@ -1105,7 +1126,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE)) __WEAK void EvrRtxTimerDestroyed (osTimerId_t timer_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxTimerDestroyed, (uint32_t)timer_id, 0U); + (void)EventRecord2(EvtRtxTimerDestroyed, (uint32_t)timer_id, 0U); #else (void)timer_id; #endif @@ -1118,7 +1139,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_ERROR_DISABLE)) __WEAK void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsError, (uint32_t)ef_id, (uint32_t)status); + (void)EventRecord2(EvtRtxEventFlagsError, (uint32_t)ef_id, (uint32_t)status); #else (void)ef_id; (void)status; @@ -1129,9 +1150,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE)) __WEAK void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsNew, (uint32_t)attr, 0U); + (void)EventRecord2(EvtRtxEventFlagsNew, (uint32_t)attr, 0U); if (attr != NULL) { - EventRecordData(EvtRtxEventFlagsNew_Detail, attr, sizeof (osEventFlagsAttr_t)); + (void)EventRecordData(EvtRtxEventFlagsNew_Detail, attr, sizeof (osEventFlagsAttr_t)); } #else (void)attr; @@ -1140,11 +1161,12 @@ #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE)) -__WEAK void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id) { +__WEAK void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsCreated, (uint32_t)ef_id, 0U); + (void)EventRecord2(EvtRtxEventFlagsCreated, (uint32_t)ef_id, (uint32_t)name); #else (void)ef_id; + (void)name; #endif } #endif @@ -1152,9 +1174,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE)) __WEAK void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsGetName, (uint32_t)ef_id, (uint32_t)name); + (void)EventRecord2(EvtRtxEventFlagsGetName, (uint32_t)ef_id, (uint32_t)name); if (name != NULL) { - EventRecordData(EvtRtxEventFlagsGetName_Detail, name, strlen(name)); + (void)EventRecordData(EvtRtxEventFlagsGetName_Detail, name, strlen(name)); } #else (void)ef_id; @@ -1166,7 +1188,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DISABLE)) __WEAK void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsSet, (uint32_t)ef_id, flags); + (void)EventRecord2(EvtRtxEventFlagsSet, (uint32_t)ef_id, flags); #else (void)ef_id; (void)flags; @@ -1177,7 +1199,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE)) __WEAK void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsSetDone, (uint32_t)ef_id, event_flags); + (void)EventRecord2(EvtRtxEventFlagsSetDone, (uint32_t)ef_id, event_flags); #else (void)ef_id; (void)event_flags; @@ -1188,7 +1210,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE)) __WEAK void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsClear, (uint32_t)ef_id, flags); + (void)EventRecord2(EvtRtxEventFlagsClear, (uint32_t)ef_id, flags); #else (void)ef_id; (void)flags; @@ -1199,7 +1221,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE)) __WEAK void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsClearDone, (uint32_t)ef_id, event_flags); + (void)EventRecord2(EvtRtxEventFlagsClearDone, (uint32_t)ef_id, event_flags); #else (void)ef_id; (void)event_flags; @@ -1210,7 +1232,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_DISABLE)) __WEAK void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsGet, (uint32_t)ef_id, event_flags); + (void)EventRecord2(EvtRtxEventFlagsGet, (uint32_t)ef_id, event_flags); #else (void)ef_id; (void)event_flags; @@ -1221,7 +1243,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_DISABLE)) __WEAK void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxEventFlagsWait, (uint32_t)ef_id, flags, options, timeout); + (void)EventRecord4(EvtRtxEventFlagsWait, (uint32_t)ef_id, flags, options, timeout); #else (void)ef_id; (void)flags; @@ -1234,7 +1256,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE)) __WEAK void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxEventFlagsWaitPending, (uint32_t)ef_id, flags, options, timeout); + (void)EventRecord4(EvtRtxEventFlagsWaitPending, (uint32_t)ef_id, flags, options, timeout); #else (void)ef_id; (void)flags; @@ -1247,7 +1269,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE)) __WEAK void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsWaitTimeout, (uint32_t)ef_id, 0U); + (void)EventRecord2(EvtRtxEventFlagsWaitTimeout, (uint32_t)ef_id, 0U); #else (void)ef_id; #endif @@ -1257,7 +1279,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE)) __WEAK void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxEventFlagsWaitCompleted, (uint32_t)ef_id, flags, options, event_flags); + (void)EventRecord4(EvtRtxEventFlagsWaitCompleted, (uint32_t)ef_id, flags, options, event_flags); #else (void)ef_id; (void)flags; @@ -1270,7 +1292,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE)) __WEAK void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxEventFlagsWaitNotCompleted, (uint32_t)ef_id, flags, options, 0U); + (void)EventRecord4(EvtRtxEventFlagsWaitNotCompleted, (uint32_t)ef_id, flags, options, 0U); #else (void)ef_id; (void)flags; @@ -1282,7 +1304,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DELETE_DISABLE)) __WEAK void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsDelete, (uint32_t)ef_id, 0U); + (void)EventRecord2(EvtRtxEventFlagsDelete, (uint32_t)ef_id, 0U); #else (void)ef_id; #endif @@ -1292,7 +1314,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE)) __WEAK void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxEventFlagsDestroyed, (uint32_t)ef_id, 0U); + (void)EventRecord2(EvtRtxEventFlagsDestroyed, (uint32_t)ef_id, 0U); #else (void)ef_id; #endif @@ -1305,7 +1327,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ERROR_DISABLE)) __WEAK void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexError, (uint32_t)mutex_id, (uint32_t)status); + (void)EventRecord2(EvtRtxMutexError, (uint32_t)mutex_id, (uint32_t)status); #else (void)mutex_id; (void)status; @@ -1316,9 +1338,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE)) __WEAK void EvrRtxMutexNew (const osMutexAttr_t *attr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexNew, (uint32_t)attr, 0U); + (void)EventRecord2(EvtRtxMutexNew, (uint32_t)attr, 0U); if (attr != NULL) { - EventRecordData(EvtRtxMutexNew_Detail, attr, sizeof (osMutexAttr_t)); + (void)EventRecordData(EvtRtxMutexNew_Detail, attr, sizeof (osMutexAttr_t)); } #else (void)attr; @@ -1327,11 +1349,12 @@ #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE)) -__WEAK void EvrRtxMutexCreated (osMutexId_t mutex_id) { +__WEAK void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexCreated, (uint32_t)mutex_id, 0U); + (void)EventRecord2(EvtRtxMutexCreated, (uint32_t)mutex_id, (uint32_t)name); #else (void)mutex_id; + (void)name; #endif } #endif @@ -1339,9 +1362,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE)) __WEAK void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexGetName, (uint32_t)mutex_id, (uint32_t)name); + (void)EventRecord2(EvtRtxMutexGetName, (uint32_t)mutex_id, (uint32_t)name); if (name != NULL) { - EventRecordData(EvtRtxMutexGetName_Detail, name, strlen(name)); + (void)EventRecordData(EvtRtxMutexGetName_Detail, name, strlen(name)); } #else (void)mutex_id; @@ -1353,7 +1376,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_DISABLE)) __WEAK void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexAcquire, (uint32_t)mutex_id, timeout); + (void)EventRecord2(EvtRtxMutexAcquire, (uint32_t)mutex_id, timeout); #else (void)mutex_id; (void)timeout; @@ -1364,7 +1387,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE)) __WEAK void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexAcquirePending, (uint32_t)mutex_id, timeout); + (void)EventRecord2(EvtRtxMutexAcquirePending, (uint32_t)mutex_id, timeout); #else (void)mutex_id; (void)timeout; @@ -1375,7 +1398,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE)) __WEAK void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexAcquireTimeout, (uint32_t)mutex_id, 0U); + (void)EventRecord2(EvtRtxMutexAcquireTimeout, (uint32_t)mutex_id, 0U); #else (void)mutex_id; #endif @@ -1385,7 +1408,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE)) __WEAK void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexAcquired, (uint32_t)mutex_id, lock); + (void)EventRecord2(EvtRtxMutexAcquired, (uint32_t)mutex_id, lock); #else (void)mutex_id; (void)lock; @@ -1396,7 +1419,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE)) __WEAK void EvrRtxMutexNotAcquired (osMutexId_t mutex_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexNotAcquired, (uint32_t)mutex_id, 0U); + (void)EventRecord2(EvtRtxMutexNotAcquired, (uint32_t)mutex_id, 0U); #else (void)mutex_id; #endif @@ -1406,7 +1429,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASE_DISABLE)) __WEAK void EvrRtxMutexRelease (osMutexId_t mutex_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexRelease, (uint32_t)mutex_id, 0U); + (void)EventRecord2(EvtRtxMutexRelease, (uint32_t)mutex_id, 0U); #else (void)mutex_id; #endif @@ -1416,7 +1439,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE)) __WEAK void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexReleased, (uint32_t)mutex_id, lock); + (void)EventRecord2(EvtRtxMutexReleased, (uint32_t)mutex_id, lock); #else (void)mutex_id; (void)lock; @@ -1427,7 +1450,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_OWNER_DISABLE)) __WEAK void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexGetOwner, (uint32_t)mutex_id, (uint32_t)thread_id); + (void)EventRecord2(EvtRtxMutexGetOwner, (uint32_t)mutex_id, (uint32_t)thread_id); #else (void)mutex_id; (void)thread_id; @@ -1438,7 +1461,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DELETE_DISABLE)) __WEAK void EvrRtxMutexDelete (osMutexId_t mutex_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexDelete, (uint32_t)mutex_id, 0U); + (void)EventRecord2(EvtRtxMutexDelete, (uint32_t)mutex_id, 0U); #else (void)mutex_id; #endif @@ -1448,7 +1471,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DESTROYED_DISABLE)) __WEAK void EvrRtxMutexDestroyed (osMutexId_t mutex_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMutexDestroyed, (uint32_t)mutex_id, 0U); + (void)EventRecord2(EvtRtxMutexDestroyed, (uint32_t)mutex_id, 0U); #else (void)mutex_id; #endif @@ -1461,7 +1484,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ERROR_DISABLE)) __WEAK void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreError, (uint32_t)semaphore_id, (uint32_t)status); + (void)EventRecord2(EvtRtxSemaphoreError, (uint32_t)semaphore_id, (uint32_t)status); #else (void)semaphore_id; (void)status; @@ -1472,9 +1495,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NEW_DISABLE)) __WEAK void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxSemaphoreNew, max_count, initial_count, (uint32_t)attr, 0U); + (void)EventRecord4(EvtRtxSemaphoreNew, max_count, initial_count, (uint32_t)attr, 0U); if (attr != NULL) { - EventRecordData(EvtRtxSemaphoreNew_Detail, attr, sizeof (osSemaphoreAttr_t)); + (void)EventRecordData(EvtRtxSemaphoreNew_Detail, attr, sizeof (osSemaphoreAttr_t)); } #else (void)max_count; @@ -1485,11 +1508,12 @@ #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE)) -__WEAK void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id) { +__WEAK void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreCreated, (uint32_t)semaphore_id, 0U); + (void)EventRecord2(EvtRtxSemaphoreCreated, (uint32_t)semaphore_id, (uint32_t)name); #else (void)semaphore_id; + (void)name; #endif } #endif @@ -1497,9 +1521,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_NAME_DISABLE)) __WEAK void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreGetName, (uint32_t)semaphore_id, (uint32_t)name); + (void)EventRecord2(EvtRtxSemaphoreGetName, (uint32_t)semaphore_id, (uint32_t)name); if (name != NULL) { - EventRecordData(EvtRtxSemaphoreGetName_Detail, name, strlen(name)); + (void)EventRecordData(EvtRtxSemaphoreGetName_Detail, name, strlen(name)); } #else #endif @@ -1511,7 +1535,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE)) __WEAK void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreAcquire, (uint32_t)semaphore_id, timeout); + (void)EventRecord2(EvtRtxSemaphoreAcquire, (uint32_t)semaphore_id, timeout); #else (void)semaphore_id; (void)timeout; @@ -1522,7 +1546,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE)) __WEAK void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreAcquirePending, (uint32_t)semaphore_id, (uint32_t)timeout); + (void)EventRecord2(EvtRtxSemaphoreAcquirePending, (uint32_t)semaphore_id, (uint32_t)timeout); #else (void)semaphore_id; (void)timeout; @@ -1533,7 +1557,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE)) __WEAK void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreAcquireTimeout, (uint32_t)semaphore_id, 0U); + (void)EventRecord2(EvtRtxSemaphoreAcquireTimeout, (uint32_t)semaphore_id, 0U); #else (void)semaphore_id; #endif @@ -1543,7 +1567,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE)) __WEAK void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreAcquired, (uint32_t)semaphore_id, 0U); + (void)EventRecord2(EvtRtxSemaphoreAcquired, (uint32_t)semaphore_id, 0U); #else (void)semaphore_id; #endif @@ -1553,7 +1577,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE)) __WEAK void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreNotAcquired, (uint32_t)semaphore_id, 0U); + (void)EventRecord2(EvtRtxSemaphoreNotAcquired, (uint32_t)semaphore_id, 0U); #else (void)semaphore_id; #endif @@ -1563,7 +1587,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASE_DISABLE)) __WEAK void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreRelease, (uint32_t)semaphore_id, 0U); + (void)EventRecord2(EvtRtxSemaphoreRelease, (uint32_t)semaphore_id, 0U); #else (void)semaphore_id; #endif @@ -1573,7 +1597,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE)) __WEAK void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreReleased, (uint32_t)semaphore_id, 0U); + (void)EventRecord2(EvtRtxSemaphoreReleased, (uint32_t)semaphore_id, 0U); #else (void)semaphore_id; #endif @@ -1583,7 +1607,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE)) __WEAK void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreGetCount, (uint32_t)semaphore_id, count); + (void)EventRecord2(EvtRtxSemaphoreGetCount, (uint32_t)semaphore_id, count); #else (void)semaphore_id; (void)count; @@ -1594,7 +1618,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DELETE_DISABLE)) __WEAK void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreDelete, (uint32_t)semaphore_id, 0U); + (void)EventRecord2(EvtRtxSemaphoreDelete, (uint32_t)semaphore_id, 0U); #else (void)semaphore_id; #endif @@ -1604,7 +1628,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DESTROYED_DISABLE)) __WEAK void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxSemaphoreDestroyed, (uint32_t)semaphore_id, 0U); + (void)EventRecord2(EvtRtxSemaphoreDestroyed, (uint32_t)semaphore_id, 0U); #else (void)semaphore_id; #endif @@ -1617,7 +1641,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ERROR_DISABLE)) __WEAK void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolError, (uint32_t)mp_id, (uint32_t)status); + (void)EventRecord2(EvtRtxMemoryPoolError, (uint32_t)mp_id, (uint32_t)status); #else (void)mp_id; (void)status; @@ -1628,9 +1652,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_NEW_DISABLE)) __WEAK void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMemoryPoolNew, block_count, block_size, (uint32_t)attr, 0U); + (void)EventRecord4(EvtRtxMemoryPoolNew, block_count, block_size, (uint32_t)attr, 0U); if (attr != NULL) { - EventRecordData(EvtRtxMemoryPoolNew_Detail, attr, sizeof (osMemoryPoolAttr_t)); + (void)EventRecordData(EvtRtxMemoryPoolNew_Detail, attr, sizeof (osMemoryPoolAttr_t)); } #else (void)block_count; @@ -1641,11 +1665,12 @@ #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE)) -__WEAK void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id) { +__WEAK void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolCreated, (uint32_t)mp_id, 0U); + (void)EventRecord2(EvtRtxMemoryPoolCreated, (uint32_t)mp_id, (uint32_t)name); #else (void)mp_id; + (void)name; #endif } #endif @@ -1653,9 +1678,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE)) __WEAK void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolGetName, (uint32_t)mp_id, (uint32_t)name); + (void)EventRecord2(EvtRtxMemoryPoolGetName, (uint32_t)mp_id, (uint32_t)name); if (name != NULL) { - EventRecordData(EvtRtxMemoryPoolGetName_Detail, name, strlen(name)); + (void)EventRecordData(EvtRtxMemoryPoolGetName_Detail, name, strlen(name)); } #else (void)mp_id; @@ -1667,7 +1692,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_DISABLE)) __WEAK void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolAlloc, (uint32_t)mp_id, timeout); + (void)EventRecord2(EvtRtxMemoryPoolAlloc, (uint32_t)mp_id, timeout); #else (void)mp_id; (void)timeout; @@ -1678,7 +1703,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE)) __WEAK void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolAllocPending, (uint32_t)mp_id, timeout); + (void)EventRecord2(EvtRtxMemoryPoolAllocPending, (uint32_t)mp_id, timeout); #else (void)mp_id; (void)timeout; @@ -1689,7 +1714,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE)) __WEAK void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolAllocTimeout, (uint32_t)mp_id, 0U); + (void)EventRecord2(EvtRtxMemoryPoolAllocTimeout, (uint32_t)mp_id, 0U); #else (void)mp_id; #endif @@ -1699,7 +1724,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE)) __WEAK void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolAllocated, (uint32_t)mp_id, (uint32_t)block); + (void)EventRecord2(EvtRtxMemoryPoolAllocated, (uint32_t)mp_id, (uint32_t)block); #else (void)mp_id; (void)block; @@ -1710,7 +1735,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE)) __WEAK void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolAllocFailed, (uint32_t)mp_id, 0U); + (void)EventRecord2(EvtRtxMemoryPoolAllocFailed, (uint32_t)mp_id, 0U); #else (void)mp_id; #endif @@ -1720,7 +1745,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_DISABLE)) __WEAK void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolFree, (uint32_t)mp_id, (uint32_t)block); + (void)EventRecord2(EvtRtxMemoryPoolFree, (uint32_t)mp_id, (uint32_t)block); #else (void)mp_id; (void)block; @@ -1731,7 +1756,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE)) __WEAK void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolDeallocated, (uint32_t)mp_id, (uint32_t)block); + (void)EventRecord2(EvtRtxMemoryPoolDeallocated, (uint32_t)mp_id, (uint32_t)block); #else (void)mp_id; (void)block; @@ -1742,7 +1767,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE)) __WEAK void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolFreeFailed, (uint32_t)mp_id, (uint32_t)block); + (void)EventRecord2(EvtRtxMemoryPoolFreeFailed, (uint32_t)mp_id, (uint32_t)block); #else (void)mp_id; (void)block; @@ -1753,7 +1778,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE)) __WEAK void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolGetCapacity, (uint32_t)mp_id, capacity); + (void)EventRecord2(EvtRtxMemoryPoolGetCapacity, (uint32_t)mp_id, capacity); #else (void)mp_id; (void)capacity; @@ -1764,7 +1789,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE)) __WEAK void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolGetBlockSize, (uint32_t)mp_id, block_size); + (void)EventRecord2(EvtRtxMemoryPoolGetBlockSize, (uint32_t)mp_id, block_size); #else (void)mp_id; (void)block_size; @@ -1775,7 +1800,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE)) __WEAK void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolGetCount, (uint32_t)mp_id, count); + (void)EventRecord2(EvtRtxMemoryPoolGetCount, (uint32_t)mp_id, count); #else (void)mp_id; (void)count; @@ -1786,7 +1811,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE)) __WEAK void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolGetSpace, (uint32_t)mp_id, space); + (void)EventRecord2(EvtRtxMemoryPoolGetSpace, (uint32_t)mp_id, space); #else (void)mp_id; (void)space; @@ -1797,7 +1822,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DELETE_DISABLE)) __WEAK void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolDelete, (uint32_t)mp_id, 0U); + (void)EventRecord2(EvtRtxMemoryPoolDelete, (uint32_t)mp_id, 0U); #else (void)mp_id; #endif @@ -1807,7 +1832,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE)) __WEAK void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMemoryPoolDestroyed, (uint32_t)mp_id, 0U); + (void)EventRecord2(EvtRtxMemoryPoolDestroyed, (uint32_t)mp_id, 0U); #else (void)mp_id; #endif @@ -1820,7 +1845,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE)) __WEAK void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2 (EvtRtxMessageQueueError, (uint32_t)mq_id, (uint32_t)status); + (void)EventRecord2 (EvtRtxMessageQueueError, (uint32_t)mq_id, (uint32_t)status); #else (void)mq_id; (void)status; @@ -1831,9 +1856,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE)) __WEAK void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMessageQueueNew, msg_count, msg_size, (uint32_t)attr, 0U); + (void)EventRecord4(EvtRtxMessageQueueNew, msg_count, msg_size, (uint32_t)attr, 0U); if (attr != NULL) { - EventRecordData(EvtRtxMessageQueueNew_Detail, attr, sizeof (osMemoryPoolAttr_t)); + (void)EventRecordData(EvtRtxMessageQueueNew_Detail, attr, sizeof (osMemoryPoolAttr_t)); } #else (void)msg_count; @@ -1844,11 +1869,12 @@ #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE)) -__WEAK void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id) { +__WEAK void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueCreated, (uint32_t)mq_id, 0U); + (void)EventRecord2(EvtRtxMessageQueueCreated, (uint32_t)mq_id, (uint32_t)name); #else (void)mq_id; + (void)name; #endif } #endif @@ -1856,9 +1882,9 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE)) __WEAK void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueGetName, (uint32_t)mq_id, (uint32_t)name); + (void)EventRecord2(EvtRtxMessageQueueGetName, (uint32_t)mq_id, (uint32_t)name); if (name != NULL) { - EventRecordData(EvtRtxMessageQueueGetName_Detail, name, strlen(name)); + (void)EventRecordData(EvtRtxMessageQueueGetName_Detail, name, strlen(name)); } #else (void)mq_id; @@ -1870,7 +1896,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE)) __WEAK void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMessageQueuePut, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout); + (void)EventRecord4(EvtRtxMessageQueuePut, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout); #else (void)mq_id; (void)msg_ptr; @@ -1883,7 +1909,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE)) __WEAK void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMessageQueuePutPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U); + (void)EventRecord4(EvtRtxMessageQueuePutPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U); #else (void)mq_id; (void)msg_ptr; @@ -1895,7 +1921,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE)) __WEAK void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueuePutTimeout, (uint32_t)mq_id, 0U); + (void)EventRecord2(EvtRtxMessageQueuePutTimeout, (uint32_t)mq_id, 0U); #else (void)mq_id; #endif @@ -1905,7 +1931,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE)) __WEAK void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueInsertPending, (uint32_t)mq_id, (uint32_t)msg_ptr); + (void)EventRecord2(EvtRtxMessageQueueInsertPending, (uint32_t)mq_id, (uint32_t)msg_ptr); #else (void)mq_id; (void)msg_ptr; @@ -1916,7 +1942,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE)) __WEAK void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueInserted, (uint32_t)mq_id, (uint32_t)msg_ptr); + (void)EventRecord2(EvtRtxMessageQueueInserted, (uint32_t)mq_id, (uint32_t)msg_ptr); #else (void)mq_id; (void)msg_ptr; @@ -1927,7 +1953,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE)) __WEAK void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueNotInserted, (uint32_t)mq_id, (uint32_t)msg_ptr); + (void)EventRecord2(EvtRtxMessageQueueNotInserted, (uint32_t)mq_id, (uint32_t)msg_ptr); #else (void)mq_id; (void)msg_ptr; @@ -1938,7 +1964,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_DISABLE)) __WEAK void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMessageQueueGet, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout); + (void)EventRecord4(EvtRtxMessageQueueGet, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout); #else (void)mq_id; (void)msg_ptr; @@ -1951,7 +1977,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE)) __WEAK void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout) { #if defined(RTE_Compiler_EventRecorder) - EventRecord4(EvtRtxMessageQueueGetPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U); + (void)EventRecord4(EvtRtxMessageQueueGetPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U); #else (void)mq_id; (void)msg_ptr; @@ -1963,7 +1989,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE)) __WEAK void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueGetTimeout, (uint32_t)mq_id, 0U); + (void)EventRecord2(EvtRtxMessageQueueGetTimeout, (uint32_t)mq_id, 0U); #else (void)mq_id; #endif @@ -1973,7 +1999,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE)) __WEAK void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr); + (void)EventRecord2(EvtRtxMessageQueueRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr); #else (void)mq_id; (void)msg_ptr; @@ -1984,7 +2010,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE)) __WEAK void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueNotRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr); + (void)EventRecord2(EvtRtxMessageQueueNotRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr); #else (void)mq_id; (void)msg_ptr; @@ -1995,7 +2021,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE)) __WEAK void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueGetCapacity, (uint32_t)mq_id, capacity); + (void)EventRecord2(EvtRtxMessageQueueGetCapacity, (uint32_t)mq_id, capacity); #else (void)mq_id; (void)capacity; @@ -2006,7 +2032,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE)) __WEAK void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueGetMsgSize, (uint32_t)mq_id, msg_size); + (void)EventRecord2(EvtRtxMessageQueueGetMsgSize, (uint32_t)mq_id, msg_size); #else (void)mq_id; (void)msg_size; @@ -2017,7 +2043,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE)) __WEAK void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueGetCount, (uint32_t)mq_id, count); + (void)EventRecord2(EvtRtxMessageQueueGetCount, (uint32_t)mq_id, count); #else (void)mq_id; (void)count; @@ -2028,7 +2054,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE)) __WEAK void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueGetSpace, (uint32_t)mq_id, space); + (void)EventRecord2(EvtRtxMessageQueueGetSpace, (uint32_t)mq_id, space); #else (void)mq_id; (void)space; @@ -2039,7 +2065,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE)) __WEAK void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueReset, (uint32_t)mq_id, 0U); + (void)EventRecord2(EvtRtxMessageQueueReset, (uint32_t)mq_id, 0U); #else (void)mq_id; #endif @@ -2049,7 +2075,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE)) __WEAK void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueResetDone, (uint32_t)mq_id, 0U); + (void)EventRecord2(EvtRtxMessageQueueResetDone, (uint32_t)mq_id, 0U); #else (void)mq_id; #endif @@ -2059,7 +2085,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE)) __WEAK void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueDelete, (uint32_t)mq_id, 0U); + (void)EventRecord2(EvtRtxMessageQueueDelete, (uint32_t)mq_id, 0U); #else (void)mq_id; #endif @@ -2069,7 +2095,7 @@ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE)) __WEAK void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxMessageQueueDestroyed, (uint32_t)mq_id, 0U); + (void)EventRecord2(EvtRtxMessageQueueDestroyed, (uint32_t)mq_id, 0U); #else (void)mq_id; #endif diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c index 8284034..685ae5c 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -29,6 +29,7 @@ // OS Runtime Information osRtxInfo_t osRtxInfo __attribute__((section(".data.os"))) = +//lint -e{785} "Initialize only OS ID, OS Version and Kernel State" { .os_id = osRtxKernelId, .version = osRtxVersionKernel, .kernel.state = osRtxKernelInactive }; @@ -65,46 +66,45 @@ // ==== Service Calls ==== -// Service Calls definitions -SVC0_0M(KernelInitialize, osStatus_t) -SVC0_3 (KernelGetInfo, osStatus_t, osVersion_t *, char *, uint32_t) -SVC0_0M(KernelStart, osStatus_t) -SVC0_0 (KernelLock, int32_t) -SVC0_0 (KernelUnlock, int32_t) -SVC0_1 (KernelRestoreLock, int32_t, int32_t) -SVC0_0 (KernelSuspend, uint32_t) -SVC0_1N(KernelResume, void, uint32_t) -SVC0_0 (KernelGetState, osKernelState_t) -SVC0_0 (KernelGetTickCount, uint32_t) -SVC0_0 (KernelGetTickFreq, uint32_t) -SVC0_0 (KernelGetSysTimerCount, uint32_t) -SVC0_0 (KernelGetSysTimerFreq, uint32_t) - /// Initialize the RTOS Kernel. /// \note API identical to osKernelInitialize -osStatus_t svcRtxKernelInitialize (void) { +static osStatus_t svcRtxKernelInitialize (void) { if (osRtxInfo.kernel.state == osRtxKernelReady) { EvrRtxKernelInitializeCompleted(); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osOK; } - if (osRtxInfo.kernel.state != osKernelInactive) { - EvrRtxKernelError(osError); + if (osRtxInfo.kernel.state != osRtxKernelInactive) { + EvrRtxKernelError((int32_t)osError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osError; } - // Initialize osRtxInfo - memset(&osRtxInfo.kernel, 0, sizeof(osRtxInfo) - offsetof(osRtxInfo_t, kernel)); - if (osRtxConfig.thread_stack_size < (64U + 8U)) { EvrRtxKernelError(osRtxErrorInvalidThreadStack); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osError; } if ((osRtxConfig.isr_queue.data == NULL) || (osRtxConfig.isr_queue.max == 0U)) { - EvrRtxKernelError(osError); + EvrRtxKernelError((int32_t)osError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osError; } + +#if (DOMAIN_NS == 1) + // Initialize Secure Process Stack + if (TZ_InitContextSystem_S() == 0U) { + EvrRtxKernelError(osRtxErrorTZ_InitContext_S); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osError; + } +#endif + + // Initialize osRtxInfo + memset(&osRtxInfo.kernel, 0, sizeof(osRtxInfo) - offsetof(osRtxInfo_t, kernel)); + osRtxInfo.isr_queue.data = osRtxConfig.isr_queue.data; osRtxInfo.isr_queue.max = osRtxConfig.isr_queue.max; @@ -131,74 +131,71 @@ } // Initialize Memory Pools (Fixed Block Size) - if ((osRtxConfig.mpi.stack != NULL) && - (osRtxMemoryPoolInit(osRtxConfig.mpi.stack, - osRtxConfig.mpi.stack->max_blocks, - osRtxConfig.mpi.stack->block_size, - osRtxConfig.mpi.stack->block_base) != 0U)) { - osRtxInfo.mpi.stack = osRtxConfig.mpi.stack; + if (osRtxConfig.mpi.stack != NULL) { + if (osRtxMemoryPoolInit(osRtxConfig.mpi.stack, + osRtxConfig.mpi.stack->max_blocks, + osRtxConfig.mpi.stack->block_size, + osRtxConfig.mpi.stack->block_base) != 0U) { + osRtxInfo.mpi.stack = osRtxConfig.mpi.stack; + } } - if ((osRtxConfig.mpi.thread != NULL) && - (osRtxMemoryPoolInit(osRtxConfig.mpi.thread, - osRtxConfig.mpi.thread->max_blocks, - osRtxConfig.mpi.thread->block_size, - osRtxConfig.mpi.thread->block_base) != 0U)) { - osRtxInfo.mpi.thread = osRtxConfig.mpi.thread; + if (osRtxConfig.mpi.thread != NULL) { + if (osRtxMemoryPoolInit(osRtxConfig.mpi.thread, + osRtxConfig.mpi.thread->max_blocks, + osRtxConfig.mpi.thread->block_size, + osRtxConfig.mpi.thread->block_base) != 0U) { + osRtxInfo.mpi.thread = osRtxConfig.mpi.thread; + } } - if ((osRtxConfig.mpi.timer != NULL) && - (osRtxMemoryPoolInit(osRtxConfig.mpi.timer, - osRtxConfig.mpi.timer->max_blocks, - osRtxConfig.mpi.timer->block_size, - osRtxConfig.mpi.timer->block_base) != 0U)) { - osRtxInfo.mpi.timer = osRtxConfig.mpi.timer; + if (osRtxConfig.mpi.timer != NULL) { + if (osRtxMemoryPoolInit(osRtxConfig.mpi.timer, + osRtxConfig.mpi.timer->max_blocks, + osRtxConfig.mpi.timer->block_size, + osRtxConfig.mpi.timer->block_base) != 0U) { + osRtxInfo.mpi.timer = osRtxConfig.mpi.timer; + } } - if ((osRtxConfig.mpi.event_flags != NULL) && - (osRtxMemoryPoolInit(osRtxConfig.mpi.event_flags, - osRtxConfig.mpi.event_flags->max_blocks, - osRtxConfig.mpi.event_flags->block_size, - osRtxConfig.mpi.event_flags->block_base) != 0U)) { - osRtxInfo.mpi.event_flags = osRtxConfig.mpi.event_flags; + if (osRtxConfig.mpi.event_flags != NULL) { + if (osRtxMemoryPoolInit(osRtxConfig.mpi.event_flags, + osRtxConfig.mpi.event_flags->max_blocks, + osRtxConfig.mpi.event_flags->block_size, + osRtxConfig.mpi.event_flags->block_base) != 0U) { + osRtxInfo.mpi.event_flags = osRtxConfig.mpi.event_flags; + } } - if ((osRtxConfig.mpi.mutex != NULL) && - (osRtxMemoryPoolInit(osRtxConfig.mpi.mutex, - osRtxConfig.mpi.mutex->max_blocks, - osRtxConfig.mpi.mutex->block_size, - osRtxConfig.mpi.mutex->block_base) != 0U)) { - osRtxInfo.mpi.mutex = osRtxConfig.mpi.mutex; + if (osRtxConfig.mpi.mutex != NULL) { + if (osRtxMemoryPoolInit(osRtxConfig.mpi.mutex, + osRtxConfig.mpi.mutex->max_blocks, + osRtxConfig.mpi.mutex->block_size, + osRtxConfig.mpi.mutex->block_base) != 0U) { + osRtxInfo.mpi.mutex = osRtxConfig.mpi.mutex; + } } - if ((osRtxConfig.mpi.semaphore != NULL) && - (osRtxMemoryPoolInit(osRtxConfig.mpi.semaphore, - osRtxConfig.mpi.semaphore->max_blocks, - osRtxConfig.mpi.semaphore->block_size, - osRtxConfig.mpi.semaphore->block_base) != 0U)) { - osRtxInfo.mpi.semaphore = osRtxConfig.mpi.semaphore; + if (osRtxConfig.mpi.semaphore != NULL) { + if (osRtxMemoryPoolInit(osRtxConfig.mpi.semaphore, + osRtxConfig.mpi.semaphore->max_blocks, + osRtxConfig.mpi.semaphore->block_size, + osRtxConfig.mpi.semaphore->block_base) != 0U) { + osRtxInfo.mpi.semaphore = osRtxConfig.mpi.semaphore; + } } - if ((osRtxConfig.mpi.memory_pool != NULL) && - (osRtxMemoryPoolInit(osRtxConfig.mpi.memory_pool, - osRtxConfig.mpi.memory_pool->max_blocks, - osRtxConfig.mpi.memory_pool->block_size, - osRtxConfig.mpi.memory_pool->block_base) != 0U)) { - osRtxInfo.mpi.memory_pool = osRtxConfig.mpi.memory_pool; + if (osRtxConfig.mpi.memory_pool != NULL) { + if (osRtxMemoryPoolInit(osRtxConfig.mpi.memory_pool, + osRtxConfig.mpi.memory_pool->max_blocks, + osRtxConfig.mpi.memory_pool->block_size, + osRtxConfig.mpi.memory_pool->block_base) != 0U) { + osRtxInfo.mpi.memory_pool = osRtxConfig.mpi.memory_pool; + } } - if ((osRtxConfig.mpi.message_queue != NULL) && - (osRtxMemoryPoolInit(osRtxConfig.mpi.message_queue, - osRtxConfig.mpi.message_queue->max_blocks, - osRtxConfig.mpi.message_queue->block_size, - osRtxConfig.mpi.message_queue->block_base) != 0U)) { - osRtxInfo.mpi.message_queue = osRtxConfig.mpi.message_queue; + if (osRtxConfig.mpi.message_queue != NULL) { + if (osRtxMemoryPoolInit(osRtxConfig.mpi.message_queue, + osRtxConfig.mpi.message_queue->max_blocks, + osRtxConfig.mpi.message_queue->block_size, + osRtxConfig.mpi.message_queue->block_base) != 0U) { + osRtxInfo.mpi.message_queue = osRtxConfig.mpi.message_queue; + } } -#if (__DOMAIN_NS == 1U) - // Initialize Secure Process Stack - if (TZ_InitContextSystem_S() == 0U) { - EvrRtxKernelError(osRtxErrorTZ_InitContext_S); - return osError; - } -#endif - - // Initialize SVC and PendSV System Service Calls - SVC_Initialize(); - osRtxInfo.kernel.state = osRtxKernelReady; EvrRtxKernelInitializeCompleted(); @@ -208,7 +205,8 @@ /// Get RTOS Kernel Information. /// \note API identical to osKernelGetInfo -osStatus_t svcRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { +static osStatus_t svcRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { + uint32_t size; if (version != NULL) { version->api = osRtxVersionAPI; @@ -217,9 +215,11 @@ if ((id_buf != NULL) && (id_size != 0U)) { if (id_size > sizeof(osRtxKernelId)) { - id_size = sizeof(osRtxKernelId); + size = sizeof(osRtxKernelId); + } else { + size = id_size; } - memcpy(id_buf, osRtxKernelId, id_size); + memcpy(id_buf, osRtxKernelId, size); } EvrRtxKernelInfoRetrieved(version, id_buf); @@ -229,56 +229,49 @@ /// Get the current RTOS Kernel state. /// \note API identical to osKernelGetState -osKernelState_t svcRtxKernelGetState (void) { - EvrRtxKernelGetState((osKernelState_t)(osRtxInfo.kernel.state)); - return ((osKernelState_t)(osRtxInfo.kernel.state)); +static osKernelState_t svcRtxKernelGetState (void) { + osKernelState_t state = osRtxKernelState(); + EvrRtxKernelGetState(state); + return state; } /// Start the RTOS Kernel scheduler. /// \note API identical to osKernelStart -osStatus_t svcRtxKernelStart (void) { +static osStatus_t svcRtxKernelStart (void) { os_thread_t *thread; if (osRtxInfo.kernel.state != osRtxKernelReady) { EvrRtxKernelError(osRtxErrorKernelNotReady); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osError; } - // Create Idle Thread - if (osRtxInfo.thread.idle == NULL) { - osRtxInfo.thread.idle = svcRtxThreadNew(osRtxIdleThread, NULL, osRtxConfig.idle_thread_attr, NULL); - if (osRtxInfo.thread.idle == NULL) { - EvrRtxKernelError(osError); - return osError; - } + // Thread startup (Idle and Timer Thread) + if (!osRtxThreadStartup()) { + EvrRtxKernelError((int32_t)osError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osError; } - // Create Timer Thread - if (osRtxConfig.timer_mq_mcnt != 0U) { - if (osRtxInfo.timer.thread == NULL) { - osRtxInfo.timer.thread = svcRtxThreadNew(osRtxTimerThread, NULL, osRtxConfig.timer_thread_attr, NULL); - if (osRtxInfo.timer.thread == NULL) { - EvrRtxKernelError(osError); - return osError; - } - } - } + // Setup SVC and PendSV System Service Calls + SVC_Setup(); // Setup RTOS Tick - if (OS_Tick_Setup(osRtxConfig.tick_freq, OS_TICK_HANDLER) != 0U) { + if (OS_Tick_Setup(osRtxConfig.tick_freq, OS_TICK_HANDLER) != 0) { + EvrRtxKernelError((int32_t)osError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osError; } osRtxInfo.tick_irqn = OS_Tick_GetIRQn(); // Enable RTOS Tick - if (OS_Tick_Enable() != 0U) { - return osError; - } + OS_Tick_Enable(); // Switch to Ready Thread with highest Priority thread = osRtxThreadListGet(&osRtxInfo.thread.ready); if (thread == NULL) { - EvrRtxKernelError(osError); + EvrRtxKernelError((int32_t)osError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osError; } osRtxThreadSwitch(thread); @@ -301,72 +294,92 @@ /// Lock the RTOS Kernel scheduler. /// \note API identical to osKernelLock int32_t svcRtxKernelLock (void) { + int32_t lock; - if (osRtxInfo.kernel.state == osRtxKernelLocked) { - EvrRtxKernelLocked(1); - return 1; + switch (osRtxInfo.kernel.state) { + case osRtxKernelRunning: + osRtxInfo.kernel.state = osRtxKernelLocked; + EvrRtxKernelLocked(0); + lock = 0; + break; + case osRtxKernelLocked: + EvrRtxKernelLocked(1); + lock = 1; + break; + default: + EvrRtxKernelError((int32_t)osError); + lock = (int32_t)osError; + break; } - if (osRtxInfo.kernel.state == osRtxKernelRunning) { - osRtxInfo.kernel.state = osRtxKernelLocked; - EvrRtxKernelLocked(0); - return 0; - } - - EvrRtxKernelError(osError); - return osError; + return lock; } - + /// Unlock the RTOS Kernel scheduler. /// \note API identical to osKernelUnlock int32_t svcRtxKernelUnlock (void) { + int32_t lock; - if (osRtxInfo.kernel.state == osRtxKernelLocked) { - osRtxInfo.kernel.state = osRtxKernelRunning; - EvrRtxKernelUnlocked(1); - return 1; + switch (osRtxInfo.kernel.state) { + case osRtxKernelRunning: + EvrRtxKernelUnlocked(0); + lock = 0; + break; + case osRtxKernelLocked: + osRtxInfo.kernel.state = osRtxKernelRunning; + EvrRtxKernelUnlocked(1); + lock = 1; + break; + default: + EvrRtxKernelError((int32_t)osError); + lock = (int32_t)osError; + break; } - if (osRtxInfo.kernel.state == osRtxKernelRunning) { - EvrRtxKernelUnlocked(0); - return 0; - } - - EvrRtxKernelError(osError); - return osError; + return lock; } /// Restore the RTOS Kernel scheduler lock state. /// \note API identical to osKernelRestoreLock -int32_t svcRtxKernelRestoreLock (int32_t lock) { +static int32_t svcRtxKernelRestoreLock (int32_t lock) { + int32_t lock_new; - if ((osRtxInfo.kernel.state == osRtxKernelRunning) || - (osRtxInfo.kernel.state == osRtxKernelLocked)) { - switch (lock) { - case 1: - osRtxInfo.kernel.state = osRtxKernelLocked; - EvrRtxKernelLockRestored(1); - return 1; - case 0: - osRtxInfo.kernel.state = osRtxKernelRunning; - EvrRtxKernelLockRestored(0); - return 0; - default: - break; - } + switch (osRtxInfo.kernel.state) { + case osRtxKernelRunning: + case osRtxKernelLocked: + switch (lock) { + case 0: + osRtxInfo.kernel.state = osRtxKernelRunning; + EvrRtxKernelLockRestored(0); + lock_new = 0; + break; + case 1: + osRtxInfo.kernel.state = osRtxKernelLocked; + EvrRtxKernelLockRestored(1); + lock_new = 1; + break; + default: + EvrRtxKernelError((int32_t)osError); + lock_new = (int32_t)osError; + break; + } + break; + default: + EvrRtxKernelError((int32_t)osError); + lock_new = (int32_t)osError; + break; } - - EvrRtxKernelError(osError); - return osError; + return lock_new; } /// Suspend the RTOS Kernel scheduler. /// \note API identical to osKernelSuspend -uint32_t svcRtxKernelSuspend (void) { - os_thread_t *thread; - os_timer_t *timer; - uint32_t delay; +static uint32_t svcRtxKernelSuspend (void) { + const os_thread_t *thread; + const os_timer_t *timer; + uint32_t delay; if (osRtxInfo.kernel.state != osRtxKernelRunning) { EvrRtxKernelError(osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -397,13 +410,14 @@ /// Resume the RTOS Kernel scheduler. /// \note API identical to osKernelResume -void svcRtxKernelResume (uint32_t sleep_ticks) { +static void svcRtxKernelResume (uint32_t sleep_ticks) { os_thread_t *thread; os_timer_t *timer; uint32_t delay; if (osRtxInfo.kernel.state != osRtxKernelSuspended) { EvrRtxKernelResumed(); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } @@ -417,7 +431,7 @@ thread->delay = 1U; do { osRtxThreadDelayTick(); - if (delay == 0U) { + if (delay == 0U) { break; } delay--; @@ -460,27 +474,27 @@ /// Get the RTOS kernel tick count. /// \note API identical to osKernelGetTickCount -uint32_t svcRtxKernelGetTickCount (void) { +static uint32_t svcRtxKernelGetTickCount (void) { EvrRtxKernelGetTickCount(osRtxInfo.kernel.tick); return osRtxInfo.kernel.tick; } /// Get the RTOS kernel tick frequency. /// \note API identical to osKernelGetTickFreq -uint32_t svcRtxKernelGetTickFreq (void) { +static uint32_t svcRtxKernelGetTickFreq (void) { EvrRtxKernelGetTickFreq(osRtxConfig.tick_freq); return osRtxConfig.tick_freq; } /// Get the RTOS kernel system timer count. /// \note API identical to osKernelGetSysTimerCount -uint32_t svcRtxKernelGetSysTimerCount (void) { +static uint32_t svcRtxKernelGetSysTimerCount (void) { uint32_t tick; uint32_t count; tick = (uint32_t)osRtxInfo.kernel.tick; count = OS_Tick_GetCount(); - if (OS_Tick_GetOverflow()) { + if (OS_Tick_GetOverflow() != 0U) { count = OS_Tick_GetCount(); tick++; } @@ -491,153 +505,203 @@ /// Get the RTOS kernel system timer frequency. /// \note API identical to osKernelGetSysTimerFreq -uint32_t svcRtxKernelGetSysTimerFreq (void) { +static uint32_t svcRtxKernelGetSysTimerFreq (void) { uint32_t freq = OS_Tick_GetClock(); EvrRtxKernelGetSysTimerFreq(freq); return freq; } +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_0 (KernelInitialize, osStatus_t) +SVC0_3 (KernelGetInfo, osStatus_t, osVersion_t *, char *, uint32_t) +SVC0_0 (KernelStart, osStatus_t) +SVC0_0 (KernelLock, int32_t) +SVC0_0 (KernelUnlock, int32_t) +SVC0_1 (KernelRestoreLock, int32_t, int32_t) +SVC0_0 (KernelSuspend, uint32_t) +SVC0_1N(KernelResume, void, uint32_t) +SVC0_0 (KernelGetState, osKernelState_t) +SVC0_0 (KernelGetTickCount, uint32_t) +SVC0_0 (KernelGetTickFreq, uint32_t) +SVC0_0 (KernelGetSysTimerCount, uint32_t) +SVC0_0 (KernelGetSysTimerFreq, uint32_t) +//lint --flb "Library End" + // ==== Public API ==== /// Initialize the RTOS Kernel. osStatus_t osKernelInitialize (void) { + osStatus_t status; + EvrRtxKernelInitialize(); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxKernelError(osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcKernelInitialize(); } - return __svcKernelInitialize(); + return status; } /// Get RTOS Kernel Information. osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { + osStatus_t status; + EvrRtxKernelGetInfo(version, id_buf, id_size); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxKernelError(osErrorISR); - return osErrorISR; - } - if (IS_PRIVILEGED()) { - return svcRtxKernelGetInfo(version, id_buf, id_size); + if (IsPrivileged() || IsIrqMode() || IsIrqMasked()) { + status = svcRtxKernelGetInfo(version, id_buf, id_size); } else { - return __svcKernelGetInfo(version, id_buf, id_size); + status = __svcKernelGetInfo(version, id_buf, id_size); } + return status; } /// Get the current RTOS Kernel state. osKernelState_t osKernelGetState (void) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxKernelGetState(osKernelError); - return osKernelError; - } - if (IS_PRIVILEGED()) { - return svcRtxKernelGetState(); + osKernelState_t state; + + if (IsPrivileged() || IsIrqMode() || IsIrqMasked()) { + state = svcRtxKernelGetState(); } else { - return __svcKernelGetState(); + state = __svcKernelGetState(); } + return state; } /// Start the RTOS Kernel scheduler. osStatus_t osKernelStart (void) { + osStatus_t status; + EvrRtxKernelStart(); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxKernelError(osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + status = osErrorISR; + } else { + /* Call the pre-start event (from unprivileged mode) if the handler exists + * and the kernel is not running. */ + /* FIXME osEventObs needs to be readable but not writable from unprivileged + * code. */ + if (osKernelGetState() != osKernelRunning && osEventObs && osEventObs->pre_start) { + osEventObs->pre_start(); + } + status = __svcKernelStart(); } - - /* Call the pre-start event (from unprivileged mode) if the handler exists - * and the kernel is not running. */ - /* FIXME osEventObs needs to be readable but not writable from unprivileged - * code. */ - if (osKernelGetState() != osKernelRunning && osEventObs && osEventObs->pre_start) { - osEventObs->pre_start(); - } - - return __svcKernelStart(); + return status; } /// Lock the RTOS Kernel scheduler. int32_t osKernelLock (void) { + int32_t lock; + EvrRtxKernelLock(); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxKernelError(osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + lock = (int32_t)osErrorISR; + } else { + lock = __svcKernelLock(); } - return __svcKernelLock(); + return lock; } - + /// Unlock the RTOS Kernel scheduler. int32_t osKernelUnlock (void) { + int32_t lock; + EvrRtxKernelUnlock(); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxKernelError(osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + lock = (int32_t)osErrorISR; + } else { + lock = __svcKernelUnlock(); } - return __svcKernelUnlock(); + return lock; } /// Restore the RTOS Kernel scheduler lock state. int32_t osKernelRestoreLock (int32_t lock) { + int32_t lock_new; + EvrRtxKernelRestoreLock(lock); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxKernelError(osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + lock_new = (int32_t)osErrorISR; + } else { + lock_new = __svcKernelRestoreLock(lock); } - return __svcKernelRestoreLock(lock); + return lock_new; } /// Suspend the RTOS Kernel scheduler. uint32_t osKernelSuspend (void) { + uint32_t ticks; + EvrRtxKernelSuspend(); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxKernelError(osErrorISR); - return 0U; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + ticks = 0U; + } else { + ticks = __svcKernelSuspend(); } - return __svcKernelSuspend(); + return ticks; } /// Resume the RTOS Kernel scheduler. void osKernelResume (uint32_t sleep_ticks) { + EvrRtxKernelResume(sleep_ticks); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxKernelError(osErrorISR); - return; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + } else { + __svcKernelResume(sleep_ticks); } - __svcKernelResume(sleep_ticks); } /// Get the RTOS kernel tick count. uint32_t osKernelGetTickCount (void) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxKernelGetTickCount(); + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + count = svcRtxKernelGetTickCount(); } else { - return __svcKernelGetTickCount(); + count = __svcKernelGetTickCount(); } + return count; } /// Get the RTOS kernel tick frequency. uint32_t osKernelGetTickFreq (void) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxKernelGetTickFreq(); + uint32_t freq; + + if (IsIrqMode() || IsIrqMasked()) { + freq = svcRtxKernelGetTickFreq(); } else { - return __svcKernelGetTickFreq(); + freq = __svcKernelGetTickFreq(); } + return freq; } /// Get the RTOS kernel system timer count. uint32_t osKernelGetSysTimerCount (void) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxKernelGetSysTimerCount(); + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + count = svcRtxKernelGetSysTimerCount(); } else { - return __svcKernelGetSysTimerCount(); + count = __svcKernelGetSysTimerCount(); } + return count; } /// Get the RTOS kernel system timer frequency. uint32_t osKernelGetSysTimerFreq (void) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxKernelGetSysTimerFreq(); + uint32_t freq; + + if (IsIrqMode() || IsIrqMasked()) { + freq = svcRtxKernelGetSysTimerFreq(); } else { - return __svcKernelGetSysTimerFreq(); + freq = __svcKernelGetSysTimerFreq(); } + return freq; } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c index 17e1b68..58f67f3 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -24,8 +24,8 @@ */ #include "cmsis_compiler.h" -#include "rtx_os.h" #include "RTX_Config.h" +#include "rtx_os.h" // System Configuration @@ -33,7 +33,7 @@ // Dynamic Memory #if (OS_DYNAMIC_MEM_SIZE != 0) -#if ((OS_DYNAMIC_MEM_SIZE & 7) != 0) +#if ((OS_DYNAMIC_MEM_SIZE % 8) != 0) #error "Invalid Dynamic Memory size!" #endif static uint64_t os_mem[OS_DYNAMIC_MEM_SIZE/8] \ @@ -53,11 +53,11 @@ // Thread Configuration // ==================== -#if (((OS_STACK_SIZE & 7) != 0) || (OS_STACK_SIZE < 72)) +#if (((OS_STACK_SIZE % 8) != 0) || (OS_STACK_SIZE < 72)) #error "Invalid default Thread Stack size!" #endif -#if (((OS_IDLE_THREAD_STACK_SIZE & 7) != 0) || (OS_IDLE_THREAD_STACK_SIZE < 72)) +#if (((OS_IDLE_THREAD_STACK_SIZE % 8) != 0) || (OS_IDLE_THREAD_STACK_SIZE < 72)) #error "Invalid Idle Thread Stack size!" #endif @@ -68,7 +68,7 @@ #error "Invalid number of user Threads!" #endif -#if ((OS_THREAD_USER_STACK_SIZE != 0) && ((OS_THREAD_USER_STACK_SIZE & 7) != 0)) +#if ((OS_THREAD_USER_STACK_SIZE != 0) && ((OS_THREAD_USER_STACK_SIZE % 8) != 0)) #error "Invalid total Stack size!" #endif @@ -85,18 +85,18 @@ // Memory Pool for Thread Control Blocks static osRtxMpInfo_t os_mpi_thread \ __attribute__((section(".data.os.thread.mpi"))) = -{ (uint32_t)OS_THREAD_NUM, 0U, (uint32_t)osRtxThreadCbSize, &os_thread_cb, NULL, NULL }; +{ (uint32_t)OS_THREAD_NUM, 0U, (uint32_t)osRtxThreadCbSize, &os_thread_cb[0], NULL, NULL }; // Memory Pool for Thread Default Stack #if (OS_THREAD_DEF_STACK_NUM != 0) static osRtxMpInfo_t os_mpi_def_stack \ __attribute__((section(".data.os.thread.mpi"))) = -{ (uint32_t)OS_THREAD_DEF_STACK_NUM, 0U, (uint32_t)OS_STACK_SIZE, &os_thread_def_stack, NULL, NULL }; +{ (uint32_t)OS_THREAD_DEF_STACK_NUM, 0U, (uint32_t)OS_STACK_SIZE, &os_thread_def_stack[0], NULL, NULL }; #endif // Memory Pool for Thread Stack #if (OS_THREAD_USER_STACK_SIZE != 0) -static uint64_t os_thread_stack[OS_THREAD_USER_STACK_SIZE/8] \ +static uint64_t os_thread_stack[2 + OS_THREAD_NUM + (OS_THREAD_USER_STACK_SIZE/8)] \ __attribute__((section(".bss.os.thread.stack"))); #endif @@ -121,11 +121,15 @@ // Idle Thread Attributes static const osThreadAttr_t os_idle_thread_attr = { +#if defined(OS_IDLE_THREAD_NAME) + OS_IDLE_THREAD_NAME, +#else NULL, +#endif osThreadDetached, &os_idle_thread_cb, (uint32_t)sizeof(os_idle_thread_cb), - &os_idle_thread_stack, + &os_idle_thread_stack[0], (uint32_t)sizeof(os_idle_thread_stack), osPriorityIdle, #if defined(OS_IDLE_THREAD_TZ_MOD_ID) @@ -153,14 +157,14 @@ // Memory Pool for Timer Control Blocks static osRtxMpInfo_t os_mpi_timer \ __attribute__((section(".data.os.timer.mpi"))) = -{ (uint32_t)OS_TIMER_NUM, 0U, (uint32_t)osRtxTimerCbSize, &os_timer_cb, NULL, NULL }; +{ (uint32_t)OS_TIMER_NUM, 0U, (uint32_t)osRtxTimerCbSize, &os_timer_cb[0], NULL, NULL }; #endif // (OS_TIMER_OBJ_MEM != 0) #if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0)) -#if (((OS_TIMER_THREAD_STACK_SIZE & 7) != 0) || (OS_TIMER_THREAD_STACK_SIZE < 96)) +#if (((OS_TIMER_THREAD_STACK_SIZE % 8) != 0) || (OS_TIMER_THREAD_STACK_SIZE < 96)) #error "Invalid Timer Thread Stack size!" #endif @@ -174,12 +178,17 @@ // Timer Thread Attributes static const osThreadAttr_t os_timer_thread_attr = { +#if defined(OS_TIMER_THREAD_NAME) + OS_TIMER_THREAD_NAME, +#else NULL, +#endif osThreadDetached, &os_timer_thread_cb, (uint32_t)sizeof(os_timer_thread_cb), - &os_timer_thread_stack, + &os_timer_thread_stack[0], (uint32_t)sizeof(os_timer_thread_stack), + //lint -e{9030} -e{9034} "cast from signed to enum" (osPriority_t)OS_TIMER_THREAD_PRIO, #if defined(OS_TIMER_THREAD_TZ_MOD_ID) (uint32_t)OS_TIMER_THREAD_TZ_MOD_ID, @@ -203,7 +212,7 @@ 0U, &os_timer_mq_cb, (uint32_t)sizeof(os_timer_mq_cb), - &os_timer_mq_data, + &os_timer_mq_data[0], (uint32_t)sizeof(os_timer_mq_data) }; @@ -231,7 +240,7 @@ // Memory Pool for Event Flags Control Blocks static osRtxMpInfo_t os_mpi_ef \ __attribute__((section(".data.os.evflags.mpi"))) = -{ (uint32_t)OS_EVFLAGS_NUM, 0U, (uint32_t)osRtxEventFlagsCbSize, &os_ef_cb, NULL, NULL }; +{ (uint32_t)OS_EVFLAGS_NUM, 0U, (uint32_t)osRtxEventFlagsCbSize, &os_ef_cb[0], NULL, NULL }; #endif // (OS_EVFLAGS_OBJ_MEM != 0) @@ -252,7 +261,7 @@ // Memory Pool for Mutex Control Blocks static osRtxMpInfo_t os_mpi_mutex \ __attribute__((section(".data.os.mutex.mpi"))) = -{ (uint32_t)OS_MUTEX_NUM, 0U, (uint32_t)osRtxMutexCbSize, &os_mutex_cb, NULL, NULL }; +{ (uint32_t)OS_MUTEX_NUM, 0U, (uint32_t)osRtxMutexCbSize, &os_mutex_cb[0], NULL, NULL }; #endif // (OS_MUTEX_OBJ_MEM != 0) @@ -273,7 +282,7 @@ // Memory Pool for Semaphore Control Blocks static osRtxMpInfo_t os_mpi_semaphore \ __attribute__((section(".data.os.semaphore.mpi"))) = -{ (uint32_t)OS_SEMAPHORE_NUM, 0U, (uint32_t)osRtxSemaphoreCbSize, &os_semaphore_cb, NULL, NULL }; +{ (uint32_t)OS_SEMAPHORE_NUM, 0U, (uint32_t)osRtxSemaphoreCbSize, &os_semaphore_cb[0], NULL, NULL }; #endif // (OS_SEMAPHORE_OBJ_MEM != 0) @@ -294,14 +303,14 @@ // Memory Pool for Memory Pool Control Blocks static osRtxMpInfo_t os_mpi_mp \ __attribute__((section(".data.os.mempool.mpi"))) = -{ (uint32_t)OS_MEMPOOL_NUM, 0U, (uint32_t)osRtxMemoryPoolCbSize, &os_mp_cb, NULL, NULL }; +{ (uint32_t)OS_MEMPOOL_NUM, 0U, (uint32_t)osRtxMemoryPoolCbSize, &os_mp_cb[0], NULL, NULL }; // Memory Pool for Memory Pool Data Storage #if (OS_MEMPOOL_DATA_SIZE != 0) -#if ((OS_MEMPOOL_DATA_SIZE & 7) != 0) +#if ((OS_MEMPOOL_DATA_SIZE % 8) != 0) #error "Invalid Data Memory size for Memory Pools!" #endif -static uint64_t os_mp_data[OS_MEMPOOL_DATA_SIZE/8] \ +static uint64_t os_mp_data[2 + OS_MEMPOOL_NUM + (OS_MEMPOOL_DATA_SIZE/8)] \ __attribute__((section(".bss.os.mempool.mem"))); #endif @@ -324,14 +333,14 @@ // Memory Pool for Message Queue Control Blocks static osRtxMpInfo_t os_mpi_mq \ __attribute__((section(".data.os.msgqueue.mpi"))) = -{ (uint32_t)OS_MSGQUEUE_NUM, 0U, (uint32_t)osRtxMessageQueueCbSize, &os_mq_cb, NULL, NULL }; +{ (uint32_t)OS_MSGQUEUE_NUM, 0U, (uint32_t)osRtxMessageQueueCbSize, &os_mq_cb[0], NULL, NULL }; // Memory Pool for Message Queue Data Storage #if (OS_MSGQUEUE_DATA_SIZE != 0) -#if ((OS_MSGQUEUE_DATA_SIZE & 7) != 0) +#if ((OS_MSGQUEUE_DATA_SIZE % 8) != 0) #error "Invalid Data Memory size for Message Queues!" #endif -static uint64_t os_mq_data[OS_MSGQUEUE_DATA_SIZE/8] \ +static uint64_t os_mq_data[2 + OS_MSGQUEUE_NUM + (OS_MSGQUEUE_DATA_SIZE/8)] \ __attribute__((section(".bss.os.msgqueue.mem"))); #endif @@ -341,9 +350,12 @@ // OS Configuration // ================ -__USED -__attribute__((section(".rodata"))) -const osRtxConfig_t osRtxConfig = { + +const osRtxConfig_t osRtxConfig \ +__USED \ +__attribute__((section(".rodata"))) = +{ + //lint -e{835} "Zero argument to operator" 0U // Flags #if (OS_PRIVILEGE_MODE != 0) | osRtxConfigPrivilegedMode @@ -361,26 +373,26 @@ #else 0U, #endif - { &os_isr_queue[0], sizeof(os_isr_queue)/sizeof(void *), 0U }, - { + { &os_isr_queue[0], (uint16_t)(sizeof(os_isr_queue)/sizeof(void *)), 0U }, + { // Memory Pools (Variable Block Size) #if ((OS_THREAD_OBJ_MEM != 0) && (OS_THREAD_USER_STACK_SIZE != 0)) - &os_thread_stack, (uint32_t)OS_THREAD_USER_STACK_SIZE, + &os_thread_stack[0], sizeof(os_thread_stack), #else NULL, 0U, #endif #if ((OS_MEMPOOL_OBJ_MEM != 0) && (OS_MEMPOOL_DATA_SIZE != 0)) - &os_mp_data, (uint32_t)OS_MEMPOOL_DATA_SIZE, + &os_mp_data[0], sizeof(os_mp_data), #else NULL, 0U, #endif #if ((OS_MSGQUEUE_OBJ_MEM != 0) && (OS_MSGQUEUE_DATA_SIZE != 0)) - &os_mq_data, (uint32_t)OS_MSGQUEUE_DATA_SIZE, + &os_mq_data[0], sizeof(os_mq_data), #else NULL, 0U, #endif #if (OS_DYNAMIC_MEM_SIZE != 0) - &os_mem, (uint32_t)OS_DYNAMIC_MEM_SIZE, + &os_mem[0], (uint32_t)OS_DYNAMIC_MEM_SIZE, #else NULL, 0U #endif @@ -395,7 +407,7 @@ #endif &os_mpi_thread, #else - NULL, + NULL, NULL, #endif #if (OS_TIMER_OBJ_MEM != 0) @@ -444,11 +456,17 @@ // Non weak reference to library irq module +//lint -esym(526,irqRtxLib) "Defined by Exception handlers" +//lint -esym(714,irqRtxLibRef) "Non weak reference" +//lint -esym(765,irqRtxLibRef) "Global scope" extern uint8_t irqRtxLib; extern const uint8_t *irqRtxLibRef; const uint8_t *irqRtxLibRef = &irqRtxLib; // Default User SVC Table +//lint -esym(714,osRtxUserSVC) "Referenced by Exception handlers" +//lint -esym(765,osRtxUserSVC) "Global scope" +//lint -e{9067} "extern array declared without size" extern void * const osRtxUserSVC[]; __WEAK void * const osRtxUserSVC[1] = { (void *)0 }; @@ -456,7 +474,47 @@ // OS Sections // =========== +#if defined(__CC_ARM) +__asm void os_cb_sections_wrapper (void) { + EXTERN ||.bss.os.thread.cb$$Base|| [WEAK] + EXTERN ||.bss.os.thread.cb$$Limit|| [WEAK] + EXTERN ||.bss.os.timer.cb$$Base|| [WEAK] + EXTERN ||.bss.os.timer.cb$$Limit|| [WEAK] + EXTERN ||.bss.os.evflags.cb$$Base|| [WEAK] + EXTERN ||.bss.os.evflags.cb$$Limit|| [WEAK] + EXTERN ||.bss.os.mutex.cb$$Base|| [WEAK] + EXTERN ||.bss.os.mutex.cb$$Limit|| [WEAK] + EXTERN ||.bss.os.semaphore.cb$$Base|| [WEAK] + EXTERN ||.bss.os.semaphore.cb$$Limit|| [WEAK] + EXTERN ||.bss.os.mempool.cb$$Base|| [WEAK] + EXTERN ||.bss.os.mempool.cb$$Limit|| [WEAK] + EXTERN ||.bss.os.msgqueue.cb$$Base|| [WEAK] + EXTERN ||.bss.os.msgqueue.cb$$Limit|| [WEAK] + + AREA ||.rodata||, DATA, READONLY + EXPORT os_cb_sections +os_cb_sections + DCD ||.bss.os.thread.cb$$Base|| + DCD ||.bss.os.thread.cb$$Limit|| + DCD ||.bss.os.timer.cb$$Base|| + DCD ||.bss.os.timer.cb$$Limit|| + DCD ||.bss.os.evflags.cb$$Base|| + DCD ||.bss.os.evflags.cb$$Limit|| + DCD ||.bss.os.mutex.cb$$Base|| + DCD ||.bss.os.mutex.cb$$Limit|| + DCD ||.bss.os.semaphore.cb$$Base|| + DCD ||.bss.os.semaphore.cb$$Limit|| + DCD ||.bss.os.mempool.cb$$Base|| + DCD ||.bss.os.mempool.cb$$Limit|| + DCD ||.bss.os.msgqueue.cb$$Base|| + DCD ||.bss.os.msgqueue.cb$$Limit|| + + AREA ||.emb_text||, CODE +}; +#endif + #if (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +//lint -e{19} "Linker symbols" __asm ( ".weakref __os_thread_cb_start__, .bss.os.thread.cb$$Base\n\t" ".weakref __os_thread_cb_end__, .bss.os.thread.cb$$Limit\n\t" @@ -478,27 +536,33 @@ #if (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ (defined(__GNUC__) && !defined(__CC_ARM)) -extern __attribute__((weak)) uint32_t __os_thread_cb_start__; -extern __attribute__((weak)) uint32_t __os_thread_cb_end__; -extern __attribute__((weak)) uint32_t __os_timer_cb_start__; -extern __attribute__((weak)) uint32_t __os_timer_cb_end__; -extern __attribute__((weak)) uint32_t __os_evflags_cb_start__; -extern __attribute__((weak)) uint32_t __os_evflags_cb_end__; -extern __attribute__((weak)) uint32_t __os_mutex_cb_start__; -extern __attribute__((weak)) uint32_t __os_mutex_cb_end__; -extern __attribute__((weak)) uint32_t __os_semaphore_cb_start__; -extern __attribute__((weak)) uint32_t __os_semaphore_cb_end__; -extern __attribute__((weak)) uint32_t __os_mempool_cb_start__; -extern __attribute__((weak)) uint32_t __os_mempool_cb_end__; -extern __attribute__((weak)) uint32_t __os_msgqueue_cb_start__; -extern __attribute__((weak)) uint32_t __os_msgqueue_cb_end__; +extern __attribute__((weak)) uint32_t __os_thread_cb_start__; //lint -esym(526,__os_thread_cb_start__) +extern __attribute__((weak)) uint32_t __os_thread_cb_end__; //lint -esym(526,__os_thread_cb_end__) +extern __attribute__((weak)) uint32_t __os_timer_cb_start__; //lint -esym(526,__os_timer_cb_start__) +extern __attribute__((weak)) uint32_t __os_timer_cb_end__; //lint -esym(526,__os_timer_cb_end__) +extern __attribute__((weak)) uint32_t __os_evflags_cb_start__; //lint -esym(526,__os_evflags_cb_start__) +extern __attribute__((weak)) uint32_t __os_evflags_cb_end__; //lint -esym(526,__os_evflags_cb_end__) +extern __attribute__((weak)) uint32_t __os_mutex_cb_start__; //lint -esym(526,__os_mutex_cb_start__) +extern __attribute__((weak)) uint32_t __os_mutex_cb_end__; //lint -esym(526,__os_mutex_cb_end__) +extern __attribute__((weak)) uint32_t __os_semaphore_cb_start__; //lint -esym(526,__os_semaphore_cb_start__) +extern __attribute__((weak)) uint32_t __os_semaphore_cb_end__; //lint -esym(526,__os_semaphore_cb_end__) +extern __attribute__((weak)) uint32_t __os_mempool_cb_start__; //lint -esym(526,__os_mempool_cb_start__) +extern __attribute__((weak)) uint32_t __os_mempool_cb_end__; //lint -esym(526,__os_mempool_cb_end__) +extern __attribute__((weak)) uint32_t __os_msgqueue_cb_start__; //lint -esym(526,__os_msgqueue_cb_start__) +extern __attribute__((weak)) uint32_t __os_msgqueue_cb_end__; //lint -esym(526,__os_msgqueue_cb_end__) +//lint -e{19} "Global symbol" __asm (".global os_cb_sections"); +//lint -e{9067} "extern array declared without size" extern const uint32_t os_cb_sections[]; -__attribute__((section(".rodata"))) -const uint32_t os_cb_sections[] = { +//lint -esym(714,os_cb_sections) "Referenced by debugger" +//lint -esym(765,os_cb_sections) "Global scope" +//lint -e{923} -e{9078} "cast from pointer to unsigned int" +const uint32_t os_cb_sections[] \ +__attribute__((section(".rodata"))) = +{ (uint32_t)&__os_thread_cb_start__, (uint32_t)&__os_thread_cb_end__, (uint32_t)&__os_timer_cb_start__, @@ -525,9 +589,11 @@ (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) #ifndef __MICROLIB +//lint -esym(714,_platform_post_stackheap_init) "Referenced by C library" +//lint -esym(765,_platform_post_stackheap_init) "Global scope" extern void _platform_post_stackheap_init (void); __WEAK void _platform_post_stackheap_init (void) { - osKernelInitialize(); + (void)osKernelInitialize(); } #endif @@ -535,7 +601,7 @@ extern void software_init_hook (void); __WEAK void software_init_hook (void) { - osKernelInitialize(); + (void)osKernelInitialize(); } #endif @@ -544,19 +610,24 @@ // C/C++ Standard Library Multithreading Interface // =============================================== -#if (( defined(__CC_ARM) || \ +#if ( !defined(RTX_NO_MULTITHREAD_CLIB) && \ + ( defined(__CC_ARM) || \ (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \ !defined(__MICROLIB)) #define LIBSPACE_SIZE 96 +//lint -esym(714,__user_perthread_libspace,_mutex_*) "Referenced by C library" +//lint -esym(765,__user_perthread_libspace,_mutex_*) "Global scope" +//lint -esym(9003, os_libspace*) "variables 'os_libspace*' defined at module scope" + // Memory for libspace -static uint32_t os_libspace[OS_THREAD_LIBSPACE_NUM+1][LIBSPACE_SIZE/sizeof(uint32_t)] \ -__attribute__((section(".bss.os"))); +static uint32_t os_libspace[OS_THREAD_LIBSPACE_NUM+1][LIBSPACE_SIZE/4] \ +__attribute__((section(".bss.os.libspace"))); // Thread IDs for libspace static osThreadId_t os_libspace_id[OS_THREAD_LIBSPACE_NUM] \ -__attribute__((section(".bss.os"))); +__attribute__((section(".bss.os.libspace"))); // Check if Kernel has been started static uint32_t os_kernel_is_active (void) { @@ -565,12 +636,9 @@ if (os_kernel_active == 0U) { if (osKernelGetState() > osKernelReady) { os_kernel_active = 1U; - return 1U; } - return 0U; - } else { - return 1U; } + return (uint32_t)os_kernel_active; } // Provide libspace for current thread @@ -579,53 +647,59 @@ osThreadId_t id; uint32_t n; - if (!os_kernel_is_active()) { - return (void *)&os_libspace[OS_THREAD_LIBSPACE_NUM][0]; - } - - id = osThreadGetId(); - for (n = 0U; n < OS_THREAD_LIBSPACE_NUM; n++) { - if (os_libspace_id[n] == NULL) { - os_libspace_id[n] = id; - return (void *)&os_libspace[n][0]; + if (os_kernel_is_active() != 0U) { + id = osThreadGetId(); + for (n = 0U; n < (uint32_t)OS_THREAD_LIBSPACE_NUM; n++) { + if (os_libspace_id[n] == NULL) { + os_libspace_id[n] = id; + } + if (os_libspace_id[n] == id) { + break; + } } - if (os_libspace_id[n] == id) { - return (void *)&os_libspace[n][0]; + if (n == (uint32_t)OS_THREAD_LIBSPACE_NUM) { + (void)osRtxErrorNotify(osRtxErrorClibSpace, id); } + } else { + n = OS_THREAD_LIBSPACE_NUM; } - if (n == OS_THREAD_LIBSPACE_NUM) { - osRtxErrorNotify(osRtxErrorClibSpace, id); - } - + //lint -e{9087} "cast between pointers to different object types" return (void *)&os_libspace[n][0]; } // Mutex identifier typedef void *mutex; +//lint -save "Function prototypes defined in C library" +//lint -e970 "Use of 'int' outside of a typedef" +//lint -e818 "Pointer 'm' could be declared as pointing to const" + // Initialize mutex #if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050 __USED #endif int _mutex_initialize(mutex *m); __WEAK int _mutex_initialize(mutex *m) { + int result; *m = osMutexNew(NULL); - if (*m == NULL) { - osRtxErrorNotify(osRtxErrorClibMutex, m); - return 0; + if (*m != NULL) { + result = 1; + } else { + result = 0; + (void)osRtxErrorNotify(osRtxErrorClibMutex, m); } - return 1; + return result; } // Acquire mutex #if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050 __USED #endif -void _mutex_acquire(mutex *m); -__WEAK void _mutex_acquire(mutex *m) { - if (os_kernel_is_active()) { - osMutexAcquire(*m, osWaitForever); +__WEAK void _mutex_acquire(mutex *m); +void _mutex_acquire(mutex *m) { + if (os_kernel_is_active() != 0U) { + (void)osMutexAcquire(*m, osWaitForever); } } @@ -633,10 +707,10 @@ #if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050 __USED #endif -void _mutex_release(mutex *m); -__WEAK void _mutex_release(mutex *m) { - if (os_kernel_is_active()) { - osMutexRelease(*m); +__WEAK void _mutex_release(mutex *m); +void _mutex_release(mutex *m) { + if (os_kernel_is_active() != 0U) { + (void)osMutexRelease(*m); } } @@ -644,9 +718,11 @@ #if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050 __USED #endif -void _mutex_free(mutex *m); -__WEAK void _mutex_free(mutex *m) { - osMutexDelete(*m); +__WEAK void _mutex_free(mutex *m); +void _mutex_free(mutex *m) { + (void)osMutexDelete(*m); } +//lint -restore + #endif diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h index e5863f1..1fd876c1 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -27,13 +27,14 @@ #define RTX_LIB_H_ #include -#include #include "rtx_core_c.h" // Cortex core definitions -#if ((__ARM_ARCH_8M_BASE__ != 0) || (__ARM_ARCH_8M_MAIN__ != 0)) +#if ((defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0))) #include "tz_context.h" // TrustZone Context API #endif -#include "os_tick.h" +#include "os_tick.h" // CMSIS OS Tick API #include "cmsis_os2.h" // CMSIS RTOS API +#include "RTX_Config.h" // RTX Configuration #include "rtx_os.h" // RTX OS definitions #include "rtx_evr.h" // RTX Event Recorder definitions @@ -54,37 +55,140 @@ // ==== Inline functions ==== -// Kernel Inline functions -__STATIC_INLINE uint8_t osRtxKernelGetState (void) { return osRtxInfo.kernel.state; } +// Thread ID +__STATIC_INLINE os_thread_t *osRtxThreadId (osThreadId_t thread_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_thread_t *)thread_id); +} +// Timer ID +__STATIC_INLINE os_timer_t *osRtxTimerId (osTimerId_t timer_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_timer_t *)timer_id); +} +// Event Flags ID +__STATIC_INLINE os_event_flags_t *osRtxEventFlagsId (osEventFlagsId_t ef_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_event_flags_t *)ef_id); +} +// Mutex ID +__STATIC_INLINE os_mutex_t *osRtxMutexId (osMutexId_t mutex_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_mutex_t *)mutex_id); +} +// Semaphore ID +__STATIC_INLINE os_semaphore_t *osRtxSemaphoreId (osSemaphoreId_t semaphore_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_semaphore_t *)semaphore_id); +} +// Memory Pool ID +__STATIC_INLINE os_memory_pool_t *osRtxMemoryPoolId (osMemoryPoolId_t mp_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_memory_pool_t *)mp_id); +} +// Message Queue ID +__STATIC_INLINE os_message_queue_t *osRtxMessageQueueId (osMessageQueueId_t mq_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_message_queue_t *)mq_id); +} -// Thread Inline functions -__STATIC_INLINE os_thread_t *osRtxThreadGetRunning (void) { return osRtxInfo.thread.run.curr; } -__STATIC_INLINE void osRtxThreadSetRunning (os_thread_t *thread) { osRtxInfo.thread.run.curr = thread; } +// Generic Object +__STATIC_INLINE os_object_t *osRtxObject (void *object) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 3] + return ((os_object_t *)object); +} + +// Thread Object +__STATIC_INLINE os_thread_t *osRtxThreadObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_thread_t *)object); +} +// Timer Object +__STATIC_INLINE os_timer_t *osRtxTimerObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_timer_t *)object); +} +// Event Flags Object +__STATIC_INLINE os_event_flags_t *osRtxEventFlagsObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_event_flags_t *)object); +} +// Mutex Object +__STATIC_INLINE os_mutex_t *osRtxMutexObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_mutex_t *)object); +} +// Semaphore Object +__STATIC_INLINE os_semaphore_t *osRtxSemaphoreObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_semaphore_t *)object); +} +// Memory Pool Object +__STATIC_INLINE os_memory_pool_t *osRtxMemoryPoolObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_memory_pool_t *)object); +} +// Message Queue Object +__STATIC_INLINE os_message_queue_t *osRtxMessageQueueObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_message_queue_t *)object); +} +// Message Object +__STATIC_INLINE os_message_t *osRtxMessageObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_message_t *)object); +} + +// Kernel State +__STATIC_INLINE osKernelState_t osRtxKernelState (void) { + //lint -e{9030} -e{9034} "cast to enum" + return ((osKernelState_t)(osRtxInfo.kernel.state)); +} + +// Thread State +__STATIC_INLINE osThreadState_t osRtxThreadState (const os_thread_t *thread) { + uint8_t state = thread->state & osRtxThreadStateMask; + //lint -e{9030} -e{9034} "cast to enum" + return ((osThreadState_t)state); +} + +// Thread Priority +__STATIC_INLINE osPriority_t osRtxThreadPriority (const os_thread_t *thread) { + //lint -e{9030} -e{9034} "cast to enum" + return ((osPriority_t)thread->priority); +} + +// Kernel Get State +__STATIC_INLINE uint8_t osRtxKernelGetState (void) { + return osRtxInfo.kernel.state; +} + +// Thread Get/Set Running +__STATIC_INLINE os_thread_t *osRtxThreadGetRunning (void) { + return osRtxInfo.thread.run.curr; +} +__STATIC_INLINE void osRtxThreadSetRunning (os_thread_t *thread) { + osRtxInfo.thread.run.curr = thread; +} // ==== Library functions ==== // Thread Library functions -extern void osRtxThreadListPut (volatile os_object_t *object, os_thread_t *thread); -extern os_thread_t *osRtxThreadListGet (volatile os_object_t *object); -extern void *osRtxThreadListRoot (os_thread_t *thread); -extern void osRtxThreadListSort (os_thread_t *thread); -extern void osRtxThreadListRemove (os_thread_t *thread); -extern void osRtxThreadListUnlink (os_thread_t **thread_list, os_thread_t *thread); -extern void osRtxThreadReadyPut (os_thread_t *thread); -extern void osRtxThreadDelayInsert (os_thread_t *thread, uint32_t delay); -extern void osRtxThreadDelayRemove (os_thread_t *thread); -extern void osRtxThreadDelayTick (void); -extern uint32_t *osRtxThreadRegPtr (os_thread_t *thread); -extern void osRtxThreadBlock (os_thread_t *thread); -extern void osRtxThreadSwitch (os_thread_t *thread); -extern void osRtxThreadDispatch (os_thread_t *thread); -extern void osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool dispatch); -extern bool osRtxThreadWaitEnter (uint8_t state, uint32_t timeout); -extern void osRtxThreadStackCheck (void); +extern void osRtxThreadListPut (os_object_t *object, os_thread_t *thread); +extern os_thread_t *osRtxThreadListGet (os_object_t *object); +extern void osRtxThreadListSort (os_thread_t *thread); +extern void osRtxThreadListRemove (os_thread_t *thread); +extern void osRtxThreadReadyPut (os_thread_t *thread); +extern void osRtxThreadDelayTick (void); +extern uint32_t *osRtxThreadRegPtr (const os_thread_t *thread); +extern void osRtxThreadSwitch (os_thread_t *thread); +extern void osRtxThreadDispatch (os_thread_t *thread); +extern void osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool_t dispatch); +extern bool_t osRtxThreadWaitEnter (uint8_t state, uint32_t timeout); +extern void osRtxThreadStackCheck (void); +extern bool_t osRtxThreadStartup (void); // Timer Library functions -extern void osRtxTimerTick (void); extern void osRtxTimerThread (void *argument); // Mutex Library functions @@ -96,7 +200,7 @@ extern uint32_t osRtxMemoryFree (void *mem, void *block); // Memory Pool Library functions -extern uint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t blocks, uint32_t block_size, void *block_mem); +extern uint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem); extern void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info); extern osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block); @@ -105,113 +209,5 @@ extern void osRtxPendSV_Handler (void); extern void osRtxPostProcess (os_object_t *object); -// Post ISR processing functions -extern void osRtxThreadPostProcess (os_thread_t *thread); -extern void osRtxEventFlagsPostProcess (os_event_flags_t *ef); -extern void osRtxSemaphorePostProcess (os_semaphore_t *semaphore); -extern void osRtxMemoryPoolPostProcess (os_memory_pool_t *mp); -extern void osRtxMessageQueuePostProcess (os_message_t *msg); - - -// ==== Service Calls ==== - -// Kernel Service Calls -extern osStatus_t svcRtxKernelInitialize (void); -extern osStatus_t svcRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); -extern osKernelState_t svcRtxKernelGetState (void); -extern osStatus_t svcRtxKernelStart (void); -extern int32_t svcRtxKernelLock (void); -extern int32_t svcRtxKernelUnlock (void); -extern int32_t svcRtxKernelRestoreLock (int32_t lock); -extern uint32_t svcRtxKernelSuspend (void); -extern void svcRtxKernelResume (uint32_t sleep_ticks); -extern uint32_t svcRtxKernelGetTickCount (void); -extern uint32_t svcRtxKernelGetTickFreq (void); -extern uint32_t svcRtxKernelGetSysTimerCount (void); -extern uint32_t svcRtxKernelGetSysTimerFreq (void); - -// Thread Service Calls -extern osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr, void *context); -extern const char * svcRtxThreadGetName (osThreadId_t thread_id); -extern osThreadId_t svcRtxThreadGetId (void); -extern osThreadState_t svcRtxThreadGetState (osThreadId_t thread_id); -extern uint32_t svcRtxThreadGetStackSize (osThreadId_t thread_id); -extern uint32_t svcRtxThreadGetStackSpace(osThreadId_t thread_id); -extern osStatus_t svcRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); -extern osPriority_t svcRtxThreadGetPriority (osThreadId_t thread_id); -extern osStatus_t svcRtxThreadYield (void); -extern osStatus_t svcRtxThreadSuspend (osThreadId_t thread_id); -extern osStatus_t svcRtxThreadResume (osThreadId_t thread_id); -extern osStatus_t svcRtxThreadDetach (osThreadId_t thread_id); -extern osStatus_t svcRtxThreadJoin (osThreadId_t thread_id); -extern void svcRtxThreadExit (void); -extern osStatus_t svcRtxThreadTerminate (osThreadId_t thread_id); -extern uint32_t svcRtxThreadGetCount (void); -extern uint32_t svcRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); -extern uint32_t svcRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); -extern uint32_t svcRtxThreadFlagsClear (uint32_t flags); -extern uint32_t svcRtxThreadFlagsGet (void); -extern uint32_t svcRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); - -// Delay Service Calls -extern osStatus_t svcRtxDelay (uint32_t ticks); -extern osStatus_t svcRtxDelayUntil (uint32_t ticks); - -// Timer Service Calls -extern osTimerId_t svcRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); -extern const char * svcRtxTimerGetName (osTimerId_t timer_id); -extern osStatus_t svcRtxTimerStart (osTimerId_t timer_id, uint32_t ticks); -extern osStatus_t svcRtxTimerStop (osTimerId_t timer_id); -extern uint32_t svcRtxTimerIsRunning (osTimerId_t timer_id); -extern osStatus_t svcRtxTimerDelete (osTimerId_t timer_id); - -// Event Flags Service Calls -extern osEventFlagsId_t svcRtxEventFlagsNew (const osEventFlagsAttr_t *attr); -extern const char * svcRtxEventFlagsGetName (osEventFlagsId_t ef_id); -extern uint32_t svcRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); -extern uint32_t svcRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); -extern uint32_t svcRtxEventFlagsGet (osEventFlagsId_t ef_id); -extern uint32_t svcRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); -extern osStatus_t svcRtxEventFlagsDelete (osEventFlagsId_t ef_id); - -// Mutex Service Calls -extern osMutexId_t svcRtxMutexNew (const osMutexAttr_t *attr); -extern const char * svcRtxMutexGetName (osMutexId_t mutex_id); -extern osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); -extern osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id); -extern osThreadId_t svcRtxMutexGetOwner (osMutexId_t mutex_id); -extern osStatus_t svcRtxMutexDelete (osMutexId_t mutex_id); - -// Semaphore Service Calls -extern osSemaphoreId_t svcRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); -extern const char * svcRtxSemaphoreGetName (osSemaphoreId_t semaphore_id); -extern osStatus_t svcRtxSemaphoreRelease (osSemaphoreId_t semaphore_id); -extern osStatus_t svcRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); -extern uint32_t svcRtxSemaphoreGetCount(osSemaphoreId_t semaphore_id); -extern osStatus_t svcRtxSemaphoreDelete (osSemaphoreId_t semaphore_id); - -// Memory Pool Service Calls -extern osMemoryPoolId_t svcRtxMemoryPoolNew (uint32_t blocks, uint32_t block_size, const osMemoryPoolAttr_t *attr); -extern const char * svcRtxMemoryPoolGetName (osMemoryPoolId_t mp_id); -extern void * svcRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); -extern osStatus_t svcRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); -extern uint32_t svcRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); -extern uint32_t svcRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); -extern uint32_t svcRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id); -extern uint32_t svcRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id); -extern osStatus_t svcRtxMemoryPoolDelete (osMemoryPoolId_t mp_id); - -// Message Queue Service Calls -extern osMessageQueueId_t svcRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); -extern const char * svcRtxMessageQueueGetName (osMessageQueueId_t mq_id); -extern osStatus_t svcRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); -extern osStatus_t svcRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); -extern uint32_t svcRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id); -extern uint32_t svcRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id); -extern uint32_t svcRtxMessageQueueGetCount (osMessageQueueId_t mq_id); -extern uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_id); -extern osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id); -extern osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id); - #endif // RTX_LIB_H_ diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_memory.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_memory.c index f86e802..b22bfda 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_memory.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_memory.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ // Memory Pool Header structure -typedef struct mem_head_s { +typedef struct { uint32_t size; // Memory Pool size uint32_t used; // Used Memory } mem_head_t; @@ -35,11 +35,30 @@ // Memory Block Header structure typedef struct mem_block_s { struct mem_block_s *next; // Next Memory Block in list - uint32_t info; // Info: length = <31:2>:'00', type = <1:0> + uint32_t info; // Block Info or max used Memory (in last block) } mem_block_t; -#define MB_INFO_LEN_MASK 0xFFFFFFFCU -#define MB_INFO_TYPE_MASK 0x00000003U +// Memory Block Info: Length = <31:2>:'00', Type = <1:0> +#define MB_INFO_LEN_MASK 0xFFFFFFFCU // Length mask +#define MB_INFO_TYPE_MASK 0x00000003U // Type mask + +// Memory Head Pointer +__STATIC_INLINE mem_head_t *MemHeadPtr (void *mem) { + //lint -e{9079} -e{9087} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + return ((mem_head_t *)mem); +} + +// Memory Block Pointer +__STATIC_INLINE mem_block_t *MemBlockPtr (void *mem, uint32_t offset) { + uint32_t addr; + mem_block_t *ptr; + + //lint --e{923} --e{9078} "cast between pointer and unsigned int" [MISRA Note 8] + addr = (uint32_t)mem + offset; + ptr = (mem_block_t *)addr; + + return ptr; +} // ==== Library functions ==== @@ -52,19 +71,25 @@ mem_head_t *head; mem_block_t *ptr; - if ((mem == NULL) || ((uint32_t)mem & 7U) || (size & 7U) || - (size < (sizeof(mem_head_t) + 2*sizeof(mem_block_t)))) { + // Check parameters + //lint -e{923} "cast from pointer to unsigned int" [MISRA Note 7] + if ((mem == NULL) || (((uint32_t)mem & 7U) != 0U) || ((size & 7U) != 0U) || + (size < (sizeof(mem_head_t) + (2U*sizeof(mem_block_t))))) { EvrRtxMemoryInit(mem, size, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } - head = (mem_head_t *)mem; + // Initialize memory pool header + head = MemHeadPtr(mem); head->size = size; head->used = sizeof(mem_head_t) + sizeof(mem_block_t); - ptr = (mem_block_t *)((uint32_t)mem + sizeof(mem_head_t)); - ptr->next = (mem_block_t *)((uint32_t)mem + size - sizeof(mem_block_t)); + // Initialize first and last block header + ptr = MemBlockPtr(mem, sizeof(mem_head_t)); + ptr->next = MemBlockPtr(mem, size - sizeof(mem_block_t)); ptr->next->next = NULL; + ptr->next->info = sizeof(mem_head_t) + sizeof(mem_block_t); ptr->info = 0U; EvrRtxMemoryInit(mem, size, 1U); @@ -78,25 +103,30 @@ /// \param[in] type memory block type: 0 - generic, 1 - control block /// \return allocated memory block or NULL in case of no memory is available. __WEAK void *osRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type) { - mem_block_t *p, *p_new, *ptr; + mem_block_t *ptr; + mem_block_t *p, *p_new; + uint32_t block_size; uint32_t hole_size; - if ((mem == NULL) || (size == 0U) || (type & ~MB_INFO_TYPE_MASK)) { + // Check parameters + if ((mem == NULL) || (size == 0U) || ((type & ~MB_INFO_TYPE_MASK) != 0U)) { EvrRtxMemoryAlloc(mem, size, type, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } - // Add header to size - size += sizeof(mem_block_t); + // Add block header to size + block_size = size + sizeof(mem_block_t); // Make sure that block is 8-byte aligned - size = (size + 7U) & ~((uint32_t)7U); + block_size = (block_size + 7U) & ~((uint32_t)7U); // Search for hole big enough - p = (mem_block_t *)((uint32_t)mem + sizeof(mem_head_t)); + p = MemBlockPtr(mem, sizeof(mem_head_t)); for (;;) { + //lint -e{923} -e{9078} "cast from pointer to unsigned int" hole_size = (uint32_t)p->next - (uint32_t)p; hole_size -= p->info & MB_INFO_LEN_MASK; - if (hole_size >= size) { + if (hole_size >= block_size) { // Hole found break; } @@ -104,23 +134,32 @@ if (p->next == NULL) { // Failed (end of list) EvrRtxMemoryAlloc(mem, size, type, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } - ((mem_head_t *)mem)->used += size; + // Update used memory + (MemHeadPtr(mem))->used += block_size; + // Update max used memory + p_new = MemBlockPtr(mem, (MemHeadPtr(mem))->size - sizeof(mem_block_t)); + if (p_new->info < (MemHeadPtr(mem))->used) { + p_new->info = (MemHeadPtr(mem))->used; + } + + // Allocate block if (p->info == 0U) { // No block allocated, set info of first element - p->info = size | type; - ptr = (mem_block_t *)((uint32_t)p + sizeof(mem_block_t)); + p->info = block_size | type; + ptr = MemBlockPtr(p, sizeof(mem_block_t)); } else { // Insert new element into the list - p_new = (mem_block_t *)((uint32_t)p + (p->info & MB_INFO_LEN_MASK)); + p_new = MemBlockPtr(p, p->info & MB_INFO_LEN_MASK); p_new->next = p->next; - p_new->info = size | type; + p_new->info = block_size | type; p->next = p_new; - ptr = (mem_block_t *)((uint32_t)p_new + sizeof(mem_block_t)); + ptr = MemBlockPtr(p_new, sizeof(mem_block_t)); } EvrRtxMemoryAlloc(mem, size, type, ptr); @@ -133,30 +172,38 @@ /// \param[in] block memory block to be returned to the memory pool. /// \return 1 - success, 0 - failure. __WEAK uint32_t osRtxMemoryFree (void *mem, void *block) { - mem_block_t *p, *p_prev, *ptr; + const mem_block_t *ptr; + mem_block_t *p, *p_prev; + // Check parameters if ((mem == NULL) || (block == NULL)) { EvrRtxMemoryFree(mem, block, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } - ptr = (mem_block_t *)((uint32_t)block - sizeof(mem_block_t)); + // Memory block header + ptr = MemBlockPtr(block, 0U); + ptr--; - // Search for header + // Search for block header p_prev = NULL; - p = (mem_block_t *)((uint32_t)mem + sizeof(mem_head_t)); + p = MemBlockPtr(mem, sizeof(mem_head_t)); while (p != ptr) { p_prev = p; p = p->next; if (p == NULL) { // Not found EvrRtxMemoryFree(mem, block, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } } - ((mem_head_t *)mem)->used -= p->info & MB_INFO_LEN_MASK; + // Update used memory + (MemHeadPtr(mem))->used -= p->info & MB_INFO_LEN_MASK; + // Free block if (p_prev == NULL) { // Release first block, only set info to 0 p->info = 0U; diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mempool.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mempool.c index 63bb32a..849b156 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mempool.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mempool.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,6 +26,14 @@ #include "rtx_lib.h" +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxMemoryPoolMemUsage \ +__attribute__((section(".data.os.mempool.obj"))) = +{ 0U, 0U, 0U }; +#endif + + // ==== Library functions ==== /// Initialize Memory Pool. @@ -35,10 +43,13 @@ /// \param[in] block_mem pointer to memory for block storage. /// \return 1 - success, 0 - failure. uint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem) { + //lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + void *mem; void *block; // Check parameters - if ((mp_info == NULL) || (block_count == 0U) || (block_size == 0U) || (block_mem == NULL)) { + if ((mp_info == NULL) || (block_count == 0U) || (block_size == 0U) || (block_mem == NULL)) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -48,17 +59,18 @@ mp_info->block_size = block_size; mp_info->block_base = block_mem; mp_info->block_free = block_mem; - mp_info->block_lim = (uint8_t *)block_mem + (block_count * block_size); + mp_info->block_lim = &(((uint8_t *)block_mem)[block_count * block_size]); EvrRtxMemoryBlockInit(mp_info, block_count, block_size, block_mem); // Link all free blocks - while (--block_count) { - block = (uint8_t *)block_mem + block_size; - *((void **)block_mem) = block; - block_mem = block; + mem = block_mem; + while (--block_count != 0U) { + block = &((uint8_t *)mem)[block_size]; + *((void **)mem) = block; + mem = block; } - *((void **)block_mem) = NULL; + *((void **)mem) = NULL; return 1U; } @@ -67,23 +79,25 @@ /// \param[in] mp_info memory pool info. /// \return address of the allocated memory block or NULL in case of no memory is available. void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif void *block; if (mp_info == NULL) { EvrRtxMemoryBlockAlloc(NULL, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); if (mp_info->used_blocks < mp_info->max_blocks) { mp_info->used_blocks++; block = mp_info->block_free; if (block != NULL) { + //lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" mp_info->block_free = *((void **)block); } } else { @@ -111,21 +125,24 @@ /// \param[in] block address of the allocated memory block to be returned to the memory pool. /// \return status code that indicates the execution status of the function. osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif osStatus_t status; + //lint -e{946} "Relational operator applied to pointers" if ((mp_info == NULL) || (block < mp_info->block_base) || (block >= mp_info->block_lim)) { - EvrRtxMemoryBlockFree(mp_info, block, osErrorParameter); + EvrRtxMemoryBlockFree(mp_info, block, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); if (mp_info->used_blocks != 0U) { mp_info->used_blocks--; + //lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" *((void **)block) = mp_info->block_free; mp_info->block_free = block; status = osOK; @@ -145,18 +162,22 @@ } #endif - EvrRtxMemoryBlockFree(mp_info, block, status); + EvrRtxMemoryBlockFree(mp_info, block, (int32_t)status); return status; } + +// ==== Post ISR processing ==== + /// Memory Pool post ISR processing. /// \param[in] mp memory pool object. -void osRtxMemoryPoolPostProcess (os_memory_pool_t *mp) { +static void osRtxMemoryPoolPostProcess (os_memory_pool_t *mp) { void *block; os_thread_t *thread; if (mp->state == osRtxObjectInactive) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } @@ -166,8 +187,9 @@ block = osRtxMemoryPoolAlloc(&mp->mp_info); if (block != NULL) { // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)mp); - osRtxThreadWaitExit(thread, (uint32_t)block, false); + thread = osRtxThreadListGet(osRtxObject(mp)); + //lint -e{923} "cast from pointer to unsigned int" + osRtxThreadWaitExit(thread, (uint32_t)block, FALSE); EvrRtxMemoryPoolAllocated(mp, block); } } @@ -176,65 +198,67 @@ // ==== Service Calls ==== -// Service Calls definitions -SVC0_3M(MemoryPoolNew, osMemoryPoolId_t, uint32_t, uint32_t, const osMemoryPoolAttr_t *) -SVC0_1 (MemoryPoolGetName, const char *, osMemoryPoolId_t) -SVC0_2 (MemoryPoolAlloc, void *, osMemoryPoolId_t, uint32_t) -SVC0_2 (MemoryPoolFree, osStatus_t, osMemoryPoolId_t, void *) -SVC0_1 (MemoryPoolGetCapacity, uint32_t, osMemoryPoolId_t) -SVC0_1 (MemoryPoolGetBlockSize, uint32_t, osMemoryPoolId_t) -SVC0_1 (MemoryPoolGetCount, uint32_t, osMemoryPoolId_t) -SVC0_1 (MemoryPoolGetSpace, uint32_t, osMemoryPoolId_t) -SVC0_1 (MemoryPoolDelete, osStatus_t, osMemoryPoolId_t) - /// Create and Initialize a Memory Pool object. /// \note API identical to osMemoryPoolNew -osMemoryPoolId_t svcRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { +static osMemoryPoolId_t svcRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { os_memory_pool_t *mp; void *mp_mem; uint32_t mp_size; + uint32_t b_count; + uint32_t b_size; uint32_t size; uint8_t flags; const char *name; // Check parameters if ((block_count == 0U) || (block_size == 0U)) { - EvrRtxMemoryPoolError(NULL, osErrorParameter); + EvrRtxMemoryPoolError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } - block_size = (block_size + 3U) & ~3UL; - if ((__CLZ(block_count) + __CLZ(block_size)) < 32) { - EvrRtxMemoryPoolError(NULL, osErrorParameter); + b_count = block_count; + b_size = (block_size + 3U) & ~3UL; + if ((__CLZ(b_count) + __CLZ(b_size)) < 32U) { + EvrRtxMemoryPoolError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } - size = block_count * block_size; + size = b_count * b_size; // Process attributes if (attr != NULL) { name = attr->name; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] mp = attr->cb_mem; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] mp_mem = attr->mp_mem; mp_size = attr->mp_size; if (mp != NULL) { - if (((uint32_t)mp & 3U) || (attr->cb_size < sizeof(os_memory_pool_t))) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)mp & 3U) != 0U) || (attr->cb_size < sizeof(os_memory_pool_t))) { EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } else { if (attr->cb_size != 0U) { EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } if (mp_mem != NULL) { - if (((uint32_t)mp_mem & 3U) || (mp_size < size)) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)mp_mem & 3U) != 0U) || (mp_size < size)) { EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidDataMemory); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } else { if (mp_size != 0U) { EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidDataMemory); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } @@ -247,67 +271,85 @@ // Allocate object memory if not provided if (mp == NULL) { if (osRtxInfo.mpi.memory_pool != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] mp = osRtxMemoryPoolAlloc(osRtxInfo.mpi.memory_pool); } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] mp = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_memory_pool_t), 1U); } - if (mp == NULL) { - EvrRtxMemoryPoolError(NULL, osErrorNoMemory); - return NULL; +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (mp != NULL) { + uint32_t used; + osRtxMemoryPoolMemUsage.cnt_alloc++; + used = osRtxMemoryPoolMemUsage.cnt_alloc - osRtxMemoryPoolMemUsage.cnt_free; + if (osRtxMemoryPoolMemUsage.max_used < used) { + osRtxMemoryPoolMemUsage.max_used = used; + } } +#endif flags = osRtxFlagSystemObject; } else { flags = 0U; } // Allocate data memory if not provided - if (mp_mem == NULL) { + if ((mp != NULL) && (mp_mem == NULL)) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] mp_mem = osRtxMemoryAlloc(osRtxInfo.mem.mp_data, size, 0U); if (mp_mem == NULL) { - EvrRtxMemoryPoolError(NULL, osErrorNoMemory); - if (flags & osRtxFlagSystemObject) { + if ((flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.memory_pool != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp); } else { - osRtxMemoryFree(osRtxInfo.mem.common, mp); + (void)osRtxMemoryFree(osRtxInfo.mem.common, mp); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxMemoryPoolMemUsage.cnt_free++; +#endif } - return NULL; + mp = NULL; + } else { + memset(mp_mem, 0, size); } - memset(mp_mem, 0, size); flags |= osRtxFlagSystemMemory; } - // Initialize control block - mp->id = osRtxIdMemoryPool; - mp->state = osRtxObjectActive; - mp->flags = flags; - mp->name = name; - mp->thread_list = NULL; - osRtxMemoryPoolInit(&mp->mp_info, block_count, block_size, mp_mem); + if (mp != NULL) { + // Initialize control block + mp->id = osRtxIdMemoryPool; + mp->state = osRtxObjectActive; + mp->flags = flags; + mp->name = name; + mp->thread_list = NULL; + (void)osRtxMemoryPoolInit(&mp->mp_info, b_count, b_size, mp_mem); - // Register post ISR processing function - osRtxInfo.post_process.memory_pool = osRtxMemoryPoolPostProcess; + // Register post ISR processing function + osRtxInfo.post_process.memory_pool = osRtxMemoryPoolPostProcess; - EvrRtxMemoryPoolCreated(mp); + EvrRtxMemoryPoolCreated(mp, mp->name); + } else { + EvrRtxMemoryPoolError(NULL, (int32_t)osErrorNoMemory); + } return mp; } /// Get name of a Memory Pool object. /// \note API identical to osMemoryPoolGetName -const char *svcRtxMemoryPoolGetName (osMemoryPoolId_t mp_id) { - os_memory_pool_t *mp = (os_memory_pool_t *)mp_id; +static const char *svcRtxMemoryPoolGetName (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); // Check parameters if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { EvrRtxMemoryPoolGetName(mp, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check object state if (mp->state == osRtxObjectInactive) { EvrRtxMemoryPoolGetName(mp, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -318,36 +360,41 @@ /// Allocate a memory block from a Memory Pool. /// \note API identical to osMemoryPoolAlloc -void *svcRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { - os_memory_pool_t *mp = (os_memory_pool_t *)mp_id; +static void *svcRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); void *block; // Check parameters if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { - EvrRtxMemoryPoolError(mp, osErrorParameter); + EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check object state if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolError(mp, osErrorResource); + EvrRtxMemoryPoolError(mp, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Allocate memory block = osRtxMemoryPoolAlloc(&mp->mp_info); - if (block == NULL) { + if (block != NULL) { + EvrRtxMemoryPoolAllocated(mp, block); + } else { // No memory available if (timeout != 0U) { EvrRtxMemoryPoolAllocPending(mp, timeout); // Suspend current Thread - osRtxThreadListPut((os_object_t*)mp, osRtxThreadGetRunning()); - osRtxThreadWaitEnter(osRtxThreadWaitingMemoryPool, timeout); + if (osRtxThreadWaitEnter(osRtxThreadWaitingMemoryPool, timeout)) { + osRtxThreadListPut(osRtxObject(mp), osRtxThreadGetRunning()); + } else { + EvrRtxMemoryPoolAllocTimeout(mp); + } } else { EvrRtxMemoryPoolAllocFailed(mp); } - } else { - EvrRtxMemoryPoolAllocated(mp, block); } return block; @@ -355,20 +402,23 @@ /// Return an allocated memory block back to a Memory Pool. /// \note API identical to osMemoryPoolFree -osStatus_t svcRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { - os_memory_pool_t *mp = (os_memory_pool_t *)mp_id; +static osStatus_t svcRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + void *block0; os_thread_t *thread; osStatus_t status; // Check parameters if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { - EvrRtxMemoryPoolError(mp, osErrorParameter); + EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolError(mp, osErrorResource); + EvrRtxMemoryPoolError(mp, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -379,12 +429,13 @@ // Check if Thread is waiting to allocate memory if (mp->thread_list != NULL) { // Allocate memory - block = osRtxMemoryPoolAlloc(&mp->mp_info); - if (block != NULL) { + block0 = osRtxMemoryPoolAlloc(&mp->mp_info); + if (block0 != NULL) { // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)mp); - osRtxThreadWaitExit(thread, (uint32_t)block, true); - EvrRtxMemoryPoolAllocated(mp, block); + thread = osRtxThreadListGet(osRtxObject(mp)); + //lint -e{923} "cast from pointer to unsigned int" + osRtxThreadWaitExit(thread, (uint32_t)block0, TRUE); + EvrRtxMemoryPoolAllocated(mp, block0); } } } else { @@ -396,18 +447,20 @@ /// Get maximum number of memory blocks in a Memory Pool. /// \note API identical to osMemoryPoolGetCapacity -uint32_t svcRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) { - os_memory_pool_t *mp = (os_memory_pool_t *)mp_id; +static uint32_t svcRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); // Check parameters if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { EvrRtxMemoryPoolGetCapacity(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (mp->state == osRtxObjectInactive) { EvrRtxMemoryPoolGetCapacity(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -418,18 +471,20 @@ /// Get memory block size in a Memory Pool. /// \note API identical to osMemoryPoolGetBlockSize -uint32_t svcRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) { - os_memory_pool_t *mp = (os_memory_pool_t *)mp_id; +static uint32_t svcRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); // Check parameters if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { EvrRtxMemoryPoolGetBlockSize(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (mp->state == osRtxObjectInactive) { EvrRtxMemoryPoolGetBlockSize(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -440,18 +495,20 @@ /// Get number of memory blocks used in a Memory Pool. /// \note API identical to osMemoryPoolGetCount -uint32_t svcRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id) { - os_memory_pool_t *mp = (os_memory_pool_t *)mp_id; +static uint32_t svcRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); // Check parameters if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { EvrRtxMemoryPoolGetCount(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (mp->state == osRtxObjectInactive) { EvrRtxMemoryPoolGetCount(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -462,18 +519,20 @@ /// Get number of memory blocks available in a Memory Pool. /// \note API identical to osMemoryPoolGetSpace -uint32_t svcRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id) { - os_memory_pool_t *mp = (os_memory_pool_t *)mp_id; +static uint32_t svcRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); // Check parameters if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { EvrRtxMemoryPoolGetSpace(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (mp->state == osRtxObjectInactive) { EvrRtxMemoryPoolGetSpace(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -484,19 +543,21 @@ /// Delete a Memory Pool object. /// \note API identical to osMemoryPoolDelete -osStatus_t svcRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) { - os_memory_pool_t *mp = (os_memory_pool_t *)mp_id; +static osStatus_t svcRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); os_thread_t *thread; // Check parameters if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { - EvrRtxMemoryPoolError(mp, osErrorParameter); + EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolError(mp, osErrorResource); + EvrRtxMemoryPoolError(mp, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -506,24 +567,27 @@ // Unblock waiting threads if (mp->thread_list != NULL) { do { - thread = osRtxThreadListGet((os_object_t*)mp); - osRtxThreadWaitExit(thread, 0U, false); + thread = osRtxThreadListGet(osRtxObject(mp)); + osRtxThreadWaitExit(thread, 0U, FALSE); } while (mp->thread_list != NULL); osRtxThreadDispatch(NULL); } // Free data memory - if (mp->flags & osRtxFlagSystemMemory) { - osRtxMemoryFree(osRtxInfo.mem.mp_data, mp->mp_info.block_base); + if ((mp->flags & osRtxFlagSystemMemory) != 0U) { + (void)osRtxMemoryFree(osRtxInfo.mem.mp_data, mp->mp_info.block_base); } // Free object memory - if (mp->flags & osRtxFlagSystemObject) { + if ((mp->flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.memory_pool != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp); } else { - osRtxMemoryFree(osRtxInfo.mem.common, mp); + (void)osRtxMemoryFree(osRtxInfo.mem.common, mp); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxMemoryPoolMemUsage.cnt_free++; +#endif } EvrRtxMemoryPoolDestroyed(mp); @@ -531,6 +595,19 @@ return osOK; } +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_3(MemoryPoolNew, osMemoryPoolId_t, uint32_t, uint32_t, const osMemoryPoolAttr_t *) +SVC0_1(MemoryPoolGetName, const char *, osMemoryPoolId_t) +SVC0_2(MemoryPoolAlloc, void *, osMemoryPoolId_t, uint32_t) +SVC0_2(MemoryPoolFree, osStatus_t, osMemoryPoolId_t, void *) +SVC0_1(MemoryPoolGetCapacity, uint32_t, osMemoryPoolId_t) +SVC0_1(MemoryPoolGetBlockSize, uint32_t, osMemoryPoolId_t) +SVC0_1(MemoryPoolGetCount, uint32_t, osMemoryPoolId_t) +SVC0_1(MemoryPoolGetSpace, uint32_t, osMemoryPoolId_t) +SVC0_1(MemoryPoolDelete, osStatus_t, osMemoryPoolId_t) +//lint --flb "Library End" + // ==== ISR Calls ==== @@ -538,18 +615,20 @@ /// \note API identical to osMemoryPoolAlloc __STATIC_INLINE void *isrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { - os_memory_pool_t *mp = (os_memory_pool_t *)mp_id; + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); void *block; // Check parameters if ((mp == NULL) || (mp->id != osRtxIdMemoryPool) || (timeout != 0U)) { - EvrRtxMemoryPoolError(mp, osErrorParameter); + EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check object state if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolError(mp, osErrorResource); + EvrRtxMemoryPoolError(mp, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -568,18 +647,20 @@ /// \note API identical to osMemoryPoolFree __STATIC_INLINE osStatus_t isrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { - os_memory_pool_t *mp = (os_memory_pool_t *)mp_id; + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); osStatus_t status; // Check parameters if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { - EvrRtxMemoryPoolError(mp, osErrorParameter); + EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolError(mp, osErrorResource); + EvrRtxMemoryPoolError(mp, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -587,7 +668,7 @@ status = osRtxMemoryPoolFree(&mp->mp_info, block); if (status == osOK) { // Register post ISR processing - osRtxPostProcess((os_object_t *)mp); + osRtxPostProcess(osRtxObject(mp)); EvrRtxMemoryPoolDeallocated(mp, block); } else { EvrRtxMemoryPoolFreeFailed(mp, block); @@ -601,85 +682,115 @@ /// Create and Initialize a Memory Pool object. osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { + osMemoryPoolId_t mp_id; + EvrRtxMemoryPoolNew(block_count, block_size, attr); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxMemoryPoolError(NULL, osErrorISR); - return NULL; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMemoryPoolError(NULL, (int32_t)osErrorISR); + mp_id = NULL; + } else { + mp_id = __svcMemoryPoolNew(block_count, block_size, attr); } - return __svcMemoryPoolNew(block_count, block_size, attr); + return mp_id; } /// Get name of a Memory Pool object. const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxMemoryPoolGetName(mp_id, NULL); - return NULL; + name = NULL; + } else { + name = __svcMemoryPoolGetName(mp_id); } - return __svcMemoryPoolGetName(mp_id); + return name; } /// Allocate a memory block from a Memory Pool. void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { + void *memory; + EvrRtxMemoryPoolAlloc(mp_id, timeout); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return isrRtxMemoryPoolAlloc(mp_id, timeout); + if (IsIrqMode() || IsIrqMasked()) { + memory = isrRtxMemoryPoolAlloc(mp_id, timeout); } else { - return __svcMemoryPoolAlloc(mp_id, timeout); + memory = __svcMemoryPoolAlloc(mp_id, timeout); } + return memory; } /// Return an allocated memory block back to a Memory Pool. osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { + osStatus_t status; + EvrRtxMemoryPoolFree(mp_id, block); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return isrRtxMemoryPoolFree(mp_id, block); + if (IsIrqMode() || IsIrqMasked()) { + status = isrRtxMemoryPoolFree(mp_id, block); } else { - return __svcMemoryPoolFree(mp_id, block); + status = __svcMemoryPoolFree(mp_id, block); } + return status; } /// Get maximum number of memory blocks in a Memory Pool. uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxMemoryPoolGetCapacity(mp_id); + uint32_t capacity; + + if (IsIrqMode() || IsIrqMasked()) { + capacity = svcRtxMemoryPoolGetCapacity(mp_id); } else { - return __svcMemoryPoolGetCapacity(mp_id); + capacity = __svcMemoryPoolGetCapacity(mp_id); } + return capacity; } /// Get memory block size in a Memory Pool. uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxMemoryPoolGetBlockSize(mp_id); + uint32_t block_size; + + if (IsIrqMode() || IsIrqMasked()) { + block_size = svcRtxMemoryPoolGetBlockSize(mp_id); } else { - return __svcMemoryPoolGetBlockSize(mp_id); + block_size = __svcMemoryPoolGetBlockSize(mp_id); } + return block_size; } /// Get number of memory blocks used in a Memory Pool. uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxMemoryPoolGetCount(mp_id); + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + count = svcRtxMemoryPoolGetCount(mp_id); } else { - return __svcMemoryPoolGetCount(mp_id); + count = __svcMemoryPoolGetCount(mp_id); } + return count; } /// Get number of memory blocks available in a Memory Pool. uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxMemoryPoolGetSpace(mp_id); + uint32_t space; + + if (IsIrqMode() || IsIrqMasked()) { + space = svcRtxMemoryPoolGetSpace(mp_id); } else { - return __svcMemoryPoolGetSpace(mp_id); + space = __svcMemoryPoolGetSpace(mp_id); } + return space; } /// Delete a Memory Pool object. osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) { + osStatus_t status; + EvrRtxMemoryPoolDelete(mp_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxMemoryPoolError(mp_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMemoryPoolError(mp_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMemoryPoolDelete(mp_id); } - return __svcMemoryPoolDelete(mp_id); + return status; } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c index ae33f64..9fbffdb 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,13 +26,21 @@ #include "rtx_lib.h" +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxMessageQueueMemUsage \ +__attribute__((section(".data.os.msgqueue.obj"))) = +{ 0U, 0U, 0U }; +#endif + + // ==== Helper functions ==== /// Put a Message into Queue sorted by Priority (Highest at Head). /// \param[in] mq message queue object. /// \param[in] msg message object. static void MessageQueuePut (os_message_queue_t *mq, os_message_t *msg) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif os_message_t *prev, *next; @@ -63,7 +71,7 @@ mq->msg_last = msg; } -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); mq->msg_count++; @@ -72,7 +80,7 @@ __enable_irq(); } #else - atomic_inc32(&mq->msg_count); + (void)atomic_inc32(&mq->msg_count); #endif } @@ -80,14 +88,14 @@ /// \param[in] mq message queue object. /// \return message object or NULL. static os_message_t *MessageQueueGet (os_message_queue_t *mq) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif os_message_t *msg; uint32_t count; uint8_t flags; -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); count = mq->msg_count; @@ -102,29 +110,29 @@ count = atomic_dec32_nz(&mq->msg_count); #endif - if (count == 0U) { - return NULL; - } + if (count != 0U) { + msg = mq->msg_first; - msg = mq->msg_first; + while (msg != NULL) { +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); - while (msg != NULL) { -#if (__EXCLUSIVE_ACCESS == 0U) - __disable_irq(); + flags = msg->flags; + msg->flags = 1U; - flags = msg->flags; - msg->flags = 1U; - - if (primask == 0U) { - __enable_irq(); - } + if (primask == 0U) { + __enable_irq(); + } #else - flags = atomic_wr8(&msg->flags, 1U); + flags = atomic_wr8(&msg->flags, 1U); #endif - if (flags == 0U) { - break; + if (flags == 0U) { + break; + } + msg = msg->next; } - msg = msg->next; + } else { + msg = NULL; } return msg; @@ -133,7 +141,7 @@ /// Remove a Message from Queue /// \param[in] mq message queue object. /// \param[in] msg message object. -static void MessageQueueRemove (os_message_queue_t *mq, os_message_t *msg) { +static void MessageQueueRemove (os_message_queue_t *mq, const os_message_t *msg) { if (msg->prev != NULL) { msg->prev->next = msg->next; @@ -148,75 +156,89 @@ } -// ==== Library functions ==== +// ==== Post ISR processing ==== /// Message Queue post ISR processing. /// \param[in] msg message object. -void osRtxMessageQueuePostProcess (os_message_t *msg) { +static void osRtxMessageQueuePostProcess (os_message_t *msg) { os_message_queue_t *mq; + os_message_t *msg0; os_thread_t *thread; - uint32_t *reg; - void **ptr; + const uint32_t *reg; + const void *ptr_src; + void *ptr_dst; if (msg->state == osRtxObjectInactive) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } if (msg->flags != 0U) { // Remove Message - ptr = (void *)((uint8_t *)msg + sizeof(os_message_t)); - mq = *ptr; + //lint -e{9079} -e{9087} "cast between pointers to different object types" + mq = *((os_message_queue_t **)(void *)&msg[1]); if (mq->state == osRtxObjectInactive) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } MessageQueueRemove(mq, msg); // Free memory msg->state = osRtxObjectInactive; - osRtxMemoryPoolFree(&mq->mp_info, msg); + (void)osRtxMemoryPoolFree(&mq->mp_info, msg); // Check if Thread is waiting to send a Message if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) { // Try to allocate memory - msg = osRtxMemoryPoolAlloc(&mq->mp_info); - if (msg != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + msg0 = osRtxMemoryPoolAlloc(&mq->mp_info); + if (msg0 != NULL) { // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)mq); - osRtxThreadWaitExit(thread, (uint32_t)osOK, false); + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); // Copy Message (R2: const void *msg_ptr, R3: uint8_t msg_prio) reg = osRtxThreadRegPtr(thread); - memcpy((uint8_t *)msg + sizeof(os_message_t), (void *)reg[2], mq->msg_size); + //lint -e{923} "cast from unsigned int to pointer" + ptr_src = (const void *)reg[2]; + memcpy(&msg0[1], ptr_src, mq->msg_size); // Store Message into Queue - msg->id = osRtxIdMessage; - msg->state = osRtxObjectActive; - msg->flags = 0U; - msg->priority = (uint8_t)reg[3]; - MessageQueuePut(mq, msg); - EvrRtxMessageQueueInserted(mq, (void *)reg[2]); + msg0->id = osRtxIdMessage; + msg0->state = osRtxObjectActive; + msg0->flags = 0U; + msg0->priority = (uint8_t)reg[3]; + MessageQueuePut(mq, msg0); + EvrRtxMessageQueueInserted(mq, ptr_src); } } } else { // New Message + //lint -e{9079} -e{9087} "cast between pointers to different object types" mq = (void *)msg->next; if (mq->state == osRtxObjectInactive) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } + //lint -e{9087} "cast between pointers to different object types" + ptr_src = (const void *)msg->prev; // Check if Thread is waiting to receive a Message if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) { - EvrRtxMessageQueueInserted(mq, (void *)msg->prev); + EvrRtxMessageQueueInserted(mq, ptr_src); // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)mq); - osRtxThreadWaitExit(thread, (uint32_t)osOK, false); + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); // Copy Message (R2: void *msg_ptr, R3: uint8_t *msg_prio) reg = osRtxThreadRegPtr(thread); - memcpy((void *)reg[2], (uint8_t *)msg + sizeof(os_message_t), mq->msg_size); + //lint -e{923} "cast from unsigned int to pointer" + ptr_dst = (void *)reg[2]; + memcpy(ptr_dst, &msg[1], mq->msg_size); if (reg[3] != 0U) { + //lint -e{923} -e{9078} "cast from unsigned int to pointer" *((uint8_t *)reg[3]) = msg->priority; } - EvrRtxMessageQueueRetrieved(mq, (void *)reg[2]); + EvrRtxMessageQueueRetrieved(mq, ptr_dst); // Free memory msg->state = osRtxObjectInactive; - osRtxMemoryPoolFree(&mq->mp_info, msg); + (void)osRtxMemoryPoolFree(&mq->mp_info, msg); } else { - EvrRtxMessageQueueInserted(mq, (void *)msg->prev); + EvrRtxMessageQueueInserted(mq, ptr_src); MessageQueuePut(mq, msg); } } @@ -225,20 +247,9 @@ // ==== Service Calls ==== -SVC0_3M(MessageQueueNew, osMessageQueueId_t, uint32_t, uint32_t, const osMessageQueueAttr_t *) -SVC0_1 (MessageQueueGetName, const char *, osMessageQueueId_t) -SVC0_4 (MessageQueuePut, osStatus_t, osMessageQueueId_t, const void *, uint8_t, uint32_t) -SVC0_4 (MessageQueueGet, osStatus_t, osMessageQueueId_t, void *, uint8_t *, uint32_t) -SVC0_1 (MessageQueueGetCapacity, uint32_t, osMessageQueueId_t) -SVC0_1 (MessageQueueGetMsgSize, uint32_t, osMessageQueueId_t) -SVC0_1 (MessageQueueGetCount, uint32_t, osMessageQueueId_t) -SVC0_1 (MessageQueueGetSpace, uint32_t, osMessageQueueId_t) -SVC0_1 (MessageQueueReset, osStatus_t, osMessageQueueId_t) -SVC0_1 (MessageQueueDelete, osStatus_t, osMessageQueueId_t) - /// Create and Initialize a Message Queue object. /// \note API identical to osMessageQueueNew -osMessageQueueId_t svcRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { +static osMessageQueueId_t svcRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { os_message_queue_t *mq; void *mq_mem; uint32_t mq_size; @@ -249,12 +260,14 @@ // Check parameters if ((msg_count == 0U) || (msg_size == 0U)) { - EvrRtxMessageQueueError(NULL, osErrorParameter); + EvrRtxMessageQueueError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } block_size = ((msg_size + 3U) & ~3UL) + sizeof(os_message_t); - if ((__CLZ(msg_count) + __CLZ(block_size)) < 32) { - EvrRtxMessageQueueError(NULL, osErrorParameter); + if ((__CLZ(msg_count) + __CLZ(block_size)) < 32U) { + EvrRtxMessageQueueError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -263,28 +276,36 @@ // Process attributes if (attr != NULL) { name = attr->name; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] mq = attr->cb_mem; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] mq_mem = attr->mq_mem; mq_size = attr->mq_size; if (mq != NULL) { - if (((uint32_t)mq & 3U) || (attr->cb_size < sizeof(os_message_queue_t))) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)mq & 3U) != 0U) || (attr->cb_size < sizeof(os_message_queue_t))) { EvrRtxMessageQueueError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } else { if (attr->cb_size != 0U) { EvrRtxMessageQueueError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } if (mq_mem != NULL) { - if (((uint32_t)mq_mem & 3U) || (mq_size < size)) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)mq_mem & 3U) != 0U) || (mq_size < size)) { EvrRtxMessageQueueError(NULL, osRtxErrorInvalidDataMemory); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } else { if (mq_size != 0U) { EvrRtxMessageQueueError(NULL, osRtxErrorInvalidDataMemory); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } @@ -297,71 +318,89 @@ // Allocate object memory if not provided if (mq == NULL) { if (osRtxInfo.mpi.message_queue != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] mq = osRtxMemoryPoolAlloc(osRtxInfo.mpi.message_queue); } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] mq = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_message_queue_t), 1U); } - if (mq == NULL) { - EvrRtxMessageQueueError(NULL, osErrorNoMemory); - return NULL; +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (mq != NULL) { + uint32_t used; + osRtxMessageQueueMemUsage.cnt_alloc++; + used = osRtxMessageQueueMemUsage.cnt_alloc - osRtxMessageQueueMemUsage.cnt_free; + if (osRtxMessageQueueMemUsage.max_used < used) { + osRtxMessageQueueMemUsage.max_used = used; + } } +#endif flags = osRtxFlagSystemObject; } else { flags = 0U; } // Allocate data memory if not provided - if (mq_mem == NULL) { + if ((mq != NULL) && (mq_mem == NULL)) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] mq_mem = osRtxMemoryAlloc(osRtxInfo.mem.mq_data, size, 0U); if (mq_mem == NULL) { - EvrRtxMessageQueueError(NULL, osErrorNoMemory); - if (flags & osRtxFlagSystemObject) { + if ((flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.message_queue != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq); } else { - osRtxMemoryFree(osRtxInfo.mem.common, mq); + (void)osRtxMemoryFree(osRtxInfo.mem.common, mq); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxMessageQueueMemUsage.cnt_free++; +#endif } - return NULL; + mq = NULL; + } else { + memset(mq_mem, 0, size); } - memset(mq_mem, 0, size); flags |= osRtxFlagSystemMemory; } - // Initialize control block - mq->id = osRtxIdMessageQueue; - mq->state = osRtxObjectActive; - mq->flags = flags; - mq->name = name; - mq->thread_list = NULL; - mq->msg_size = msg_size; - mq->msg_count = 0U; - mq->msg_first = NULL; - mq->msg_last = NULL; - osRtxMemoryPoolInit(&mq->mp_info, msg_count, block_size, mq_mem); + if (mq != NULL) { + // Initialize control block + mq->id = osRtxIdMessageQueue; + mq->state = osRtxObjectActive; + mq->flags = flags; + mq->name = name; + mq->thread_list = NULL; + mq->msg_size = msg_size; + mq->msg_count = 0U; + mq->msg_first = NULL; + mq->msg_last = NULL; + (void)osRtxMemoryPoolInit(&mq->mp_info, msg_count, block_size, mq_mem); - // Register post ISR processing function - osRtxInfo.post_process.message_queue = osRtxMessageQueuePostProcess; + // Register post ISR processing function + osRtxInfo.post_process.message = osRtxMessageQueuePostProcess; - EvrRtxMessageQueueCreated(mq); + EvrRtxMessageQueueCreated(mq, mq->name); + } else { + EvrRtxMessageQueueError(NULL, (int32_t)osErrorNoMemory); + } return mq; } /// Get name of a Message Queue object. /// \note API identical to osMessageQueueGetName -const char *svcRtxMessageQueueGetName (osMessageQueueId_t mq_id) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; +static const char *svcRtxMessageQueueGetName (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { EvrRtxMessageQueueGetName(mq, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check object state if (mq->state == osRtxObjectInactive) { EvrRtxMessageQueueGetName(mq, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -372,21 +411,25 @@ /// Put a Message into a Queue or timeout if Queue is full. /// \note API identical to osMessageQueuePut -osStatus_t svcRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; +static osStatus_t svcRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); os_message_t *msg; os_thread_t *thread; uint32_t *reg; + void *ptr; + osStatus_t status; // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL)) { - EvrRtxMessageQueueError(mq, osErrorParameter); + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, osErrorResource); + EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -394,69 +437,83 @@ if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) { EvrRtxMessageQueueInserted(mq, msg_ptr); // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)mq); - osRtxThreadWaitExit(thread, (uint32_t)osOK, true); + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE); // Copy Message (R2: void *msg_ptr, R3: uint8_t *msg_prio) reg = osRtxThreadRegPtr(thread); - memcpy((void *)reg[2], msg_ptr, mq->msg_size); + //lint -e{923} "cast from unsigned int to pointer" + ptr = (void *)reg[2]; + memcpy(ptr, msg_ptr, mq->msg_size); if (reg[3] != 0U) { + //lint -e{923} -e{9078} "cast from unsigned int to pointer" *((uint8_t *)reg[3]) = msg_prio; } - EvrRtxMessageQueueRetrieved(mq, (void *)reg[2]); - return osOK; - } - - // Try to allocate memory - msg = osRtxMemoryPoolAlloc(&mq->mp_info); - if (msg != NULL) { - // Copy Message - memcpy((uint8_t *)msg + sizeof(os_message_t), msg_ptr, mq->msg_size); - // Put Message into Queue - msg->id = osRtxIdMessage; - msg->state = osRtxObjectActive; - msg->flags = 0U; - msg->priority = msg_prio; - MessageQueuePut(mq, msg); + EvrRtxMessageQueueRetrieved(mq, ptr); + status = osOK; } else { - // No memory available - if (timeout != 0U) { - EvrRtxMessageQueuePutPending(mq, msg_ptr, timeout); - // Suspend current Thread - osRtxThreadListPut((os_object_t*)mq, osRtxThreadGetRunning()); - osRtxThreadWaitEnter(osRtxThreadWaitingMessagePut, timeout); - // Save arguments (R2: const void *msg_ptr, R3: uint8_t msg_prio) - reg = (uint32_t *)(__get_PSP()); - reg[2] = (uint32_t)msg_ptr; - reg[3] = (uint32_t)msg_prio; - return osErrorTimeout; + // Try to allocate memory + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + msg = osRtxMemoryPoolAlloc(&mq->mp_info); + if (msg != NULL) { + // Copy Message + memcpy(&msg[1], msg_ptr, mq->msg_size); + // Put Message into Queue + msg->id = osRtxIdMessage; + msg->state = osRtxObjectActive; + msg->flags = 0U; + msg->priority = msg_prio; + MessageQueuePut(mq, msg); + EvrRtxMessageQueueInserted(mq, msg_ptr); + status = osOK; } else { - EvrRtxMessageQueueNotInserted(mq, msg_ptr); - return osErrorResource; + // No memory available + if (timeout != 0U) { + EvrRtxMessageQueuePutPending(mq, msg_ptr, timeout); + // Suspend current Thread + if (osRtxThreadWaitEnter(osRtxThreadWaitingMessagePut, timeout)) { + osRtxThreadListPut(osRtxObject(mq), osRtxThreadGetRunning()); + // Save arguments (R2: const void *msg_ptr, R3: uint8_t msg_prio) + //lint -e{923} -e{9078} "cast from unsigned int to pointer" + reg = (uint32_t *)(__get_PSP()); + //lint -e{923} -e{9078} "cast from pointer to unsigned int" + reg[2] = (uint32_t)msg_ptr; + //lint -e{923} -e{9078} "cast from pointer to unsigned int" + reg[3] = (uint32_t)msg_prio; + } else { + EvrRtxMessageQueuePutTimeout(mq); + } + status = osErrorTimeout; + } else { + EvrRtxMessageQueueNotInserted(mq, msg_ptr); + status = osErrorResource; + } } } - EvrRtxMessageQueueInserted(mq, msg_ptr); - - return osOK; + return status; } /// Get a Message from a Queue or timeout if Queue is empty. /// \note API identical to osMessageQueueGet -osStatus_t svcRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; +static osStatus_t svcRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); os_message_t *msg; os_thread_t *thread; uint32_t *reg; + const void *ptr; + osStatus_t status; // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL)) { - EvrRtxMessageQueueError(mq, osErrorParameter); + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, osErrorResource); + EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -465,70 +522,81 @@ if (msg != NULL) { MessageQueueRemove(mq, msg); // Copy Message - memcpy(msg_ptr, (uint8_t *)msg + sizeof(os_message_t), mq->msg_size); + memcpy(msg_ptr, &msg[1], mq->msg_size); if (msg_prio != NULL) { *msg_prio = msg->priority; } EvrRtxMessageQueueRetrieved(mq, msg_ptr); // Free memory msg->state = osRtxObjectInactive; - osRtxMemoryPoolFree(&mq->mp_info, msg); + (void)osRtxMemoryPoolFree(&mq->mp_info, msg); + // Check if Thread is waiting to send a Message + if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) { + // Try to allocate memory + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + msg = osRtxMemoryPoolAlloc(&mq->mp_info); + if (msg != NULL) { + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE); + // Copy Message (R2: const void *msg_ptr, R3: uint8_t msg_prio) + reg = osRtxThreadRegPtr(thread); + //lint -e{923} "cast from unsigned int to pointer" + ptr = (const void *)reg[2]; + memcpy(&msg[1], ptr, mq->msg_size); + // Store Message into Queue + msg->id = osRtxIdMessage; + msg->state = osRtxObjectActive; + msg->flags = 0U; + msg->priority = (uint8_t)reg[3]; + MessageQueuePut(mq, msg); + EvrRtxMessageQueueInserted(mq, ptr); + } + } + status = osOK; } else { // No Message available if (timeout != 0U) { EvrRtxMessageQueueGetPending(mq, msg_ptr, timeout); // Suspend current Thread - osRtxThreadListPut((os_object_t*)mq, osRtxThreadGetRunning()); - osRtxThreadWaitEnter(osRtxThreadWaitingMessageGet, timeout); - // Save arguments (R2: void *msg_ptr, R3: uint8_t *msg_prio) - reg = (uint32_t *)(__get_PSP()); - reg[2] = (uint32_t)msg_ptr; - reg[3] = (uint32_t)msg_prio; - return osErrorTimeout; + if (osRtxThreadWaitEnter(osRtxThreadWaitingMessageGet, timeout)) { + osRtxThreadListPut(osRtxObject(mq), osRtxThreadGetRunning()); + // Save arguments (R2: void *msg_ptr, R3: uint8_t *msg_prio) + //lint -e{923} -e{9078} "cast from unsigned int to pointer" + reg = (uint32_t *)(__get_PSP()); + //lint -e{923} -e{9078} "cast from pointer to unsigned int" + reg[2] = (uint32_t)msg_ptr; + //lint -e{923} -e{9078} "cast from pointer to unsigned int" + reg[3] = (uint32_t)msg_prio; + } else { + EvrRtxMessageQueueGetTimeout(mq); + } + status = osErrorTimeout; } else { EvrRtxMessageQueueNotRetrieved(mq, msg_ptr); - return osErrorResource; + status = osErrorResource; } } - // Check if Thread is waiting to send a Message - if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) { - // Try to allocate memory - msg = osRtxMemoryPoolAlloc(&mq->mp_info); - if (msg != NULL) { - // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)mq); - osRtxThreadWaitExit(thread, (uint32_t)osOK, true); - // Copy Message (R2: const void *msg_ptr, R3: uint8_t msg_prio) - reg = osRtxThreadRegPtr(thread); - memcpy((uint8_t *)msg + sizeof(os_message_t), (void *)reg[2], mq->msg_size); - // Store Message into Queue - msg->id = osRtxIdMessage; - msg->state = osRtxObjectActive; - msg->flags = 0U; - msg->priority = (uint8_t)reg[3]; - MessageQueuePut(mq, msg); - EvrRtxMessageQueueInserted(mq, (void *)reg[2]); - } - } - - return osOK; + return status; } /// Get maximum number of messages in a Message Queue. /// \note API identical to osMessageGetCapacity -uint32_t svcRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; +static uint32_t svcRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { EvrRtxMessageQueueGetCapacity(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (mq->state == osRtxObjectInactive) { EvrRtxMessageQueueGetCapacity(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -539,18 +607,20 @@ /// Get maximum message size in a Memory Pool. /// \note API identical to osMessageGetMsgSize -uint32_t svcRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; +static uint32_t svcRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { EvrRtxMessageQueueGetMsgSize(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (mq->state == osRtxObjectInactive) { EvrRtxMessageQueueGetMsgSize(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -561,18 +631,20 @@ /// Get number of queued messages in a Message Queue. /// \note API identical to osMessageGetCount -uint32_t svcRtxMessageQueueGetCount (osMessageQueueId_t mq_id) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; +static uint32_t svcRtxMessageQueueGetCount (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { EvrRtxMessageQueueGetCount(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (mq->state == osRtxObjectInactive) { EvrRtxMessageQueueGetCount(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -583,18 +655,20 @@ /// Get number of available slots for messages in a Message Queue. /// \note API identical to osMessageGetSpace -uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_id) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; +static uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { EvrRtxMessageQueueGetSpace(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (mq->state == osRtxObjectInactive) { EvrRtxMessageQueueGetSpace(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -605,21 +679,24 @@ /// Reset a Message Queue to initial empty state. /// \note API identical to osMessageQueueReset -osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; +static osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); os_message_t *msg; os_thread_t *thread; - uint32_t *reg; + const uint32_t *reg; + const void *ptr; // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { - EvrRtxMessageQueueError(mq, osErrorParameter); + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, osErrorResource); + EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -634,28 +711,31 @@ EvrRtxMessageQueueRetrieved(mq, NULL); // Free memory msg->state = osRtxObjectInactive; - osRtxMemoryPoolFree(&mq->mp_info, msg); + (void)osRtxMemoryPoolFree(&mq->mp_info, msg); } // Check if Threads are waiting to send Messages if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) { do { // Try to allocate memory + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] msg = osRtxMemoryPoolAlloc(&mq->mp_info); if (msg != NULL) { // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)mq); - osRtxThreadWaitExit(thread, (uint32_t)osOK, false); + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); // Copy Message (R2: const void *msg_ptr, R3: uint8_t msg_prio) reg = osRtxThreadRegPtr(thread); - memcpy((uint8_t *)msg + sizeof(os_message_t), (void *)reg[2], mq->msg_size); + //lint -e{923} "cast from unsigned int to pointer" + ptr = (const void *)reg[2]; + memcpy(&msg[1], ptr, mq->msg_size); // Store Message into Queue msg->id = osRtxIdMessage; msg->state = osRtxObjectActive; msg->flags = 0U; msg->priority = (uint8_t)reg[3]; MessageQueuePut(mq, msg); - EvrRtxMessageQueueInserted(mq, (void *)reg[2]); + EvrRtxMessageQueueInserted(mq, ptr); } } while ((msg != NULL) && (mq->thread_list != NULL)); osRtxThreadDispatch(NULL); @@ -668,19 +748,21 @@ /// Delete a Message Queue object. /// \note API identical to osMessageQueueDelete -osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; +static osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); os_thread_t *thread; // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { - EvrRtxMessageQueueError(mq, osErrorParameter); + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, osErrorResource); + EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -690,24 +772,27 @@ // Unblock waiting threads if (mq->thread_list != NULL) { do { - thread = osRtxThreadListGet((os_object_t*)mq); - osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, false); + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE); } while (mq->thread_list != NULL); osRtxThreadDispatch(NULL); } // Free data memory - if (mq->flags & osRtxFlagSystemMemory) { - osRtxMemoryFree(osRtxInfo.mem.mq_data, mq->mp_info.block_base); + if ((mq->flags & osRtxFlagSystemMemory) != 0U) { + (void)osRtxMemoryFree(osRtxInfo.mem.mq_data, mq->mp_info.block_base); } // Free object memory - if (mq->flags & osRtxFlagSystemObject) { + if ((mq->flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.message_queue != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq); } else { - osRtxMemoryFree(osRtxInfo.mem.common, mq); + (void)osRtxMemoryFree(osRtxInfo.mem.common, mq); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxMessageQueueMemUsage.cnt_free++; +#endif } EvrRtxMessageQueueDestroyed(mq); @@ -715,6 +800,20 @@ return osOK; } +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_3(MessageQueueNew, osMessageQueueId_t, uint32_t, uint32_t, const osMessageQueueAttr_t *) +SVC0_1(MessageQueueGetName, const char *, osMessageQueueId_t) +SVC0_4(MessageQueuePut, osStatus_t, osMessageQueueId_t, const void *, uint8_t, uint32_t) +SVC0_4(MessageQueueGet, osStatus_t, osMessageQueueId_t, void *, uint8_t *, uint32_t) +SVC0_1(MessageQueueGetCapacity, uint32_t, osMessageQueueId_t) +SVC0_1(MessageQueueGetMsgSize, uint32_t, osMessageQueueId_t) +SVC0_1(MessageQueueGetCount, uint32_t, osMessageQueueId_t) +SVC0_1(MessageQueueGetSpace, uint32_t, osMessageQueueId_t) +SVC0_1(MessageQueueReset, osStatus_t, osMessageQueueId_t) +SVC0_1(MessageQueueDelete, osStatus_t, osMessageQueueId_t) +//lint --flb "Library End" + // ==== ISR Calls ==== @@ -722,65 +821,70 @@ /// \note API identical to osMessageQueuePut __STATIC_INLINE osStatus_t isrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); os_message_t *msg; - const void **ptr; + osStatus_t status; // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL) || (timeout != 0U)) { - EvrRtxMessageQueueError(mq, osErrorParameter); + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, osErrorResource); + EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } // Try to allocate memory + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] msg = osRtxMemoryPoolAlloc(&mq->mp_info); if (msg != NULL) { // Copy Message - memcpy((uint8_t *)msg + sizeof(os_message_t), msg_ptr, mq->msg_size); + memcpy(&msg[1], msg_ptr, mq->msg_size); msg->id = osRtxIdMessage; msg->state = osRtxObjectActive; msg->flags = 0U; msg->priority = msg_prio; // Register post ISR processing - ptr = (void *)&msg->prev; - *ptr = msg_ptr; - ptr = (void *)&msg->next; - *ptr = mq; - osRtxPostProcess((os_object_t *)msg); + //lint -e{9079} -e{9087} "cast between pointers to different object types" + *((const void **)(void *)&msg->prev) = msg_ptr; + //lint -e{9079} -e{9087} "cast between pointers to different object types" + *( (void **) &msg->next) = mq; + osRtxPostProcess(osRtxObject(msg)); + EvrRtxMessageQueueInsertPending(mq, msg_ptr); + status = osOK; } else { // No memory available EvrRtxMessageQueueNotInserted(mq, msg_ptr); - return osErrorResource; + status = osErrorResource; } - EvrRtxMessageQueueInsertPending(mq, msg_ptr); - - return osOK; + return status; } /// Get a Message from a Queue or timeout if Queue is empty. /// \note API identical to osMessageQueueGet __STATIC_INLINE osStatus_t isrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { - os_message_queue_t *mq = (os_message_queue_t *)mq_id; + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); os_message_t *msg; - void **ptr; + osStatus_t status; // Check parameters if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL) || (timeout != 0U)) { - EvrRtxMessageQueueError(mq, osErrorParameter); + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, osErrorResource); + EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -788,22 +892,23 @@ msg = MessageQueueGet(mq); if (msg != NULL) { // Copy Message - memcpy(msg_ptr, (uint8_t *)msg + sizeof(os_message_t), mq->msg_size); + memcpy(msg_ptr, &msg[1], mq->msg_size); if (msg_prio != NULL) { *msg_prio = msg->priority; } - EvrRtxMessageQueueRetrieved(mq, msg_ptr); // Register post ISR processing - ptr = (void *)((uint8_t *)msg + sizeof(os_message_t)); - *ptr = mq; - osRtxPostProcess((os_object_t *)msg); + //lint -e{9079} -e{9087} "cast between pointers to different object types" + *((os_message_queue_t **)(void *)&msg[1]) = mq; + osRtxPostProcess(osRtxObject(msg)); + EvrRtxMessageQueueRetrieved(mq, msg_ptr); + status = osOK; } else { // No Message available EvrRtxMessageQueueNotRetrieved(mq, msg_ptr); - return osErrorResource; + status = osErrorResource; } - return osOK; + return status; } @@ -811,95 +916,129 @@ /// Create and Initialize a Message Queue object. osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { + osMessageQueueId_t mq_id; + EvrRtxMessageQueueNew(msg_count, msg_size, attr); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxMessageQueueError(NULL, osErrorISR); - return NULL; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMessageQueueError(NULL, (int32_t)osErrorISR); + mq_id = NULL; + } else { + mq_id = __svcMessageQueueNew(msg_count, msg_size, attr); } - return __svcMessageQueueNew(msg_count, msg_size, attr); + return mq_id; } /// Get name of a Message Queue object. const char *osMessageQueueGetName (osMessageQueueId_t mq_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxMessageQueueGetName(mq_id, NULL); - return NULL; + name = NULL; + } else { + name = __svcMessageQueueGetName(mq_id); } - return __svcMessageQueueGetName(mq_id); + return name; } /// Put a Message into a Queue or timeout if Queue is full. osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + osStatus_t status; + EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return isrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout); + if (IsIrqMode() || IsIrqMasked()) { + status = isrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout); } else { - return __svcMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout); + status = __svcMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout); } + return status; } /// Get a Message from a Queue or timeout if Queue is empty. osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + osStatus_t status; + EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return isrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout); + if (IsIrqMode() || IsIrqMasked()) { + status = isrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout); } else { - return __svcMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout); + status = __svcMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout); } + return status; } /// Get maximum number of messages in a Message Queue. uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxMessageQueueGetCapacity(mq_id); + uint32_t capacity; + + if (IsIrqMode() || IsIrqMasked()) { + capacity = svcRtxMessageQueueGetCapacity(mq_id); } else { - return __svcMessageQueueGetCapacity(mq_id); + capacity = __svcMessageQueueGetCapacity(mq_id); } + return capacity; } /// Get maximum message size in a Memory Pool. uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxMessageQueueGetMsgSize(mq_id); + uint32_t msg_size; + + if (IsIrqMode() || IsIrqMasked()) { + msg_size = svcRtxMessageQueueGetMsgSize(mq_id); } else { - return __svcMessageQueueGetMsgSize(mq_id); + msg_size = __svcMessageQueueGetMsgSize(mq_id); } + return msg_size; } /// Get number of queued messages in a Message Queue. uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxMessageQueueGetCount(mq_id); + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + count = svcRtxMessageQueueGetCount(mq_id); } else { - return __svcMessageQueueGetCount(mq_id); + count = __svcMessageQueueGetCount(mq_id); } + return count; } /// Get number of available slots for messages in a Message Queue. uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxMessageQueueGetSpace(mq_id); + uint32_t space; + + if (IsIrqMode() || IsIrqMasked()) { + space = svcRtxMessageQueueGetSpace(mq_id); } else { - return __svcMessageQueueGetSpace(mq_id); + space = __svcMessageQueueGetSpace(mq_id); } + return space; } /// Reset a Message Queue to initial empty state. osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) { + osStatus_t status; + EvrRtxMessageQueueReset(mq_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxMessageQueueError(mq_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMessageQueueError(mq_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMessageQueueReset(mq_id); } - return __svcMessageQueueReset(mq_id); + return status; } /// Delete a Message Queue object. osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) { + osStatus_t status; + EvrRtxMessageQueueDelete(mq_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxMessageQueueError(mq_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMessageQueueError(mq_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMessageQueueDelete(mq_id); } - return __svcMessageQueueDelete(mq_id); + return status; } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c index 2151c02..609d4f4 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,6 +26,14 @@ #include "rtx_lib.h" +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxMutexMemUsage \ +__attribute__((section(".data.os.mutex.obj"))) = +{ 0U, 0U, 0U }; +#endif + + // ==== Library functions ==== /// Release Mutex list when owner Thread terminates. @@ -33,21 +41,22 @@ /// \return 1 - success, 0 - failure. void osRtxMutexOwnerRelease (os_mutex_t *mutex_list) { os_mutex_t *mutex; + os_mutex_t *mutex_next; os_thread_t *thread; mutex = mutex_list; - while (mutex) { - mutex_list = mutex->owner_next; + while (mutex != NULL) { + mutex_next = mutex->owner_next; // Check if Mutex is Robust - if (mutex->attr & osMutexRobust) { + if ((mutex->attr & osMutexRobust) != 0U) { // Clear Lock counter mutex->lock = 0U; EvrRtxMutexReleased(mutex, 0U); // Check if Thread is waiting for a Mutex if (mutex->thread_list != NULL) { // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)mutex); - osRtxThreadWaitExit(thread, (uint32_t)osOK, false); + thread = osRtxThreadListGet(osRtxObject(mutex)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); // Thread is the new Mutex owner mutex->owner_thread = thread; mutex->owner_next = thread->mutex_list; @@ -57,24 +66,16 @@ EvrRtxMutexAcquired(mutex, 1U); } } - mutex = mutex_list; + mutex = mutex_next; } } // ==== Service Calls ==== -// Service Calls definitions -SVC0_1M(MutexNew, osMutexId_t, const osMutexAttr_t *) -SVC0_1 (MutexGetName, const char *, osMutexId_t) -SVC0_2 (MutexAcquire, osStatus_t, osMutexId_t, uint32_t) -SVC0_1 (MutexRelease, osStatus_t, osMutexId_t) -SVC0_1 (MutexGetOwner, osThreadId_t, osMutexId_t) -SVC0_1 (MutexDelete, osStatus_t, osMutexId_t) - /// Create and Initialize a Mutex object. /// \note API identical to osMutexNew -osMutexId_t svcRtxMutexNew (const osMutexAttr_t *attr) { +static osMutexId_t svcRtxMutexNew (const osMutexAttr_t *attr) { os_mutex_t *mutex; uint32_t attr_bits; uint8_t flags; @@ -84,15 +85,19 @@ if (attr != NULL) { name = attr->name; attr_bits = attr->attr_bits; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] mutex = attr->cb_mem; if (mutex != NULL) { - if (((uint32_t)mutex & 3U) || (attr->cb_size < sizeof(os_mutex_t))) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)mutex & 3U) != 0U) || (attr->cb_size < sizeof(os_mutex_t))) { EvrRtxMutexError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } else { if (attr->cb_size != 0U) { EvrRtxMutexError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } @@ -105,50 +110,64 @@ // Allocate object memory if not provided if (mutex == NULL) { if (osRtxInfo.mpi.mutex != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] mutex = osRtxMemoryPoolAlloc(osRtxInfo.mpi.mutex); } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] mutex = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_mutex_t), 1U); } - if (mutex == NULL) { - EvrRtxMutexError(NULL, osErrorNoMemory); - return NULL; +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (mutex != NULL) { + uint32_t used; + osRtxMutexMemUsage.cnt_alloc++; + used = osRtxMutexMemUsage.cnt_alloc - osRtxMutexMemUsage.cnt_free; + if (osRtxMutexMemUsage.max_used < used) { + osRtxMutexMemUsage.max_used = used; + } } +#endif flags = osRtxFlagSystemObject; } else { flags = 0U; } - // Initialize control block - mutex->id = osRtxIdMutex; - mutex->state = osRtxObjectActive; - mutex->flags = flags; - mutex->attr = (uint8_t)attr_bits; - mutex->name = name; - mutex->thread_list = NULL; - mutex->owner_thread = NULL; - mutex->owner_prev = NULL; - mutex->owner_next = NULL; - mutex->lock = 0U; + if (mutex != NULL) { + // Initialize control block + mutex->id = osRtxIdMutex; + mutex->state = osRtxObjectActive; + mutex->flags = flags; + mutex->attr = (uint8_t)attr_bits; + mutex->name = name; + mutex->thread_list = NULL; + mutex->owner_thread = NULL; + mutex->owner_prev = NULL; + mutex->owner_next = NULL; + mutex->lock = 0U; - EvrRtxMutexCreated(mutex); + EvrRtxMutexCreated(mutex, mutex->name); + } else { + EvrRtxMutexError(NULL, (int32_t)osErrorNoMemory); + } return mutex; } /// Get name of a Mutex object. /// \note API identical to osMutexGetName -const char *svcRtxMutexGetName (osMutexId_t mutex_id) { - os_mutex_t *mutex = (os_mutex_t *)mutex_id; +static const char *svcRtxMutexGetName (osMutexId_t mutex_id) { + os_mutex_t *mutex = osRtxMutexId(mutex_id); // Check parameters if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) { EvrRtxMutexGetName(mutex, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check object state if (mutex->state == osRtxObjectInactive) { EvrRtxMutexGetName(mutex, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -159,25 +178,30 @@ /// Acquire a Mutex or timeout if it is locked. /// \note API identical to osMutexAcquire -osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { - os_mutex_t *mutex = (os_mutex_t *)mutex_id; +static osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { + os_mutex_t *mutex = osRtxMutexId(mutex_id); os_thread_t *runnig_thread; + osStatus_t status; + // Check running thread runnig_thread = osRtxThreadGetRunning(); if (runnig_thread == NULL) { EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osError; } // Check parameters if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) { - EvrRtxMutexError(mutex, osErrorParameter); + EvrRtxMutexError(mutex, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mutex->state == osRtxObjectInactive) { - EvrRtxMutexError(mutex, osErrorResource); + EvrRtxMutexError(mutex, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -193,80 +217,90 @@ runnig_thread->mutex_list = mutex; mutex->lock = 1U; EvrRtxMutexAcquired(mutex, mutex->lock); - return osOK; - } - - // Check if Mutex is recursive and running Thread is the owner - if ((mutex->attr & osMutexRecursive) && (mutex->owner_thread == runnig_thread)) { - // Increment lock counter - if (mutex->lock == osRtxMutexLockLimit) { - EvrRtxMutexError(mutex, osRtxErrorMutexLockLimit); - return osErrorResource; - } - mutex->lock++; - EvrRtxMutexAcquired(mutex, mutex->lock); - return osOK; - } - - // Check if timeout is specified - if (timeout != 0U) { - // Check if Priority inheritance protocol is enabled - if (mutex->attr & osMutexPrioInherit) { - // Raise priority of owner Thread if lower than priority of running Thread - if (mutex->owner_thread->priority < runnig_thread->priority) { - mutex->owner_thread->priority = runnig_thread->priority; - osRtxThreadListSort(mutex->owner_thread); + status = osOK; + } else { + // Check if Mutex is recursive and running Thread is the owner + if (((mutex->attr & osMutexRecursive) != 0U) && (mutex->owner_thread == runnig_thread)) { + // Try to increment lock counter + if (mutex->lock == osRtxMutexLockLimit) { + EvrRtxMutexError(mutex, osRtxErrorMutexLockLimit); + status = osErrorResource; + } else { + mutex->lock++; + EvrRtxMutexAcquired(mutex, mutex->lock); + status = osOK; + } + } else { + // Check if timeout is specified + if (timeout != 0U) { + // Check if Priority inheritance protocol is enabled + if ((mutex->attr & osMutexPrioInherit) != 0U) { + // Raise priority of owner Thread if lower than priority of running Thread + if (mutex->owner_thread->priority < runnig_thread->priority) { + mutex->owner_thread->priority = runnig_thread->priority; + osRtxThreadListSort(mutex->owner_thread); + } + } + EvrRtxMutexAcquirePending(mutex, timeout); + // Suspend current Thread + if (osRtxThreadWaitEnter(osRtxThreadWaitingMutex, timeout)) { + osRtxThreadListPut(osRtxObject(mutex), runnig_thread); + } else { + EvrRtxMutexAcquireTimeout(mutex); + } + status = osErrorTimeout; + } else { + EvrRtxMutexNotAcquired(mutex); + status = osErrorResource; } } - EvrRtxMutexAcquirePending(mutex, timeout); - // Suspend current Thread - osRtxThreadListPut((os_object_t*)mutex, runnig_thread); - osRtxThreadWaitEnter(osRtxThreadWaitingMutex, timeout); - return osErrorTimeout; } - // Mutex was not acquired - EvrRtxMutexNotAcquired(mutex); - - return osErrorResource; + return status; } /// Release a Mutex that was acquired by osMutexAcquire. /// \note API identical to osMutexRelease -osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) { - os_mutex_t *mutex = (os_mutex_t *)mutex_id; - os_mutex_t *mutex0; - os_thread_t *thread; - os_thread_t *runnig_thread; - int8_t priority; +static osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) { + os_mutex_t *mutex = osRtxMutexId(mutex_id); + const os_mutex_t *mutex0; + os_thread_t *thread; + os_thread_t *runnig_thread; + int8_t priority; + // Check running thread runnig_thread = osRtxThreadGetRunning(); if (runnig_thread == NULL) { EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osError; } // Check parameters if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) { - EvrRtxMutexError(mutex, osErrorParameter); + EvrRtxMutexError(mutex, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mutex->state == osRtxObjectInactive) { - EvrRtxMutexError(mutex, osErrorResource); + EvrRtxMutexError(mutex, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } // Check if running Thread is not the owner if (mutex->owner_thread != runnig_thread) { EvrRtxMutexError(mutex, osRtxErrorMutexNotOwned); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } // Check if Mutex is not locked if (mutex->lock == 0U) { EvrRtxMutexError(mutex, osRtxErrorMutexNotLocked); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -275,74 +309,76 @@ EvrRtxMutexReleased(mutex, mutex->lock); // Check Lock counter - if (mutex->lock != 0U) { - return osOK; - } + if (mutex->lock == 0U) { - // Remove Mutex from Thread owner list - if (mutex->owner_next != NULL) { - mutex->owner_next->owner_prev = mutex->owner_prev; - } - if (mutex->owner_prev != NULL) { - mutex->owner_prev->owner_next = mutex->owner_next; - } else { - runnig_thread->mutex_list = mutex->owner_next; - } - - // Restore running Thread priority - if (mutex->attr & osMutexPrioInherit) { - priority = runnig_thread->priority_base; - mutex0 = runnig_thread->mutex_list; - while (mutex0) { - // Mutexes owned by running Thread - if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) { - // Higher priority Thread is waiting for Mutex - priority = mutex0->thread_list->priority; - } - mutex0 = mutex0->owner_next; + // Remove Mutex from Thread owner list + if (mutex->owner_next != NULL) { + mutex->owner_next->owner_prev = mutex->owner_prev; } - runnig_thread->priority = priority; - } + if (mutex->owner_prev != NULL) { + mutex->owner_prev->owner_next = mutex->owner_next; + } else { + runnig_thread->mutex_list = mutex->owner_next; + } - // Check if Thread is waiting for a Mutex - if (mutex->thread_list != NULL) { - // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)mutex); - osRtxThreadWaitExit(thread, (uint32_t)osOK, false); - // Thread is the new Mutex owner - mutex->owner_thread = thread; - mutex->owner_next = thread->mutex_list; - mutex->owner_prev = NULL; - thread->mutex_list = mutex; - mutex->lock = 1U; - EvrRtxMutexAcquired(mutex, 1U); - } + // Restore running Thread priority + if ((mutex->attr & osMutexPrioInherit) != 0U) { + priority = runnig_thread->priority_base; + mutex0 = runnig_thread->mutex_list; + while (mutex0 != NULL) { + // Mutexes owned by running Thread + if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) { + // Higher priority Thread is waiting for Mutex + priority = mutex0->thread_list->priority; + } + mutex0 = mutex0->owner_next; + } + runnig_thread->priority = priority; + } - osRtxThreadDispatch(NULL); + // Check if Thread is waiting for a Mutex + if (mutex->thread_list != NULL) { + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mutex)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); + // Thread is the new Mutex owner + mutex->owner_thread = thread; + mutex->owner_next = thread->mutex_list; + mutex->owner_prev = NULL; + thread->mutex_list = mutex; + mutex->lock = 1U; + EvrRtxMutexAcquired(mutex, 1U); + } + + osRtxThreadDispatch(NULL); + } return osOK; } /// Get Thread which owns a Mutex object. /// \note API identical to osMutexGetOwner -osThreadId_t svcRtxMutexGetOwner (osMutexId_t mutex_id) { - os_mutex_t *mutex = (os_mutex_t *)mutex_id; +static osThreadId_t svcRtxMutexGetOwner (osMutexId_t mutex_id) { + os_mutex_t *mutex = osRtxMutexId(mutex_id); // Check parameters if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) { EvrRtxMutexGetOwner(mutex, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check object state if (mutex->state == osRtxObjectInactive) { EvrRtxMutexGetOwner(mutex, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check if Mutex is not locked if (mutex->lock == 0U) { EvrRtxMutexGetOwner(mutex, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -353,21 +389,23 @@ /// Delete a Mutex object. /// \note API identical to osMutexDelete -osStatus_t svcRtxMutexDelete (osMutexId_t mutex_id) { - os_mutex_t *mutex = (os_mutex_t *)mutex_id; - os_mutex_t *mutex0; - os_thread_t *thread; - int8_t priority; +static osStatus_t svcRtxMutexDelete (osMutexId_t mutex_id) { + os_mutex_t *mutex = osRtxMutexId(mutex_id); + const os_mutex_t *mutex0; + os_thread_t *thread; + int8_t priority; // Check parameters if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) { - EvrRtxMutexError(mutex, osErrorParameter); + EvrRtxMutexError(mutex, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (mutex->state == osRtxObjectInactive) { - EvrRtxMutexError(mutex, osErrorResource); + EvrRtxMutexError(mutex, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -390,10 +428,10 @@ } // Restore owner Thread priority - if (mutex->attr & osMutexPrioInherit) { + if ((mutex->attr & osMutexPrioInherit) != 0U) { priority = thread->priority_base; mutex0 = thread->mutex_list; - while (mutex0) { + while (mutex0 != NULL) { // Mutexes owned by running Thread if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) { // Higher priority Thread is waiting for Mutex @@ -410,8 +448,8 @@ // Unblock waiting threads if (mutex->thread_list != NULL) { do { - thread = osRtxThreadListGet((os_object_t*)mutex); - osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, false); + thread = osRtxThreadListGet(osRtxObject(mutex)); + osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE); } while (mutex->thread_list != NULL); } @@ -419,12 +457,15 @@ } // Free object memory - if (mutex->flags & osRtxFlagSystemObject) { + if ((mutex->flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.mutex != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.mutex, mutex); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.mutex, mutex); } else { - osRtxMemoryFree(osRtxInfo.mem.common, mutex); + (void)osRtxMemoryFree(osRtxInfo.mem.common, mutex); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxMutexMemUsage.cnt_free++; +#endif } EvrRtxMutexDestroyed(mutex); @@ -432,63 +473,97 @@ return osOK; } +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_1(MutexNew, osMutexId_t, const osMutexAttr_t *) +SVC0_1(MutexGetName, const char *, osMutexId_t) +SVC0_2(MutexAcquire, osStatus_t, osMutexId_t, uint32_t) +SVC0_1(MutexRelease, osStatus_t, osMutexId_t) +SVC0_1(MutexGetOwner, osThreadId_t, osMutexId_t) +SVC0_1(MutexDelete, osStatus_t, osMutexId_t) +//lint --flb "Library End" + // ==== Public API ==== /// Create and Initialize a Mutex object. osMutexId_t osMutexNew (const osMutexAttr_t *attr) { + osMutexId_t mutex_id; + EvrRtxMutexNew(attr); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxMutexError(NULL, osErrorISR); - return NULL; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMutexError(NULL, (int32_t)osErrorISR); + mutex_id = NULL; + } else { + mutex_id = __svcMutexNew(attr); } - return __svcMutexNew(attr); + return mutex_id; } /// Get name of a Mutex object. const char *osMutexGetName (osMutexId_t mutex_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxMutexGetName(mutex_id, NULL); - return NULL; + name = NULL; + } else { + name = __svcMutexGetName(mutex_id); } - return __svcMutexGetName(mutex_id); + return name; } /// Acquire a Mutex or timeout if it is locked. osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { + osStatus_t status; + EvrRtxMutexAcquire(mutex_id, timeout); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxMutexError(mutex_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMutexError(mutex_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMutexAcquire(mutex_id, timeout); } - return __svcMutexAcquire(mutex_id, timeout); + return status; } /// Release a Mutex that was acquired by \ref osMutexAcquire. osStatus_t osMutexRelease (osMutexId_t mutex_id) { + osStatus_t status; + EvrRtxMutexRelease(mutex_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxMutexError(mutex_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMutexError(mutex_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMutexRelease(mutex_id); } - return __svcMutexRelease(mutex_id); + return status; } /// Get Thread which owns a Mutex object. osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + osThreadId_t thread; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxMutexGetOwner(mutex_id, NULL); - return NULL; + thread = NULL; + } else { + thread = __svcMutexGetOwner(mutex_id); } - return __svcMutexGetOwner(mutex_id); + return thread; } /// Delete a Mutex object. osStatus_t osMutexDelete (osMutexId_t mutex_id) { + osStatus_t status; + EvrRtxMutexDelete(mutex_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxMutexError(mutex_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMutexError(mutex_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMutexDelete(mutex_id); } - return __svcMutexDelete(mutex_id); + return status; } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_semaphore.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_semaphore.c index f0a3c40..a1f8d4c 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_semaphore.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_semaphore.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,18 +26,26 @@ #include "rtx_lib.h" +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxSemaphoreMemUsage \ +__attribute__((section(".data.os.semaphore.obj"))) = +{ 0U, 0U, 0U }; +#endif + + // ==== Helper functions ==== /// Decrement Semaphore tokens. /// \param[in] semaphore semaphore object. /// \return 1 - success, 0 - failure. static uint32_t SemaphoreTokenDecrement (os_semaphore_t *semaphore) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif uint32_t ret; -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); if (semaphore->tokens != 0U) { @@ -65,12 +73,12 @@ /// \param[in] semaphore semaphore object. /// \return 1 - success, 0 - failure. static uint32_t SemaphoreTokenIncrement (os_semaphore_t *semaphore) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif uint32_t ret; -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); if (semaphore->tokens < semaphore->max_tokens) { @@ -95,14 +103,15 @@ } -// ==== Library functions ==== +// ==== Post ISR processing ==== /// Semaphore post ISR processing. /// \param[in] semaphore semaphore object. -void osRtxSemaphorePostProcess (os_semaphore_t *semaphore) { +static void osRtxSemaphorePostProcess (os_semaphore_t *semaphore) { os_thread_t *thread; if (semaphore->state == osRtxObjectInactive) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } @@ -111,8 +120,8 @@ // Try to acquire token if (SemaphoreTokenDecrement(semaphore) != 0U) { // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)semaphore); - osRtxThreadWaitExit(thread, (uint32_t)osOK, false); + thread = osRtxThreadListGet(osRtxObject(semaphore)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); EvrRtxSemaphoreAcquired(semaphore); } } @@ -121,39 +130,36 @@ // ==== Service Calls ==== -// Service Calls definitions -SVC0_3M(SemaphoreNew, osSemaphoreId_t, uint32_t, uint32_t, const osSemaphoreAttr_t *) -SVC0_1 (SemaphoreGetName, const char *, osSemaphoreId_t) -SVC0_2 (SemaphoreAcquire, osStatus_t, osSemaphoreId_t, uint32_t) -SVC0_1 (SemaphoreRelease, osStatus_t, osSemaphoreId_t) -SVC0_1 (SemaphoreGetCount, uint32_t, osSemaphoreId_t) -SVC0_1 (SemaphoreDelete, osStatus_t, osSemaphoreId_t) - /// Create and Initialize a Semaphore object. /// \note API identical to osSemaphoreNew -osSemaphoreId_t svcRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { +static osSemaphoreId_t svcRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { os_semaphore_t *semaphore; uint8_t flags; const char *name; // Check parameters if ((max_count == 0U) || (max_count > osRtxSemaphoreTokenLimit) || (initial_count > max_count)) { - EvrRtxSemaphoreError(NULL, osErrorParameter); + EvrRtxSemaphoreError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Process attributes if (attr != NULL) { name = attr->name; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] semaphore = attr->cb_mem; if (semaphore != NULL) { - if (((uint32_t)semaphore & 3U) || (attr->cb_size < sizeof(os_semaphore_t))) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)semaphore & 3U) != 0U) || (attr->cb_size < sizeof(os_semaphore_t))) { EvrRtxSemaphoreError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } else { if (attr->cb_size != 0U) { EvrRtxSemaphoreError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } @@ -165,50 +171,64 @@ // Allocate object memory if not provided if (semaphore == NULL) { if (osRtxInfo.mpi.semaphore != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] semaphore = osRtxMemoryPoolAlloc(osRtxInfo.mpi.semaphore); } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] semaphore = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_semaphore_t), 1U); } - if (semaphore == NULL) { - EvrRtxSemaphoreError(NULL, osErrorNoMemory); - return NULL; +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (semaphore != NULL) { + uint32_t used; + osRtxSemaphoreMemUsage.cnt_alloc++; + used = osRtxSemaphoreMemUsage.cnt_alloc - osRtxSemaphoreMemUsage.cnt_free; + if (osRtxSemaphoreMemUsage.max_used < used) { + osRtxSemaphoreMemUsage.max_used = used; + } } +#endif flags = osRtxFlagSystemObject; } else { flags = 0U; } - // Initialize control block - semaphore->id = osRtxIdSemaphore; - semaphore->state = osRtxObjectActive; - semaphore->flags = flags; - semaphore->name = name; - semaphore->thread_list = NULL; - semaphore->tokens = (uint16_t)initial_count; - semaphore->max_tokens = (uint16_t)max_count; + if (semaphore != NULL) { + // Initialize control block + semaphore->id = osRtxIdSemaphore; + semaphore->state = osRtxObjectActive; + semaphore->flags = flags; + semaphore->name = name; + semaphore->thread_list = NULL; + semaphore->tokens = (uint16_t)initial_count; + semaphore->max_tokens = (uint16_t)max_count; - // Register post ISR processing function - osRtxInfo.post_process.semaphore = osRtxSemaphorePostProcess; + // Register post ISR processing function + osRtxInfo.post_process.semaphore = osRtxSemaphorePostProcess; - EvrRtxSemaphoreCreated(semaphore); + EvrRtxSemaphoreCreated(semaphore, semaphore->name); + } else { + EvrRtxSemaphoreError(NULL,(int32_t)osErrorNoMemory); + } return semaphore; } /// Get name of a Semaphore object. /// \note API identical to osSemaphoreGetName -const char *svcRtxSemaphoreGetName (osSemaphoreId_t semaphore_id) { - os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id; +static const char *svcRtxSemaphoreGetName (osSemaphoreId_t semaphore_id) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); // Check parameters if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { EvrRtxSemaphoreGetName(semaphore, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check object state if (semaphore->state == osRtxObjectInactive) { EvrRtxSemaphoreGetName(semaphore, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -219,56 +239,66 @@ /// Acquire a Semaphore token or timeout if no tokens are available. /// \note API identical to osSemaphoreAcquire -osStatus_t svcRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { - os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id; +static osStatus_t svcRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); + osStatus_t status; // Check parameters if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { - EvrRtxSemaphoreError(semaphore, osErrorParameter); + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreError(semaphore, osErrorResource); + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } // Try to acquire token - if (SemaphoreTokenDecrement(semaphore) == 0U) { + if (SemaphoreTokenDecrement(semaphore) != 0U) { + EvrRtxSemaphoreAcquired(semaphore); + status = osOK; + } else { // No token available if (timeout != 0U) { EvrRtxSemaphoreAcquirePending(semaphore, timeout); // Suspend current Thread - osRtxThreadListPut((os_object_t*)semaphore, osRtxThreadGetRunning()); - osRtxThreadWaitEnter(osRtxThreadWaitingSemaphore, timeout); - return osErrorTimeout; + if (osRtxThreadWaitEnter(osRtxThreadWaitingSemaphore, timeout)) { + osRtxThreadListPut(osRtxObject(semaphore), osRtxThreadGetRunning()); + } else { + EvrRtxSemaphoreAcquireTimeout(semaphore); + } + status = osErrorTimeout; } else { EvrRtxSemaphoreNotAcquired(semaphore); - return osErrorResource; + status = osErrorResource; } } - EvrRtxSemaphoreAcquired(semaphore); - - return osOK; + return status; } /// Release a Semaphore token that was acquired by osSemaphoreAcquire. /// \note API identical to osSemaphoreRelease -osStatus_t svcRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) { - os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id; +static osStatus_t svcRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); os_thread_t *thread; + osStatus_t status; // Check parameters if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { - EvrRtxSemaphoreError(semaphore, osErrorParameter); + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreError(semaphore, osErrorResource); + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -276,35 +306,40 @@ if (semaphore->thread_list != NULL) { EvrRtxSemaphoreReleased(semaphore); // Wakeup waiting Thread with highest Priority - thread = osRtxThreadListGet((os_object_t*)semaphore); - osRtxThreadWaitExit(thread, (uint32_t)osOK, true); + thread = osRtxThreadListGet(osRtxObject(semaphore)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE); EvrRtxSemaphoreAcquired(semaphore); + status = osOK; } else { // Try to release token - if (SemaphoreTokenIncrement(semaphore) == 0U) { + if (SemaphoreTokenIncrement(semaphore) != 0U) { + EvrRtxSemaphoreReleased(semaphore); + status = osOK; + } else { EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit); - return osErrorResource; + status = osErrorResource; } - EvrRtxSemaphoreReleased(semaphore); } - return osOK; + return status; } /// Get current Semaphore token count. /// \note API identical to osSemaphoreGetCount -uint32_t svcRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id) { - os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id; +static uint32_t svcRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); // Check parameters if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { EvrRtxSemaphoreGetCount(semaphore, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (semaphore->state == osRtxObjectInactive) { EvrRtxSemaphoreGetCount(semaphore, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -315,19 +350,21 @@ /// Delete a Semaphore object. /// \note API identical to osSemaphoreDelete -osStatus_t svcRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) { - os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id; +static osStatus_t svcRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); os_thread_t *thread; // Check parameters if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { - EvrRtxSemaphoreError(semaphore, osErrorParameter); + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreError(semaphore, osErrorResource); + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -337,19 +374,22 @@ // Unblock waiting threads if (semaphore->thread_list != NULL) { do { - thread = osRtxThreadListGet((os_object_t*)semaphore); - osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, false); + thread = osRtxThreadListGet(osRtxObject(semaphore)); + osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE); } while (semaphore->thread_list != NULL); osRtxThreadDispatch(NULL); } // Free object memory - if (semaphore->flags & osRtxFlagSystemObject) { + if ((semaphore->flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.semaphore != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.semaphore, semaphore); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.semaphore, semaphore); } else { - osRtxMemoryFree(osRtxInfo.mem.common, semaphore); + (void)osRtxMemoryFree(osRtxInfo.mem.common, semaphore); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxSemaphoreMemUsage.cnt_free++; +#endif } EvrRtxSemaphoreDestroyed(semaphore); @@ -357,6 +397,16 @@ return osOK; } +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_3(SemaphoreNew, osSemaphoreId_t, uint32_t, uint32_t, const osSemaphoreAttr_t *) +SVC0_1(SemaphoreGetName, const char *, osSemaphoreId_t) +SVC0_2(SemaphoreAcquire, osStatus_t, osSemaphoreId_t, uint32_t) +SVC0_1(SemaphoreRelease, osStatus_t, osSemaphoreId_t) +SVC0_1(SemaphoreGetCount, uint32_t, osSemaphoreId_t) +SVC0_1(SemaphoreDelete, osStatus_t, osSemaphoreId_t) +//lint --flb "Library End" + // ==== ISR Calls ==== @@ -364,62 +414,69 @@ /// \note API identical to osSemaphoreAcquire __STATIC_INLINE osStatus_t isrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { - os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id; + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); + osStatus_t status; // Check parameters if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore) || (timeout != 0U)) { - EvrRtxSemaphoreError(semaphore, osErrorParameter); + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreError(semaphore, osErrorResource); + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } // Try to acquire token - if (SemaphoreTokenDecrement(semaphore) == 0U) { + if (SemaphoreTokenDecrement(semaphore) != 0U) { + EvrRtxSemaphoreAcquired(semaphore); + status = osOK; + } else { // No token available EvrRtxSemaphoreNotAcquired(semaphore); - return osErrorResource; + status = osErrorResource; } - EvrRtxSemaphoreAcquired(semaphore); - - return osOK; + return status; } /// Release a Semaphore token that was acquired by osSemaphoreAcquire. /// \note API identical to osSemaphoreRelease __STATIC_INLINE osStatus_t isrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) { - os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id; + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); + osStatus_t status; // Check parameters if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { - EvrRtxSemaphoreError(semaphore, osErrorParameter); + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreError(semaphore, osErrorResource); + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } // Try to release token if (SemaphoreTokenIncrement(semaphore) != 0U) { // Register post ISR processing - osRtxPostProcess((os_object_t *)semaphore); + osRtxPostProcess(osRtxObject(semaphore)); + EvrRtxSemaphoreReleased(semaphore); + status = osOK; } else { EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit); - return osErrorResource; + status = osErrorResource; } - EvrRtxSemaphoreReleased(semaphore); - - return osOK; + return status; } @@ -427,58 +484,79 @@ /// Create and Initialize a Semaphore object. osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { + osSemaphoreId_t semaphore_id; + EvrRtxSemaphoreNew(max_count, initial_count, attr); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxSemaphoreError(NULL, osErrorISR); - return NULL; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxSemaphoreError(NULL, (int32_t)osErrorISR); + semaphore_id = NULL; + } else { + semaphore_id = __svcSemaphoreNew(max_count, initial_count, attr); } - return __svcSemaphoreNew(max_count, initial_count, attr); + return semaphore_id; } /// Get name of a Semaphore object. const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxSemaphoreGetName(semaphore_id, NULL); - return NULL; + name = NULL; + } else { + name = __svcSemaphoreGetName(semaphore_id); } - return __svcSemaphoreGetName(semaphore_id); + return name; } /// Acquire a Semaphore token or timeout if no tokens are available. osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + osStatus_t status; + EvrRtxSemaphoreAcquire(semaphore_id, timeout); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return isrRtxSemaphoreAcquire(semaphore_id, timeout); + if (IsIrqMode() || IsIrqMasked()) { + status = isrRtxSemaphoreAcquire(semaphore_id, timeout); } else { - return __svcSemaphoreAcquire(semaphore_id, timeout); + status = __svcSemaphoreAcquire(semaphore_id, timeout); } + return status; } /// Release a Semaphore token that was acquired by osSemaphoreAcquire. osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) { + osStatus_t status; + EvrRtxSemaphoreRelease(semaphore_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return isrRtxSemaphoreRelease(semaphore_id); + if (IsIrqMode() || IsIrqMasked()) { + status = isrRtxSemaphoreRelease(semaphore_id); } else { - return __svcSemaphoreRelease(semaphore_id); + status = __svcSemaphoreRelease(semaphore_id); } + return status; } /// Get current Semaphore token count. uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return svcRtxSemaphoreGetCount(semaphore_id); + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + count = svcRtxSemaphoreGetCount(semaphore_id); } else { - return __svcSemaphoreGetCount(semaphore_id); + count = __svcSemaphoreGetCount(semaphore_id); } + return count; } /// Delete a Semaphore object. osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) { + osStatus_t status; + EvrRtxSemaphoreDelete(semaphore_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxSemaphoreError(semaphore_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxSemaphoreError(semaphore_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcSemaphoreDelete(semaphore_id); } - return __svcSemaphoreDelete(semaphore_id); + return status; } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_system.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_system.c index fc64c93..f7acbf0 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_system.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_system.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -31,8 +31,8 @@ /// Put Object into ISR Queue. /// \param[in] object object. /// \return 1 - success, 0 - failure. -static uint32_t isr_queue_put (void *object) { -#if (__EXCLUSIVE_ACCESS == 0U) +static uint32_t isr_queue_put (os_object_t *object) { +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #else uint32_t n; @@ -42,7 +42,7 @@ max = osRtxInfo.isr_queue.max; -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); if (osRtxInfo.isr_queue.cnt < max) { @@ -74,23 +74,23 @@ /// Get Object from ISR Queue. /// \return object or NULL. -static void *isr_queue_get (void) { -#if (__EXCLUSIVE_ACCESS == 0U) - uint32_t primask = __get_PRIMASK(); +static os_object_t *isr_queue_get (void) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); #else - uint32_t n; + uint32_t n; #endif - uint16_t max; - void *ret; + uint16_t max; + os_object_t *ret; max = osRtxInfo.isr_queue.max; -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); if (osRtxInfo.isr_queue.cnt != 0U) { osRtxInfo.isr_queue.cnt--; - ret = osRtxInfo.isr_queue.data[osRtxInfo.isr_queue.out]; + ret = osRtxObject(osRtxInfo.isr_queue.data[osRtxInfo.isr_queue.out]); if (++osRtxInfo.isr_queue.out == max) { osRtxInfo.isr_queue.out = 0U; } @@ -104,7 +104,7 @@ #else if (atomic_dec16_nz(&osRtxInfo.isr_queue.cnt) != 0U) { n = atomic_inc16_lim(&osRtxInfo.isr_queue.out, max); - ret = osRtxInfo.isr_queue.data[n]; + ret = osRtxObject(osRtxInfo.isr_queue.data[n]); } else { ret = NULL; } @@ -117,6 +117,9 @@ // ==== Library Functions ==== /// Tick Handler. +//lint -esym(714,osRtxTick_Handler) "Referenced by Exception handlers" +//lint -esym(759,osRtxTick_Handler) "Prototype in header" +//lint -esym(765,osRtxTick_Handler) "Global scope" void osRtxTick_Handler (void) { os_thread_t *thread; @@ -150,6 +153,7 @@ if ((thread != NULL) && (thread->priority == osRtxInfo.thread.robin.thread->priority)) { osRtxThreadListRemove(thread); osRtxThreadReadyPut(osRtxInfo.thread.robin.thread); + EvrRtxThreadPreempted(osRtxInfo.thread.robin.thread); osRtxThreadSwitch(thread); osRtxInfo.thread.robin.thread = thread; osRtxInfo.thread.robin.tick = osRtxInfo.thread.robin.timeout; @@ -161,6 +165,9 @@ } /// Pending Service Call Handler. +//lint -esym(714,osRtxPendSV_Handler) "Referenced by Exception handlers" +//lint -esym(759,osRtxPendSV_Handler) "Prototype in header" +//lint -esym(765,osRtxPendSV_Handler) "Global scope" void osRtxPendSV_Handler (void) { os_object_t *object; @@ -171,21 +178,22 @@ } switch (object->id) { case osRtxIdThread: - osRtxInfo.post_process.thread((os_thread_t *)object); + osRtxInfo.post_process.thread(osRtxThreadObject(object)); break; case osRtxIdEventFlags: - osRtxInfo.post_process.event_flags((os_event_flags_t *)object); + osRtxInfo.post_process.event_flags(osRtxEventFlagsObject(object)); break; case osRtxIdSemaphore: - osRtxInfo.post_process.semaphore((os_semaphore_t *)object); + osRtxInfo.post_process.semaphore(osRtxSemaphoreObject(object)); break; case osRtxIdMemoryPool: - osRtxInfo.post_process.memory_pool((os_memory_pool_t *)object); + osRtxInfo.post_process.memory_pool(osRtxMemoryPoolObject(object)); break; case osRtxIdMessage: - osRtxInfo.post_process.message_queue((os_message_t *)object); + osRtxInfo.post_process.message(osRtxMessageObject(object)); break; default: + // Should never come here break; } } @@ -204,6 +212,6 @@ osRtxInfo.kernel.pendSV = 1U; } } else { - osRtxErrorNotify(osRtxErrorISRQueueOverflow, object); + (void)osRtxErrorNotify(osRtxErrorISRQueueOverflow, object); } } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c index 6e15a4c..43a55c7 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,6 +26,14 @@ #include "rtx_lib.h" #include "rt_OsEventObserver.h" +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxThreadMemUsage \ +__attribute__((section(".data.os.thread.obj"))) = +{ 0U, 0U, 0U }; +#endif + + // ==== Helper functions ==== /// Set Thread Flags. @@ -33,12 +41,12 @@ /// \param[in] flags specifies the flags to set. /// \return thread flags after setting. static uint32_t ThreadFlagsSet (os_thread_t *thread, uint32_t flags) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif uint32_t thread_flags; -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); thread->thread_flags |= flags; @@ -59,12 +67,12 @@ /// \param[in] flags specifies the flags to clear. /// \return thread flags before clearing. static uint32_t ThreadFlagsClear (os_thread_t *thread, uint32_t flags) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif uint32_t thread_flags; -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) __disable_irq(); thread_flags = thread->thread_flags; @@ -86,13 +94,13 @@ /// \param[in] options specifies flags options (osFlagsXxxx). /// \return thread flags before clearing or 0 if specified flags have not been set. static uint32_t ThreadFlagsCheck (os_thread_t *thread, uint32_t flags, uint32_t options) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) uint32_t primask; #endif uint32_t thread_flags; if ((options & osFlagsNoClear) == 0U) { -#if (__EXCLUSIVE_ACCESS == 0U) +#if (EXCLUSIVE_ACCESS == 0) primask = __get_PRIMASK(); __disable_irq(); @@ -131,17 +139,18 @@ /// Put a Thread into specified Object list sorted by Priority (Highest at Head). /// \param[in] object generic object. /// \param[in] thread thread object. -void osRtxThreadListPut (volatile os_object_t *object, os_thread_t *thread) { +void osRtxThreadListPut (os_object_t *object, os_thread_t *thread) { os_thread_t *prev, *next; int32_t priority; if (thread == NULL) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } priority = thread->priority; - prev = (os_thread_t *)(uint32_t)object; + prev = osRtxThreadObject(object); next = object->thread_list; while ((next != NULL) && (next->priority >= priority)) { prev = next; @@ -157,15 +166,15 @@ /// Get a Thread with Highest Priority from specified Object list and remove it. /// \param[in] object generic object. -/// \return thread object. -os_thread_t *osRtxThreadListGet (volatile os_object_t *object) { +/// \return thread object. +os_thread_t *osRtxThreadListGet (os_object_t *object) { os_thread_t *thread; thread = object->thread_list; if (thread != NULL) { object->thread_list = thread->thread_next; if (thread->thread_next != NULL) { - thread->thread_next->thread_prev = (os_thread_t *)(uint32_t)object; + thread->thread_next->thread_prev = osRtxThreadObject(object); } thread->thread_prev = NULL; } @@ -175,13 +184,17 @@ /// Retrieve Thread list root. /// \param[in] thread thread object. -void *osRtxThreadListRoot (os_thread_t *thread) { +#ifndef EVR_RTX_DISABLE +static void *osRtxThreadListRoot (os_thread_t *thread) { + os_thread_t *thread0; - while ((thread != NULL) && (thread->id == osRtxIdThread)) { - thread = thread->thread_prev; + thread0 = thread; + while ((thread0 != NULL) && (thread0->id == osRtxIdThread)) { + thread0 = thread0->thread_prev; } - return ((void *)thread); + return thread0; } +#endif /// Re-sort a Thread in linked Object list by Priority (Highest at Head). /// \param[in] thread thread object. @@ -191,16 +204,15 @@ // Search for object thread0 = thread; - while (thread0->id == osRtxIdThread) { + while ((thread0 != NULL) && (thread0->id == osRtxIdThread)) { thread0 = thread0->thread_prev; - if (thread0 == NULL) { - return; - } } - object = (os_object_t *)thread0; + object = osRtxObject(thread0); - osRtxThreadListRemove(thread); - osRtxThreadListPut(object, thread); + if (object != NULL) { + osRtxThreadListRemove(thread); + osRtxThreadListPut(object, thread); + } } /// Remove a Thread from linked Object list. @@ -218,7 +230,7 @@ /// Unlink a Thread from specified linked list. /// \param[in] thread thread object. -void osRtxThreadListUnlink (os_thread_t **thread_list, os_thread_t *thread) { +static void osRtxThreadListUnlink (os_thread_t **thread_list, os_thread_t *thread) { if (thread->thread_next != NULL) { thread->thread_next->thread_prev = thread->thread_prev; @@ -242,7 +254,7 @@ /// Insert a Thread into the Delay list sorted by Delay (Lowest at Head). /// \param[in] thread thread object. /// \param[in] delay delay value. -void osRtxThreadDelayInsert (os_thread_t *thread, uint32_t delay) { +static void osRtxThreadDelayInsert (os_thread_t *thread, uint32_t delay) { os_thread_t *prev, *next; if (delay == osWaitForever) { @@ -254,15 +266,12 @@ } thread->delay = delay; thread->delay_prev = prev; - thread->delay_next = next; + thread->delay_next = NULL; if (prev != NULL) { prev->delay_next = thread; } else { osRtxInfo.thread.wait_list = thread; } - if (next != NULL) { - next->delay_prev = thread; - } } else { prev = NULL; next = osRtxInfo.thread.delay_list; @@ -288,34 +297,32 @@ /// Remove a Thread from the Delay list. /// \param[in] thread thread object. -void osRtxThreadDelayRemove (os_thread_t *thread) { +static void osRtxThreadDelayRemove (os_thread_t *thread) { if (thread->delay == osWaitForever) { - if ((thread->delay_prev == NULL) && (osRtxInfo.thread.wait_list != thread)) { - return; - } - if (thread->delay_next != NULL) { - thread->delay_next->delay_prev = thread->delay_prev; - } - if (thread->delay_prev != NULL) { - thread->delay_prev->delay_next = thread->delay_next; - thread->delay_prev = NULL; - } else { - osRtxInfo.thread.wait_list = thread->delay_next; + if ((thread->delay_prev != NULL) || (osRtxInfo.thread.wait_list == thread)) { + if (thread->delay_next != NULL) { + thread->delay_next->delay_prev = thread->delay_prev; + } + if (thread->delay_prev != NULL) { + thread->delay_prev->delay_next = thread->delay_next; + thread->delay_prev = NULL; + } else { + osRtxInfo.thread.wait_list = thread->delay_next; + } } } else { - if ((thread->delay_prev == NULL) && (osRtxInfo.thread.delay_list != thread)) { - return; - } - if (thread->delay_next != NULL) { - thread->delay_next->delay += thread->delay; - thread->delay_next->delay_prev = thread->delay_prev; - } - if (thread->delay_prev != NULL) { - thread->delay_prev->delay_next = thread->delay_next; - thread->delay_prev = NULL; - } else { - osRtxInfo.thread.delay_list = thread->delay_next; + if ((thread->delay_prev != NULL) || (osRtxInfo.thread.delay_list == thread)) { + if (thread->delay_next != NULL) { + thread->delay_next->delay += thread->delay; + thread->delay_next->delay_prev = thread->delay_prev; + } + if (thread->delay_prev != NULL) { + thread->delay_prev->delay_next = thread->delay_next; + thread->delay_prev = NULL; + } else { + osRtxInfo.thread.delay_list = thread->delay_next; + } } } } @@ -326,6 +333,7 @@ thread = osRtxInfo.thread.delay_list; if (thread == NULL) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } @@ -359,6 +367,7 @@ EvrRtxMessageQueuePutTimeout((osMessageQueueId_t)osRtxThreadListRoot(thread)); break; default: + // Invalid break; } EvrRtxThreadUnblocked(thread, (osRtxThreadRegPtr(thread))[0]); @@ -376,13 +385,15 @@ /// Get pointer to Thread registers (R0..R3) /// \param[in] thread thread object. /// \return pointer to registers R0-R3. -uint32_t *osRtxThreadRegPtr (os_thread_t *thread) { - return ((uint32_t *)(thread->sp + STACK_OFFSET_R0(thread->stack_frame))); +uint32_t *osRtxThreadRegPtr (const os_thread_t *thread) { + uint32_t addr = thread->sp + StackOffsetR0(thread->stack_frame); + //lint -e{923} -e{9078} "cast from unsigned int to pointer" + return ((uint32_t *)addr); } /// Block running Thread execution and register it as Ready to Run. /// \param[in] thread running thread object. -void osRtxThreadBlock (os_thread_t *thread) { +static void osRtxThreadBlock (os_thread_t *thread) { os_thread_t *prev, *next; int32_t priority; @@ -390,7 +401,7 @@ priority = thread->priority; - prev = (os_thread_t *)(uint32_t)&osRtxInfo.thread.ready; + prev = osRtxThreadObject(&osRtxInfo.thread.ready); next = prev->thread_next; while ((next != NULL) && (next->priority > priority)) { @@ -403,6 +414,8 @@ if (next != NULL) { next->thread_prev = thread; } + + EvrRtxThreadPreempted(thread); } /// Switch to specified Thread. @@ -412,7 +425,11 @@ thread->state = osRtxThreadRunning; osRtxInfo.thread.run.next = thread; osRtxThreadStackCheck(); - EvrRtxThreadSwitch(thread); + EvrRtxThreadSwitched(thread); + + if (osEventObs && osEventObs->thread_switch) { + osEventObs->thread_switch(thread->context); + } } /// Notify the OS event observer of an imminent thread switch. @@ -427,10 +444,11 @@ void osRtxThreadDispatch (os_thread_t *thread) { uint8_t kernel_state; os_thread_t *thread_running; + os_thread_t *thread_ready; kernel_state = osRtxKernelGetState(); thread_running = osRtxThreadGetRunning(); -#if (__ARM_ARCH_7A__ != 0U) +#if (defined(__ARM_ARCH_7A__) && (__ARM_ARCH_7A__ != 0)) // On Cortex-A PendSV_Handler is executed before final context switch. if ((thread_running != NULL) && (thread_running->state != osRtxThreadRunning)) { thread_running = osRtxInfo.thread.run.next; @@ -438,14 +456,14 @@ #endif if (thread == NULL) { - thread = osRtxInfo.thread.ready.thread_list; + thread_ready = osRtxInfo.thread.ready.thread_list; if ((kernel_state == osRtxKernelRunning) && - (thread_running != NULL) && (thread != NULL) && - (thread->priority > thread_running->priority)) { + (thread_running != NULL) && (thread_ready != NULL) && + (thread_ready->priority > thread_running->priority)) { // Preempt running Thread - osRtxThreadListRemove(thread); + osRtxThreadListRemove(thread_ready); osRtxThreadBlock(thread_running); - osRtxThreadSwitch(thread); + osRtxThreadSwitch(thread_ready); } } else { if ((kernel_state == osRtxKernelRunning) && @@ -465,7 +483,7 @@ /// \param[in] thread thread object. /// \param[in] ret_val return value. /// \param[in] dispatch dispatch flag. -void osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool dispatch) { +void osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool_t dispatch) { uint32_t *reg; EvrRtxThreadUnblocked(thread, ret_val); @@ -485,21 +503,26 @@ /// \param[in] state new thread state. /// \param[in] timeout timeout. /// \return true - success, false - failure. -bool osRtxThreadWaitEnter (uint8_t state, uint32_t timeout) { +bool_t osRtxThreadWaitEnter (uint8_t state, uint32_t timeout) { os_thread_t *thread; + // Check if Kernel is running + if (osRtxKernelGetState() != osRtxKernelRunning) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return FALSE; + } + + // Check running thread thread = osRtxThreadGetRunning(); if (thread == NULL) { - return false; + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return FALSE; } - if (osRtxKernelGetState() != osRtxKernelRunning) { - osRtxThreadListRemove(thread); - return false; - } - + // Check if any thread is ready if (osRtxInfo.thread.ready.thread_list == NULL) { - return false; + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return FALSE; } EvrRtxThreadBlocked(thread, timeout); @@ -509,29 +532,38 @@ thread = osRtxThreadListGet(&osRtxInfo.thread.ready); osRtxThreadSwitch(thread); - return true; + return TRUE; } /// Check current running Thread Stack. +//lint -esym(759,osRtxThreadStackCheck) "Prototype in header" +//lint -esym(765,osRtxThreadStackCheck) "Global scope (can be overridden)" __WEAK void osRtxThreadStackCheck (void) { os_thread_t *thread; thread = osRtxThreadGetRunning(); if (thread != NULL) { + //lint -e{923} "cast from pointer to unsigned int" + //lint -e{9079} -e{9087} "cast between pointers to different object types" if ((thread->sp <= (uint32_t)thread->stack_mem) || (*((uint32_t *)thread->stack_mem) != osRtxStackMagicWord)) { - osRtxErrorNotify(osRtxErrorStackUnderflow, thread); + (void)osRtxErrorNotify(osRtxErrorStackUnderflow, thread); } } } + +// ==== Post ISR processing ==== + /// Thread post ISR processing. /// \param[in] thread thread object. -void osRtxThreadPostProcess (os_thread_t *thread) { +static void osRtxThreadPostProcess (os_thread_t *thread) { uint32_t thread_flags; + // Check thread state if ((thread->state == osRtxThreadInactive) || (thread->state == osRtxThreadTerminated)) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } @@ -539,7 +571,7 @@ if (thread->state == osRtxThreadWaitingThreadFlags) { thread_flags = ThreadFlagsCheck(thread, thread->wait_flags, thread->flags_options); if (thread_flags != 0U) { - osRtxThreadWaitExit(thread, thread_flags, false); + osRtxThreadWaitExit(thread, thread_flags, FALSE); EvrRtxThreadFlagsWaitCompleted(thread->wait_flags, thread->flags_options, thread_flags); } } @@ -548,29 +580,6 @@ // ==== Service Calls ==== -// Service Calls definitions -SVC0_4M(ThreadNew, osThreadId_t, osThreadFunc_t, void *, const osThreadAttr_t *, void *) -SVC0_1 (ThreadGetName, const char *, osThreadId_t) -SVC0_0 (ThreadGetId, osThreadId_t) -SVC0_1 (ThreadGetState, osThreadState_t, osThreadId_t) -SVC0_1 (ThreadGetStackSize, uint32_t, osThreadId_t) -SVC0_1 (ThreadGetStackSpace, uint32_t, osThreadId_t) -SVC0_2 (ThreadSetPriority, osStatus_t, osThreadId_t, osPriority_t) -SVC0_1 (ThreadGetPriority, osPriority_t, osThreadId_t) -SVC0_0 (ThreadYield, osStatus_t) -SVC0_1 (ThreadSuspend, osStatus_t, osThreadId_t) -SVC0_1 (ThreadResume, osStatus_t, osThreadId_t) -SVC0_1 (ThreadDetach, osStatus_t, osThreadId_t) -SVC0_1 (ThreadJoin, osStatus_t, osThreadId_t) -SVC0_0N(ThreadExit, void) -SVC0_1 (ThreadTerminate, osStatus_t, osThreadId_t) -SVC0_0 (ThreadGetCount, uint32_t) -SVC0_2 (ThreadEnumerate, uint32_t, osThreadId_t *, uint32_t) -SVC0_2 (ThreadFlagsSet, uint32_t, osThreadId_t, uint32_t) -SVC0_1 (ThreadFlagsClear, uint32_t, uint32_t) -SVC0_0 (ThreadFlagsGet, uint32_t) -SVC0_3 (ThreadFlagsWait, uint32_t, uint32_t, uint32_t, uint32_t) - /// Create a thread and add it to Active Threads. /// \note API identical to osThreadContextNew osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr, void *context) { @@ -583,14 +592,15 @@ const char *name; uint32_t *ptr; uint32_t n; -#if (__DOMAIN_NS == 1U) +#if (DOMAIN_NS == 1) TZ_ModuleId_t tz_module; TZ_MemoryId_t tz_memory; #endif // Check parameters if (func == NULL) { - EvrRtxThreadError(NULL, osErrorParameter); + EvrRtxThreadError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -598,27 +608,34 @@ if (attr != NULL) { name = attr->name; attr_bits = attr->attr_bits; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] thread = attr->cb_mem; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] stack_mem = attr->stack_mem; stack_size = attr->stack_size; priority = attr->priority; -#if (__DOMAIN_NS == 1U) +#if (DOMAIN_NS == 1) tz_module = attr->tz_module; #endif if (thread != NULL) { - if (((uint32_t)thread & 3U) || (attr->cb_size < sizeof(os_thread_t))) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)thread & 3U) != 0U) || (attr->cb_size < sizeof(os_thread_t))) { EvrRtxThreadError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } else { if (attr->cb_size != 0U) { EvrRtxThreadError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } if (stack_mem != NULL) { - if (((uint32_t)stack_mem & 7U) || (stack_size == 0U)) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)stack_mem & 7U) != 0U) || (stack_size == 0U)) { EvrRtxThreadError(NULL, osRtxErrorInvalidThreadStack); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } @@ -627,6 +644,7 @@ } else { if ((priority < osPriorityIdle) || (priority > osPriorityISR)) { EvrRtxThreadError(NULL, osRtxErrorInvalidPriority); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } @@ -637,141 +655,166 @@ stack_mem = NULL; stack_size = 0U; priority = osPriorityNormal; -#if (__DOMAIN_NS == 1U) +#if (DOMAIN_NS == 1) tz_module = 0U; #endif } // Check stack size - if ((stack_size != 0U) && ((stack_size & 7U) || (stack_size < (64U + 8U)))) { + if ((stack_size != 0U) && (((stack_size & 7U) != 0U) || (stack_size < (64U + 8U)))) { EvrRtxThreadError(NULL, osRtxErrorInvalidThreadStack); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Allocate object memory if not provided if (thread == NULL) { if (osRtxInfo.mpi.thread != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] thread = osRtxMemoryPoolAlloc(osRtxInfo.mpi.thread); } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] thread = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_thread_t), 1U); } - if (thread == NULL) { - EvrRtxThreadError(NULL, osErrorNoMemory); - return NULL; +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (thread != NULL) { + uint32_t used; + osRtxThreadMemUsage.cnt_alloc++; + used = osRtxThreadMemUsage.cnt_alloc - osRtxThreadMemUsage.cnt_free; + if (osRtxThreadMemUsage.max_used < used) { + osRtxThreadMemUsage.max_used = used; + } } +#endif flags = osRtxFlagSystemObject; } else { flags = 0U; } // Allocate stack memory if not provided - if (stack_mem == NULL) { + if ((thread != NULL) && (stack_mem == NULL)) { if (stack_size == 0U) { stack_size = osRtxConfig.thread_stack_size; if (osRtxInfo.mpi.stack != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] stack_mem = osRtxMemoryPoolAlloc(osRtxInfo.mpi.stack); if (stack_mem != NULL) { flags |= osRtxThreadFlagDefStack; } } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] stack_mem = osRtxMemoryAlloc(osRtxInfo.mem.stack, stack_size, 0U); } } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] stack_mem = osRtxMemoryAlloc(osRtxInfo.mem.stack, stack_size, 0U); } if (stack_mem == NULL) { - EvrRtxThreadError(NULL, osErrorNoMemory); - if (flags & osRtxFlagSystemObject) { + if ((flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.thread != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread); } else { - osRtxMemoryFree(osRtxInfo.mem.common, thread); + (void)osRtxMemoryFree(osRtxInfo.mem.common, thread); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxThreadMemUsage.cnt_free++; +#endif } - return NULL; + thread = NULL; } flags |= osRtxFlagSystemMemory; } -#if (__DOMAIN_NS == 1U) +#if (DOMAIN_NS == 1) // Allocate secure process stack - if (tz_module != 0U) { + if ((thread != NULL) && (tz_module != 0U)) { tz_memory = TZ_AllocModuleContext_S(tz_module); if (tz_memory == 0U) { EvrRtxThreadError(NULL, osRtxErrorTZ_AllocContext_S); - if (flags & osRtxFlagSystemMemory) { - if (flags & osRtxThreadFlagDefStack) { - osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem); + if ((flags & osRtxFlagSystemMemory) != 0U) { + if ((flags & osRtxThreadFlagDefStack) != 0U) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem); } else { - osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem); + (void)osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem); } } - if (flags & osRtxFlagSystemObject) { + if ((flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.thread != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread); } else { - osRtxMemoryFree(osRtxInfo.mem.common, thread); + (void)osRtxMemoryFree(osRtxInfo.mem.common, thread); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxThreadMemUsage.cnt_free++; +#endif } - return NULL; + thread = NULL; } } else { tz_memory = 0U; } #endif - // Initialize control block - thread->id = osRtxIdThread; - thread->state = osRtxThreadReady; - thread->flags = flags; - thread->attr = (uint8_t)attr_bits; - thread->name = name; - thread->thread_next = NULL; - thread->thread_prev = NULL; - thread->delay_next = NULL; - thread->delay_prev = NULL; - thread->thread_join = NULL; - thread->delay = 0U; - thread->priority = (int8_t)priority; - thread->priority_base = (int8_t)priority; - thread->stack_frame = STACK_FRAME_INIT; - thread->flags_options = 0U; - thread->wait_flags = 0U; - thread->thread_flags = 0U; - thread->mutex_list = NULL; - thread->stack_mem = stack_mem; - thread->stack_size = stack_size; - thread->sp = (uint32_t)stack_mem + stack_size - 64U; - thread->thread_addr = (uint32_t)func; -#if (__DOMAIN_NS == 1U) - thread->tz_memory = tz_memory; -#endif + if (thread != NULL) { + // Initialize control block + //lint --e{923} --e{9078} "cast between pointers and unsigned int" + //lint --e{9079} --e{9087} "cast between pointers to different object types" + //lint --e{9074} "conversion between a pointer to function and another type" + thread->id = osRtxIdThread; + thread->state = osRtxThreadReady; + thread->flags = flags; + thread->attr = (uint8_t)attr_bits; + thread->name = name; + thread->thread_next = NULL; + thread->thread_prev = NULL; + thread->delay_next = NULL; + thread->delay_prev = NULL; + thread->thread_join = NULL; + thread->delay = 0U; + thread->priority = (int8_t)priority; + thread->priority_base = (int8_t)priority; + thread->stack_frame = STACK_FRAME_INIT_VAL; + thread->flags_options = 0U; + thread->wait_flags = 0U; + thread->thread_flags = 0U; + thread->mutex_list = NULL; + thread->stack_mem = stack_mem; + thread->stack_size = stack_size; + thread->sp = (uint32_t)stack_mem + stack_size - 64U; + thread->thread_addr = (uint32_t)func; + #if (DOMAIN_NS == 1) + thread->tz_memory = tz_memory; + #endif - // Initialize stack - ptr = (uint32_t *)stack_mem; - *ptr++ = osRtxStackMagicWord; - if (osRtxConfig.flags & osRtxConfigStackWatermark) { - for (n = (stack_size/4U) - (16U + 1U); n; n--) { - *ptr++ = osRtxStackFillPattern; + // Initialize stack + //lint --e{613} false detection: "Possible use of null pointer" + ptr = (uint32_t *)stack_mem; + ptr[0] = osRtxStackMagicWord; + if ((osRtxConfig.flags & osRtxConfigStackWatermark) != 0U) { + for (n = (stack_size/4U) - (16U + 1U); n != 0U; n--) { + ptr++; + *ptr = osRtxStackFillPattern; + } } - } else { ptr = (uint32_t *)thread->sp; - } - for (n = 13U; n; n--) { - *ptr++ = 0U; // R4..R11, R0..R3, R12 - } - *ptr++ = (uint32_t)osThreadExit; // LR - *ptr++ = (uint32_t)func; // PC - *ptr++ = xPSR_INIT( - (osRtxConfig.flags & osRtxConfigPrivilegedMode), - ((uint32_t)func & 1U) - ); // xPSR - *(ptr-8) = (uint32_t)argument; // R0 + for (n = 0U; n != 13U; n++) { + ptr[n] = 0U; // R4..R11, R0..R3, R12 + } + ptr[13] = (uint32_t)osThreadExit; // LR + ptr[14] = (uint32_t)func; // PC + ptr[15] = xPSR_InitVal( + (bool_t)((osRtxConfig.flags & osRtxConfigPrivilegedMode) != 0U), + (bool_t)(((uint32_t)func & 1U) != 0U) + ); // xPSR + ptr[8] = (uint32_t)argument; // R0 - // Register post ISR processing function - osRtxInfo.post_process.thread = osRtxThreadPostProcess; + // Register post ISR processing function + osRtxInfo.post_process.thread = osRtxThreadPostProcess; - EvrRtxThreadCreated(thread); + EvrRtxThreadCreated(thread, thread->thread_addr); + } else { + EvrRtxThreadError(NULL, (int32_t)osErrorNoMemory); + } /* Notify the OS event observer of a new thread. */ if (osEventObs && osEventObs->thread_create) { @@ -780,25 +823,29 @@ thread->context = context; } - osRtxThreadDispatch(thread); + if (thread != NULL) { + osRtxThreadDispatch(thread); + } return thread; } /// Get name of a thread. /// \note API identical to osThreadGetName -const char *svcRtxThreadGetName (osThreadId_t thread_id) { - os_thread_t *thread = (os_thread_t *)thread_id; +static const char *svcRtxThreadGetName (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread)) { EvrRtxThreadGetName(thread, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check object state if (thread->state == osRtxObjectInactive) { EvrRtxThreadGetName(thread, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -809,7 +856,7 @@ /// Return the thread ID of the current running thread. /// \note API identical to osThreadGetId -osThreadId_t svcRtxThreadGetId (void) { +static osThreadId_t svcRtxThreadGetId (void) { os_thread_t *thread; thread = osRtxThreadGetRunning(); @@ -819,34 +866,40 @@ /// Get current thread state of a thread. /// \note API identical to osThreadGetState -osThreadState_t svcRtxThreadGetState (osThreadId_t thread_id) { - os_thread_t *thread = (os_thread_t *)thread_id; +static osThreadState_t svcRtxThreadGetState (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + osThreadState_t state; // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread)) { EvrRtxThreadGetState(thread, osThreadError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osThreadError; } - EvrRtxThreadGetState(thread, (osThreadState_t)(thread->state & osRtxThreadStateMask)); + state = osRtxThreadState(thread); - return ((osThreadState_t)(thread->state & osRtxThreadStateMask)); + EvrRtxThreadGetState(thread, state); + + return state; } /// Get stack size of a thread. /// \note API identical to osThreadGetStackSize -uint32_t svcRtxThreadGetStackSize (osThreadId_t thread_id) { - os_thread_t *thread = (os_thread_t *)thread_id; +static uint32_t svcRtxThreadGetStackSize (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread)) { EvrRtxThreadGetStackSize(thread, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (thread->state == osRtxObjectInactive) { EvrRtxThreadGetStackSize(thread, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -857,37 +910,42 @@ /// Get available stack space of a thread based on stack watermark recording during execution. /// \note API identical to osThreadGetStackSpace -uint32_t svcRtxThreadGetStackSpace (osThreadId_t thread_id) { - os_thread_t *thread = (os_thread_t *)thread_id; - uint32_t *stack; - uint32_t space; +static uint32_t svcRtxThreadGetStackSpace (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + const uint32_t *stack; + uint32_t space; // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread)) { EvrRtxThreadGetStackSpace(thread, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (thread->state == osRtxObjectInactive) { EvrRtxThreadGetStackSpace(thread, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } + // Check if stack watermark is not enabled if ((osRtxConfig.flags & osRtxConfigStackWatermark) == 0U) { EvrRtxThreadGetStackSpace(thread, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } + //lint -e{9079} "conversion from pointer to void to pointer to other type" stack = thread->stack_mem; - if (*stack++ != osRtxStackMagicWord) { - EvrRtxThreadGetStackSpace(thread, 0U); - return 0U; - } - for (space = 4U; space < thread->stack_size; space += 4U) { - if (*stack++ != osRtxStackFillPattern) { - break; + if (*stack++ == osRtxStackMagicWord) { + for (space = 4U; space < thread->stack_size; space += 4U) { + if (*stack++ != osRtxStackFillPattern) { + break; + } } + } else { + space = 0U; } EvrRtxThreadGetStackSpace(thread, space); @@ -897,20 +955,22 @@ /// Change priority of a thread. /// \note API identical to osThreadSetPriority -osStatus_t svcRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { - os_thread_t *thread = (os_thread_t *)thread_id; +static osStatus_t svcRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { + os_thread_t *thread = osRtxThreadId(thread_id); // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread) || (priority < osPriorityIdle) || (priority > osPriorityISR)) { - EvrRtxThreadError(thread, osErrorParameter); + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if ((thread->state == osRtxThreadInactive) || (thread->state == osRtxThreadTerminated)) { - EvrRtxThreadError(thread, osErrorResource); + EvrRtxThreadError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -926,12 +986,14 @@ /// Get current priority of a thread. /// \note API identical to osThreadGetPriority -osPriority_t svcRtxThreadGetPriority (osThreadId_t thread_id) { - os_thread_t *thread = (os_thread_t *)thread_id; +static osPriority_t svcRtxThreadGetPriority (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + osPriority_t priority; // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread)) { EvrRtxThreadGetPriority(thread, osPriorityError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osPriorityError; } @@ -939,17 +1001,20 @@ if ((thread->state == osRtxThreadInactive) || (thread->state == osRtxThreadTerminated)) { EvrRtxThreadGetPriority(thread, osPriorityError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osPriorityError; } - EvrRtxThreadGetPriority(thread, (osPriority_t)thread->priority); + priority = osRtxThreadPriority(thread); - return ((osPriority_t)thread->priority); + EvrRtxThreadGetPriority(thread, priority); + + return priority; } /// Pass control to next thread that is in state READY. /// \note API identical to osThreadYield -osStatus_t svcRtxThreadYield (void) { +static osStatus_t svcRtxThreadYield (void) { uint8_t kernel_state; os_thread_t *thread_running; os_thread_t *thread_ready; @@ -962,6 +1027,7 @@ (thread_ready->priority == thread_running->priority)) { osRtxThreadListRemove(thread_ready); osRtxThreadReadyPut(thread_running); + EvrRtxThreadPreempted(thread_running); osRtxThreadSwitch(thread_ready); } @@ -970,12 +1036,14 @@ /// Suspend execution of a thread. /// \note API identical to osThreadSuspend -osStatus_t svcRtxThreadSuspend (osThreadId_t thread_id) { - os_thread_t *thread = (os_thread_t *)thread_id; +static osStatus_t svcRtxThreadSuspend (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + osStatus_t status; // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread)) { - EvrRtxThreadError(thread, osErrorParameter); + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } @@ -984,53 +1052,62 @@ case osRtxThreadRunning: if ((osRtxKernelGetState() != osRtxKernelRunning) || (osRtxInfo.thread.ready.thread_list == NULL)) { - EvrRtxThreadError(thread, osErrorResource); - return osErrorResource; + EvrRtxThreadError(thread, (int32_t)osErrorResource); + status = osErrorResource; + } else { + status = osOK; } break; case osRtxThreadReady: osRtxThreadListRemove(thread); + status = osOK; break; case osRtxThreadBlocked: osRtxThreadListRemove(thread); osRtxThreadDelayRemove(thread); + status = osOK; break; case osRtxThreadInactive: case osRtxThreadTerminated: default: - EvrRtxThreadError(thread, osErrorResource); - return osErrorResource; + EvrRtxThreadError(thread, (int32_t)osErrorResource); + status = osErrorResource; + break; } - EvrRtxThreadSuspended(thread); + if (status == osOK) { + EvrRtxThreadSuspended(thread); - if (thread->state == osRtxThreadRunning) { - osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready)); + if (thread->state == osRtxThreadRunning) { + osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready)); + } + + // Update Thread State and put it into Delay list + thread->state = osRtxThreadBlocked; + thread->thread_prev = NULL; + thread->thread_next = NULL; + osRtxThreadDelayInsert(thread, osWaitForever); } - // Update Thread State and put it into Delay list - thread->state = osRtxThreadBlocked; - thread->thread_prev = NULL; - thread->thread_next = NULL; - osRtxThreadDelayInsert(thread, osWaitForever); - - return osOK; + return status; } /// Resume execution of a thread. /// \note API identical to osThreadResume -osStatus_t svcRtxThreadResume (osThreadId_t thread_id) { - os_thread_t *thread = (os_thread_t *)thread_id; +static osStatus_t svcRtxThreadResume (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread)) { - EvrRtxThreadError(thread, osErrorParameter); + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if ((thread->state & osRtxThreadStateMask) != osRtxThreadBlocked) { - EvrRtxThreadError(thread, osErrorResource); + EvrRtxThreadError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -1051,52 +1128,58 @@ // Mark object as inactive thread->state = osRtxThreadInactive; -#if (__DOMAIN_NS == 1U) +#if (DOMAIN_NS == 1) // Free secure process stack if (thread->tz_memory != 0U) { - TZ_FreeModuleContext_S(thread->tz_memory); + (void)TZ_FreeModuleContext_S(thread->tz_memory); } #endif // Free stack memory - if (thread->flags & osRtxFlagSystemMemory) { - if (thread->flags & osRtxThreadFlagDefStack) { - osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem); + if ((thread->flags & osRtxFlagSystemMemory) != 0U) { + if ((thread->flags & osRtxThreadFlagDefStack) != 0U) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem); } else { - osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem); + (void)osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem); } } // Free object memory - if (thread->flags & osRtxFlagSystemObject) { + if ((thread->flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.thread != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread); } else { - osRtxMemoryFree(osRtxInfo.mem.common, thread); + (void)osRtxMemoryFree(osRtxInfo.mem.common, thread); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxThreadMemUsage.cnt_free++; +#endif } } /// Detach a thread (thread storage can be reclaimed when thread terminates). /// \note API identical to osThreadDetach -osStatus_t svcRtxThreadDetach (osThreadId_t thread_id) { - os_thread_t *thread = (os_thread_t *)thread_id; +static osStatus_t svcRtxThreadDetach (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread)) { - EvrRtxThreadError(thread, osErrorParameter); + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object attributes if ((thread->attr & osThreadJoinable) == 0U) { EvrRtxThreadError(thread, osRtxErrorThreadNotJoinable); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } // Check object state if (thread->state == osRtxThreadInactive) { - EvrRtxThreadError(thread, osErrorResource); + EvrRtxThreadError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -1114,52 +1197,67 @@ /// Wait for specified thread to terminate. /// \note API identical to osThreadJoin -osStatus_t svcRtxThreadJoin (osThreadId_t thread_id) { - os_thread_t *thread = (os_thread_t *)thread_id; +static osStatus_t svcRtxThreadJoin (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + osStatus_t status; // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread)) { - EvrRtxThreadError(thread, osErrorParameter); + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object attributes if ((thread->attr & osThreadJoinable) == 0U) { EvrRtxThreadError(thread, osRtxErrorThreadNotJoinable); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } // Check object state if ((thread->state == osRtxThreadInactive) || (thread->state == osRtxThreadRunning)) { - EvrRtxThreadError(thread, osErrorResource); + EvrRtxThreadError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } if (thread->state == osRtxThreadTerminated) { osRtxThreadListUnlink(&osRtxInfo.thread.terminate_list, thread); osRtxThreadFree(thread); + EvrRtxThreadJoined(thread); + status = osOK; } else { - EvrRtxThreadJoinPending(thread); // Suspend current Thread if (osRtxThreadWaitEnter(osRtxThreadWaitingJoin, osWaitForever)) { thread->thread_join = osRtxThreadGetRunning(); + EvrRtxThreadJoinPending(thread); + } else { + EvrRtxThreadError(thread, (int32_t)osErrorResource); } - return osErrorResource; + status = osErrorResource; } - EvrRtxThreadJoined(thread); - - return osOK; + return status; } /// Terminate execution of current running thread. /// \note API identical to osThreadExit -void svcRtxThreadExit (void) { +static void svcRtxThreadExit (void) { os_thread_t *thread; + // Check running thread thread = osRtxThreadGetRunning(); if (thread == NULL) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return; + } + + // Check if switch to next Ready Thread is possible + if ((osRtxKernelGetState() != osRtxKernelRunning) || + (osRtxInfo.thread.ready.thread_list == NULL)) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } @@ -1168,15 +1266,11 @@ // Wakeup Thread waiting to Join if (thread->thread_join != NULL) { - osRtxThreadWaitExit(thread->thread_join, (uint32_t)osOK, false); + osRtxThreadWaitExit(thread->thread_join, (uint32_t)osOK, FALSE); EvrRtxThreadJoined(thread->thread_join); } // Switch to next Ready Thread - if ((osRtxKernelGetState() != osRtxKernelRunning) || - (osRtxInfo.thread.ready.thread_list == NULL)) { - return; - } thread->sp = __get_PSP(); osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready)); osRtxThreadSetRunning(NULL); @@ -1199,98 +1293,113 @@ /// Terminate execution of a thread. /// \note API identical to osThreadTerminate -osStatus_t svcRtxThreadTerminate (osThreadId_t thread_id) { - os_thread_t *thread = (os_thread_t *)thread_id; +static osStatus_t svcRtxThreadTerminate (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + osStatus_t status; // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread)) { - EvrRtxThreadError(thread, osErrorParameter); + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state switch (thread->state & osRtxThreadStateMask) { case osRtxThreadRunning: + if ((osRtxKernelGetState() != osRtxKernelRunning) || + (osRtxInfo.thread.ready.thread_list == NULL)) { + EvrRtxThreadError(thread, (int32_t)osErrorResource); + status = osErrorResource; + } else { + status = osOK; + } break; case osRtxThreadReady: osRtxThreadListRemove(thread); + status = osOK; break; case osRtxThreadBlocked: osRtxThreadListRemove(thread); osRtxThreadDelayRemove(thread); + status = osOK; break; case osRtxThreadInactive: case osRtxThreadTerminated: default: - EvrRtxThreadError(thread, osErrorResource); - return osErrorResource; + EvrRtxThreadError(thread, (int32_t)osErrorResource); + status = osErrorResource; + break; } if (osEventObs && osEventObs->thread_destroy) { osEventObs->thread_destroy(thread->context); } - // Release owned Mutexes - osRtxMutexOwnerRelease(thread->mutex_list); + if (status == osOK) { + // Release owned Mutexes + osRtxMutexOwnerRelease(thread->mutex_list); - // Wakeup Thread waiting to Join - if (thread->thread_join != NULL) { - osRtxThreadWaitExit(thread->thread_join, (uint32_t)osOK, false); - EvrRtxThreadJoined(thread->thread_join); - } - - // Switch to next Ready Thread when terminating running Thread - if (thread->state == osRtxThreadRunning) { - if ((osRtxKernelGetState() != osRtxKernelRunning) || - (osRtxInfo.thread.ready.thread_list == NULL)) { - EvrRtxThreadError(thread, osErrorResource); - return osErrorResource; + // Wakeup Thread waiting to Join + if (thread->thread_join != NULL) { + osRtxThreadWaitExit(thread->thread_join, (uint32_t)osOK, FALSE); + EvrRtxThreadJoined(thread->thread_join); } - thread->sp = __get_PSP(); - osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready)); - osRtxThreadSetRunning(NULL); - } else { - osRtxThreadDispatch(NULL); - } - if (((thread->attr & osThreadJoinable) == 0U) || (thread->thread_join != NULL)) { - osRtxThreadFree(thread); - } else { - // Update Thread State and put it into Terminate Thread list - thread->state = osRtxThreadTerminated; - thread->thread_prev = NULL; - thread->thread_next = osRtxInfo.thread.terminate_list; - if (osRtxInfo.thread.terminate_list != NULL) { - osRtxInfo.thread.terminate_list->thread_prev = thread; + // Switch to next Ready Thread when terminating running Thread + if (thread->state == osRtxThreadRunning) { + thread->sp = __get_PSP(); + osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready)); + osRtxThreadSetRunning(NULL); + } else { + osRtxThreadDispatch(NULL); } - osRtxInfo.thread.terminate_list = thread; + + if (((thread->attr & osThreadJoinable) == 0U) || (thread->thread_join != NULL)) { + osRtxThreadFree(thread); + } else { + // Update Thread State and put it into Terminate Thread list + thread->state = osRtxThreadTerminated; + thread->thread_prev = NULL; + thread->thread_next = osRtxInfo.thread.terminate_list; + if (osRtxInfo.thread.terminate_list != NULL) { + osRtxInfo.thread.terminate_list->thread_prev = thread; + } + osRtxInfo.thread.terminate_list = thread; + } + + EvrRtxThreadDestroyed(thread); } - EvrRtxThreadDestroyed(thread); - - return osOK; + return status; } /// Get number of active threads. /// \note API identical to osThreadGetCount -uint32_t svcRtxThreadGetCount (void) { - os_thread_t *thread; - uint32_t count; +static uint32_t svcRtxThreadGetCount (void) { + const os_thread_t *thread; + uint32_t count; // Running Thread count = 1U; // Ready List for (thread = osRtxInfo.thread.ready.thread_list; - (thread != NULL); thread = thread->thread_next, count++) {}; + thread != NULL; thread = thread->thread_next) { + count++; + } // Delay List for (thread = osRtxInfo.thread.delay_list; - (thread != NULL); thread = thread->delay_next, count++) {}; + thread != NULL; thread = thread->delay_next) { + count++; + } // Wait List for (thread = osRtxInfo.thread.wait_list; - (thread != NULL); thread = thread->delay_next, count++) {}; + thread != NULL; thread = thread->delay_next) { + count++; + } EvrRtxThreadGetCount(count); @@ -1299,36 +1408,44 @@ /// Enumerate active threads. /// \note API identical to osThreadEnumerate -uint32_t svcRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) { +static uint32_t svcRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) { os_thread_t *thread; uint32_t count; // Check parameters if ((thread_array == NULL) || (array_items == 0U)) { EvrRtxThreadEnumerate(thread_array, array_items, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Running Thread - *thread_array++ = osRtxThreadGetRunning(); - count = 1U; + *thread_array = osRtxThreadGetRunning(); + thread_array++; + count = 1U; // Ready List for (thread = osRtxInfo.thread.ready.thread_list; - (thread != NULL) && (count < array_items); thread = thread->thread_next, count++) { - *thread_array++ = thread; + (thread != NULL) && (count < array_items); thread = thread->thread_next) { + *thread_array = thread; + thread_array++; + count++; } // Delay List for (thread = osRtxInfo.thread.delay_list; - (thread != NULL) && (count < array_items); thread = thread->delay_next, count++) { - *thread_array++ = thread; + (thread != NULL) && (count < array_items); thread = thread->delay_next) { + *thread_array = thread; + thread_array++; + count++; } // Wait List for (thread = osRtxInfo.thread.wait_list; - (thread != NULL) && (count < array_items); thread = thread->delay_next, count++) { - *thread_array++ = thread; + (thread != NULL) && (count < array_items); thread = thread->delay_next) { + *thread_array = thread; + thread_array++; + count++; } EvrRtxThreadEnumerate(thread_array - count, array_items, count); @@ -1338,22 +1455,24 @@ /// Set the specified Thread Flags of a thread. /// \note API identical to osThreadFlagsSet -uint32_t svcRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { - os_thread_t *thread = (os_thread_t *)thread_id; +static uint32_t svcRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { + os_thread_t *thread = osRtxThreadId(thread_id); uint32_t thread_flags; uint32_t thread_flags0; // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread) || - (flags & ~((1U << osRtxThreadFlagsLimit) - 1U))) { - EvrRtxThreadError(thread, osErrorParameter); + ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U)) { + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorParameter); } // Check object state if ((thread->state == osRtxThreadInactive) || (thread->state == osRtxThreadTerminated)) { - EvrRtxThreadError(thread, osErrorResource); + EvrRtxThreadError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorResource); } @@ -1369,7 +1488,7 @@ } else { thread_flags = thread_flags0; } - osRtxThreadWaitExit(thread, thread_flags0, true); + osRtxThreadWaitExit(thread, thread_flags0, TRUE); EvrRtxThreadFlagsWaitCompleted(thread->wait_flags, thread->flags_options, thread_flags0); } } @@ -1381,26 +1500,30 @@ /// Clear the specified Thread Flags of current running thread. /// \note API identical to osThreadFlagsClear -uint32_t svcRtxThreadFlagsClear (uint32_t flags) { +static uint32_t svcRtxThreadFlagsClear (uint32_t flags) { os_thread_t *thread; uint32_t thread_flags; + // Check running thread thread = osRtxThreadGetRunning(); if (thread == NULL) { EvrRtxThreadError(NULL, osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osError); } // Check parameters - if (flags & ~((1U << osRtxThreadFlagsLimit) - 1U)) { - EvrRtxThreadError(thread, osErrorParameter); + if ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U) { + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorParameter); } // Check object state if ((thread->state == osRtxThreadInactive) || (thread->state == osRtxThreadTerminated)) { - EvrRtxThreadError(thread, osErrorResource); + EvrRtxThreadError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorResource); } @@ -1414,12 +1537,14 @@ /// Get the current Thread Flags of current running thread. /// \note API identical to osThreadFlagsGet -uint32_t svcRtxThreadFlagsGet (void) { - os_thread_t *thread; +static uint32_t svcRtxThreadFlagsGet (void) { + const os_thread_t *thread; + // Check running thread thread = osRtxThreadGetRunning(); if (thread == NULL) { EvrRtxThreadFlagsGet(0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -1427,6 +1552,7 @@ if ((thread->state == osRtxThreadInactive) || (thread->state == osRtxThreadTerminated)) { EvrRtxThreadFlagsGet(0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } @@ -1437,19 +1563,22 @@ /// Wait for one or more Thread Flags of the current running thread to become signaled. /// \note API identical to osThreadFlagsWait -uint32_t svcRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { +static uint32_t svcRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { os_thread_t *thread; uint32_t thread_flags; + // Check running thread thread = osRtxThreadGetRunning(); if (thread == NULL) { EvrRtxThreadError(NULL, osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osError); } // Check parameters - if (flags & ~((1U << osRtxThreadFlagsLimit) - 1U)) { - EvrRtxThreadError(thread, osErrorParameter); + if ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U) { + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorParameter); } @@ -1457,25 +1586,51 @@ thread_flags = ThreadFlagsCheck(thread, flags, options); if (thread_flags != 0U) { EvrRtxThreadFlagsWaitCompleted(flags, options, thread_flags); - return thread_flags; + } else { + // Check if timeout is specified + if (timeout != 0U) { + // Store waiting flags and options + EvrRtxThreadFlagsWaitPending(flags, options, timeout); + thread->wait_flags = flags; + thread->flags_options = (uint8_t)options; + // Suspend current Thread + if (!osRtxThreadWaitEnter(osRtxThreadWaitingThreadFlags, timeout)) { + EvrRtxThreadFlagsWaitTimeout(); + } + thread_flags = (uint32_t)osErrorTimeout; + } else { + EvrRtxThreadFlagsWaitNotCompleted(flags, options); + thread_flags = (uint32_t)osErrorResource; + } } - - // Check if timeout is specified - if (timeout != 0U) { - // Store waiting flags and options - EvrRtxThreadFlagsWaitPending(flags, options, timeout); - thread->wait_flags = flags; - thread->flags_options = (uint8_t)options; - // Suspend current Thread - osRtxThreadWaitEnter(osRtxThreadWaitingThreadFlags, timeout); - return ((uint32_t)osErrorTimeout); - } - - EvrRtxThreadFlagsWaitNotCompleted(flags, options); - - return ((uint32_t)osErrorResource); + return thread_flags; } +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_4 (ThreadNew, osThreadId_t, osThreadFunc_t, void *, const osThreadAttr_t *, void *) +SVC0_1 (ThreadGetName, const char *, osThreadId_t) +SVC0_0 (ThreadGetId, osThreadId_t) +SVC0_1 (ThreadGetState, osThreadState_t, osThreadId_t) +SVC0_1 (ThreadGetStackSize, uint32_t, osThreadId_t) +SVC0_1 (ThreadGetStackSpace, uint32_t, osThreadId_t) +SVC0_2 (ThreadSetPriority, osStatus_t, osThreadId_t, osPriority_t) +SVC0_1 (ThreadGetPriority, osPriority_t, osThreadId_t) +SVC0_0 (ThreadYield, osStatus_t) +SVC0_1 (ThreadSuspend, osStatus_t, osThreadId_t) +SVC0_1 (ThreadResume, osStatus_t, osThreadId_t) +SVC0_1 (ThreadDetach, osStatus_t, osThreadId_t) +SVC0_1 (ThreadJoin, osStatus_t, osThreadId_t) +SVC0_0N(ThreadExit, void) +SVC0_1 (ThreadTerminate, osStatus_t, osThreadId_t) +SVC0_0 (ThreadGetCount, uint32_t) +SVC0_2 (ThreadEnumerate, uint32_t, osThreadId_t *, uint32_t) +SVC0_2 (ThreadFlagsSet, uint32_t, osThreadId_t, uint32_t) +SVC0_1 (ThreadFlagsClear, uint32_t, uint32_t) +SVC0_0 (ThreadFlagsGet, uint32_t) +SVC0_3 (ThreadFlagsWait, uint32_t, uint32_t, uint32_t, uint32_t) +//lint --flb "Library End" + // ==== ISR Calls ==== @@ -1483,20 +1638,22 @@ /// \note API identical to osThreadFlagsSet __STATIC_INLINE uint32_t isrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { - os_thread_t *thread = (os_thread_t *)thread_id; + os_thread_t *thread = osRtxThreadId(thread_id); uint32_t thread_flags; // Check parameters if ((thread == NULL) || (thread->id != osRtxIdThread) || - (flags & ~((1U << osRtxThreadFlagsLimit) - 1U))) { - EvrRtxThreadError(thread, osErrorParameter); + ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U)) { + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorParameter); } // Check object state if ((thread->state == osRtxThreadInactive) || (thread->state == osRtxThreadTerminated)) { - EvrRtxThreadError(thread, osErrorResource); + EvrRtxThreadError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorResource); } @@ -1504,7 +1661,7 @@ thread_flags = ThreadFlagsSet(thread, flags); // Register post ISR processing - osRtxPostProcess((os_object_t *)thread); + osRtxPostProcess(osRtxObject(thread)); EvrRtxThreadFlagsSetDone(thread, thread_flags); @@ -1512,6 +1669,39 @@ } +// ==== Library functions ==== + +/// Thread startup (Idle and Timer Thread). +/// \return true - success, false - failure. +bool_t osRtxThreadStartup (void) { + bool_t ret = TRUE; + + // Create Idle Thread + if (osRtxInfo.thread.idle == NULL) { + osRtxInfo.thread.idle = osRtxThreadId( + svcRtxThreadNew(osRtxIdleThread, NULL, osRtxConfig.idle_thread_attr, NULL) + ); + if (osRtxInfo.thread.idle == NULL) { + ret = FALSE; + } + } + + // Create Timer Thread + if (osRtxConfig.timer_mq_mcnt != 0U) { + if (osRtxInfo.timer.thread == NULL) { + osRtxInfo.timer.thread = osRtxThreadId( + svcRtxThreadNew(osRtxTimerThread, NULL, osRtxConfig.timer_thread_attr, NULL) + ); + if (osRtxInfo.timer.thread == NULL) { + ret = FALSE; + } + } + } + + return ret; +} + + // ==== Public API ==== /// Create a thread and add it to Active Threads. @@ -1520,199 +1710,277 @@ } osThreadId_t osThreadContextNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr, void *context) { + osThreadId_t thread_id; EvrRtxThreadNew(func, argument, attr); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(NULL, osErrorISR); - return NULL; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(NULL, (int32_t)osErrorISR); + thread_id = NULL; + } else { + thread_id = __svcThreadNew(func, argument, attr, context); } - return __svcThreadNew(func, argument, attr, context); + return thread_id; } /// Get name of a thread. const char *osThreadGetName (osThreadId_t thread_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxThreadGetName(thread_id, NULL); - return NULL; + name = NULL; + } else { + name = __svcThreadGetName(thread_id); } - return __svcThreadGetName(thread_id); + return name; } /// Return the thread ID of the current running thread. osThreadId_t osThreadGetId (void) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + osThreadId_t thread_id; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxThreadGetId(NULL); - return NULL; + thread_id = NULL; + } else { + thread_id = __svcThreadGetId(); } - return __svcThreadGetId(); + return thread_id; } /// Get current thread state of a thread. osThreadState_t osThreadGetState (osThreadId_t thread_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + osThreadState_t state; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxThreadGetState(thread_id, osThreadError); - return osThreadError; + state = osThreadError; + } else { + state = __svcThreadGetState(thread_id); } - return __svcThreadGetState(thread_id); + return state; } /// Get stack size of a thread. uint32_t osThreadGetStackSize (osThreadId_t thread_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + uint32_t stack_size; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxThreadGetStackSize(thread_id, 0U); - return 0U; + stack_size = 0U; + } else { + stack_size = __svcThreadGetStackSize(thread_id); } - return __svcThreadGetStackSize(thread_id); + return stack_size; } /// Get available stack space of a thread based on stack watermark recording during execution. uint32_t osThreadGetStackSpace (osThreadId_t thread_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + uint32_t stack_space; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxThreadGetStackSpace(thread_id, 0U); - return 0U; + stack_space = 0U; + } else { + stack_space = __svcThreadGetStackSpace(thread_id); } - return __svcThreadGetStackSpace(thread_id); + return stack_space; } /// Change priority of a thread. osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { + osStatus_t status; + EvrRtxThreadSetPriority(thread_id, priority); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(thread_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadSetPriority(thread_id, priority); } - return __svcThreadSetPriority(thread_id, priority); + return status; } /// Get current priority of a thread. osPriority_t osThreadGetPriority (osThreadId_t thread_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + osPriority_t priority; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxThreadGetPriority(thread_id, osPriorityError); - return osPriorityError; + priority = osPriorityError; + } else { + priority = __svcThreadGetPriority(thread_id); } - return __svcThreadGetPriority(thread_id); + return priority; } /// Pass control to next thread that is in state READY. osStatus_t osThreadYield (void) { + osStatus_t status; + EvrRtxThreadYield(); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(NULL, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(NULL, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadYield(); } - return __svcThreadYield(); + return status; } /// Suspend execution of a thread. osStatus_t osThreadSuspend (osThreadId_t thread_id) { + osStatus_t status; + EvrRtxThreadSuspend(thread_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(thread_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadSuspend(thread_id); } - return __svcThreadSuspend(thread_id); + return status; } /// Resume execution of a thread. osStatus_t osThreadResume (osThreadId_t thread_id) { + osStatus_t status; + EvrRtxThreadResume(thread_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(thread_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadResume(thread_id); } - return __svcThreadResume(thread_id); + return status; } /// Detach a thread (thread storage can be reclaimed when thread terminates). osStatus_t osThreadDetach (osThreadId_t thread_id) { + osStatus_t status; + EvrRtxThreadDetach(thread_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(thread_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadDetach(thread_id); } - return __svcThreadDetach(thread_id); + return status; } /// Wait for specified thread to terminate. osStatus_t osThreadJoin (osThreadId_t thread_id) { + osStatus_t status; + EvrRtxThreadJoin(thread_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(thread_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadJoin(thread_id); } - return __svcThreadJoin(thread_id); + return status; } /// Terminate execution of current running thread. __NO_RETURN void osThreadExit (void) { EvrRtxThreadExit(); __svcThreadExit(); - EvrRtxThreadError(NULL, osError); - for (;;); + EvrRtxThreadError(NULL, (int32_t)osError); + for (;;) {} } /// Terminate execution of a thread. osStatus_t osThreadTerminate (osThreadId_t thread_id) { + osStatus_t status; + EvrRtxThreadTerminate(thread_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(thread_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadTerminate(thread_id); } - return __svcThreadTerminate(thread_id); + return status; } /// Get number of active threads. uint32_t osThreadGetCount (void) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxThreadGetCount(0U); - return 0U; + count = 0U; + } else { + count = __svcThreadGetCount(); } - return __svcThreadGetCount(); + return count; } /// Enumerate active threads. uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxThreadEnumerate(thread_array, array_items, 0U); - return 0U; + count = 0U; + } else { + count = __svcThreadEnumerate(thread_array, array_items); } - return __svcThreadEnumerate(thread_array, array_items); + return count; } /// Set the specified Thread Flags of a thread. uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { + uint32_t thread_flags; + EvrRtxThreadFlagsSet(thread_id, flags); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - return isrRtxThreadFlagsSet(thread_id, flags); + if (IsIrqMode() || IsIrqMasked()) { + thread_flags = isrRtxThreadFlagsSet(thread_id, flags); } else { - return __svcThreadFlagsSet(thread_id, flags); + thread_flags = __svcThreadFlagsSet(thread_id, flags); } + return thread_flags; } /// Clear the specified Thread Flags of current running thread. uint32_t osThreadFlagsClear (uint32_t flags) { + uint32_t thread_flags; + EvrRtxThreadFlagsClear(flags); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(NULL, osErrorISR); - return ((uint32_t)osErrorISR); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(NULL, (int32_t)osErrorISR); + thread_flags = (uint32_t)osErrorISR; + } else { + thread_flags = __svcThreadFlagsClear(flags); } - return __svcThreadFlagsClear(flags); + return thread_flags; } /// Get the current Thread Flags of current running thread. uint32_t osThreadFlagsGet (void) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + uint32_t thread_flags; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxThreadFlagsGet(0U); - return 0U; + thread_flags = 0U; + } else { + thread_flags = __svcThreadFlagsGet(); } - return __svcThreadFlagsGet(); + return thread_flags; } /// Wait for one or more Thread Flags of the current running thread to become signaled. uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { + uint32_t thread_flags; + EvrRtxThreadFlagsWait(flags, options, timeout); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxThreadError(NULL, osErrorISR); - return ((uint32_t)osErrorISR); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(NULL, (int32_t)osErrorISR); + thread_flags = (uint32_t)osErrorISR; + } else { + thread_flags = __svcThreadFlagsWait(flags, options, timeout); } - return __svcThreadFlagsWait(flags, options, timeout); + return thread_flags; } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_timer.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_timer.c index 90bd795..450123f 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_timer.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,6 +26,14 @@ #include "rtx_lib.h" +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxTimerMemUsage \ +__attribute__((section(".data.os.timer.obj"))) = +{ 0U, 0U, 0U }; +#endif + + // ==== Helper functions ==== /// Insert Timer into the Timer List sorted by Time. @@ -57,7 +65,7 @@ /// Remove Timer from the Timer List. /// \param[in] timer timer object. -static void TimerRemove (os_timer_t *timer) { +static void TimerRemove (const os_timer_t *timer) { if (timer->next != NULL) { timer->next->tick += timer->tick; @@ -72,7 +80,7 @@ /// Unlink Timer from the Timer List Head. /// \param[in] timer timer object. -static void TimerUnlink (os_timer_t *timer) { +static void TimerUnlink (const os_timer_t *timer) { if (timer->next != NULL) { timer->next->prev = timer->prev; @@ -84,12 +92,13 @@ // ==== Library functions ==== /// Timer Tick (called each SysTick). -void osRtxTimerTick (void) { +static void osRtxTimerTick (void) { os_timer_t *timer; osStatus_t status; timer = osRtxInfo.timer.list; if (timer == NULL) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } @@ -98,7 +107,7 @@ TimerUnlink(timer); status = osMessageQueuePut(osRtxInfo.timer.mq, &timer->finfo, 0U, 0U); if (status != osOK) { - osRtxErrorNotify(osRtxErrorTimerQueueOverflow, timer); + (void)osRtxErrorNotify(osRtxErrorTimerQueueOverflow, timer); } if (timer->type == osRtxTimerPeriodic) { TimerInsert(timer, timer->load); @@ -115,55 +124,56 @@ osStatus_t status; (void) argument; - osRtxInfo.timer.mq = osMessageQueueNew(osRtxConfig.timer_mq_mcnt, sizeof(os_timer_finfo_t), osRtxConfig.timer_mq_attr); + osRtxInfo.timer.mq = osRtxMessageQueueId( + osMessageQueueNew(osRtxConfig.timer_mq_mcnt, sizeof(os_timer_finfo_t), osRtxConfig.timer_mq_attr) + ); if (osRtxInfo.timer.mq == NULL) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return; } osRtxInfo.timer.tick = osRtxTimerTick; for (;;) { + //lint -e{934} "Taking address of near auto variable" status = osMessageQueueGet(osRtxInfo.timer.mq, &finfo, NULL, osWaitForever); if (status == osOK) { - EvrRtxTimerCallback(*(osTimerFunc_t)finfo.fp, finfo.arg); - (*(osTimerFunc_t)finfo.fp)(finfo.arg); + EvrRtxTimerCallback(finfo.func, finfo.arg); + (finfo.func)(finfo.arg); } } } // ==== Service Calls ==== -// Service Calls definitions -SVC0_4M(TimerNew, osTimerId_t, osTimerFunc_t, osTimerType_t, void *, const osTimerAttr_t *) -SVC0_1 (TimerGetName, const char *, osTimerId_t) -SVC0_2 (TimerStart, osStatus_t, osTimerId_t, uint32_t) -SVC0_1 (TimerStop, osStatus_t, osTimerId_t) -SVC0_1 (TimerIsRunning, uint32_t, osTimerId_t) -SVC0_1 (TimerDelete, osStatus_t, osTimerId_t) - /// Create and Initialize a timer. /// \note API identical to osTimerNew -osTimerId_t svcRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { +static osTimerId_t svcRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { os_timer_t *timer; uint8_t flags; const char *name; // Check parameters if ((func == NULL) || ((type != osTimerOnce) && (type != osTimerPeriodic))) { - EvrRtxTimerError(NULL, osErrorParameter); + EvrRtxTimerError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Process attributes if (attr != NULL) { name = attr->name; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] timer = attr->cb_mem; if (timer != NULL) { - if (((uint32_t)timer & 3U) || (attr->cb_size < sizeof(os_timer_t))) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)timer & 3U) != 0U) || (attr->cb_size < sizeof(os_timer_t))) { EvrRtxTimerError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } else { if (attr->cb_size != 0U) { EvrRtxTimerError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } } @@ -175,51 +185,65 @@ // Allocate object memory if not provided if (timer == NULL) { if (osRtxInfo.mpi.timer != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] timer = osRtxMemoryPoolAlloc(osRtxInfo.mpi.timer); } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] timer = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_timer_t), 1U); } - if (timer == NULL) { - EvrRtxTimerError(NULL, osErrorNoMemory); - return NULL; +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (timer != NULL) { + uint32_t used; + osRtxTimerMemUsage.cnt_alloc++; + used = osRtxTimerMemUsage.cnt_alloc - osRtxTimerMemUsage.cnt_free; + if (osRtxTimerMemUsage.max_used < used) { + osRtxTimerMemUsage.max_used = used; + } } +#endif flags = osRtxFlagSystemObject; } else { flags = 0U; } - // Initialize control block - timer->id = osRtxIdTimer; - timer->state = osRtxTimerStopped; - timer->flags = flags; - timer->type = (uint8_t)type; - timer->name = name; - timer->prev = NULL; - timer->next = NULL; - timer->tick = 0U; - timer->load = 0U; - timer->finfo.fp = (void *)func; - timer->finfo.arg = argument; + if (timer != NULL) { + // Initialize control block + timer->id = osRtxIdTimer; + timer->state = osRtxTimerStopped; + timer->flags = flags; + timer->type = (uint8_t)type; + timer->name = name; + timer->prev = NULL; + timer->next = NULL; + timer->tick = 0U; + timer->load = 0U; + timer->finfo.func = func; + timer->finfo.arg = argument; - EvrRtxTimerCreated(timer); + EvrRtxTimerCreated(timer, timer->name); + } else { + EvrRtxTimerError(NULL, (int32_t)osErrorNoMemory); + } return timer; } /// Get name of a timer. /// \note API identical to osTimerGetName -const char *svcRtxTimerGetName (osTimerId_t timer_id) { - os_timer_t *timer = (os_timer_t *)timer_id; +static const char *svcRtxTimerGetName (osTimerId_t timer_id) { + os_timer_t *timer = osRtxTimerId(timer_id); // Check parameters if ((timer == NULL) || (timer->id != osRtxIdTimer)) { EvrRtxTimerGetName(timer, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } // Check object state if (timer->state == osRtxObjectInactive) { EvrRtxTimerGetName(timer, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return NULL; } @@ -230,32 +254,33 @@ /// Start or restart a timer. /// \note API identical to osTimerStart -osStatus_t svcRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) { - os_timer_t *timer = (os_timer_t *)timer_id; +static osStatus_t svcRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) { + os_timer_t *timer = osRtxTimerId(timer_id); // Check parameters if ((timer == NULL) || (timer->id != osRtxIdTimer) || (ticks == 0U)) { - EvrRtxTimerError(timer, osErrorParameter); + EvrRtxTimerError(timer, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state - switch (timer->state) { - case osRtxTimerStopped: - if (osRtxInfo.timer.tick == NULL) { - EvrRtxTimerError(timer, osErrorResource); - return osErrorResource; - } + if (timer->state == osRtxTimerInactive) { + EvrRtxTimerError(timer, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } + if (timer->state == osRtxTimerRunning) { + TimerRemove(timer); + } else { + if (osRtxInfo.timer.tick == NULL) { + EvrRtxTimerError(timer, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } else { timer->state = osRtxTimerRunning; timer->load = ticks; - break; - case osRtxTimerRunning: - TimerRemove(timer); - break; - case osRtxTimerInactive: - default: - EvrRtxTimerError(timer, osErrorResource); - return osErrorResource; + } } TimerInsert(timer, ticks); @@ -267,18 +292,20 @@ /// Stop a timer. /// \note API identical to osTimerStop -osStatus_t svcRtxTimerStop (osTimerId_t timer_id) { - os_timer_t *timer = (os_timer_t *)timer_id; +static osStatus_t svcRtxTimerStop (osTimerId_t timer_id) { + os_timer_t *timer = osRtxTimerId(timer_id); // Check parameters if ((timer == NULL) || (timer->id != osRtxIdTimer)) { - EvrRtxTimerError(timer, osErrorParameter); + EvrRtxTimerError(timer, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state if (timer->state != osRtxTimerRunning) { - EvrRtxTimerError(timer, osErrorResource); + EvrRtxTimerError(timer, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -293,59 +320,64 @@ /// Check if a timer is running. /// \note API identical to osTimerIsRunning -uint32_t svcRtxTimerIsRunning (osTimerId_t timer_id) { - os_timer_t *timer = (os_timer_t *)timer_id; +static uint32_t svcRtxTimerIsRunning (osTimerId_t timer_id) { + os_timer_t *timer = osRtxTimerId(timer_id); + uint32_t is_running; // Check parameters if ((timer == NULL) || (timer->id != osRtxIdTimer)) { EvrRtxTimerIsRunning(timer, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return 0U; } // Check object state if (timer->state == osRtxTimerRunning) { EvrRtxTimerIsRunning(timer, 1U); - return 1U; + is_running = 1U; + } else { + EvrRtxTimerIsRunning(timer, 0U); + is_running = 0; } - EvrRtxTimerIsRunning(timer, 0U); - return 0U; + return is_running; } /// Delete a timer. /// \note API identical to osTimerDelete -osStatus_t svcRtxTimerDelete (osTimerId_t timer_id) { - os_timer_t *timer = (os_timer_t *)timer_id; +static osStatus_t svcRtxTimerDelete (osTimerId_t timer_id) { + os_timer_t *timer = osRtxTimerId(timer_id); // Check parameters if ((timer == NULL) || (timer->id != osRtxIdTimer)) { - EvrRtxTimerError(timer, osErrorParameter); + EvrRtxTimerError(timer, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } // Check object state - switch (timer->state) { - case osRtxTimerStopped: - break; - case osRtxTimerRunning: - TimerRemove(timer); - break; - case osRtxTimerInactive: - default: - EvrRtxTimerError(timer, osErrorResource); - return osErrorResource; + if (timer->state == osRtxTimerInactive) { + EvrRtxTimerError(timer, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } + if (timer->state == osRtxTimerRunning) { + TimerRemove(timer); } // Mark object as inactive timer->state = osRtxTimerInactive; // Free object memory - if (timer->flags & osRtxFlagSystemObject) { + if ((timer->flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.timer != NULL) { - osRtxMemoryPoolFree(osRtxInfo.mpi.timer, timer); + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.timer, timer); } else { - osRtxMemoryFree(osRtxInfo.mem.common, timer); + (void)osRtxMemoryFree(osRtxInfo.mem.common, timer); } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxTimerMemUsage.cnt_free++; +#endif } EvrRtxTimerDestroyed(timer); @@ -353,63 +385,97 @@ return osOK; } +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_4(TimerNew, osTimerId_t, osTimerFunc_t, osTimerType_t, void *, const osTimerAttr_t *) +SVC0_1(TimerGetName, const char *, osTimerId_t) +SVC0_2(TimerStart, osStatus_t, osTimerId_t, uint32_t) +SVC0_1(TimerStop, osStatus_t, osTimerId_t) +SVC0_1(TimerIsRunning, uint32_t, osTimerId_t) +SVC0_1(TimerDelete, osStatus_t, osTimerId_t) +//lint --flb "Library End" + // ==== Public API ==== /// Create and Initialize a timer. osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { + osTimerId_t timer_id; + EvrRtxTimerNew(func, type, argument, attr); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxTimerError(NULL, osErrorISR); - return NULL; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxTimerError(NULL, (int32_t)osErrorISR); + timer_id = NULL; + } else { + timer_id = __svcTimerNew(func, type, argument, attr); } - return __svcTimerNew(func, type, argument, attr); + return timer_id; } /// Get name of a timer. const char *osTimerGetName (osTimerId_t timer_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxTimerGetName(timer_id, NULL); - return NULL; + name = NULL; + } else { + name = __svcTimerGetName(timer_id); } - return __svcTimerGetName(timer_id); + return name; } /// Start or restart a timer. osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { + osStatus_t status; + EvrRtxTimerStart(timer_id, ticks); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxTimerError(timer_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxTimerError(timer_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcTimerStart(timer_id, ticks); } - return __svcTimerStart(timer_id, ticks); + return status; } /// Stop a timer. osStatus_t osTimerStop (osTimerId_t timer_id) { + osStatus_t status; + EvrRtxTimerStop(timer_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxTimerError(timer_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxTimerError(timer_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcTimerStop(timer_id); } - return __svcTimerStop(timer_id); + return status; } /// Check if a timer is running. uint32_t osTimerIsRunning (osTimerId_t timer_id) { - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { + uint32_t is_running; + + if (IsIrqMode() || IsIrqMasked()) { EvrRtxTimerIsRunning(timer_id, 0U); - return 0U; + is_running = 0U; + } else { + is_running = __svcTimerIsRunning(timer_id); } - return __svcTimerIsRunning(timer_id); + return is_running; } /// Delete a timer. osStatus_t osTimerDelete (osTimerId_t timer_id) { + osStatus_t status; + EvrRtxTimerDelete(timer_id); - if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { - EvrRtxTimerError(timer_id, osErrorISR); - return osErrorISR; + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxTimerError(timer_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcTimerDelete(timer_id); } - return __svcTimerDelete(timer_id); + return status; } diff --git a/rtos/TARGET_CORTEX/rtx5/Source/os_systick.c b/rtos/TARGET_CORTEX/rtx5/Source/os_systick.c index 16bf53c..985a9d9 100644 --- a/rtos/TARGET_CORTEX/rtx5/Source/os_systick.c +++ b/rtos/TARGET_CORTEX/rtx5/Source/os_systick.c @@ -1,8 +1,8 @@ /**************************************************************************//** * @file os_systick.c * @brief CMSIS OS Tick SysTick implementation - * @version V1.0.0 - * @date 05. June 2017 + * @version V1.0.1 + * @date 24. November 2017 ******************************************************************************/ /* * Copyright (c) 2017-2017 ARM Limited. All rights reserved. @@ -24,7 +24,9 @@ #include "os_tick.h" -#include +//lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer" +#include "RTE_Components.h" +#include CMSIS_device_header #ifdef SysTick @@ -35,30 +37,32 @@ static uint8_t PendST; // Setup OS Tick. -__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { +__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { uint32_t load; (void)handler; if (freq == 0U) { + //lint -e{904} "Return statement before end of function" return (-1); } load = (SystemCoreClock / freq) - 1U; if (load > 0x00FFFFFFU) { + //lint -e{904} "Return statement before end of function" return (-1); } // Set SysTick Interrupt Priority -#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1U)) || \ +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ (defined(__CORTEX_M) && (__CORTEX_M == 7U))) - SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY; -#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1U)) - SCB->SHPR[1] |= (SYSTICK_IRQ_PRIORITY << 24); -#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1U)) || \ - (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1U))) - SCB->SHP[11] = SYSTICK_IRQ_PRIORITY; -#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ == 1U)) - SCB->SHP[1] |= (SYSTICK_IRQ_PRIORITY << 24); + SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0))) + SCB->SHP[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) + SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); #else #error "Unknown ARM Core!" #endif @@ -73,7 +77,7 @@ } /// Enable OS Tick. -__WEAK int32_t OS_Tick_Enable (void) { +__WEAK void OS_Tick_Enable (void) { if (PendST != 0U) { PendST = 0U; @@ -81,12 +85,10 @@ } SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - - return (0); } /// Disable OS Tick. -__WEAK int32_t OS_Tick_Disable (void) { +__WEAK void OS_Tick_Disable (void) { SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; @@ -94,19 +96,16 @@ SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; PendST = 1U; } - - return (0); } // Acknowledge OS Tick IRQ. -__WEAK int32_t OS_Tick_AcknowledgeIRQ (void) { +__WEAK void OS_Tick_AcknowledgeIRQ (void) { (void)SysTick->CTRL; - return (0); } // Get OS Tick IRQ number. __WEAK int32_t OS_Tick_GetIRQn (void) { - return (SysTick_IRQn); + return ((int32_t)SysTick_IRQn); } // Get OS Tick clock. diff --git a/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c b/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c index b909e7e..ae216eb 100644 --- a/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c +++ b/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c @@ -1,8 +1,8 @@ /**************************************************************************//** * @file os_tick_ptim.c * @brief CMSIS OS Tick implementation for Private Timer - * @version V1.0.0 - * @date 29. June 2017 + * @version V1.0.1 + * @date 24. November 2017 ******************************************************************************/ /* * Copyright (c) 2017 ARM Limited. All rights reserved. @@ -22,13 +22,14 @@ * limitations under the License. */ +#include "RTE_Components.h" +#include CMSIS_device_header + #if defined(PTIM) #include "os_tick.h" #include "irq_ctrl.h" -#include - #ifndef PTIM_IRQ_PRIORITY #define PTIM_IRQ_PRIORITY 0xFFU #endif @@ -36,7 +37,7 @@ static uint8_t PTIM_PendIRQ; // Timer interrupt pending flag // Setup OS Tick. -int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { uint32_t load; uint32_t prio; uint32_t bits; @@ -74,7 +75,7 @@ } prio >>= 1; } - + // Adjust configured priority to the number of implemented priority bits prio = (PTIM_IRQ_PRIORITY << bits) & 0xFFUL; @@ -97,7 +98,7 @@ } /// Enable OS Tick. -int32_t OS_Tick_Enable (void) { +void OS_Tick_Enable (void) { uint32_t ctrl; // Set pending interrupt if flag set @@ -111,14 +112,12 @@ // Set bit: Timer enable ctrl |= 1U; PTIM_SetControl (ctrl); - - return (0); } /// Disable OS Tick. -int32_t OS_Tick_Disable (void) { +void OS_Tick_Disable (void) { uint32_t ctrl; - + // Stop the Private Timer ctrl = PTIM_GetControl(); // Clear bit: Timer enable @@ -130,14 +129,11 @@ IRQ_ClearPending (PrivTimer_IRQn); PTIM_PendIRQ = 1U; } - - return (0); } // Acknowledge OS Tick IRQ. -int32_t OS_Tick_AcknowledgeIRQ (void) { +void OS_Tick_AcknowledgeIRQ (void) { PTIM_ClearEventFlag(); - return (0); } // Get OS Tick IRQ number. diff --git a/targets/TARGET_ARM_SSG/TARGET_BEETLE/cordio/include/wsf/generic/wsf_types.h b/targets/TARGET_ARM_SSG/TARGET_BEETLE/cordio/include/wsf/generic/wsf_types.h index 9ba363f..7d5ce3f 100644 --- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/cordio/include/wsf/generic/wsf_types.h +++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/cordio/include/wsf/generic/wsf_types.h @@ -22,30 +22,7 @@ #ifndef WSF_TYPES_H #define WSF_TYPES_H -/************************************************************************************************** - Macros -**************************************************************************************************/ - -#ifndef NULL -#define NULL 0 -#endif - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -/************************************************************************************************** - Data Types -**************************************************************************************************/ - -/* Integer data types */ #include - -/* Boolean data type */ -typedef uint8_t bool_t; +#include #endif /* WSF_TYPES_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c index e28da96..89420e5 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c @@ -131,7 +131,7 @@ } /// Enable OS Tick. -int32_t OS_Tick_Enable (void) +void OS_Tick_Enable (void) { if (OSTM_PendIRQ != 0U) { @@ -141,12 +141,10 @@ // Start the OSTM counter OSTM.OSTMnTS = 0x01U; - - return (0); } /// Disable OS Tick. -int32_t OS_Tick_Disable (void) { +void OS_Tick_Disable (void) { // Stop the OSTM counter OSTM.OSTMnTT = 0x01U; @@ -155,14 +153,12 @@ IRQ_ClearPending (OSTM_IRQn); OSTM_PendIRQ = 1U; } - - return (0); } // Acknowledge OS Tick IRQ. -int32_t OS_Tick_AcknowledgeIRQ (void) +void OS_Tick_AcknowledgeIRQ (void) { - return (IRQ_ClearPending (OSTM_IRQn)); + IRQ_ClearPending (OSTM_IRQn); } // Get OS Tick IRQ number. diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c index f198340..30b830d 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c @@ -131,7 +131,7 @@ } /// Enable OS Tick. -int32_t OS_Tick_Enable (void) +void OS_Tick_Enable (void) { if (OSTM_PendIRQ != 0U) { @@ -141,12 +141,10 @@ // Start the OSTM counter OSTM.OSTMnTS = 0x01U; - - return (0); } /// Disable OS Tick. -int32_t OS_Tick_Disable (void) +void OS_Tick_Disable (void) { // Stop the OSTM counter @@ -156,14 +154,12 @@ IRQ_ClearPending (OSTM_IRQn); OSTM_PendIRQ = 1U; } - - return (0); } // Acknowledge OS Tick IRQ. -int32_t OS_Tick_AcknowledgeIRQ (void) +void OS_Tick_AcknowledgeIRQ (void) { - return (IRQ_ClearPending (OSTM_IRQn)); + IRQ_ClearPending (OSTM_IRQn); } // Get OS Tick IRQ number. diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c index e5b2591..830b407 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c @@ -131,7 +131,7 @@ } /// Enable OS Tick. -int32_t OS_Tick_Enable (void) +void OS_Tick_Enable (void) { if (OSTM_PendIRQ != 0U) { @@ -141,12 +141,10 @@ // Start the OSTM counter OSTM.OSTMnTS = 0x01U; - - return (0); } /// Disable OS Tick. -int32_t OS_Tick_Disable (void) +void OS_Tick_Disable (void) { // Stop the OSTM counter @@ -156,14 +154,12 @@ IRQ_ClearPending (OSTM_IRQn); OSTM_PendIRQ = 1U; } - - return (0); } // Acknowledge OS Tick IRQ. -int32_t OS_Tick_AcknowledgeIRQ (void) +void OS_Tick_AcknowledgeIRQ (void) { - return (IRQ_ClearPending (OSTM_IRQn)); + IRQ_ClearPending (OSTM_IRQn); } // Get OS Tick IRQ number. diff --git a/targets/TARGET_RENESAS/mbed_rtx.h b/targets/TARGET_RENESAS/mbed_rtx.h index f7c91c6..c8eba52 100644 --- a/targets/TARGET_RENESAS/mbed_rtx.h +++ b/targets/TARGET_RENESAS/mbed_rtx.h @@ -19,7 +19,6 @@ #include #if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H) || defined(TARGET_GR_LYCHEE) -#define OS_IDLE_THREAD_STACK_SIZE 512 #if defined(__CC_ARM) extern char Image$$ARM_LIB_STACK$$Base[]; diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index dc5c8d8..d323e3b 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -17,6 +17,8 @@ #ifndef MBED_MBED_RTX_H #define MBED_MBED_RTX_H +#include + #ifndef INITIAL_SP #if (defined(TARGET_STM32L475VG) ||\ diff --git a/tools/importer/cmsis_importer.json b/tools/importer/cmsis_importer.json index ff7f94a..d1a3b9f 100644 --- a/tools/importer/cmsis_importer.json +++ b/tools/importer/cmsis_importer.json @@ -111,6 +111,10 @@ "dest_folder" : "rtos/TARGET_CORTEX/rtx5/Include/" }, { + "src_folder" : "CMSIS/RTOS2/Source/", + "dest_folder" : "rtos/TARGET_CORTEX/rtx5/Source/" + }, + { "src_folder" : "CMSIS/RTOS2/RTX/Include1/", "dest_folder" : "rtos/TARGET_CORTEX/rtx4/" }, @@ -136,21 +140,19 @@ } ], "commit_sha" : [ - "428acae1b2ac15c3ad523e8d40755a9301220822", - "d9d622afe0ca8c7ab9d24c17f9fe59b54dcc61c9", - "a1fcd36be8ee00aba2c9c1b079f5728368922bc8", - "f3db103d481d8729950414868cfc8123b8055601", - "c07cc6b0f42ff4fe215aa1641a043e205d9128a5", - "dd8fdf4c768e5fef3a7ce2e014de4339dbafe5ce", - "2a837ea97900cc30f82e5a23b95b3f293d17eae1", - "c03b3f9eedab7cb0732d1519c4f1a8d90b08eede", - "314a9eb559752132a89b0dbd986db960b3ab9055", - "e83fd0099a69e6eb865e4e6fcadbfb1328c04c85", - "a019acaf8d6fb1f0512414d072f667cc2749b1d9", - "a884fdc0639ae4e17299838ec9de4fddd83cf93c", - "6c827cb5879bc096e45efd992dfadcb96c1d50bc", - "919282322e106b82fea50878f41b6c75a7eb356b", - "d0a43b8af0eef4775ec4c3da5994ecceb9ed4558" + "466b74e518eb9a4f2389dee1fc58ec1617be35d7", + "a06759d76e286994e457ba5aa6a8f6bb028828ce", + "0f0f21fdfeb25f0b350bbaba560270537f873e7a", + "3f7a235c6cc118b0bf634f330185718ef95477d9", + "0774ee3c8515ba447230433f44aab94a2cea02d2", + "5611950394fda1308087520ef3381c95244df201", + "b108cc8a8ad3d5e9c51b4ef95139aacf690d4223", + "adb6e821cc448f005e63ba9c7e2ce335abd54082", + "acd8ab1ff0588410f0fc5463fa12094250a371fb", + "1a511c456143bd31606f6a47807f506da1b51b90", + "474d2e3c9944d2866a0643795aafdfee743488eb", + "7b3a3a441ab6451462bd476721d6e8cb6ddd6c9d", + "d30da821a19fb6776e15eea33c5b45052a264dfd" ] } diff --git a/tools/profiles/debug.json b/tools/profiles/debug.json index b5229e2..e45d0e1 100644 --- a/tools/profiles/debug.json +++ b/tools/profiles/debug.json @@ -6,7 +6,7 @@ "-ffunction-sections", "-fdata-sections", "-funsigned-char", "-MMD", "-fno-delete-null-pointer-checks", "-fomit-frame-pointer", "-O0", "-g3", "-DMBED_DEBUG", - "-DMBED_TRAP_ERRORS_ENABLED=1"], + "-DMBED_TRAP_ERRORS_ENABLED=1", "-D_RTE_"], "asm": ["-x", "assembler-with-cpp"], "c": ["-std=gnu99"], "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"], @@ -19,7 +19,7 @@ "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-g", "-O0", "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions", "-DMULADDC_CANNOT_USE_R7", "-fdata-sections", - "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)="], + "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)=", "-D_RTE_"], "asm": [], "c": ["-D__ASSERT_MSG", "-std=gnu99"], "cxx": ["-fno-rtti", "-std=gnu++98"], @@ -30,7 +30,7 @@ "common": ["-c", "--gnu", "-Otime", "--split_sections", "--apcs=interwork", "--brief_diagnostics", "--restrict", "--multibyte_chars", "-O0", "-g", "-DMBED_DEBUG", - "-DMBED_TRAP_ERRORS_ENABLED=1"], + "-DMBED_TRAP_ERRORS_ENABLED=1", "-D_RTE_"], "asm": [], "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"], "cxx": ["--cpp", "--no_rtti", "--no_vla"], @@ -41,7 +41,7 @@ "--apcs=interwork", "--brief_diagnostics", "--restrict", "--multibyte_chars", "-O0", "-D__MICROLIB", "-g", "--library_type=microlib", "-DMBED_RTOS_SINGLE_THREAD", "-DMBED_DEBUG", - "-DMBED_TRAP_ERRORS_ENABLED=1"], + "-DMBED_TRAP_ERRORS_ENABLED=1", "-D_RTE_"], "asm": [], "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"], "cxx": ["--cpp", "--no_rtti", "--no_vla"], @@ -51,7 +51,7 @@ "common": [ "--no_wrap_diagnostics", "-e", "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-On", "-r", "-DMBED_DEBUG", - "-DMBED_TRAP_ERRORS_ENABLED=1", "--enable_restrict"], + "-DMBED_TRAP_ERRORS_ENABLED=1", "--enable_restrict", "-D_RTE_"], "asm": [], "c": ["--vla"], "cxx": ["--guard_calls", "--no_static_destruction"], diff --git a/tools/profiles/develop.json b/tools/profiles/develop.json index 7858826..cdaa328 100644 --- a/tools/profiles/develop.json +++ b/tools/profiles/develop.json @@ -5,7 +5,7 @@ "-fmessage-length=0", "-fno-exceptions", "-fno-builtin", "-ffunction-sections", "-fdata-sections", "-funsigned-char", "-MMD", "-fno-delete-null-pointer-checks", - "-fomit-frame-pointer", "-Os", "-g1"], + "-fomit-frame-pointer", "-Os", "-g1", "-D_RTE_"], "asm": ["-x", "assembler-with-cpp"], "c": ["-std=gnu99"], "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"], @@ -18,7 +18,7 @@ "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Os", "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions", "-DMULADDC_CANNOT_USE_R7", "-fdata-sections", - "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)="], + "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)=", "-D_RTE_"], "asm": [], "c": ["-D__ASSERT_MSG", "-std=gnu99"], "cxx": ["-fno-rtti", "-std=gnu++98"], @@ -27,7 +27,7 @@ "ARM": { "common": ["-c", "--gnu", "-Otime", "--split_sections", "--apcs=interwork", "--brief_diagnostics", "--restrict", - "--multibyte_chars", "-O3"], + "--multibyte_chars", "-O3", "-D_RTE_"], "asm": [], "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"], "cxx": ["--cpp", "--no_rtti", "--no_vla"], @@ -37,7 +37,7 @@ "common": ["-c", "--gnu", "-Otime", "--split_sections", "--apcs=interwork", "--brief_diagnostics", "--restrict", "--multibyte_chars", "-O3", "-D__MICROLIB", - "--library_type=microlib", "-DMBED_RTOS_SINGLE_THREAD"], + "--library_type=microlib", "-DMBED_RTOS_SINGLE_THREAD", "-D_RTE_"], "asm": [], "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"], "cxx": ["--cpp", "--no_rtti", "--no_vla"], @@ -46,7 +46,7 @@ "IAR": { "common": [ "--no_wrap_diagnostics", "-e", - "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh", "--enable_restrict"], + "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh", "--enable_restrict", "-D_RTE_"], "asm": [], "c": ["--vla"], "cxx": ["--guard_calls", "--no_static_destruction"], diff --git a/tools/profiles/release.json b/tools/profiles/release.json index 42bc2cf..ac3f3dc 100644 --- a/tools/profiles/release.json +++ b/tools/profiles/release.json @@ -5,7 +5,7 @@ "-fmessage-length=0", "-fno-exceptions", "-fno-builtin", "-ffunction-sections", "-fdata-sections", "-funsigned-char", "-MMD", "-fno-delete-null-pointer-checks", - "-fomit-frame-pointer", "-Os", "-DNDEBUG", "-g1"], + "-fomit-frame-pointer", "-Os", "-DNDEBUG", "-g1", "-D_RTE_"], "asm": ["-x", "assembler-with-cpp"], "c": ["-std=gnu99"], "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"], @@ -18,7 +18,7 @@ "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Oz", "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions", "-DMULADDC_CANNOT_USE_R7", "-fdata-sections", - "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)="], + "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)=", "-D_RTE_"], "asm": [], "c": ["-D__ASSERT_MSG", "-std=gnu99"], "cxx": ["-fno-rtti", "-std=gnu++98"], @@ -27,7 +27,7 @@ "ARM": { "common": ["-c", "--gnu", "-Ospace", "--split_sections", "--apcs=interwork", "--brief_diagnostics", "--restrict", - "--multibyte_chars", "-O3", "-DNDEBUG"], + "--multibyte_chars", "-O3", "-DNDEBUG", "-D_RTE_"], "asm": [], "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"], "cxx": ["--cpp", "--no_rtti", "--no_vla"], @@ -37,7 +37,7 @@ "common": ["-c", "--gnu", "-Ospace", "--split_sections", "--apcs=interwork", "--brief_diagnostics", "--restrict", "--multibyte_chars", "-O3", "-D__MICROLIB", - "--library_type=microlib", "-DMBED_RTOS_SINGLE_THREAD", "-DNDEBUG"], + "--library_type=microlib", "-DMBED_RTOS_SINGLE_THREAD", "-DNDEBUG", "-D_RTE_"], "asm": [], "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"], "cxx": ["--cpp", "--no_rtti", "--no_vla"], @@ -46,7 +46,7 @@ "IAR": { "common": [ "--no_wrap_diagnostics", "-e", - "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Ohz", "-DNDEBUG", "--enable_restrict"], + "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Ohz", "-DNDEBUG", "--enable_restrict", "-D_RTE_"], "asm": [], "c": ["--vla"], "cxx": ["--guard_calls", "--no_static_destruction"], diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py index c95b1c0..ef4b397 100644 --- a/tools/toolchains/__init__.py +++ b/tools/toolchains/__init__.py @@ -377,11 +377,11 @@ "Cortex-M7F" : ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-M7FD" : ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-A9" : ["__CORTEX_A9", "ARM_MATH_CA9", "__FPU_PRESENT", "__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA9"], - "Cortex-M23-NS": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "__DOMAIN_NS=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], + "Cortex-M23-NS": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "DOMAIN_NS=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-M23": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], - "Cortex-M33-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__DOMAIN_NS=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], + "Cortex-M33-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-M33": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], - "Cortex-M33F-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__DOMAIN_NS=1", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], + "Cortex-M33F-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=1", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-M33F": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], }